system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
__global__ void empty()
{
return;
}
int main()
{
dim3 gridSize = dim3(1, 1, 1);
dim3 blockSize = dim3(1, 1, 1);
empty<<<gridSize, blockSize>>>();
printf("Hello World\n");
return 0;
} | code for sm_80
Function : _Z5emptyv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
__global__ void empty()
{
return;
}
int main()
{
dim3 gridSize = dim3(1, 1, 1);
dim3 blockSize = dim3(1, 1, 1);
empty<<<gridSize, blockSize>>>();
printf("Hello World\n");
return 0;
} | .file "tmpxft_0003c9e4_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5emptyvv
.type _Z23__device_stub__Z5emptyvv, @function
_Z23__device_stub__Z5emptyvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5emptyv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5emptyvv, .-_Z23__device_stub__Z5emptyvv
.globl _Z5emptyv
.type _Z5emptyv, @function
_Z5emptyv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5emptyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5emptyv, .-_Z5emptyv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5emptyvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5emptyv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5emptyv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime_api.h>
__global__ void empty()
{
return;
}
int main()
{
dim3 gridSize = dim3(1, 1, 1);
dim3 blockSize = dim3(1, 1, 1);
empty<<<gridSize, blockSize>>>();
printf("Hello World\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
__global__ void empty()
{
return;
}
int main()
{
dim3 gridSize = dim3(1, 1, 1);
dim3 blockSize = dim3(1, 1, 1);
empty<<<gridSize, blockSize>>>();
printf("Hello World\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
__global__ void empty()
{
return;
}
int main()
{
dim3 gridSize = dim3(1, 1, 1);
dim3 blockSize = dim3(1, 1, 1);
empty<<<gridSize, blockSize>>>();
printf("Hello World\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5emptyv
.globl _Z5emptyv
.p2align 8
.type _Z5emptyv,@function
_Z5emptyv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5emptyv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5emptyv, .Lfunc_end0-_Z5emptyv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5emptyv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z5emptyv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
__global__ void empty()
{
return;
}
int main()
{
dim3 gridSize = dim3(1, 1, 1);
dim3 blockSize = dim3(1, 1, 1);
empty<<<gridSize, blockSize>>>();
printf("Hello World\n");
return 0;
} | .text
.file "main.hip"
.globl _Z20__device_stub__emptyv # -- Begin function _Z20__device_stub__emptyv
.p2align 4, 0x90
.type _Z20__device_stub__emptyv,@function
_Z20__device_stub__emptyv: # @_Z20__device_stub__emptyv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5emptyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__emptyv, .Lfunc_end0-_Z20__device_stub__emptyv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5emptyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5emptyv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5emptyv,@object # @_Z5emptyv
.section .rodata,"a",@progbits
.globl _Z5emptyv
.p2align 3, 0x0
_Z5emptyv:
.quad _Z20__device_stub__emptyv
.size _Z5emptyv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5emptyv"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__emptyv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5emptyv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5emptyv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5emptyv
.globl _Z5emptyv
.p2align 8
.type _Z5emptyv,@function
_Z5emptyv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5emptyv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5emptyv, .Lfunc_end0-_Z5emptyv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5emptyv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z5emptyv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003c9e4_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5emptyvv
.type _Z23__device_stub__Z5emptyvv, @function
_Z23__device_stub__Z5emptyvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5emptyv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5emptyvv, .-_Z23__device_stub__Z5emptyvv
.globl _Z5emptyv
.type _Z5emptyv, @function
_Z5emptyv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5emptyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5emptyv, .-_Z5emptyv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5emptyvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z5emptyv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5emptyv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z20__device_stub__emptyv # -- Begin function _Z20__device_stub__emptyv
.p2align 4, 0x90
.type _Z20__device_stub__emptyv,@function
_Z20__device_stub__emptyv: # @_Z20__device_stub__emptyv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5emptyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__emptyv, .Lfunc_end0-_Z20__device_stub__emptyv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5emptyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5emptyv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5emptyv,@object # @_Z5emptyv
.section .rodata,"a",@progbits
.globl _Z5emptyv
.p2align 3, 0x0
_Z5emptyv:
.quad _Z20__device_stub__emptyv
.size _Z5emptyv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5emptyv"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__emptyv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5emptyv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <errno.h>
#include <fcntl.h>
#include <signal.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
#include <cuda_runtime.h>
#include <curand.h>
#include <curand_kernel.h>
// Controls the number of threads per block to use.
#define DEFAULT_BLOCK_SIZE (512)
// Controls the default number of blocks to use.
#define DEFAULT_BLOCK_COUNT (512)
// The name given to the output file if one isn't specified.
#define DEFAULT_OUTPUT_NAME "output.pgm"
// This macro takes a cudaError_t value and exits the program if it isn't equal
// to cudaSuccess.
#define CheckCUDAError(val) (InternalCUDAErrorCheck((val), #val, __FILE__, __LINE__))
// Increasing this may increase efficiency, but decrease responsiveness to
// signals.
#define SAMPLES_PER_THREAD (50)
// The RNG seed used when initializing the RNG states on the GPU.
#define DEFAULT_RNG_SEED (1337)
// The type that we use to keep track of internal pixel counts. Must be a
// numerical type that will work with both IncrementPixelCounter,
// GetLinearColorScale, and DoGammaCorrection. Floating-point values *ought* to
// work here, too.
typedef uint32_t Pixel;
// Holds the boundaries and sizes of the fractal, in both pixels and numbers
typedef struct {
// The width and height of the image in pixels.
int w;
int h;
// The boundaries of the fractal.
double min_real;
double min_imag;
double max_real;
double max_imag;
// The distance between pixels in the real and imaginary axes.
double delta_real;
double delta_imag;
} FractalDimensions;
// This struct holds the parameters for different types of "iterations" needed
// when calculating the Buddhabrot.
typedef struct {
// This is the maximum number of iterations to run to see if a point escapes.
int max_escape_iterations;
// If a point escapes in fewer than this many iterations, it will be ignored.
int min_escape_iterations;
} IterationControl;
// Holds global state in a single struct.
static struct {
// The CUDA device to use. Defaults to 0.
int cuda_device;
// This tracks the random number generator states for the GPU code.
curandState_t *rng_states;
// The number of threads and blocks to use when calculating the Buddhabrot.
int block_size, block_count;
// The filename to which a bitmap image will be saved, or NULL if an image
// should not be saved.
const char *output_image;
// The filename from which to load an in-progress image buffer, or to which
// the in-progress buffer should be stored if operation is interrupted.
const char *inprogress_file;
// The number of seconds to run the calculation. If negative, run
// indefinitely until a signal is received.
double seconds_to_run;
// If this is nonzero, the program should save the image and quit as soon as
// the current iteration finishes.
int quit_signal_received;
// Holds various iteration-related settings.
IterationControl iterations;
// The size and location of the fractal and output image.
FractalDimensions dimensions;
// The host and device buffers which contain the numbers of times an escaping
// point's path crossed each point in the complex plane.
Pixel *device_buddhabrot;
Pixel *host_buddhabrot;
// The gamma value for gamma correction.
double gamma_correction;
// Buffer for a single grayscale image.
uint16_t *grayscale_image;
} g;
// Returns the size, in bytes, of the internal image buffer used to hold the
// pixel data.
static uint64_t GetImageBufferSize(void) {
return ((uint64_t) g.dimensions.w) * ((uint64_t) g.dimensions.h) *
sizeof(Pixel);
}
// If any globals have been initialized, this will free them. (Relies on
// globals being set to 0 at the start of the program)
static void CleanupGlobals(void) {
cudaFree(g.rng_states);
cudaFree(g.device_buddhabrot);
cudaFree(g.rng_states);
free(g.grayscale_image);
free(g.host_buddhabrot);
memset(&g, 0, sizeof(g));
}
// Returns the current time in seconds.
static double CurrentSeconds(void) {
struct timespec ts;
if (clock_gettime(CLOCK_REALTIME, &ts) != 0) {
printf("Error getting time.\n");
exit(1);
}
return ((double) ts.tv_sec) + (((double) ts.tv_nsec) / 1e9);
}
// Prints an error message and exits the program if the cudaError_t value is
// not equal to cudaSuccess. Generally, this will be called via the
// CheckCUDAError macro.
static void InternalCUDAErrorCheck(cudaError_t result, const char *fn,
const char *file, int line) {
if (result == cudaSuccess) return;
printf("CUDA error %d (%s) in %s, line %d (%s)\n", (int) result,
cudaGetErrorString(result), file, line, fn);
CleanupGlobals();
exit(1);
}
// This function is used to initialize the RNG states to use when generating
// starting points in the Buddhabrot calculation. The states array must hold
// one entry for every thread in every block.
__global__ void InitializeRNG(uint64_t seed, curandState_t *states) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
curand_init(seed, index, 0, states + index);
}
// Allocates CUDA memory and calculates block/grid sizes. Must be called after
// g.w and g.h have been set.
static void SetupCUDA(void) {
float gpu_memory_needed, cpu_memory_needed;
CheckCUDAError(cudaSetDevice(g.cuda_device));
size_t pixel_count = g.dimensions.w * g.dimensions.h;
// The GPU will need space for the image and the RNG states.
gpu_memory_needed = GetImageBufferSize() +
(g.block_size * g.block_count * sizeof(curandState_t));
gpu_memory_needed /= (1024.0 * 1024.0);
// The CPU needs space for the image and grayscale conversion.
cpu_memory_needed = GetImageBufferSize() + (pixel_count * sizeof(uint16_t));
cpu_memory_needed /= (1024.0 * 1024.0);
printf("Approximate memory needed: %.03f MiB GPU, %.03f MiB CPU\n",
gpu_memory_needed, cpu_memory_needed);
// Initialize the host and device image buffers.
CheckCUDAError(cudaMalloc(&(g.device_buddhabrot), GetImageBufferSize()));
CheckCUDAError(cudaMemset(g.device_buddhabrot, 0, GetImageBufferSize()));
g.host_buddhabrot = (Pixel *) calloc(1, GetImageBufferSize());
if (!g.host_buddhabrot) {
CleanupGlobals();
exit(1);
}
// Initialize the RNG state for the device.
CheckCUDAError(cudaMalloc(&(g.rng_states), g.block_size * g.block_count *
sizeof(curandState_t)));
InitializeRNG<<<g.block_size, g.block_count>>>(DEFAULT_RNG_SEED,
g.rng_states);
CheckCUDAError(cudaDeviceSynchronize());
g.grayscale_image = (uint16_t *) calloc(pixel_count, sizeof(uint16_t));
if (!g.grayscale_image) {
printf("Failed allocating grayscale image.\n");
CleanupGlobals();
exit(1);
}
}
// Returns the size, in bytes, of f. Exits on error.
static uint64_t GetFileSize(FILE *f) {
int64_t to_return;
if (fseek(f, 0, SEEK_END) != 0) {
printf("Failed seeking file end: %s\n", strerror(errno));
CleanupGlobals();
exit(1);
}
to_return = ftell(f);
if (to_return < 0) {
printf("Failed reading file size: %s\n", strerror(errno));
CleanupGlobals();
exit(1);
}
if (fseek(f, 0, SEEK_SET) != 0) {
printf("Failed seeking file start: %s\n", strerror(errno));
CleanupGlobals();
exit(1);
}
return to_return;
}
// Loads the in-progress buffer from a file, if the file exists. Exits if an
// error occurs. Creates the file if it doesn't exist.
static void LoadInProgressBuffer(void) {
uint64_t expected_size, file_size;
FILE *f = NULL;
if (!g.inprogress_file) return;
// We won't consider it an error if the file doesn't exist, and won't try to
// load its contents.
f = fopen(g.inprogress_file, "rb");
expected_size = GetImageBufferSize();
printf("Loading previous image state from %s.\n",
g.inprogress_file);
if (!f) {
if (errno == ENOENT) {
printf("File %s doesn't exist yet. Not loading.\n",
g.inprogress_file);
return;
}
printf("Failed opening %s: %s\n", g.inprogress_file, strerror(errno));
CleanupGlobals();
exit(1);
}
file_size = GetFileSize(f);
// Ensure the file matches the expected size of our image buffer.
if (file_size != expected_size) {
printf("The size of %s doesn't match the expected size of %lu bytes.\n",
g.inprogress_file, (unsigned long) expected_size);
fclose(f);
CleanupGlobals();
exit(1);
}
// Read the file to the local buffer, then update the device copy.
if (fread(g.host_buddhabrot, expected_size, 1, f) != 1) {
printf("Failed reading %s: %s\n", g.inprogress_file, strerror(errno));
fclose(f);
CleanupGlobals();
exit(1);
}
fclose(f);
f = NULL;
CheckCUDAError(cudaMemcpy(g.device_buddhabrot, g.host_buddhabrot,
expected_size, cudaMemcpyHostToDevice));
}
// Saves the in-progress buffer to a file, if the filename was specified.
// Exits if an error occurs.
static void SaveInProgressBuffer(void) {
FILE *f = NULL;
if (!g.inprogress_file) return;
printf("Saving in-progress buffer to %s.\n", g.inprogress_file);
f = fopen(g.inprogress_file, "wb");
if (!f) {
printf("Failed opening %s: %s\n", g.inprogress_file, strerror(errno));
CleanupGlobals();
exit(1);
}
if (fwrite(g.host_buddhabrot, GetImageBufferSize(), 1, f) != 1) {
printf("Failed writing data to %s: %s\n", g.inprogress_file,
strerror(errno));
fclose(f);
CleanupGlobals();
exit(1);
}
fclose(f);
}
// This returns nonzero if the given point is in the main cardioid of the set
// and is therefore guaranteed to not escape.
inline __device__ int InMainCardioid(double real, double imag) {
// This algorithm was taken from the Wikipedia Mandelbrot set page.
double imag_squared = imag * imag;
double q = (real - 0.25);
q = q * q + imag_squared;
return q * (q + (real - 0.25)) < (imag_squared * 0.25);
}
// This returns nonzero if the given point is in the order 2 bulb of the set
// and therefore guaranteed to not escape.
inline __device__ int InOrder2Bulb(double real, double imag) {
double tmp = real + 1;
tmp = tmp * tmp;
return (tmp + (imag * imag)) < (1.0 / 16.0);
}
// This should be used to update the pixel data for a point that is encountered
// in the set.
inline __device__ void IncrementPixelCounter(double real, double imag,
Pixel *data, FractalDimensions *d) {
int row, col;
// There's a small issue here with integer-dividing where values that should
// be immediately outside of the canvas can still appear on row or col 0, so
// just return early if we're outside the boundary.
if ((real < d->min_real) || (imag < d->min_imag)) return;
col = (real - d->min_real) / d->delta_real;
row = (imag - d->min_imag) / d->delta_imag;
if ((row >= 0) && (row < d->h) && (col >= 0) && (col < d->w)) {
data[(row * d->w) + col] += 1;
}
}
// Does the Mandelbrot-set iterations for the given (real, imag) point. Returns
// the number of iterations before the point escapes, or max_iterations if the
// point never escapes.
inline __device__ int IterateMandelbrot(double start_real, double start_imag,
int max_iterations) {
double tmp, real, imag;
int i;
real = start_real;
imag = start_imag;
// This loop-unrolling was tested on a Radeon VII, anything higher or lower
// than 4 produced worse performance. May differ on other devices, or future
// compiler updates.
//#pragma unroll 4
for (i = 0; i < max_iterations; i++) {
real = fabs(real);
imag = fabs(imag);
tmp = (real * real) - (imag * imag) + start_real;
imag = 2 * real * imag + start_imag;
real = tmp;
// If the point escapes, stop iterating and indicate the loop ended due
// to the point escaping.
if (((real * real) + (imag * imag)) > 4) return i;
}
// The point didn't escape, return max_iterations.
return max_iterations;
}
// Like IterateMandelbrot, but records the point's path. For efficiency, this
// function also has an important difference from IterateMandelbrot: *it does
// not check the max iterations*. This is important! Do not call this function
// for a point unless you're sure that it escapes in a finite number of
// iterations.
inline __device__ void IterateAndRecord(double start_real, double start_imag,
Pixel *data, FractalDimensions *d) {
double tmp, real, imag;
real = start_real;
imag = start_imag;
//#pragma unroll 4
while (1) {
real = fabs(real);
imag = fabs(imag);
tmp = (real * real) - (imag * imag) + start_real;
imag = 2 * real * imag + start_imag;
real = tmp;
IncrementPixelCounter(real, imag, data, d);
// Stop iterating when the point escapes. This must be *guaranteed* to
// happen by the caller performing a prior check!
if (((real * real) + (imag * imag)) > 4) break;
}
}
// This kernel is responsible for drawing the paths of "particles" that escape
// the mandelbrot set. It works as follows:
//
// 1. For each "sample", compute a new random starting point in the complex
// plane
// 2. Do the normal mandelbrot iterations on the starting point, *without*
// recording its path
// 3. If the point didn't escape the path, take a new sample (return to step 1)
// 4. If the point escaped (within the min and max iteration limits), then
// repeat the mandelbrot iterations (e.g. step 2), except record its path
// by incrementing the pixel value for every point it passes through.
__global__ void DrawBuddhabrot(FractalDimensions dimensions, Pixel *data,
IterationControl iterations, curandState_t *states) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
curandState_t *rng = states + index;
int sample, iterations_needed, max_iterations, min_iterations;
double real, imag;
max_iterations = iterations.max_escape_iterations;
min_iterations = iterations.min_escape_iterations;
// We're going to pick a number of random starting points determined by the
// SAMPLES_PER_THREAD value.
for (sample = 0; sample < SAMPLES_PER_THREAD; sample++) {
// Sample across the entire domain of the set regardless of our "canvas"
real = (curand_uniform_double(rng) * 4.0) - 2.0;
imag = (curand_uniform_double(rng) * 4.0) - 2.0;
// Optimization: we know ahead of time that points from the main cardioid
// and the largest "bulb" will never escape, and it's fast to check them.
//if (InMainCardioid(real, imag) || InOrder2Bulb(real, imag)) continue;
// Now, do the normal Mandelbrot iterations to see how quickly the point
// escapes (if it does). However, we won't record the path yet.
iterations_needed = IterateMandelbrot(real, imag, max_iterations);
// Don't record the path if the point never escaped, or if it escaped too
// quickly.
if (iterations_needed >= max_iterations) continue;
if (iterations_needed < min_iterations) continue;
// At this point, do the Mandelbrot iterations, but actually record the
// path because we know the point is "good".
IterateAndRecord(real, imag, data, &dimensions);
}
}
static uint16_t Clamp(double v) {
if (v <= 0) return 0;
if (v >= 0xffff) return 0xffff;
return (uint16_t) v;
}
// Returns the amount to multiply the original count by in order to get a value
// by which Buddhabrot counts can be multiplied to get a number between 0 and
// 0xffff.
static double GetLinearColorScale(void) {
int x, y, index;
Pixel max = 0;
double to_return;
index = 0;
for (y = 0; y < g.dimensions.h; y++) {
for (x = 0; x < g.dimensions.w; x++) {
if (g.host_buddhabrot[index] > max) max = g.host_buddhabrot[index];
index++;
}
}
to_return = ((double) 0xffff) / ((double) max);
printf("Max value: %lu, scale: %f\n", (unsigned long) max, to_return);
return to_return;
}
// Returns the gamma-corrected 16-bit color channel value given a Buddhabrot
// iteration count c.
static uint16_t DoGammaCorrection(Pixel c, double linear_scale) {
double max = 0xffff;
double scaled = ((double) c) * linear_scale;
// Don't do gamma correction if the gamma correction argument was negative.
if (g.gamma_correction <= 0.0) return scaled;
return Clamp(max * pow(scaled / max, 1 / g.gamma_correction));
}
// Converts the buffer of pixel values to a gamma-corrected grayscale image
// with 16-bit colors. The Pixel values are scaled to fill the 16-bit color
// range.
static void SetGrayscalePixels(void) {
int x, y;
uint16_t color_value;
double linear_scale = GetLinearColorScale();
Pixel *host_data = g.host_buddhabrot;
uint16_t *grayscale = g.grayscale_image;
for (y = 0; y < g.dimensions.h; y++) {
for (x = 0; x < g.dimensions.w; x++) {
color_value = DoGammaCorrection(*host_data, linear_scale);
*grayscale = color_value;
grayscale++;
host_data++;
}
}
}
// Renders the fractal image.
static void RenderImage(void) {
int passes_count = 0;
double start_seconds;
printf("Calculating Buddhabrot.\n");
if (g.seconds_to_run < 0) {
printf("Press ctrl+C to finish.\n");
} else {
printf("Running for %.03f seconds.\n", g.seconds_to_run);
}
// Run until either the time elapsed or we've received a SIGINT.
start_seconds = CurrentSeconds();
while (!g.quit_signal_received) {
passes_count++;
DrawBuddhabrot<<<g.block_count, g.block_size>>>(g.dimensions,
g.device_buddhabrot, g.iterations, g.rng_states);
CheckCUDAError(cudaDeviceSynchronize());
if ((g.seconds_to_run >= 0) && ((CurrentSeconds() - start_seconds) >
g.seconds_to_run)) {
break;
}
}
// Copy the resulting image to CPU memory, and convert the pixels to proper
// grayscale values.
CheckCUDAError(cudaMemcpy(g.host_buddhabrot, g.device_buddhabrot,
GetImageBufferSize(), cudaMemcpyDeviceToHost));
printf("%d Buddhabrot passes took %f seconds.\n", passes_count,
CurrentSeconds() - start_seconds);
SetGrayscalePixels();
}
// Recomputes the spacing between pixels in the image. Returns 0 if any image-
// dimension setting is invalid. Otherwise, returns 1.
static int RecomputePixelDeltas(void) {
FractalDimensions *dims = &(g.dimensions);
if (dims->w <= 0) {
printf("Output width must be positive.\n");
return 0;
}
if (dims->h <= 0) {
printf("Output height must be positive.\n");
return 0;
}
if (dims->max_real <= dims->min_real) {
printf("Maximum real value must be greater than minimum real value.\n");
return 0;
}
if (dims->max_imag <= dims->min_imag) {
printf("Minimum imaginary value must be greater than maximum imaginary "
"value.\n");
return 0;
}
dims->delta_imag = (dims->max_imag - dims->min_imag) / ((double) dims->h);
dims->delta_real = (dims->max_real - dims->min_real) / ((double) dims->w);
return 1;
}
// Sets the image boundaries and dimensions to their default values.
static void SetDefaultCanvas(void) {
FractalDimensions *dims = &(g.dimensions);
memset(dims, 0, sizeof(*dims));
dims->w = 1000;
dims->h = 1000;
dims->min_real = -2.0;
dims->max_real = 2.0;
dims->min_imag = -2.0;
dims->max_imag = 2.0;
if (!RecomputePixelDeltas()) {
printf("Internal error setting default canvas boundaries!\n");
exit(1);
}
}
// If a filename has been set for saving the image, this will attempt to save
// the image to the file. This can modify the image buffer! (For changing byte
// order.)
static void SaveImage(void) {
uint16_t tmp;
int i;
int pixel_count = g.dimensions.w * g.dimensions.h;
FILE *output = fopen(g.output_image, "wb");
if (!output) {
printf("Failed opening output image.\n");
return;
}
if (fprintf(output, "P5\n%d %d\n%d\n", g.dimensions.w, g.dimensions.h,
0xffff) <= 0) {
printf("Failed writing pgm header.\n");
fclose(output);
return;
}
// Flip the byte-order for the image. This assumes the program is running on
// a little-endian architecture. I'll fix it if there's ever a demand to run
// this on something other than Linux on x86 or ARM64 (lol).
for (i = 0; i < pixel_count; i++) {
tmp = g.grayscale_image[i];
tmp = ((tmp & 0xff) << 8) | (tmp >> 8);
g.grayscale_image[i] = tmp;
}
if (!fwrite(g.grayscale_image, pixel_count * sizeof(uint16_t), 1, output)) {
printf("Failed writing pixel data.\n");
fclose(output);
return;
}
fclose(output);
}
static void PrintUsage(char *program_name) {
printf("Usage: %s [options]\n\n", program_name);
printf("Options may be one or more of the following:\n"
" --help: Prints these instructions.\n"
" -d <device number>: Sets which GPU to use. Defaults to GPU 0.\n"
" -o <output file name>: If provided, the rendered image will be saved\n"
" to a .pgm file with the given name. Otherwise, saves the image\n"
" to " DEFAULT_OUTPUT_NAME ".\n"
" -m <max escape iterations>: The maximum number of iterations to use\n"
" before giving up on seeing whether a point escapes.\n"
" -c <min escape iterations>: If a point escapes before this number of\n"
" iterations, it will be ignored.\n"
" -g <gamma correction>: A gamma-correction value to use on the\n"
" resulting image. If negative, no gamma correction will occur.\n"
" -t <seconds to run>: A number of seconds to run the calculation for.\n"
" Defaults to 10.0. If negative, the program will run continuously\n"
" and will terminate (saving the image) when it receives a SIGINT.\n"
" -w <width>: The width of the output image, in pixels. Defaults to\n"
" 1000.\n"
" -h <height>: The height of the output image, in pixels. Defaults to\n"
" 1000.\n"
" -s <save/load file>: If provided, this gives a file name into which\n"
" the rendering buffer will be saved, for future continuation.\n"
" If the program is loaded and the file exists, the buffer will be\n"
" filled with the contents of the file, but the dimensions must\n"
" match. Note that this file may be huge for high-resolution images.\n"
"\n"
"The following settings control the location of the output image on the\n"
"complex plane, but samples are always drawn from the entire Mandelbrot-\n"
"set domain (-2-2i to 2+2i). So these settings can be used to save\n"
"memory or \"crop\" the output, but won't otherwise speed up rendering:\n"
" --min-real <min real>: The minimum value along the real axis to\n"
" include in the output image. Defaults to -2.0.\n"
" --max-real <max real>: The maximum value along the real axis to\n"
" include in the output image. Defaults to 2.0.\n"
" --min-imag <min imag>: The minimum value along the imaginary axis to\n"
" include in the output image. Defaults to -2.0.\n"
" --max-imag <max imag>: The maximum value along the imaginary axis to\n"
" include in the output image. Defaults to 2.0.\n"
"");
exit(0);
}
// Returns an integer at the argument after index in argv. Exits if the integer
// is invalid. Takes the index before the expected int value in order to print
// better error messages.
static int ParseIntArg(int argc, char **argv, int index) {
char *tmp = NULL;
int to_return = 0;
if ((index + 1) >= argc) {
printf("Argument %s needs a value.\n", argv[index]);
PrintUsage(argv[0]);
}
to_return = strtol(argv[index + 1], &tmp, 10);
// Make sure that, if tmp is a null character, that the argument wasn't
// simply a string with no content.
if ((*tmp != 0) || (argv[index + 1][0] == 0)) {
printf("Invalid number given to argument %s: %s\n", argv[index],
argv[index + 1]);
PrintUsage(argv[0]);
}
return to_return;
}
// Like ParseIntArg, except expects a floating-point double arg.
static double ParseDoubleArg(int argc, char **argv, int index) {
char *tmp = NULL;
double to_return = 0.0;
if ((index + 1) >= argc) {
printf("Argument %s needs a value.\n", argv[index]);
PrintUsage(argv[0]);
}
to_return = strtod(argv[index + 1], &tmp);
if ((*tmp != 0) || (argv[index + 1][0] == 0)) {
printf("Invalid number given to argument %s: %s\n", argv[index],
argv[index + 1]);
PrintUsage(argv[0]);
}
return to_return;
}
// Processes command-line arguments, setting values in the globals struct as
// necessary.
static void ParseArguments(int argc, char **argv) {
for (int i = 1; i < argc; i++) {
if (strcmp(argv[i], "--help") == 0) {
PrintUsage(argv[0]);
}
if (strcmp(argv[i], "-d") == 0) {
g.cuda_device = ParseIntArg(argc, argv, i);
i++;
continue;
}
if (strcmp(argv[i], "-o") == 0) {
if ((i + 1) >= argc) {
printf("Missing output file name.\n");
PrintUsage(argv[0]);
}
i++;
g.output_image = argv[i];
continue;
}
if (strcmp(argv[i], "-s") == 0) {
if ((i + 1) >= argc) {
printf("Missing in-progress buffer file name.\n");
PrintUsage(argv[0]);
}
i++;
g.inprogress_file = argv[i];
continue;
}
if (strcmp(argv[i], "-m") == 0) {
g.iterations.max_escape_iterations = ParseIntArg(argc, argv, i);
if (g.iterations.max_escape_iterations > 60000) {
printf("Warning: Using a high number of iterations may cause the "
"program respond slowly to Ctrl+C or time running out.\n");
}
i++;
continue;
}
if (strcmp(argv[i], "-c") == 0) {
g.iterations.min_escape_iterations = ParseIntArg(argc, argv, i);
i++;
continue;
}
if (strcmp(argv[i], "-w") == 0) {
g.dimensions.w = ParseIntArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "-h") == 0) {
g.dimensions.h = ParseIntArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "-g") == 0) {
g.gamma_correction = ParseDoubleArg(argc, argv, i);
i++;
continue;
}
if (strcmp(argv[i], "-t") == 0) {
g.seconds_to_run = ParseDoubleArg(argc, argv, i);
i++;
continue;
}
if (strcmp(argv[i], "--min-real") == 0) {
g.dimensions.min_real = ParseDoubleArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "--max-real") == 0) {
g.dimensions.max_real = ParseDoubleArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "--min-imag") == 0) {
g.dimensions.min_imag = ParseDoubleArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "--max-imag") == 0) {
g.dimensions.max_imag = ParseDoubleArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
// Unrecognized argument, print the usage string.
printf("Invalid argument: %s\n", argv[i]);
PrintUsage(argv[0]);
}
}
void SignalHandler(int signal_number) {
g.quit_signal_received = 1;
printf("Signal %d received, waiting for current pass to finish...\n",
signal_number);
}
int main(int argc, char **argv) {
memset(&g, 0, sizeof(g));
g.output_image = DEFAULT_OUTPUT_NAME;
g.iterations.max_escape_iterations = 100;
g.iterations.min_escape_iterations = 20;
g.block_size = DEFAULT_BLOCK_SIZE;
g.block_count = DEFAULT_BLOCK_COUNT;
g.seconds_to_run = 10.0;
g.gamma_correction = 1.0;
SetDefaultCanvas();
g.cuda_device = 0;
ParseArguments(argc, argv);
if (signal(SIGINT, SignalHandler) == SIG_ERR) {
printf("Failed setting signal handler.\n");
CleanupGlobals();
return 1;
}
printf("Creating %dx%d image, %d max iterations.\n",
g.dimensions.w, g.dimensions.h, g.iterations.max_escape_iterations);
printf("Calculating image...\n");
SetupCUDA();
LoadInProgressBuffer();
RenderImage();
SaveInProgressBuffer();
printf("Saving image.\n");
SaveImage();
printf("Done! Output image saved: %s\n", g.output_image);
CleanupGlobals();
return 0;
} | #include <errno.h>
#include <fcntl.h>
#include <signal.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
// Controls the number of threads per block to use.
#define DEFAULT_BLOCK_SIZE (512)
// Controls the default number of blocks to use.
#define DEFAULT_BLOCK_COUNT (512)
// The name given to the output file if one isn't specified.
#define DEFAULT_OUTPUT_NAME "output.pgm"
// This macro takes a cudaError_t value and exits the program if it isn't equal
// to cudaSuccess.
#define CheckCUDAError(val) (InternalCUDAErrorCheck((val), #val, __FILE__, __LINE__))
// Increasing this may increase efficiency, but decrease responsiveness to
// signals.
#define SAMPLES_PER_THREAD (50)
// The RNG seed used when initializing the RNG states on the GPU.
#define DEFAULT_RNG_SEED (1337)
// The type that we use to keep track of internal pixel counts. Must be a
// numerical type that will work with both IncrementPixelCounter,
// GetLinearColorScale, and DoGammaCorrection. Floating-point values *ought* to
// work here, too.
typedef uint32_t Pixel;
// Holds the boundaries and sizes of the fractal, in both pixels and numbers
typedef struct {
// The width and height of the image in pixels.
int w;
int h;
// The boundaries of the fractal.
double min_real;
double min_imag;
double max_real;
double max_imag;
// The distance between pixels in the real and imaginary axes.
double delta_real;
double delta_imag;
} FractalDimensions;
// This struct holds the parameters for different types of "iterations" needed
// when calculating the Buddhabrot.
typedef struct {
// This is the maximum number of iterations to run to see if a point escapes.
int max_escape_iterations;
// If a point escapes in fewer than this many iterations, it will be ignored.
int min_escape_iterations;
} IterationControl;
// Holds global state in a single struct.
static struct {
// The CUDA device to use. Defaults to 0.
int cuda_device;
// This tracks the random number generator states for the GPU code.
hiprandState_t *rng_states;
// The number of threads and blocks to use when calculating the Buddhabrot.
int block_size, block_count;
// The filename to which a bitmap image will be saved, or NULL if an image
// should not be saved.
const char *output_image;
// The filename from which to load an in-progress image buffer, or to which
// the in-progress buffer should be stored if operation is interrupted.
const char *inprogress_file;
// The number of seconds to run the calculation. If negative, run
// indefinitely until a signal is received.
double seconds_to_run;
// If this is nonzero, the program should save the image and quit as soon as
// the current iteration finishes.
int quit_signal_received;
// Holds various iteration-related settings.
IterationControl iterations;
// The size and location of the fractal and output image.
FractalDimensions dimensions;
// The host and device buffers which contain the numbers of times an escaping
// point's path crossed each point in the complex plane.
Pixel *device_buddhabrot;
Pixel *host_buddhabrot;
// The gamma value for gamma correction.
double gamma_correction;
// Buffer for a single grayscale image.
uint16_t *grayscale_image;
} g;
// Returns the size, in bytes, of the internal image buffer used to hold the
// pixel data.
static uint64_t GetImageBufferSize(void) {
return ((uint64_t) g.dimensions.w) * ((uint64_t) g.dimensions.h) *
sizeof(Pixel);
}
// If any globals have been initialized, this will free them. (Relies on
// globals being set to 0 at the start of the program)
static void CleanupGlobals(void) {
hipFree(g.rng_states);
hipFree(g.device_buddhabrot);
hipFree(g.rng_states);
free(g.grayscale_image);
free(g.host_buddhabrot);
memset(&g, 0, sizeof(g));
}
// Returns the current time in seconds.
static double CurrentSeconds(void) {
struct timespec ts;
if (clock_gettime(CLOCK_REALTIME, &ts) != 0) {
printf("Error getting time.\n");
exit(1);
}
return ((double) ts.tv_sec) + (((double) ts.tv_nsec) / 1e9);
}
// Prints an error message and exits the program if the cudaError_t value is
// not equal to cudaSuccess. Generally, this will be called via the
// CheckCUDAError macro.
static void InternalCUDAErrorCheck(hipError_t result, const char *fn,
const char *file, int line) {
if (result == hipSuccess) return;
printf("CUDA error %d (%s) in %s, line %d (%s)\n", (int) result,
hipGetErrorString(result), file, line, fn);
CleanupGlobals();
exit(1);
}
// This function is used to initialize the RNG states to use when generating
// starting points in the Buddhabrot calculation. The states array must hold
// one entry for every thread in every block.
__global__ void InitializeRNG(uint64_t seed, hiprandState_t *states) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
hiprand_init(seed, index, 0, states + index);
}
// Allocates CUDA memory and calculates block/grid sizes. Must be called after
// g.w and g.h have been set.
static void SetupCUDA(void) {
float gpu_memory_needed, cpu_memory_needed;
CheckCUDAError(hipSetDevice(g.cuda_device));
size_t pixel_count = g.dimensions.w * g.dimensions.h;
// The GPU will need space for the image and the RNG states.
gpu_memory_needed = GetImageBufferSize() +
(g.block_size * g.block_count * sizeof(hiprandState_t));
gpu_memory_needed /= (1024.0 * 1024.0);
// The CPU needs space for the image and grayscale conversion.
cpu_memory_needed = GetImageBufferSize() + (pixel_count * sizeof(uint16_t));
cpu_memory_needed /= (1024.0 * 1024.0);
printf("Approximate memory needed: %.03f MiB GPU, %.03f MiB CPU\n",
gpu_memory_needed, cpu_memory_needed);
// Initialize the host and device image buffers.
CheckCUDAError(hipMalloc(&(g.device_buddhabrot), GetImageBufferSize()));
CheckCUDAError(hipMemset(g.device_buddhabrot, 0, GetImageBufferSize()));
g.host_buddhabrot = (Pixel *) calloc(1, GetImageBufferSize());
if (!g.host_buddhabrot) {
CleanupGlobals();
exit(1);
}
// Initialize the RNG state for the device.
CheckCUDAError(hipMalloc(&(g.rng_states), g.block_size * g.block_count *
sizeof(hiprandState_t)));
InitializeRNG<<<g.block_size, g.block_count>>>(DEFAULT_RNG_SEED,
g.rng_states);
CheckCUDAError(hipDeviceSynchronize());
g.grayscale_image = (uint16_t *) calloc(pixel_count, sizeof(uint16_t));
if (!g.grayscale_image) {
printf("Failed allocating grayscale image.\n");
CleanupGlobals();
exit(1);
}
}
// Returns the size, in bytes, of f. Exits on error.
static uint64_t GetFileSize(FILE *f) {
int64_t to_return;
if (fseek(f, 0, SEEK_END) != 0) {
printf("Failed seeking file end: %s\n", strerror(errno));
CleanupGlobals();
exit(1);
}
to_return = ftell(f);
if (to_return < 0) {
printf("Failed reading file size: %s\n", strerror(errno));
CleanupGlobals();
exit(1);
}
if (fseek(f, 0, SEEK_SET) != 0) {
printf("Failed seeking file start: %s\n", strerror(errno));
CleanupGlobals();
exit(1);
}
return to_return;
}
// Loads the in-progress buffer from a file, if the file exists. Exits if an
// error occurs. Creates the file if it doesn't exist.
static void LoadInProgressBuffer(void) {
uint64_t expected_size, file_size;
FILE *f = NULL;
if (!g.inprogress_file) return;
// We won't consider it an error if the file doesn't exist, and won't try to
// load its contents.
f = fopen(g.inprogress_file, "rb");
expected_size = GetImageBufferSize();
printf("Loading previous image state from %s.\n",
g.inprogress_file);
if (!f) {
if (errno == ENOENT) {
printf("File %s doesn't exist yet. Not loading.\n",
g.inprogress_file);
return;
}
printf("Failed opening %s: %s\n", g.inprogress_file, strerror(errno));
CleanupGlobals();
exit(1);
}
file_size = GetFileSize(f);
// Ensure the file matches the expected size of our image buffer.
if (file_size != expected_size) {
printf("The size of %s doesn't match the expected size of %lu bytes.\n",
g.inprogress_file, (unsigned long) expected_size);
fclose(f);
CleanupGlobals();
exit(1);
}
// Read the file to the local buffer, then update the device copy.
if (fread(g.host_buddhabrot, expected_size, 1, f) != 1) {
printf("Failed reading %s: %s\n", g.inprogress_file, strerror(errno));
fclose(f);
CleanupGlobals();
exit(1);
}
fclose(f);
f = NULL;
CheckCUDAError(hipMemcpy(g.device_buddhabrot, g.host_buddhabrot,
expected_size, hipMemcpyHostToDevice));
}
// Saves the in-progress buffer to a file, if the filename was specified.
// Exits if an error occurs.
static void SaveInProgressBuffer(void) {
FILE *f = NULL;
if (!g.inprogress_file) return;
printf("Saving in-progress buffer to %s.\n", g.inprogress_file);
f = fopen(g.inprogress_file, "wb");
if (!f) {
printf("Failed opening %s: %s\n", g.inprogress_file, strerror(errno));
CleanupGlobals();
exit(1);
}
if (fwrite(g.host_buddhabrot, GetImageBufferSize(), 1, f) != 1) {
printf("Failed writing data to %s: %s\n", g.inprogress_file,
strerror(errno));
fclose(f);
CleanupGlobals();
exit(1);
}
fclose(f);
}
// This returns nonzero if the given point is in the main cardioid of the set
// and is therefore guaranteed to not escape.
inline __device__ int InMainCardioid(double real, double imag) {
// This algorithm was taken from the Wikipedia Mandelbrot set page.
double imag_squared = imag * imag;
double q = (real - 0.25);
q = q * q + imag_squared;
return q * (q + (real - 0.25)) < (imag_squared * 0.25);
}
// This returns nonzero if the given point is in the order 2 bulb of the set
// and therefore guaranteed to not escape.
inline __device__ int InOrder2Bulb(double real, double imag) {
double tmp = real + 1;
tmp = tmp * tmp;
return (tmp + (imag * imag)) < (1.0 / 16.0);
}
// This should be used to update the pixel data for a point that is encountered
// in the set.
inline __device__ void IncrementPixelCounter(double real, double imag,
Pixel *data, FractalDimensions *d) {
int row, col;
// There's a small issue here with integer-dividing where values that should
// be immediately outside of the canvas can still appear on row or col 0, so
// just return early if we're outside the boundary.
if ((real < d->min_real) || (imag < d->min_imag)) return;
col = (real - d->min_real) / d->delta_real;
row = (imag - d->min_imag) / d->delta_imag;
if ((row >= 0) && (row < d->h) && (col >= 0) && (col < d->w)) {
data[(row * d->w) + col] += 1;
}
}
// Does the Mandelbrot-set iterations for the given (real, imag) point. Returns
// the number of iterations before the point escapes, or max_iterations if the
// point never escapes.
inline __device__ int IterateMandelbrot(double start_real, double start_imag,
int max_iterations) {
double tmp, real, imag;
int i;
real = start_real;
imag = start_imag;
// This loop-unrolling was tested on a Radeon VII, anything higher or lower
// than 4 produced worse performance. May differ on other devices, or future
// compiler updates.
//#pragma unroll 4
for (i = 0; i < max_iterations; i++) {
real = fabs(real);
imag = fabs(imag);
tmp = (real * real) - (imag * imag) + start_real;
imag = 2 * real * imag + start_imag;
real = tmp;
// If the point escapes, stop iterating and indicate the loop ended due
// to the point escaping.
if (((real * real) + (imag * imag)) > 4) return i;
}
// The point didn't escape, return max_iterations.
return max_iterations;
}
// Like IterateMandelbrot, but records the point's path. For efficiency, this
// function also has an important difference from IterateMandelbrot: *it does
// not check the max iterations*. This is important! Do not call this function
// for a point unless you're sure that it escapes in a finite number of
// iterations.
inline __device__ void IterateAndRecord(double start_real, double start_imag,
Pixel *data, FractalDimensions *d) {
double tmp, real, imag;
real = start_real;
imag = start_imag;
//#pragma unroll 4
while (1) {
real = fabs(real);
imag = fabs(imag);
tmp = (real * real) - (imag * imag) + start_real;
imag = 2 * real * imag + start_imag;
real = tmp;
IncrementPixelCounter(real, imag, data, d);
// Stop iterating when the point escapes. This must be *guaranteed* to
// happen by the caller performing a prior check!
if (((real * real) + (imag * imag)) > 4) break;
}
}
// This kernel is responsible for drawing the paths of "particles" that escape
// the mandelbrot set. It works as follows:
//
// 1. For each "sample", compute a new random starting point in the complex
// plane
// 2. Do the normal mandelbrot iterations on the starting point, *without*
// recording its path
// 3. If the point didn't escape the path, take a new sample (return to step 1)
// 4. If the point escaped (within the min and max iteration limits), then
// repeat the mandelbrot iterations (e.g. step 2), except record its path
// by incrementing the pixel value for every point it passes through.
__global__ void DrawBuddhabrot(FractalDimensions dimensions, Pixel *data,
IterationControl iterations, hiprandState_t *states) {
int index = (blockIdx.x * blockDim.x) + threadIdx.x;
hiprandState_t *rng = states + index;
int sample, iterations_needed, max_iterations, min_iterations;
double real, imag;
max_iterations = iterations.max_escape_iterations;
min_iterations = iterations.min_escape_iterations;
// We're going to pick a number of random starting points determined by the
// SAMPLES_PER_THREAD value.
for (sample = 0; sample < SAMPLES_PER_THREAD; sample++) {
// Sample across the entire domain of the set regardless of our "canvas"
real = (hiprand_uniform_double(rng) * 4.0) - 2.0;
imag = (hiprand_uniform_double(rng) * 4.0) - 2.0;
// Optimization: we know ahead of time that points from the main cardioid
// and the largest "bulb" will never escape, and it's fast to check them.
//if (InMainCardioid(real, imag) || InOrder2Bulb(real, imag)) continue;
// Now, do the normal Mandelbrot iterations to see how quickly the point
// escapes (if it does). However, we won't record the path yet.
iterations_needed = IterateMandelbrot(real, imag, max_iterations);
// Don't record the path if the point never escaped, or if it escaped too
// quickly.
if (iterations_needed >= max_iterations) continue;
if (iterations_needed < min_iterations) continue;
// At this point, do the Mandelbrot iterations, but actually record the
// path because we know the point is "good".
IterateAndRecord(real, imag, data, &dimensions);
}
}
static uint16_t Clamp(double v) {
if (v <= 0) return 0;
if (v >= 0xffff) return 0xffff;
return (uint16_t) v;
}
// Returns the amount to multiply the original count by in order to get a value
// by which Buddhabrot counts can be multiplied to get a number between 0 and
// 0xffff.
static double GetLinearColorScale(void) {
int x, y, index;
Pixel max = 0;
double to_return;
index = 0;
for (y = 0; y < g.dimensions.h; y++) {
for (x = 0; x < g.dimensions.w; x++) {
if (g.host_buddhabrot[index] > max) max = g.host_buddhabrot[index];
index++;
}
}
to_return = ((double) 0xffff) / ((double) max);
printf("Max value: %lu, scale: %f\n", (unsigned long) max, to_return);
return to_return;
}
// Returns the gamma-corrected 16-bit color channel value given a Buddhabrot
// iteration count c.
static uint16_t DoGammaCorrection(Pixel c, double linear_scale) {
double max = 0xffff;
double scaled = ((double) c) * linear_scale;
// Don't do gamma correction if the gamma correction argument was negative.
if (g.gamma_correction <= 0.0) return scaled;
return Clamp(max * pow(scaled / max, 1 / g.gamma_correction));
}
// Converts the buffer of pixel values to a gamma-corrected grayscale image
// with 16-bit colors. The Pixel values are scaled to fill the 16-bit color
// range.
static void SetGrayscalePixels(void) {
int x, y;
uint16_t color_value;
double linear_scale = GetLinearColorScale();
Pixel *host_data = g.host_buddhabrot;
uint16_t *grayscale = g.grayscale_image;
for (y = 0; y < g.dimensions.h; y++) {
for (x = 0; x < g.dimensions.w; x++) {
color_value = DoGammaCorrection(*host_data, linear_scale);
*grayscale = color_value;
grayscale++;
host_data++;
}
}
}
// Renders the fractal image.
static void RenderImage(void) {
int passes_count = 0;
double start_seconds;
printf("Calculating Buddhabrot.\n");
if (g.seconds_to_run < 0) {
printf("Press ctrl+C to finish.\n");
} else {
printf("Running for %.03f seconds.\n", g.seconds_to_run);
}
// Run until either the time elapsed or we've received a SIGINT.
start_seconds = CurrentSeconds();
while (!g.quit_signal_received) {
passes_count++;
DrawBuddhabrot<<<g.block_count, g.block_size>>>(g.dimensions,
g.device_buddhabrot, g.iterations, g.rng_states);
CheckCUDAError(hipDeviceSynchronize());
if ((g.seconds_to_run >= 0) && ((CurrentSeconds() - start_seconds) >
g.seconds_to_run)) {
break;
}
}
// Copy the resulting image to CPU memory, and convert the pixels to proper
// grayscale values.
CheckCUDAError(hipMemcpy(g.host_buddhabrot, g.device_buddhabrot,
GetImageBufferSize(), hipMemcpyDeviceToHost));
printf("%d Buddhabrot passes took %f seconds.\n", passes_count,
CurrentSeconds() - start_seconds);
SetGrayscalePixels();
}
// Recomputes the spacing between pixels in the image. Returns 0 if any image-
// dimension setting is invalid. Otherwise, returns 1.
static int RecomputePixelDeltas(void) {
FractalDimensions *dims = &(g.dimensions);
if (dims->w <= 0) {
printf("Output width must be positive.\n");
return 0;
}
if (dims->h <= 0) {
printf("Output height must be positive.\n");
return 0;
}
if (dims->max_real <= dims->min_real) {
printf("Maximum real value must be greater than minimum real value.\n");
return 0;
}
if (dims->max_imag <= dims->min_imag) {
printf("Minimum imaginary value must be greater than maximum imaginary "
"value.\n");
return 0;
}
dims->delta_imag = (dims->max_imag - dims->min_imag) / ((double) dims->h);
dims->delta_real = (dims->max_real - dims->min_real) / ((double) dims->w);
return 1;
}
// Sets the image boundaries and dimensions to their default values.
static void SetDefaultCanvas(void) {
FractalDimensions *dims = &(g.dimensions);
memset(dims, 0, sizeof(*dims));
dims->w = 1000;
dims->h = 1000;
dims->min_real = -2.0;
dims->max_real = 2.0;
dims->min_imag = -2.0;
dims->max_imag = 2.0;
if (!RecomputePixelDeltas()) {
printf("Internal error setting default canvas boundaries!\n");
exit(1);
}
}
// If a filename has been set for saving the image, this will attempt to save
// the image to the file. This can modify the image buffer! (For changing byte
// order.)
static void SaveImage(void) {
uint16_t tmp;
int i;
int pixel_count = g.dimensions.w * g.dimensions.h;
FILE *output = fopen(g.output_image, "wb");
if (!output) {
printf("Failed opening output image.\n");
return;
}
if (fprintf(output, "P5\n%d %d\n%d\n", g.dimensions.w, g.dimensions.h,
0xffff) <= 0) {
printf("Failed writing pgm header.\n");
fclose(output);
return;
}
// Flip the byte-order for the image. This assumes the program is running on
// a little-endian architecture. I'll fix it if there's ever a demand to run
// this on something other than Linux on x86 or ARM64 (lol).
for (i = 0; i < pixel_count; i++) {
tmp = g.grayscale_image[i];
tmp = ((tmp & 0xff) << 8) | (tmp >> 8);
g.grayscale_image[i] = tmp;
}
if (!fwrite(g.grayscale_image, pixel_count * sizeof(uint16_t), 1, output)) {
printf("Failed writing pixel data.\n");
fclose(output);
return;
}
fclose(output);
}
static void PrintUsage(char *program_name) {
printf("Usage: %s [options]\n\n", program_name);
printf("Options may be one or more of the following:\n"
" --help: Prints these instructions.\n"
" -d <device number>: Sets which GPU to use. Defaults to GPU 0.\n"
" -o <output file name>: If provided, the rendered image will be saved\n"
" to a .pgm file with the given name. Otherwise, saves the image\n"
" to " DEFAULT_OUTPUT_NAME ".\n"
" -m <max escape iterations>: The maximum number of iterations to use\n"
" before giving up on seeing whether a point escapes.\n"
" -c <min escape iterations>: If a point escapes before this number of\n"
" iterations, it will be ignored.\n"
" -g <gamma correction>: A gamma-correction value to use on the\n"
" resulting image. If negative, no gamma correction will occur.\n"
" -t <seconds to run>: A number of seconds to run the calculation for.\n"
" Defaults to 10.0. If negative, the program will run continuously\n"
" and will terminate (saving the image) when it receives a SIGINT.\n"
" -w <width>: The width of the output image, in pixels. Defaults to\n"
" 1000.\n"
" -h <height>: The height of the output image, in pixels. Defaults to\n"
" 1000.\n"
" -s <save/load file>: If provided, this gives a file name into which\n"
" the rendering buffer will be saved, for future continuation.\n"
" If the program is loaded and the file exists, the buffer will be\n"
" filled with the contents of the file, but the dimensions must\n"
" match. Note that this file may be huge for high-resolution images.\n"
"\n"
"The following settings control the location of the output image on the\n"
"complex plane, but samples are always drawn from the entire Mandelbrot-\n"
"set domain (-2-2i to 2+2i). So these settings can be used to save\n"
"memory or \"crop\" the output, but won't otherwise speed up rendering:\n"
" --min-real <min real>: The minimum value along the real axis to\n"
" include in the output image. Defaults to -2.0.\n"
" --max-real <max real>: The maximum value along the real axis to\n"
" include in the output image. Defaults to 2.0.\n"
" --min-imag <min imag>: The minimum value along the imaginary axis to\n"
" include in the output image. Defaults to -2.0.\n"
" --max-imag <max imag>: The maximum value along the imaginary axis to\n"
" include in the output image. Defaults to 2.0.\n"
"");
exit(0);
}
// Returns an integer at the argument after index in argv. Exits if the integer
// is invalid. Takes the index before the expected int value in order to print
// better error messages.
static int ParseIntArg(int argc, char **argv, int index) {
char *tmp = NULL;
int to_return = 0;
if ((index + 1) >= argc) {
printf("Argument %s needs a value.\n", argv[index]);
PrintUsage(argv[0]);
}
to_return = strtol(argv[index + 1], &tmp, 10);
// Make sure that, if tmp is a null character, that the argument wasn't
// simply a string with no content.
if ((*tmp != 0) || (argv[index + 1][0] == 0)) {
printf("Invalid number given to argument %s: %s\n", argv[index],
argv[index + 1]);
PrintUsage(argv[0]);
}
return to_return;
}
// Like ParseIntArg, except expects a floating-point double arg.
static double ParseDoubleArg(int argc, char **argv, int index) {
char *tmp = NULL;
double to_return = 0.0;
if ((index + 1) >= argc) {
printf("Argument %s needs a value.\n", argv[index]);
PrintUsage(argv[0]);
}
to_return = strtod(argv[index + 1], &tmp);
if ((*tmp != 0) || (argv[index + 1][0] == 0)) {
printf("Invalid number given to argument %s: %s\n", argv[index],
argv[index + 1]);
PrintUsage(argv[0]);
}
return to_return;
}
// Processes command-line arguments, setting values in the globals struct as
// necessary.
static void ParseArguments(int argc, char **argv) {
for (int i = 1; i < argc; i++) {
if (strcmp(argv[i], "--help") == 0) {
PrintUsage(argv[0]);
}
if (strcmp(argv[i], "-d") == 0) {
g.cuda_device = ParseIntArg(argc, argv, i);
i++;
continue;
}
if (strcmp(argv[i], "-o") == 0) {
if ((i + 1) >= argc) {
printf("Missing output file name.\n");
PrintUsage(argv[0]);
}
i++;
g.output_image = argv[i];
continue;
}
if (strcmp(argv[i], "-s") == 0) {
if ((i + 1) >= argc) {
printf("Missing in-progress buffer file name.\n");
PrintUsage(argv[0]);
}
i++;
g.inprogress_file = argv[i];
continue;
}
if (strcmp(argv[i], "-m") == 0) {
g.iterations.max_escape_iterations = ParseIntArg(argc, argv, i);
if (g.iterations.max_escape_iterations > 60000) {
printf("Warning: Using a high number of iterations may cause the "
"program respond slowly to Ctrl+C or time running out.\n");
}
i++;
continue;
}
if (strcmp(argv[i], "-c") == 0) {
g.iterations.min_escape_iterations = ParseIntArg(argc, argv, i);
i++;
continue;
}
if (strcmp(argv[i], "-w") == 0) {
g.dimensions.w = ParseIntArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "-h") == 0) {
g.dimensions.h = ParseIntArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "-g") == 0) {
g.gamma_correction = ParseDoubleArg(argc, argv, i);
i++;
continue;
}
if (strcmp(argv[i], "-t") == 0) {
g.seconds_to_run = ParseDoubleArg(argc, argv, i);
i++;
continue;
}
if (strcmp(argv[i], "--min-real") == 0) {
g.dimensions.min_real = ParseDoubleArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "--max-real") == 0) {
g.dimensions.max_real = ParseDoubleArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "--min-imag") == 0) {
g.dimensions.min_imag = ParseDoubleArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
if (strcmp(argv[i], "--max-imag") == 0) {
g.dimensions.max_imag = ParseDoubleArg(argc, argv, i);
if (!RecomputePixelDeltas()) PrintUsage(argv[0]);
i++;
continue;
}
// Unrecognized argument, print the usage string.
printf("Invalid argument: %s\n", argv[i]);
PrintUsage(argv[0]);
}
}
void SignalHandler(int signal_number) {
g.quit_signal_received = 1;
printf("Signal %d received, waiting for current pass to finish...\n",
signal_number);
}
int main(int argc, char **argv) {
memset(&g, 0, sizeof(g));
g.output_image = DEFAULT_OUTPUT_NAME;
g.iterations.max_escape_iterations = 100;
g.iterations.min_escape_iterations = 20;
g.block_size = DEFAULT_BLOCK_SIZE;
g.block_count = DEFAULT_BLOCK_COUNT;
g.seconds_to_run = 10.0;
g.gamma_correction = 1.0;
SetDefaultCanvas();
g.cuda_device = 0;
ParseArguments(argc, argv);
if (signal(SIGINT, SignalHandler) == SIG_ERR) {
printf("Failed setting signal handler.\n");
CleanupGlobals();
return 1;
}
printf("Creating %dx%d image, %d max iterations.\n",
g.dimensions.w, g.dimensions.h, g.iterations.max_escape_iterations);
printf("Calculating image...\n");
SetupCUDA();
LoadInProgressBuffer();
RenderImage();
SaveInProgressBuffer();
printf("Saving image.\n");
SaveImage();
printf("Done! Output image saved: %s\n", g.output_image);
CleanupGlobals();
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define N 4096
#define N_2 N*N
#define BLOCK_SIZE 32
float a[N_2], b[N_2];
float c[N_2];
__global__ void mm_kernel(float* A, float* B, float* C) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N) {
float tmp = 0;
for (int i = 0; i < N; ++i) {
tmp += A[row * N + i] * B[i * N + col];
}
C[row * N + col] = tmp;
}
}
int main() {
srand(time(NULL));
//dim3 dimGrid(3, 3, 1);
//dim3 dimBlock(N/3, N/3, 1);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i*N + j] = rand() % 10 + 1;
b[i*N + j] = rand() % 10 + 1;
}
}
/*
printf("a:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", a[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");
printf("b:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", b[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");*/
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float*d_a, *d_b;
float *d_c;
cudaMalloc((void **)&d_a, N_2*sizeof(float));
cudaMalloc((void **)&d_b, N_2*sizeof(float));
cudaMalloc((void **)&d_c, N_2*sizeof(float));
cudaMemcpy(d_a, a, N_2*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, N_2*sizeof(float), cudaMemcpyHostToDevice);
unsigned int grid_rows = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows, 1); //.x
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1); //.y
cudaEventRecord(start);
mm_kernel<<<dimGrid, dimBlock>>> (d_a, d_b, d_c);
cudaMemcpy(c, d_c, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("time : %f\n", milliseconds);
/*
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%lf ", c[i*N + j]);
}
printf("\n");
}*/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z9mm_kernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0xfff, PT ; /* 0x00000fff0000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R9, 0xfff, P0 ; /* 0x00000fff0900780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R9, R9, 0xc, RZ ; /* 0x0000000c09097819 */
/* 0x000fe200000006ff */
/*00b0*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*00f0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0100*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0110*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe40007ffe0ff */
/*0120*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0130*/ IMAD.WIDE R14, R9, 0x4, R4 ; /* 0x00000004090e7825 */
/* 0x000fe200078e0204 */
/*0140*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fc60008000f00 */
/*0150*/ IMAD.WIDE R2, R11, 0x4, R4 ; /* 0x000000040b027825 */
/* 0x000fe400078e0204 */
/*0160*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*0170*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe400078e0206 */
/*0180*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ee8000c1e1900 */
/*0190*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R27, [R6.64+0x4000] ; /* 0x00400004061b7981 */
/* 0x000ee8000c1e1900 */
/*01b0*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000f28000c1e1900 */
/*01c0*/ LDG.E R19, [R6.64+0x8000] ; /* 0x0080000406137981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R20, [R6.64+0xc000] ; /* 0x00c0000406147981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R25, [R6.64+0x10000] ; /* 0x0100000406197981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R18, [R2.64+0x10] ; /* 0x0000100402127981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R21, [R6.64+0x14000] ; /* 0x0140000406157981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R13, [R6.64+0x18000] ; /* 0x01800004060d7981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0x1c000] ; /* 0x01c00004060f7981 */
/* 0x001f68000c1e1900 */
/*0260*/ LDG.E R26, [R6.64+0x3c000] ; /* 0x03c00004061a7981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R29, [R2.64+0x38] ; /* 0x00003804021d7981 */
/* 0x000f62000c1e1900 */
/*0280*/ FFMA R14, R17, R14, R12 ; /* 0x0000000e110e7223 */
/* 0x004fc6000000000c */
/*0290*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ FFMA R24, R27, R24, R14 ; /* 0x000000181b187223 */
/* 0x008fc6000000000e */
/*02b0*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R17, [R6.64+0x20000] ; /* 0x0200000406117981 */
/* 0x000ee2000c1e1900 */
/*02d0*/ FFMA R24, R19, R16, R24 ; /* 0x0000001013187223 */
/* 0x010fc60000000018 */
/*02e0*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R19, [R6.64+0x24000] ; /* 0x0240000406137981 */
/* 0x000f22000c1e1900 */
/*0300*/ FFMA R24, R20, R23, R24 ; /* 0x0000001714187223 */
/* 0x020fc60000000018 */
/*0310*/ LDG.E R23, [R2.64+0x24] ; /* 0x0000240402177981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R20, [R6.64+0x28000] ; /* 0x0280000406147981 */
/* 0x000f62000c1e1900 */
/*0330*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x000fc60000000018 */
/*0340*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280402197981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R22, [R6.64+0x2c000] ; /* 0x02c0000406167981 */
/* 0x000f62000c1e1900 */
/*0360*/ FFMA R24, R21, R18, R24 ; /* 0x0000001215187223 */
/* 0x000fc60000000018 */
/*0370*/ LDG.E R21, [R2.64+0x2c] ; /* 0x00002c0402157981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R18, [R6.64+0x30000] ; /* 0x0300000406127981 */
/* 0x000f62000c1e1900 */
/*0390*/ FFMA R28, R13, R10, R24 ; /* 0x0000000a0d1c7223 */
/* 0x000fc60000000018 */
/*03a0*/ LDG.E R24, [R2.64+0x30] ; /* 0x0000300402187981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R13, [R6.64+0x34000] ; /* 0x03400004060d7981 */
/* 0x000f68000c1e1900 */
/*03c0*/ LDG.E R10, [R6.64+0x38000] ; /* 0x03800004060a7981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R27, [R2.64+0x34] ; /* 0x00003404021b7981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*03f0*/ ISETP.NE.AND P0, PT, R8, 0x1000, PT ; /* 0x000010000800780c */
/* 0x000fe20003f05270 */
/*0400*/ UIADD3 UR6, UP0, UR6, 0x40000, URZ ; /* 0x0004000006067890 */
/* 0x000fe2000ff1e03f */
/*0410*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fc60007f3e0ff */
/*0420*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0430*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0440*/ FFMA R12, R15, R12, R28 ; /* 0x0000000c0f0c7223 */
/* 0x004fc8000000001c */
/*0450*/ FFMA R12, R17, R14, R12 ; /* 0x0000000e110c7223 */
/* 0x008fc8000000000c */
/*0460*/ FFMA R12, R19, R16, R12 ; /* 0x00000010130c7223 */
/* 0x010fc8000000000c */
/*0470*/ FFMA R12, R20, R23, R12 ; /* 0x00000017140c7223 */
/* 0x020fc8000000000c */
/*0480*/ FFMA R12, R22, R25, R12 ; /* 0x00000019160c7223 */
/* 0x000fc8000000000c */
/*0490*/ FFMA R12, R18, R21, R12 ; /* 0x00000015120c7223 */
/* 0x000fc8000000000c */
/*04a0*/ FFMA R12, R13, R24, R12 ; /* 0x000000180d0c7223 */
/* 0x000fc8000000000c */
/*04b0*/ FFMA R12, R10, R27, R12 ; /* 0x0000001b0a0c7223 */
/* 0x000fc8000000000c */
/*04c0*/ FFMA R12, R26, R29, R12 ; /* 0x0000001d1a0c7223 */
/* 0x000fe2000000000c */
/*04d0*/ @P0 BRA 0x120 ; /* 0xfffffc4000000947 */
/* 0x000fea000383ffff */
/*04e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04f0*/ IADD3 R2, R0, R9, RZ ; /* 0x0000000900027210 */
/* 0x000fd20007ffe0ff */
/*0500*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0510*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101904 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define N 4096
#define N_2 N*N
#define BLOCK_SIZE 32
float a[N_2], b[N_2];
float c[N_2];
__global__ void mm_kernel(float* A, float* B, float* C) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N) {
float tmp = 0;
for (int i = 0; i < N; ++i) {
tmp += A[row * N + i] * B[i * N + col];
}
C[row * N + col] = tmp;
}
}
int main() {
srand(time(NULL));
//dim3 dimGrid(3, 3, 1);
//dim3 dimBlock(N/3, N/3, 1);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i*N + j] = rand() % 10 + 1;
b[i*N + j] = rand() % 10 + 1;
}
}
/*
printf("a:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", a[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");
printf("b:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", b[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");*/
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float*d_a, *d_b;
float *d_c;
cudaMalloc((void **)&d_a, N_2*sizeof(float));
cudaMalloc((void **)&d_b, N_2*sizeof(float));
cudaMalloc((void **)&d_c, N_2*sizeof(float));
cudaMemcpy(d_a, a, N_2*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, N_2*sizeof(float), cudaMemcpyHostToDevice);
unsigned int grid_rows = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows, 1); //.x
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1); //.y
cudaEventRecord(start);
mm_kernel<<<dimGrid, dimBlock>>> (d_a, d_b, d_c);
cudaMemcpy(c, d_c, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("time : %f\n", milliseconds);
/*
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%lf ", c[i*N + j]);
}
printf("\n");
}*/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_000b790c_00000000-6_mm_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_
.type _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_, @function
_Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mm_kernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_, .-_Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_
.globl _Z9mm_kernelPfS_S_
.type _Z9mm_kernelPfS_S_, @function
_Z9mm_kernelPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9mm_kernelPfS_S_, .-_Z9mm_kernelPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "time : %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq a(%rip), %rbp
leaq b(%rip), %r12
leaq 67108864(%rbp), %r13
.L12:
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq $16384, %rbx
jne .L13
addq $16384, %rbp
addq $16384, %r12
cmpq %r13, %rbp
jne .L12
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $67108864, %edx
leaq a(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
leaq b(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 48(%rsp)
movl $128, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movl $67108864, %edx
movq 40(%rsp), %rsi
leaq c(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9mm_kernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mm_kernelPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl c
.bss
.align 32
.type c, @object
.size c, 67108864
c:
.zero 67108864
.globl b
.align 32
.type b, @object
.size b, 67108864
b:
.zero 67108864
.globl a
.align 32
.type a, @object
.size a, 67108864
a:
.zero 67108864
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define N 4096
#define N_2 N*N
#define BLOCK_SIZE 32
float a[N_2], b[N_2];
float c[N_2];
__global__ void mm_kernel(float* A, float* B, float* C) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N) {
float tmp = 0;
for (int i = 0; i < N; ++i) {
tmp += A[row * N + i] * B[i * N + col];
}
C[row * N + col] = tmp;
}
}
int main() {
srand(time(NULL));
//dim3 dimGrid(3, 3, 1);
//dim3 dimBlock(N/3, N/3, 1);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i*N + j] = rand() % 10 + 1;
b[i*N + j] = rand() % 10 + 1;
}
}
/*
printf("a:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", a[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");
printf("b:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", b[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");*/
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float*d_a, *d_b;
float *d_c;
cudaMalloc((void **)&d_a, N_2*sizeof(float));
cudaMalloc((void **)&d_b, N_2*sizeof(float));
cudaMalloc((void **)&d_c, N_2*sizeof(float));
cudaMemcpy(d_a, a, N_2*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, N_2*sizeof(float), cudaMemcpyHostToDevice);
unsigned int grid_rows = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows, 1); //.x
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1); //.y
cudaEventRecord(start);
mm_kernel<<<dimGrid, dimBlock>>> (d_a, d_b, d_c);
cudaMemcpy(c, d_c, N*N*sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("time : %f\n", milliseconds);
/*
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%lf ", c[i*N + j]);
}
printf("\n");
}*/
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define N 4096
#define N_2 N*N
#define BLOCK_SIZE 32
float a[N_2], b[N_2];
float c[N_2];
__global__ void mm_kernel(float* A, float* B, float* C) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N) {
float tmp = 0;
for (int i = 0; i < N; ++i) {
tmp += A[row * N + i] * B[i * N + col];
}
C[row * N + col] = tmp;
}
}
int main() {
srand(time(NULL));
//dim3 dimGrid(3, 3, 1);
//dim3 dimBlock(N/3, N/3, 1);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i*N + j] = rand() % 10 + 1;
b[i*N + j] = rand() % 10 + 1;
}
}
/*
printf("a:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", a[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");
printf("b:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", b[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");*/
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float*d_a, *d_b;
float *d_c;
hipMalloc((void **)&d_a, N_2*sizeof(float));
hipMalloc((void **)&d_b, N_2*sizeof(float));
hipMalloc((void **)&d_c, N_2*sizeof(float));
hipMemcpy(d_a, a, N_2*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, N_2*sizeof(float), hipMemcpyHostToDevice);
unsigned int grid_rows = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows, 1); //.x
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1); //.y
hipEventRecord(start);
mm_kernel<<<dimGrid, dimBlock>>> (d_a, d_b, d_c);
hipMemcpy(c, d_c, N*N*sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("time : %f\n", milliseconds);
/*
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%lf ", c[i*N + j]);
}
printf("\n");
}*/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define N 4096
#define N_2 N*N
#define BLOCK_SIZE 32
float a[N_2], b[N_2];
float c[N_2];
__global__ void mm_kernel(float* A, float* B, float* C) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N) {
float tmp = 0;
for (int i = 0; i < N; ++i) {
tmp += A[row * N + i] * B[i * N + col];
}
C[row * N + col] = tmp;
}
}
int main() {
srand(time(NULL));
//dim3 dimGrid(3, 3, 1);
//dim3 dimBlock(N/3, N/3, 1);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i*N + j] = rand() % 10 + 1;
b[i*N + j] = rand() % 10 + 1;
}
}
/*
printf("a:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", a[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");
printf("b:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", b[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");*/
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float*d_a, *d_b;
float *d_c;
hipMalloc((void **)&d_a, N_2*sizeof(float));
hipMalloc((void **)&d_b, N_2*sizeof(float));
hipMalloc((void **)&d_c, N_2*sizeof(float));
hipMemcpy(d_a, a, N_2*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, N_2*sizeof(float), hipMemcpyHostToDevice);
unsigned int grid_rows = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows, 1); //.x
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1); //.y
hipEventRecord(start);
mm_kernel<<<dimGrid, dimBlock>>> (d_a, d_b, d_c);
hipMemcpy(c, d_c, N*N*sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("time : %f\n", milliseconds);
/*
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%lf ", c[i*N + j]);
}
printf("\n");
}*/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mm_kernelPfS_S_
.globl _Z9mm_kernelPfS_S_
.p2align 8
.type _Z9mm_kernelPfS_S_,@function
_Z9mm_kernelPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x1000, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 12, v1
v_mov_b32_e32 v4, 0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v2, v0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v7, vcc_lo, v5, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, 0x1000, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x4000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v3, v7
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v1, 12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mm_kernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mm_kernelPfS_S_, .Lfunc_end0-_Z9mm_kernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mm_kernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mm_kernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#define N 4096
#define N_2 N*N
#define BLOCK_SIZE 32
float a[N_2], b[N_2];
float c[N_2];
__global__ void mm_kernel(float* A, float* B, float* C) {
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N) {
float tmp = 0;
for (int i = 0; i < N; ++i) {
tmp += A[row * N + i] * B[i * N + col];
}
C[row * N + col] = tmp;
}
}
int main() {
srand(time(NULL));
//dim3 dimGrid(3, 3, 1);
//dim3 dimBlock(N/3, N/3, 1);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
a[i*N + j] = rand() % 10 + 1;
b[i*N + j] = rand() % 10 + 1;
}
}
/*
printf("a:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", a[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");
printf("b:\n");
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%f ", b[i*N + j]);
}
printf("\n");
}
printf("\n");
printf("\n");*/
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float*d_a, *d_b;
float *d_c;
hipMalloc((void **)&d_a, N_2*sizeof(float));
hipMalloc((void **)&d_b, N_2*sizeof(float));
hipMalloc((void **)&d_c, N_2*sizeof(float));
hipMemcpy(d_a, a, N_2*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, N_2*sizeof(float), hipMemcpyHostToDevice);
unsigned int grid_rows = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (N + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows, 1); //.x
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE, 1); //.y
hipEventRecord(start);
mm_kernel<<<dimGrid, dimBlock>>> (d_a, d_b, d_c);
hipMemcpy(c, d_c, N*N*sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("time : %f\n", milliseconds);
/*
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
printf("%lf ", c[i*N + j]);
}
printf("\n");
}*/
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "mm_1.hip"
.globl _Z24__device_stub__mm_kernelPfS_S_ # -- Begin function _Z24__device_stub__mm_kernelPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__mm_kernelPfS_S_,@function
_Z24__device_stub__mm_kernelPfS_S_: # @_Z24__device_stub__mm_kernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mm_kernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__mm_kernelPfS_S_, .Lfunc_end0-_Z24__device_stub__mm_kernelPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movq $-16384, %r15 # imm = 0xC000
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, a+16384(%rbx,%r15)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, b+16384(%rbx,%r15)
addq $4, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $16384, %rbx # imm = 0x4000
cmpq $4096, %r14 # imm = 0x1000
jne .LBB1_1
# %bb.4:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 24(%rsp), %rdi
movl $a, %esi
movl $67108864, %edx # imm = 0x4000000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $b, %esi
movl $67108864, %edx # imm = 0x4000000
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9mm_kernelPfS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $c, %edi
movl $67108864, %edx # imm = 0x4000000
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mm_kernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type a,@object # @a
.bss
.globl a
.p2align 4, 0x0
a:
.zero 67108864
.size a, 67108864
.type b,@object # @b
.globl b
.p2align 4, 0x0
b:
.zero 67108864
.size b, 67108864
.type c,@object # @c
.globl c
.p2align 4, 0x0
c:
.zero 67108864
.size c, 67108864
.type _Z9mm_kernelPfS_S_,@object # @_Z9mm_kernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z9mm_kernelPfS_S_
.p2align 3, 0x0
_Z9mm_kernelPfS_S_:
.quad _Z24__device_stub__mm_kernelPfS_S_
.size _Z9mm_kernelPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "time : %f\n"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9mm_kernelPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mm_kernelPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym a
.addrsig_sym b
.addrsig_sym c
.addrsig_sym _Z9mm_kernelPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9mm_kernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0xfff, PT ; /* 0x00000fff0000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R9, 0xfff, P0 ; /* 0x00000fff0900780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ SHF.L.U32 R9, R9, 0xc, RZ ; /* 0x0000000c09097819 */
/* 0x000fe200000006ff */
/*00b0*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*00f0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0100*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0110*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe40007ffe0ff */
/*0120*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0130*/ IMAD.WIDE R14, R9, 0x4, R4 ; /* 0x00000004090e7825 */
/* 0x000fe200078e0204 */
/*0140*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fc60008000f00 */
/*0150*/ IMAD.WIDE R2, R11, 0x4, R4 ; /* 0x000000040b027825 */
/* 0x000fe400078e0204 */
/*0160*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000a4000c1e1900 */
/*0170*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe400078e0206 */
/*0180*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ee8000c1e1900 */
/*0190*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R27, [R6.64+0x4000] ; /* 0x00400004061b7981 */
/* 0x000ee8000c1e1900 */
/*01b0*/ LDG.E R16, [R2.64+0x4] ; /* 0x0000040402107981 */
/* 0x000f28000c1e1900 */
/*01c0*/ LDG.E R19, [R6.64+0x8000] ; /* 0x0080000406137981 */
/* 0x000f28000c1e1900 */
/*01d0*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080402177981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R20, [R6.64+0xc000] ; /* 0x00c0000406147981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R22, [R2.64+0xc] ; /* 0x00000c0402167981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R25, [R6.64+0x10000] ; /* 0x0100000406197981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R18, [R2.64+0x10] ; /* 0x0000100402127981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R21, [R6.64+0x14000] ; /* 0x0140000406157981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R10, [R2.64+0x14] ; /* 0x00001404020a7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R13, [R6.64+0x18000] ; /* 0x01800004060d7981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R15, [R6.64+0x1c000] ; /* 0x01c00004060f7981 */
/* 0x001f68000c1e1900 */
/*0260*/ LDG.E R26, [R6.64+0x3c000] ; /* 0x03c00004061a7981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R29, [R2.64+0x38] ; /* 0x00003804021d7981 */
/* 0x000f62000c1e1900 */
/*0280*/ FFMA R14, R17, R14, R12 ; /* 0x0000000e110e7223 */
/* 0x004fc6000000000c */
/*0290*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ FFMA R24, R27, R24, R14 ; /* 0x000000181b187223 */
/* 0x008fc6000000000e */
/*02b0*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R17, [R6.64+0x20000] ; /* 0x0200000406117981 */
/* 0x000ee2000c1e1900 */
/*02d0*/ FFMA R24, R19, R16, R24 ; /* 0x0000001013187223 */
/* 0x010fc60000000018 */
/*02e0*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000f28000c1e1900 */
/*02f0*/ LDG.E R19, [R6.64+0x24000] ; /* 0x0240000406137981 */
/* 0x000f22000c1e1900 */
/*0300*/ FFMA R24, R20, R23, R24 ; /* 0x0000001714187223 */
/* 0x020fc60000000018 */
/*0310*/ LDG.E R23, [R2.64+0x24] ; /* 0x0000240402177981 */
/* 0x000f68000c1e1900 */
/*0320*/ LDG.E R20, [R6.64+0x28000] ; /* 0x0280000406147981 */
/* 0x000f62000c1e1900 */
/*0330*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x000fc60000000018 */
/*0340*/ LDG.E R25, [R2.64+0x28] ; /* 0x0000280402197981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R22, [R6.64+0x2c000] ; /* 0x02c0000406167981 */
/* 0x000f62000c1e1900 */
/*0360*/ FFMA R24, R21, R18, R24 ; /* 0x0000001215187223 */
/* 0x000fc60000000018 */
/*0370*/ LDG.E R21, [R2.64+0x2c] ; /* 0x00002c0402157981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R18, [R6.64+0x30000] ; /* 0x0300000406127981 */
/* 0x000f62000c1e1900 */
/*0390*/ FFMA R28, R13, R10, R24 ; /* 0x0000000a0d1c7223 */
/* 0x000fc60000000018 */
/*03a0*/ LDG.E R24, [R2.64+0x30] ; /* 0x0000300402187981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R13, [R6.64+0x34000] ; /* 0x03400004060d7981 */
/* 0x000f68000c1e1900 */
/*03c0*/ LDG.E R10, [R6.64+0x38000] ; /* 0x03800004060a7981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R27, [R2.64+0x34] ; /* 0x00003404021b7981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fc80007ffe0ff */
/*03f0*/ ISETP.NE.AND P0, PT, R8, 0x1000, PT ; /* 0x000010000800780c */
/* 0x000fe20003f05270 */
/*0400*/ UIADD3 UR6, UP0, UR6, 0x40000, URZ ; /* 0x0004000006067890 */
/* 0x000fe2000ff1e03f */
/*0410*/ IADD3 R4, P1, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x000fc60007f3e0ff */
/*0420*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0430*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0440*/ FFMA R12, R15, R12, R28 ; /* 0x0000000c0f0c7223 */
/* 0x004fc8000000001c */
/*0450*/ FFMA R12, R17, R14, R12 ; /* 0x0000000e110c7223 */
/* 0x008fc8000000000c */
/*0460*/ FFMA R12, R19, R16, R12 ; /* 0x00000010130c7223 */
/* 0x010fc8000000000c */
/*0470*/ FFMA R12, R20, R23, R12 ; /* 0x00000017140c7223 */
/* 0x020fc8000000000c */
/*0480*/ FFMA R12, R22, R25, R12 ; /* 0x00000019160c7223 */
/* 0x000fc8000000000c */
/*0490*/ FFMA R12, R18, R21, R12 ; /* 0x00000015120c7223 */
/* 0x000fc8000000000c */
/*04a0*/ FFMA R12, R13, R24, R12 ; /* 0x000000180d0c7223 */
/* 0x000fc8000000000c */
/*04b0*/ FFMA R12, R10, R27, R12 ; /* 0x0000001b0a0c7223 */
/* 0x000fc8000000000c */
/*04c0*/ FFMA R12, R26, R29, R12 ; /* 0x0000001d1a0c7223 */
/* 0x000fe2000000000c */
/*04d0*/ @P0 BRA 0x120 ; /* 0xfffffc4000000947 */
/* 0x000fea000383ffff */
/*04e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*04f0*/ IADD3 R2, R0, R9, RZ ; /* 0x0000000900027210 */
/* 0x000fd20007ffe0ff */
/*0500*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0510*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101904 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mm_kernelPfS_S_
.globl _Z9mm_kernelPfS_S_
.p2align 8
.type _Z9mm_kernelPfS_S_,@function
_Z9mm_kernelPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x1000, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 12, v1
v_mov_b32_e32 v4, 0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v2, v0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v7, vcc_lo, v5, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, 0x1000, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x4000
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v3, v7
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v1, 12, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mm_kernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mm_kernelPfS_S_, .Lfunc_end0-_Z9mm_kernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mm_kernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mm_kernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b790c_00000000-6_mm_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_
.type _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_, @function
_Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9mm_kernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_, .-_Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_
.globl _Z9mm_kernelPfS_S_
.type _Z9mm_kernelPfS_S_, @function
_Z9mm_kernelPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9mm_kernelPfS_S_, .-_Z9mm_kernelPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "time : %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq a(%rip), %rbp
leaq b(%rip), %r12
leaq 67108864(%rbp), %r13
.L12:
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq $16384, %rbx
jne .L13
addq $16384, %rbp
addq $16384, %r12
cmpq %r13, %rbp
jne .L12
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $67108864, %edx
leaq a(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
leaq b(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 48(%rsp)
movl $128, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movl $67108864, %edx
movq 40(%rsp), %rsi
leaq c(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z9mm_kernelPfS_S_PfS_S_
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9mm_kernelPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mm_kernelPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl c
.bss
.align 32
.type c, @object
.size c, 67108864
c:
.zero 67108864
.globl b
.align 32
.type b, @object
.size b, 67108864
b:
.zero 67108864
.globl a
.align 32
.type a, @object
.size a, 67108864
a:
.zero 67108864
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mm_1.hip"
.globl _Z24__device_stub__mm_kernelPfS_S_ # -- Begin function _Z24__device_stub__mm_kernelPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__mm_kernelPfS_S_,@function
_Z24__device_stub__mm_kernelPfS_S_: # @_Z24__device_stub__mm_kernelPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mm_kernelPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__mm_kernelPfS_S_, .Lfunc_end0-_Z24__device_stub__mm_kernelPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movq $-16384, %r15 # imm = 0xC000
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, a+16384(%rbx,%r15)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, b+16384(%rbx,%r15)
addq $4, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r14
addq $16384, %rbx # imm = 0x4000
cmpq $4096, %r14 # imm = 0x1000
jne .LBB1_1
# %bb.4:
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 24(%rsp), %rdi
movl $a, %esi
movl $67108864, %edx # imm = 0x4000000
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $b, %esi
movl $67108864, %edx # imm = 0x4000000
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9mm_kernelPfS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $c, %edi
movl $67108864, %edx # imm = 0x4000000
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mm_kernelPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type a,@object # @a
.bss
.globl a
.p2align 4, 0x0
a:
.zero 67108864
.size a, 67108864
.type b,@object # @b
.globl b
.p2align 4, 0x0
b:
.zero 67108864
.size b, 67108864
.type c,@object # @c
.globl c
.p2align 4, 0x0
c:
.zero 67108864
.size c, 67108864
.type _Z9mm_kernelPfS_S_,@object # @_Z9mm_kernelPfS_S_
.section .rodata,"a",@progbits
.globl _Z9mm_kernelPfS_S_
.p2align 3, 0x0
_Z9mm_kernelPfS_S_:
.quad _Z24__device_stub__mm_kernelPfS_S_
.size _Z9mm_kernelPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "time : %f\n"
.size .L.str, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9mm_kernelPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mm_kernelPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym a
.addrsig_sym b
.addrsig_sym c
.addrsig_sym _Z9mm_kernelPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Author: Rajiur Rahman ( rajiurrahman.bd@gmail.com )
// Department of Computer Science, Wayne State University
// knn implemented for GPU.
// have to provide training data, trianing data label, test data, test data label in separate text files. All the files should be ' ' space separated.
/* Instruction for compiling and running
* the commands should be following
* compile - nvcc knn.cu -o knn.o
* run - ./knn.o numTrainRow numTestRow numCol k
*
* For example:
* ./knn.o 20 5 10 4
* ./knn.o 15997 4000 30000 5
* ./knn_new.o 69 20 1000 5
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h> /* strtok() */
#include <sys/types.h> /* open() */
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h> /* read(), close() */
#include <math.h>
#include <time.h>
/*__global__ void kernel(int *a)
{
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
int tidy = threadIdx.y + blockIdx.y * blockDim.y;
}*/
__device__ void showData(float* data, int numRow, int numCol, int tidx){
for(int i =tidx*numCol; i<((tidx*numCol)+numCol); i++){
printf("%d-%f\t", i, data[i]);
}
}
// this function calculates the distance between two rows.
__device__ float calculate_distance(float* d_trainData, float* d_testData, int numTrainRow, int numTestRow, int numCol, int currentTestIndex, int currentTrainIndex){
float distance = (float) 100.0;
for (int i = 0; i<numCol; i++){
distance += ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] ) * ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] );
}
//distance = distance/(float)numCol;
//distance = (float)sqrt(distance);
return distance;
}
// this function will return nearest neighbor information for a particular test row.
// called from main kernel // d_neighborhoodMatrix has size numTestRow*numTrainRow .. it is a flat array
__device__ float* calculate_distance_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol, int tidx){
//printf("Dealing with test data row %d\n", tidx);
for(int i=0; i<numTrainRow; i++){
//distance form rows testData[tidx] <--> trainData[i]
d_neighborhoodMatrix[tidx*numTrainRow+i] = calculate_distance(d_trainData, d_testData, numTrainRow, numTestRow, numCol, tidx, i);
}
return d_neighborhoodMatrix;
}
// kernel function that will perform k-nearest neighbor classification
// There will be one karnel launched for each row in the test data.
// This function will manage finding nearest neighbors from test data row to training data
__global__ void calculate_similarity_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("Inside Kernel %d\n", tidx);
//showData(d_testData, numTestRow, numCol, tidx);
//call function for calculating the nearest neighbor of tidx'th row of test data
d_neighborhoodMatrix = calculate_distance_matrix(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol, tidx);
}
// this funciton will read the data. It takes parameters file name as string, number of rows and columns.
// It will read a 2-d matrix and save as a flat 1-D array and return the pointer
float* read_data(char* fileName, int numRow, int numCol){
float* data;
data = (float*)malloc(numRow*numCol*sizeof(float));
FILE *file;
file=fopen(fileName, "r");
for (int i=0; i<numRow*numCol; i++){
if (!fscanf(file, "%f", &data[i])){
break;
}
//printf("%d-%f\n",i, data[i]);
}
fclose(file);
return data;
}
void show_data(float* data, int numRow, int numCol){
/*printf("numrow-%d numcol-%d\n\n", numRow, numCol);
for(int i =0; i<numRow*numCol; i++){
printf("%d-%f\t", i, data[i]);
}*/
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%f ",data[i*numCol+j]);
}
printf("\n");
}
}
//comment
__device__ int calculate_nearest_neighbor_index(float* d_neighborhoodMatrix, int tidx, int numTrainRow){
float minValue = 99999.0;
int minIndex = 0;
for (int i=(tidx*numTrainRow); i< (tidx*numTrainRow)+numTrainRow; i++){
if (d_neighborhoodMatrix[i] <= minValue ){
minValue = d_neighborhoodMatrix[i];
minIndex = i-(tidx*numTrainRow);
}
}
return minIndex;
}
// this function will calculate the nearest neighbors from similarity matrix
// a kernel will be launched for each test instance
__global__ void calculate_nearest_neighbor(float* d_neighborhoodMatrix, int* d_nearestNeighborIndices, int numTrainRow, int numTestRow, int numCol, int k){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
for(int i=0; i<k; i++){
int minIndex = calculate_nearest_neighbor_index(d_neighborhoodMatrix, tidx, numTrainRow);
d_nearestNeighborIndices[tidx*k+i] = minIndex;
d_neighborhoodMatrix[tidx*numTrainRow+minIndex] = (float)99999.0;
}
}
//calculate the label of a test instance
float calculate_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k, int currentInstance){
float label = (float)0.0;
float sum1 = (float)0.0;
int currentIndex = 0;
for(int i=0; i<k; i++){
currentIndex = host_nearestNeighborIndices[currentInstance*k + i];
//printf("%d - %f\n", currentIndex, trainLabel[currentIndex]);
sum1 += trainLabel[currentIndex];
//printf("currentIndex -%d, valueIndex-%f\n",currentIndex, trainLabel[currentIndex]);
}
printf("\n");
//printf("nstance-%d sum-%f\n", currentInstance, sum1);
if(sum1 >= (k/2) ){
label = (float)1.0;
}
return label;
}
//predict class labels of test data from calculated nearest neighbors
float* predict_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k){
float* predictedLabel;
predictedLabel = (float*)malloc( numTestRow*sizeof(float) );
for(int i=0; i<numTestRow; i++){
predictedLabel[i] = calculate_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k, i);
//printf("label prediction of instance %d\n", i);
}
return predictedLabel;
}
//calculate accuracy of prediction from original class labels and predicted labels
float calculate_accuracy(float* predictedLabel, float* testLabel, int numTestRow){
int correctPredictionCount = 0;
for(int i=0; i<numTestRow; i++ ){
//printf("original %f \t predicted %f\n", testLabel[i], predictedLabel[i]);
if(predictedLabel[i] == testLabel[i]){
correctPredictionCount ++;
}
}
//printf("\n\n");
return (float)100*((float)correctPredictionCount/(float)numTestRow);
}
void show_data_int(int* data, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
void show_data_nearest_neighbor_labels(int* data, float* trainLabel, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
int main(int argc, char* argv[])
{
//start the timer
clock_t begin_time = clock();
// first, catch the arguments from command line
int numTrainRow = atoi(argv[1]);
int numTestRow = atoi(argv[2]);
int numCol = atoi(argv[3]);
int k = atoi(argv[4]);
printf("\n**************** Hello World ! ******************\n");
// read the data files
float* trainData, *testData, *trainLabel, *trainLabel_1, *testLabel, *predictedLabel;
trainData = read_data("train.txt", numTrainRow, numCol);
testData = read_data("test.txt", numTestRow, numCol);
trainLabel = read_data("label_train.txt", numTrainRow, 1);
testLabel = read_data("label_test.txt", numTestRow, 1);
//trainData = read_data("vec_1k_train.txt", numTrainRow, numCol);
//testData = read_data("vec_1k_test.txt", numTestRow, numCol);
//trainLabel = read_data("label_1k_train.txt", numTrainRow, 1);
//testLabel = read_data("label_1k_test.txt", numTestRow, 1);
printf("Data Read Complete\n");
//show_data(testData, numTestRow, numCol);
//printf("\n\n\n");
//show_data(trainLabel, numTrainRow, 1);
//printf("\n\n\n");
// allocate memory and copy read files to device (GPU) memory from host (CPU) memory
float *d_trainData, *d_testData, *d_neighborhoodMatrix, *host_neighborhoodMatrix; //neighborhood matrix will have numTestRow rows and numTrainRow columns
int *d_nearestNeighborIndices, *host_nearestNeighborIndices; //it has numTestRow rows and k columns
const size_t trainSize = sizeof(float) * size_t(numTrainRow*numCol);
const size_t testSize = sizeof(float) * size_t(numTestRow*numCol);
const size_t neighborhoodMatrixSize = sizeof(float)*size_t(numTestRow*numTrainRow);
cudaMalloc((void **)&d_trainData, trainSize);
cudaMemcpy(d_trainData, trainData, trainSize, cudaMemcpyHostToDevice);
cudaMalloc((void **)&d_testData, testSize);
cudaMemcpy(d_testData, testData, testSize, cudaMemcpyHostToDevice);
cudaMalloc((void **)&d_neighborhoodMatrix, neighborhoodMatrixSize);
cudaMalloc((void **)&d_nearestNeighborIndices, (numTestRow*k*sizeof(int)) );
calculate_similarity_matrix<<<1,numTestRow>>>(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol);
cudaFree(d_trainData);
cudaFree(d_testData);
printf("Similarity matrix building complete\n");
// copy nearest neighbor matrix from device to CPU and print to view it
host_neighborhoodMatrix = (float*)malloc(neighborhoodMatrixSize);
cudaMemcpy(host_neighborhoodMatrix, d_neighborhoodMatrix, neighborhoodMatrixSize, cudaMemcpyDeviceToHost);
printf("\ncopying similarity matrix from device to host complete\n" );
//printf("\n\nSimilarity matrix\n");
show_data(host_neighborhoodMatrix, numTestRow, numTrainRow);
calculate_nearest_neighbor<<<1,numTestRow>>>(d_neighborhoodMatrix, d_nearestNeighborIndices, numTrainRow, numTestRow, numCol, k);
printf("Nearest Neighbour calculation complete\n");
// copy nearest neighbour indices from device (GPU) to host (CPU)
host_nearestNeighborIndices = (int*)malloc(numTestRow*k*sizeof(int));
cudaMemcpy(host_nearestNeighborIndices, d_nearestNeighborIndices, (numTestRow*k*sizeof(int)), cudaMemcpyDeviceToHost);
//printf("\nCopying nearest neighbour indices from device to host complete\n");
//printf("indices of nearest neighbour\n");
//show_data_int(host_nearestNeighborIndices, numTestRow, k);
predictedLabel = predict_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k);
printf("\nClass label prediction complete\n");
//show_data(predictedLabel, numTestRow, 1);
float acc = calculate_accuracy(predictedLabel, testLabel, numTestRow);
printf("\nPrediction Accuracy: %f", acc);
//take the end time and print time taken for running the program
clock_t end_tiem = clock();
double diff_time = (end_tiem - begin_time) / CLOCKS_PER_SEC;
printf("\n\nTime taken for running the program: %lf\n\n", diff_time);
free(testData);
free(trainData);
free(host_nearestNeighborIndices);
free(host_neighborhoodMatrix);
cudaFree(d_neighborhoodMatrix);
return 0;
} | .file "tmpxft_00191705_00000000-6_knn_new.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8showDataPfiii
.type _Z8showDataPfiii, @function
_Z8showDataPfiii:
.LFB2074:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2074:
.size _Z8showDataPfiii, .-_Z8showDataPfiii
.globl _Z18calculate_distancePfS_iiiii
.type _Z18calculate_distancePfS_iiiii, @function
_Z18calculate_distancePfS_iiiii:
.LFB2075:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2075:
.size _Z18calculate_distancePfS_iiiii, .-_Z18calculate_distancePfS_iiiii
.globl _Z25calculate_distance_matrixPfS_S_iiii
.type _Z25calculate_distance_matrixPfS_S_iiii, @function
_Z25calculate_distance_matrixPfS_S_iiii:
.LFB2076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2076:
.size _Z25calculate_distance_matrixPfS_S_iiii, .-_Z25calculate_distance_matrixPfS_S_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%f"
.text
.globl _Z9read_dataPcii
.type _Z9read_dataPcii, @function
_Z9read_dataPcii:
.LFB2077:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
imull %edx, %esi
movl %esi, %ebx
movslq %esi, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L10
movq %r13, %rbx
addq %r13, %rbp
leaq .LC1(%rip), %r14
.L11:
movq %rbx, %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
testl %eax, %eax
je .L10
addq $4, %rbx
cmpq %rbp, %rbx
jne .L11
.L10:
movq %r12, %rdi
call fclose@PLT
movq %r13, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _Z9read_dataPcii, .-_Z9read_dataPcii
.section .rodata.str1.1
.LC2:
.string "%f "
.LC3:
.string "\n"
.text
.globl _Z9show_dataPfii
.type _Z9show_dataPfii, @function
_Z9show_dataPfii:
.LFB2078:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L14
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC2(%rip), %r12
jmp .L16
.L18:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
.L19:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L14
.L16:
testl %r15d, %r15d
jg .L18
jmp .L19
.L14:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _Z9show_dataPfii, .-_Z9show_dataPfii
.globl _Z32calculate_nearest_neighbor_indexPfii
.type _Z32calculate_nearest_neighbor_indexPfii, @function
_Z32calculate_nearest_neighbor_indexPfii:
.LFB2079:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2079:
.size _Z32calculate_nearest_neighbor_indexPfii, .-_Z32calculate_nearest_neighbor_indexPfii
.globl _Z15calculate_labelPiPfiiii
.type _Z15calculate_labelPiPfiiii, @function
_Z15calculate_labelPiPfiiii:
.LFB2080:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movl %r8d, %ebx
testl %r8d, %r8d
jle .L28
imull %r8d, %r9d
movslq %r9d, %rdx
leaq (%rdi,%rdx,4), %rax
movslq %r8d, %rcx
addq %rcx, %rdx
leaq (%rdi,%rdx,4), %rcx
movl $0x00000000, 12(%rsp)
.L26:
movslq (%rax), %rdx
movss 12(%rsp), %xmm2
addss (%rsi,%rdx,4), %xmm2
movss %xmm2, 12(%rsp)
addq $4, %rax
cmpq %rcx, %rax
jne .L26
.L25:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
movss .LC5(%rip), %xmm0
cmpless 12(%rsp), %xmm1
andps %xmm1, %xmm0
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $0x00000000, 12(%rsp)
jmp .L25
.cfi_endproc
.LFE2080:
.size _Z15calculate_labelPiPfiiii, .-_Z15calculate_labelPiPfiiii
.globl _Z13predict_labelPiPfiii
.type _Z13predict_labelPiPfiii, @function
_Z13predict_labelPiPfiii:
.LFB2081:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movl %edx, %ebp
movl %ecx, %r13d
movl %r8d, %r14d
movslq %edx, %r15
leaq 0(,%r15,4), %rdi
call malloc@PLT
movq %rax, %r12
testl %ebp, %ebp
jle .L32
movl $0, %ebx
.L34:
movl %ebx, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z15calculate_labelPiPfiiii
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r15
jne .L34
.L32:
movq %r12, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _Z13predict_labelPiPfiii, .-_Z13predict_labelPiPfiii
.globl _Z18calculate_accuracyPfS_i
.type _Z18calculate_accuracyPfS_i, @function
_Z18calculate_accuracyPfS_i:
.LFB2082:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L42
movslq %edx, %rcx
salq $2, %rcx
movl $0, %eax
movl $0, %r8d
jmp .L41
.L39:
addq $4, %rax
cmpq %rcx, %rax
je .L38
.L41:
movss (%rdi,%rax), %xmm0
ucomiss (%rsi,%rax), %xmm0
jp .L39
jne .L39
addl $1, %r8d
jmp .L39
.L42:
movl $0, %r8d
.L38:
pxor %xmm0, %xmm0
cvtsi2ssl %r8d, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
divss %xmm1, %xmm0
mulss .LC6(%rip), %xmm0
ret
.cfi_endproc
.LFE2082:
.size _Z18calculate_accuracyPfS_i, .-_Z18calculate_accuracyPfS_i
.section .rodata.str1.1
.LC7:
.string "%d "
.text
.globl _Z13show_data_intPiii
.type _Z13show_data_intPiii, @function
_Z13show_data_intPiii:
.LFB2083:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L45
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC7(%rip), %r12
jmp .L47
.L49:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %rbp
.L48:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L48
.L50:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L45
.L47:
testl %r15d, %r15d
jg .L49
jmp .L50
.L45:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13show_data_intPiii, .-_Z13show_data_intPiii
.globl _Z33show_data_nearest_neighbor_labelsPiPfii
.type _Z33show_data_nearest_neighbor_labelsPiPfii, @function
_Z33show_data_nearest_neighbor_labelsPiPfii:
.LFB2084:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %edx, 12(%rsp)
testl %edx, %edx
jle .L53
movl %ecx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %ecx, %rax
movq %rax, 24(%rsp)
leaq .LC7(%rip), %r12
jmp .L55
.L57:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rsi
addq %rsi, %rax
leaq (%rcx,%rax,4), %rbp
.L56:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L56
.L58:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L53
.L55:
testl %r15d, %r15d
jg .L57
jmp .L58
.L53:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z33show_data_nearest_neighbor_labelsPiPfii, .-_Z33show_data_nearest_neighbor_labelsPiPfii
.globl _Z54__device_stub__Z27calculate_similarity_matrixPfS_S_iiiPfS_S_iii
.type _Z54__device_stub__Z27calculate_similarity_matrixPfS_S_iiiPfS_S_iii, @function
_Z54__device_stub__Z27calculate_similarity_matrixPfS_S_iiiPfS_S_iii:
.LFB2110:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L65
.L61:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L66
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27calculate_similarity_matrixPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L61
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2110:
.size _Z54__device_stub__Z27calculate_similarity_matrixPfS_S_iiiPfS_S_iii, .-_Z54__device_stub__Z27calculate_similarity_matrixPfS_S_iiiPfS_S_iii
.globl _Z27calculate_similarity_matrixPfS_S_iii
.type _Z27calculate_similarity_matrixPfS_S_iii, @function
_Z27calculate_similarity_matrixPfS_S_iii:
.LFB2111:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z27calculate_similarity_matrixPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2111:
.size _Z27calculate_similarity_matrixPfS_S_iii, .-_Z27calculate_similarity_matrixPfS_S_iii
.globl _Z52__device_stub__Z26calculate_nearest_neighborPfPiiiiiPfPiiiii
.type _Z52__device_stub__Z26calculate_nearest_neighborPfPiiiiiPfPiiiii, @function
_Z52__device_stub__Z26calculate_nearest_neighborPfPiiiiiPfPiiiii:
.LFB2112:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L73
.L69:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26calculate_nearest_neighborPfPiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L69
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2112:
.size _Z52__device_stub__Z26calculate_nearest_neighborPfPiiiiiPfPiiiii, .-_Z52__device_stub__Z26calculate_nearest_neighborPfPiiiiiPfPiiiii
.globl _Z26calculate_nearest_neighborPfPiiiii
.type _Z26calculate_nearest_neighborPfPiiiii, @function
_Z26calculate_nearest_neighborPfPiiiii:
.LFB2113:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26calculate_nearest_neighborPfPiiiiiPfPiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2113:
.size _Z26calculate_nearest_neighborPfPiiiii, .-_Z26calculate_nearest_neighborPfPiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "\n**************** Hello World ! ******************\n"
.section .rodata.str1.1
.LC9:
.string "train.txt"
.LC10:
.string "test.txt"
.LC11:
.string "label_train.txt"
.LC12:
.string "label_test.txt"
.LC13:
.string "Data Read Complete\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Similarity matrix building complete\n"
.align 8
.LC15:
.string "\ncopying similarity matrix from device to host complete\n"
.align 8
.LC16:
.string "Nearest Neighbour calculation complete\n"
.align 8
.LC17:
.string "\nClass label prediction complete\n"
.section .rodata.str1.1
.LC18:
.string "\nPrediction Accuracy: %f"
.section .rodata.str1.8
.align 8
.LC19:
.string "\n\nTime taken for running the program: %lf\n\n"
.text
.globl main
.type main, @function
main:
.LFB2085:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, 40(%rsp)
movq 8(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r15d
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 32(%rsp)
movl %eax, %r13d
movq 32(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 8(%rsp)
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edx
movl %ebx, %esi
leaq .LC9(%rip), %rdi
call _Z9read_dataPcii
movq %rax, 16(%rsp)
movl %r13d, %edx
movl %ebp, %esi
leaq .LC10(%rip), %rdi
call _Z9read_dataPcii
movq %rax, 24(%rsp)
movl $1, %edx
movl %ebx, %esi
leaq .LC11(%rip), %rdi
call _Z9read_dataPcii
movq %rax, 48(%rsp)
movl $1, %edx
movl %ebp, %esi
leaq .LC12(%rip), %rdi
call _Z9read_dataPcii
movq %rax, 56(%rsp)
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rcx
movl %ecx, %r13d
imull %ebx, %r13d
movslq %r13d, %r13
salq $2, %r13
movl %ecx, %r12d
imull %ebp, %r12d
movslq %r12d, %r12
salq $2, %r12
imull %ebp, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
leaq 72(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl 8(%rsp), %eax
imull %ebp, %eax
cltq
leaq 0(,%rax,4), %r13
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %ebp, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L78:
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edx
movl %r15d, %esi
movq %r12, %rdi
call _Z9show_dataPfii
movl %ebp, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L83
.L79:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %r13, %rdx
movq 88(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl 8(%rsp), %r8d
movl %r14d, %ecx
movl %r15d, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call _Z13predict_labelPiPfiii
movq %rax, %rbp
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call _Z18calculate_accuracyPfS_i
cvtss2sd %xmm0, %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq 40(%rsp), %rcx
subq %rcx, %rax
movq %rax, %rcx
movabsq $4835703278458516699, %rdx
imulq %rdx
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L84
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
movl 32(%rsp), %r9d
movl %ebp, %r8d
movl %r14d, %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z54__device_stub__Z27calculate_similarity_matrixPfS_S_iiiPfS_S_iii
jmp .L78
.L83:
movl 8(%rsp), %r9d
movl 32(%rsp), %r8d
movl %r15d, %ecx
movl %r14d, %edx
movq 88(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z52__device_stub__Z26calculate_nearest_neighborPfPiiiiiPfPiiiii
jmp .L79
.L84:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC20:
.string "_Z26calculate_nearest_neighborPfPiiiii"
.align 8
.LC21:
.string "_Z27calculate_similarity_matrixPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2115:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z26calculate_nearest_neighborPfPiiiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z27calculate_similarity_matrixPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2115:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1065353216
.align 4
.LC6:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Author: Rajiur Rahman ( rajiurrahman.bd@gmail.com )
// Department of Computer Science, Wayne State University
// knn implemented for GPU.
// have to provide training data, trianing data label, test data, test data label in separate text files. All the files should be ' ' space separated.
/* Instruction for compiling and running
* the commands should be following
* compile - nvcc knn.cu -o knn.o
* run - ./knn.o numTrainRow numTestRow numCol k
*
* For example:
* ./knn.o 20 5 10 4
* ./knn.o 15997 4000 30000 5
* ./knn_new.o 69 20 1000 5
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h> /* strtok() */
#include <sys/types.h> /* open() */
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h> /* read(), close() */
#include <math.h>
#include <time.h>
/*__global__ void kernel(int *a)
{
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
int tidy = threadIdx.y + blockIdx.y * blockDim.y;
}*/
__device__ void showData(float* data, int numRow, int numCol, int tidx){
for(int i =tidx*numCol; i<((tidx*numCol)+numCol); i++){
printf("%d-%f\t", i, data[i]);
}
}
// this function calculates the distance between two rows.
__device__ float calculate_distance(float* d_trainData, float* d_testData, int numTrainRow, int numTestRow, int numCol, int currentTestIndex, int currentTrainIndex){
float distance = (float) 100.0;
for (int i = 0; i<numCol; i++){
distance += ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] ) * ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] );
}
//distance = distance/(float)numCol;
//distance = (float)sqrt(distance);
return distance;
}
// this function will return nearest neighbor information for a particular test row.
// called from main kernel // d_neighborhoodMatrix has size numTestRow*numTrainRow .. it is a flat array
__device__ float* calculate_distance_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol, int tidx){
//printf("Dealing with test data row %d\n", tidx);
for(int i=0; i<numTrainRow; i++){
//distance form rows testData[tidx] <--> trainData[i]
d_neighborhoodMatrix[tidx*numTrainRow+i] = calculate_distance(d_trainData, d_testData, numTrainRow, numTestRow, numCol, tidx, i);
}
return d_neighborhoodMatrix;
}
// kernel function that will perform k-nearest neighbor classification
// There will be one karnel launched for each row in the test data.
// This function will manage finding nearest neighbors from test data row to training data
__global__ void calculate_similarity_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("Inside Kernel %d\n", tidx);
//showData(d_testData, numTestRow, numCol, tidx);
//call function for calculating the nearest neighbor of tidx'th row of test data
d_neighborhoodMatrix = calculate_distance_matrix(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol, tidx);
}
// this funciton will read the data. It takes parameters file name as string, number of rows and columns.
// It will read a 2-d matrix and save as a flat 1-D array and return the pointer
float* read_data(char* fileName, int numRow, int numCol){
float* data;
data = (float*)malloc(numRow*numCol*sizeof(float));
FILE *file;
file=fopen(fileName, "r");
for (int i=0; i<numRow*numCol; i++){
if (!fscanf(file, "%f", &data[i])){
break;
}
//printf("%d-%f\n",i, data[i]);
}
fclose(file);
return data;
}
void show_data(float* data, int numRow, int numCol){
/*printf("numrow-%d numcol-%d\n\n", numRow, numCol);
for(int i =0; i<numRow*numCol; i++){
printf("%d-%f\t", i, data[i]);
}*/
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%f ",data[i*numCol+j]);
}
printf("\n");
}
}
//comment
__device__ int calculate_nearest_neighbor_index(float* d_neighborhoodMatrix, int tidx, int numTrainRow){
float minValue = 99999.0;
int minIndex = 0;
for (int i=(tidx*numTrainRow); i< (tidx*numTrainRow)+numTrainRow; i++){
if (d_neighborhoodMatrix[i] <= minValue ){
minValue = d_neighborhoodMatrix[i];
minIndex = i-(tidx*numTrainRow);
}
}
return minIndex;
}
// this function will calculate the nearest neighbors from similarity matrix
// a kernel will be launched for each test instance
__global__ void calculate_nearest_neighbor(float* d_neighborhoodMatrix, int* d_nearestNeighborIndices, int numTrainRow, int numTestRow, int numCol, int k){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
for(int i=0; i<k; i++){
int minIndex = calculate_nearest_neighbor_index(d_neighborhoodMatrix, tidx, numTrainRow);
d_nearestNeighborIndices[tidx*k+i] = minIndex;
d_neighborhoodMatrix[tidx*numTrainRow+minIndex] = (float)99999.0;
}
}
//calculate the label of a test instance
float calculate_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k, int currentInstance){
float label = (float)0.0;
float sum1 = (float)0.0;
int currentIndex = 0;
for(int i=0; i<k; i++){
currentIndex = host_nearestNeighborIndices[currentInstance*k + i];
//printf("%d - %f\n", currentIndex, trainLabel[currentIndex]);
sum1 += trainLabel[currentIndex];
//printf("currentIndex -%d, valueIndex-%f\n",currentIndex, trainLabel[currentIndex]);
}
printf("\n");
//printf("nstance-%d sum-%f\n", currentInstance, sum1);
if(sum1 >= (k/2) ){
label = (float)1.0;
}
return label;
}
//predict class labels of test data from calculated nearest neighbors
float* predict_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k){
float* predictedLabel;
predictedLabel = (float*)malloc( numTestRow*sizeof(float) );
for(int i=0; i<numTestRow; i++){
predictedLabel[i] = calculate_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k, i);
//printf("label prediction of instance %d\n", i);
}
return predictedLabel;
}
//calculate accuracy of prediction from original class labels and predicted labels
float calculate_accuracy(float* predictedLabel, float* testLabel, int numTestRow){
int correctPredictionCount = 0;
for(int i=0; i<numTestRow; i++ ){
//printf("original %f \t predicted %f\n", testLabel[i], predictedLabel[i]);
if(predictedLabel[i] == testLabel[i]){
correctPredictionCount ++;
}
}
//printf("\n\n");
return (float)100*((float)correctPredictionCount/(float)numTestRow);
}
void show_data_int(int* data, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
void show_data_nearest_neighbor_labels(int* data, float* trainLabel, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
int main(int argc, char* argv[])
{
//start the timer
clock_t begin_time = clock();
// first, catch the arguments from command line
int numTrainRow = atoi(argv[1]);
int numTestRow = atoi(argv[2]);
int numCol = atoi(argv[3]);
int k = atoi(argv[4]);
printf("\n**************** Hello World ! ******************\n");
// read the data files
float* trainData, *testData, *trainLabel, *trainLabel_1, *testLabel, *predictedLabel;
trainData = read_data("train.txt", numTrainRow, numCol);
testData = read_data("test.txt", numTestRow, numCol);
trainLabel = read_data("label_train.txt", numTrainRow, 1);
testLabel = read_data("label_test.txt", numTestRow, 1);
//trainData = read_data("vec_1k_train.txt", numTrainRow, numCol);
//testData = read_data("vec_1k_test.txt", numTestRow, numCol);
//trainLabel = read_data("label_1k_train.txt", numTrainRow, 1);
//testLabel = read_data("label_1k_test.txt", numTestRow, 1);
printf("Data Read Complete\n");
//show_data(testData, numTestRow, numCol);
//printf("\n\n\n");
//show_data(trainLabel, numTrainRow, 1);
//printf("\n\n\n");
// allocate memory and copy read files to device (GPU) memory from host (CPU) memory
float *d_trainData, *d_testData, *d_neighborhoodMatrix, *host_neighborhoodMatrix; //neighborhood matrix will have numTestRow rows and numTrainRow columns
int *d_nearestNeighborIndices, *host_nearestNeighborIndices; //it has numTestRow rows and k columns
const size_t trainSize = sizeof(float) * size_t(numTrainRow*numCol);
const size_t testSize = sizeof(float) * size_t(numTestRow*numCol);
const size_t neighborhoodMatrixSize = sizeof(float)*size_t(numTestRow*numTrainRow);
cudaMalloc((void **)&d_trainData, trainSize);
cudaMemcpy(d_trainData, trainData, trainSize, cudaMemcpyHostToDevice);
cudaMalloc((void **)&d_testData, testSize);
cudaMemcpy(d_testData, testData, testSize, cudaMemcpyHostToDevice);
cudaMalloc((void **)&d_neighborhoodMatrix, neighborhoodMatrixSize);
cudaMalloc((void **)&d_nearestNeighborIndices, (numTestRow*k*sizeof(int)) );
calculate_similarity_matrix<<<1,numTestRow>>>(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol);
cudaFree(d_trainData);
cudaFree(d_testData);
printf("Similarity matrix building complete\n");
// copy nearest neighbor matrix from device to CPU and print to view it
host_neighborhoodMatrix = (float*)malloc(neighborhoodMatrixSize);
cudaMemcpy(host_neighborhoodMatrix, d_neighborhoodMatrix, neighborhoodMatrixSize, cudaMemcpyDeviceToHost);
printf("\ncopying similarity matrix from device to host complete\n" );
//printf("\n\nSimilarity matrix\n");
show_data(host_neighborhoodMatrix, numTestRow, numTrainRow);
calculate_nearest_neighbor<<<1,numTestRow>>>(d_neighborhoodMatrix, d_nearestNeighborIndices, numTrainRow, numTestRow, numCol, k);
printf("Nearest Neighbour calculation complete\n");
// copy nearest neighbour indices from device (GPU) to host (CPU)
host_nearestNeighborIndices = (int*)malloc(numTestRow*k*sizeof(int));
cudaMemcpy(host_nearestNeighborIndices, d_nearestNeighborIndices, (numTestRow*k*sizeof(int)), cudaMemcpyDeviceToHost);
//printf("\nCopying nearest neighbour indices from device to host complete\n");
//printf("indices of nearest neighbour\n");
//show_data_int(host_nearestNeighborIndices, numTestRow, k);
predictedLabel = predict_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k);
printf("\nClass label prediction complete\n");
//show_data(predictedLabel, numTestRow, 1);
float acc = calculate_accuracy(predictedLabel, testLabel, numTestRow);
printf("\nPrediction Accuracy: %f", acc);
//take the end time and print time taken for running the program
clock_t end_tiem = clock();
double diff_time = (end_tiem - begin_time) / CLOCKS_PER_SEC;
printf("\n\nTime taken for running the program: %lf\n\n", diff_time);
free(testData);
free(trainData);
free(host_nearestNeighborIndices);
free(host_neighborhoodMatrix);
cudaFree(d_neighborhoodMatrix);
return 0;
} | // Author: Rajiur Rahman ( rajiurrahman.bd@gmail.com )
// Department of Computer Science, Wayne State University
// knn implemented for GPU.
// have to provide training data, trianing data label, test data, test data label in separate text files. All the files should be ' ' space separated.
/* Instruction for compiling and running
* the commands should be following
* compile - nvcc knn.cu -o knn.o
* run - ./knn.o numTrainRow numTestRow numCol k
*
* For example:
* ./knn.o 20 5 10 4
* ./knn.o 15997 4000 30000 5
* ./knn_new.o 69 20 1000 5
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h> /* strtok() */
#include <sys/types.h> /* open() */
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h> /* read(), close() */
#include <math.h>
#include <time.h>
/*__global__ void kernel(int *a)
{
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
int tidy = threadIdx.y + blockIdx.y * blockDim.y;
}*/
__device__ void showData(float* data, int numRow, int numCol, int tidx){
for(int i =tidx*numCol; i<((tidx*numCol)+numCol); i++){
printf("%d-%f\t", i, data[i]);
}
}
// this function calculates the distance between two rows.
__device__ float calculate_distance(float* d_trainData, float* d_testData, int numTrainRow, int numTestRow, int numCol, int currentTestIndex, int currentTrainIndex){
float distance = (float) 100.0;
for (int i = 0; i<numCol; i++){
distance += ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] ) * ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] );
}
//distance = distance/(float)numCol;
//distance = (float)sqrt(distance);
return distance;
}
// this function will return nearest neighbor information for a particular test row.
// called from main kernel // d_neighborhoodMatrix has size numTestRow*numTrainRow .. it is a flat array
__device__ float* calculate_distance_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol, int tidx){
//printf("Dealing with test data row %d\n", tidx);
for(int i=0; i<numTrainRow; i++){
//distance form rows testData[tidx] <--> trainData[i]
d_neighborhoodMatrix[tidx*numTrainRow+i] = calculate_distance(d_trainData, d_testData, numTrainRow, numTestRow, numCol, tidx, i);
}
return d_neighborhoodMatrix;
}
// kernel function that will perform k-nearest neighbor classification
// There will be one karnel launched for each row in the test data.
// This function will manage finding nearest neighbors from test data row to training data
__global__ void calculate_similarity_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("Inside Kernel %d\n", tidx);
//showData(d_testData, numTestRow, numCol, tidx);
//call function for calculating the nearest neighbor of tidx'th row of test data
d_neighborhoodMatrix = calculate_distance_matrix(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol, tidx);
}
// this funciton will read the data. It takes parameters file name as string, number of rows and columns.
// It will read a 2-d matrix and save as a flat 1-D array and return the pointer
float* read_data(char* fileName, int numRow, int numCol){
float* data;
data = (float*)malloc(numRow*numCol*sizeof(float));
FILE *file;
file=fopen(fileName, "r");
for (int i=0; i<numRow*numCol; i++){
if (!fscanf(file, "%f", &data[i])){
break;
}
//printf("%d-%f\n",i, data[i]);
}
fclose(file);
return data;
}
void show_data(float* data, int numRow, int numCol){
/*printf("numrow-%d numcol-%d\n\n", numRow, numCol);
for(int i =0; i<numRow*numCol; i++){
printf("%d-%f\t", i, data[i]);
}*/
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%f ",data[i*numCol+j]);
}
printf("\n");
}
}
//comment
__device__ int calculate_nearest_neighbor_index(float* d_neighborhoodMatrix, int tidx, int numTrainRow){
float minValue = 99999.0;
int minIndex = 0;
for (int i=(tidx*numTrainRow); i< (tidx*numTrainRow)+numTrainRow; i++){
if (d_neighborhoodMatrix[i] <= minValue ){
minValue = d_neighborhoodMatrix[i];
minIndex = i-(tidx*numTrainRow);
}
}
return minIndex;
}
// this function will calculate the nearest neighbors from similarity matrix
// a kernel will be launched for each test instance
__global__ void calculate_nearest_neighbor(float* d_neighborhoodMatrix, int* d_nearestNeighborIndices, int numTrainRow, int numTestRow, int numCol, int k){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
for(int i=0; i<k; i++){
int minIndex = calculate_nearest_neighbor_index(d_neighborhoodMatrix, tidx, numTrainRow);
d_nearestNeighborIndices[tidx*k+i] = minIndex;
d_neighborhoodMatrix[tidx*numTrainRow+minIndex] = (float)99999.0;
}
}
//calculate the label of a test instance
float calculate_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k, int currentInstance){
float label = (float)0.0;
float sum1 = (float)0.0;
int currentIndex = 0;
for(int i=0; i<k; i++){
currentIndex = host_nearestNeighborIndices[currentInstance*k + i];
//printf("%d - %f\n", currentIndex, trainLabel[currentIndex]);
sum1 += trainLabel[currentIndex];
//printf("currentIndex -%d, valueIndex-%f\n",currentIndex, trainLabel[currentIndex]);
}
printf("\n");
//printf("nstance-%d sum-%f\n", currentInstance, sum1);
if(sum1 >= (k/2) ){
label = (float)1.0;
}
return label;
}
//predict class labels of test data from calculated nearest neighbors
float* predict_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k){
float* predictedLabel;
predictedLabel = (float*)malloc( numTestRow*sizeof(float) );
for(int i=0; i<numTestRow; i++){
predictedLabel[i] = calculate_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k, i);
//printf("label prediction of instance %d\n", i);
}
return predictedLabel;
}
//calculate accuracy of prediction from original class labels and predicted labels
float calculate_accuracy(float* predictedLabel, float* testLabel, int numTestRow){
int correctPredictionCount = 0;
for(int i=0; i<numTestRow; i++ ){
//printf("original %f \t predicted %f\n", testLabel[i], predictedLabel[i]);
if(predictedLabel[i] == testLabel[i]){
correctPredictionCount ++;
}
}
//printf("\n\n");
return (float)100*((float)correctPredictionCount/(float)numTestRow);
}
void show_data_int(int* data, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
void show_data_nearest_neighbor_labels(int* data, float* trainLabel, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
int main(int argc, char* argv[])
{
//start the timer
clock_t begin_time = clock();
// first, catch the arguments from command line
int numTrainRow = atoi(argv[1]);
int numTestRow = atoi(argv[2]);
int numCol = atoi(argv[3]);
int k = atoi(argv[4]);
printf("\n**************** Hello World ! ******************\n");
// read the data files
float* trainData, *testData, *trainLabel, *trainLabel_1, *testLabel, *predictedLabel;
trainData = read_data("train.txt", numTrainRow, numCol);
testData = read_data("test.txt", numTestRow, numCol);
trainLabel = read_data("label_train.txt", numTrainRow, 1);
testLabel = read_data("label_test.txt", numTestRow, 1);
//trainData = read_data("vec_1k_train.txt", numTrainRow, numCol);
//testData = read_data("vec_1k_test.txt", numTestRow, numCol);
//trainLabel = read_data("label_1k_train.txt", numTrainRow, 1);
//testLabel = read_data("label_1k_test.txt", numTestRow, 1);
printf("Data Read Complete\n");
//show_data(testData, numTestRow, numCol);
//printf("\n\n\n");
//show_data(trainLabel, numTrainRow, 1);
//printf("\n\n\n");
// allocate memory and copy read files to device (GPU) memory from host (CPU) memory
float *d_trainData, *d_testData, *d_neighborhoodMatrix, *host_neighborhoodMatrix; //neighborhood matrix will have numTestRow rows and numTrainRow columns
int *d_nearestNeighborIndices, *host_nearestNeighborIndices; //it has numTestRow rows and k columns
const size_t trainSize = sizeof(float) * size_t(numTrainRow*numCol);
const size_t testSize = sizeof(float) * size_t(numTestRow*numCol);
const size_t neighborhoodMatrixSize = sizeof(float)*size_t(numTestRow*numTrainRow);
hipMalloc((void **)&d_trainData, trainSize);
hipMemcpy(d_trainData, trainData, trainSize, hipMemcpyHostToDevice);
hipMalloc((void **)&d_testData, testSize);
hipMemcpy(d_testData, testData, testSize, hipMemcpyHostToDevice);
hipMalloc((void **)&d_neighborhoodMatrix, neighborhoodMatrixSize);
hipMalloc((void **)&d_nearestNeighborIndices, (numTestRow*k*sizeof(int)) );
calculate_similarity_matrix<<<1,numTestRow>>>(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol);
hipFree(d_trainData);
hipFree(d_testData);
printf("Similarity matrix building complete\n");
// copy nearest neighbor matrix from device to CPU and print to view it
host_neighborhoodMatrix = (float*)malloc(neighborhoodMatrixSize);
hipMemcpy(host_neighborhoodMatrix, d_neighborhoodMatrix, neighborhoodMatrixSize, hipMemcpyDeviceToHost);
printf("\ncopying similarity matrix from device to host complete\n" );
//printf("\n\nSimilarity matrix\n");
show_data(host_neighborhoodMatrix, numTestRow, numTrainRow);
calculate_nearest_neighbor<<<1,numTestRow>>>(d_neighborhoodMatrix, d_nearestNeighborIndices, numTrainRow, numTestRow, numCol, k);
printf("Nearest Neighbour calculation complete\n");
// copy nearest neighbour indices from device (GPU) to host (CPU)
host_nearestNeighborIndices = (int*)malloc(numTestRow*k*sizeof(int));
hipMemcpy(host_nearestNeighborIndices, d_nearestNeighborIndices, (numTestRow*k*sizeof(int)), hipMemcpyDeviceToHost);
//printf("\nCopying nearest neighbour indices from device to host complete\n");
//printf("indices of nearest neighbour\n");
//show_data_int(host_nearestNeighborIndices, numTestRow, k);
predictedLabel = predict_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k);
printf("\nClass label prediction complete\n");
//show_data(predictedLabel, numTestRow, 1);
float acc = calculate_accuracy(predictedLabel, testLabel, numTestRow);
printf("\nPrediction Accuracy: %f", acc);
//take the end time and print time taken for running the program
clock_t end_tiem = clock();
double diff_time = (end_tiem - begin_time) / CLOCKS_PER_SEC;
printf("\n\nTime taken for running the program: %lf\n\n", diff_time);
free(testData);
free(trainData);
free(host_nearestNeighborIndices);
free(host_neighborhoodMatrix);
hipFree(d_neighborhoodMatrix);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Author: Rajiur Rahman ( rajiurrahman.bd@gmail.com )
// Department of Computer Science, Wayne State University
// knn implemented for GPU.
// have to provide training data, trianing data label, test data, test data label in separate text files. All the files should be ' ' space separated.
/* Instruction for compiling and running
* the commands should be following
* compile - nvcc knn.cu -o knn.o
* run - ./knn.o numTrainRow numTestRow numCol k
*
* For example:
* ./knn.o 20 5 10 4
* ./knn.o 15997 4000 30000 5
* ./knn_new.o 69 20 1000 5
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h> /* strtok() */
#include <sys/types.h> /* open() */
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h> /* read(), close() */
#include <math.h>
#include <time.h>
/*__global__ void kernel(int *a)
{
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
int tidy = threadIdx.y + blockIdx.y * blockDim.y;
}*/
__device__ void showData(float* data, int numRow, int numCol, int tidx){
for(int i =tidx*numCol; i<((tidx*numCol)+numCol); i++){
printf("%d-%f\t", i, data[i]);
}
}
// this function calculates the distance between two rows.
__device__ float calculate_distance(float* d_trainData, float* d_testData, int numTrainRow, int numTestRow, int numCol, int currentTestIndex, int currentTrainIndex){
float distance = (float) 100.0;
for (int i = 0; i<numCol; i++){
distance += ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] ) * ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] );
}
//distance = distance/(float)numCol;
//distance = (float)sqrt(distance);
return distance;
}
// this function will return nearest neighbor information for a particular test row.
// called from main kernel // d_neighborhoodMatrix has size numTestRow*numTrainRow .. it is a flat array
__device__ float* calculate_distance_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol, int tidx){
//printf("Dealing with test data row %d\n", tidx);
for(int i=0; i<numTrainRow; i++){
//distance form rows testData[tidx] <--> trainData[i]
d_neighborhoodMatrix[tidx*numTrainRow+i] = calculate_distance(d_trainData, d_testData, numTrainRow, numTestRow, numCol, tidx, i);
}
return d_neighborhoodMatrix;
}
// kernel function that will perform k-nearest neighbor classification
// There will be one karnel launched for each row in the test data.
// This function will manage finding nearest neighbors from test data row to training data
__global__ void calculate_similarity_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("Inside Kernel %d\n", tidx);
//showData(d_testData, numTestRow, numCol, tidx);
//call function for calculating the nearest neighbor of tidx'th row of test data
d_neighborhoodMatrix = calculate_distance_matrix(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol, tidx);
}
// this funciton will read the data. It takes parameters file name as string, number of rows and columns.
// It will read a 2-d matrix and save as a flat 1-D array and return the pointer
float* read_data(char* fileName, int numRow, int numCol){
float* data;
data = (float*)malloc(numRow*numCol*sizeof(float));
FILE *file;
file=fopen(fileName, "r");
for (int i=0; i<numRow*numCol; i++){
if (!fscanf(file, "%f", &data[i])){
break;
}
//printf("%d-%f\n",i, data[i]);
}
fclose(file);
return data;
}
void show_data(float* data, int numRow, int numCol){
/*printf("numrow-%d numcol-%d\n\n", numRow, numCol);
for(int i =0; i<numRow*numCol; i++){
printf("%d-%f\t", i, data[i]);
}*/
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%f ",data[i*numCol+j]);
}
printf("\n");
}
}
//comment
__device__ int calculate_nearest_neighbor_index(float* d_neighborhoodMatrix, int tidx, int numTrainRow){
float minValue = 99999.0;
int minIndex = 0;
for (int i=(tidx*numTrainRow); i< (tidx*numTrainRow)+numTrainRow; i++){
if (d_neighborhoodMatrix[i] <= minValue ){
minValue = d_neighborhoodMatrix[i];
minIndex = i-(tidx*numTrainRow);
}
}
return minIndex;
}
// this function will calculate the nearest neighbors from similarity matrix
// a kernel will be launched for each test instance
__global__ void calculate_nearest_neighbor(float* d_neighborhoodMatrix, int* d_nearestNeighborIndices, int numTrainRow, int numTestRow, int numCol, int k){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
for(int i=0; i<k; i++){
int minIndex = calculate_nearest_neighbor_index(d_neighborhoodMatrix, tidx, numTrainRow);
d_nearestNeighborIndices[tidx*k+i] = minIndex;
d_neighborhoodMatrix[tidx*numTrainRow+minIndex] = (float)99999.0;
}
}
//calculate the label of a test instance
float calculate_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k, int currentInstance){
float label = (float)0.0;
float sum1 = (float)0.0;
int currentIndex = 0;
for(int i=0; i<k; i++){
currentIndex = host_nearestNeighborIndices[currentInstance*k + i];
//printf("%d - %f\n", currentIndex, trainLabel[currentIndex]);
sum1 += trainLabel[currentIndex];
//printf("currentIndex -%d, valueIndex-%f\n",currentIndex, trainLabel[currentIndex]);
}
printf("\n");
//printf("nstance-%d sum-%f\n", currentInstance, sum1);
if(sum1 >= (k/2) ){
label = (float)1.0;
}
return label;
}
//predict class labels of test data from calculated nearest neighbors
float* predict_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k){
float* predictedLabel;
predictedLabel = (float*)malloc( numTestRow*sizeof(float) );
for(int i=0; i<numTestRow; i++){
predictedLabel[i] = calculate_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k, i);
//printf("label prediction of instance %d\n", i);
}
return predictedLabel;
}
//calculate accuracy of prediction from original class labels and predicted labels
float calculate_accuracy(float* predictedLabel, float* testLabel, int numTestRow){
int correctPredictionCount = 0;
for(int i=0; i<numTestRow; i++ ){
//printf("original %f \t predicted %f\n", testLabel[i], predictedLabel[i]);
if(predictedLabel[i] == testLabel[i]){
correctPredictionCount ++;
}
}
//printf("\n\n");
return (float)100*((float)correctPredictionCount/(float)numTestRow);
}
void show_data_int(int* data, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
void show_data_nearest_neighbor_labels(int* data, float* trainLabel, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
int main(int argc, char* argv[])
{
//start the timer
clock_t begin_time = clock();
// first, catch the arguments from command line
int numTrainRow = atoi(argv[1]);
int numTestRow = atoi(argv[2]);
int numCol = atoi(argv[3]);
int k = atoi(argv[4]);
printf("\n**************** Hello World ! ******************\n");
// read the data files
float* trainData, *testData, *trainLabel, *trainLabel_1, *testLabel, *predictedLabel;
trainData = read_data("train.txt", numTrainRow, numCol);
testData = read_data("test.txt", numTestRow, numCol);
trainLabel = read_data("label_train.txt", numTrainRow, 1);
testLabel = read_data("label_test.txt", numTestRow, 1);
//trainData = read_data("vec_1k_train.txt", numTrainRow, numCol);
//testData = read_data("vec_1k_test.txt", numTestRow, numCol);
//trainLabel = read_data("label_1k_train.txt", numTrainRow, 1);
//testLabel = read_data("label_1k_test.txt", numTestRow, 1);
printf("Data Read Complete\n");
//show_data(testData, numTestRow, numCol);
//printf("\n\n\n");
//show_data(trainLabel, numTrainRow, 1);
//printf("\n\n\n");
// allocate memory and copy read files to device (GPU) memory from host (CPU) memory
float *d_trainData, *d_testData, *d_neighborhoodMatrix, *host_neighborhoodMatrix; //neighborhood matrix will have numTestRow rows and numTrainRow columns
int *d_nearestNeighborIndices, *host_nearestNeighborIndices; //it has numTestRow rows and k columns
const size_t trainSize = sizeof(float) * size_t(numTrainRow*numCol);
const size_t testSize = sizeof(float) * size_t(numTestRow*numCol);
const size_t neighborhoodMatrixSize = sizeof(float)*size_t(numTestRow*numTrainRow);
hipMalloc((void **)&d_trainData, trainSize);
hipMemcpy(d_trainData, trainData, trainSize, hipMemcpyHostToDevice);
hipMalloc((void **)&d_testData, testSize);
hipMemcpy(d_testData, testData, testSize, hipMemcpyHostToDevice);
hipMalloc((void **)&d_neighborhoodMatrix, neighborhoodMatrixSize);
hipMalloc((void **)&d_nearestNeighborIndices, (numTestRow*k*sizeof(int)) );
calculate_similarity_matrix<<<1,numTestRow>>>(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol);
hipFree(d_trainData);
hipFree(d_testData);
printf("Similarity matrix building complete\n");
// copy nearest neighbor matrix from device to CPU and print to view it
host_neighborhoodMatrix = (float*)malloc(neighborhoodMatrixSize);
hipMemcpy(host_neighborhoodMatrix, d_neighborhoodMatrix, neighborhoodMatrixSize, hipMemcpyDeviceToHost);
printf("\ncopying similarity matrix from device to host complete\n" );
//printf("\n\nSimilarity matrix\n");
show_data(host_neighborhoodMatrix, numTestRow, numTrainRow);
calculate_nearest_neighbor<<<1,numTestRow>>>(d_neighborhoodMatrix, d_nearestNeighborIndices, numTrainRow, numTestRow, numCol, k);
printf("Nearest Neighbour calculation complete\n");
// copy nearest neighbour indices from device (GPU) to host (CPU)
host_nearestNeighborIndices = (int*)malloc(numTestRow*k*sizeof(int));
hipMemcpy(host_nearestNeighborIndices, d_nearestNeighborIndices, (numTestRow*k*sizeof(int)), hipMemcpyDeviceToHost);
//printf("\nCopying nearest neighbour indices from device to host complete\n");
//printf("indices of nearest neighbour\n");
//show_data_int(host_nearestNeighborIndices, numTestRow, k);
predictedLabel = predict_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k);
printf("\nClass label prediction complete\n");
//show_data(predictedLabel, numTestRow, 1);
float acc = calculate_accuracy(predictedLabel, testLabel, numTestRow);
printf("\nPrediction Accuracy: %f", acc);
//take the end time and print time taken for running the program
clock_t end_tiem = clock();
double diff_time = (end_tiem - begin_time) / CLOCKS_PER_SEC;
printf("\n\nTime taken for running the program: %lf\n\n", diff_time);
free(testData);
free(trainData);
free(host_nearestNeighborIndices);
free(host_neighborhoodMatrix);
hipFree(d_neighborhoodMatrix);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27calculate_similarity_matrixPfS_S_iii
.globl _Z27calculate_similarity_matrixPfS_S_iii
.p2align 8
.type _Z27calculate_similarity_matrixPfS_S_iii,@function
_Z27calculate_similarity_matrixPfS_S_iii:
s_load_b32 s10, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s11, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v5, 0
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s8, s9
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_gt_i32 s11, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x10
s_cselect_b32 s0, -1, 0
s_mov_b32 s1, s9
v_cndmask_b32_e64 v0, 0, 1, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s11
v_mul_lo_u32 v4, v1, s10
v_cmp_ne_u32_e64 s0, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
v_mov_b32_e32 v6, 0x42c80000
.LBB0_3:
v_add_nc_u32_e32 v2, s1, v4
s_add_i32 s1, s1, 1
s_add_i32 s8, s8, s11
s_cmp_lg_u32 s1, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v6, off
s_cbranch_scc0 .LBB0_7
.LBB0_4:
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
v_dual_mov_b32 v6, 0x42c80000 :: v_dual_mov_b32 v3, v1
s_lshl_b64 s[6:7], s[8:9], 2
v_mov_b32_e32 v2, v0
s_add_u32 s6, s4, s6
s_addc_u32 s7, s5, s7
s_mov_b32 s12, s11
.LBB0_6:
global_load_b32 v7, v[2:3], off
global_load_b32 v8, v5, s[6:7]
v_add_co_u32 v2, vcc_lo, v2, 4
s_add_i32 s12, s12, -1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s12, 0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v7
s_cbranch_scc1 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27calculate_similarity_matrixPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27calculate_similarity_matrixPfS_S_iii, .Lfunc_end0-_Z27calculate_similarity_matrixPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26calculate_nearest_neighborPfPiiiii
.globl _Z26calculate_nearest_neighborPfPiiiii
.p2align 8
.type _Z26calculate_nearest_neighborPfPiiiii,@function
_Z26calculate_nearest_neighborPfPiiiii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_7
s_clause 0x2
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v7, 0x47c34f80
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_gt_i32 s8, 0
v_mad_u64_u32 v[2:3], null, s15, s3, v[0:1]
s_cselect_b32 s1, -1, 0
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v2, s8
v_mul_lo_u32 v5, v2, s2
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v6, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_co_u32 v1, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
v_add_nc_u32_e32 v3, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v9, v8, v0
s_add_i32 s3, s3, 1
s_cmp_eq_u32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_store_b32 v[3:4], v8, off
global_store_b32 v[9:10], v7, off
s_cbranch_scc1 .LBB1_7
.LBB1_3:
v_mov_b32_e32 v8, 0
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB1_2
v_dual_mov_b32 v9, 0x47c34f80 :: v_dual_mov_b32 v4, v2
v_mov_b32_e32 v3, v1
s_mov_b32 s8, 0
s_mov_b32 s9, 0
.LBB1_5:
global_load_b32 v10, v[3:4], off
v_add_co_u32 v3, s0, v3, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
s_waitcnt vmcnt(0)
v_cmp_nle_f32_e32 vcc_lo, v10, v9
v_cndmask_b32_e32 v8, s9, v8, vcc_lo
s_add_i32 s9, s9, 1
v_dual_cndmask_b32 v9, v10, v9 :: v_dual_add_nc_u32 v10, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v10, v6
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB1_5
s_or_b32 exec_lo, exec_lo, s8
s_branch .LBB1_2
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26calculate_nearest_neighborPfPiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z26calculate_nearest_neighborPfPiiiii, .Lfunc_end1-_Z26calculate_nearest_neighborPfPiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27calculate_similarity_matrixPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27calculate_similarity_matrixPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26calculate_nearest_neighborPfPiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26calculate_nearest_neighborPfPiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Author: Rajiur Rahman ( rajiurrahman.bd@gmail.com )
// Department of Computer Science, Wayne State University
// knn implemented for GPU.
// have to provide training data, trianing data label, test data, test data label in separate text files. All the files should be ' ' space separated.
/* Instruction for compiling and running
* the commands should be following
* compile - nvcc knn.cu -o knn.o
* run - ./knn.o numTrainRow numTestRow numCol k
*
* For example:
* ./knn.o 20 5 10 4
* ./knn.o 15997 4000 30000 5
* ./knn_new.o 69 20 1000 5
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h> /* strtok() */
#include <sys/types.h> /* open() */
#include <sys/stat.h>
#include <fcntl.h>
#include <unistd.h> /* read(), close() */
#include <math.h>
#include <time.h>
/*__global__ void kernel(int *a)
{
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
int tidy = threadIdx.y + blockIdx.y * blockDim.y;
}*/
__device__ void showData(float* data, int numRow, int numCol, int tidx){
for(int i =tidx*numCol; i<((tidx*numCol)+numCol); i++){
printf("%d-%f\t", i, data[i]);
}
}
// this function calculates the distance between two rows.
__device__ float calculate_distance(float* d_trainData, float* d_testData, int numTrainRow, int numTestRow, int numCol, int currentTestIndex, int currentTrainIndex){
float distance = (float) 100.0;
for (int i = 0; i<numCol; i++){
distance += ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] ) * ( d_testData[currentTestIndex*numCol+i] - d_trainData[currentTrainIndex*numCol+i] );
}
//distance = distance/(float)numCol;
//distance = (float)sqrt(distance);
return distance;
}
// this function will return nearest neighbor information for a particular test row.
// called from main kernel // d_neighborhoodMatrix has size numTestRow*numTrainRow .. it is a flat array
__device__ float* calculate_distance_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol, int tidx){
//printf("Dealing with test data row %d\n", tidx);
for(int i=0; i<numTrainRow; i++){
//distance form rows testData[tidx] <--> trainData[i]
d_neighborhoodMatrix[tidx*numTrainRow+i] = calculate_distance(d_trainData, d_testData, numTrainRow, numTestRow, numCol, tidx, i);
}
return d_neighborhoodMatrix;
}
// kernel function that will perform k-nearest neighbor classification
// There will be one karnel launched for each row in the test data.
// This function will manage finding nearest neighbors from test data row to training data
__global__ void calculate_similarity_matrix(float* d_trainData, float* d_testData, float* d_neighborhoodMatrix, int numTrainRow, int numTestRow, int numCol){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
//printf("Inside Kernel %d\n", tidx);
//showData(d_testData, numTestRow, numCol, tidx);
//call function for calculating the nearest neighbor of tidx'th row of test data
d_neighborhoodMatrix = calculate_distance_matrix(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol, tidx);
}
// this funciton will read the data. It takes parameters file name as string, number of rows and columns.
// It will read a 2-d matrix and save as a flat 1-D array and return the pointer
float* read_data(char* fileName, int numRow, int numCol){
float* data;
data = (float*)malloc(numRow*numCol*sizeof(float));
FILE *file;
file=fopen(fileName, "r");
for (int i=0; i<numRow*numCol; i++){
if (!fscanf(file, "%f", &data[i])){
break;
}
//printf("%d-%f\n",i, data[i]);
}
fclose(file);
return data;
}
void show_data(float* data, int numRow, int numCol){
/*printf("numrow-%d numcol-%d\n\n", numRow, numCol);
for(int i =0; i<numRow*numCol; i++){
printf("%d-%f\t", i, data[i]);
}*/
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%f ",data[i*numCol+j]);
}
printf("\n");
}
}
//comment
__device__ int calculate_nearest_neighbor_index(float* d_neighborhoodMatrix, int tidx, int numTrainRow){
float minValue = 99999.0;
int minIndex = 0;
for (int i=(tidx*numTrainRow); i< (tidx*numTrainRow)+numTrainRow; i++){
if (d_neighborhoodMatrix[i] <= minValue ){
minValue = d_neighborhoodMatrix[i];
minIndex = i-(tidx*numTrainRow);
}
}
return minIndex;
}
// this function will calculate the nearest neighbors from similarity matrix
// a kernel will be launched for each test instance
__global__ void calculate_nearest_neighbor(float* d_neighborhoodMatrix, int* d_nearestNeighborIndices, int numTrainRow, int numTestRow, int numCol, int k){
int tidx = threadIdx.x + blockIdx.x * blockDim.x;
for(int i=0; i<k; i++){
int minIndex = calculate_nearest_neighbor_index(d_neighborhoodMatrix, tidx, numTrainRow);
d_nearestNeighborIndices[tidx*k+i] = minIndex;
d_neighborhoodMatrix[tidx*numTrainRow+minIndex] = (float)99999.0;
}
}
//calculate the label of a test instance
float calculate_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k, int currentInstance){
float label = (float)0.0;
float sum1 = (float)0.0;
int currentIndex = 0;
for(int i=0; i<k; i++){
currentIndex = host_nearestNeighborIndices[currentInstance*k + i];
//printf("%d - %f\n", currentIndex, trainLabel[currentIndex]);
sum1 += trainLabel[currentIndex];
//printf("currentIndex -%d, valueIndex-%f\n",currentIndex, trainLabel[currentIndex]);
}
printf("\n");
//printf("nstance-%d sum-%f\n", currentInstance, sum1);
if(sum1 >= (k/2) ){
label = (float)1.0;
}
return label;
}
//predict class labels of test data from calculated nearest neighbors
float* predict_label(int* host_nearestNeighborIndices, float* trainLabel, int numTestRow, int numTrainRow, int k){
float* predictedLabel;
predictedLabel = (float*)malloc( numTestRow*sizeof(float) );
for(int i=0; i<numTestRow; i++){
predictedLabel[i] = calculate_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k, i);
//printf("label prediction of instance %d\n", i);
}
return predictedLabel;
}
//calculate accuracy of prediction from original class labels and predicted labels
float calculate_accuracy(float* predictedLabel, float* testLabel, int numTestRow){
int correctPredictionCount = 0;
for(int i=0; i<numTestRow; i++ ){
//printf("original %f \t predicted %f\n", testLabel[i], predictedLabel[i]);
if(predictedLabel[i] == testLabel[i]){
correctPredictionCount ++;
}
}
//printf("\n\n");
return (float)100*((float)correctPredictionCount/(float)numTestRow);
}
void show_data_int(int* data, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
void show_data_nearest_neighbor_labels(int* data, float* trainLabel, int numRow, int numCol){
for(int i=0; i< numRow; i++){
for(int j=0; j<numCol; j++){
printf("%d ",data[i*numCol+j]);
}
printf("\n");
}
}
int main(int argc, char* argv[])
{
//start the timer
clock_t begin_time = clock();
// first, catch the arguments from command line
int numTrainRow = atoi(argv[1]);
int numTestRow = atoi(argv[2]);
int numCol = atoi(argv[3]);
int k = atoi(argv[4]);
printf("\n**************** Hello World ! ******************\n");
// read the data files
float* trainData, *testData, *trainLabel, *trainLabel_1, *testLabel, *predictedLabel;
trainData = read_data("train.txt", numTrainRow, numCol);
testData = read_data("test.txt", numTestRow, numCol);
trainLabel = read_data("label_train.txt", numTrainRow, 1);
testLabel = read_data("label_test.txt", numTestRow, 1);
//trainData = read_data("vec_1k_train.txt", numTrainRow, numCol);
//testData = read_data("vec_1k_test.txt", numTestRow, numCol);
//trainLabel = read_data("label_1k_train.txt", numTrainRow, 1);
//testLabel = read_data("label_1k_test.txt", numTestRow, 1);
printf("Data Read Complete\n");
//show_data(testData, numTestRow, numCol);
//printf("\n\n\n");
//show_data(trainLabel, numTrainRow, 1);
//printf("\n\n\n");
// allocate memory and copy read files to device (GPU) memory from host (CPU) memory
float *d_trainData, *d_testData, *d_neighborhoodMatrix, *host_neighborhoodMatrix; //neighborhood matrix will have numTestRow rows and numTrainRow columns
int *d_nearestNeighborIndices, *host_nearestNeighborIndices; //it has numTestRow rows and k columns
const size_t trainSize = sizeof(float) * size_t(numTrainRow*numCol);
const size_t testSize = sizeof(float) * size_t(numTestRow*numCol);
const size_t neighborhoodMatrixSize = sizeof(float)*size_t(numTestRow*numTrainRow);
hipMalloc((void **)&d_trainData, trainSize);
hipMemcpy(d_trainData, trainData, trainSize, hipMemcpyHostToDevice);
hipMalloc((void **)&d_testData, testSize);
hipMemcpy(d_testData, testData, testSize, hipMemcpyHostToDevice);
hipMalloc((void **)&d_neighborhoodMatrix, neighborhoodMatrixSize);
hipMalloc((void **)&d_nearestNeighborIndices, (numTestRow*k*sizeof(int)) );
calculate_similarity_matrix<<<1,numTestRow>>>(d_trainData, d_testData, d_neighborhoodMatrix, numTrainRow, numTestRow, numCol);
hipFree(d_trainData);
hipFree(d_testData);
printf("Similarity matrix building complete\n");
// copy nearest neighbor matrix from device to CPU and print to view it
host_neighborhoodMatrix = (float*)malloc(neighborhoodMatrixSize);
hipMemcpy(host_neighborhoodMatrix, d_neighborhoodMatrix, neighborhoodMatrixSize, hipMemcpyDeviceToHost);
printf("\ncopying similarity matrix from device to host complete\n" );
//printf("\n\nSimilarity matrix\n");
show_data(host_neighborhoodMatrix, numTestRow, numTrainRow);
calculate_nearest_neighbor<<<1,numTestRow>>>(d_neighborhoodMatrix, d_nearestNeighborIndices, numTrainRow, numTestRow, numCol, k);
printf("Nearest Neighbour calculation complete\n");
// copy nearest neighbour indices from device (GPU) to host (CPU)
host_nearestNeighborIndices = (int*)malloc(numTestRow*k*sizeof(int));
hipMemcpy(host_nearestNeighborIndices, d_nearestNeighborIndices, (numTestRow*k*sizeof(int)), hipMemcpyDeviceToHost);
//printf("\nCopying nearest neighbour indices from device to host complete\n");
//printf("indices of nearest neighbour\n");
//show_data_int(host_nearestNeighborIndices, numTestRow, k);
predictedLabel = predict_label(host_nearestNeighborIndices, trainLabel, numTestRow, numTrainRow, k);
printf("\nClass label prediction complete\n");
//show_data(predictedLabel, numTestRow, 1);
float acc = calculate_accuracy(predictedLabel, testLabel, numTestRow);
printf("\nPrediction Accuracy: %f", acc);
//take the end time and print time taken for running the program
clock_t end_tiem = clock();
double diff_time = (end_tiem - begin_time) / CLOCKS_PER_SEC;
printf("\n\nTime taken for running the program: %lf\n\n", diff_time);
free(testData);
free(trainData);
free(host_nearestNeighborIndices);
free(host_neighborhoodMatrix);
hipFree(d_neighborhoodMatrix);
return 0;
} | .text
.file "knn_new.hip"
.globl _Z42__device_stub__calculate_similarity_matrixPfS_S_iii # -- Begin function _Z42__device_stub__calculate_similarity_matrixPfS_S_iii
.p2align 4, 0x90
.type _Z42__device_stub__calculate_similarity_matrixPfS_S_iii,@function
_Z42__device_stub__calculate_similarity_matrixPfS_S_iii: # @_Z42__device_stub__calculate_similarity_matrixPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27calculate_similarity_matrixPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z42__device_stub__calculate_similarity_matrixPfS_S_iii, .Lfunc_end0-_Z42__device_stub__calculate_similarity_matrixPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z9read_dataPcii # -- Begin function _Z9read_dataPcii
.p2align 4, 0x90
.type _Z9read_dataPcii,@function
_Z9read_dataPcii: # @_Z9read_dataPcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
imull %edx, %ebp
movslq %ebp, %r15
leaq (,%r15,4), %rdi
callq malloc
movq %rax, %rbx
movl $.L.str, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
testl %r15d, %r15d
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
decq %r12
movq %rbx, %r15
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
subq $1, %r12
setb %cl
testl %eax, %eax
je .LBB1_4
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
addq $4, %r15
testb %cl, %cl
je .LBB1_2
.LBB1_4: # %._crit_edge
movq %r14, %rdi
callq fclose
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9read_dataPcii, .Lfunc_end1-_Z9read_dataPcii
.cfi_endproc
# -- End function
.globl _Z9show_dataPfii # -- Begin function _Z9show_dataPfii
.p2align 4, 0x90
.type _Z9show_dataPfii,@function
_Z9show_dataPfii: # @_Z9show_dataPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9show_dataPfii, .Lfunc_end2-_Z9show_dataPfii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__calculate_nearest_neighborPfPiiiii # -- Begin function _Z41__device_stub__calculate_nearest_neighborPfPiiiii
.p2align 4, 0x90
.type _Z41__device_stub__calculate_nearest_neighborPfPiiiii,@function
_Z41__device_stub__calculate_nearest_neighborPfPiiiii: # @_Z41__device_stub__calculate_nearest_neighborPfPiiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26calculate_nearest_neighborPfPiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end3:
.size _Z41__device_stub__calculate_nearest_neighborPfPiiiii, .Lfunc_end3-_Z41__device_stub__calculate_nearest_neighborPfPiiiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15calculate_labelPiPfiiii
.LCPI4_0:
.long 0x3f800000 # float 1
.text
.globl _Z15calculate_labelPiPfiiii
.p2align 4, 0x90
.type _Z15calculate_labelPiPfiiii,@function
_Z15calculate_labelPiPfiiii: # @_Z15calculate_labelPiPfiiii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl %r8d, %ebx
testl %r8d, %r8d
jle .LBB4_1
# %bb.3: # %.lr.ph
imull %ebx, %r9d
movslq %r9d, %rcx
movl %ebx, %eax
leaq (%rdi,%rcx,4), %rcx
xorps %xmm0, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_4: # =>This Inner Loop Header: Depth=1
movslq (%rcx,%rdx,4), %rdi
addss (%rsi,%rdi,4), %xmm0
incq %rdx
cmpq %rdx, %rax
jne .LBB4_4
jmp .LBB4_2
.LBB4_1:
xorps %xmm0, %xmm0
.LBB4_2: # %._crit_edge
movss %xmm0, 12(%rsp) # 4-byte Spill
movl $10, %edi
callq putchar@PLT
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
cmpnless 12(%rsp), %xmm0 # 4-byte Folded Reload
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
andnps %xmm1, %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z15calculate_labelPiPfiiii, .Lfunc_end4-_Z15calculate_labelPiPfiiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13predict_labelPiPfiii
.LCPI5_0:
.long 0x3f800000 # float 1
.text
.globl _Z13predict_labelPiPfiii
.p2align 4, 0x90
.type _Z13predict_labelPiPfiii,@function
_Z13predict_labelPiPfiii: # @_Z13predict_labelPiPfiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, 4(%rsp) # 4-byte Spill
movl %edx, %r12d
movq %rsi, %r14
movq %rdi, %r15
movslq %edx, %rbx
leaq (,%rbx,4), %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB5_7
# %bb.1: # %.lr.ph
movl 4(%rsp), %ecx # 4-byte Reload
movl %ecx, %r13d
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
cvtsi2ss %eax, %xmm0
movss %xmm0, 8(%rsp) # 4-byte Spill
movslq %ecx, %rbp
movl %r12d, %ebx
shlq $2, %rbp
xorl %r12d, %r12d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_3: # in Loop: Header=BB5_2 Depth=1
xorps %xmm0, %xmm0
.LBB5_6: # %_Z15calculate_labelPiPfiiii.exit
# in Loop: Header=BB5_2 Depth=1
movss %xmm0, 12(%rsp) # 4-byte Spill
movl $10, %edi
callq putchar@PLT
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cmpnless 12(%rsp), %xmm0 # 4-byte Folded Reload
movss .LCPI5_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
andnps %xmm1, %xmm0
movq 16(%rsp), %rax # 8-byte Reload
movss %xmm0, (%rax,%r12,4)
incq %r12
addq %rbp, %r15
cmpq %rbx, %r12
je .LBB5_7
.LBB5_2: # =>This Loop Header: Depth=1
# Child Loop BB5_5 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB5_3
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB5_2 Depth=1
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_5: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%r15,%rax,4), %rcx
addss (%r14,%rcx,4), %xmm0
incq %rax
cmpq %rax, %r13
jne .LBB5_5
jmp .LBB5_6
.LBB5_7: # %._crit_edge
movq 16(%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z13predict_labelPiPfiii, .Lfunc_end5-_Z13predict_labelPiPfiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z18calculate_accuracyPfS_i
.LCPI6_0:
.long 0x42c80000 # float 100
.text
.globl _Z18calculate_accuracyPfS_i
.p2align 4, 0x90
.type _Z18calculate_accuracyPfS_i,@function
_Z18calculate_accuracyPfS_i: # @_Z18calculate_accuracyPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB6_1
# %bb.4: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB6_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpeqss (%rdi,%rcx,4), %xmm0
movd %xmm0, %r9d
subl %r9d, %r8d
incq %rcx
cmpq %rcx, %rax
jne .LBB6_5
# %bb.2: # %._crit_edge.loopexit
xorps %xmm0, %xmm0
cvtsi2ss %r8d, %xmm0
jmp .LBB6_3
.LBB6_1:
xorps %xmm0, %xmm0
.LBB6_3: # %._crit_edge
cvtsi2ss %edx, %xmm1
divss %xmm1, %xmm0
mulss .LCPI6_0(%rip), %xmm0
retq
.Lfunc_end6:
.size _Z18calculate_accuracyPfS_i, .Lfunc_end6-_Z18calculate_accuracyPfS_i
.cfi_endproc
# -- End function
.globl _Z13show_data_intPiii # -- Begin function _Z13show_data_intPiii
.p2align 4, 0x90
.type _Z13show_data_intPiii,@function
_Z13show_data_intPiii: # @_Z13show_data_intPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB7_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_5: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB7_6
.LBB7_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
testl %ebx, %ebx
jle .LBB7_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB7_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_4: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB7_4
jmp .LBB7_5
.LBB7_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z13show_data_intPiii, .Lfunc_end7-_Z13show_data_intPiii
.cfi_endproc
# -- End function
.globl _Z33show_data_nearest_neighbor_labelsPiPfii # -- Begin function _Z33show_data_nearest_neighbor_labelsPiPfii
.p2align 4, 0x90
.type _Z33show_data_nearest_neighbor_labelsPiPfii,@function
_Z33show_data_nearest_neighbor_labelsPiPfii: # @_Z33show_data_nearest_neighbor_labelsPiPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB8_6
# %bb.1: # %.preheader.lr.ph
movl %ecx, %ebx
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ecx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB8_2
.p2align 4, 0x90
.LBB8_5: # %._crit_edge
# in Loop: Header=BB8_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB8_6
.LBB8_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_4 Depth 2
testl %ebx, %ebx
jle .LBB8_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB8_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_4: # Parent Loop BB8_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB8_4
jmp .LBB8_5
.LBB8_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z33show_data_nearest_neighbor_labelsPiPfii, .Lfunc_end8-_Z33show_data_nearest_neighbor_labelsPiPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI9_0:
.long 0x3f800000 # float 1
.LCPI9_1:
.long 0x42c80000 # float 100
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
callq clock
movq %rax, 272(%rsp) # 8-byte Spill
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 72(%rsp) # 8-byte Spill
movl $.Lstr, %edi
callq puts@PLT
movq %r14, 40(%rsp) # 8-byte Spill
# kill: def $r14d killed $r14d killed $r14
imull %r13d, %r14d
movslq %r14d, %r15
leaq (,%r15,4), %rdi
movq %rdi, %rbp
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movl $.L.str.6, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB9_4
# %bb.1: # %.lr.ph.preheader.i
movl %r14d, %r15d
decq %r15
movq 24(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB9_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
subq $1, %r15
setb %cl
testl %eax, %eax
je .LBB9_4
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB9_2 Depth=1
addq $4, %r14
testb %cl, %cl
je .LBB9_2
.LBB9_4: # %_Z9read_dataPcii.exit
movq %rbx, %rdi
callq fclose
movq 40(%rsp), %rax # 8-byte Reload
movl %eax, %r15d
movq %r12, 32(%rsp) # 8-byte Spill
imull %r12d, %r15d
movslq %r15d, %r12
leaq (,%r12,4), %rdi
movq %rdi, 56(%rsp) # 8-byte Spill
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movl $.L.str.7, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r14
testl %r12d, %r12d
jle .LBB9_8
# %bb.5: # %.lr.ph.preheader.i72
movl %r15d, %r12d
decq %r12
movq 88(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB9_6: # %.lr.ph.i74
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
subq $1, %r12
setb %cl
testl %eax, %eax
je .LBB9_8
# %bb.7: # %.lr.ph.i74
# in Loop: Header=BB9_6 Depth=1
addq $4, %r15
testb %cl, %cl
je .LBB9_6
.LBB9_8: # %_Z9read_dataPcii.exit80
movq %r14, %rdi
callq fclose
movslq %r13d, %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r14
movl $.L.str.8, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r15
movq %r13, 48(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB9_12
# %bb.9: # %.lr.ph.preheader.i81
movl 48(%rsp), %r13d # 4-byte Reload
decq %r13
movq %r14, %r12
.p2align 4, 0x90
.LBB9_10: # %.lr.ph.i83
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
subq $1, %r13
setb %cl
testl %eax, %eax
je .LBB9_12
# %bb.11: # %.lr.ph.i83
# in Loop: Header=BB9_10 Depth=1
addq $4, %r12
testb %cl, %cl
je .LBB9_10
.LBB9_12: # %_Z9read_dataPcii.exit89
movq %r15, %rdi
callq fclose
movq 32(%rsp), %r12 # 8-byte Reload
movslq %r12d, %rdi
shlq $2, %rdi
movq %rdi, 64(%rsp) # 8-byte Spill
callq malloc
movq %rax, 184(%rsp) # 8-byte Spill
movl $.L.str.9, %edi
movl $.L.str, %esi
callq fopen
movq %rax, %r15
testl %r12d, %r12d
jle .LBB9_16
# %bb.13: # %.lr.ph.preheader.i90
movl 32(%rsp), %r13d # 4-byte Reload
decq %r13
movq 184(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB9_14: # %.lr.ph.i92
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
subq $1, %r13
setb %cl
testl %eax, %eax
je .LBB9_16
# %bb.15: # %.lr.ph.i92
# in Loop: Header=BB9_14 Depth=1
addq $4, %r12
testb %cl, %cl
je .LBB9_14
.LBB9_16: # %_Z9read_dataPcii.exit98
movabsq $4294967297, %rbx # imm = 0x100000001
movq %r15, %rdi
callq fclose
movl $.Lstr.1, %edi
callq puts@PLT
movq 48(%rsp), %r13 # 8-byte Reload
movl %r13d, %eax
movq 32(%rsp), %r12 # 8-byte Reload
imull %r12d, %eax
movslq %eax, %r15
shlq $2, %r15
leaq 104(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 104(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 96(%rsp), %rdi
movq 56(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
movq 96(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 80(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 72(%rsp), %rax # 8-byte Reload
# kill: def $eax killed $eax killed $rax
imull %r12d, %eax
movslq %eax, %rsi
shlq $2, %rsi
leaq 200(%rsp), %rdi
movq %rsi, 264(%rsp) # 8-byte Spill
callq hipMalloc
movl %r12d, %ebp
leaq (%rbx,%rbp), %rdx
decq %rdx
movq %rbx, %rdi
movl $1, %esi
movq %rdx, 256(%rsp) # 8-byte Spill
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_18
# %bb.17:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 80(%rsp), %rdx
movq %rax, 176(%rsp)
movq %rcx, 168(%rsp)
movq %rdx, 128(%rsp)
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movl %eax, 12(%rsp)
leaq 176(%rsp), %rax
movq %rax, 208(%rsp)
leaq 168(%rsp), %rax
movq %rax, 216(%rsp)
leaq 128(%rsp), %rax
movq %rax, 224(%rsp)
leaq 20(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 12(%rsp), %rax
movq %rax, 248(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z27calculate_similarity_matrixPfS_S_iii, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_18:
movq 104(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movl $.Lstr.2, %edi
callq puts@PLT
movq %r15, %rdi
callq malloc
movq 80(%rsp), %rsi
movq %rax, 192(%rsp) # 8-byte Spill
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
testl %r12d, %r12d
movq %rbp, 56(%rsp) # 8-byte Spill
jle .LBB9_24
# %bb.19: # %.preheader.i.preheader
movl %r13d, %ebx
xorl %r15d, %r15d
xorl %r12d, %r12d
jmp .LBB9_20
.p2align 4, 0x90
.LBB9_23: # %._crit_edge.i
# in Loop: Header=BB9_20 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r12
movq 48(%rsp), %r13 # 8-byte Reload
addl %r13d, %r15d
movq 56(%rsp), %rbp # 8-byte Reload
cmpq %rbp, %r12
je .LBB9_24
.LBB9_20: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB9_22 Depth 2
testl %r13d, %r13d
jle .LBB9_23
# %bb.21: # %.lr.ph.i99
# in Loop: Header=BB9_20 Depth=1
movl %r15d, %eax
movq 192(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB9_22: # Parent Loop BB9_20 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %rbp
cmpq %rbp, %rbx
jne .LBB9_22
jmp .LBB9_23
.LBB9_24: # %_Z9show_dataPfii.exit
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq 256(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 32(%rsp), %r12 # 8-byte Reload
jne .LBB9_26
# %bb.25:
movq 80(%rsp), %rax
movq 200(%rsp), %rcx
movq %rax, 176(%rsp)
movq %rcx, 168(%rsp)
movl %r13d, 112(%rsp)
movl %r12d, 20(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movl %eax, 16(%rsp)
movq 72(%rsp), %rax # 8-byte Reload
movl %eax, 12(%rsp)
leaq 176(%rsp), %rax
movq %rax, 208(%rsp)
leaq 168(%rsp), %rax
movq %rax, 216(%rsp)
leaq 112(%rsp), %rax
movq %rax, 224(%rsp)
leaq 20(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 12(%rsp), %rax
movq %rax, 248(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 208(%rsp), %r9
movl $_Z26calculate_nearest_neighborPfPiiiii, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_26:
movl $.Lstr.4, %edi
callq puts@PLT
movq 264(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq 200(%rsp), %rsi
movq %rax, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi # 8-byte Reload
callq malloc
testl %r12d, %r12d
jle .LBB9_38
# %bb.27: # %.lr.ph.i111
movq %rax, %r15
movq 72(%rsp), %rcx # 8-byte Reload
movl %ecx, %ebp
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 40(%rsp) # 4-byte Spill
movq %r13, %r12
movslq %ecx, %r13
shlq $2, %r13
xorl %ebx, %ebx
movq %r12, 64(%rsp) # 8-byte Spill
jmp .LBB9_28
.p2align 4, 0x90
.LBB9_29: # in Loop: Header=BB9_28 Depth=1
xorps %xmm0, %xmm0
.LBB9_32: # %_Z15calculate_labelPiPfiiii.exit.i
# in Loop: Header=BB9_28 Depth=1
movss %xmm0, 48(%rsp) # 4-byte Spill
movl $10, %edi
callq putchar@PLT
movss 40(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cmpnless 48(%rsp), %xmm0 # 4-byte Folded Reload
movss .LCPI9_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
andnps %xmm1, %xmm0
movss %xmm0, (%r15,%rbx,4)
incq %rbx
addq %r13, %r12
cmpq 56(%rsp), %rbx # 8-byte Folded Reload
je .LBB9_33
.LBB9_28: # =>This Loop Header: Depth=1
# Child Loop BB9_31 Depth 2
cmpl $0, 72(%rsp) # 4-byte Folded Reload
jle .LBB9_29
# %bb.30: # %.lr.ph.i.i
# in Loop: Header=BB9_28 Depth=1
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB9_31: # Parent Loop BB9_28 Depth=1
# => This Inner Loop Header: Depth=2
movslq (%r12,%rax,4), %rcx
addss (%r14,%rcx,4), %xmm0
incq %rax
cmpq %rax, %rbp
jne .LBB9_31
jmp .LBB9_32
.LBB9_33: # %_Z13predict_labelPiPfiii.exit
movl $.Lstr.5, %edi
callq puts@PLT
movq 32(%rsp), %r12 # 8-byte Reload
testl %r12d, %r12d
jle .LBB9_34
# %bb.35: # %.lr.ph.i119.preheader
xorl %eax, %eax
xorl %ecx, %ecx
movq 24(%rsp), %rbx # 8-byte Reload
movq 184(%rsp), %rsi # 8-byte Reload
movq 56(%rsp), %rdi # 8-byte Reload
movq 64(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB9_36: # %.lr.ph.i119
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cmpeqss (%r15,%rax,4), %xmm0
movd %xmm0, %edx
subl %edx, %ecx
incq %rax
cmpq %rax, %rdi
jne .LBB9_36
# %bb.37: # %._crit_edge.loopexit.i
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
jmp .LBB9_39
.LBB9_38: # %_Z18calculate_accuracyPfS_i.exit.critedge
movl $.Lstr.5, %edi
callq puts@PLT
xorps %xmm0, %xmm0
movq 24(%rsp), %rbx # 8-byte Reload
jmp .LBB9_39
.LBB9_34:
xorps %xmm0, %xmm0
movq 24(%rsp), %rbx # 8-byte Reload
movq 64(%rsp), %r13 # 8-byte Reload
.LBB9_39: # %_Z18calculate_accuracyPfS_i.exit
xorps %xmm1, %xmm1
cvtsi2ss %r12d, %xmm1
divss %xmm1, %xmm0
mulss .LCPI9_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
callq clock
subq 272(%rsp), %rax # 8-byte Folded Reload
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
imulq %rcx
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
xorps %xmm0, %xmm0
cvtsi2sd %rdx, %xmm0
movl $.L.str.16, %edi
movb $1, %al
callq printf
movq 88(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
movq %r13, %rdi
callq free
movq 192(%rsp), %rdi # 8-byte Reload
callq free
movq 80(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27calculate_similarity_matrixPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26calculate_nearest_neighborPfPiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27calculate_similarity_matrixPfS_S_iii,@object # @_Z27calculate_similarity_matrixPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z27calculate_similarity_matrixPfS_S_iii
.p2align 3, 0x0
_Z27calculate_similarity_matrixPfS_S_iii:
.quad _Z42__device_stub__calculate_similarity_matrixPfS_S_iii
.size _Z27calculate_similarity_matrixPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f "
.size .L.str.2, 5
.type _Z26calculate_nearest_neighborPfPiiiii,@object # @_Z26calculate_nearest_neighborPfPiiiii
.section .rodata,"a",@progbits
.globl _Z26calculate_nearest_neighborPfPiiiii
.p2align 3, 0x0
_Z26calculate_nearest_neighborPfPiiiii:
.quad _Z41__device_stub__calculate_nearest_neighborPfPiiiii
.size _Z26calculate_nearest_neighborPfPiiiii, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "%d "
.size .L.str.4, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "train.txt"
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "test.txt"
.size .L.str.7, 9
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "label_train.txt"
.size .L.str.8, 16
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "label_test.txt"
.size .L.str.9, 15
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\nPrediction Accuracy: %f"
.size .L.str.15, 25
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "\n\nTime taken for running the program: %lf\n\n"
.size .L.str.16, 44
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27calculate_similarity_matrixPfS_S_iii"
.size .L__unnamed_1, 41
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26calculate_nearest_neighborPfPiiiii"
.size .L__unnamed_2, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n**************** Hello World ! ******************"
.size .Lstr, 51
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Data Read Complete"
.size .Lstr.1, 19
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Similarity matrix building complete"
.size .Lstr.2, 36
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\ncopying similarity matrix from device to host complete"
.size .Lstr.3, 56
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Nearest Neighbour calculation complete"
.size .Lstr.4, 39
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "\nClass label prediction complete"
.size .Lstr.5, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__calculate_similarity_matrixPfS_S_iii
.addrsig_sym _Z41__device_stub__calculate_nearest_neighborPfPiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27calculate_similarity_matrixPfS_S_iii
.addrsig_sym _Z26calculate_nearest_neighborPfPiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void dkernel()
{
printf("Hello World! \n");
}
int main()
{
dkernel<<<1, 32>>>(); //32 threads within 1 thread block
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z7dkernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda.h>
__global__ void dkernel()
{
printf("Hello World! \n");
}
int main()
{
dkernel<<<1, 32>>>(); //32 threads within 1 thread block
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00101ebe_00000000-6_helloWorldParallel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7dkernelvv
.type _Z25__device_stub__Z7dkernelvv, @function
_Z25__device_stub__Z7dkernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7dkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z7dkernelvv, .-_Z25__device_stub__Z7dkernelvv
.globl _Z7dkernelv
.type _Z7dkernelv, @function
_Z7dkernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7dkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7dkernelv, .-_Z7dkernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z25__device_stub__Z7dkernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7dkernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda.h>
__global__ void dkernel()
{
printf("Hello World! \n");
}
int main()
{
dkernel<<<1, 32>>>(); //32 threads within 1 thread block
cudaDeviceSynchronize();
return 0;
} | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void dkernel()
{
printf("Hello World! \n");
}
int main()
{
dkernel<<<1, 32>>>(); //32 threads within 1 thread block
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void dkernel()
{
printf("Hello World! \n");
}
int main()
{
dkernel<<<1, 32>>>(); //32 threads within 1 thread block
hipDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7dkernelv
.globl _Z7dkernelv
.p2align 8
.type _Z7dkernelv,@function
_Z7dkernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 15
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7dkernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7dkernelv, .Lfunc_end0-_Z7dkernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World! \n"
.size .str, 15
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7dkernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z7dkernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
__global__ void dkernel()
{
printf("Hello World! \n");
}
int main()
{
dkernel<<<1, 32>>>(); //32 threads within 1 thread block
hipDeviceSynchronize();
return 0;
} | .text
.file "helloWorldParallel1.hip"
.globl _Z22__device_stub__dkernelv # -- Begin function _Z22__device_stub__dkernelv
.p2align 4, 0x90
.type _Z22__device_stub__dkernelv,@function
_Z22__device_stub__dkernelv: # @_Z22__device_stub__dkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__dkernelv, .Lfunc_end0-_Z22__device_stub__dkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7dkernelv,@object # @_Z7dkernelv
.section .rodata,"a",@progbits
.globl _Z7dkernelv
.p2align 3, 0x0
_Z7dkernelv:
.quad _Z22__device_stub__dkernelv
.size _Z7dkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7dkernelv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__dkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7dkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7dkernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7dkernelv
.globl _Z7dkernelv
.p2align 8
.type _Z7dkernelv,@function
_Z7dkernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 15
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7dkernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7dkernelv, .Lfunc_end0-_Z7dkernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World! \n"
.size .str, 15
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7dkernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z7dkernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00101ebe_00000000-6_helloWorldParallel1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z7dkernelvv
.type _Z25__device_stub__Z7dkernelvv, @function
_Z25__device_stub__Z7dkernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z7dkernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z7dkernelvv, .-_Z25__device_stub__Z7dkernelvv
.globl _Z7dkernelv
.type _Z7dkernelv, @function
_Z7dkernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7dkernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7dkernelv, .-_Z7dkernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z25__device_stub__Z7dkernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7dkernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloWorldParallel1.hip"
.globl _Z22__device_stub__dkernelv # -- Begin function _Z22__device_stub__dkernelv
.p2align 4, 0x90
.type _Z22__device_stub__dkernelv,@function
_Z22__device_stub__dkernelv: # @_Z22__device_stub__dkernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z22__device_stub__dkernelv, .Lfunc_end0-_Z22__device_stub__dkernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z7dkernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7dkernelv,@object # @_Z7dkernelv
.section .rodata,"a",@progbits
.globl _Z7dkernelv
.p2align 3, 0x0
_Z7dkernelv:
.quad _Z22__device_stub__dkernelv
.size _Z7dkernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7dkernelv"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__dkernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7dkernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void interp3_cuda(
float * vOutput,
int nPoints,
int xSize,
int ySize,
int zSize,
float * gridX,
float * gridY,
float * gridZ,
float * vInput,
float * xInterp,
float * yInterp,
float * zInterp)
{
int idx = blockDim.x * (gridDim.x * blockIdx.y + blockIdx.x) + threadIdx.x;
if (idx >= nPoints)
{
return;
}
float x = xInterp[idx];
float y = yInterp[idx];
float z = zInterp[idx];
if (x < gridX[0] || x > gridX[xSize-1] ||
y < gridY[0] || y > gridY[ySize-1] ||
z < gridZ[0] || z > gridZ[zSize-1])
{
vOutput[idx] = 0.0f;
return;
}
float x0, y0, z0, x1, y1, z1;
int ibx, itx, iby, ity, ibz, itz, im;
ibx = 0;
itx = xSize - 1;
while (ibx < (itx-1))
{
im = ((ibx + itx) >> 1);
if (x <= gridX[im])
{
itx = im;
}
else
{
ibx = im;
}
}
x0 = gridX[ibx];
x1 = gridX[itx];
iby = 0;
ity = ySize - 1;
while (iby < (ity-1))
{
im = ((iby + ity) >> 1);
if (y <= gridY[im])
{
ity = im;
}
else
{
iby = im;
}
}
y0 = gridY[iby];
y1 = gridY[ity];
ibz = 0;
itz = zSize - 1;
while (ibz < (itz-1))
{
im = ((ibz + itz) >> 1);
if (z <= gridZ[im])
{
itz = im;
}
else
{
ibz = im;
}
}
z0 = gridZ[ibz];
z1 = gridZ[itz];
int sliceDim = xSize * ySize;
int zOff0 = sliceDim * ibz;
int zOff1 = zOff0 + sliceDim;
int yOff0 = ySize * ibx;
int yOff1 = yOff0 + ySize;
float ax0 = (x - x0) / (x1 - x0);
float ay0 = (y - y0) / (y1 - y0);
float az0 = (z - z0) / (z1 - z0);
float ax1 = 1.0f - ax0;
float ay1 = 1.0f - ay0;
float v000 = vInput[zOff0 + yOff0 + iby];
float v001 = vInput[zOff0 + yOff0 + ity];
float v010 = vInput[zOff0 + yOff1 + iby];
float v011 = vInput[zOff0 + yOff1 + ity];
float v100 = vInput[zOff1 + yOff0 + iby];
float v101 = vInput[zOff1 + yOff0 + ity];
float v110 = vInput[zOff1 + yOff1 + iby];
float v111 = vInput[zOff1 + yOff1 + ity];
float v00 = v000 * ay1 + v001 * ay0;
float v01 = v010 * ay1 + v011 * ay0;
float v10 = v100 * ay1 + v101 * ay0;
float v11 = v110 * ay1 + v111 * ay0;
float v0 = v00 * ax1 + v01 * ax0;
float v1 = v10 * ax1 + v11 * ax0;
vOutput[idx] = v0 * (1.0f - az0) + v1 * az0;
} | code for sm_80
Function : _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R15, R0, c[0x0][0x0], R15 ; /* 0x00000000000f7a24 */
/* 0x002fca00078e020f */
/*0060*/ ISETP.GE.AND P0, PT, R15, c[0x0][0x168], PT ; /* 0x00005a000f007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; /* 0x00000004ff0c7424 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.WIDE R4, R15, R12, c[0x0][0x198] ; /* 0x000066000f047625 */
/* 0x000fc600078e020c */
/*00d0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ BSSY B0, 0xd20 ; /* 0x00000c2000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.WIDE R2, R15, R12, c[0x0][0x160] ; /* 0x000058000f027625 */
/* 0x000fe200078e020c */
/*0110*/ FSETP.GEU.AND P0, PT, R11, R0, PT ; /* 0x000000000b00720b */
/* 0x004fda0003f0e000 */
/*0120*/ @!P0 BRA 0xd10 ; /* 0x00000be000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff047624 */
/* 0x000fca00078e00ff */
/*0140*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fca0007ffe0ff */
/*0150*/ IMAD.WIDE R6, R5, R12, c[0x0][0x178] ; /* 0x00005e0005067625 */
/* 0x000fca00078e020c */
/*0160*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000ea4000c1e1900 */
/*0170*/ FSETP.GT.AND P0, PT, R11, R21, PT ; /* 0x000000150b00720b */
/* 0x004fda0003f04000 */
/*0180*/ @P0 BRA 0xd10 ; /* 0x00000b8000000947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.WIDE R6, R15, R12, c[0x0][0x1a0] ; /* 0x000068000f067625 */
/* 0x000fe200078e020c */
/*01a0*/ MOV R8, c[0x0][0x180] ; /* 0x0000600000087a02 */
/* 0x000fc60000000f00 */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe200078e00ff */
/*01c0*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FSETP.GEU.AND P0, PT, R10, R19, PT ; /* 0x000000130a00720b */
/* 0x004fda0003f0e000 */
/*01f0*/ @!P0 BRA 0xd10 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*0200*/ MOV R9, c[0x0][0x170] ; /* 0x00005c0000097a02 */
/* 0x000fc80000000f00 */
/*0210*/ IADD3 R13, R9, -0x1, RZ ; /* 0xffffffff090d7810 */
/* 0x000fca0007ffe0ff */
/*0220*/ IMAD.WIDE R6, R13, R12, c[0x0][0x180] ; /* 0x000060000d067625 */
/* 0x000fca00078e020c */
/*0230*/ LDG.E R22, [R6.64] ; /* 0x0000000406167981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FSETP.GT.AND P0, PT, R10, R22, PT ; /* 0x000000160a00720b */
/* 0x004fda0003f04000 */
/*0250*/ @P0 BRA 0xd10 ; /* 0x00000ab000000947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.WIDE R14, R15, R12, c[0x0][0x1a8] ; /* 0x00006a000f0e7625 */
/* 0x000fe200078e020c */
/*0270*/ MOV R7, c[0x0][0x18c] ; /* 0x0000630000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x000fe200078e00ff */
/*0290*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ FSETP.GEU.AND P0, PT, R8, R17, PT ; /* 0x000000110800720b */
/* 0x004fda0003f0e000 */
/*02c0*/ @!P0 BRA 0xd10 ; /* 0x00000a4000008947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff127624 */
/* 0x000fca00078e00ff */
/*02e0*/ IADD3 R15, R18, -0x1, RZ ; /* 0xffffffff120f7810 */
/* 0x000fca0007ffe0ff */
/*02f0*/ IMAD.WIDE R6, R15, R12, c[0x0][0x188] ; /* 0x000062000f067625 */
/* 0x000fca00078e020c */
/*0300*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FSETP.GT.AND P0, PT, R8, R20, PT ; /* 0x000000140800720b */
/* 0x004fda0003f04000 */
/*0320*/ @P0 BRA 0xd10 ; /* 0x000009e000000947 */
/* 0x000fea0003800000 */
/*0330*/ ISETP.GE.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06270 */
/*0340*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*0350*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd600078e00ff */
/*0360*/ @!P0 BRA 0x490 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0370*/ BSSY B1, 0x450 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0380*/ MOV R7, R5 ; /* 0x0000000500077202 */
/* 0x000fe20000000f00 */
/*0390*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fca00078e00ff */
/*03a0*/ IADD3 R0, R16, R7, RZ ; /* 0x0000000710007210 */
/* 0x000fc80007ffe0ff */
/*03b0*/ SHF.R.S32.HI R21, RZ, 0x1, R0 ; /* 0x00000001ff157819 */
/* 0x000fca0000011400 */
/*03c0*/ IMAD.WIDE R4, R21, R12, c[0x0][0x178] ; /* 0x00005e0015047625 */
/* 0x000fcc00078e020c */
/*03d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ FSETP.GTU.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720b */
/* 0x004fc80003f0c000 */
/*03f0*/ SEL R7, R21, R7, !P0 ; /* 0x0000000715077207 */
/* 0x000fe40004000000 */
/*0400*/ SEL R16, R16, R21, !P0 ; /* 0x0000001510107207 */
/* 0x000fe40004000000 */
/*0410*/ IADD3 R21, R7, -0x1, RZ ; /* 0xffffffff07157810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GE.AND P0, PT, R16, R21, PT ; /* 0x000000151000720c */
/* 0x000fda0003f06270 */
/*0430*/ @!P0 BRA 0x3a0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0440*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0450*/ IMAD.WIDE R6, R7, R12, c[0x0][0x178] ; /* 0x00005e0007067625 */
/* 0x000fc800078e020c */
/*0460*/ IMAD.WIDE R4, R16, R12, c[0x0][0x178] ; /* 0x00005e0010047625 */
/* 0x000fe200078e020c */
/*0470*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000168000c1e1900 */
/*0480*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000164000c1e1900 */
/*0490*/ ISETP.GE.AND P0, PT, R9, 0x3, PT ; /* 0x000000030900780c */
/* 0x000fda0003f06270 */
/*04a0*/ @!P0 BRA 0x5c0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*04b0*/ BSSY B1, 0x580 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*04c0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fca00078e00ff */
/*04d0*/ IADD3 R4, R14, R13, RZ ; /* 0x0000000d0e047210 */
/* 0x001fc80007ffe0ff */
/*04e0*/ SHF.R.S32.HI R7, RZ, 0x1, R4 ; /* 0x00000001ff077819 */
/* 0x000fca0000011404 */
/*04f0*/ IMAD.WIDE R4, R7, R12, c[0x0][0x180] ; /* 0x0000600007047625 */
/* 0x000fcc00078e020c */
/*0500*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0510*/ FSETP.GTU.AND P0, PT, R10, R5, PT ; /* 0x000000050a00720b */
/* 0x004fc80003f0c000 */
/*0520*/ SEL R13, R7, R13, !P0 ; /* 0x0000000d070d7207 */
/* 0x000fe40004000000 */
/*0530*/ SEL R14, R14, R7, !P0 ; /* 0x000000070e0e7207 */
/* 0x000fe40004000000 */
/*0540*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fc80007ffe0ff */
/*0550*/ ISETP.GE.AND P0, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x000fda0003f06270 */
/*0560*/ @!P0 BRA 0x4d0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0570*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0580*/ IMAD.WIDE R6, R14, R12, c[0x0][0x180] ; /* 0x000060000e067625 */
/* 0x000fc800078e020c */
/*0590*/ IMAD.WIDE R4, R13, R12, c[0x0][0x180] ; /* 0x000060000d047625 */
/* 0x000fe200078e020c */
/*05a0*/ LDG.E R19, [R6.64] ; /* 0x0000000406137981 */
/* 0x000168000c1e1900 */
/*05b0*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000164000c1e1900 */
/*05c0*/ ISETP.GE.AND P0, PT, R18, 0x3, PT ; /* 0x000000031200780c */
/* 0x000fe20003f06270 */
/*05d0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fd800078e00ff */
/*05e0*/ @!P0 BRA 0x700 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*05f0*/ BSSY B1, 0x6c0 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*0600*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fca0000000f00 */
/*0610*/ IMAD.IADD R4, R18, 0x1, R15 ; /* 0x0000000112047824 */
/* 0x001fca00078e020f */
/*0620*/ SHF.R.S32.HI R7, RZ, 0x1, R4 ; /* 0x00000001ff077819 */
/* 0x000fca0000011404 */
/*0630*/ IMAD.WIDE R4, R7, R12, c[0x0][0x188] ; /* 0x0000620007047625 */
/* 0x000fcc00078e020c */
/*0640*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0650*/ FSETP.GTU.AND P0, PT, R8, R5, PT ; /* 0x000000050800720b */
/* 0x004fc80003f0c000 */
/*0660*/ SEL R15, R7, R15, !P0 ; /* 0x0000000f070f7207 */
/* 0x000fe40004000000 */
/*0670*/ SEL R18, R18, R7, !P0 ; /* 0x0000000712127207 */
/* 0x000fe40004000000 */
/*0680*/ IADD3 R7, R15, -0x1, RZ ; /* 0xffffffff0f077810 */
/* 0x000fc80007ffe0ff */
/*0690*/ ISETP.GE.AND P0, PT, R18, R7, PT ; /* 0x000000071200720c */
/* 0x000fda0003f06270 */
/*06a0*/ @!P0 BRA 0x610 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*06b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R4, R18, R12, c[0x0][0x188] ; /* 0x0000620012047625 */
/* 0x000fc800078e020c */
/*06d0*/ IMAD.WIDE R6, R15, R12, c[0x0][0x188] ; /* 0x000062000f067625 */
/* 0x000fe200078e020c */
/*06e0*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000168000c1e1900 */
/*06f0*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000164000c1e1900 */
/*0700*/ FADD R24, R21, -R0.reuse ; /* 0x8000000015187221 */
/* 0x120fe20000000000 */
/*0710*/ BSSY B1, 0x830 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*0720*/ FADD R21, R11, -R0 ; /* 0x800000000b157221 */
/* 0x000fe40000000000 */
/*0730*/ MUFU.RCP R4, R24 ; /* 0x0000001800047308 */
/* 0x001e220000001000 */
/*0740*/ IMAD R12, R16, R9, c[0x0][0x170] ; /* 0x00005c00100c7624 */
/* 0x000fce00078e0209 */
/*0750*/ FCHK P0, R21, R24 ; /* 0x0000001815007302 */
/* 0x000e620000000000 */
/*0760*/ FFMA R5, -R24, R4, 1 ; /* 0x3f80000018057423 */
/* 0x001fc80000000104 */
/*0770*/ FFMA R5, R4, R5, R4 ; /* 0x0000000504057223 */
/* 0x000fe40000000004 */
/*0780*/ IMAD R4, R9, c[0x0][0x16c], RZ ; /* 0x00005b0009047a24 */
/* 0x000fe400078e02ff */
/*0790*/ FFMA R0, R21, R5, RZ ; /* 0x0000000515007223 */
/* 0x000fe400000000ff */
/*07a0*/ IMAD R7, R4, R18, RZ ; /* 0x0000001204077224 */
/* 0x000fe400078e02ff */
/*07b0*/ FFMA R6, -R24, R0, R21 ; /* 0x0000000018067223 */
/* 0x000fc60000000115 */
/*07c0*/ IADD3 R9, R4, R7, RZ ; /* 0x0000000704097210 */
/* 0x000fe20007ffe0ff */
/*07d0*/ FFMA R0, R5, R6, R0 ; /* 0x0000000605007223 */
/* 0x000fe20000000000 */
/*07e0*/ @!P0 BRA 0x820 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*07f0*/ MOV R4, 0x810 ; /* 0x0000081000047802 */
/* 0x000fe40000000f00 */
/*0800*/ CALL.REL.NOINC 0xd40 ; /* 0x0000053000007944 */
/* 0x000fea0003c00000 */
/*0810*/ IMAD.MOV.U32 R0, RZ, RZ, R15 ; /* 0x000000ffff007224 */
/* 0x001fe400078e000f */
/*0820*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0830*/ FADD R24, R22, -R19.reuse ; /* 0x8000001316187221 */
/* 0x100fe20000000000 */
/*0840*/ BSSY B1, 0x920 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0850*/ FADD R21, R10, -R19 ; /* 0x800000130a157221 */
/* 0x000fe40000000000 */
/*0860*/ MUFU.RCP R4, R24 ; /* 0x0000001800047308 */
/* 0x000e300000001000 */
/*0870*/ FCHK P0, R21, R24 ; /* 0x0000001815007302 */
/* 0x000e620000000000 */
/*0880*/ FFMA R5, -R24, R4, 1 ; /* 0x3f80000018057423 */
/* 0x001fc80000000104 */
/*0890*/ FFMA R5, R4, R5, R4 ; /* 0x0000000504057223 */
/* 0x000fc80000000004 */
/*08a0*/ FFMA R6, R21, R5, RZ ; /* 0x0000000515067223 */
/* 0x000fc800000000ff */
/*08b0*/ FFMA R4, -R24, R6, R21 ; /* 0x0000000618047223 */
/* 0x000fc80000000115 */
/*08c0*/ FFMA R6, R5, R4, R6 ; /* 0x0000000405067223 */
/* 0x000fe20000000006 */
/*08d0*/ @!P0 BRA 0x910 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*08e0*/ MOV R4, 0x900 ; /* 0x0000090000047802 */
/* 0x000fe40000000f00 */
/*08f0*/ CALL.REL.NOINC 0xd40 ; /* 0x0000044000007944 */
/* 0x000fea0003c00000 */
/*0900*/ MOV R6, R15 ; /* 0x0000000f00067202 */
/* 0x001fe40000000f00 */
/*0910*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0920*/ FADD R24, R20, -R17.reuse ; /* 0x8000001114187221 */
/* 0x100fe20000000000 */
/*0930*/ BSSY B1, 0xa10 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0940*/ FADD R21, R8, -R17 ; /* 0x8000001108157221 */
/* 0x000fe40000000000 */
/*0950*/ MUFU.RCP R4, R24 ; /* 0x0000001800047308 */
/* 0x000e300000001000 */
/*0960*/ FCHK P0, R21, R24 ; /* 0x0000001815007302 */
/* 0x000e620000000000 */
/*0970*/ FFMA R5, -R24, R4, 1 ; /* 0x3f80000018057423 */
/* 0x001fc80000000104 */
/*0980*/ FFMA R4, R4, R5, R4 ; /* 0x0000000504047223 */
/* 0x000fc80000000004 */
/*0990*/ FFMA R5, R21, R4, RZ ; /* 0x0000000415057223 */
/* 0x000fc800000000ff */
/*09a0*/ FFMA R8, -R24, R5, R21 ; /* 0x0000000518087223 */
/* 0x000fc80000000115 */
/*09b0*/ FFMA R4, R4, R8, R5 ; /* 0x0000000804047223 */
/* 0x000fe20000000005 */
/*09c0*/ @!P0 BRA 0xa00 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*09d0*/ MOV R4, 0x9f0 ; /* 0x000009f000047802 */
/* 0x000fe40000000f00 */
/*09e0*/ CALL.REL.NOINC 0xd40 ; /* 0x0000035000007944 */
/* 0x000fea0003c00000 */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, R15 ; /* 0x000000ffff047224 */
/* 0x001fe400078e000f */
/*0a00*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD R10, R16.reuse, c[0x0][0x170], R9 ; /* 0x00005c00100a7a24 */
/* 0x040fe200078e0209 */
/*0a20*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0a30*/ IMAD.IADD R9, R9, 0x1, R12 ; /* 0x0000000109097824 */
/* 0x000fe400078e020c */
/*0a40*/ IMAD R8, R16, c[0x0][0x170], R7 ; /* 0x00005c0010087a24 */
/* 0x000fe200078e0207 */
/*0a50*/ IADD3 R7, R7, R12, RZ ; /* 0x0000000c07077210 */
/* 0x000fe20007ffe0ff */
/*0a60*/ IMAD.IADD R12, R10.reuse, 0x1, R13.reuse ; /* 0x000000010a0c7824 */
/* 0x140fe200078e020d */
/*0a70*/ IADD3 R26, R9, R13, RZ ; /* 0x0000000d091a7210 */
/* 0x000fe20007ffe0ff */
/*0a80*/ IMAD.IADD R22, R10, 0x1, R14 ; /* 0x000000010a167824 */
/* 0x000fe200078e020e */
/*0a90*/ IADD3 R20, R7.reuse, R14.reuse, RZ ; /* 0x0000000e07147210 */
/* 0x0c0fe20007ffe0ff */
/*0aa0*/ IMAD.IADD R18, R7, 0x1, R13 ; /* 0x0000000107127824 */
/* 0x000fe200078e020d */
/*0ab0*/ IADD3 R24, R9, R14, RZ ; /* 0x0000000e09187210 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ IMAD.WIDE R10, R26, R5, c[0x0][0x190] ; /* 0x000064001a0a7625 */
/* 0x000fc800078e0205 */
/*0ad0*/ IMAD.IADD R16, R8.reuse, 0x1, R13 ; /* 0x0000000108107824 */
/* 0x040fe200078e020d */
/*0ae0*/ IADD3 R8, R8, R14, RZ ; /* 0x0000000e08087210 */
/* 0x000fe20007ffe0ff */
/*0af0*/ IMAD.WIDE R12, R12, R5.reuse, c[0x0][0x190] ; /* 0x000064000c0c7625 */
/* 0x080fe200078e0205 */
/*0b00*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea6000c1e1900 */
/*0b10*/ IMAD.WIDE R14, R20, R5.reuse, c[0x0][0x190] ; /* 0x00006400140e7625 */
/* 0x080fe400078e0205 */
/*0b20*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ IMAD.WIDE R18, R18, R5, c[0x0][0x190] ; /* 0x0000640012127625 */
/* 0x000fc400078e0205 */
/*0b40*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f24000c1e1900 */
/*0b50*/ IMAD.WIDE R20, R24, R5.reuse, c[0x0][0x190] ; /* 0x0000640018147625 */
/* 0x080fe400078e0205 */
/*0b60*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f64000c1e1900 */
/*0b70*/ IMAD.WIDE R16, R16, R5.reuse, c[0x0][0x190] ; /* 0x0000640010107625 */
/* 0x080fe400078e0205 */
/*0b80*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f24000c1e1900 */
/*0b90*/ IMAD.WIDE R22, R22, R5, c[0x0][0x190] ; /* 0x0000640016167625 */
/* 0x000fc400078e0205 */
/*0ba0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000524000c1e1900 */
/*0bb0*/ IMAD.WIDE R8, R8, R5, c[0x0][0x190] ; /* 0x0000640008087625 */
/* 0x000fe400078e0205 */
/*0bc0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f28000c1e1900 */
/*0bd0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f22000c1e1900 */
/*0be0*/ FADD R7, -R6, 1 ; /* 0x3f80000006077421 */
/* 0x000fe40000000100 */
/*0bf0*/ FMUL R16, R11, R6 ; /* 0x000000060b107220 */
/* 0x004fc40000400000 */
/*0c00*/ FMUL R5, R13, R6.reuse ; /* 0x000000060d057220 */
/* 0x088fe40000400000 */
/*0c10*/ FMUL R19, R19, R6 ; /* 0x0000000613137220 */
/* 0x020fe40000400000 */
/*0c20*/ FFMA R11, R7.reuse, R20, R16 ; /* 0x00000014070b7223 */
/* 0x050fe40000000010 */
/*0c30*/ FFMA R19, R7, R14, R19 ; /* 0x0000000e07137223 */
/* 0x000fe40000000013 */
/*0c40*/ FMUL R17, R17, R6 ; /* 0x0000000611117220 */
/* 0x000fe40000400000 */
/*0c50*/ FMUL R11, R11, R0 ; /* 0x000000000b0b7220 */
/* 0x000fc40000400000 */
/*0c60*/ FFMA R6, R7.reuse, R22, R5 ; /* 0x0000001607067223 */
/* 0x040fe40000000005 */
/*0c70*/ FADD R5, -R0, 1 ; /* 0x3f80000000057421 */
/* 0x000fe40000000100 */
/*0c80*/ FFMA R8, R7, R8, R17 ; /* 0x0000000807087223 */
/* 0x000fe40000000011 */
/*0c90*/ FMUL R19, R19, R0 ; /* 0x0000000013137220 */
/* 0x000fe40000400000 */
/*0ca0*/ FFMA R11, R5, R6, R11 ; /* 0x00000006050b7223 */
/* 0x000fe4000000000b */
/*0cb0*/ FADD R7, -R4, 1 ; /* 0x3f80000004077421 */
/* 0x000fc40000000100 */
/*0cc0*/ FFMA R8, R5, R8, R19 ; /* 0x0000000805087223 */
/* 0x000fe40000000013 */
/*0cd0*/ FMUL R11, R11, R4 ; /* 0x000000040b0b7220 */
/* 0x000fc80000400000 */
/*0ce0*/ FFMA R7, R8, R7, R11 ; /* 0x0000000708077223 */
/* 0x000fca000000000b */
/*0cf0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0d00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d20*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0d30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d40*/ SHF.R.U32.HI R5, RZ, 0x17, R24 ; /* 0x00000017ff057819 */
/* 0x000fe20000011618 */
/*0d50*/ BSSY B2, 0x1380 ; /* 0x0000062000027945 */
/* 0x000fe20003800000 */
/*0d60*/ SHF.R.U32.HI R18, RZ, 0x17, R21 ; /* 0x00000017ff127819 */
/* 0x000fe40000011615 */
/*0d70*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0d80*/ LOP3.LUT R18, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12127812 */
/* 0x000fe400078ec0ff */
/*0d90*/ IADD3 R23, R5, -0x1, RZ ; /* 0xffffffff05177810 */
/* 0x000fc40007ffe0ff */
/*0da0*/ IADD3 R15, R18, -0x1, RZ ; /* 0xffffffff120f7810 */
/* 0x000fe40007ffe0ff */
/*0db0*/ ISETP.GT.U32.AND P0, PT, R23, 0xfd, PT ; /* 0x000000fd1700780c */
/* 0x000fc80003f04070 */
/*0dc0*/ ISETP.GT.U32.OR P0, PT, R15, 0xfd, P0 ; /* 0x000000fd0f00780c */
/* 0x000fda0000704470 */
/*0dd0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b8224 */
/* 0x000fe200078e00ff */
/*0de0*/ @!P0 BRA 0xf60 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0df0*/ FSETP.GTU.FTZ.AND P0, PT, |R21|, +INF , PT ; /* 0x7f8000001500780b */
/* 0x000fe40003f1c200 */
/*0e00*/ FSETP.GTU.FTZ.AND P1, PT, |R24|, +INF , PT ; /* 0x7f8000001800780b */
/* 0x000fc80003f3c200 */
/*0e10*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0e20*/ @P0 BRA 0x1360 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0e30*/ LOP3.LUT P0, RZ, R24, 0x7fffffff, R21, 0xc8, !PT ; /* 0x7fffffff18ff7812 */
/* 0x000fda000780c815 */
/*0e40*/ @!P0 BRA 0x1340 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0e50*/ FSETP.NEU.FTZ.AND P2, PT, |R21|.reuse, +INF , PT ; /* 0x7f8000001500780b */
/* 0x040fe40003f5d200 */
/*0e60*/ FSETP.NEU.FTZ.AND P1, PT, |R24|, +INF , PT ; /* 0x7f8000001800780b */
/* 0x000fe40003f3d200 */
/*0e70*/ FSETP.NEU.FTZ.AND P0, PT, |R21|, +INF , PT ; /* 0x7f8000001500780b */
/* 0x000fd60003f1d200 */
/*0e80*/ @!P1 BRA !P2, 0x1340 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0e90*/ LOP3.LUT P2, RZ, R21, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff15ff7812 */
/* 0x000fc8000784c0ff */
/*0ea0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0eb0*/ @P1 BRA 0x1320 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0ec0*/ LOP3.LUT P1, RZ, R24, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff18ff7812 */
/* 0x000fc8000782c0ff */
/*0ed0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0ee0*/ @P0 BRA 0x12f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0ef0*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f06270 */
/*0f00*/ ISETP.GE.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fd60003f26270 */
/*0f10*/ @P0 MOV R11, RZ ; /* 0x000000ff000b0202 */
/* 0x000fe20000000f00 */
/*0f20*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, -0x40 ; /* 0xffffffc0ff0b8424 */
/* 0x000fe400078e00ff */
/*0f30*/ @!P0 FFMA R21, R21, 1.84467440737095516160e+19, RZ ; /* 0x5f80000015158823 */
/* 0x000fe400000000ff */
/*0f40*/ @!P1 FFMA R24, R24, 1.84467440737095516160e+19, RZ ; /* 0x5f80000018189823 */
/* 0x000fe200000000ff */
/*0f50*/ @!P1 IADD3 R11, R11, 0x40, RZ ; /* 0x000000400b0b9810 */
/* 0x000fe40007ffe0ff */
/*0f60*/ LEA R15, R5, 0xc0800000, 0x17 ; /* 0xc0800000050f7811 */
/* 0x000fe200078eb8ff */
/*0f70*/ BSSY B3, 0x12e0 ; /* 0x0000036000037945 */
/* 0x000fe20003800000 */
/*0f80*/ IADD3 R18, R18, -0x7f, RZ ; /* 0xffffff8112127810 */
/* 0x000fe40007ffe0ff */
/*0f90*/ IADD3 R25, -R15, R24, RZ ; /* 0x000000180f197210 */
/* 0x000fc60007ffe1ff */
/*0fa0*/ IMAD R26, R18.reuse, -0x800000, R21 ; /* 0xff800000121a7824 */
/* 0x040fe200078e0215 */
/*0fb0*/ MUFU.RCP R24, R25 ; /* 0x0000001900187308 */
/* 0x000e220000001000 */
/*0fc0*/ FADD.FTZ R15, -R25, -RZ ; /* 0x800000ff190f7221 */
/* 0x000fe20000010100 */
/*0fd0*/ IADD3 R18, R18, 0x7f, -R5 ; /* 0x0000007f12127810 */
/* 0x000fca0007ffe805 */
/*0fe0*/ IMAD.IADD R18, R18, 0x1, R11 ; /* 0x0000000112127824 */
/* 0x000fe400078e020b */
/*0ff0*/ FFMA R23, R24, R15, 1 ; /* 0x3f80000018177423 */
/* 0x001fc8000000000f */
/*1000*/ FFMA R21, R24, R23, R24 ; /* 0x0000001718157223 */
/* 0x000fc80000000018 */
/*1010*/ FFMA R24, R26, R21, RZ ; /* 0x000000151a187223 */
/* 0x000fc800000000ff */
/*1020*/ FFMA R23, R15, R24, R26 ; /* 0x000000180f177223 */
/* 0x000fc8000000001a */
/*1030*/ FFMA R24, R21, R23, R24 ; /* 0x0000001715187223 */
/* 0x000fc80000000018 */
/*1040*/ FFMA R23, R15, R24, R26 ; /* 0x000000180f177223 */
/* 0x000fc8000000001a */
/*1050*/ FFMA R15, R21, R23, R24 ; /* 0x00000017150f7223 */
/* 0x000fca0000000018 */
/*1060*/ SHF.R.U32.HI R5, RZ, 0x17, R15 ; /* 0x00000017ff057819 */
/* 0x000fc8000001160f */
/*1070*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*1080*/ IADD3 R5, R5, R18, RZ ; /* 0x0000001205057210 */
/* 0x000fc80007ffe0ff */
/*1090*/ IADD3 R11, R5, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x000fc80007ffe0ff */
/*10a0*/ ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f06070 */
/*10b0*/ @!P0 BRA 0x12c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*10c0*/ ISETP.GT.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f04270 */
/*10d0*/ @P0 BRA 0x1290 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*10e0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*10f0*/ @P0 BRA 0x12d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*1100*/ ISETP.GE.AND P0, PT, R5, -0x18, PT ; /* 0xffffffe80500780c */
/* 0x000fe40003f06270 */
/*1110*/ LOP3.LUT R15, R15, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000f0f7812 */
/* 0x000fd600078ec0ff */
/*1120*/ @!P0 BRA 0x12d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*1130*/ FFMA.RZ R11, R21, R23.reuse, R24.reuse ; /* 0x00000017150b7223 */
/* 0x180fe2000000c018 */
/*1140*/ ISETP.NE.AND P2, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720c */
/* 0x040fe40003f45270 */
/*1150*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f25270 */
/*1160*/ LOP3.LUT R18, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b127812 */
/* 0x000fe200078ec0ff */
/*1170*/ FFMA.RP R11, R21.reuse, R23.reuse, R24.reuse ; /* 0x00000017150b7223 */
/* 0x1c0fe40000008018 */
/*1180*/ FFMA.RM R24, R21, R23, R24 ; /* 0x0000001715187223 */
/* 0x000fe20000004018 */
/*1190*/ IADD3 R21, R5, 0x20, RZ ; /* 0x0000002005157810 */
/* 0x000fe20007ffe0ff */
/*11a0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a05 */
/*11b0*/ LOP3.LUT R18, R18, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000012127812 */
/* 0x000fc400078efcff */
/*11c0*/ FSETP.NEU.FTZ.AND P0, PT, R11, R24, PT ; /* 0x000000180b00720b */
/* 0x000fe40003f1d000 */
/*11d0*/ SHF.L.U32 R21, R18, R21, RZ ; /* 0x0000001512157219 */
/* 0x000fe400000006ff */
/*11e0*/ SEL R5, R5, RZ, P2 ; /* 0x000000ff05057207 */
/* 0x000fe40001000000 */
/*11f0*/ ISETP.NE.AND P1, PT, R21, RZ, P1 ; /* 0x000000ff1500720c */
/* 0x000fe40000f25270 */
/*1200*/ SHF.R.U32.HI R5, RZ, R5, R18 ; /* 0x00000005ff057219 */
/* 0x000fe40000011612 */
/*1210*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*1220*/ SHF.R.U32.HI R18, RZ, 0x1, R5 ; /* 0x00000001ff127819 */
/* 0x000fe40000011605 */
/*1230*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*1240*/ LOP3.LUT R24, R11, 0x1, R18, 0xf8, !PT ; /* 0x000000010b187812 */
/* 0x000fc800078ef812 */
/*1250*/ LOP3.LUT R5, R24, R5, RZ, 0xc0, !PT ; /* 0x0000000518057212 */
/* 0x000fc800078ec0ff */
/*1260*/ IADD3 R18, R18, R5, RZ ; /* 0x0000000512127210 */
/* 0x000fc80007ffe0ff */
/*1270*/ LOP3.LUT R15, R18, R15, RZ, 0xfc, !PT ; /* 0x0000000f120f7212 */
/* 0x000fe200078efcff */
/*1280*/ BRA 0x12d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1290*/ LOP3.LUT R15, R15, 0x80000000, RZ, 0xc0, !PT ; /* 0x800000000f0f7812 */
/* 0x000fc800078ec0ff */
/*12a0*/ LOP3.LUT R15, R15, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000f0f7812 */
/* 0x000fe200078efcff */
/*12b0*/ BRA 0x12d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*12c0*/ IMAD R15, R18, 0x800000, R15 ; /* 0x00800000120f7824 */
/* 0x000fe400078e020f */
/*12d0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*12e0*/ BRA 0x1370 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*12f0*/ LOP3.LUT R15, R24, 0x80000000, R21, 0x48, !PT ; /* 0x80000000180f7812 */
/* 0x000fc800078e4815 */
/*1300*/ LOP3.LUT R15, R15, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f8000000f0f7812 */
/* 0x000fe200078efcff */
/*1310*/ BRA 0x1370 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1320*/ LOP3.LUT R15, R24, 0x80000000, R21, 0x48, !PT ; /* 0x80000000180f7812 */
/* 0x000fe200078e4815 */
/*1330*/ BRA 0x1370 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1340*/ MUFU.RSQ R15, -QNAN ; /* 0xffc00000000f7908 */
/* 0x000e220000001400 */
/*1350*/ BRA 0x1370 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1360*/ FADD.FTZ R15, R21, R24 ; /* 0x00000018150f7221 */
/* 0x000fe40000010000 */
/*1370*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1380*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fcc00000001ff */
/*1390*/ RET.REL.NODEC R4 0x0 ; /* 0xffffec6004007950 */
/* 0x000fea0003c3ffff */
/*13a0*/ BRA 0x13a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void interp3_cuda(
float * vOutput,
int nPoints,
int xSize,
int ySize,
int zSize,
float * gridX,
float * gridY,
float * gridZ,
float * vInput,
float * xInterp,
float * yInterp,
float * zInterp)
{
int idx = blockDim.x * (gridDim.x * blockIdx.y + blockIdx.x) + threadIdx.x;
if (idx >= nPoints)
{
return;
}
float x = xInterp[idx];
float y = yInterp[idx];
float z = zInterp[idx];
if (x < gridX[0] || x > gridX[xSize-1] ||
y < gridY[0] || y > gridY[ySize-1] ||
z < gridZ[0] || z > gridZ[zSize-1])
{
vOutput[idx] = 0.0f;
return;
}
float x0, y0, z0, x1, y1, z1;
int ibx, itx, iby, ity, ibz, itz, im;
ibx = 0;
itx = xSize - 1;
while (ibx < (itx-1))
{
im = ((ibx + itx) >> 1);
if (x <= gridX[im])
{
itx = im;
}
else
{
ibx = im;
}
}
x0 = gridX[ibx];
x1 = gridX[itx];
iby = 0;
ity = ySize - 1;
while (iby < (ity-1))
{
im = ((iby + ity) >> 1);
if (y <= gridY[im])
{
ity = im;
}
else
{
iby = im;
}
}
y0 = gridY[iby];
y1 = gridY[ity];
ibz = 0;
itz = zSize - 1;
while (ibz < (itz-1))
{
im = ((ibz + itz) >> 1);
if (z <= gridZ[im])
{
itz = im;
}
else
{
ibz = im;
}
}
z0 = gridZ[ibz];
z1 = gridZ[itz];
int sliceDim = xSize * ySize;
int zOff0 = sliceDim * ibz;
int zOff1 = zOff0 + sliceDim;
int yOff0 = ySize * ibx;
int yOff1 = yOff0 + ySize;
float ax0 = (x - x0) / (x1 - x0);
float ay0 = (y - y0) / (y1 - y0);
float az0 = (z - z0) / (z1 - z0);
float ax1 = 1.0f - ax0;
float ay1 = 1.0f - ay0;
float v000 = vInput[zOff0 + yOff0 + iby];
float v001 = vInput[zOff0 + yOff0 + ity];
float v010 = vInput[zOff0 + yOff1 + iby];
float v011 = vInput[zOff0 + yOff1 + ity];
float v100 = vInput[zOff1 + yOff0 + iby];
float v101 = vInput[zOff1 + yOff0 + ity];
float v110 = vInput[zOff1 + yOff1 + iby];
float v111 = vInput[zOff1 + yOff1 + ity];
float v00 = v000 * ay1 + v001 * ay0;
float v01 = v010 * ay1 + v011 * ay0;
float v10 = v100 * ay1 + v101 * ay0;
float v11 = v110 * ay1 + v111 * ay0;
float v0 = v00 * ax1 + v01 * ax0;
float v1 = v10 * ax1 + v11 * ax0;
vOutput[idx] = v0 * (1.0f - az0) + v1 * az0;
} | .file "tmpxft_0005febb_00000000-6_interp3_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_
.type _Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_, @function
_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movl %esi, 68(%rsp)
movl %edx, 64(%rsp)
movl %ecx, 60(%rsp)
movl %r8d, 56(%rsp)
movq %r9, 48(%rsp)
movq 272(%rsp), %rax
movq %rax, 40(%rsp)
movq 280(%rsp), %rax
movq %rax, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 296(%rsp), %rax
movq %rax, 16(%rsp)
movq 304(%rsp), %rax
movq %rax, 8(%rsp)
movq 312(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 68(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_, .-_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_
.globl _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.type _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, @function
_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, .-_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void interp3_cuda(
float * vOutput,
int nPoints,
int xSize,
int ySize,
int zSize,
float * gridX,
float * gridY,
float * gridZ,
float * vInput,
float * xInterp,
float * yInterp,
float * zInterp)
{
int idx = blockDim.x * (gridDim.x * blockIdx.y + blockIdx.x) + threadIdx.x;
if (idx >= nPoints)
{
return;
}
float x = xInterp[idx];
float y = yInterp[idx];
float z = zInterp[idx];
if (x < gridX[0] || x > gridX[xSize-1] ||
y < gridY[0] || y > gridY[ySize-1] ||
z < gridZ[0] || z > gridZ[zSize-1])
{
vOutput[idx] = 0.0f;
return;
}
float x0, y0, z0, x1, y1, z1;
int ibx, itx, iby, ity, ibz, itz, im;
ibx = 0;
itx = xSize - 1;
while (ibx < (itx-1))
{
im = ((ibx + itx) >> 1);
if (x <= gridX[im])
{
itx = im;
}
else
{
ibx = im;
}
}
x0 = gridX[ibx];
x1 = gridX[itx];
iby = 0;
ity = ySize - 1;
while (iby < (ity-1))
{
im = ((iby + ity) >> 1);
if (y <= gridY[im])
{
ity = im;
}
else
{
iby = im;
}
}
y0 = gridY[iby];
y1 = gridY[ity];
ibz = 0;
itz = zSize - 1;
while (ibz < (itz-1))
{
im = ((ibz + itz) >> 1);
if (z <= gridZ[im])
{
itz = im;
}
else
{
ibz = im;
}
}
z0 = gridZ[ibz];
z1 = gridZ[itz];
int sliceDim = xSize * ySize;
int zOff0 = sliceDim * ibz;
int zOff1 = zOff0 + sliceDim;
int yOff0 = ySize * ibx;
int yOff1 = yOff0 + ySize;
float ax0 = (x - x0) / (x1 - x0);
float ay0 = (y - y0) / (y1 - y0);
float az0 = (z - z0) / (z1 - z0);
float ax1 = 1.0f - ax0;
float ay1 = 1.0f - ay0;
float v000 = vInput[zOff0 + yOff0 + iby];
float v001 = vInput[zOff0 + yOff0 + ity];
float v010 = vInput[zOff0 + yOff1 + iby];
float v011 = vInput[zOff0 + yOff1 + ity];
float v100 = vInput[zOff1 + yOff0 + iby];
float v101 = vInput[zOff1 + yOff0 + ity];
float v110 = vInput[zOff1 + yOff1 + iby];
float v111 = vInput[zOff1 + yOff1 + ity];
float v00 = v000 * ay1 + v001 * ay0;
float v01 = v010 * ay1 + v011 * ay0;
float v10 = v100 * ay1 + v101 * ay0;
float v11 = v110 * ay1 + v111 * ay0;
float v0 = v00 * ax1 + v01 * ax0;
float v1 = v10 * ax1 + v11 * ax0;
vOutput[idx] = v0 * (1.0f - az0) + v1 * az0;
} | #include <hip/hip_runtime.h>
__global__ void interp3_cuda(
float * vOutput,
int nPoints,
int xSize,
int ySize,
int zSize,
float * gridX,
float * gridY,
float * gridZ,
float * vInput,
float * xInterp,
float * yInterp,
float * zInterp)
{
int idx = blockDim.x * (gridDim.x * blockIdx.y + blockIdx.x) + threadIdx.x;
if (idx >= nPoints)
{
return;
}
float x = xInterp[idx];
float y = yInterp[idx];
float z = zInterp[idx];
if (x < gridX[0] || x > gridX[xSize-1] ||
y < gridY[0] || y > gridY[ySize-1] ||
z < gridZ[0] || z > gridZ[zSize-1])
{
vOutput[idx] = 0.0f;
return;
}
float x0, y0, z0, x1, y1, z1;
int ibx, itx, iby, ity, ibz, itz, im;
ibx = 0;
itx = xSize - 1;
while (ibx < (itx-1))
{
im = ((ibx + itx) >> 1);
if (x <= gridX[im])
{
itx = im;
}
else
{
ibx = im;
}
}
x0 = gridX[ibx];
x1 = gridX[itx];
iby = 0;
ity = ySize - 1;
while (iby < (ity-1))
{
im = ((iby + ity) >> 1);
if (y <= gridY[im])
{
ity = im;
}
else
{
iby = im;
}
}
y0 = gridY[iby];
y1 = gridY[ity];
ibz = 0;
itz = zSize - 1;
while (ibz < (itz-1))
{
im = ((ibz + itz) >> 1);
if (z <= gridZ[im])
{
itz = im;
}
else
{
ibz = im;
}
}
z0 = gridZ[ibz];
z1 = gridZ[itz];
int sliceDim = xSize * ySize;
int zOff0 = sliceDim * ibz;
int zOff1 = zOff0 + sliceDim;
int yOff0 = ySize * ibx;
int yOff1 = yOff0 + ySize;
float ax0 = (x - x0) / (x1 - x0);
float ay0 = (y - y0) / (y1 - y0);
float az0 = (z - z0) / (z1 - z0);
float ax1 = 1.0f - ax0;
float ay1 = 1.0f - ay0;
float v000 = vInput[zOff0 + yOff0 + iby];
float v001 = vInput[zOff0 + yOff0 + ity];
float v010 = vInput[zOff0 + yOff1 + iby];
float v011 = vInput[zOff0 + yOff1 + ity];
float v100 = vInput[zOff1 + yOff0 + iby];
float v101 = vInput[zOff1 + yOff0 + ity];
float v110 = vInput[zOff1 + yOff1 + iby];
float v111 = vInput[zOff1 + yOff1 + ity];
float v00 = v000 * ay1 + v001 * ay0;
float v01 = v010 * ay1 + v011 * ay0;
float v10 = v100 * ay1 + v101 * ay0;
float v11 = v110 * ay1 + v111 * ay0;
float v0 = v00 * ax1 + v01 * ax0;
float v1 = v10 * ax1 + v11 * ax0;
vOutput[idx] = v0 * (1.0f - az0) + v1 * az0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void interp3_cuda(
float * vOutput,
int nPoints,
int xSize,
int ySize,
int zSize,
float * gridX,
float * gridY,
float * gridZ,
float * vInput,
float * xInterp,
float * yInterp,
float * zInterp)
{
int idx = blockDim.x * (gridDim.x * blockIdx.y + blockIdx.x) + threadIdx.x;
if (idx >= nPoints)
{
return;
}
float x = xInterp[idx];
float y = yInterp[idx];
float z = zInterp[idx];
if (x < gridX[0] || x > gridX[xSize-1] ||
y < gridY[0] || y > gridY[ySize-1] ||
z < gridZ[0] || z > gridZ[zSize-1])
{
vOutput[idx] = 0.0f;
return;
}
float x0, y0, z0, x1, y1, z1;
int ibx, itx, iby, ity, ibz, itz, im;
ibx = 0;
itx = xSize - 1;
while (ibx < (itx-1))
{
im = ((ibx + itx) >> 1);
if (x <= gridX[im])
{
itx = im;
}
else
{
ibx = im;
}
}
x0 = gridX[ibx];
x1 = gridX[itx];
iby = 0;
ity = ySize - 1;
while (iby < (ity-1))
{
im = ((iby + ity) >> 1);
if (y <= gridY[im])
{
ity = im;
}
else
{
iby = im;
}
}
y0 = gridY[iby];
y1 = gridY[ity];
ibz = 0;
itz = zSize - 1;
while (ibz < (itz-1))
{
im = ((ibz + itz) >> 1);
if (z <= gridZ[im])
{
itz = im;
}
else
{
ibz = im;
}
}
z0 = gridZ[ibz];
z1 = gridZ[itz];
int sliceDim = xSize * ySize;
int zOff0 = sliceDim * ibz;
int zOff1 = zOff0 + sliceDim;
int yOff0 = ySize * ibx;
int yOff1 = yOff0 + ySize;
float ax0 = (x - x0) / (x1 - x0);
float ay0 = (y - y0) / (y1 - y0);
float az0 = (z - z0) / (z1 - z0);
float ax1 = 1.0f - ax0;
float ay1 = 1.0f - ay0;
float v000 = vInput[zOff0 + yOff0 + iby];
float v001 = vInput[zOff0 + yOff0 + ity];
float v010 = vInput[zOff0 + yOff1 + iby];
float v011 = vInput[zOff0 + yOff1 + ity];
float v100 = vInput[zOff1 + yOff0 + iby];
float v101 = vInput[zOff1 + yOff0 + ity];
float v110 = vInput[zOff1 + yOff1 + iby];
float v111 = vInput[zOff1 + yOff1 + ity];
float v00 = v000 * ay1 + v001 * ay0;
float v01 = v010 * ay1 + v011 * ay0;
float v10 = v100 * ay1 + v101 * ay0;
float v11 = v110 * ay1 + v111 * ay0;
float v0 = v00 * ax1 + v01 * ax0;
float v1 = v10 * ax1 + v11 * ax0;
vOutput[idx] = v0 * (1.0f - az0) + v1 * az0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.globl _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.p2align 8
.type _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_,@function
_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x50
s_load_b32 s3, s[0:1], 0x5c
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_26
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b64 s[6:7], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_load_b32 s2, s[6:7], 0x0
global_load_b32 v9, v[4:5], off
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_ngt_f32_e32 s2, v9
s_cbranch_execz .LBB0_25
s_load_b32 s17, s[0:1], 0xc
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s12, s17, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s13, s12, 31
s_lshl_b64 s[2:3], s[12:13], 2
s_mov_b32 s13, exec_lo
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmpx_nlt_f32_e32 s2, v9
s_cbranch_execz .LBB0_24
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x40
s_load_b64 s[4:5], s[0:1], 0x20
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_mov_b32 s15, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_load_b32 s2, s[4:5], 0x0
global_load_b32 v10, v[4:5], off
v_mov_b32_e32 v4, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_ngt_f32_e32 s2, v10
s_cbranch_execz .LBB0_23
s_load_b32 s18, s[0:1], 0x10
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s10, s18, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[2:3], s[10:11], 2
s_mov_b32 s11, exec_lo
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_cmpx_nlt_f32_e32 s2, v10
s_cbranch_execz .LBB0_22
s_load_b64 s[2:3], s[0:1], 0x48
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mov_b32_e32 v4, 0
s_mov_b32 s16, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x28
global_load_b32 v11, v[2:3], off
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_ngt_f32_e32 s8, v11
s_cbranch_execz .LBB0_21
s_load_b32 s19, s[0:1], 0x14
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s8, s19, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[20:21], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s2, s20
s_addc_u32 s21, s3, s21
s_load_b32 s9, s[20:21], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_nlt_f32_e32 vcc_lo, s9, v11
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_20
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, s12
s_cmp_lt_i32 s17, 3
s_cbranch_scc1 .LBB0_11
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, s12
s_mov_b32 s12, 0
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v6, v2
v_ashrrev_i32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_nle_f32_e32 vcc_lo, v9, v4
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v6, v6, v3 :: v_dual_add_nc_u32 v3, -1, v2
v_cmp_ge_i32_e32 vcc_lo, v6, v3
s_or_b32 s12, vcc_lo, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_9
s_or_b32 exec_lo, exec_lo, s12
.LBB0_11:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v3, 31, v2
s_cmp_lt_i32 s18, 3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_clause 0x1
global_load_b32 v12, v[4:5], off
global_load_b32 v13, v[2:3], off
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, s10
s_cbranch_scc1 .LBB0_15
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, s10
s_mov_b32 s6, 0
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v2, v4
v_ashrrev_i32_e32 v7, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[14:15], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
global_load_b32 v3, v[14:15], off
s_waitcnt vmcnt(0)
v_cmp_nle_f32_e32 vcc_lo, v10, v3
v_cndmask_b32_e32 v4, v7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v7 :: v_dual_add_nc_u32 v3, -1, v4
v_cmp_ge_i32_e32 vcc_lo, v2, v3
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_13
s_or_b32 exec_lo, exec_lo, s6
.LBB0_15:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_cmp_lt_i32 s19, 3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_lshlrev_b64 v[14:15], 2, v[4:5]
v_mov_b32_e32 v5, s8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s5, v15, vcc_lo
s_clause 0x1
global_load_b32 v3, v[7:8], off
global_load_b32 v14, v[14:15], off
v_mov_b32_e32 v7, 0
s_cbranch_scc1 .LBB0_19
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v5, s8
s_mov_b32 s4, 0
.LBB0_17:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v7, v5
v_ashrrev_i32_e32 v15, 1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[16:17], 2, v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v16, vcc_lo, s2, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s3, v17, vcc_lo
global_load_b32 v8, v[16:17], off
s_waitcnt vmcnt(0)
v_cmp_nle_f32_e32 vcc_lo, v11, v8
v_cndmask_b32_e32 v5, v15, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v7, v7, v15 :: v_dual_add_nc_u32 v8, -1, v5
v_cmp_ge_i32_e32 vcc_lo, v7, v8
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_17
s_or_b32 exec_lo, exec_lo, s4
.LBB0_19:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_mul_lo_u32 v19, v6, s18
s_mul_i32 s6, s18, s17
v_ashrrev_i32_e32 v6, 31, v5
v_mul_lo_u32 v20, v7, s6
v_lshlrev_b64 v[15:16], 2, v[7:8]
s_load_b64 s[4:5], s[0:1], 0x30
s_waitcnt vmcnt(1)
v_sub_f32_e32 v10, v10, v3
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_nc_u32_e32 v22, s18, v19
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, v14, v3
v_add_co_u32 v7, vcc_lo, s2, v15
v_add_nc_u32_e32 v18, v20, v19
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v16, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_nc_u32_e32 v21, v20, v22
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_nc_u32_e32 v15, v18, v4
s_clause 0x1
global_load_b32 v25, v[7:8], off
global_load_b32 v26, v[5:6], off
v_add_nc_u32_e32 v17, v21, v2
v_add_nc_u32_e32 v7, v21, v4
v_ashrrev_i32_e32 v16, 31, v15
v_add_nc_u32_e32 v23, s6, v20
v_add_nc_u32_e32 v5, v18, v2
v_ashrrev_i32_e32 v18, 31, v17
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_nc_u32_e32 v21, v23, v19
v_add_nc_u32_e32 v24, v23, v22
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_nc_u32_e32 v19, v21, v2
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v17, vcc_lo, s4, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_ashrrev_i32_e32 v20, 31, v19
v_add_nc_u32_e32 v21, v21, v4
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_nc_u32_e32 v23, v24, v4
v_lshlrev_b64 v[19:20], 2, v[19:20]
v_ashrrev_i32_e32 v22, 31, v21
s_clause 0x2
global_load_b32 v27, v[15:16], off
global_load_b32 v28, v[17:18], off
global_load_b32 v29, v[7:8], off
v_add_nc_u32_e32 v15, v24, v2
v_ashrrev_i32_e32 v24, 31, v23
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_lshlrev_b64 v[7:8], 2, v[21:22]
v_add_co_u32 v17, vcc_lo, s4, v19
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v20, vcc_lo
v_lshlrev_b64 v[19:20], 2, v[23:24]
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v19, vcc_lo, s4, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v20, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
s_clause 0x3
global_load_b32 v2, v[19:20], off
global_load_b32 v6, v[7:8], off
global_load_b32 v7, v[17:18], off
global_load_b32 v8, v[15:16], off
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_div_scale_f32 v19, s2, v10, v3, v10
global_load_b32 v4, v[4:5], off
v_sub_f32_e32 v5, v9, v12
v_sub_f32_e32 v9, v13, v12
v_div_scale_f32 v13, null, v3, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v12, null, v9, v9, v5
v_rcp_f32_e32 v15, v13
v_div_scale_f32 v18, vcc_lo, v5, v9, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v14, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v17, -v13, v15, 1.0
v_fma_f32 v16, -v12, v14, 1.0
v_dual_fmac_f32 v15, v17, v15 :: v_dual_fmac_f32 v14, v16, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v20, v19, v15 :: v_dual_mul_f32 v17, v18, v14
v_fma_f32 v23, -v13, v20, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v22, -v12, v17, v18
v_dual_fmac_f32 v20, v23, v15 :: v_dual_fmac_f32 v17, v22, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v13, v20, v19
v_fma_f32 v12, -v12, v17, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fmas_f32 v12, v12, v14, v17
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v13, v13, v15, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v5, v12, v9, v5
v_div_fixup_f32 v3, v13, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v10, 1.0, v5
v_sub_f32_e32 v12, 1.0, v3
s_waitcnt vmcnt(8)
v_sub_f32_e32 v16, v26, v25
s_waitcnt vmcnt(4)
v_mul_f32_e32 v2, v3, v2
s_waitcnt vmcnt(3)
v_mul_f32_e32 v6, v3, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v11, v11, v25 :: v_dual_fmac_f32 v2, v12, v8
v_fmac_f32_e32 v6, v12, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_scale_f32 v21, null, v16, v16, v11
v_div_scale_f32 v14, s3, v11, v16, v11
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v24, v21
v_dual_mul_f32 v2, v5, v2 :: v_dual_mul_f32 v13, v3, v29
v_dual_mul_f32 v3, v3, v27 :: v_dual_fmac_f32 v2, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v12, v28
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, v12, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v18, -v21, v24, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v5, v5, v13 :: v_dual_fmac_f32 v24, v18, v24
v_fmac_f32_e32 v5, v10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, v14, v24
v_fma_f32 v9, -v21, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v9, v24
v_fma_f32 v9, -v21, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v7, v9, v24, v15
v_div_fixup_f32 v4, v7, v16, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, 1.0, v4 :: v_dual_mul_f32 v4, v4, v2
v_fmac_f32_e32 v4, v3, v5
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_21:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s16
.LBB0_22:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
.LBB0_23:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s15
.LBB0_24:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
.LBB0_25:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_26:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, .Lfunc_end0-_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void interp3_cuda(
float * vOutput,
int nPoints,
int xSize,
int ySize,
int zSize,
float * gridX,
float * gridY,
float * gridZ,
float * vInput,
float * xInterp,
float * yInterp,
float * zInterp)
{
int idx = blockDim.x * (gridDim.x * blockIdx.y + blockIdx.x) + threadIdx.x;
if (idx >= nPoints)
{
return;
}
float x = xInterp[idx];
float y = yInterp[idx];
float z = zInterp[idx];
if (x < gridX[0] || x > gridX[xSize-1] ||
y < gridY[0] || y > gridY[ySize-1] ||
z < gridZ[0] || z > gridZ[zSize-1])
{
vOutput[idx] = 0.0f;
return;
}
float x0, y0, z0, x1, y1, z1;
int ibx, itx, iby, ity, ibz, itz, im;
ibx = 0;
itx = xSize - 1;
while (ibx < (itx-1))
{
im = ((ibx + itx) >> 1);
if (x <= gridX[im])
{
itx = im;
}
else
{
ibx = im;
}
}
x0 = gridX[ibx];
x1 = gridX[itx];
iby = 0;
ity = ySize - 1;
while (iby < (ity-1))
{
im = ((iby + ity) >> 1);
if (y <= gridY[im])
{
ity = im;
}
else
{
iby = im;
}
}
y0 = gridY[iby];
y1 = gridY[ity];
ibz = 0;
itz = zSize - 1;
while (ibz < (itz-1))
{
im = ((ibz + itz) >> 1);
if (z <= gridZ[im])
{
itz = im;
}
else
{
ibz = im;
}
}
z0 = gridZ[ibz];
z1 = gridZ[itz];
int sliceDim = xSize * ySize;
int zOff0 = sliceDim * ibz;
int zOff1 = zOff0 + sliceDim;
int yOff0 = ySize * ibx;
int yOff1 = yOff0 + ySize;
float ax0 = (x - x0) / (x1 - x0);
float ay0 = (y - y0) / (y1 - y0);
float az0 = (z - z0) / (z1 - z0);
float ax1 = 1.0f - ax0;
float ay1 = 1.0f - ay0;
float v000 = vInput[zOff0 + yOff0 + iby];
float v001 = vInput[zOff0 + yOff0 + ity];
float v010 = vInput[zOff0 + yOff1 + iby];
float v011 = vInput[zOff0 + yOff1 + ity];
float v100 = vInput[zOff1 + yOff0 + iby];
float v101 = vInput[zOff1 + yOff0 + ity];
float v110 = vInput[zOff1 + yOff1 + iby];
float v111 = vInput[zOff1 + yOff1 + ity];
float v00 = v000 * ay1 + v001 * ay0;
float v01 = v010 * ay1 + v011 * ay0;
float v10 = v100 * ay1 + v101 * ay0;
float v11 = v110 * ay1 + v111 * ay0;
float v0 = v00 * ax1 + v01 * ax0;
float v1 = v10 * ax1 + v11 * ax0;
vOutput[idx] = v0 * (1.0f - az0) + v1 * az0;
} | .text
.file "interp3_cuda.hip"
.globl _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_ # -- Begin function _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_,@function
_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_: # @_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_, .Lfunc_end0-_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_,@object # @_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.p2align 3, 0x0
_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_:
.quad _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.size _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005febb_00000000-6_interp3_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_
.type _Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_, @function
_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 72(%rsp)
movl %esi, 68(%rsp)
movl %edx, 64(%rsp)
movl %ecx, 60(%rsp)
movl %r8d, 56(%rsp)
movq %r9, 48(%rsp)
movq 272(%rsp), %rax
movq %rax, 40(%rsp)
movq 280(%rsp), %rax
movq %rax, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 296(%rsp), %rax
movq %rax, 16(%rsp)
movq 304(%rsp), %rax
movq %rax, 8(%rsp)
movq 312(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 68(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 48(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 32(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_, .-_Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_
.globl _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.type _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, @function
_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z50__device_stub__Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_PfiiiiS_S_S_S_S_S_S_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, .-_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "interp3_cuda.hip"
.globl _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_ # -- Begin function _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.p2align 4, 0x90
.type _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_,@function
_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_: # @_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_, .Lfunc_end0-_Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_,@object # @_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.p2align 3, 0x0
_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_:
.quad _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.size _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__interp3_cudaPfiiiiS_S_S_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12interp3_cudaPfiiiiS_S_S_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void update_disp_veloc_kernel(float * displ, float * veloc, float * accel, const int size, const float deltat, const float deltatsqover2, const float deltatover2){
int id;
id = threadIdx.x + (blockIdx.x) * (blockDim.x) + (blockIdx.y) * ((gridDim.x) * (blockDim.x));
if (id < size) {
displ[id] = displ[id] + (deltat) * (veloc[id]) + (deltatsqover2) * (accel[id]);
veloc[id] = veloc[id] + (deltatover2) * (accel[id]);
accel[id] = 0.0f;
}
} | code for sm_80
Function : _Z24update_disp_veloc_kernelPfS_S_ifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ee2000c1e1900 */
/*0100*/ FFMA R0, R0, c[0x0][0x17c], R9 ; /* 0x00005f0000007a23 */
/* 0x004fc80000000009 */
/*0110*/ FFMA R11, R11, c[0x0][0x180], R0 ; /* 0x000060000b0b7a23 */
/* 0x008fca0000000000 */
/*0120*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0130*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FFMA R9, R0, c[0x0][0x184], R9 ; /* 0x0000610000097a23 */
/* 0x004fca0000000009 */
/*0160*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0170*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void update_disp_veloc_kernel(float * displ, float * veloc, float * accel, const int size, const float deltat, const float deltatsqover2, const float deltatover2){
int id;
id = threadIdx.x + (blockIdx.x) * (blockDim.x) + (blockIdx.y) * ((gridDim.x) * (blockDim.x));
if (id < size) {
displ[id] = displ[id] + (deltat) * (veloc[id]) + (deltatsqover2) * (accel[id]);
veloc[id] = veloc[id] + (deltatover2) * (accel[id]);
accel[id] = 0.0f;
}
} | .file "tmpxft_00121140_00000000-6_update_disp_veloc_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff
.type _Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff, @function
_Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24update_disp_veloc_kernelPfS_S_ifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff, .-_Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff
.globl _Z24update_disp_veloc_kernelPfS_S_ifff
.type _Z24update_disp_veloc_kernelPfS_S_ifff, @function
_Z24update_disp_veloc_kernelPfS_S_ifff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24update_disp_veloc_kernelPfS_S_ifff, .-_Z24update_disp_veloc_kernelPfS_S_ifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24update_disp_veloc_kernelPfS_S_ifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24update_disp_veloc_kernelPfS_S_ifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void update_disp_veloc_kernel(float * displ, float * veloc, float * accel, const int size, const float deltat, const float deltatsqover2, const float deltatover2){
int id;
id = threadIdx.x + (blockIdx.x) * (blockDim.x) + (blockIdx.y) * ((gridDim.x) * (blockDim.x));
if (id < size) {
displ[id] = displ[id] + (deltat) * (veloc[id]) + (deltatsqover2) * (accel[id]);
veloc[id] = veloc[id] + (deltatover2) * (accel[id]);
accel[id] = 0.0f;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_disp_veloc_kernel(float * displ, float * veloc, float * accel, const int size, const float deltat, const float deltatsqover2, const float deltatover2){
int id;
id = threadIdx.x + (blockIdx.x) * (blockDim.x) + (blockIdx.y) * ((gridDim.x) * (blockDim.x));
if (id < size) {
displ[id] = displ[id] + (deltat) * (veloc[id]) + (deltatsqover2) * (accel[id]);
veloc[id] = veloc[id] + (deltatover2) * (accel[id]);
accel[id] = 0.0f;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_disp_veloc_kernel(float * displ, float * veloc, float * accel, const int size, const float deltat, const float deltatsqover2, const float deltatover2){
int id;
id = threadIdx.x + (blockIdx.x) * (blockDim.x) + (blockIdx.y) * ((gridDim.x) * (blockDim.x));
if (id < size) {
displ[id] = displ[id] + (deltat) * (veloc[id]) + (deltatsqover2) * (accel[id]);
veloc[id] = veloc[id] + (deltatover2) * (accel[id]);
accel[id] = 0.0f;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24update_disp_veloc_kernelPfS_S_ifff
.globl _Z24update_disp_veloc_kernelPfS_S_ifff
.p2align 8
.type _Z24update_disp_veloc_kernelPfS_S_ifff,@function
_Z24update_disp_veloc_kernelPfS_S_ifff:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
global_load_b32 v8, v[0:1], off
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b32 s0, s[0:1], 0x24
s_waitcnt vmcnt(1) lgkmcnt(0)
v_fmac_f32_e32 v6, s2, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v6, s3, v8
global_store_b32 v[2:3], v6, off
global_load_b32 v2, v[4:5], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v2, s0, v3 :: v_dual_mov_b32 v3, 0
global_store_b32 v[4:5], v2, off
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24update_disp_veloc_kernelPfS_S_ifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24update_disp_veloc_kernelPfS_S_ifff, .Lfunc_end0-_Z24update_disp_veloc_kernelPfS_S_ifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24update_disp_veloc_kernelPfS_S_ifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24update_disp_veloc_kernelPfS_S_ifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_disp_veloc_kernel(float * displ, float * veloc, float * accel, const int size, const float deltat, const float deltatsqover2, const float deltatover2){
int id;
id = threadIdx.x + (blockIdx.x) * (blockDim.x) + (blockIdx.y) * ((gridDim.x) * (blockDim.x));
if (id < size) {
displ[id] = displ[id] + (deltat) * (veloc[id]) + (deltatsqover2) * (accel[id]);
veloc[id] = veloc[id] + (deltatover2) * (accel[id]);
accel[id] = 0.0f;
}
} | .text
.file "update_disp_veloc_kernel.hip"
.globl _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff # -- Begin function _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.p2align 4, 0x90
.type _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff,@function
_Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff: # @_Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24update_disp_veloc_kernelPfS_S_ifff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff, .Lfunc_end0-_Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24update_disp_veloc_kernelPfS_S_ifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24update_disp_veloc_kernelPfS_S_ifff,@object # @_Z24update_disp_veloc_kernelPfS_S_ifff
.section .rodata,"a",@progbits
.globl _Z24update_disp_veloc_kernelPfS_S_ifff
.p2align 3, 0x0
_Z24update_disp_veloc_kernelPfS_S_ifff:
.quad _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.size _Z24update_disp_veloc_kernelPfS_S_ifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24update_disp_veloc_kernelPfS_S_ifff"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24update_disp_veloc_kernelPfS_S_ifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24update_disp_veloc_kernelPfS_S_ifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ee2000c1e1900 */
/*0100*/ FFMA R0, R0, c[0x0][0x17c], R9 ; /* 0x00005f0000007a23 */
/* 0x004fc80000000009 */
/*0110*/ FFMA R11, R11, c[0x0][0x180], R0 ; /* 0x000060000b0b7a23 */
/* 0x008fca0000000000 */
/*0120*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0130*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea4000c1e1900 */
/*0150*/ FFMA R9, R0, c[0x0][0x184], R9 ; /* 0x0000610000097a23 */
/* 0x004fca0000000009 */
/*0160*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe8000c101904 */
/*0170*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24update_disp_veloc_kernelPfS_S_ifff
.globl _Z24update_disp_veloc_kernelPfS_S_ifff
.p2align 8
.type _Z24update_disp_veloc_kernelPfS_S_ifff,@function
_Z24update_disp_veloc_kernelPfS_S_ifff:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
global_load_b32 v8, v[0:1], off
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b32 s0, s[0:1], 0x24
s_waitcnt vmcnt(1) lgkmcnt(0)
v_fmac_f32_e32 v6, s2, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v6, s3, v8
global_store_b32 v[2:3], v6, off
global_load_b32 v2, v[4:5], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v2, s0, v3 :: v_dual_mov_b32 v3, 0
global_store_b32 v[4:5], v2, off
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24update_disp_veloc_kernelPfS_S_ifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24update_disp_veloc_kernelPfS_S_ifff, .Lfunc_end0-_Z24update_disp_veloc_kernelPfS_S_ifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24update_disp_veloc_kernelPfS_S_ifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24update_disp_veloc_kernelPfS_S_ifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00121140_00000000-6_update_disp_veloc_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff
.type _Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff, @function
_Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z24update_disp_veloc_kernelPfS_S_ifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff, .-_Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff
.globl _Z24update_disp_veloc_kernelPfS_S_ifff
.type _Z24update_disp_veloc_kernelPfS_S_ifff, @function
_Z24update_disp_veloc_kernelPfS_S_ifff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z24update_disp_veloc_kernelPfS_S_ifffPfS_S_ifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24update_disp_veloc_kernelPfS_S_ifff, .-_Z24update_disp_veloc_kernelPfS_S_ifff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24update_disp_veloc_kernelPfS_S_ifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24update_disp_veloc_kernelPfS_S_ifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update_disp_veloc_kernel.hip"
.globl _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff # -- Begin function _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.p2align 4, 0x90
.type _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff,@function
_Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff: # @_Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24update_disp_veloc_kernelPfS_S_ifff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff, .Lfunc_end0-_Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24update_disp_veloc_kernelPfS_S_ifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24update_disp_veloc_kernelPfS_S_ifff,@object # @_Z24update_disp_veloc_kernelPfS_S_ifff
.section .rodata,"a",@progbits
.globl _Z24update_disp_veloc_kernelPfS_S_ifff
.p2align 3, 0x0
_Z24update_disp_veloc_kernelPfS_S_ifff:
.quad _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.size _Z24update_disp_veloc_kernelPfS_S_ifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24update_disp_veloc_kernelPfS_S_ifff"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__update_disp_veloc_kernelPfS_S_ifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24update_disp_veloc_kernelPfS_S_ifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <vector>
#define N 60000
using namespace std;
__global__ void add( float *a, float *b, float *c )
{
int tid = blockIdx.x;
if ( tid < N )
c[ tid ] = a[ tid ] + b[ tid ];
}
int main ( void )
{
//host vectors
vector < float > firstVec( N, 1.11f );
vector < float > secondVec( N, 3.01f );
vector < float > resultsVec( N, 0.0f );
//GPU memory allocation
float *dev_a, *dev_b, *dev_c;
cudaMalloc( ( void** )&dev_a, N * sizeof( float ) );
cudaMalloc( ( void** )&dev_b, N * sizeof( float ) );
cudaMalloc( ( void** )&dev_c, N * sizeof( float ) );
//copy / download data in direction HostToDevice
cudaMemcpy( dev_a, &firstVec[0], N * sizeof( float ), cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, &secondVec[0], N * sizeof( float ), cudaMemcpyHostToDevice );
//calculate vectors sum, using Blocks
add<<<N,1>>> ( dev_a, dev_b, dev_c );
//copy / upload results data c[] in direction DeviceToHost
cudaMemcpy( &resultsVec[0], dev_c, N * sizeof( float ), cudaMemcpyDeviceToHost );
//show results
for ( int i = 0; i < 5; i++ )
cout << firstVec[ i ] << " + " << secondVec[ i ] << " = " << resultsVec[ i ] << endl;
//free GPU memory
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z3addPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0xea5f, PT ; /* 0x0000ea5f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <vector>
#define N 60000
using namespace std;
__global__ void add( float *a, float *b, float *c )
{
int tid = blockIdx.x;
if ( tid < N )
c[ tid ] = a[ tid ] + b[ tid ];
}
int main ( void )
{
//host vectors
vector < float > firstVec( N, 1.11f );
vector < float > secondVec( N, 3.01f );
vector < float > resultsVec( N, 0.0f );
//GPU memory allocation
float *dev_a, *dev_b, *dev_c;
cudaMalloc( ( void** )&dev_a, N * sizeof( float ) );
cudaMalloc( ( void** )&dev_b, N * sizeof( float ) );
cudaMalloc( ( void** )&dev_c, N * sizeof( float ) );
//copy / download data in direction HostToDevice
cudaMemcpy( dev_a, &firstVec[0], N * sizeof( float ), cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, &secondVec[0], N * sizeof( float ), cudaMemcpyHostToDevice );
//calculate vectors sum, using Blocks
add<<<N,1>>> ( dev_a, dev_b, dev_c );
//copy / upload results data c[] in direction DeviceToHost
cudaMemcpy( &resultsVec[0], dev_c, N * sizeof( float ), cudaMemcpyDeviceToHost );
//show results
for ( int i = 0; i < 5; i++ )
cout << firstVec[ i ] << " + " << secondVec[ i ] << " = " << resultsVec[ i ] << endl;
//free GPU memory
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
cudaDeviceReset();
return 0;
} | .file "tmpxft_0004b599_00000000-6_vecSum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPfS_S_PfS_S_
.type _Z26__device_stub__Z3addPfS_S_PfS_S_, @function
_Z26__device_stub__Z3addPfS_S_PfS_S_:
.LFB4057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z26__device_stub__Z3addPfS_S_PfS_S_, .-_Z26__device_stub__Z3addPfS_S_PfS_S_
.globl _Z3addPfS_S_
.type _Z3addPfS_S_, @function
_Z3addPfS_S_:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z3addPfS_S_, .-_Z3addPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4370:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4370:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.1
.LC4:
.string " + "
.LC5:
.string " = "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $240000, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %r13
movq %rax, 48(%rsp)
leaq 240000(%rax), %rdx
movq %rdx, 64(%rsp)
movss .LC1(%rip), %xmm0
.L20:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $240000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %r14
movq %rax, 80(%rsp)
leaq 240000(%rax), %rdx
movq %rdx, 96(%rsp)
movss .LC2(%rip), %xmm0
.L21:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
movq %rdx, 88(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movl $240000, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, %r15
movq %rax, 112(%rsp)
leaq 240000(%rax), %rdx
movq %rdx, 128(%rsp)
.L22:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
movq %rdx, 120(%rsp)
movq %rsp, %rdi
movl $240000, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $240000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $240000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $240000, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $240000, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $60000, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPfS_S_PfS_S_
.L23:
movl $2, %ecx
movl $240000, %edx
movq 16(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
jmp .L28
.L47:
movq %rax, %rbp
movl $3, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L43
cmpb $0, 56(%r12)
je .L26
movzbl 67(%r12), %esi
.L27:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L44
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L36:
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L30:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L31:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L32
call __stack_chk_fail@PLT
.L45:
call __stack_chk_fail@PLT
.L26:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L44:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbx
cmpq $20, %rbx
je .L46
.L28:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L47
.L46:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
.LEHE3:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L30
.L34:
endbr64
movq %rax, %rbx
jmp .L31
.L32:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L35-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L36-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1066275963
.align 4
.LC2:
.long 1077978071
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <vector>
#define N 60000
using namespace std;
__global__ void add( float *a, float *b, float *c )
{
int tid = blockIdx.x;
if ( tid < N )
c[ tid ] = a[ tid ] + b[ tid ];
}
int main ( void )
{
//host vectors
vector < float > firstVec( N, 1.11f );
vector < float > secondVec( N, 3.01f );
vector < float > resultsVec( N, 0.0f );
//GPU memory allocation
float *dev_a, *dev_b, *dev_c;
cudaMalloc( ( void** )&dev_a, N * sizeof( float ) );
cudaMalloc( ( void** )&dev_b, N * sizeof( float ) );
cudaMalloc( ( void** )&dev_c, N * sizeof( float ) );
//copy / download data in direction HostToDevice
cudaMemcpy( dev_a, &firstVec[0], N * sizeof( float ), cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, &secondVec[0], N * sizeof( float ), cudaMemcpyHostToDevice );
//calculate vectors sum, using Blocks
add<<<N,1>>> ( dev_a, dev_b, dev_c );
//copy / upload results data c[] in direction DeviceToHost
cudaMemcpy( &resultsVec[0], dev_c, N * sizeof( float ), cudaMemcpyDeviceToHost );
//show results
for ( int i = 0; i < 5; i++ )
cout << firstVec[ i ] << " + " << secondVec[ i ] << " = " << resultsVec[ i ] << endl;
//free GPU memory
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#define N 60000
using namespace std;
__global__ void add( float *a, float *b, float *c )
{
int tid = blockIdx.x;
if ( tid < N )
c[ tid ] = a[ tid ] + b[ tid ];
}
int main ( void )
{
//host vectors
vector < float > firstVec( N, 1.11f );
vector < float > secondVec( N, 3.01f );
vector < float > resultsVec( N, 0.0f );
//GPU memory allocation
float *dev_a, *dev_b, *dev_c;
hipMalloc( ( void** )&dev_a, N * sizeof( float ) );
hipMalloc( ( void** )&dev_b, N * sizeof( float ) );
hipMalloc( ( void** )&dev_c, N * sizeof( float ) );
//copy / download data in direction HostToDevice
hipMemcpy( dev_a, &firstVec[0], N * sizeof( float ), hipMemcpyHostToDevice );
hipMemcpy( dev_b, &secondVec[0], N * sizeof( float ), hipMemcpyHostToDevice );
//calculate vectors sum, using Blocks
add<<<N,1>>> ( dev_a, dev_b, dev_c );
//copy / upload results data c[] in direction DeviceToHost
hipMemcpy( &resultsVec[0], dev_c, N * sizeof( float ), hipMemcpyDeviceToHost );
//show results
for ( int i = 0; i < 5; i++ )
cout << firstVec[ i ] << " + " << secondVec[ i ] << " = " << resultsVec[ i ] << endl;
//free GPU memory
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#define N 60000
using namespace std;
__global__ void add( float *a, float *b, float *c )
{
int tid = blockIdx.x;
if ( tid < N )
c[ tid ] = a[ tid ] + b[ tid ];
}
int main ( void )
{
//host vectors
vector < float > firstVec( N, 1.11f );
vector < float > secondVec( N, 3.01f );
vector < float > resultsVec( N, 0.0f );
//GPU memory allocation
float *dev_a, *dev_b, *dev_c;
hipMalloc( ( void** )&dev_a, N * sizeof( float ) );
hipMalloc( ( void** )&dev_b, N * sizeof( float ) );
hipMalloc( ( void** )&dev_c, N * sizeof( float ) );
//copy / download data in direction HostToDevice
hipMemcpy( dev_a, &firstVec[0], N * sizeof( float ), hipMemcpyHostToDevice );
hipMemcpy( dev_b, &secondVec[0], N * sizeof( float ), hipMemcpyHostToDevice );
//calculate vectors sum, using Blocks
add<<<N,1>>> ( dev_a, dev_b, dev_c );
//copy / upload results data c[] in direction DeviceToHost
hipMemcpy( &resultsVec[0], dev_c, N * sizeof( float ), hipMemcpyDeviceToHost );
//show results
for ( int i = 0; i < 5; i++ )
cout << firstVec[ i ] << " + " << secondVec[ i ] << " = " << resultsVec[ i ] << endl;
//free GPU memory
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_S_
.globl _Z3addPfS_S_
.p2align 8
.type _Z3addPfS_S_,@function
_Z3addPfS_S_:
s_cmp_gt_i32 s15, 0xea5f
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v0, s4, s5
global_store_b32 v1, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_S_, .Lfunc_end0-_Z3addPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
#define N 60000
using namespace std;
__global__ void add( float *a, float *b, float *c )
{
int tid = blockIdx.x;
if ( tid < N )
c[ tid ] = a[ tid ] + b[ tid ];
}
int main ( void )
{
//host vectors
vector < float > firstVec( N, 1.11f );
vector < float > secondVec( N, 3.01f );
vector < float > resultsVec( N, 0.0f );
//GPU memory allocation
float *dev_a, *dev_b, *dev_c;
hipMalloc( ( void** )&dev_a, N * sizeof( float ) );
hipMalloc( ( void** )&dev_b, N * sizeof( float ) );
hipMalloc( ( void** )&dev_c, N * sizeof( float ) );
//copy / download data in direction HostToDevice
hipMemcpy( dev_a, &firstVec[0], N * sizeof( float ), hipMemcpyHostToDevice );
hipMemcpy( dev_b, &secondVec[0], N * sizeof( float ), hipMemcpyHostToDevice );
//calculate vectors sum, using Blocks
add<<<N,1>>> ( dev_a, dev_b, dev_c );
//copy / upload results data c[] in direction DeviceToHost
hipMemcpy( &resultsVec[0], dev_c, N * sizeof( float ), hipMemcpyDeviceToHost );
//show results
for ( int i = 0; i < 5; i++ )
cout << firstVec[ i ] << " + " << secondVec[ i ] << " = " << resultsVec[ i ] << endl;
//free GPU memory
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
hipDeviceReset();
return 0;
} | .text
.file "vecSum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPfS_S_ # -- Begin function _Z18__device_stub__addPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_,@function
_Z18__device_stub__addPfS_S_: # @_Z18__device_stub__addPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_, .Lfunc_end0-_Z18__device_stub__addPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %.noexc
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $240000, %edi # imm = 0x3A980
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1066275963, (%rbx,%rax) # imm = 0x3F8E147B
addq $4, %rax
cmpq $240000, %rax # imm = 0x3A980
jne .LBB1_1
# %bb.2: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $240000, %edi # imm = 0x3A980
callq _Znwm
.Ltmp1:
# %bb.3: # %.lr.ph.i.i.i.i.i.i.i.i.i18.preheader
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph.i.i.i.i.i.i.i.i.i18
# =>This Inner Loop Header: Depth=1
movl $1077978071, (%r14,%rax) # imm = 0x4040A3D7
addq $4, %rax
cmpq $240000, %rax # imm = 0x3A980
jne .LBB1_4
# %bb.5: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit22
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $240000, %edi # imm = 0x3A980
callq _Znwm
.Ltmp4:
# %bb.6: # %.lr.ph.i.i.i.i.i.i.i.i.i23.preheader
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $240000, %edx # imm = 0x3A980
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $240000, %esi # imm = 0x3A980
callq hipMalloc
.Ltmp7:
# %bb.7:
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $240000, %esi # imm = 0x3A980
callq hipMalloc
.Ltmp9:
# %bb.8:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $240000, %esi # imm = 0x3A980
callq hipMalloc
.Ltmp11:
# %bb.9:
movq 16(%rsp), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $240000, %edx # imm = 0x3A980
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.10:
movq 8(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $240000, %edx # imm = 0x3A980
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp15:
# %bb.11:
.Ltmp16:
.cfi_escape 0x2e, 0x00
movabsq $4295027296, %rdi # imm = 0x10000EA60
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp17:
# %bb.12:
testl %eax, %eax
jne .LBB1_15
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp19:
# %bb.14: # %.noexc28
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp20:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z3addPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp21:
.LBB1_15:
movq (%rsp), %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $240000, %edx # imm = 0x3A980
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp23:
# %bb.16: # %.preheader.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_17: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp25:
# %bb.18: # %_ZNSolsEf.exit
# in Loop: Header=BB1_17 Depth=1
.Ltmp26:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp27:
# %bb.19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_17 Depth=1
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp29:
# %bb.20: # %_ZNSolsEf.exit33
# in Loop: Header=BB1_17 Depth=1
.Ltmp30:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp31:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit35
# in Loop: Header=BB1_17 Depth=1
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp33:
# %bb.22: # %_ZNSolsEf.exit37
# in Loop: Header=BB1_17 Depth=1
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_23
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_17 Depth=1
cmpb $0, 56(%r13)
je .LBB1_29
# %bb.28: # in Loop: Header=BB1_17 Depth=1
movzbl 67(%r13), %eax
jmp .LBB1_31
.p2align 4, 0x90
.LBB1_29: # in Loop: Header=BB1_17 Depth=1
.Ltmp34:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp35:
# %bb.30: # %.noexc51
# in Loop: Header=BB1_17 Depth=1
movq (%r13), %rax
.Ltmp36:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp37:
.LBB1_31: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_17 Depth=1
.Ltmp38:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp39:
# %bb.32: # %.noexc53
# in Loop: Header=BB1_17 Depth=1
.Ltmp40:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp41:
# %bb.33: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_17 Depth=1
incq %rbp
cmpq $5, %rbp
jne .LBB1_17
# %bb.34:
movq 16(%rsp), %rdi
.Ltmp43:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp44:
# %bb.35:
movq 8(%rsp), %rdi
.Ltmp45:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp46:
# %bb.36:
movq (%rsp), %rdi
.Ltmp47:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp48:
# %bb.37:
.Ltmp49:
.cfi_escape 0x2e, 0x00
callq hipDeviceReset
.Ltmp50:
# %bb.38: # %_ZNSt6vectorIfSaIfEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 176
.Ltmp52:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp53:
# %bb.26: # %.noexc50
.LBB1_25:
.Ltmp5:
movq %rax, %r12
jmp .LBB1_43
.LBB1_24:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_44
.LBB1_41:
.Ltmp51:
jmp .LBB1_42
.LBB1_40: # %.loopexit.split-lp
.Ltmp54:
jmp .LBB1_42
.LBB1_39: # %.loopexit
.Ltmp42:
.LBB1_42: # %_ZNSt6vectorIfSaIfEED2Ev.exit44
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB1_43: # %_ZNSt6vectorIfSaIfEED2Ev.exit46
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_44: # %_ZNSt6vectorIfSaIfEED2Ev.exit48
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp23-.Ltmp6 # Call between .Ltmp6 and .Ltmp23
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp41-.Ltmp24 # Call between .Ltmp24 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp50-.Ltmp43 # Call between .Ltmp43 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53
.uleb128 .Ltmp54-.Lfunc_begin0 # jumps to .Ltmp54
.byte 0 # On action: cleanup
.uleb128 .Ltmp53-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp53 # Call between .Ltmp53 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_,@object # @_Z3addPfS_S_
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_
.p2align 3, 0x0
_Z3addPfS_S_:
.quad _Z18__device_stub__addPfS_S_
.size _Z3addPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " + "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " = "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3addPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0xea5f, PT ; /* 0x0000ea5f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_S_
.globl _Z3addPfS_S_
.p2align 8
.type _Z3addPfS_S_,@function
_Z3addPfS_S_:
s_cmp_gt_i32 s15, 0xea5f
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt lgkmcnt(0)
v_add_f32_e64 v0, s4, s5
global_store_b32 v1, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_S_, .Lfunc_end0-_Z3addPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004b599_00000000-6_vecSum.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPfS_S_PfS_S_
.type _Z26__device_stub__Z3addPfS_S_PfS_S_, @function
_Z26__device_stub__Z3addPfS_S_PfS_S_:
.LFB4057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z26__device_stub__Z3addPfS_S_PfS_S_, .-_Z26__device_stub__Z3addPfS_S_PfS_S_
.globl _Z3addPfS_S_
.type _Z3addPfS_S_, @function
_Z3addPfS_S_:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z3addPfS_S_, .-_Z3addPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4370:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4370:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.1
.LC4:
.string " + "
.LC5:
.string " = "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $240000, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %r13
movq %rax, 48(%rsp)
leaq 240000(%rax), %rdx
movq %rdx, 64(%rsp)
movss .LC1(%rip), %xmm0
.L20:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $240000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %r14
movq %rax, 80(%rsp)
leaq 240000(%rax), %rdx
movq %rdx, 96(%rsp)
movss .LC2(%rip), %xmm0
.L21:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
movq %rdx, 88(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movl $240000, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, %r15
movq %rax, 112(%rsp)
leaq 240000(%rax), %rdx
movq %rdx, 128(%rsp)
.L22:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L22
movq %rdx, 120(%rsp)
movq %rsp, %rdi
movl $240000, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $240000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $240000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $240000, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $240000, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $60000, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPfS_S_PfS_S_
.L23:
movl $2, %ecx
movl $240000, %edx
movq 16(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
jmp .L28
.L47:
movq %rax, %rbp
movl $3, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $3, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L43
cmpb $0, 56(%r12)
je .L26
movzbl 67(%r12), %esi
.L27:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L44
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L36:
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L30:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L31:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L32
call __stack_chk_fail@PLT
.L45:
call __stack_chk_fail@PLT
.L26:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L44:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbx
cmpq $20, %rbx
je .L46
.L28:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L47
.L46:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
.LEHE3:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L30
.L34:
endbr64
movq %rax, %rbx
jmp .L31
.L32:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L34-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L35-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L36-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1066275963
.align 4
.LC2:
.long 1077978071
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecSum.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPfS_S_ # -- Begin function _Z18__device_stub__addPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_,@function
_Z18__device_stub__addPfS_S_: # @_Z18__device_stub__addPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_, .Lfunc_end0-_Z18__device_stub__addPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %.noexc
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $240000, %edi # imm = 0x3A980
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1066275963, (%rbx,%rax) # imm = 0x3F8E147B
addq $4, %rax
cmpq $240000, %rax # imm = 0x3A980
jne .LBB1_1
# %bb.2: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $240000, %edi # imm = 0x3A980
callq _Znwm
.Ltmp1:
# %bb.3: # %.lr.ph.i.i.i.i.i.i.i.i.i18.preheader
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph.i.i.i.i.i.i.i.i.i18
# =>This Inner Loop Header: Depth=1
movl $1077978071, (%r14,%rax) # imm = 0x4040A3D7
addq $4, %rax
cmpq $240000, %rax # imm = 0x3A980
jne .LBB1_4
# %bb.5: # %_ZNSt6vectorIfSaIfEEC2EmRKfRKS0_.exit22
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $240000, %edi # imm = 0x3A980
callq _Znwm
.Ltmp4:
# %bb.6: # %.lr.ph.i.i.i.i.i.i.i.i.i23.preheader
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $240000, %edx # imm = 0x3A980
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $240000, %esi # imm = 0x3A980
callq hipMalloc
.Ltmp7:
# %bb.7:
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $240000, %esi # imm = 0x3A980
callq hipMalloc
.Ltmp9:
# %bb.8:
.Ltmp10:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $240000, %esi # imm = 0x3A980
callq hipMalloc
.Ltmp11:
# %bb.9:
movq 16(%rsp), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $240000, %edx # imm = 0x3A980
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.10:
movq 8(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $240000, %edx # imm = 0x3A980
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp15:
# %bb.11:
.Ltmp16:
.cfi_escape 0x2e, 0x00
movabsq $4295027296, %rdi # imm = 0x10000EA60
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp17:
# %bb.12:
testl %eax, %eax
jne .LBB1_15
# %bb.13:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
.Ltmp18:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp19:
# %bb.14: # %.noexc28
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp20:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z3addPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp21:
.LBB1_15:
movq (%rsp), %rsi
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $240000, %edx # imm = 0x3A980
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp23:
# %bb.16: # %.preheader.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_17: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp24:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp25:
# %bb.18: # %_ZNSolsEf.exit
# in Loop: Header=BB1_17 Depth=1
.Ltmp26:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp27:
# %bb.19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_17 Depth=1
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp28:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp29:
# %bb.20: # %_ZNSolsEf.exit33
# in Loop: Header=BB1_17 Depth=1
.Ltmp30:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp31:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit35
# in Loop: Header=BB1_17 Depth=1
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp32:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp33:
# %bb.22: # %_ZNSolsEf.exit37
# in Loop: Header=BB1_17 Depth=1
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_23
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_17 Depth=1
cmpb $0, 56(%r13)
je .LBB1_29
# %bb.28: # in Loop: Header=BB1_17 Depth=1
movzbl 67(%r13), %eax
jmp .LBB1_31
.p2align 4, 0x90
.LBB1_29: # in Loop: Header=BB1_17 Depth=1
.Ltmp34:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp35:
# %bb.30: # %.noexc51
# in Loop: Header=BB1_17 Depth=1
movq (%r13), %rax
.Ltmp36:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp37:
.LBB1_31: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_17 Depth=1
.Ltmp38:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
.Ltmp39:
# %bb.32: # %.noexc53
# in Loop: Header=BB1_17 Depth=1
.Ltmp40:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp41:
# %bb.33: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_17 Depth=1
incq %rbp
cmpq $5, %rbp
jne .LBB1_17
# %bb.34:
movq 16(%rsp), %rdi
.Ltmp43:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp44:
# %bb.35:
movq 8(%rsp), %rdi
.Ltmp45:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp46:
# %bb.36:
movq (%rsp), %rdi
.Ltmp47:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp48:
# %bb.37:
.Ltmp49:
.cfi_escape 0x2e, 0x00
callq hipDeviceReset
.Ltmp50:
# %bb.38: # %_ZNSt6vectorIfSaIfEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 176
.Ltmp52:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp53:
# %bb.26: # %.noexc50
.LBB1_25:
.Ltmp5:
movq %rax, %r12
jmp .LBB1_43
.LBB1_24:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_44
.LBB1_41:
.Ltmp51:
jmp .LBB1_42
.LBB1_40: # %.loopexit.split-lp
.Ltmp54:
jmp .LBB1_42
.LBB1_39: # %.loopexit
.Ltmp42:
.LBB1_42: # %_ZNSt6vectorIfSaIfEED2Ev.exit44
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB1_43: # %_ZNSt6vectorIfSaIfEED2Ev.exit46
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_44: # %_ZNSt6vectorIfSaIfEED2Ev.exit48
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp23-.Ltmp6 # Call between .Ltmp6 and .Ltmp23
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp41-.Ltmp24 # Call between .Ltmp24 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp43-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp50-.Ltmp43 # Call between .Ltmp43 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53
.uleb128 .Ltmp54-.Lfunc_begin0 # jumps to .Ltmp54
.byte 0 # On action: cleanup
.uleb128 .Ltmp53-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp53 # Call between .Ltmp53 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_,@object # @_Z3addPfS_S_
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_
.p2align 3, 0x0
_Z3addPfS_S_:
.quad _Z18__device_stub__addPfS_S_
.size _Z3addPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " + "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " = "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3addPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void testKernel(int param){
printf("%d, %d\n", threadIdx.x, param);
}
int main(void){
// initialize cuPrintf
int N = 3;
int a = 456;
dim3 threadsPerBlock(N, N);
printf("init\n");
testKernel<<<1,threadsPerBlock>>>(a);
return 0;
} | code for sm_80
Function : _Z10testKerneli
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff097624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void testKernel(int param){
printf("%d, %d\n", threadIdx.x, param);
}
int main(void){
// initialize cuPrintf
int N = 3;
int a = 456;
dim3 threadsPerBlock(N, N);
printf("init\n");
testKernel<<<1,threadsPerBlock>>>(a);
return 0;
} | .file "tmpxft_000dd8bf_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10testKernelii
.type _Z29__device_stub__Z10testKernelii, @function
_Z29__device_stub__Z10testKernelii:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10testKerneli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10testKernelii, .-_Z29__device_stub__Z10testKernelii
.globl _Z10testKerneli
.type _Z10testKerneli, @function
_Z10testKerneli:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10testKernelii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10testKerneli, .-_Z10testKerneli
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "init\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $3, 8(%rsp)
movl $3, 12(%rsp)
movl $1, 16(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl $456, %edi
call _Z29__device_stub__Z10testKernelii
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10testKerneli"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testKerneli(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void testKernel(int param){
printf("%d, %d\n", threadIdx.x, param);
}
int main(void){
// initialize cuPrintf
int N = 3;
int a = 456;
dim3 threadsPerBlock(N, N);
printf("init\n");
testKernel<<<1,threadsPerBlock>>>(a);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void testKernel(int param){
printf("%d, %d\n", threadIdx.x, param);
}
int main(void){
// initialize cuPrintf
int N = 3;
int a = 456;
dim3 threadsPerBlock(N, N);
printf("init\n");
testKernel<<<1,threadsPerBlock>>>(a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void testKernel(int param){
printf("%d, %d\n", threadIdx.x, param);
}
int main(void){
// initialize cuPrintf
int N = 3;
int a = 456;
dim3 threadsPerBlock(N, N);
printf("init\n");
testKernel<<<1,threadsPerBlock>>>(a);
return 0;
} | .text
.file "test.hip"
.globl _Z25__device_stub__testKerneli # -- Begin function _Z25__device_stub__testKerneli
.p2align 4, 0x90
.type _Z25__device_stub__testKerneli,@function
_Z25__device_stub__testKerneli: # @_Z25__device_stub__testKerneli
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10testKerneli, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__testKerneli, .Lfunc_end0-_Z25__device_stub__testKerneli
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $12884901891, %rdx # imm = 0x300000003
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $456, 12(%rsp) # imm = 0x1C8
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10testKerneli, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testKerneli, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testKerneli,@object # @_Z10testKerneli
.section .rodata,"a",@progbits
.globl _Z10testKerneli
.p2align 3, 0x0
_Z10testKerneli:
.quad _Z25__device_stub__testKerneli
.size _Z10testKerneli, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testKerneli"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "init"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testKerneli
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testKerneli
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dd8bf_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10testKernelii
.type _Z29__device_stub__Z10testKernelii, @function
_Z29__device_stub__Z10testKernelii:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10testKerneli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10testKernelii, .-_Z29__device_stub__Z10testKernelii
.globl _Z10testKerneli
.type _Z10testKerneli, @function
_Z10testKerneli:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10testKernelii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10testKerneli, .-_Z10testKerneli
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "init\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $3, 8(%rsp)
movl $3, 12(%rsp)
movl $1, 16(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl $456, %edi
call _Z29__device_stub__Z10testKernelii
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10testKerneli"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10testKerneli(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z25__device_stub__testKerneli # -- Begin function _Z25__device_stub__testKerneli
.p2align 4, 0x90
.type _Z25__device_stub__testKerneli,@function
_Z25__device_stub__testKerneli: # @_Z25__device_stub__testKerneli
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10testKerneli, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__testKerneli, .Lfunc_end0-_Z25__device_stub__testKerneli
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $12884901891, %rdx # imm = 0x300000003
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl $456, 12(%rsp) # imm = 0x1C8
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10testKerneli, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10testKerneli, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10testKerneli,@object # @_Z10testKerneli
.section .rodata,"a",@progbits
.globl _Z10testKerneli
.p2align 3, 0x0
_Z10testKerneli:
.quad _Z25__device_stub__testKerneli
.size _Z10testKerneli, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10testKerneli"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "init"
.size .Lstr, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__testKerneli
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10testKerneli
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | ///
/// \file multiply_kernel.cuh
/// \brief This file provide different kernel function definations \
/// of matrix multiply. a is M*K, b is K*N. c = a*b, c is M*N.
///
/// \author Rudan Chen
/// \date 2016-01-21
__global__ void kComputeMatMultiply_v1(const float *a, const float *b, \
float *c, const int M, const int K, const int N){
const int idx = (blockIdx.x%M)*N + (blockIdx.x/M)*blockDim.x + threadIdx.x;
float result = 0;
for(int i=0; i<K; i++){
result += a[(blockIdx.x%M)*K+i]*b[i*N+(blockIdx.x/M)*blockDim.x+threadIdx.x];
}
c[idx] = result;
}
__global__ void kComputeMatMultiply_v2(const float *a, const float *b, \
float *c, const int K, const int N){
extern __shared__ float result[];
float local_result=0;
for(int i=0; (i*blockDim.x+threadIdx.x)<K; i++){
local_result += a[blockIdx.x*K+i*blockDim.x+threadIdx.x]*b[(i*blockDim.x+threadIdx.x)*N+blockIdx.y];
}
result[threadIdx.x] = local_result;
__syncthreads();
for(int activeThreads = blockDim.x/2; activeThreads; activeThreads/=2){
if(threadIdx.x < activeThreads)
result[threadIdx.x] += result[threadIdx.x + activeThreads];
__syncthreads();
}
if(threadIdx.x == 0)
c[blockIdx.x*N+blockIdx.y] = result[0];
__syncthreads();
}
__global__ void kComputeMatMultiply_v3(const float *a, const float *b, \
float *c, const int K, const int N){
extern __shared__ float sh_a[]; ///save one row of a, shared with b
const int idx = blockIdx.x*N + threadIdx.x;
int i = threadIdx.x;
while(i<K){
sh_a[i] = a[blockIdx.x*K+i];
i += blockDim.x;
}
for(int j=0; j<(N/blockDim.x); j++){
float result = 0;
for(int i=0; i<K; i++){
result += sh_a[i]*b[i*N + j*blockDim.x + threadIdx.x];
}
c[idx + j*blockDim.x] = result;
}
}
#define ASUB_HEIGHT 16
#define ASUB_WIDTH 32
#define BSUB_HEIGHT 32
#define BSUB_WIDTH 256
#define CSUB_HEIGHT 16
#define CSUB_WIDTH 256
/// thread number of one block is fixed at 128
/// each thread compute 16*2 region of c
///
__global__ void kComputeMatMultiply_v4(const float *a, const float *b, \
float *c, const int M, const int K, const int N){
__shared__ float sh_a[ASUB_HEIGHT*ASUB_WIDTH];
float local_c[CSUB_HEIGHT][2];
const int c_block_row = blockIdx.x / (N/CSUB_WIDTH);
const int c_block_col = blockIdx.x % (N/CSUB_WIDTH);
const int v1 = c_block_row*CSUB_HEIGHT; ///v1 is the tmp variable, so as the v2...
const int v2 = c_block_col*CSUB_WIDTH;
const int v3 = threadIdx.x*2;
//copy c to local variable
for(int i=0; i<CSUB_HEIGHT; i++){
local_c[i][0] = c[(v1+i)*N + v2 + v3];
local_c[i][1] = c[(v1+i)*N + v2 + v3 + 1];
}
for(int i=0; i<(K/ASUB_WIDTH); i++){
const int v4 = i*ASUB_WIDTH;
const int v5 = i*BSUB_HEIGHT;
for(int j=0; j<4; j++){
int row_id = (threadIdx.x + j*blockDim.x)/ASUB_WIDTH;
int col_id = (threadIdx.x + j*blockDim.x)%ASUB_WIDTH;
sh_a[threadIdx.x + j*blockDim.x] = a[(v1+row_id)*K + v4 + col_id];
}
__syncthreads();
for(int k=0; k<BSUB_HEIGHT; k++){
for(int m=0; m<CSUB_HEIGHT; m++){
local_c[m][0] += sh_a[m*ASUB_WIDTH + k]*b[(v5 + k)*N \
+ v2 + v3];
local_c[m][1] += sh_a[m*ASUB_WIDTH + k]*b[(v5 + k)*N \
+ v2 + v3 + 1];
}
}
__syncthreads();
}
for(int i=0; i<CSUB_HEIGHT; i++){
c[(v1+i)*N + v2 + v3] = local_c[i][0];
c[(v1+i)*N + v2 + v3 + 1] = local_c[i][1];
}
} | .file "tmpxft_000be037_00000000-6_multiply_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii
.type _Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii, @function
_Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22kComputeMatMultiply_v1PKfS0_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii, .-_Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii
.globl _Z22kComputeMatMultiply_v1PKfS0_Pfiii
.type _Z22kComputeMatMultiply_v1PKfS0_Pfiii, @function
_Z22kComputeMatMultiply_v1PKfS0_Pfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22kComputeMatMultiply_v1PKfS0_Pfiii, .-_Z22kComputeMatMultiply_v1PKfS0_Pfiii
.globl _Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii
.type _Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii, @function
_Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22kComputeMatMultiply_v2PKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii, .-_Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii
.globl _Z22kComputeMatMultiply_v2PKfS0_Pfii
.type _Z22kComputeMatMultiply_v2PKfS0_Pfii, @function
_Z22kComputeMatMultiply_v2PKfS0_Pfii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z22kComputeMatMultiply_v2PKfS0_Pfii, .-_Z22kComputeMatMultiply_v2PKfS0_Pfii
.globl _Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii
.type _Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii, @function
_Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22kComputeMatMultiply_v3PKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii, .-_Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii
.globl _Z22kComputeMatMultiply_v3PKfS0_Pfii
.type _Z22kComputeMatMultiply_v3PKfS0_Pfii, @function
_Z22kComputeMatMultiply_v3PKfS0_Pfii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z22kComputeMatMultiply_v3PKfS0_Pfii, .-_Z22kComputeMatMultiply_v3PKfS0_Pfii
.globl _Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii
.type _Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii, @function
_Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii:
.LFB2057:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22kComputeMatMultiply_v4PKfS0_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii, .-_Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii
.globl _Z22kComputeMatMultiply_v4PKfS0_Pfiii
.type _Z22kComputeMatMultiply_v4PKfS0_Pfiii, @function
_Z22kComputeMatMultiply_v4PKfS0_Pfiii:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z22kComputeMatMultiply_v4PKfS0_Pfiii, .-_Z22kComputeMatMultiply_v4PKfS0_Pfiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22kComputeMatMultiply_v4PKfS0_Pfiii"
.align 8
.LC1:
.string "_Z22kComputeMatMultiply_v3PKfS0_Pfii"
.align 8
.LC2:
.string "_Z22kComputeMatMultiply_v2PKfS0_Pfii"
.align 8
.LC3:
.string "_Z22kComputeMatMultiply_v1PKfS0_Pfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kComputeMatMultiply_v4PKfS0_Pfiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kComputeMatMultiply_v3PKfS0_Pfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kComputeMatMultiply_v2PKfS0_Pfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kComputeMatMultiply_v1PKfS0_Pfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | ///
/// \file multiply_kernel.cuh
/// \brief This file provide different kernel function definations \
/// of matrix multiply. a is M*K, b is K*N. c = a*b, c is M*N.
///
/// \author Rudan Chen
/// \date 2016-01-21
__global__ void kComputeMatMultiply_v1(const float *a, const float *b, \
float *c, const int M, const int K, const int N){
const int idx = (blockIdx.x%M)*N + (blockIdx.x/M)*blockDim.x + threadIdx.x;
float result = 0;
for(int i=0; i<K; i++){
result += a[(blockIdx.x%M)*K+i]*b[i*N+(blockIdx.x/M)*blockDim.x+threadIdx.x];
}
c[idx] = result;
}
__global__ void kComputeMatMultiply_v2(const float *a, const float *b, \
float *c, const int K, const int N){
extern __shared__ float result[];
float local_result=0;
for(int i=0; (i*blockDim.x+threadIdx.x)<K; i++){
local_result += a[blockIdx.x*K+i*blockDim.x+threadIdx.x]*b[(i*blockDim.x+threadIdx.x)*N+blockIdx.y];
}
result[threadIdx.x] = local_result;
__syncthreads();
for(int activeThreads = blockDim.x/2; activeThreads; activeThreads/=2){
if(threadIdx.x < activeThreads)
result[threadIdx.x] += result[threadIdx.x + activeThreads];
__syncthreads();
}
if(threadIdx.x == 0)
c[blockIdx.x*N+blockIdx.y] = result[0];
__syncthreads();
}
__global__ void kComputeMatMultiply_v3(const float *a, const float *b, \
float *c, const int K, const int N){
extern __shared__ float sh_a[]; ///save one row of a, shared with b
const int idx = blockIdx.x*N + threadIdx.x;
int i = threadIdx.x;
while(i<K){
sh_a[i] = a[blockIdx.x*K+i];
i += blockDim.x;
}
for(int j=0; j<(N/blockDim.x); j++){
float result = 0;
for(int i=0; i<K; i++){
result += sh_a[i]*b[i*N + j*blockDim.x + threadIdx.x];
}
c[idx + j*blockDim.x] = result;
}
}
#define ASUB_HEIGHT 16
#define ASUB_WIDTH 32
#define BSUB_HEIGHT 32
#define BSUB_WIDTH 256
#define CSUB_HEIGHT 16
#define CSUB_WIDTH 256
/// thread number of one block is fixed at 128
/// each thread compute 16*2 region of c
///
__global__ void kComputeMatMultiply_v4(const float *a, const float *b, \
float *c, const int M, const int K, const int N){
__shared__ float sh_a[ASUB_HEIGHT*ASUB_WIDTH];
float local_c[CSUB_HEIGHT][2];
const int c_block_row = blockIdx.x / (N/CSUB_WIDTH);
const int c_block_col = blockIdx.x % (N/CSUB_WIDTH);
const int v1 = c_block_row*CSUB_HEIGHT; ///v1 is the tmp variable, so as the v2...
const int v2 = c_block_col*CSUB_WIDTH;
const int v3 = threadIdx.x*2;
//copy c to local variable
for(int i=0; i<CSUB_HEIGHT; i++){
local_c[i][0] = c[(v1+i)*N + v2 + v3];
local_c[i][1] = c[(v1+i)*N + v2 + v3 + 1];
}
for(int i=0; i<(K/ASUB_WIDTH); i++){
const int v4 = i*ASUB_WIDTH;
const int v5 = i*BSUB_HEIGHT;
for(int j=0; j<4; j++){
int row_id = (threadIdx.x + j*blockDim.x)/ASUB_WIDTH;
int col_id = (threadIdx.x + j*blockDim.x)%ASUB_WIDTH;
sh_a[threadIdx.x + j*blockDim.x] = a[(v1+row_id)*K + v4 + col_id];
}
__syncthreads();
for(int k=0; k<BSUB_HEIGHT; k++){
for(int m=0; m<CSUB_HEIGHT; m++){
local_c[m][0] += sh_a[m*ASUB_WIDTH + k]*b[(v5 + k)*N \
+ v2 + v3];
local_c[m][1] += sh_a[m*ASUB_WIDTH + k]*b[(v5 + k)*N \
+ v2 + v3 + 1];
}
}
__syncthreads();
}
for(int i=0; i<CSUB_HEIGHT; i++){
c[(v1+i)*N + v2 + v3] = local_c[i][0];
c[(v1+i)*N + v2 + v3 + 1] = local_c[i][1];
}
} | #include <hip/hip_runtime.h>
///
/// \file multiply_kernel.cuh
/// \brief This file provide different kernel function declarations \
/// of matrix multiply. a is M*K, b is K*N. c = a*b, c is M*N.
///
/// \author Rudan Chen
/// \date 2016-01-21
///
/// This version is the simplest, one thread computes
/// one point of c.
///
__global__ void kComputeMatMultiply_v1(const float *a, const float *b, \
float *c, const int M, const int K, const int N);
///
/// This function means one block computes one point of c.
///
__global__ void kComputeMatMultiply_v2(const float *a, const float *b, \
float *c, const int K, const int N);
///
/// This function means one block computes one row of c.
///
__global__ void kComputeMatMultiply_v3(const float *a, const float *b, \
float *c, const int K, const int N);
///
/// This function adopt an acceleration algorithm.
///
__global__ void kComputeMatMultiply_v4(const float *a, const float *b, \
float *c, const int M, const int K, const int N); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
///
/// \file multiply_kernel.cuh
/// \brief This file provide different kernel function declarations \
/// of matrix multiply. a is M*K, b is K*N. c = a*b, c is M*N.
///
/// \author Rudan Chen
/// \date 2016-01-21
///
/// This version is the simplest, one thread computes
/// one point of c.
///
__global__ void kComputeMatMultiply_v1(const float *a, const float *b, \
float *c, const int M, const int K, const int N);
///
/// This function means one block computes one point of c.
///
__global__ void kComputeMatMultiply_v2(const float *a, const float *b, \
float *c, const int K, const int N);
///
/// This function means one block computes one row of c.
///
__global__ void kComputeMatMultiply_v3(const float *a, const float *b, \
float *c, const int K, const int N);
///
/// This function adopt an acceleration algorithm.
///
__global__ void kComputeMatMultiply_v4(const float *a, const float *b, \
float *c, const int M, const int K, const int N); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
///
/// \file multiply_kernel.cuh
/// \brief This file provide different kernel function declarations \
/// of matrix multiply. a is M*K, b is K*N. c = a*b, c is M*N.
///
/// \author Rudan Chen
/// \date 2016-01-21
///
/// This version is the simplest, one thread computes
/// one point of c.
///
__global__ void kComputeMatMultiply_v1(const float *a, const float *b, \
float *c, const int M, const int K, const int N);
///
/// This function means one block computes one point of c.
///
__global__ void kComputeMatMultiply_v2(const float *a, const float *b, \
float *c, const int K, const int N);
///
/// This function means one block computes one row of c.
///
__global__ void kComputeMatMultiply_v3(const float *a, const float *b, \
float *c, const int K, const int N);
///
/// This function adopt an acceleration algorithm.
///
__global__ void kComputeMatMultiply_v4(const float *a, const float *b, \
float *c, const int M, const int K, const int N); | .text
.file "multiply_kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000be037_00000000-6_multiply_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii
.type _Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii, @function
_Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22kComputeMatMultiply_v1PKfS0_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii, .-_Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii
.globl _Z22kComputeMatMultiply_v1PKfS0_Pfiii
.type _Z22kComputeMatMultiply_v1PKfS0_Pfiii, @function
_Z22kComputeMatMultiply_v1PKfS0_Pfiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z22kComputeMatMultiply_v1PKfS0_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22kComputeMatMultiply_v1PKfS0_Pfiii, .-_Z22kComputeMatMultiply_v1PKfS0_Pfiii
.globl _Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii
.type _Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii, @function
_Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22kComputeMatMultiply_v2PKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii, .-_Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii
.globl _Z22kComputeMatMultiply_v2PKfS0_Pfii
.type _Z22kComputeMatMultiply_v2PKfS0_Pfii, @function
_Z22kComputeMatMultiply_v2PKfS0_Pfii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z22kComputeMatMultiply_v2PKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z22kComputeMatMultiply_v2PKfS0_Pfii, .-_Z22kComputeMatMultiply_v2PKfS0_Pfii
.globl _Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii
.type _Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii, @function
_Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22kComputeMatMultiply_v3PKfS0_Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii, .-_Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii
.globl _Z22kComputeMatMultiply_v3PKfS0_Pfii
.type _Z22kComputeMatMultiply_v3PKfS0_Pfii, @function
_Z22kComputeMatMultiply_v3PKfS0_Pfii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z22kComputeMatMultiply_v3PKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z22kComputeMatMultiply_v3PKfS0_Pfii, .-_Z22kComputeMatMultiply_v3PKfS0_Pfii
.globl _Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii
.type _Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii, @function
_Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii:
.LFB2057:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22kComputeMatMultiply_v4PKfS0_Pfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii, .-_Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii
.globl _Z22kComputeMatMultiply_v4PKfS0_Pfiii
.type _Z22kComputeMatMultiply_v4PKfS0_Pfiii, @function
_Z22kComputeMatMultiply_v4PKfS0_Pfiii:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z22kComputeMatMultiply_v4PKfS0_PfiiiPKfS0_Pfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z22kComputeMatMultiply_v4PKfS0_Pfiii, .-_Z22kComputeMatMultiply_v4PKfS0_Pfiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22kComputeMatMultiply_v4PKfS0_Pfiii"
.align 8
.LC1:
.string "_Z22kComputeMatMultiply_v3PKfS0_Pfii"
.align 8
.LC2:
.string "_Z22kComputeMatMultiply_v2PKfS0_Pfii"
.align 8
.LC3:
.string "_Z22kComputeMatMultiply_v1PKfS0_Pfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kComputeMatMultiply_v4PKfS0_Pfiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kComputeMatMultiply_v3PKfS0_Pfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kComputeMatMultiply_v2PKfS0_Pfii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z22kComputeMatMultiply_v1PKfS0_Pfiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiply_kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=512 --gridDim=1 --warp-sync=32 --no-inline
#include <cuda.h>
#include <stdio.h>
#define N 32
__global__ void scan (int* A)
{
int tid = threadIdx.x;
unsigned int lane = tid & 31;
if (lane >= 1) A[tid] = A[tid - 1] + A[tid];
if (lane >= 2) A[tid] = A[tid - 2] + A[tid];
if (lane >= 4) A[tid] = A[tid - 4] + A[tid];
if (lane >= 8) A[tid] = A[tid - 8] + A[tid];
if (lane >= 16) A[tid] = A[tid - 16] + A[tid];
} | code for sm_80
Function : _Z4scanPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x110 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0050*/ LOP3.LUT P0, R0, R2.reuse, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f02007812 */
/* 0x041fe2000780c0ff */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0203 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R0.reuse, 0x2, PT ; /* 0x000000020000780c */
/* 0x040fe40003f26070 */
/*0080*/ ISETP.GE.U32.AND P2, PT, R0.reuse, 0x4, PT ; /* 0x000000040000780c */
/* 0x040fe40003f46070 */
/*0090*/ ISETP.GE.U32.AND P3, PT, R0.reuse, 0x8, PT ; /* 0x000000080000780c */
/* 0x040fe40003f66070 */
/*00a0*/ ISETP.GE.U32.AND P4, PT, R0, 0x10, PT ; /* 0x000000100000780c */
/* 0x000fc60003f86070 */
/*00b0*/ @!P0 BRA 0x100 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R2.64+-0x4] ; /* 0xfffffc0402057981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ BSSY B0, 0x180 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0120*/ @!P1 BRA 0x170 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0130*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*0140*/ LDG.E R0, [R2.64+-0x8] ; /* 0xfffff80402007981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ BSSY B0, 0x1f0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0190*/ @!P2 BRA 0x1e0 ; /* 0x000000400000a947 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*01b0*/ LDG.E R0, [R2.64+-0x10] ; /* 0xfffff00402007981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ BSSY B0, 0x260 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0200*/ @!P3 BRA 0x250 ; /* 0x000000400000b947 */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*0220*/ LDG.E R0, [R2.64+-0x20] ; /* 0xffffe00402007981 */
/* 0x000ea4000c1e1900 */
/*0230*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ @!P4 EXIT ; /* 0x000000000000c94d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*0280*/ LDG.E R0, [R2.64+-0x40] ; /* 0xffffc00402007981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=512 --gridDim=1 --warp-sync=32 --no-inline
#include <cuda.h>
#include <stdio.h>
#define N 32
__global__ void scan (int* A)
{
int tid = threadIdx.x;
unsigned int lane = tid & 31;
if (lane >= 1) A[tid] = A[tid - 1] + A[tid];
if (lane >= 2) A[tid] = A[tid - 2] + A[tid];
if (lane >= 4) A[tid] = A[tid - 4] + A[tid];
if (lane >= 8) A[tid] = A[tid - 8] + A[tid];
if (lane >= 16) A[tid] = A[tid - 16] + A[tid];
} | .file "tmpxft_000d058a_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4scanPiPi
.type _Z23__device_stub__Z4scanPiPi, @function
_Z23__device_stub__Z4scanPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z23__device_stub__Z4scanPiPi, .-_Z23__device_stub__Z4scanPiPi
.globl _Z4scanPi
.type _Z4scanPi, @function
_Z4scanPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z4scanPi, .-_Z4scanPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4scanPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=512 --gridDim=1 --warp-sync=32 --no-inline
#include <cuda.h>
#include <stdio.h>
#define N 32
__global__ void scan (int* A)
{
int tid = threadIdx.x;
unsigned int lane = tid & 31;
if (lane >= 1) A[tid] = A[tid - 1] + A[tid];
if (lane >= 2) A[tid] = A[tid - 2] + A[tid];
if (lane >= 4) A[tid] = A[tid - 4] + A[tid];
if (lane >= 8) A[tid] = A[tid - 8] + A[tid];
if (lane >= 16) A[tid] = A[tid - 16] + A[tid];
} | //pass
//--blockDim=512 --gridDim=1 --warp-sync=32 --no-inline
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 32
__global__ void scan (int* A)
{
int tid = threadIdx.x;
unsigned int lane = tid & 31;
if (lane >= 1) A[tid] = A[tid - 1] + A[tid];
if (lane >= 2) A[tid] = A[tid - 2] + A[tid];
if (lane >= 4) A[tid] = A[tid - 4] + A[tid];
if (lane >= 8) A[tid] = A[tid - 8] + A[tid];
if (lane >= 16) A[tid] = A[tid - 16] + A[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=512 --gridDim=1 --warp-sync=32 --no-inline
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 32
__global__ void scan (int* A)
{
int tid = threadIdx.x;
unsigned int lane = tid & 31;
if (lane >= 1) A[tid] = A[tid - 1] + A[tid];
if (lane >= 2) A[tid] = A[tid - 2] + A[tid];
if (lane >= 4) A[tid] = A[tid - 4] + A[tid];
if (lane >= 8) A[tid] = A[tid - 8] + A[tid];
if (lane >= 16) A[tid] = A[tid - 16] + A[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPi
.globl _Z4scanPi
.p2align 8
.type _Z4scanPi,@function
_Z4scanPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_and_b32_e32 v1, 31, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v2, s[0:1] offset:-4
global_load_b32 v4, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v2, v3, s[0:1]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 1, v1
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v2, s[0:1] offset:-8
global_load_b32 v4, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v2, v3, s[0:1]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 3, v1
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v2, s[0:1] offset:-16
global_load_b32 v4, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v2, v3, s[0:1]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 7, v1
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v2, s[0:1] offset:-32
global_load_b32 v4, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v2, v3, s[0:1]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 15, v1
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[0:1] offset:-64
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4scanPi, .Lfunc_end0-_Z4scanPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z4scanPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=512 --gridDim=1 --warp-sync=32 --no-inline
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 32
__global__ void scan (int* A)
{
int tid = threadIdx.x;
unsigned int lane = tid & 31;
if (lane >= 1) A[tid] = A[tid - 1] + A[tid];
if (lane >= 2) A[tid] = A[tid - 2] + A[tid];
if (lane >= 4) A[tid] = A[tid - 4] + A[tid];
if (lane >= 8) A[tid] = A[tid - 8] + A[tid];
if (lane >= 16) A[tid] = A[tid - 16] + A[tid];
} | .text
.file "main.hip"
.globl _Z19__device_stub__scanPi # -- Begin function _Z19__device_stub__scanPi
.p2align 4, 0x90
.type _Z19__device_stub__scanPi,@function
_Z19__device_stub__scanPi: # @_Z19__device_stub__scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__scanPi, .Lfunc_end0-_Z19__device_stub__scanPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPi,@object # @_Z4scanPi
.section .rodata,"a",@progbits
.globl _Z4scanPi
.p2align 3, 0x0
_Z4scanPi:
.quad _Z19__device_stub__scanPi
.size _Z4scanPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4scanPi"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4scanPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x110 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0050*/ LOP3.LUT P0, R0, R2.reuse, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f02007812 */
/* 0x041fe2000780c0ff */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0203 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R0.reuse, 0x2, PT ; /* 0x000000020000780c */
/* 0x040fe40003f26070 */
/*0080*/ ISETP.GE.U32.AND P2, PT, R0.reuse, 0x4, PT ; /* 0x000000040000780c */
/* 0x040fe40003f46070 */
/*0090*/ ISETP.GE.U32.AND P3, PT, R0.reuse, 0x8, PT ; /* 0x000000080000780c */
/* 0x040fe40003f66070 */
/*00a0*/ ISETP.GE.U32.AND P4, PT, R0, 0x10, PT ; /* 0x000000100000780c */
/* 0x000fc60003f86070 */
/*00b0*/ @!P0 BRA 0x100 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R5, [R2.64+-0x4] ; /* 0xfffffc0402057981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ BSSY B0, 0x180 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0120*/ @!P1 BRA 0x170 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0130*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*0140*/ LDG.E R0, [R2.64+-0x8] ; /* 0xfffff80402007981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ BSSY B0, 0x1f0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0190*/ @!P2 BRA 0x1e0 ; /* 0x000000400000a947 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*01b0*/ LDG.E R0, [R2.64+-0x10] ; /* 0xfffff00402007981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ BSSY B0, 0x260 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0200*/ @!P3 BRA 0x250 ; /* 0x000000400000b947 */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*0220*/ LDG.E R0, [R2.64+-0x20] ; /* 0xffffe00402007981 */
/* 0x000ea4000c1e1900 */
/*0230*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ @!P4 EXIT ; /* 0x000000000000c94d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*0280*/ LDG.E R0, [R2.64+-0x40] ; /* 0xffffc00402007981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x004fca0007ffe0ff */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4scanPi
.globl _Z4scanPi
.p2align 8
.type _Z4scanPi,@function
_Z4scanPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_and_b32_e32 v1, 31, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e32 0, v1
s_cbranch_execz .LBB0_2
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v2, s[0:1] offset:-4
global_load_b32 v4, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v2, v3, s[0:1]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 1, v1
s_cbranch_execz .LBB0_4
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v2, s[0:1] offset:-8
global_load_b32 v4, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v2, v3, s[0:1]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 3, v1
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v2, s[0:1] offset:-16
global_load_b32 v4, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v2, v3, s[0:1]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 7, v1
s_cbranch_execz .LBB0_8
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v3, v2, s[0:1] offset:-32
global_load_b32 v4, v2, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v2, v3, s[0:1]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
v_cmpx_lt_u32_e32 15, v1
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[0:1] offset:-64
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4scanPi, .Lfunc_end0-_Z4scanPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z4scanPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d058a_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4scanPiPi
.type _Z23__device_stub__Z4scanPiPi, @function
_Z23__device_stub__Z4scanPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z23__device_stub__Z4scanPiPi, .-_Z23__device_stub__Z4scanPiPi
.globl _Z4scanPi
.type _Z4scanPi, @function
_Z4scanPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z4scanPi, .-_Z4scanPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4scanPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z19__device_stub__scanPi # -- Begin function _Z19__device_stub__scanPi
.p2align 4, 0x90
.type _Z19__device_stub__scanPi,@function
_Z19__device_stub__scanPi: # @_Z19__device_stub__scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__scanPi, .Lfunc_end0-_Z19__device_stub__scanPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4scanPi,@object # @_Z4scanPi
.section .rodata,"a",@progbits
.globl _Z4scanPi
.p2align 3, 0x0
_Z4scanPi:
.quad _Z19__device_stub__scanPi
.size _Z4scanPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4scanPi"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__scanPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4scanPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/reduce.h>
int main()
{
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/reduce.h>
int main()
{
} | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/reduce.h>
int main()
{
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/reduce.h>
int main()
{
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/reduce.h>
int main()
{
} | .text
.file "ThrustTest.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include "cuda_runtime.h"
__global__ void addone(int *a)
{
*a = *a + 1;
printf("add one \n");
}
int main()
{
int a = 0;
int *d_a;
cudaMalloc(&d_a, sizeof(int));
cudaMemcpy(d_a, &a, sizeof(int), cudaMemcpyHostToDevice);
addone<<<1,32>>>(d_a);
cudaMemcpy(&a, d_a, sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<a<<std::endl;
cudaFree(d_a);
return 0;
} | code for sm_80
Function : _Z6addonePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ LDC.64 R10, c[0x4][R0] ; /* 0x01000000000a7b82 */
/* 0x0000620000000a00 */
/*00a0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*00c0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*00d0*/ MOV R9, 0x140 ; /* 0x0000014000097802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0120*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0130*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x000fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include "cuda_runtime.h"
__global__ void addone(int *a)
{
*a = *a + 1;
printf("add one \n");
}
int main()
{
int a = 0;
int *d_a;
cudaMalloc(&d_a, sizeof(int));
cudaMemcpy(d_a, &a, sizeof(int), cudaMemcpyHostToDevice);
addone<<<1,32>>>(d_a);
cudaMemcpy(&a, d_a, sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<a<<std::endl;
cudaFree(d_a);
return 0;
} | .file "tmpxft_0014d3f4_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6addonePiPi
.type _Z25__device_stub__Z6addonePiPi, @function
_Z25__device_stub__Z6addonePiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6addonePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z6addonePiPi, .-_Z25__device_stub__Z6addonePiPi
.globl _Z6addonePi
.type _Z6addonePi, @function
_Z6addonePi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6addonePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6addonePi, .-_Z6addonePi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6addonePiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6addonePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addonePi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include "cuda_runtime.h"
__global__ void addone(int *a)
{
*a = *a + 1;
printf("add one \n");
}
int main()
{
int a = 0;
int *d_a;
cudaMalloc(&d_a, sizeof(int));
cudaMemcpy(d_a, &a, sizeof(int), cudaMemcpyHostToDevice);
addone<<<1,32>>>(d_a);
cudaMemcpy(&a, d_a, sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<a<<std::endl;
cudaFree(d_a);
return 0;
} | #include<iostream>
#include "hip/hip_runtime.h"
__global__ void addone(int *a)
{
*a = *a + 1;
printf("add one \n");
}
int main()
{
int a = 0;
int *d_a;
hipMalloc(&d_a, sizeof(int));
hipMemcpy(d_a, &a, sizeof(int), hipMemcpyHostToDevice);
addone<<<1,32>>>(d_a);
hipMemcpy(&a, d_a, sizeof(int), hipMemcpyDeviceToHost);
std::cout<<a<<std::endl;
hipFree(d_a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<iostream>
#include "hip/hip_runtime.h"
__global__ void addone(int *a)
{
*a = *a + 1;
printf("add one \n");
}
int main()
{
int a = 0;
int *d_a;
hipMalloc(&d_a, sizeof(int));
hipMemcpy(d_a, &a, sizeof(int), hipMemcpyHostToDevice);
addone<<<1,32>>>(d_a);
hipMemcpy(&a, d_a, sizeof(int), hipMemcpyDeviceToHost);
std::cout<<a<<std::endl;
hipFree(d_a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addonePi
.globl _Z6addonePi
.p2align 8
.type _Z6addonePi,@function
_Z6addonePi:
s_load_b64 s[2:3], s[0:1], 0x0
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v4, v20
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s4, 1
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
global_store_b32 v0, v1, s[2:3]
s_load_b64 s[2:3], s[0:1], 0x58
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
s_waitcnt lgkmcnt(0)
global_load_b64 v[7:8], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, v2, v8
v_and_b32_e32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, 24
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[5:6], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v0, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[5:6], v[7:8]
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, 0
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[2:3], v1, s[2:3] offset:40
global_load_b64 v[9:10], v1, s[2:3]
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, v2, v7
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v2, 24, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, v6 :: v_dual_and_b32 v3, v3, v8
v_mad_u64_u32 v[9:10], null, v3, 24, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v9
global_load_b64 v[5:6], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[7:8], v0, s[2:3] offset:40
global_load_b128 v[0:3], v0, s[2:3]
v_readfirstlane_b32 s4, v5
v_readfirstlane_b32 s5, v6
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v7
v_readfirstlane_b32 s7, v8
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[9:10], v[5:8], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 33
s_lshl_b64 s[8:9], s[6:7], 12
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 6, v[4:5]
s_mov_b32 s8, 0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_mov_b32_e32 v9, 0
v_add_co_u32 v6, vcc_lo, v2, v6
v_dual_mov_b32 v15, s11 :: v_dual_mov_b32 v14, s10
v_add_co_ci_u32_e32 v7, vcc_lo, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v13, s9
v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, s8
s_clause 0x3
global_store_b128 v[6:7], v[8:11], off
global_store_b128 v[6:7], v[12:15], off offset:16
global_store_b128 v[6:7], v[12:15], off offset:32
global_store_b128 v[6:7], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
s_clause 0x1
global_load_b64 v[12:13], v5, s[2:3] offset:32 glc
global_load_b64 v[2:3], v5, s[2:3] offset:40
v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[12:13], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v5, v[10:13], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[12:13]
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v10, 0
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 10
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addonePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addonePi, .Lfunc_end0-_Z6addonePi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "add one \n"
.size .str, 10
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
- .offset: 88
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addonePi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z6addonePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<iostream>
#include "hip/hip_runtime.h"
__global__ void addone(int *a)
{
*a = *a + 1;
printf("add one \n");
}
int main()
{
int a = 0;
int *d_a;
hipMalloc(&d_a, sizeof(int));
hipMemcpy(d_a, &a, sizeof(int), hipMemcpyHostToDevice);
addone<<<1,32>>>(d_a);
hipMemcpy(&a, d_a, sizeof(int), hipMemcpyDeviceToHost);
std::cout<<a<<std::endl;
hipFree(d_a);
return 0;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__addonePi # -- Begin function _Z21__device_stub__addonePi
.p2align 4, 0x90
.type _Z21__device_stub__addonePi,@function
_Z21__device_stub__addonePi: # @_Z21__device_stub__addonePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6addonePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__addonePi, .Lfunc_end0-_Z21__device_stub__addonePi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6addonePi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addonePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addonePi,@object # @_Z6addonePi
.section .rodata,"a",@progbits
.globl _Z6addonePi
.p2align 3, 0x0
_Z6addonePi:
.quad _Z21__device_stub__addonePi
.size _Z6addonePi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6addonePi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addonePi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addonePi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6addonePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ LDC.64 R10, c[0x4][R0] ; /* 0x01000000000a7b82 */
/* 0x0000620000000a00 */
/*00a0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*00c0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*00d0*/ MOV R9, 0x140 ; /* 0x0000014000097802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0120*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0130*/ CALL.ABS.NOINC R10 ; /* 0x000000000a007343 */
/* 0x000fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addonePi
.globl _Z6addonePi
.p2align 8
.type _Z6addonePi,@function
_Z6addonePi:
s_load_b64 s[2:3], s[0:1], 0x0
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v4, v20
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s4, 1
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
global_store_b32 v0, v1, s[2:3]
s_load_b64 s[2:3], s[0:1], 0x58
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
s_waitcnt lgkmcnt(0)
global_load_b64 v[7:8], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_mov_b32 s4, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v2, v2, v8
v_and_b32_e32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v2, 24
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[5:6], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v0, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[5:6], v[7:8]
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, 0
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[2:3], v1, s[2:3] offset:40
global_load_b64 v[9:10], v1, s[2:3]
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, v2, v7
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v2, 24, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v2, v6 :: v_dual_and_b32 v3, v3, v8
v_mad_u64_u32 v[9:10], null, v3, 24, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v9
global_load_b64 v[5:6], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[5:6], v1, v[5:8], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[7:8]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[7:8], v0, s[2:3] offset:40
global_load_b128 v[0:3], v0, s[2:3]
v_readfirstlane_b32 s4, v5
v_readfirstlane_b32 s5, v6
s_mov_b32 s8, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v7
v_readfirstlane_b32 s7, v8
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v7, 2 :: v_dual_mov_b32 v8, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v9, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[9:10], v[5:8], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 33
s_lshl_b64 s[8:9], s[6:7], 12
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 6, v[4:5]
s_mov_b32 s8, 0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_mov_b32_e32 v9, 0
v_add_co_u32 v6, vcc_lo, v2, v6
v_dual_mov_b32 v15, s11 :: v_dual_mov_b32 v14, s10
v_add_co_ci_u32_e32 v7, vcc_lo, v3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v13, s9
v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v12, s8
s_clause 0x3
global_store_b128 v[6:7], v[8:11], off
global_store_b128 v[6:7], v[12:15], off offset:16
global_store_b128 v[6:7], v[12:15], off offset:32
global_store_b128 v[6:7], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
s_clause 0x1
global_load_b64 v[12:13], v5, s[2:3] offset:32 glc
global_load_b64 v[2:3], v5, s[2:3] offset:40
v_dual_mov_b32 v10, s4 :: v_dual_mov_b32 v11, s5
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[12:13], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v5, v[10:13], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[12:13]
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v10, 0
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 10
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addonePi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addonePi, .Lfunc_end0-_Z6addonePi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "add one \n"
.size .str, 10
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
- .offset: 88
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addonePi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z6addonePi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014d3f4_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6addonePiPi
.type _Z25__device_stub__Z6addonePiPi, @function
_Z25__device_stub__Z6addonePiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6addonePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z6addonePiPi, .-_Z25__device_stub__Z6addonePiPi
.globl _Z6addonePi
.type _Z6addonePi, @function
_Z6addonePi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6addonePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6addonePi, .-_Z6addonePi
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6addonePiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6addonePi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addonePi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__addonePi # -- Begin function _Z21__device_stub__addonePi
.p2align 4, 0x90
.type _Z21__device_stub__addonePi,@function
_Z21__device_stub__addonePi: # @_Z21__device_stub__addonePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6addonePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__addonePi, .Lfunc_end0-_Z21__device_stub__addonePi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6addonePi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB1_6
.LBB1_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addonePi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addonePi,@object # @_Z6addonePi
.section .rodata,"a",@progbits
.globl _Z6addonePi
.p2align 3, 0x0
_Z6addonePi:
.quad _Z21__device_stub__addonePi
.size _Z6addonePi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6addonePi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addonePi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addonePi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
__global__ void MatrixMulKernel(int m, int n, int k, float *A, float *B, float *C)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
if ((Row < m) && (Col < k))
{
float Cvalue = 0.0;
for (int i = 0; i < n; ++i)
Cvalue += A[Row * n + i] * B[Col + i * k];
C[Row * k + Col] = Cvalue;
}
}
#define TILE_WIDTH 16
int main()
{
//这里将矩阵按照行优先转换成了一维的形式
int m = 4096, n = 4096, k = 4096;
float *A = (float *)malloc(m * n * sizeof(float));
float *B = (float *)malloc(n * k * sizeof(float));
float *C = (float *)malloc(m * k * sizeof(float));
float *result = (float *)malloc(m * k * sizeof(float));
for (int i = 0; i < m; ++i)
for (int j = 0; j < m; ++j)
{
A[i * m + j] = (i - 0.1 * j + 1) / (i + j + 1);
B[i * m + j] = (j - 0.2 * i + 1) * (i + j + 1) / (i * i + j * j + 1);
C[i * m + j] = 0.0;
}
//分配显存空间
int size = sizeof(float);
float *d_a;
float *d_b;
float *d_c;
// GPU time calculate start
cudaEvent_t start, stop;
float elapsedTime = 0.0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMalloc((void **)&d_a, m * n * size);
cudaMalloc((void **)&d_b, n * k * size);
cudaMalloc((void **)&d_c, m * k * size);
//把数据从Host传到Device
cudaMemcpy(d_a, A, size * m * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, B, size * n * k, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, C, size * m * k, cudaMemcpyHostToDevice);
//分配网格结构
dim3 dimGrid((k - 1) / TILE_WIDTH + 1, (m - 1) / TILE_WIDTH + 1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//调用内核函数
MatrixMulKernel<<<dimGrid, dimBlock>>>(m, n, k, d_a, d_b, d_c);
//将结果传回到主机端
cudaMemcpy(C, d_c, size * m * k, cudaMemcpyDeviceToHost);
// GPU time calculate end
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU time: " << elapsedTime << " ms" << endl;
//CPU计算正确结果
clock_t begin = clock();
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < m; ++j)
{
float sum = 0;
for (int k = 0; k < m; ++k)
sum += A[i * m + k] * B[k * m + j];
result[i * m + j] = sum;
}
}
clock_t end = clock();
cout << "CPU time: " << (end - begin) * 1000 / CLOCKS_PER_SEC << " ms" << endl;
//比较结果
bool flag = true;
for (int i = 0; i < m * k; ++i)
{
if (abs(result[i] - C[i]) > 0.001)
{
flag = false;
cout << result[i] << "-" << C[i] << endl;
}
}
if (flag)
cout << "Check answer: Correct!" << endl;
else
cout << "Check answer: Error!" << endl;
//释放显存空间
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(A);
free(B);
free(C);
free(result);
return 0;
} | code for sm_80
Function : _Z15MatrixMulKerneliiiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x160], P0 ; /* 0x0000580003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x164] ; /* 0x0000590000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x164], RZ ; /* 0x0000590004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x164], RZ ; /* 0x0000590003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x164], R2 ; /* 0x0000590003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x168], R0 ; /* 0x00005a0002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x168] ; /* 0x00005a00000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
__global__ void MatrixMulKernel(int m, int n, int k, float *A, float *B, float *C)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
if ((Row < m) && (Col < k))
{
float Cvalue = 0.0;
for (int i = 0; i < n; ++i)
Cvalue += A[Row * n + i] * B[Col + i * k];
C[Row * k + Col] = Cvalue;
}
}
#define TILE_WIDTH 16
int main()
{
//这里将矩阵按照行优先转换成了一维的形式
int m = 4096, n = 4096, k = 4096;
float *A = (float *)malloc(m * n * sizeof(float));
float *B = (float *)malloc(n * k * sizeof(float));
float *C = (float *)malloc(m * k * sizeof(float));
float *result = (float *)malloc(m * k * sizeof(float));
for (int i = 0; i < m; ++i)
for (int j = 0; j < m; ++j)
{
A[i * m + j] = (i - 0.1 * j + 1) / (i + j + 1);
B[i * m + j] = (j - 0.2 * i + 1) * (i + j + 1) / (i * i + j * j + 1);
C[i * m + j] = 0.0;
}
//分配显存空间
int size = sizeof(float);
float *d_a;
float *d_b;
float *d_c;
// GPU time calculate start
cudaEvent_t start, stop;
float elapsedTime = 0.0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMalloc((void **)&d_a, m * n * size);
cudaMalloc((void **)&d_b, n * k * size);
cudaMalloc((void **)&d_c, m * k * size);
//把数据从Host传到Device
cudaMemcpy(d_a, A, size * m * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, B, size * n * k, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, C, size * m * k, cudaMemcpyHostToDevice);
//分配网格结构
dim3 dimGrid((k - 1) / TILE_WIDTH + 1, (m - 1) / TILE_WIDTH + 1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//调用内核函数
MatrixMulKernel<<<dimGrid, dimBlock>>>(m, n, k, d_a, d_b, d_c);
//将结果传回到主机端
cudaMemcpy(C, d_c, size * m * k, cudaMemcpyDeviceToHost);
// GPU time calculate end
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU time: " << elapsedTime << " ms" << endl;
//CPU计算正确结果
clock_t begin = clock();
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < m; ++j)
{
float sum = 0;
for (int k = 0; k < m; ++k)
sum += A[i * m + k] * B[k * m + j];
result[i * m + j] = sum;
}
}
clock_t end = clock();
cout << "CPU time: " << (end - begin) * 1000 / CLOCKS_PER_SEC << " ms" << endl;
//比较结果
bool flag = true;
for (int i = 0; i < m * k; ++i)
{
if (abs(result[i] - C[i]) > 0.001)
{
flag = false;
cout << result[i] << "-" << C[i] << endl;
}
}
if (flag)
cout << "Check answer: Correct!" << endl;
else
cout << "Check answer: Error!" << endl;
//释放显存空间
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(A);
free(B);
free(C);
free(result);
return 0;
} | .file "tmpxft_001161d2_00000000-6_global_memory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_
.type _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_, @function
_Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKerneliiiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_, .-_Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_
.globl _Z15MatrixMulKerneliiiPfS_S_
.type _Z15MatrixMulKerneliiiPfS_S_, @function
_Z15MatrixMulKerneliiiPfS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15MatrixMulKerneliiiPfS_S_, .-_Z15MatrixMulKerneliiiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU time: "
.LC5:
.string " ms"
.LC6:
.string "CPU time: "
.LC9:
.string "-"
.LC10:
.string "Check answer: Correct!"
.LC11:
.string "Check answer: Error!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rsi
movq %rbp, %rcx
movq %r12, %rdx
movl $0, %r9d
movsd .LC1(%rip), %xmm5
movsd .LC2(%rip), %xmm3
.L12:
pxor %xmm4, %xmm4
cvtsi2sdl %r9d, %xmm4
movsd .LC3(%rip), %xmm6
mulsd %xmm4, %xmm6
movl %r9d, %r8d
imull %r9d, %r8d
movl $0, %eax
leal 1(%r9), %edi
.L13:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
leal (%rdi,%rax), %r10d
pxor %xmm2, %xmm2
cvtsi2sdl %r10d, %xmm2
movapd %xmm0, %xmm7
mulsd %xmm5, %xmm7
movapd %xmm4, %xmm1
subsd %xmm7, %xmm1
addsd %xmm3, %xmm1
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rdx,%rax,4)
subsd %xmm6, %xmm0
addsd %xmm3, %xmm0
mulsd %xmm2, %xmm0
movl %eax, %r10d
imull %eax, %r10d
leal 1(%r8,%r10), %r10d
pxor %xmm1, %xmm1
cvtsi2sdl %r10d, %xmm1
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rcx,%rax,4)
movl $0x00000000, (%rsi,%rax,4)
addq $1, %rax
cmpq $4096, %rax
jne .L13
addl $1, %r9d
addq $16384, %rdx
addq $16384, %rcx
addq $16384, %rsi
cmpl $4096, %r9d
jne .L12
movl $0x00000000, 20(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 64(%rsp)
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L15:
movl $2, %ecx
movl $67108864, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %r13
movl $0, %r9d
jmp .L16
.L36:
movq 40(%rsp), %r9
movq 32(%rsp), %r8
movq 24(%rsp), %rcx
movl $4096, %edx
movl $4096, %esi
movl $4096, %edi
call _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_
jmp .L15
.L37:
movss %xmm1, (%rdi,%rsi,4)
addq $1, %rsi
addq $4, %rcx
cmpq $4096, %rsi
je .L18
.L20:
leaq -67108864(%rcx), %rax
movq %r8, %rdx
pxor %xmm1, %xmm1
.L17:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rdx
addq $16384, %rax
cmpq %rcx, %rax
jne .L17
jmp .L37
.L18:
addq $1, %r9
cmpq $4096, %r9
je .L19
.L16:
leaq 67108864(%rbp), %rcx
movq %r9, %rdi
salq $14, %rdi
leaq (%r12,%rdi), %r8
movq 8(%rsp), %rax
addq %rax, %rdi
movl $0, %esi
jmp .L20
.L19:
call clock@PLT
movq %rax, %r14
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r14, %rcx
subq %r13, %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rsi
subq %rcx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r13d
movl $1, %eax
jmp .L27
.L40:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L38
call _ZSt16__throw_bad_castv@PLT
.L38:
call __stack_chk_fail@PLT
.L25:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
.L26:
movsbl %al, %esi
movq %r15, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L21:
addq $4, %r13
cmpq $67108864, %r13
je .L39
.L27:
movq 8(%rsp), %rsi
movss (%rsi,%r13), %xmm1
movaps %xmm1, %xmm0
subss (%rbx,%r13), %xmm0
andps .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC8(%rip), %xmm0
jbe .L21
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r14
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r13), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .L40
cmpb $0, 56(%r14)
je .L25
movzbl 67(%r14), %eax
jmp .L26
.L39:
testb %al, %al
je .L28
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L29:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L29
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z15MatrixMulKerneliiiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKerneliiiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1717986918
.long 1069128089
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long -1717986918
.long 1070176665
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC8:
.long -755914244
.long 1062232653
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
__global__ void MatrixMulKernel(int m, int n, int k, float *A, float *B, float *C)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
if ((Row < m) && (Col < k))
{
float Cvalue = 0.0;
for (int i = 0; i < n; ++i)
Cvalue += A[Row * n + i] * B[Col + i * k];
C[Row * k + Col] = Cvalue;
}
}
#define TILE_WIDTH 16
int main()
{
//这里将矩阵按照行优先转换成了一维的形式
int m = 4096, n = 4096, k = 4096;
float *A = (float *)malloc(m * n * sizeof(float));
float *B = (float *)malloc(n * k * sizeof(float));
float *C = (float *)malloc(m * k * sizeof(float));
float *result = (float *)malloc(m * k * sizeof(float));
for (int i = 0; i < m; ++i)
for (int j = 0; j < m; ++j)
{
A[i * m + j] = (i - 0.1 * j + 1) / (i + j + 1);
B[i * m + j] = (j - 0.2 * i + 1) * (i + j + 1) / (i * i + j * j + 1);
C[i * m + j] = 0.0;
}
//分配显存空间
int size = sizeof(float);
float *d_a;
float *d_b;
float *d_c;
// GPU time calculate start
cudaEvent_t start, stop;
float elapsedTime = 0.0;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMalloc((void **)&d_a, m * n * size);
cudaMalloc((void **)&d_b, n * k * size);
cudaMalloc((void **)&d_c, m * k * size);
//把数据从Host传到Device
cudaMemcpy(d_a, A, size * m * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, B, size * n * k, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, C, size * m * k, cudaMemcpyHostToDevice);
//分配网格结构
dim3 dimGrid((k - 1) / TILE_WIDTH + 1, (m - 1) / TILE_WIDTH + 1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//调用内核函数
MatrixMulKernel<<<dimGrid, dimBlock>>>(m, n, k, d_a, d_b, d_c);
//将结果传回到主机端
cudaMemcpy(C, d_c, size * m * k, cudaMemcpyDeviceToHost);
// GPU time calculate end
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU time: " << elapsedTime << " ms" << endl;
//CPU计算正确结果
clock_t begin = clock();
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < m; ++j)
{
float sum = 0;
for (int k = 0; k < m; ++k)
sum += A[i * m + k] * B[k * m + j];
result[i * m + j] = sum;
}
}
clock_t end = clock();
cout << "CPU time: " << (end - begin) * 1000 / CLOCKS_PER_SEC << " ms" << endl;
//比较结果
bool flag = true;
for (int i = 0; i < m * k; ++i)
{
if (abs(result[i] - C[i]) > 0.001)
{
flag = false;
cout << result[i] << "-" << C[i] << endl;
}
}
if (flag)
cout << "Check answer: Correct!" << endl;
else
cout << "Check answer: Error!" << endl;
//释放显存空间
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(A);
free(B);
free(C);
free(result);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void MatrixMulKernel(int m, int n, int k, float *A, float *B, float *C)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
if ((Row < m) && (Col < k))
{
float Cvalue = 0.0;
for (int i = 0; i < n; ++i)
Cvalue += A[Row * n + i] * B[Col + i * k];
C[Row * k + Col] = Cvalue;
}
}
#define TILE_WIDTH 16
int main()
{
//这里将矩阵按照行优先转换成了一维的形式
int m = 4096, n = 4096, k = 4096;
float *A = (float *)malloc(m * n * sizeof(float));
float *B = (float *)malloc(n * k * sizeof(float));
float *C = (float *)malloc(m * k * sizeof(float));
float *result = (float *)malloc(m * k * sizeof(float));
for (int i = 0; i < m; ++i)
for (int j = 0; j < m; ++j)
{
A[i * m + j] = (i - 0.1 * j + 1) / (i + j + 1);
B[i * m + j] = (j - 0.2 * i + 1) * (i + j + 1) / (i * i + j * j + 1);
C[i * m + j] = 0.0;
}
//分配显存空间
int size = sizeof(float);
float *d_a;
float *d_b;
float *d_c;
// GPU time calculate start
hipEvent_t start, stop;
float elapsedTime = 0.0;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMalloc((void **)&d_a, m * n * size);
hipMalloc((void **)&d_b, n * k * size);
hipMalloc((void **)&d_c, m * k * size);
//把数据从Host传到Device
hipMemcpy(d_a, A, size * m * n, hipMemcpyHostToDevice);
hipMemcpy(d_b, B, size * n * k, hipMemcpyHostToDevice);
hipMemcpy(d_c, C, size * m * k, hipMemcpyHostToDevice);
//分配网格结构
dim3 dimGrid((k - 1) / TILE_WIDTH + 1, (m - 1) / TILE_WIDTH + 1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//调用内核函数
MatrixMulKernel<<<dimGrid, dimBlock>>>(m, n, k, d_a, d_b, d_c);
//将结果传回到主机端
hipMemcpy(C, d_c, size * m * k, hipMemcpyDeviceToHost);
// GPU time calculate end
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU time: " << elapsedTime << " ms" << endl;
//CPU计算正确结果
clock_t begin = clock();
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < m; ++j)
{
float sum = 0;
for (int k = 0; k < m; ++k)
sum += A[i * m + k] * B[k * m + j];
result[i * m + j] = sum;
}
}
clock_t end = clock();
cout << "CPU time: " << (end - begin) * 1000 / CLOCKS_PER_SEC << " ms" << endl;
//比较结果
bool flag = true;
for (int i = 0; i < m * k; ++i)
{
if (abs(result[i] - C[i]) > 0.001)
{
flag = false;
cout << result[i] << "-" << C[i] << endl;
}
}
if (flag)
cout << "Check answer: Correct!" << endl;
else
cout << "Check answer: Error!" << endl;
//释放显存空间
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(A);
free(B);
free(C);
free(result);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void MatrixMulKernel(int m, int n, int k, float *A, float *B, float *C)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
if ((Row < m) && (Col < k))
{
float Cvalue = 0.0;
for (int i = 0; i < n; ++i)
Cvalue += A[Row * n + i] * B[Col + i * k];
C[Row * k + Col] = Cvalue;
}
}
#define TILE_WIDTH 16
int main()
{
//这里将矩阵按照行优先转换成了一维的形式
int m = 4096, n = 4096, k = 4096;
float *A = (float *)malloc(m * n * sizeof(float));
float *B = (float *)malloc(n * k * sizeof(float));
float *C = (float *)malloc(m * k * sizeof(float));
float *result = (float *)malloc(m * k * sizeof(float));
for (int i = 0; i < m; ++i)
for (int j = 0; j < m; ++j)
{
A[i * m + j] = (i - 0.1 * j + 1) / (i + j + 1);
B[i * m + j] = (j - 0.2 * i + 1) * (i + j + 1) / (i * i + j * j + 1);
C[i * m + j] = 0.0;
}
//分配显存空间
int size = sizeof(float);
float *d_a;
float *d_b;
float *d_c;
// GPU time calculate start
hipEvent_t start, stop;
float elapsedTime = 0.0;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMalloc((void **)&d_a, m * n * size);
hipMalloc((void **)&d_b, n * k * size);
hipMalloc((void **)&d_c, m * k * size);
//把数据从Host传到Device
hipMemcpy(d_a, A, size * m * n, hipMemcpyHostToDevice);
hipMemcpy(d_b, B, size * n * k, hipMemcpyHostToDevice);
hipMemcpy(d_c, C, size * m * k, hipMemcpyHostToDevice);
//分配网格结构
dim3 dimGrid((k - 1) / TILE_WIDTH + 1, (m - 1) / TILE_WIDTH + 1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//调用内核函数
MatrixMulKernel<<<dimGrid, dimBlock>>>(m, n, k, d_a, d_b, d_c);
//将结果传回到主机端
hipMemcpy(C, d_c, size * m * k, hipMemcpyDeviceToHost);
// GPU time calculate end
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU time: " << elapsedTime << " ms" << endl;
//CPU计算正确结果
clock_t begin = clock();
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < m; ++j)
{
float sum = 0;
for (int k = 0; k < m; ++k)
sum += A[i * m + k] * B[k * m + j];
result[i * m + j] = sum;
}
}
clock_t end = clock();
cout << "CPU time: " << (end - begin) * 1000 / CLOCKS_PER_SEC << " ms" << endl;
//比较结果
bool flag = true;
for (int i = 0; i < m * k; ++i)
{
if (abs(result[i] - C[i]) > 0.001)
{
flag = false;
cout << result[i] << "-" << C[i] << endl;
}
}
if (flag)
cout << "Check answer: Correct!" << endl;
else
cout << "Check answer: Error!" << endl;
//释放显存空间
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(A);
free(B);
free(C);
free(result);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKerneliiiPfS_S_
.globl _Z15MatrixMulKerneliiiPfS_S_
.p2align 8
.type _Z15MatrixMulKerneliiiPfS_S_,@function
_Z15MatrixMulKerneliiiPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x10
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKerneliiiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKerneliiiPfS_S_, .Lfunc_end0-_Z15MatrixMulKerneliiiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKerneliiiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKerneliiiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void MatrixMulKernel(int m, int n, int k, float *A, float *B, float *C)
{
int Row = blockIdx.y * blockDim.y + threadIdx.y;
int Col = blockIdx.x * blockDim.x + threadIdx.x;
if ((Row < m) && (Col < k))
{
float Cvalue = 0.0;
for (int i = 0; i < n; ++i)
Cvalue += A[Row * n + i] * B[Col + i * k];
C[Row * k + Col] = Cvalue;
}
}
#define TILE_WIDTH 16
int main()
{
//这里将矩阵按照行优先转换成了一维的形式
int m = 4096, n = 4096, k = 4096;
float *A = (float *)malloc(m * n * sizeof(float));
float *B = (float *)malloc(n * k * sizeof(float));
float *C = (float *)malloc(m * k * sizeof(float));
float *result = (float *)malloc(m * k * sizeof(float));
for (int i = 0; i < m; ++i)
for (int j = 0; j < m; ++j)
{
A[i * m + j] = (i - 0.1 * j + 1) / (i + j + 1);
B[i * m + j] = (j - 0.2 * i + 1) * (i + j + 1) / (i * i + j * j + 1);
C[i * m + j] = 0.0;
}
//分配显存空间
int size = sizeof(float);
float *d_a;
float *d_b;
float *d_c;
// GPU time calculate start
hipEvent_t start, stop;
float elapsedTime = 0.0;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMalloc((void **)&d_a, m * n * size);
hipMalloc((void **)&d_b, n * k * size);
hipMalloc((void **)&d_c, m * k * size);
//把数据从Host传到Device
hipMemcpy(d_a, A, size * m * n, hipMemcpyHostToDevice);
hipMemcpy(d_b, B, size * n * k, hipMemcpyHostToDevice);
hipMemcpy(d_c, C, size * m * k, hipMemcpyHostToDevice);
//分配网格结构
dim3 dimGrid((k - 1) / TILE_WIDTH + 1, (m - 1) / TILE_WIDTH + 1, 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//调用内核函数
MatrixMulKernel<<<dimGrid, dimBlock>>>(m, n, k, d_a, d_b, d_c);
//将结果传回到主机端
hipMemcpy(C, d_c, size * m * k, hipMemcpyDeviceToHost);
// GPU time calculate end
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
cout << "GPU time: " << elapsedTime << " ms" << endl;
//CPU计算正确结果
clock_t begin = clock();
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < m; ++j)
{
float sum = 0;
for (int k = 0; k < m; ++k)
sum += A[i * m + k] * B[k * m + j];
result[i * m + j] = sum;
}
}
clock_t end = clock();
cout << "CPU time: " << (end - begin) * 1000 / CLOCKS_PER_SEC << " ms" << endl;
//比较结果
bool flag = true;
for (int i = 0; i < m * k; ++i)
{
if (abs(result[i] - C[i]) > 0.001)
{
flag = false;
cout << result[i] << "-" << C[i] << endl;
}
}
if (flag)
cout << "Check answer: Correct!" << endl;
else
cout << "Check answer: Error!" << endl;
//释放显存空间
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(A);
free(B);
free(C);
free(result);
return 0;
} | .text
.file "global_memory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__MatrixMulKerneliiiPfS_S_ # -- Begin function _Z30__device_stub__MatrixMulKerneliiiPfS_S_
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKerneliiiPfS_S_,@function
_Z30__device_stub__MatrixMulKerneliiiPfS_S_: # @_Z30__device_stub__MatrixMulKerneliiiPfS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKerneliiiPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKerneliiiPfS_S_, .Lfunc_end0-_Z30__device_stub__MatrixMulKerneliiiPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fc999999999999a # double 0.20000000000000001
.LCPI1_1:
.quad 0xbfb999999999999a # double -0.10000000000000001
.LCPI1_2:
.quad 0x3ff0000000000000 # double 1
.LCPI1_4:
.quad 0x3f50624dd2f1a9fc # double 0.001
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_3:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader147
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movq %r13, %rsi
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
incq %r13
movapd %xmm3, %xmm4
mulsd %xmm0, %xmm4
imulq %rsi, %rsi
incq %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm5, %xmm5
cvtsi2sd %edi, %xmm5
movapd %xmm5, %xmm6
mulsd %xmm1, %xmm6
addsd %xmm3, %xmm6
leal (%rax,%rdi), %r8d
xorps %xmm7, %xmm7
cvtsi2sd %r8d, %xmm7
addsd %xmm2, %xmm6
divsd %xmm7, %xmm6
cvtsd2ss %xmm6, %xmm6
subsd %xmm4, %xmm5
addsd %xmm2, %xmm5
movl %edi, %r8d
imull %edi, %r8d
addl %esi, %r8d
xorps %xmm8, %xmm8
cvtsi2sd %r8d, %xmm8
mulsd %xmm7, %xmm5
divsd %xmm8, %xmm5
cvtsd2ss %xmm5, %xmm5
movss %xmm6, (%rcx,%rdi,4)
movss %xmm5, (%rdx,%rdi,4)
incq %rdi
cmpq $4096, %rdi # imm = 0x1000
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $16384, %rdx # imm = 0x4000
addq $16384, %rcx # imm = 0x4000
cmpq $4096, %r13 # imm = 0x1000
jne .LBB1_1
# %bb.4:
movl $0, 4(%rsp)
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 40(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 40(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, 16(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $1099511628032, %rdi # imm = 0x10000000100
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movl $4096, 60(%rsp) # imm = 0x1000
movl $4096, 56(%rsp) # imm = 0x1000
movl $4096, 52(%rsp) # imm = 0x1000
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 52(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z15MatrixMulKerneliiiPfS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB1_37
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB1_9
# %bb.8:
movzbl 67(%rbp), %eax
jmp .LBB1_10
.LBB1_9:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebp, %ebp
callq clock
movq %rax, %r13
movq 16(%rsp), %rax # 8-byte Reload
.p2align 4, 0x90
.LBB1_11: # %.preheader146
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
# Child Loop BB1_13 Depth 3
movq %rbp, %rcx
shlq $14, %rcx
addq %r12, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_12: # %.preheader
# Parent Loop BB1_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_13 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_11 Depth=1
# Parent Loop BB1_12 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $16384, %rdi # imm = 0x4000
cmpq $4096, %r8 # imm = 0x1000
jne .LBB1_13
# %bb.14: # in Loop: Header=BB1_12 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $4096, %rsi # imm = 0x1000
jne .LBB1_12
# %bb.15: # in Loop: Header=BB1_11 Depth=1
incq %rbp
addq $16384, %rax # imm = 0x4000
cmpq $4096, %rbp # imm = 0x1000
jne .LBB1_11
# %bb.16:
callq clock
movq %rax, %rbp
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r13, %rbp
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
movq %rbp, %rax
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r13
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB1_37
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i125
cmpb $0, 56(%rbp)
je .LBB1_19
# %bb.18:
movzbl 67(%rbp), %eax
jmp .LBB1_20
.LBB1_19:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit128
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movb $1, %al
xorl %ebp, %ebp
movaps .LCPI1_3(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_4(%rip), %xmm3 # xmm3 = mem[0],zero
jmp .LBB1_24
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_24 Depth=1
movzbl 67(%r13), %ecx
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit133
# in Loop: Header=BB1_24 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
movaps .LCPI1_3(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_4(%rip), %xmm3 # xmm3 = mem[0],zero
.LBB1_23: # in Loop: Header=BB1_24 Depth=1
incq %rbp
cmpq $16777216, %rbp # imm = 0x1000000
je .LBB1_28
.LBB1_24: # =>This Inner Loop Header: Depth=1
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss (%r15,%rbp,4), %xmm1
andps %xmm2, %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm3, %xmm1
jbe .LBB1_23
# %bb.25: # in Loop: Header=BB1_24 Depth=1
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB1_37
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i130
# in Loop: Header=BB1_24 Depth=1
cmpb $0, 56(%r13)
jne .LBB1_21
# %bb.27: # in Loop: Header=BB1_24 Depth=1
movq %r13, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
jmp .LBB1_22
.LBB1_28:
movl $_ZSt4cout, %edi
testb $1, %al
jne .LBB1_32
# %bb.29:
movl $.L.str.5, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
movq 16(%rsp), %rbx # 8-byte Reload
je .LBB1_37
# %bb.30: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i140
cmpb $0, 56(%r13)
jne .LBB1_34
.LBB1_35:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB1_36
.LBB1_32:
movl $.L.str.4, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
movq 16(%rsp), %rbx # 8-byte Reload
je .LBB1_37
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i135
cmpb $0, 56(%r13)
je .LBB1_35
.LBB1_34:
movzbl 67(%r13), %eax
.LBB1_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit138
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_37:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKerneliiiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKerneliiiPfS_S_,@object # @_Z15MatrixMulKerneliiiPfS_S_
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKerneliiiPfS_S_
.p2align 3, 0x0
_Z15MatrixMulKerneliiiPfS_S_:
.quad _Z30__device_stub__MatrixMulKerneliiiPfS_S_
.size _Z15MatrixMulKerneliiiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU time: "
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU time: "
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "-"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Check answer: Correct!"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Check answer: Error!"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKerneliiiPfS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKerneliiiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKerneliiiPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKerneliiiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x160], P0 ; /* 0x0000580003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x164] ; /* 0x0000590000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x164], RZ ; /* 0x0000590004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x164], RZ ; /* 0x0000590003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x164], R2 ; /* 0x0000590003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x168], R0 ; /* 0x00005a0002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x168] ; /* 0x00005a00000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x180] ; /* 0x0000600003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKerneliiiPfS_S_
.globl _Z15MatrixMulKerneliiiPfS_S_
.p2align 8
.type _Z15MatrixMulKerneliiiPfS_S_,@function
_Z15MatrixMulKerneliiiPfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x10
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKerneliiiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKerneliiiPfS_S_, .Lfunc_end0-_Z15MatrixMulKerneliiiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKerneliiiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKerneliiiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001161d2_00000000-6_global_memory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_
.type _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_, @function
_Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKerneliiiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_, .-_Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_
.globl _Z15MatrixMulKerneliiiPfS_S_
.type _Z15MatrixMulKerneliiiPfS_S_, @function
_Z15MatrixMulKerneliiiPfS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15MatrixMulKerneliiiPfS_S_, .-_Z15MatrixMulKerneliiiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "GPU time: "
.LC5:
.string " ms"
.LC6:
.string "CPU time: "
.LC9:
.string "-"
.LC10:
.string "Check answer: Correct!"
.LC11:
.string "Check answer: Error!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rsi
movq %rbp, %rcx
movq %r12, %rdx
movl $0, %r9d
movsd .LC1(%rip), %xmm5
movsd .LC2(%rip), %xmm3
.L12:
pxor %xmm4, %xmm4
cvtsi2sdl %r9d, %xmm4
movsd .LC3(%rip), %xmm6
mulsd %xmm4, %xmm6
movl %r9d, %r8d
imull %r9d, %r8d
movl $0, %eax
leal 1(%r9), %edi
.L13:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
leal (%rdi,%rax), %r10d
pxor %xmm2, %xmm2
cvtsi2sdl %r10d, %xmm2
movapd %xmm0, %xmm7
mulsd %xmm5, %xmm7
movapd %xmm4, %xmm1
subsd %xmm7, %xmm1
addsd %xmm3, %xmm1
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rdx,%rax,4)
subsd %xmm6, %xmm0
addsd %xmm3, %xmm0
mulsd %xmm2, %xmm0
movl %eax, %r10d
imull %eax, %r10d
leal 1(%r8,%r10), %r10d
pxor %xmm1, %xmm1
cvtsi2sdl %r10d, %xmm1
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rcx,%rax,4)
movl $0x00000000, (%rsi,%rax,4)
addq $1, %rax
cmpq $4096, %rax
jne .L13
addl $1, %r9d
addq $16384, %rdx
addq $16384, %rcx
addq $16384, %rsi
cmpl $4096, %r9d
jne .L12
movl $0x00000000, 20(%rsp)
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 64(%rsp)
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L15:
movl $2, %ecx
movl $67108864, %edx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %r13
movl $0, %r9d
jmp .L16
.L36:
movq 40(%rsp), %r9
movq 32(%rsp), %r8
movq 24(%rsp), %rcx
movl $4096, %edx
movl $4096, %esi
movl $4096, %edi
call _Z42__device_stub__Z15MatrixMulKerneliiiPfS_S_iiiPfS_S_
jmp .L15
.L37:
movss %xmm1, (%rdi,%rsi,4)
addq $1, %rsi
addq $4, %rcx
cmpq $4096, %rsi
je .L18
.L20:
leaq -67108864(%rcx), %rax
movq %r8, %rdx
pxor %xmm1, %xmm1
.L17:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss %xmm0, %xmm1
addq $4, %rdx
addq $16384, %rax
cmpq %rcx, %rax
jne .L17
jmp .L37
.L18:
addq $1, %r9
cmpq $4096, %r9
je .L19
.L16:
leaq 67108864(%rbp), %rcx
movq %r9, %rdi
salq $14, %rdi
leaq (%r12,%rdi), %r8
movq 8(%rsp), %rax
addq %rax, %rdi
movl $0, %esi
jmp .L20
.L19:
call clock@PLT
movq %rax, %r14
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r14, %rcx
subq %r13, %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rsi
subq %rcx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r13d
movl $1, %eax
jmp .L27
.L40:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L38
call _ZSt16__throw_bad_castv@PLT
.L38:
call __stack_chk_fail@PLT
.L25:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
.L26:
movsbl %al, %esi
movq %r15, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
.L21:
addq $4, %r13
cmpq $67108864, %r13
je .L39
.L27:
movq 8(%rsp), %rsi
movss (%rsi,%r13), %xmm1
movaps %xmm1, %xmm0
subss (%rbx,%r13), %xmm0
andps .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
comisd .LC8(%rip), %xmm0
jbe .L21
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r14
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r13), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .L40
cmpb $0, 56(%r14)
je .L25
movzbl 67(%r14), %eax
jmp .L26
.L39:
testb %al, %al
je .L28
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L29:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L29
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z15MatrixMulKerneliiiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKerneliiiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1717986918
.long 1069128089
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long -1717986918
.long 1070176665
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC8:
.long -755914244
.long 1062232653
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "global_memory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__MatrixMulKerneliiiPfS_S_ # -- Begin function _Z30__device_stub__MatrixMulKerneliiiPfS_S_
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKerneliiiPfS_S_,@function
_Z30__device_stub__MatrixMulKerneliiiPfS_S_: # @_Z30__device_stub__MatrixMulKerneliiiPfS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKerneliiiPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKerneliiiPfS_S_, .Lfunc_end0-_Z30__device_stub__MatrixMulKerneliiiPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3fc999999999999a # double 0.20000000000000001
.LCPI1_1:
.quad 0xbfb999999999999a # double -0.10000000000000001
.LCPI1_2:
.quad 0x3ff0000000000000 # double 1
.LCPI1_4:
.quad 0x3f50624dd2f1a9fc # double 0.001
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_3:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1, %eax
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader147
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movq %r13, %rsi
xorps %xmm3, %xmm3
cvtsi2sd %esi, %xmm3
incq %r13
movapd %xmm3, %xmm4
mulsd %xmm0, %xmm4
imulq %rsi, %rsi
incq %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm5, %xmm5
cvtsi2sd %edi, %xmm5
movapd %xmm5, %xmm6
mulsd %xmm1, %xmm6
addsd %xmm3, %xmm6
leal (%rax,%rdi), %r8d
xorps %xmm7, %xmm7
cvtsi2sd %r8d, %xmm7
addsd %xmm2, %xmm6
divsd %xmm7, %xmm6
cvtsd2ss %xmm6, %xmm6
subsd %xmm4, %xmm5
addsd %xmm2, %xmm5
movl %edi, %r8d
imull %edi, %r8d
addl %esi, %r8d
xorps %xmm8, %xmm8
cvtsi2sd %r8d, %xmm8
mulsd %xmm7, %xmm5
divsd %xmm8, %xmm5
cvtsd2ss %xmm5, %xmm5
movss %xmm6, (%rcx,%rdi,4)
movss %xmm5, (%rdx,%rdi,4)
incq %rdi
cmpq $4096, %rdi # imm = 0x1000
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $16384, %rdx # imm = 0x4000
addq $16384, %rcx # imm = 0x4000
cmpq $4096, %r13 # imm = 0x1000
jne .LBB1_1
# %bb.4:
movl $0, 4(%rsp)
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 40(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 40(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, 16(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $1099511628032, %rdi # imm = 0x10000000100
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movl $4096, 60(%rsp) # imm = 0x1000
movl $4096, 56(%rsp) # imm = 0x1000
movl $4096, 52(%rsp) # imm = 0x1000
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rax
movq %rax, 152(%rsp)
leaq 52(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z15MatrixMulKerneliiiPfS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB1_37
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB1_9
# %bb.8:
movzbl 67(%rbp), %eax
jmp .LBB1_10
.LBB1_9:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebp, %ebp
callq clock
movq %rax, %r13
movq 16(%rsp), %rax # 8-byte Reload
.p2align 4, 0x90
.LBB1_11: # %.preheader146
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
# Child Loop BB1_13 Depth 3
movq %rbp, %rcx
shlq $14, %rcx
addq %r12, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_12: # %.preheader
# Parent Loop BB1_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_13 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_13: # Parent Loop BB1_11 Depth=1
# Parent Loop BB1_12 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $16384, %rdi # imm = 0x4000
cmpq $4096, %r8 # imm = 0x1000
jne .LBB1_13
# %bb.14: # in Loop: Header=BB1_12 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $4096, %rsi # imm = 0x1000
jne .LBB1_12
# %bb.15: # in Loop: Header=BB1_11 Depth=1
incq %rbp
addq $16384, %rax # imm = 0x4000
cmpq $4096, %rbp # imm = 0x1000
jne .LBB1_11
# %bb.16:
callq clock
movq %rax, %rbp
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r13, %rbp
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
movq %rbp, %rax
imulq %rcx
movq %rdx, %rsi
shrq $63, %rsi
sarq $7, %rdx
addq %rdx, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r13
movl $.L.str.1, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbp
testq %rbp, %rbp
je .LBB1_37
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i125
cmpb $0, 56(%rbp)
je .LBB1_19
# %bb.18:
movzbl 67(%rbp), %eax
jmp .LBB1_20
.LBB1_19:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit128
movsbl %al, %esi
movq %r13, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movb $1, %al
xorl %ebp, %ebp
movaps .LCPI1_3(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_4(%rip), %xmm3 # xmm3 = mem[0],zero
jmp .LBB1_24
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_24 Depth=1
movzbl 67(%r13), %ecx
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit133
# in Loop: Header=BB1_24 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
movaps .LCPI1_3(%rip), %xmm2 # xmm2 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_4(%rip), %xmm3 # xmm3 = mem[0],zero
.LBB1_23: # in Loop: Header=BB1_24 Depth=1
incq %rbp
cmpq $16777216, %rbp # imm = 0x1000000
je .LBB1_28
.LBB1_24: # =>This Inner Loop Header: Depth=1
movss (%r12,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss (%r15,%rbp,4), %xmm1
andps %xmm2, %xmm1
cvtss2sd %xmm1, %xmm1
ucomisd %xmm3, %xmm1
jbe .LBB1_23
# %bb.25: # in Loop: Header=BB1_24 Depth=1
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r13
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r15,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r13, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB1_37
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i130
# in Loop: Header=BB1_24 Depth=1
cmpb $0, 56(%r13)
jne .LBB1_21
# %bb.27: # in Loop: Header=BB1_24 Depth=1
movq %r13, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
jmp .LBB1_22
.LBB1_28:
movl $_ZSt4cout, %edi
testb $1, %al
jne .LBB1_32
# %bb.29:
movl $.L.str.5, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
movq 16(%rsp), %rbx # 8-byte Reload
je .LBB1_37
# %bb.30: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i140
cmpb $0, 56(%r13)
jne .LBB1_34
.LBB1_35:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB1_36
.LBB1_32:
movl $.L.str.4, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
movq 16(%rsp), %rbx # 8-byte Reload
je .LBB1_37
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i135
cmpb $0, 56(%r13)
je .LBB1_35
.LBB1_34:
movzbl 67(%r13), %eax
.LBB1_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit138
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_37:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKerneliiiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKerneliiiPfS_S_,@object # @_Z15MatrixMulKerneliiiPfS_S_
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKerneliiiPfS_S_
.p2align 3, 0x0
_Z15MatrixMulKerneliiiPfS_S_:
.quad _Z30__device_stub__MatrixMulKerneliiiPfS_S_
.size _Z15MatrixMulKerneliiiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU time: "
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU time: "
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "-"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Check answer: Correct!"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Check answer: Error!"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKerneliiiPfS_S_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKerneliiiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKerneliiiPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* skeleton code for assignment2 COMP4901D
xjia@ust.hk 2015/03
*/
#include <iostream>
#include <cstdio>
#include <cmath>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <thrust/sort.h>
#include <thrust/device_vector.h>
using namespace std;
const int TILE_WIDTH = 1024;
__global__ void mergeJoin(int *key1, float *value1, int *key2, float *value2,int N1,int N2,int *result)
{
//chunk of keys in the shared memory
__shared__ int s_key[TILE_WIDTH];
//start and end positions of the elements in the matching chunk
__shared__ int start;
__shared__ int end;
//add you code here
//load key2 element into shared memory
int index = blockIdx.x * blockDim.x + threadIdx.x;
s_key[threadIdx.x] = key2[index];
__syncthreads();
// first thread in each block is responsible for setting start and end
if (threadIdx.x == 0) {
int min_key = s_key[0];
int max_key = s_key[TILE_WIDTH - 1];
for (int i = 0; i < N1; i ++) {
if (key1[i] >= min_key) {
start = i;
break;
}
}
for (int i = start; i < N1; i ++) {
if (key1[i] <= max_key) {
end = i;
break;
}
}
}
__syncthreads();
//int numberElementPerThread = ceil(double(start - end + 1)/blockDim.x);
//int start_index = start + threadIdx.x * numberElementPerThread;
//int end_index = start + (threadIdx.x + 1) * numberElementPerThread;
if (threadIdx.x + start <= end) {
for (int i = threadIdx.x + start; i <= end; i += blockDim.x) {
int key = key1[i];
bool found = false;
for (int j = 0; j < TILE_WIDTH; j ++) {
if (s_key[j] == key) {
result[i] = blockIdx.x * blockDim.x + j;
found = true;
break;
}
}
if (!found) result[i] = -1;
}
}
}
int main()
{
freopen("in.txt","r",stdin);
int *h_key1, *h_key2, *d_key1, *d_key2;
float *h_value1, *h_value2, *d_value1, *d_value2;
int *h_result, *d_result;
int N1,N2;
scanf("%d%d",&N1,&N2);
h_key1 = (int*)malloc(N1 * sizeof(int));
h_key2 = (int*)malloc(N2 * sizeof(int));
h_value1 = (float*)malloc(N1 * sizeof(float));
h_value2 = (float*)malloc(N2 * sizeof(float));
h_result = (int*)malloc(N1 * sizeof(int));
cudaMalloc(&d_key1, N1 * sizeof(int));
cudaMalloc(&d_key2, N2 * sizeof(int));
cudaMalloc(&d_value1, N1 * sizeof(float));
cudaMalloc(&d_value2, N2 * sizeof(float));
cudaMalloc(&d_result, N1 * sizeof(int));
for(int i = 0; i < N1; ++i)
scanf("%d%f",&h_key1[i],&h_value1[i]);
for(int i = 0; i < N2; ++i)
scanf("%d%f",&h_key2[i],&h_value2[i]);
cudaEvent_t start;
cudaEvent_t stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
memset(h_result,-1,sizeof(int) * N1);
cudaMemcpy(d_key1,h_key1, sizeof(int) * N1, cudaMemcpyHostToDevice);
cudaMemcpy(d_result,h_result, sizeof(int) * N1, cudaMemcpyHostToDevice);
cudaMemcpy(d_key2,h_key2, sizeof(int) * N2, cudaMemcpyHostToDevice);
cudaMemcpy(d_value1,h_value1, sizeof(float) * N1, cudaMemcpyHostToDevice);
cudaMemcpy(d_value2,h_value2, sizeof(float) * N2, cudaMemcpyHostToDevice);
cudaEventRecord(start,0);
thrust::device_ptr<int> dev_key1(d_key1);
thrust::device_ptr<int> dev_key2(d_key2);
thrust::device_ptr<float> dev_value1(d_value1);
thrust::device_ptr<float> dev_value2(d_value2);
thrust::sort_by_key(dev_key1,dev_key1 + N1, dev_value1);
thrust::sort_by_key(dev_key2,dev_key2 + N2, dev_value2);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float ElapsedTime;
cudaEventElapsedTime(&ElapsedTime,start,stop);
printf("Sort Elapsed Time: %.3f ms\n",ElapsedTime);
dim3 grid(ceil(double(N2)/1024));
dim3 block(1024);
cudaEventRecord(start,0);
mergeJoin<<<grid,block>>>(d_key1,d_value1,d_key2,d_value2,N1,N2,d_result);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&ElapsedTime,start,stop);
printf("kernel mergeJoin Elapsed Time: %.3f ms\n",ElapsedTime);
cudaMemcpy(h_result,d_result,sizeof(int) * N1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_key1,d_key1,sizeof(int) * N1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_value1,d_value1,sizeof(float) * N1, cudaMemcpyDeviceToHost);
cudaMemcpy(h_value2,d_value2,sizeof(float) * N1, cudaMemcpyDeviceToHost);
int matched = 0;
freopen("out.txt","w",stdout);
for(int i = 0;i < N1; ++i)
{
if(h_result[i] == -1) {
cout << "h_result[" << i << "] not found " << endl;
continue;
}
matched++;
printf("Key %d\nValue1 %.2f Value2 %.2f\n\n",h_key1[i],h_value1[i],h_value2[h_result[i]]);
}
printf("Matched %d\n",matched);
fclose(stdout);
free(h_key1);
free(h_key2);
free(h_value1);
free(h_value2);
free(h_result);
cudaFree(d_key1);
cudaFree(d_key2);
cudaFree(d_value1);
cudaFree(d_value2);
cudaFree(d_result);
return 0;
} | /* skeleton code for assignment2 COMP4901D
xjia@ust.hk 2015/03
*/
#include <iostream>
#include <cstdio>
#include <cmath>
#include <hip/hip_runtime.h>
#include <thrust/sort.h>
#include <thrust/device_vector.h>
using namespace std;
const int TILE_WIDTH = 1024;
__global__ void mergeJoin(int *key1, float *value1, int *key2, float *value2,int N1,int N2,int *result)
{
//chunk of keys in the shared memory
__shared__ int s_key[TILE_WIDTH];
//start and end positions of the elements in the matching chunk
__shared__ int start;
__shared__ int end;
//add you code here
//load key2 element into shared memory
int index = blockIdx.x * blockDim.x + threadIdx.x;
s_key[threadIdx.x] = key2[index];
__syncthreads();
// first thread in each block is responsible for setting start and end
if (threadIdx.x == 0) {
int min_key = s_key[0];
int max_key = s_key[TILE_WIDTH - 1];
for (int i = 0; i < N1; i ++) {
if (key1[i] >= min_key) {
start = i;
break;
}
}
for (int i = start; i < N1; i ++) {
if (key1[i] <= max_key) {
end = i;
break;
}
}
}
__syncthreads();
//int numberElementPerThread = ceil(double(start - end + 1)/blockDim.x);
//int start_index = start + threadIdx.x * numberElementPerThread;
//int end_index = start + (threadIdx.x + 1) * numberElementPerThread;
if (threadIdx.x + start <= end) {
for (int i = threadIdx.x + start; i <= end; i += blockDim.x) {
int key = key1[i];
bool found = false;
for (int j = 0; j < TILE_WIDTH; j ++) {
if (s_key[j] == key) {
result[i] = blockIdx.x * blockDim.x + j;
found = true;
break;
}
}
if (!found) result[i] = -1;
}
}
}
int main()
{
freopen("in.txt","r",stdin);
int *h_key1, *h_key2, *d_key1, *d_key2;
float *h_value1, *h_value2, *d_value1, *d_value2;
int *h_result, *d_result;
int N1,N2;
scanf("%d%d",&N1,&N2);
h_key1 = (int*)malloc(N1 * sizeof(int));
h_key2 = (int*)malloc(N2 * sizeof(int));
h_value1 = (float*)malloc(N1 * sizeof(float));
h_value2 = (float*)malloc(N2 * sizeof(float));
h_result = (int*)malloc(N1 * sizeof(int));
hipMalloc(&d_key1, N1 * sizeof(int));
hipMalloc(&d_key2, N2 * sizeof(int));
hipMalloc(&d_value1, N1 * sizeof(float));
hipMalloc(&d_value2, N2 * sizeof(float));
hipMalloc(&d_result, N1 * sizeof(int));
for(int i = 0; i < N1; ++i)
scanf("%d%f",&h_key1[i],&h_value1[i]);
for(int i = 0; i < N2; ++i)
scanf("%d%f",&h_key2[i],&h_value2[i]);
hipEvent_t start;
hipEvent_t stop;
hipEventCreate(&start);
hipEventCreate(&stop);
memset(h_result,-1,sizeof(int) * N1);
hipMemcpy(d_key1,h_key1, sizeof(int) * N1, hipMemcpyHostToDevice);
hipMemcpy(d_result,h_result, sizeof(int) * N1, hipMemcpyHostToDevice);
hipMemcpy(d_key2,h_key2, sizeof(int) * N2, hipMemcpyHostToDevice);
hipMemcpy(d_value1,h_value1, sizeof(float) * N1, hipMemcpyHostToDevice);
hipMemcpy(d_value2,h_value2, sizeof(float) * N2, hipMemcpyHostToDevice);
hipEventRecord(start,0);
thrust::device_ptr<int> dev_key1(d_key1);
thrust::device_ptr<int> dev_key2(d_key2);
thrust::device_ptr<float> dev_value1(d_value1);
thrust::device_ptr<float> dev_value2(d_value2);
thrust::sort_by_key(dev_key1,dev_key1 + N1, dev_value1);
thrust::sort_by_key(dev_key2,dev_key2 + N2, dev_value2);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float ElapsedTime;
hipEventElapsedTime(&ElapsedTime,start,stop);
printf("Sort Elapsed Time: %.3f ms\n",ElapsedTime);
dim3 grid(ceil(double(N2)/1024));
dim3 block(1024);
hipEventRecord(start,0);
mergeJoin<<<grid,block>>>(d_key1,d_value1,d_key2,d_value2,N1,N2,d_result);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&ElapsedTime,start,stop);
printf("kernel mergeJoin Elapsed Time: %.3f ms\n",ElapsedTime);
hipMemcpy(h_result,d_result,sizeof(int) * N1, hipMemcpyDeviceToHost);
hipMemcpy(h_key1,d_key1,sizeof(int) * N1, hipMemcpyDeviceToHost);
hipMemcpy(h_value1,d_value1,sizeof(float) * N1, hipMemcpyDeviceToHost);
hipMemcpy(h_value2,d_value2,sizeof(float) * N1, hipMemcpyDeviceToHost);
int matched = 0;
freopen("out.txt","w",stdout);
for(int i = 0;i < N1; ++i)
{
if(h_result[i] == -1) {
cout << "h_result[" << i << "] not found " << endl;
continue;
}
matched++;
printf("Key %d\nValue1 %.2f Value2 %.2f\n\n",h_key1[i],h_value1[i],h_value2[h_result[i]]);
}
printf("Matched %d\n",matched);
fclose(stdout);
free(h_key1);
free(h_key2);
free(h_value1);
free(h_value2);
free(h_result);
hipFree(d_key1);
hipFree(d_key2);
hipFree(d_value1);
hipFree(d_value2);
hipFree(d_result);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define ERR_CHK(call) { gpuAssert((call), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t err, const char* file, int line, bool abort = true)
{
if (err != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(err), file, line);
if (abort) exit(err);
}
}
__global__ void vecAddKernel(int* A, int* B, int* C, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
int main() {
int* d_A, * d_B, * d_C;
int* h_A, * h_B, * h_C;
const int n = 1024;
h_A = (int*)malloc(n * sizeof(int));
h_B = (int*)malloc(n * sizeof(int));
h_C = (int*)malloc(n * sizeof(int));
for (int i = 0; i < n; i++) {
h_A[i] = rand();
h_B[i] = rand();
h_C[i] = 0;
}
ERR_CHK(cudaMalloc((void**)&d_A, n * sizeof(int)));
ERR_CHK(cudaMalloc((void**)&d_B, n * sizeof(int)));
ERR_CHK(cudaMalloc((void**)&d_C, n * sizeof(int)));
ERR_CHK(cudaMemcpy(d_A, h_A, n * sizeof(int), cudaMemcpyHostToDevice));
ERR_CHK(cudaMemcpy(d_B, h_B, n * sizeof(int), cudaMemcpyHostToDevice));
dim3 gridSize(ceil(n / 256), 1, 1);
dim3 blockSize(256, 1, 1);
vecAddKernel <<< gridSize, blockSize >>> (d_A, d_B, d_C, n);
cudaError_t err = cudaGetLastError();
ERR_CHK(err);
ERR_CHK(cudaMemcpy(h_C, d_C, n * sizeof(int), cudaMemcpyDeviceToHost));
//verifying our solution
for (int i = 0; i < n; i++) {
if (h_A[i] + h_B[i] != h_C[i]) {
printf("Incorrect addition");
printf("%d + %d = %d for i = %d\n", h_A[i], h_B[i], h_C[i], i);
}
}
printf("SUCCESS!!!!!!!!!!!");
return 0;
} | code for sm_80
Function : _Z12vecAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define ERR_CHK(call) { gpuAssert((call), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t err, const char* file, int line, bool abort = true)
{
if (err != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(err), file, line);
if (abort) exit(err);
}
}
__global__ void vecAddKernel(int* A, int* B, int* C, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
int main() {
int* d_A, * d_B, * d_C;
int* h_A, * h_B, * h_C;
const int n = 1024;
h_A = (int*)malloc(n * sizeof(int));
h_B = (int*)malloc(n * sizeof(int));
h_C = (int*)malloc(n * sizeof(int));
for (int i = 0; i < n; i++) {
h_A[i] = rand();
h_B[i] = rand();
h_C[i] = 0;
}
ERR_CHK(cudaMalloc((void**)&d_A, n * sizeof(int)));
ERR_CHK(cudaMalloc((void**)&d_B, n * sizeof(int)));
ERR_CHK(cudaMalloc((void**)&d_C, n * sizeof(int)));
ERR_CHK(cudaMemcpy(d_A, h_A, n * sizeof(int), cudaMemcpyHostToDevice));
ERR_CHK(cudaMemcpy(d_B, h_B, n * sizeof(int), cudaMemcpyHostToDevice));
dim3 gridSize(ceil(n / 256), 1, 1);
dim3 blockSize(256, 1, 1);
vecAddKernel <<< gridSize, blockSize >>> (d_A, d_B, d_C, n);
cudaError_t err = cudaGetLastError();
ERR_CHK(err);
ERR_CHK(cudaMemcpy(h_C, d_C, n * sizeof(int), cudaMemcpyDeviceToHost));
//verifying our solution
for (int i = 0; i < n; i++) {
if (h_A[i] + h_B[i] != h_C[i]) {
printf("Incorrect addition");
printf("%d + %d = %d for i = %d\n", h_A[i], h_B[i], h_C[i], i);
}
}
printf("SUCCESS!!!!!!!!!!!");
return 0;
} | .file "tmpxft_0002fb22_00000000-6_VectorAddKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
.type _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i, .-_Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
.globl _Z12vecAddKernelPiS_S_i
.type _Z12vecAddKernelPiS_S_i, @function
_Z12vecAddKernelPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12vecAddKernelPiS_S_i, .-_Z12vecAddKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dynamic-entropy/CUDA_C_programs/master/CUDA_C_programs/VectorAddKernel.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Incorrect addition"
.LC3:
.string "%d + %d = %d for i = %d\n"
.LC4:
.string "SUCCESS!!!!!!!!!!!"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %ebx
.L20:
call rand@PLT
movl %eax, (%r12,%rbx)
call rand@PLT
movl %eax, 0(%r13,%rbx)
movl $0, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L20
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $41, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $42, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $43, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $45, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $46, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaGetLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $53, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $55, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %ebx
leaq .LC2(%rip), %r15
leaq .LC3(%rip), %r14
jmp .L23
.L28:
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
jmp .L21
.L22:
addq $1, %rbx
cmpq $1024, %rbx
je .L29
.L23:
movl 0(%r13,%rbx,4), %eax
addl (%r12,%rbx,4), %eax
cmpl 0(%rbp,%rbx,4), %eax
je .L22
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%r13,%rbx,4), %ecx
movl (%r12,%rbx,4), %edx
movl %ebx, %r9d
movl 0(%rbp,%rbx,4), %r8d
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L29:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12vecAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define ERR_CHK(call) { gpuAssert((call), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t err, const char* file, int line, bool abort = true)
{
if (err != cudaSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(err), file, line);
if (abort) exit(err);
}
}
__global__ void vecAddKernel(int* A, int* B, int* C, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
int main() {
int* d_A, * d_B, * d_C;
int* h_A, * h_B, * h_C;
const int n = 1024;
h_A = (int*)malloc(n * sizeof(int));
h_B = (int*)malloc(n * sizeof(int));
h_C = (int*)malloc(n * sizeof(int));
for (int i = 0; i < n; i++) {
h_A[i] = rand();
h_B[i] = rand();
h_C[i] = 0;
}
ERR_CHK(cudaMalloc((void**)&d_A, n * sizeof(int)));
ERR_CHK(cudaMalloc((void**)&d_B, n * sizeof(int)));
ERR_CHK(cudaMalloc((void**)&d_C, n * sizeof(int)));
ERR_CHK(cudaMemcpy(d_A, h_A, n * sizeof(int), cudaMemcpyHostToDevice));
ERR_CHK(cudaMemcpy(d_B, h_B, n * sizeof(int), cudaMemcpyHostToDevice));
dim3 gridSize(ceil(n / 256), 1, 1);
dim3 blockSize(256, 1, 1);
vecAddKernel <<< gridSize, blockSize >>> (d_A, d_B, d_C, n);
cudaError_t err = cudaGetLastError();
ERR_CHK(err);
ERR_CHK(cudaMemcpy(h_C, d_C, n * sizeof(int), cudaMemcpyDeviceToHost));
//verifying our solution
for (int i = 0; i < n; i++) {
if (h_A[i] + h_B[i] != h_C[i]) {
printf("Incorrect addition");
printf("%d + %d = %d for i = %d\n", h_A[i], h_B[i], h_C[i], i);
}
}
printf("SUCCESS!!!!!!!!!!!");
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define ERR_CHK(call) { gpuAssert((call), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t err, const char* file, int line, bool abort = true)
{
if (err != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(err), file, line);
if (abort) exit(err);
}
}
__global__ void vecAddKernel(int* A, int* B, int* C, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
int main() {
int* d_A, * d_B, * d_C;
int* h_A, * h_B, * h_C;
const int n = 1024;
h_A = (int*)malloc(n * sizeof(int));
h_B = (int*)malloc(n * sizeof(int));
h_C = (int*)malloc(n * sizeof(int));
for (int i = 0; i < n; i++) {
h_A[i] = rand();
h_B[i] = rand();
h_C[i] = 0;
}
ERR_CHK(hipMalloc((void**)&d_A, n * sizeof(int)));
ERR_CHK(hipMalloc((void**)&d_B, n * sizeof(int)));
ERR_CHK(hipMalloc((void**)&d_C, n * sizeof(int)));
ERR_CHK(hipMemcpy(d_A, h_A, n * sizeof(int), hipMemcpyHostToDevice));
ERR_CHK(hipMemcpy(d_B, h_B, n * sizeof(int), hipMemcpyHostToDevice));
dim3 gridSize(ceil(n / 256), 1, 1);
dim3 blockSize(256, 1, 1);
vecAddKernel <<< gridSize, blockSize >>> (d_A, d_B, d_C, n);
hipError_t err = hipGetLastError();
ERR_CHK(err);
ERR_CHK(hipMemcpy(h_C, d_C, n * sizeof(int), hipMemcpyDeviceToHost));
//verifying our solution
for (int i = 0; i < n; i++) {
if (h_A[i] + h_B[i] != h_C[i]) {
printf("Incorrect addition");
printf("%d + %d = %d for i = %d\n", h_A[i], h_B[i], h_C[i], i);
}
}
printf("SUCCESS!!!!!!!!!!!");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define ERR_CHK(call) { gpuAssert((call), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t err, const char* file, int line, bool abort = true)
{
if (err != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(err), file, line);
if (abort) exit(err);
}
}
__global__ void vecAddKernel(int* A, int* B, int* C, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
int main() {
int* d_A, * d_B, * d_C;
int* h_A, * h_B, * h_C;
const int n = 1024;
h_A = (int*)malloc(n * sizeof(int));
h_B = (int*)malloc(n * sizeof(int));
h_C = (int*)malloc(n * sizeof(int));
for (int i = 0; i < n; i++) {
h_A[i] = rand();
h_B[i] = rand();
h_C[i] = 0;
}
ERR_CHK(hipMalloc((void**)&d_A, n * sizeof(int)));
ERR_CHK(hipMalloc((void**)&d_B, n * sizeof(int)));
ERR_CHK(hipMalloc((void**)&d_C, n * sizeof(int)));
ERR_CHK(hipMemcpy(d_A, h_A, n * sizeof(int), hipMemcpyHostToDevice));
ERR_CHK(hipMemcpy(d_B, h_B, n * sizeof(int), hipMemcpyHostToDevice));
dim3 gridSize(ceil(n / 256), 1, 1);
dim3 blockSize(256, 1, 1);
vecAddKernel <<< gridSize, blockSize >>> (d_A, d_B, d_C, n);
hipError_t err = hipGetLastError();
ERR_CHK(err);
ERR_CHK(hipMemcpy(h_C, d_C, n * sizeof(int), hipMemcpyDeviceToHost));
//verifying our solution
for (int i = 0; i < n; i++) {
if (h_A[i] + h_B[i] != h_C[i]) {
printf("Incorrect addition");
printf("%d + %d = %d for i = %d\n", h_A[i], h_B[i], h_C[i], i);
}
}
printf("SUCCESS!!!!!!!!!!!");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPiS_S_i
.globl _Z12vecAddKernelPiS_S_i
.p2align 8
.type _Z12vecAddKernelPiS_S_i,@function
_Z12vecAddKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPiS_S_i, .Lfunc_end0-_Z12vecAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define ERR_CHK(call) { gpuAssert((call), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t err, const char* file, int line, bool abort = true)
{
if (err != hipSuccess)
{
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(err), file, line);
if (abort) exit(err);
}
}
__global__ void vecAddKernel(int* A, int* B, int* C, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n) {
C[i] = A[i] + B[i];
}
}
int main() {
int* d_A, * d_B, * d_C;
int* h_A, * h_B, * h_C;
const int n = 1024;
h_A = (int*)malloc(n * sizeof(int));
h_B = (int*)malloc(n * sizeof(int));
h_C = (int*)malloc(n * sizeof(int));
for (int i = 0; i < n; i++) {
h_A[i] = rand();
h_B[i] = rand();
h_C[i] = 0;
}
ERR_CHK(hipMalloc((void**)&d_A, n * sizeof(int)));
ERR_CHK(hipMalloc((void**)&d_B, n * sizeof(int)));
ERR_CHK(hipMalloc((void**)&d_C, n * sizeof(int)));
ERR_CHK(hipMemcpy(d_A, h_A, n * sizeof(int), hipMemcpyHostToDevice));
ERR_CHK(hipMemcpy(d_B, h_B, n * sizeof(int), hipMemcpyHostToDevice));
dim3 gridSize(ceil(n / 256), 1, 1);
dim3 blockSize(256, 1, 1);
vecAddKernel <<< gridSize, blockSize >>> (d_A, d_B, d_C, n);
hipError_t err = hipGetLastError();
ERR_CHK(err);
ERR_CHK(hipMemcpy(h_C, d_C, n * sizeof(int), hipMemcpyDeviceToHost));
//verifying our solution
for (int i = 0; i < n; i++) {
if (h_A[i] + h_B[i] != h_C[i]) {
printf("Incorrect addition");
printf("%d + %d = %d for i = %d\n", h_A[i], h_B[i], h_C[i], i);
}
}
printf("SUCCESS!!!!!!!!!!!");
return 0;
} | .text
.file "VectorAddKernel.hip"
.globl _Z27__device_stub__vecAddKernelPiS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPiS_S_i,@function
_Z27__device_stub__vecAddKernelPiS_S_i: # @_Z27__device_stub__vecAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__vecAddKernelPiS_S_i, .Lfunc_end0-_Z27__device_stub__vecAddKernelPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r12,4)
callq rand
movl %eax, (%r14,%r12,4)
movl $0, (%r15,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit35
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit37
movq 32(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit39
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit41
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 12(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit43
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_23
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit45.preheader.preheader
xorl %r12d, %r12d
jmp .LBB1_19
.p2align 4, 0x90
.LBB1_21: # %_Z9gpuAssert10hipError_tPKcib.exit45
# in Loop: Header=BB1_19 Depth=1
incq %r12
cmpq $1024, %r12 # imm = 0x400
je .LBB1_22
.LBB1_19: # %_Z9gpuAssert10hipError_tPKcib.exit45.preheader
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %eax
addl (%rbx,%r12,4), %eax
cmpl (%r15,%r12,4), %eax
je .LBB1_21
# %bb.20: # in Loop: Header=BB1_19 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl (%rbx,%r12,4), %esi
movl (%r14,%r12,4), %edx
movl (%r15,%r12,4), %ecx
movl $.L.str.2, %edi
movl %r12d, %r8d
xorl %eax, %eax
callq printf
jmp .LBB1_21
.LBB1_22:
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $41, %r8d
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $42, %r8d
jmp .LBB1_4
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $43, %r8d
jmp .LBB1_4
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $45, %r8d
jmp .LBB1_4
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $46, %r8d
jmp .LBB1_4
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $53, %r8d
jmp .LBB1_4
.LBB1_23:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $55, %r8d
.LBB1_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPiS_S_i,@object # @_Z12vecAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPiS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPiS_S_i:
.quad _Z27__device_stub__vecAddKernelPiS_S_i
.size _Z12vecAddKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/dynamic-entropy/CUDA_C_programs/master/CUDA_C_programs/VectorAddKernel.hip"
.size .L.str, 132
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Incorrect addition"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d + %d = %d for i = %d\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "SUCCESS!!!!!!!!!!!"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vecAddKernelPiS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12vecAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPiS_S_i
.globl _Z12vecAddKernelPiS_S_i
.p2align 8
.type _Z12vecAddKernelPiS_S_i,@function
_Z12vecAddKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPiS_S_i, .Lfunc_end0-_Z12vecAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002fb22_00000000-6_VectorAddKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
.type _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i, .-_Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
.globl _Z12vecAddKernelPiS_S_i
.type _Z12vecAddKernelPiS_S_i, @function
_Z12vecAddKernelPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12vecAddKernelPiS_S_i, .-_Z12vecAddKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/dynamic-entropy/CUDA_C_programs/master/CUDA_C_programs/VectorAddKernel.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Incorrect addition"
.LC3:
.string "%d + %d = %d for i = %d\n"
.LC4:
.string "SUCCESS!!!!!!!!!!!"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %ebx
.L20:
call rand@PLT
movl %eax, (%r12,%rbx)
call rand@PLT
movl %eax, 0(%r13,%rbx)
movl $0, 0(%rbp,%rbx)
addq $4, %rbx
cmpq $4096, %rbx
jne .L20
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $41, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $42, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $43, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $45, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $46, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaGetLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $53, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $55, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $0, %ebx
leaq .LC2(%rip), %r15
leaq .LC3(%rip), %r14
jmp .L23
.L28:
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPiS_S_iPiS_S_i
jmp .L21
.L22:
addq $1, %rbx
cmpq $1024, %rbx
je .L29
.L23:
movl 0(%r13,%rbx,4), %eax
addl (%r12,%rbx,4), %eax
cmpl 0(%rbp,%rbx,4), %eax
je .L22
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%r13,%rbx,4), %ecx
movl (%r12,%rbx,4), %edx
movl %ebx, %r9d
movl 0(%rbp,%rbx,4), %r8d
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L29:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12vecAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorAddKernel.hip"
.globl _Z27__device_stub__vecAddKernelPiS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPiS_S_i,@function
_Z27__device_stub__vecAddKernelPiS_S_i: # @_Z27__device_stub__vecAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__vecAddKernelPiS_S_i, .Lfunc_end0-_Z27__device_stub__vecAddKernelPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r12,4)
callq rand
movl %eax, (%r14,%r12,4)
movl $0, (%r15,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPKcib.exit35
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit37
movq 32(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit39
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_12
# %bb.13: # %_Z9gpuAssert10hipError_tPKcib.exit41
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 252(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 12(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit43
movq 16(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_23
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit45.preheader.preheader
xorl %r12d, %r12d
jmp .LBB1_19
.p2align 4, 0x90
.LBB1_21: # %_Z9gpuAssert10hipError_tPKcib.exit45
# in Loop: Header=BB1_19 Depth=1
incq %r12
cmpq $1024, %r12 # imm = 0x400
je .LBB1_22
.LBB1_19: # %_Z9gpuAssert10hipError_tPKcib.exit45.preheader
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %eax
addl (%rbx,%r12,4), %eax
cmpl (%r15,%r12,4), %eax
je .LBB1_21
# %bb.20: # in Loop: Header=BB1_19 Depth=1
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl (%rbx,%r12,4), %esi
movl (%r14,%r12,4), %edx
movl (%r15,%r12,4), %ecx
movl $.L.str.2, %edi
movl %r12d, %r8d
xorl %eax, %eax
callq printf
jmp .LBB1_21
.LBB1_22:
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $41, %r8d
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $42, %r8d
jmp .LBB1_4
.LBB1_8:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $43, %r8d
jmp .LBB1_4
.LBB1_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $45, %r8d
jmp .LBB1_4
.LBB1_12:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $46, %r8d
jmp .LBB1_4
.LBB1_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $53, %r8d
jmp .LBB1_4
.LBB1_23:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $55, %r8d
.LBB1_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPiS_S_i,@object # @_Z12vecAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPiS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPiS_S_i:
.quad _Z27__device_stub__vecAddKernelPiS_S_i
.size _Z12vecAddKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/dynamic-entropy/CUDA_C_programs/master/CUDA_C_programs/VectorAddKernel.hip"
.size .L.str, 132
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Incorrect addition"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d + %d = %d for i = %d\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "SUCCESS!!!!!!!!!!!"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.4, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vecAddKernelPiS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
const int ARRAY_SIZE =500000; // size greater than 32M could not be achieved
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MAX_NO_THREADS = 512;
__global__ void vector_reduce(float *d_in1, float *d_in2, float *d_out){
int index = threadIdx.x + blockIdx.x*blockDim.x ;
*(d_out+index) = *(d_in1+index) + *(d_in2+index);
}
int check( float *h_in1, float *h_in2, float *h_out){
int i,flag = 1;
for(i=0;i<ARRAY_SIZE;i++){
if(h_in1[i]+h_in2[i]!=h_out[i]){
flag=0;
break;
}
}
return flag;
}
int main(){
//allocating size for host arrays
float h_in1[ARRAY_SIZE], h_in2[ARRAY_SIZE], h_out[ARRAY_SIZE];
//generating the input arrays
int i;
for(i=0;i<ARRAY_SIZE;i++){
h_in1[i]=(float)i;
h_in2[i]=(float)(ARRAY_SIZE-i);
}
//declaring device memory pointers
float *d_in1, *d_in2, *d_out;
//allocating device memory
cudaMalloc(&d_in1, ARRAY_BYTES);
cudaMalloc(&d_in2, ARRAY_BYTES);
cudaMalloc(&d_out, ARRAY_BYTES);
//transferring memory from host to device
cudaMemcpy(d_in1, h_in1, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_in2, h_in2, ARRAY_BYTES, cudaMemcpyHostToDevice);
//starting kernel
vector_reduce<<<(int)(ARRAY_SIZE/MAX_NO_THREADS)+1, MAX_NO_THREADS>>>(d_in1, d_in2, d_out);
//transferring memory from device to host
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
//checking correctness
if(check(h_in1, h_in2, h_out))
printf("the result is correct\n");
else
printf("the result is incorrect\n");
//freeing memory
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z13vector_reducePfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
const int ARRAY_SIZE =500000; // size greater than 32M could not be achieved
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MAX_NO_THREADS = 512;
__global__ void vector_reduce(float *d_in1, float *d_in2, float *d_out){
int index = threadIdx.x + blockIdx.x*blockDim.x ;
*(d_out+index) = *(d_in1+index) + *(d_in2+index);
}
int check( float *h_in1, float *h_in2, float *h_out){
int i,flag = 1;
for(i=0;i<ARRAY_SIZE;i++){
if(h_in1[i]+h_in2[i]!=h_out[i]){
flag=0;
break;
}
}
return flag;
}
int main(){
//allocating size for host arrays
float h_in1[ARRAY_SIZE], h_in2[ARRAY_SIZE], h_out[ARRAY_SIZE];
//generating the input arrays
int i;
for(i=0;i<ARRAY_SIZE;i++){
h_in1[i]=(float)i;
h_in2[i]=(float)(ARRAY_SIZE-i);
}
//declaring device memory pointers
float *d_in1, *d_in2, *d_out;
//allocating device memory
cudaMalloc(&d_in1, ARRAY_BYTES);
cudaMalloc(&d_in2, ARRAY_BYTES);
cudaMalloc(&d_out, ARRAY_BYTES);
//transferring memory from host to device
cudaMemcpy(d_in1, h_in1, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_in2, h_in2, ARRAY_BYTES, cudaMemcpyHostToDevice);
//starting kernel
vector_reduce<<<(int)(ARRAY_SIZE/MAX_NO_THREADS)+1, MAX_NO_THREADS>>>(d_in1, d_in2, d_out);
//transferring memory from device to host
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
//checking correctness
if(check(h_in1, h_in2, h_out))
printf("the result is correct\n");
else
printf("the result is incorrect\n");
//freeing memory
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
return 0;
} | .file "tmpxft_0000c67d_00000000-6_ArrayAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5checkPfS_S_
.type _Z5checkPfS_S_, @function
_Z5checkPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L6:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
ucomiss (%rdx,%rax), %xmm0
jp .L7
jne .L7
addq $4, %rax
cmpq $2000000, %rax
jne .L6
movl $1, %eax
ret
.L7:
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z5checkPfS_S_, .-_Z5checkPfS_S_
.globl _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_
.type _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_, @function
_Z37__device_stub__Z13vector_reducePfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13vector_reducePfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_, .-_Z37__device_stub__Z13vector_reducePfS_S_PfS_S_
.globl _Z13vector_reducePfS_S_
.type _Z13vector_reducePfS_S_, @function
_Z13vector_reducePfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13vector_reducePfS_S_, .-_Z13vector_reducePfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "the result is correct\n"
.LC1:
.string "the result is incorrect\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -5996544(%rsp), %r11
.cfi_def_cfa 11, 5996560
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3520, %rsp
.cfi_def_cfa_offset 6000080
movq %fs:40, %rax
movq %rax, 6000056(%rsp)
xorl %eax, %eax
movl $500000, %ecx
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 2000048(%rsp,%rax,4)
addq $1, %rax
cmpq $500000, %rax
jne .L19
movq %rsp, %rdi
movl $2000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $2000000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 2000048(%rsp), %rsi
movl $1, %ecx
movl $2000000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $977, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L20:
leaq 4000048(%rsp), %rbx
movl $2, %ecx
movl $2000000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 2000048(%rsp), %rsi
leaq 48(%rsp), %rdi
movq %rbx, %rdx
call _Z5checkPfS_S_
testl %eax, %eax
je .L21
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 6000056(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $6000064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_
jmp .L20
.L21:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13vector_reducePfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13vector_reducePfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
const int ARRAY_SIZE =500000; // size greater than 32M could not be achieved
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MAX_NO_THREADS = 512;
__global__ void vector_reduce(float *d_in1, float *d_in2, float *d_out){
int index = threadIdx.x + blockIdx.x*blockDim.x ;
*(d_out+index) = *(d_in1+index) + *(d_in2+index);
}
int check( float *h_in1, float *h_in2, float *h_out){
int i,flag = 1;
for(i=0;i<ARRAY_SIZE;i++){
if(h_in1[i]+h_in2[i]!=h_out[i]){
flag=0;
break;
}
}
return flag;
}
int main(){
//allocating size for host arrays
float h_in1[ARRAY_SIZE], h_in2[ARRAY_SIZE], h_out[ARRAY_SIZE];
//generating the input arrays
int i;
for(i=0;i<ARRAY_SIZE;i++){
h_in1[i]=(float)i;
h_in2[i]=(float)(ARRAY_SIZE-i);
}
//declaring device memory pointers
float *d_in1, *d_in2, *d_out;
//allocating device memory
cudaMalloc(&d_in1, ARRAY_BYTES);
cudaMalloc(&d_in2, ARRAY_BYTES);
cudaMalloc(&d_out, ARRAY_BYTES);
//transferring memory from host to device
cudaMemcpy(d_in1, h_in1, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_in2, h_in2, ARRAY_BYTES, cudaMemcpyHostToDevice);
//starting kernel
vector_reduce<<<(int)(ARRAY_SIZE/MAX_NO_THREADS)+1, MAX_NO_THREADS>>>(d_in1, d_in2, d_out);
//transferring memory from device to host
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
//checking correctness
if(check(h_in1, h_in2, h_out))
printf("the result is correct\n");
else
printf("the result is incorrect\n");
//freeing memory
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
const int ARRAY_SIZE =500000; // size greater than 32M could not be achieved
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MAX_NO_THREADS = 512;
__global__ void vector_reduce(float *d_in1, float *d_in2, float *d_out){
int index = threadIdx.x + blockIdx.x*blockDim.x ;
*(d_out+index) = *(d_in1+index) + *(d_in2+index);
}
int check( float *h_in1, float *h_in2, float *h_out){
int i,flag = 1;
for(i=0;i<ARRAY_SIZE;i++){
if(h_in1[i]+h_in2[i]!=h_out[i]){
flag=0;
break;
}
}
return flag;
}
int main(){
//allocating size for host arrays
float h_in1[ARRAY_SIZE], h_in2[ARRAY_SIZE], h_out[ARRAY_SIZE];
//generating the input arrays
int i;
for(i=0;i<ARRAY_SIZE;i++){
h_in1[i]=(float)i;
h_in2[i]=(float)(ARRAY_SIZE-i);
}
//declaring device memory pointers
float *d_in1, *d_in2, *d_out;
//allocating device memory
hipMalloc(&d_in1, ARRAY_BYTES);
hipMalloc(&d_in2, ARRAY_BYTES);
hipMalloc(&d_out, ARRAY_BYTES);
//transferring memory from host to device
hipMemcpy(d_in1, h_in1, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_in2, h_in2, ARRAY_BYTES, hipMemcpyHostToDevice);
//starting kernel
vector_reduce<<<(int)(ARRAY_SIZE/MAX_NO_THREADS)+1, MAX_NO_THREADS>>>(d_in1, d_in2, d_out);
//transferring memory from device to host
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
//checking correctness
if(check(h_in1, h_in2, h_out))
printf("the result is correct\n");
else
printf("the result is incorrect\n");
//freeing memory
hipFree(d_in1);
hipFree(d_in2);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
const int ARRAY_SIZE =500000; // size greater than 32M could not be achieved
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MAX_NO_THREADS = 512;
__global__ void vector_reduce(float *d_in1, float *d_in2, float *d_out){
int index = threadIdx.x + blockIdx.x*blockDim.x ;
*(d_out+index) = *(d_in1+index) + *(d_in2+index);
}
int check( float *h_in1, float *h_in2, float *h_out){
int i,flag = 1;
for(i=0;i<ARRAY_SIZE;i++){
if(h_in1[i]+h_in2[i]!=h_out[i]){
flag=0;
break;
}
}
return flag;
}
int main(){
//allocating size for host arrays
float h_in1[ARRAY_SIZE], h_in2[ARRAY_SIZE], h_out[ARRAY_SIZE];
//generating the input arrays
int i;
for(i=0;i<ARRAY_SIZE;i++){
h_in1[i]=(float)i;
h_in2[i]=(float)(ARRAY_SIZE-i);
}
//declaring device memory pointers
float *d_in1, *d_in2, *d_out;
//allocating device memory
hipMalloc(&d_in1, ARRAY_BYTES);
hipMalloc(&d_in2, ARRAY_BYTES);
hipMalloc(&d_out, ARRAY_BYTES);
//transferring memory from host to device
hipMemcpy(d_in1, h_in1, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_in2, h_in2, ARRAY_BYTES, hipMemcpyHostToDevice);
//starting kernel
vector_reduce<<<(int)(ARRAY_SIZE/MAX_NO_THREADS)+1, MAX_NO_THREADS>>>(d_in1, d_in2, d_out);
//transferring memory from device to host
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
//checking correctness
if(check(h_in1, h_in2, h_out))
printf("the result is correct\n");
else
printf("the result is incorrect\n");
//freeing memory
hipFree(d_in1);
hipFree(d_in2);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13vector_reducePfS_S_
.globl _Z13vector_reducePfS_S_
.p2align 8
.type _Z13vector_reducePfS_S_,@function
_Z13vector_reducePfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13vector_reducePfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13vector_reducePfS_S_, .Lfunc_end0-_Z13vector_reducePfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13vector_reducePfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13vector_reducePfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
const int ARRAY_SIZE =500000; // size greater than 32M could not be achieved
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MAX_NO_THREADS = 512;
__global__ void vector_reduce(float *d_in1, float *d_in2, float *d_out){
int index = threadIdx.x + blockIdx.x*blockDim.x ;
*(d_out+index) = *(d_in1+index) + *(d_in2+index);
}
int check( float *h_in1, float *h_in2, float *h_out){
int i,flag = 1;
for(i=0;i<ARRAY_SIZE;i++){
if(h_in1[i]+h_in2[i]!=h_out[i]){
flag=0;
break;
}
}
return flag;
}
int main(){
//allocating size for host arrays
float h_in1[ARRAY_SIZE], h_in2[ARRAY_SIZE], h_out[ARRAY_SIZE];
//generating the input arrays
int i;
for(i=0;i<ARRAY_SIZE;i++){
h_in1[i]=(float)i;
h_in2[i]=(float)(ARRAY_SIZE-i);
}
//declaring device memory pointers
float *d_in1, *d_in2, *d_out;
//allocating device memory
hipMalloc(&d_in1, ARRAY_BYTES);
hipMalloc(&d_in2, ARRAY_BYTES);
hipMalloc(&d_out, ARRAY_BYTES);
//transferring memory from host to device
hipMemcpy(d_in1, h_in1, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_in2, h_in2, ARRAY_BYTES, hipMemcpyHostToDevice);
//starting kernel
vector_reduce<<<(int)(ARRAY_SIZE/MAX_NO_THREADS)+1, MAX_NO_THREADS>>>(d_in1, d_in2, d_out);
//transferring memory from device to host
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
//checking correctness
if(check(h_in1, h_in2, h_out))
printf("the result is correct\n");
else
printf("the result is incorrect\n");
//freeing memory
hipFree(d_in1);
hipFree(d_in2);
hipFree(d_out);
return 0;
} | .text
.file "ArrayAddition.hip"
.globl _Z28__device_stub__vector_reducePfS_S_ # -- Begin function _Z28__device_stub__vector_reducePfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__vector_reducePfS_S_,@function
_Z28__device_stub__vector_reducePfS_S_: # @_Z28__device_stub__vector_reducePfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13vector_reducePfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__vector_reducePfS_S_, .Lfunc_end0-_Z28__device_stub__vector_reducePfS_S_
.cfi_endproc
# -- End function
.globl _Z5checkPfS_S_ # -- Begin function _Z5checkPfS_S_
.p2align 4, 0x90
.type _Z5checkPfS_S_,@function
_Z5checkPfS_S_: # @_Z5checkPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
ucomiss (%rdx,%rcx,4), %xmm0
jne .LBB1_4
jp .LBB1_4
# %bb.2: # in Loop: Header=BB1_1 Depth=1
incq %rcx
cmpq $500000, %rcx # imm = 0x7A120
jne .LBB1_1
# %bb.3:
movl $1, %eax
.LBB1_4:
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end1:
.size _Z5checkPfS_S_, .Lfunc_end1-_Z5checkPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $6000104, %rsp # imm = 0x5B8DE8
.cfi_def_cfa_offset 6000112
movl $500000, %eax # imm = 0x7A120
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm0, 4000096(%rsp,%rcx,4)
movss %xmm1, 2000096(%rsp,%rcx,4)
incq %rcx
decq %rax
jne .LBB2_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $2000000, %esi # imm = 0x1E8480
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2000000, %esi # imm = 0x1E8480
callq hipMalloc
movq %rsp, %rdi
movl $2000000, %esi # imm = 0x1E8480
callq hipMalloc
movq 16(%rsp), %rdi
leaq 4000096(%rsp), %rsi
movl $2000000, %edx # imm = 0x1E8480
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 2000096(%rsp), %rsi
movl $2000000, %edx # imm = 0x1E8480
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 465(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13vector_reducePfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $2000000, %edx # imm = 0x1E8480
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss 4000096(%rsp,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 2000096(%rsp,%rax,4), %xmm0
movss 96(%rsp,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB2_7
jp .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
leaq 1(%rax), %rcx
cmpq $499999, %rax # imm = 0x7A11F
movq %rcx, %rax
jne .LBB2_5
.LBB2_7: # %_Z5checkPfS_S_.exit
ucomiss %xmm1, %xmm0
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmovneq %rax, %rdi
cmovpq %rax, %rdi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $6000104, %rsp # imm = 0x5B8DE8
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13vector_reducePfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13vector_reducePfS_S_,@object # @_Z13vector_reducePfS_S_
.section .rodata,"a",@progbits
.globl _Z13vector_reducePfS_S_
.p2align 3, 0x0
_Z13vector_reducePfS_S_:
.quad _Z28__device_stub__vector_reducePfS_S_
.size _Z13vector_reducePfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13vector_reducePfS_S_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "the result is incorrect"
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "the result is correct"
.size .Lstr.1, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__vector_reducePfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13vector_reducePfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13vector_reducePfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13vector_reducePfS_S_
.globl _Z13vector_reducePfS_S_
.p2align 8
.type _Z13vector_reducePfS_S_,@function
_Z13vector_reducePfS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13vector_reducePfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13vector_reducePfS_S_, .Lfunc_end0-_Z13vector_reducePfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13vector_reducePfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13vector_reducePfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000c67d_00000000-6_ArrayAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5checkPfS_S_
.type _Z5checkPfS_S_, @function
_Z5checkPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
.L6:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
ucomiss (%rdx,%rax), %xmm0
jp .L7
jne .L7
addq $4, %rax
cmpq $2000000, %rax
jne .L6
movl $1, %eax
ret
.L7:
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z5checkPfS_S_, .-_Z5checkPfS_S_
.globl _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_
.type _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_, @function
_Z37__device_stub__Z13vector_reducePfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13vector_reducePfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_, .-_Z37__device_stub__Z13vector_reducePfS_S_PfS_S_
.globl _Z13vector_reducePfS_S_
.type _Z13vector_reducePfS_S_, @function
_Z13vector_reducePfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13vector_reducePfS_S_, .-_Z13vector_reducePfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "the result is correct\n"
.LC1:
.string "the result is incorrect\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -5996544(%rsp), %r11
.cfi_def_cfa 11, 5996560
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3520, %rsp
.cfi_def_cfa_offset 6000080
movq %fs:40, %rax
movq %rax, 6000056(%rsp)
xorl %eax, %eax
movl $500000, %ecx
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
movl %ecx, %edx
subl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 2000048(%rsp,%rax,4)
addq $1, %rax
cmpq $500000, %rax
jne .L19
movq %rsp, %rdi
movl $2000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $2000000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 2000048(%rsp), %rsi
movl $1, %ecx
movl $2000000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $977, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L20:
leaq 4000048(%rsp), %rbx
movl $2, %ecx
movl $2000000, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 2000048(%rsp), %rsi
leaq 48(%rsp), %rdi
movq %rbx, %rdx
call _Z5checkPfS_S_
testl %eax, %eax
je .L21
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L22:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 6000056(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $6000064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z37__device_stub__Z13vector_reducePfS_S_PfS_S_
jmp .L20
.L21:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13vector_reducePfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13vector_reducePfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ArrayAddition.hip"
.globl _Z28__device_stub__vector_reducePfS_S_ # -- Begin function _Z28__device_stub__vector_reducePfS_S_
.p2align 4, 0x90
.type _Z28__device_stub__vector_reducePfS_S_,@function
_Z28__device_stub__vector_reducePfS_S_: # @_Z28__device_stub__vector_reducePfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13vector_reducePfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__vector_reducePfS_S_, .Lfunc_end0-_Z28__device_stub__vector_reducePfS_S_
.cfi_endproc
# -- End function
.globl _Z5checkPfS_S_ # -- Begin function _Z5checkPfS_S_
.p2align 4, 0x90
.type _Z5checkPfS_S_,@function
_Z5checkPfS_S_: # @_Z5checkPfS_S_
.cfi_startproc
# %bb.0:
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
ucomiss (%rdx,%rcx,4), %xmm0
jne .LBB1_4
jp .LBB1_4
# %bb.2: # in Loop: Header=BB1_1 Depth=1
incq %rcx
cmpq $500000, %rcx # imm = 0x7A120
jne .LBB1_1
# %bb.3:
movl $1, %eax
.LBB1_4:
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end1:
.size _Z5checkPfS_S_, .Lfunc_end1-_Z5checkPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $6000104, %rsp # imm = 0x5B8DE8
.cfi_def_cfa_offset 6000112
movl $500000, %eax # imm = 0x7A120
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm0, 4000096(%rsp,%rcx,4)
movss %xmm1, 2000096(%rsp,%rcx,4)
incq %rcx
decq %rax
jne .LBB2_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $2000000, %esi # imm = 0x1E8480
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2000000, %esi # imm = 0x1E8480
callq hipMalloc
movq %rsp, %rdi
movl $2000000, %esi # imm = 0x1E8480
callq hipMalloc
movq 16(%rsp), %rdi
leaq 4000096(%rsp), %rsi
movl $2000000, %edx # imm = 0x1E8480
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 2000096(%rsp), %rsi
movl $2000000, %edx # imm = 0x1E8480
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 465(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13vector_reducePfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $2000000, %edx # imm = 0x1E8480
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss 4000096(%rsp,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss 2000096(%rsp,%rax,4), %xmm0
movss 96(%rsp,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB2_7
jp .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
leaq 1(%rax), %rcx
cmpq $499999, %rax # imm = 0x7A11F
movq %rcx, %rax
jne .LBB2_5
.LBB2_7: # %_Z5checkPfS_S_.exit
ucomiss %xmm1, %xmm0
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmovneq %rax, %rdi
cmovpq %rax, %rdi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $6000104, %rsp # imm = 0x5B8DE8
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13vector_reducePfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13vector_reducePfS_S_,@object # @_Z13vector_reducePfS_S_
.section .rodata,"a",@progbits
.globl _Z13vector_reducePfS_S_
.p2align 3, 0x0
_Z13vector_reducePfS_S_:
.quad _Z28__device_stub__vector_reducePfS_S_
.size _Z13vector_reducePfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13vector_reducePfS_S_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "the result is incorrect"
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "the result is correct"
.size .Lstr.1, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__vector_reducePfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13vector_reducePfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifdef _WIN32
# define NOMINMAX
#endif
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// includes, project
// includes, kernels
#include <cuda.h>
#include <cuda_runtime.h>
#define MAX_TILE_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
double* read_array(const char* filename, int len) {
double *x = (double*) malloc(len * sizeof(double));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%lf", &x[i]);
}
fclose(fp);
return x;
}
__global__ void computeOnDevice(double* dA,double* dB, double* dC, int nRows, int tileSize, float* incTime)
{
__shared__ float ds_M[MAX_TILE_SIZE];
__shared__ float ds_N[MAX_TILE_SIZE];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * tileSize + ty,
Col = bx * tileSize + tx;
double Pvalue = 0;
for (int m = 0; m < (nRows-1)/tileSize+1; ++m) {
if (Row < nRows && m*tileSize+tx < nRows)
ds_M[ty * tileSize + tx] = dA[Row*nRows + m*tileSize+tx];
else
ds_M[ty * tileSize + tx] = 0;
if (Col < nRows && m*tileSize+ty < nRows)
ds_N[ty * tileSize + tx] = dB[(m*tileSize+ty)*nRows+Col];
else
ds_N[ty * tileSize + tx] = 0;
__syncthreads();
for (int k = 0; k < tileSize; ++k)
Pvalue += ds_M[ty * tileSize + k] * ds_N[k * tileSize + tx];
__syncthreads();
}
if (Row < nRows && Col < nRows)
dC[Row*nRows+Col] = Pvalue;
return;//Placeholder
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
if(argc!=2)
{
printf("Usage: ./problem2 N\n");
return 0;
}
int nRows = 1024;
int num_elements = nRows*nRows;
int tileSize = atoi(argv[1]); //change this for scaling analysis
float incTime=0; // Time for GPU
double* hA = read_array("inputA.inp",num_elements);
double* hB = read_array("inputB.inp",num_elements);
double* hC = (double*) malloc(num_elements * sizeof(double));
dim3 dimGrid((nRows - 1) / tileSize + 1, (nRows - 1) / tileSize + 1, 1);
dim3 dimBlock(tileSize, tileSize, 1);
double * dA, *dB, *dC;
cudaError error = cudaMalloc((void**)&dA, sizeof(double)*num_elements);
error = cudaMalloc((void**)&dB, sizeof(double)*num_elements);
error = cudaMalloc((void**)&dC, sizeof(double)*num_elements);
cudaMemcpy(dA, hA, sizeof(double)*num_elements, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, sizeof(double)*num_elements, cudaMemcpyHostToDevice);
cudaEvent_t startEvent_inc, stopEvent_inc;
cudaEventCreate(&startEvent_inc);
cudaEventCreate(&stopEvent_inc);
cudaEventRecord(startEvent_inc,0); // starting timing for inclusive
// **===-------- Modify the body of this function -----------===**
computeOnDevice<<<dimGrid, dimBlock>>>(dA, dB, dC, nRows, tileSize, &incTime);
// **===-----------------------------------------------------------===**
cudaThreadSynchronize();
cudaMemcpy(hC, dC, sizeof(double)*num_elements, cudaMemcpyDeviceToHost);
cudaEventRecord(stopEvent_inc,0); //ending timing for inclusive
cudaEventSynchronize(stopEvent_inc);
cudaEventElapsedTime(&incTime, startEvent_inc, stopEvent_inc);
printf("%lf\n%f\n%d\n",hC[num_elements - 1],incTime,tileSize);
// cleanup memory
free(hA);
free(hB);
free(hC);
return 0;
} | code for sm_80
Function : _Z15computeOnDevicePdS_S_iiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R6, c[0x0][0x17c] ; /* 0x00005f0000067a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*0040*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0050*/ I2F.RP R4, R6 ; /* 0x0000000600047306 */
/* 0x000e240000209400 */
/*0060*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fcc0007ffe0ff */
/*0070*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0080*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe40007ffe0ff */
/*0090*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fc80000000000 */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000062000021f000 */
/*00b0*/ LOP3.LUT R0, R0, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0000007a12 */
/* 0x000fc800078e3cff */
/*00c0*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f46270 */
/*00d0*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000ea20000002200 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R5, R5, R6, RZ ; /* 0x0000000605057224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe400078e0002 */
/*0120*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea80000002600 */
/*0130*/ IMAD.HI.U32 R2, R3, R4, RZ ; /* 0x0000000403027227 */
/* 0x000fca00078e00ff */
/*0140*/ IADD3 R3, -R2, RZ, RZ ; /* 0x000000ff02037210 */
/* 0x000fca0007ffe1ff */
/*0150*/ IMAD R3, R6, R3, R4 ; /* 0x0000000306037224 */
/* 0x000fca00078e0204 */
/*0160*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe20003f24070 */
/*0170*/ IMAD R5, R5, c[0x0][0x17c], R0 ; /* 0x00005f0005057a24 */
/* 0x004fd800078e0200 */
/*0180*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a06 */
/*0190*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f25270 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fe40003f06070 */
/*01c0*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*01d0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e2e0000002100 */
/*01e0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ @!P2 IADD3 R2, -R2, RZ, RZ ; /* 0x000000ff0202a210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P1 LOP3.LUT R2, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff029a12 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f06270 */
/*0220*/ IMAD R6, R6, c[0x0][0x17c], R3 ; /* 0x00005f0006067a24 */
/* 0x001fd800078e0203 */
/*0230*/ @!P0 BRA 0x1310 ; /* 0x000010d000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff087624 */
/* 0x000fe200078e00ff */
/*0250*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0260*/ IMAD R7, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000077a24 */
/* 0x000fe200078e0203 */
/*0270*/ LEA R9, R3, 0x1000, 0x2 ; /* 0x0000100003097811 */
/* 0x000fe200078e10ff */
/*0280*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0290*/ IADD3 R4, R8.reuse, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x040fe40007ffe0ff */
/*02a0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*02b0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*02c0*/ IADD3 R11, -R8, c[0x0][0x17c], RZ ; /* 0x00005f00080b7a10 */
/* 0x000fc40007ffe1ff */
/*02d0*/ IMAD R13, R10.reuse, c[0x0][0x17c], R0 ; /* 0x00005f000a0d7a24 */
/* 0x040fe400078e0200 */
/*02e0*/ IMAD R14, R10, c[0x0][0x17c], R3 ; /* 0x00005f000a0e7a24 */
/* 0x000fc600078e0203 */
/*02f0*/ ISETP.GE.AND P2, PT, R13, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x000fe40003f46270 */
/*0300*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x178], PT ; /* 0x00005e000e007a0c */
/* 0x000fe40003f06270 */
/*0310*/ ISETP.GE.OR P2, PT, R6, c[0x0][0x178], P2 ; /* 0x00005e0006007a0c */
/* 0x000fe40001746670 */
/*0320*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fd60000706670 */
/*0330*/ @!P2 MOV R17, 0x8 ; /* 0x000000080011a802 */
/* 0x000fe20000000f00 */
/*0340*/ @!P2 IMAD R12, R13, c[0x0][0x178], R6 ; /* 0x00005e000d0caa24 */
/* 0x000fe400078e0206 */
/*0350*/ @!P0 IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f8424 */
/* 0x000fe400078e00ff */
/*0360*/ @!P0 IMAD R14, R5, c[0x0][0x178], R14 ; /* 0x00005e00050e8a24 */
/* 0x000fe400078e020e */
/*0370*/ @!P2 IMAD.WIDE R12, R12, R17, c[0x0][0x168] ; /* 0x00005a000c0ca625 */
/* 0x000fc800078e0211 */
/*0380*/ @!P0 IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e8625 */
/* 0x000fe400078e020f */
/*0390*/ @!P2 LDG.E.64 R12, [R12.64] ; /* 0x000000040c0ca981 */
/* 0x000ea8000c1e1b00 */
/*03a0*/ @!P0 LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e8981 */
/* 0x000ee2000c1e1b00 */
/*03b0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*03c0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*03d0*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff147624 */
/* 0x000fca00078e00ff */
/*03e0*/ @!P2 F2F.F32.F64 R4, R12 ; /* 0x0000000c0004a310 */
/* 0x004e300000301000 */
/*03f0*/ @!P0 F2F.F32.F64 R16, R14 ; /* 0x0000000e00108310 */
/* 0x00ae620000301000 */
/*0400*/ ISETP.GE.AND P0, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe40003f06270 */
/*0410*/ ISETP.GE.AND P2, PT, R10.reuse, R2, PT ; /* 0x000000020a00720c */
/* 0x040fe20003f46270 */
/*0420*/ STS [R7.X4+0x1000], R4 ; /* 0x0010000407007388 */
/* 0x0011e20000004800 */
/*0430*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fc60007ffe0ff */
/*0440*/ STS [R7.X4], R16 ; /* 0x0000001007007388 */
/* 0x0021e80000004800 */
/*0450*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0460*/ @!P0 BRA 0x12e0 ; /* 0x00000e7000008947 */
/* 0x000fea0003800000 */
/*0470*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x001fe20000000f00 */
/*0480*/ @!P1 BRA 0x1140 ; /* 0x00000cb000009947 */
/* 0x000fea0003800000 */
/*0490*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f04270 */
/*04a0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*04b0*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x000fe20000000f00 */
/*04c0*/ IMAD.MOV.U32 R27, RZ, RZ, R9 ; /* 0x000000ffff1b7224 */
/* 0x000fd400078e0009 */
/*04d0*/ @!P0 BRA 0xf70 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*04e0*/ ISETP.GT.AND P3, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f64270 */
/*04f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0500*/ @!P3 BRA 0xbd0 ; /* 0x000006c00000b947 */
/* 0x000fea0003800000 */
/*0510*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0520*/ IMAD R24, R0, c[0x0][0x17c], R21 ; /* 0x00005f0000187a24 */
/* 0x000fe200078e0215 */
/*0530*/ LDS R14, [R27] ; /* 0x000000001b0e7984 */
/* 0x000fe20000000800 */
/*0540*/ LEA R17, R20, R27, 0x2 ; /* 0x0000001b14117211 */
/* 0x000fe400078e10ff */
/*0550*/ IADD3 R26, R21, 0x4, RZ ; /* 0x00000004151a7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ LDS R15, [R24.X4] ; /* 0x00000000180f7984 */
/* 0x001e220000004800 */
/*0570*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0580*/ IMAD R29, R20, 0x4, R17 ; /* 0x00000004141d7824 */
/* 0x000fe400078e0211 */
/*0590*/ LDS R16, [R17] ; /* 0x0000000011107984 */
/* 0x000fe20000000800 */
/*05a0*/ IMAD R26, R0, c[0x0][0x17c], R26 ; /* 0x00005f00001a7a24 */
/* 0x000fe200078e021a */
/*05b0*/ ISETP.GT.AND P3, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fc40003f64270 */
/*05c0*/ LDS R23, [R24.X4+0x4] ; /* 0x0000040018177984 */
/* 0x002e620000004800 */
/*05d0*/ LEA R25, R20, R29, 0x2 ; /* 0x0000001d14197211 */
/* 0x000fc600078e10ff */
/*05e0*/ LDS R12, [R24.X4+0x8] ; /* 0x00000800180c7984 */
/* 0x000fe80000004800 */
/*05f0*/ LDS R13, [R29] ; /* 0x000000001d0d7984 */
/* 0x000ea80000000800 */
/*0600*/ LDS R22, [R24.X4+0xc] ; /* 0x00000c0018167984 */
/* 0x000fe80000004800 */
/*0610*/ LDS R24, [R26.X4+0x4] ; /* 0x000004001a187984 */
/* 0x000fe20000004800 */
/*0620*/ FMUL R14, R14, R15 ; /* 0x0000000f0e0e7220 */
/* 0x001fcc0000400000 */
/*0630*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x000e220000201800 */
/*0640*/ FMUL R27, R16, R23 ; /* 0x00000017101b7220 */
/* 0x002fe40000400000 */
/*0650*/ LDS R23, [R25] ; /* 0x0000000019177984 */
/* 0x0002ea0000000800 */
/*0660*/ F2F.F64.F32 R16, R27 ; /* 0x0000001b00107310 */
/* 0x000f220000201800 */
/*0670*/ FMUL R12, R13, R12 ; /* 0x0000000c0d0c7220 */
/* 0x004fe40000400000 */
/*0680*/ IMAD R25, R20, 0x4, R25 ; /* 0x0000000414197824 */
/* 0x002fe200078e0219 */
/*0690*/ DADD R18, R14, R18 ; /* 0x000000000e127229 */
/* 0x0011080000000012 */
/*06a0*/ LEA R28, R20.reuse, R25, 0x2 ; /* 0x00000019141c7211 */
/* 0x040fe200078e10ff */
/*06b0*/ LDS R15, [R26.X4] ; /* 0x000000001a0f7984 */
/* 0x001fe20000004800 */
/*06c0*/ F2F.F64.F32 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x000e260000201800 */
/*06d0*/ LDS R14, [R25] ; /* 0x00000000190e7984 */
/* 0x000e620000000800 */
/*06e0*/ IMAD R29, R20.reuse, 0x4, R28 ; /* 0x00000004141d7824 */
/* 0x040fe200078e021c */
/*06f0*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x0104240000000010 */
/*0700*/ LDS R27, [R28] ; /* 0x000000001c1b7984 */
/* 0x000f240000000800 */
/*0710*/ LEA R19, R20, R29, 0x2 ; /* 0x0000001d14137211 */
/* 0x004fc400078e10ff */
/*0720*/ LDS R25, [R26.X4+0x8] ; /* 0x000008001a197984 */
/* 0x000fe80000004800 */
/*0730*/ LDS R18, [R26.X4+0xc] ; /* 0x00000c001a127984 */
/* 0x000fe20000004800 */
/*0740*/ DADD R12, R16, R12 ; /* 0x00000000100c7229 */
/* 0x001086000000000c */
/*0750*/ LDS R16, [R29] ; /* 0x000000001d107984 */
/* 0x0011680000000800 */
/*0760*/ LDS R17, [R19] ; /* 0x0000000013117984 */
/* 0x0003620000000800 */
/*0770*/ FMUL R22, R23, R22 ; /* 0x0000001617167220 */
/* 0x008fe20000400000 */
/*0780*/ IADD3 R29, R21, 0x8, RZ ; /* 0x00000008151d7810 */
/* 0x001fca0007ffe0ff */
/*0790*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x000ea20000201800 */
/*07a0*/ FMUL R28, R14, R15 ; /* 0x0000000f0e1c7220 */
/* 0x002fce0000400000 */
/*07b0*/ F2F.F64.F32 R14, R28 ; /* 0x0000001c000e7310 */
/* 0x000a220000201800 */
/*07c0*/ FMUL R24, R27, R24 ; /* 0x000000181b187220 */
/* 0x010fe20000400000 */
/*07d0*/ DADD R22, R12, R22 ; /* 0x000000000c167229 */
/* 0x0042220000000016 */
/*07e0*/ IMAD R27, R20, 0x4, R19 ; /* 0x00000004141b7824 */
/* 0x000fca00078e0213 */
/*07f0*/ F2F.F64.F32 R12, R24 ; /* 0x00000018000c7310 */
/* 0x0022a20000201800 */
/*0800*/ LDS R26, [R27] ; /* 0x000000001b1a7984 */
/* 0x000fe20000000800 */
/*0810*/ LEA R19, R20, R27, 0x2 ; /* 0x0000001b14137211 */
/* 0x000fe200078e10ff */
/*0820*/ FMUL R28, R16, R25 ; /* 0x00000019101c7220 */
/* 0x020fe40000400000 */
/*0830*/ IMAD R24, R0, c[0x0][0x17c], R29 ; /* 0x00005f0000187a24 */
/* 0x002fe200078e021d */
/*0840*/ DADD R14, R22, R14 ; /* 0x00000000160e7229 */
/* 0x0010a2000000000e */
/*0850*/ FMUL R29, R17, R18 ; /* 0x00000012111d7220 */
/* 0x000fe20000400000 */
/*0860*/ LDS R23, [R19] ; /* 0x0000000013177984 */
/* 0x0011e20000000800 */
/*0870*/ F2F.F64.F32 R16, R28 ; /* 0x0000001c00107310 */
/* 0x000e660000201800 */
/*0880*/ LDS R27, [R24.X4] ; /* 0x00000000181b7984 */
/* 0x000ee20000004800 */
/*0890*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x004446000000000c */
/*08a0*/ LDS R22, [R24.X4+0x4] ; /* 0x0000040018167984 */
/* 0x000f220000004800 */
/*08b0*/ IMAD R19, R20, 0x4, R19 ; /* 0x0000000414137824 */
/* 0x001fe200078e0213 */
/*08c0*/ F2F.F64.F32 R14, R29 ; /* 0x0000001d000e7310 */
/* 0x004e240000201800 */
/*08d0*/ LDS R18, [R24.X4+0x8] ; /* 0x0000080018127984 */
/* 0x000fe80000004800 */
/*08e0*/ LDS R25, [R19] ; /* 0x0000000013197984 */
/* 0x000ea20000000800 */
/*08f0*/ DADD R16, R12, R16 ; /* 0x000000000c107229 */
/* 0x002e0c0000000010 */
/*0900*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x001064000000000e */
/*0910*/ IADD3 R17, R21.reuse, 0xc, RZ ; /* 0x0000000c15117810 */
/* 0x041fe40007ffe0ff */
/*0920*/ IADD3 R21, R21, 0x10, RZ ; /* 0x0000001015157810 */
/* 0x000fe20007ffe0ff */
/*0930*/ FMUL R12, R26, R27 ; /* 0x0000001b1a0c7220 */
/* 0x008fe20000400000 */
/*0940*/ LEA R27, R20, R19, 0x2 ; /* 0x00000013141b7211 */
/* 0x000fe200078e10ff */
/*0950*/ IMAD R26, R0, c[0x0][0x17c], R17 ; /* 0x00005f00001a7a24 */
/* 0x000fe400078e0211 */
/*0960*/ FMUL R22, R23, R22 ; /* 0x0000001617167220 */
/* 0x010fe20000400000 */
/*0970*/ LDS R17, [R24.X4+0xc] ; /* 0x00000c0018117984 */
/* 0x0001e20000004800 */
/*0980*/ F2F.F64.F32 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x000e620000201800 */
/*0990*/ IMAD R29, R20, 0x4, R27 ; /* 0x00000004141d7824 */
/* 0x000fc400078e021b */
/*09a0*/ LDS R16, [R27] ; /* 0x000000001b107984 */
/* 0x000ee20000000800 */
/*09b0*/ FMUL R25, R25, R18 ; /* 0x0000001219197220 */
/* 0x004fe40000400000 */
/*09c0*/ LEA R28, R20.reuse, R29, 0x2 ; /* 0x0000001d141c7211 */
/* 0x040fe400078e10ff */
/*09d0*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x000ea60000201800 */
/*09e0*/ IMAD R24, R20, 0x4, R28 ; /* 0x0000000414187824 */
/* 0x001fca00078e021c */
/*09f0*/ F2F.F64.F32 R18, R25 ; /* 0x0000001900127310 */
/* 0x0001220000201800 */
/*0a00*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x0022a4000000000c */
/*0a10*/ LDS R14, [R26.X4] ; /* 0x000000001a0e7984 */
/* 0x002fe80000004800 */
/*0a20*/ LDS R15, [R29] ; /* 0x000000001d0f7984 */
/* 0x000e620000000800 */
/*0a30*/ DADD R22, R12, R22 ; /* 0x000000000c167229 */
/* 0x0045220000000016 */
/*0a40*/ LEA R25, R20, R24, 0x2 ; /* 0x0000001814197211 */
/* 0x001fe400078e10ff */
/*0a50*/ LDS R12, [R26.X4+0x4] ; /* 0x000004001a0c7984 */
/* 0x004fe80000004800 */
/*0a60*/ LDS R13, [R28] ; /* 0x000000001c0d7984 */
/* 0x0006220000000800 */
/*0a70*/ DADD R18, R22, R18 ; /* 0x0000000016127229 */
/* 0x0105060000000012 */
/*0a80*/ LDS R22, [R26.X4+0x8] ; /* 0x000008001a167984 */
/* 0x004fe80000004800 */
/*0a90*/ LDS R23, [R24] ; /* 0x0000000018177984 */
/* 0x000ea80000000800 */
/*0aa0*/ LDS R24, [R26.X4+0xc] ; /* 0x00000c001a187984 */
/* 0x000fe20000004800 */
/*0ab0*/ FMUL R28, R16, R17 ; /* 0x00000011101c7220 */
/* 0x008fc60000400000 */
/*0ac0*/ LDS R27, [R25] ; /* 0x00000000191b7984 */
/* 0x000ee20000000800 */
/*0ad0*/ F2F.F64.F32 R16, R28 ; /* 0x0000001c00107310 */
/* 0x000f220000201800 */
/*0ae0*/ FMUL R29, R15, R14 ; /* 0x0000000e0f1d7220 */
/* 0x002fe20000400000 */
/*0af0*/ DADD R18, R18, R16 ; /* 0x0000000012127229 */
/* 0x01030c0000000010 */
/*0b00*/ F2F.F64.F32 R14, R29 ; /* 0x0000001d000e7310 */
/* 0x000f220000201800 */
/*0b10*/ FMUL R28, R13, R12 ; /* 0x0000000c0d1c7220 */
/* 0x001fce0000400000 */
/*0b20*/ F2F.F64.F32 R12, R28 ; /* 0x0000001c000c7310 */
/* 0x000e220000201800 */
/*0b30*/ FMUL R22, R23, R22 ; /* 0x0000001617167220 */
/* 0x004fce0000400000 */
/*0b40*/ F2F.F64.F32 R16, R22 ; /* 0x0000001600107310 */
/* 0x002e620000201800 */
/*0b50*/ DADD R14, R18, R14 ; /* 0x00000000120e7229 */
/* 0x010422000000000e */
/*0b60*/ FMUL R24, R27, R24 ; /* 0x000000181b187220 */
/* 0x008fe40000400000 */
/*0b70*/ IMAD R27, R20, 0x4, R25 ; /* 0x00000004141b7824 */
/* 0x000fc800078e0219 */
/*0b80*/ F2F.F64.F32 R18, R24 ; /* 0x0000001800127310 */
/* 0x004ea20000201800 */
/*0b90*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x001e4c000000000c */
/*0ba0*/ DADD R12, R12, R16 ; /* 0x000000000c0c7229 */
/* 0x002e8c0000000010 */
/*0bb0*/ DADD R18, R12, R18 ; /* 0x000000000c127229 */
/* 0x0040620000000012 */
/*0bc0*/ @P3 BRA 0x520 ; /* 0xfffff95000003947 */
/* 0x000fea000383ffff */
/*0bd0*/ ISETP.GT.AND P3, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f64270 */
/*0be0*/ @!P3 BRA 0xf50 ; /* 0x000003600000b947 */
/* 0x000fea0003800000 */
/*0bf0*/ IMAD R24, R0, c[0x0][0x17c], R21 ; /* 0x00005f0000187a24 */
/* 0x000fe200078e0215 */
/*0c00*/ LDS R14, [R27] ; /* 0x000000001b0e7984 */
/* 0x0005e20000000800 */
/*0c10*/ LEA R29, R20.reuse, R27, 0x2 ; /* 0x0000001b141d7211 */
/* 0x040fe400078e10ff */
/*0c20*/ IADD3 R26, R21.reuse, 0x4, RZ ; /* 0x00000004151a7810 */
/* 0x040fe20007ffe0ff */
/*0c30*/ LDS R15, [R24.X4] ; /* 0x00000000180f7984 */
/* 0x000ee20000004800 */
/*0c40*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0c50*/ IMAD R25, R20, 0x4, R29 ; /* 0x0000000414197824 */
/* 0x000fe200078e021d */
/*0c60*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0c70*/ LDS R22, [R29] ; /* 0x000000001d167984 */
/* 0x0009e20000000800 */
/*0c80*/ IMAD R26, R0, c[0x0][0x17c], R26 ; /* 0x00005f00001a7a24 */
/* 0x000fe200078e021a */
/*0c90*/ IADD3 R21, R21, 0x8, RZ ; /* 0x0000000815157810 */
/* 0x000fc40007ffe0ff */
/*0ca0*/ LDS R23, [R24.X4+0x4] ; /* 0x0000040018177984 */
/* 0x000f620000004800 */
/*0cb0*/ LEA R27, R20, R25, 0x2 ; /* 0x00000019141b7211 */
/* 0x004fc600078e10ff */
/*0cc0*/ LDS R12, [R24.X4+0x8] ; /* 0x00000800180c7984 */
/* 0x001fe20000004800 */
/*0cd0*/ LEA R29, R20, R27, 0x2 ; /* 0x0000001b141d7211 */
/* 0x010fc600078e10ff */
/*0ce0*/ LDS R13, [R25] ; /* 0x00000000190d7984 */
/* 0x0000a40000000800 */
/*0cf0*/ IMAD R25, R20, 0x4, R29 ; /* 0x0000000414197824 */
/* 0x001fe400078e021d */
/*0d00*/ FMUL R16, R14, R15 ; /* 0x0000000f0e107220 */
/* 0x008fe40000400000 */
/*0d10*/ LDS R15, [R24.X4+0xc] ; /* 0x00000c00180f7984 */
/* 0x0001e80000004800 */
/*0d20*/ F2F.F64.F32 R16, R16 ; /* 0x0000001000107310 */
/* 0x000ee20000201800 */
/*0d30*/ LDS R14, [R27] ; /* 0x000000001b0e7984 */
/* 0x000f220000000800 */
/*0d40*/ FMUL R22, R22, R23 ; /* 0x0000001716167220 */
/* 0x020fe20000400000 */
/*0d50*/ LEA R24, R20, R25, 0x2 ; /* 0x0000001914187211 */
/* 0x001fca00078e10ff */
/*0d60*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x000e220000201800 */
/*0d70*/ FMUL R28, R13, R12 ; /* 0x0000000c0d1c7220 */
/* 0x004fe20000400000 */
/*0d80*/ DADD R18, R18, R16 ; /* 0x0000000012127229 */
/* 0x00a20c0000000010 */
/*0d90*/ F2F.F64.F32 R12, R28 ; /* 0x0000001c000c7310 */
/* 0x000ea20000201800 */
/*0da0*/ LDS R16, [R26.X4] ; /* 0x000000001a107984 */
/* 0x002fe80000004800 */
/*0db0*/ LDS R17, [R29] ; /* 0x000000001d117984 */
/* 0x000e620000000800 */
/*0dc0*/ DADD R22, R18, R22 ; /* 0x0000000012167229 */
/* 0x0010860000000016 */
/*0dd0*/ LDS R18, [R26.X4+0x4] ; /* 0x000004001a127984 */
/* 0x001fe80000004800 */
/*0de0*/ LDS R19, [R25] ; /* 0x0000000019137984 */
/* 0x0000e20000000800 */
/*0df0*/ DADD R12, R22, R12 ; /* 0x00000000160c7229 */
/* 0x004546000000000c */
/*0e00*/ LDS R22, [R26.X4+0x8] ; /* 0x000008001a167984 */
/* 0x004fe20000004800 */
/*0e10*/ LEA R25, R20, R24, 0x2 ; /* 0x0000001814197211 */
/* 0x001fc600078e10ff */
/*0e20*/ LDS R23, [R24] ; /* 0x0000000018177984 */
/* 0x000e220000000800 */
/*0e30*/ FMUL R28, R14, R15 ; /* 0x0000000f0e1c7220 */
/* 0x010fc60000400000 */
/*0e40*/ LDS R24, [R26.X4+0xc] ; /* 0x00000c001a187984 */
/* 0x000fe20000004800 */
/*0e50*/ F2F.F64.F32 R14, R28 ; /* 0x0000001c000e7310 */
/* 0x000f660000201800 */
/*0e60*/ LDS R27, [R25] ; /* 0x00000000191b7984 */
/* 0x000ea20000000800 */
/*0e70*/ DADD R14, R12, R14 ; /* 0x000000000c0e7229 */
/* 0x020f22000000000e */
/*0e80*/ FMUL R29, R17, R16 ; /* 0x00000010111d7220 */
/* 0x002fc80000400000 */
/*0e90*/ F2F.F64.F32 R16, R29 ; /* 0x0000001d00107310 */
/* 0x000f220000201800 */
/*0ea0*/ FMUL R18, R19, R18 ; /* 0x0000001213127220 */
/* 0x008fce0000400000 */
/*0eb0*/ F2F.F64.F32 R18, R18 ; /* 0x0000001200127310 */
/* 0x000e620000201800 */
/*0ec0*/ FMUL R22, R23, R22 ; /* 0x0000001617167220 */
/* 0x001fe20000400000 */
/*0ed0*/ DADD R16, R14, R16 ; /* 0x000000000e107229 */
/* 0x01004c0000000010 */
/*0ee0*/ F2F.F64.F32 R12, R22 ; /* 0x00000016000c7310 */
/* 0x000ee20000201800 */
/*0ef0*/ FMUL R24, R27, R24 ; /* 0x000000181b187220 */
/* 0x004fe40000400000 */
/*0f00*/ IMAD R27, R20, 0x4, R25 ; /* 0x00000004141b7824 */
/* 0x000fca00078e0219 */
/*0f10*/ F2F.F64.F32 R14, R24 ; /* 0x00000018000e7310 */
/* 0x001e220000201800 */
/*0f20*/ DADD R16, R16, R18 ; /* 0x0000000010107229 */
/* 0x002ecc0000000012 */
/*0f30*/ DADD R12, R16, R12 ; /* 0x00000000100c7229 */
/* 0x008e0c000000000c */
/*0f40*/ DADD R18, R12, R14 ; /* 0x000000000c127229 */
/* 0x001048000000000e */
/*0f50*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0f60*/ @!P0 BRA 0x1140 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0f70*/ IMAD R29, R0, c[0x0][0x17c], R21 ; /* 0x00005f00001d7a24 */
/* 0x000fe200078e0215 */
/*0f80*/ LDS R16, [R27] ; /* 0x000000001b107984 */
/* 0x000fe20000000800 */
/*0f90*/ LEA R28, R20, R27, 0x2 ; /* 0x0000001b141c7211 */
/* 0x000fe400078e10ff */
/*0fa0*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0fb0*/ LDS R17, [R29.X4] ; /* 0x000000001d117984 */
/* 0x000ea20000004800 */
/*0fc0*/ LEA R23, R20, R28, 0x2 ; /* 0x0000001c14177211 */
/* 0x000fe400078e10ff */
/*0fd0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0fe0*/ LDS R14, [R28] ; /* 0x000000001c0e7984 */
/* 0x001fe20000000800 */
/*0ff0*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fc60007ffe0ff */
/*1000*/ LDS R15, [R29.X4+0x4] ; /* 0x000004001d0f7984 */
/* 0x000e280000004800 */
/*1010*/ LDS R12, [R29.X4+0x8] ; /* 0x000008001d0c7984 */
/* 0x000fe80000004800 */
/*1020*/ LDS R13, [R23] ; /* 0x00000000170d7984 */
/* 0x0007280000000800 */
/*1030*/ LDS R22, [R29.X4+0xc] ; /* 0x00000c001d167984 */
/* 0x000fe20000004800 */
/*1040*/ IMAD R23, R20, 0x4, R23 ; /* 0x0000000414177824 */
/* 0x008fca00078e0217 */
/*1050*/ LDS R25, [R23] ; /* 0x0000000017197984 */
/* 0x000ee20000000800 */
/*1060*/ LEA R27, R20, R23, 0x2 ; /* 0x00000017141b7211 */
/* 0x000fe200078e10ff */
/*1070*/ FMUL R24, R16, R17 ; /* 0x0000001110187220 */
/* 0x004fc80000400000 */
/*1080*/ F2F.F64.F32 R16, R24 ; /* 0x0000001800107310 */
/* 0x000ea20000201800 */
/*1090*/ FMUL R26, R14, R15 ; /* 0x0000000f0e1a7220 */
/* 0x001fce0000400000 */
/*10a0*/ F2F.F64.F32 R14, R26 ; /* 0x0000001a000e7310 */
/* 0x000e220000201800 */
/*10b0*/ FMUL R28, R13, R12 ; /* 0x0000000c0d1c7220 */
/* 0x010fce0000400000 */
/*10c0*/ F2F.F64.F32 R12, R28 ; /* 0x0000001c000c7310 */
/* 0x000f220000201800 */
/*10d0*/ DADD R16, R16, R18 ; /* 0x0000000010107229 */
/* 0x006e0c0000000012 */
/*10e0*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x001f22000000000e */
/*10f0*/ FMUL R22, R25, R22 ; /* 0x0000001619167220 */
/* 0x008fc80000400000 */
/*1100*/ F2F.F64.F32 R18, R22 ; /* 0x0000001600127310 */
/* 0x000e220000201800 */
/*1110*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x010e0c000000000c */
/*1120*/ DADD R18, R12, R18 ; /* 0x000000000c127229 */
/* 0x0010640000000012 */
/*1130*/ @P0 BRA 0xf70 ; /* 0xfffffe3000000947 */
/* 0x003fea000383ffff */
/*1140*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*1150*/ @!P0 BRA 0x12e0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*1160*/ IMAD R4, R0, c[0x0][0x17c], R21 ; /* 0x00005f0000047a24 */
/* 0x000fe200078e0215 */
/*1170*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f05270 */
/*1180*/ IMAD R21, R21, c[0x0][0x17c], R3 ; /* 0x00005f0015157a24 */
/* 0x000fc600078e0203 */
/*1190*/ SHF.L.U32 R16, R4, 0x2, RZ ; /* 0x0000000204107819 */
/* 0x000fe400000006ff */
/*11a0*/ LDS R4, [R21.X4+0x1000] ; /* 0x0010000015047984 */
/* 0x000fe20000004800 */
/*11b0*/ LEA R15, R21, 0x1000, 0x2 ; /* 0x00001000150f7811 */
/* 0x001fc600078e10ff */
/*11c0*/ LDS R13, [R16] ; /* 0x00000000100d7984 */
/* 0x000e240000000800 */
/*11d0*/ FMUL R13, R4, R13 ; /* 0x0000000d040d7220 */
/* 0x001fcc0000400000 */
/*11e0*/ F2F.F64.F32 R12, R13 ; /* 0x0000000d000c7310 */
/* 0x000e240000201800 */
/*11f0*/ DADD R18, R18, R12 ; /* 0x0000000012127229 */
/* 0x003062000000000c */
/*1200*/ @!P0 BRA 0x12e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*1210*/ ISETP.NE.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe20003f05270 */
/*1220*/ IMAD R17, R20.reuse, 0x4, R15 ; /* 0x0000000414117824 */
/* 0x040fe200078e020f */
/*1230*/ LDS R13, [R16+0x4] ; /* 0x00000400100d7984 */
/* 0x001fe80000000800 */
/*1240*/ LDS R4, [R17] ; /* 0x0000000011047984 */
/* 0x000e2e0000000800 */
/*1250*/ @P0 LEA R20, R20, R17, 0x2 ; /* 0x0000001114140211 */
/* 0x000fe200078e10ff */
/*1260*/ @P0 LDS R15, [R16+0x8] ; /* 0x00000800100f0984 */
/* 0x000fea0000000800 */
/*1270*/ @P0 LDS R20, [R20] ; /* 0x0000000014140984 */
/* 0x000ea20000000800 */
/*1280*/ FMUL R13, R4, R13 ; /* 0x0000000d040d7220 */
/* 0x001fcc0000400000 */
/*1290*/ F2F.F64.F32 R12, R13 ; /* 0x0000000d000c7310 */
/* 0x000e220000201800 */
/*12a0*/ @P0 FMUL R15, R20, R15 ; /* 0x0000000f140f0220 */
/* 0x004fce0000400000 */
/*12b0*/ @P0 F2F.F64.F32 R14, R15 ; /* 0x0000000f000e0310 */
/* 0x000ea20000201800 */
/*12c0*/ DADD R18, R18, R12 ; /* 0x0000000012127229 */
/* 0x003e8c000000000c */
/*12d0*/ @P0 DADD R18, R18, R14 ; /* 0x0000000012120229 */
/* 0x004048000000000e */
/*12e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x001fec0000010000 */
/*12f0*/ @P2 CALL.REL.NOINC 0x1310 ; /* 0x0000001000002944 */
/* 0x000fe20003c00000 */
/*1300*/ BRA 0x2d0 ; /* 0xffffefc000007947 */
/* 0x000fea000383ffff */
/*1310*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc80003f06270 */
/*1320*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fda0000706670 */
/*1330*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*1340*/ MOV R3, 0x8 ; /* 0x0000000800037802 */
/* 0x000fe20000000f00 */
/*1350*/ IMAD R2, R5, c[0x0][0x178], R6 ; /* 0x00005e0005027a24 */
/* 0x000fc800078e0206 */
/*1360*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*1370*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b04 */
/*1380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1390*/ BRA 0x1390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*13a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifdef _WIN32
# define NOMINMAX
#endif
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// includes, project
// includes, kernels
#include <cuda.h>
#include <cuda_runtime.h>
#define MAX_TILE_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
double* read_array(const char* filename, int len) {
double *x = (double*) malloc(len * sizeof(double));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%lf", &x[i]);
}
fclose(fp);
return x;
}
__global__ void computeOnDevice(double* dA,double* dB, double* dC, int nRows, int tileSize, float* incTime)
{
__shared__ float ds_M[MAX_TILE_SIZE];
__shared__ float ds_N[MAX_TILE_SIZE];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * tileSize + ty,
Col = bx * tileSize + tx;
double Pvalue = 0;
for (int m = 0; m < (nRows-1)/tileSize+1; ++m) {
if (Row < nRows && m*tileSize+tx < nRows)
ds_M[ty * tileSize + tx] = dA[Row*nRows + m*tileSize+tx];
else
ds_M[ty * tileSize + tx] = 0;
if (Col < nRows && m*tileSize+ty < nRows)
ds_N[ty * tileSize + tx] = dB[(m*tileSize+ty)*nRows+Col];
else
ds_N[ty * tileSize + tx] = 0;
__syncthreads();
for (int k = 0; k < tileSize; ++k)
Pvalue += ds_M[ty * tileSize + k] * ds_N[k * tileSize + tx];
__syncthreads();
}
if (Row < nRows && Col < nRows)
dC[Row*nRows+Col] = Pvalue;
return;//Placeholder
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
if(argc!=2)
{
printf("Usage: ./problem2 N\n");
return 0;
}
int nRows = 1024;
int num_elements = nRows*nRows;
int tileSize = atoi(argv[1]); //change this for scaling analysis
float incTime=0; // Time for GPU
double* hA = read_array("inputA.inp",num_elements);
double* hB = read_array("inputB.inp",num_elements);
double* hC = (double*) malloc(num_elements * sizeof(double));
dim3 dimGrid((nRows - 1) / tileSize + 1, (nRows - 1) / tileSize + 1, 1);
dim3 dimBlock(tileSize, tileSize, 1);
double * dA, *dB, *dC;
cudaError error = cudaMalloc((void**)&dA, sizeof(double)*num_elements);
error = cudaMalloc((void**)&dB, sizeof(double)*num_elements);
error = cudaMalloc((void**)&dC, sizeof(double)*num_elements);
cudaMemcpy(dA, hA, sizeof(double)*num_elements, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, sizeof(double)*num_elements, cudaMemcpyHostToDevice);
cudaEvent_t startEvent_inc, stopEvent_inc;
cudaEventCreate(&startEvent_inc);
cudaEventCreate(&stopEvent_inc);
cudaEventRecord(startEvent_inc,0); // starting timing for inclusive
// **===-------- Modify the body of this function -----------===**
computeOnDevice<<<dimGrid, dimBlock>>>(dA, dB, dC, nRows, tileSize, &incTime);
// **===-----------------------------------------------------------===**
cudaThreadSynchronize();
cudaMemcpy(hC, dC, sizeof(double)*num_elements, cudaMemcpyDeviceToHost);
cudaEventRecord(stopEvent_inc,0); //ending timing for inclusive
cudaEventSynchronize(stopEvent_inc);
cudaEventElapsedTime(&incTime, startEvent_inc, stopEvent_inc);
printf("%lf\n%f\n%d\n",hC[num_elements - 1],incTime,tileSize);
// cleanup memory
free(hA);
free(hB);
free(hC);
return 0;
} | .file "tmpxft_00169e73_00000000-6_problem2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%lf"
.text
.globl _Z10read_arrayPKci
.type _Z10read_arrayPKci, @function
_Z10read_arrayPKci:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %esi, %ebx
movslq %esi, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
leaq .LC0(%rip), %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %r12
testl %ebx, %ebx
jle .L4
movq %r14, %rbx
addq %r14, %rbp
leaq .LC1(%rip), %r13
.L5:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
movq %r12, %rdi
call fclose@PLT
movq %r14, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10read_arrayPKci, .-_Z10read_arrayPKci
.globl _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf
.type _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf, @function
_Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15computeOnDevicePdS_S_iiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf, .-_Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf
.globl _Z15computeOnDevicePdS_S_iiPf
.type _Z15computeOnDevicePdS_S_iiPf, @function
_Z15computeOnDevicePdS_S_iiPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15computeOnDevicePdS_S_iiPf, .-_Z15computeOnDevicePdS_S_iiPf
.section .rodata.str1.1
.LC2:
.string "Usage: ./problem2 N\n"
.LC4:
.string "inputA.inp"
.LC5:
.string "inputB.inp"
.LC6:
.string "%lf\n%f\n%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L17
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L18:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
movl $0x00000000, 4(%rsp)
movl $1048576, %esi
leaq .LC4(%rip), %rdi
call _Z10read_arrayPKci
movq %rax, %r13
movl $1048576, %esi
leaq .LC5(%rip), %rdi
call _Z10read_arrayPKci
movq %rax, %r12
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbp
movl $1023, %eax
movl $0, %edx
idivl %ebx
addl $1, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl %ebx, 60(%rsp)
movl %ebx, 64(%rsp)
movl $1, 68(%rsp)
leaq 8(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $8388608, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movsd 8388600(%rbp), %xmm0
movl %r14d, %edx
pxor %xmm1, %xmm1
cvtss2sd 4(%rsp), %xmm1
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
jmp .L18
.L23:
leaq 4(%rsp), %r9
movl %ebx, %r8d
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z43__device_stub__Z15computeOnDevicePdS_S_iiPfPdS_S_iiPf
jmp .L19
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z15computeOnDevicePdS_S_iiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15computeOnDevicePdS_S_iiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifdef _WIN32
# define NOMINMAX
#endif
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// includes, project
// includes, kernels
#include <cuda.h>
#include <cuda_runtime.h>
#define MAX_TILE_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
double* read_array(const char* filename, int len) {
double *x = (double*) malloc(len * sizeof(double));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%lf", &x[i]);
}
fclose(fp);
return x;
}
__global__ void computeOnDevice(double* dA,double* dB, double* dC, int nRows, int tileSize, float* incTime)
{
__shared__ float ds_M[MAX_TILE_SIZE];
__shared__ float ds_N[MAX_TILE_SIZE];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * tileSize + ty,
Col = bx * tileSize + tx;
double Pvalue = 0;
for (int m = 0; m < (nRows-1)/tileSize+1; ++m) {
if (Row < nRows && m*tileSize+tx < nRows)
ds_M[ty * tileSize + tx] = dA[Row*nRows + m*tileSize+tx];
else
ds_M[ty * tileSize + tx] = 0;
if (Col < nRows && m*tileSize+ty < nRows)
ds_N[ty * tileSize + tx] = dB[(m*tileSize+ty)*nRows+Col];
else
ds_N[ty * tileSize + tx] = 0;
__syncthreads();
for (int k = 0; k < tileSize; ++k)
Pvalue += ds_M[ty * tileSize + k] * ds_N[k * tileSize + tx];
__syncthreads();
}
if (Row < nRows && Col < nRows)
dC[Row*nRows+Col] = Pvalue;
return;//Placeholder
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
if(argc!=2)
{
printf("Usage: ./problem2 N\n");
return 0;
}
int nRows = 1024;
int num_elements = nRows*nRows;
int tileSize = atoi(argv[1]); //change this for scaling analysis
float incTime=0; // Time for GPU
double* hA = read_array("inputA.inp",num_elements);
double* hB = read_array("inputB.inp",num_elements);
double* hC = (double*) malloc(num_elements * sizeof(double));
dim3 dimGrid((nRows - 1) / tileSize + 1, (nRows - 1) / tileSize + 1, 1);
dim3 dimBlock(tileSize, tileSize, 1);
double * dA, *dB, *dC;
cudaError error = cudaMalloc((void**)&dA, sizeof(double)*num_elements);
error = cudaMalloc((void**)&dB, sizeof(double)*num_elements);
error = cudaMalloc((void**)&dC, sizeof(double)*num_elements);
cudaMemcpy(dA, hA, sizeof(double)*num_elements, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, sizeof(double)*num_elements, cudaMemcpyHostToDevice);
cudaEvent_t startEvent_inc, stopEvent_inc;
cudaEventCreate(&startEvent_inc);
cudaEventCreate(&stopEvent_inc);
cudaEventRecord(startEvent_inc,0); // starting timing for inclusive
// **===-------- Modify the body of this function -----------===**
computeOnDevice<<<dimGrid, dimBlock>>>(dA, dB, dC, nRows, tileSize, &incTime);
// **===-----------------------------------------------------------===**
cudaThreadSynchronize();
cudaMemcpy(hC, dC, sizeof(double)*num_elements, cudaMemcpyDeviceToHost);
cudaEventRecord(stopEvent_inc,0); //ending timing for inclusive
cudaEventSynchronize(stopEvent_inc);
cudaEventElapsedTime(&incTime, startEvent_inc, stopEvent_inc);
printf("%lf\n%f\n%d\n",hC[num_elements - 1],incTime,tileSize);
// cleanup memory
free(hA);
free(hB);
free(hC);
return 0;
} | #ifdef _WIN32
# define NOMINMAX
#endif
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <ctime>
// includes, project
// includes, kernels
#include <hip/hip_runtime.h>
#define MAX_TILE_SIZE 1024
////////////////////////////////////////////////////////////////////////////////
// declaration, forward
double* read_array(const char* filename, int len) {
double *x = (double*) malloc(len * sizeof(double));
FILE *fp = fopen(filename, "r");
for (int i = 0; i < len; i++) {
fscanf(fp, "%lf", &x[i]);
}
fclose(fp);
return x;
}
__global__ void computeOnDevice(double* dA,double* dB, double* dC, int nRows, int tileSize, float* incTime)
{
__shared__ float ds_M[MAX_TILE_SIZE];
__shared__ float ds_N[MAX_TILE_SIZE];
int bx = blockIdx.x, by = blockIdx.y,
tx = threadIdx.x, ty = threadIdx.y,
Row = by * tileSize + ty,
Col = bx * tileSize + tx;
double Pvalue = 0;
for (int m = 0; m < (nRows-1)/tileSize+1; ++m) {
if (Row < nRows && m*tileSize+tx < nRows)
ds_M[ty * tileSize + tx] = dA[Row*nRows + m*tileSize+tx];
else
ds_M[ty * tileSize + tx] = 0;
if (Col < nRows && m*tileSize+ty < nRows)
ds_N[ty * tileSize + tx] = dB[(m*tileSize+ty)*nRows+Col];
else
ds_N[ty * tileSize + tx] = 0;
__syncthreads();
for (int k = 0; k < tileSize; ++k)
Pvalue += ds_M[ty * tileSize + k] * ds_N[k * tileSize + tx];
__syncthreads();
}
if (Row < nRows && Col < nRows)
dC[Row*nRows+Col] = Pvalue;
return;//Placeholder
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv)
{
if(argc!=2)
{
printf("Usage: ./problem2 N\n");
return 0;
}
int nRows = 1024;
int num_elements = nRows*nRows;
int tileSize = atoi(argv[1]); //change this for scaling analysis
float incTime=0; // Time for GPU
double* hA = read_array("inputA.inp",num_elements);
double* hB = read_array("inputB.inp",num_elements);
double* hC = (double*) malloc(num_elements * sizeof(double));
dim3 dimGrid((nRows - 1) / tileSize + 1, (nRows - 1) / tileSize + 1, 1);
dim3 dimBlock(tileSize, tileSize, 1);
double * dA, *dB, *dC;
hipError_t error = hipMalloc((void**)&dA, sizeof(double)*num_elements);
error = hipMalloc((void**)&dB, sizeof(double)*num_elements);
error = hipMalloc((void**)&dC, sizeof(double)*num_elements);
hipMemcpy(dA, hA, sizeof(double)*num_elements, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, sizeof(double)*num_elements, hipMemcpyHostToDevice);
hipEvent_t startEvent_inc, stopEvent_inc;
hipEventCreate(&startEvent_inc);
hipEventCreate(&stopEvent_inc);
hipEventRecord(startEvent_inc,0); // starting timing for inclusive
// **===-------- Modify the body of this function -----------===**
computeOnDevice<<<dimGrid, dimBlock>>>(dA, dB, dC, nRows, tileSize, &incTime);
// **===-----------------------------------------------------------===**
hipDeviceSynchronize();
hipMemcpy(hC, dC, sizeof(double)*num_elements, hipMemcpyDeviceToHost);
hipEventRecord(stopEvent_inc,0); //ending timing for inclusive
hipEventSynchronize(stopEvent_inc);
hipEventElapsedTime(&incTime, startEvent_inc, stopEvent_inc);
printf("%lf\n%f\n%d\n",hC[num_elements - 1],incTime,tileSize);
// cleanup memory
free(hA);
free(hB);
free(hC);
return 0;
} |
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