Patent Document

BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method of signal noise reduction, and more particularly, to a method of signal noise reduction that may be applied to digital chips in a computer.  
         [0003]     2. Description of the Related Art  
         [0004]     Electrical signals from typical electronic devices, such as computers, often have signal bounce problem. In order to ensure correct signals, one method involves performing a delay process on a signal that may have noise. For example, when a digital signal changes (e.g. from 1 to 0), noise may occur. Please refer to  FIG. 1 . Between time t 0  and t 1 , received digital signals D 0  and D 1  are both 1; at time t 2 , D 2 =0, which means the digital signal has changed. Therefore, at times t 3 , t 4 , regardless of what the signals D 3  or D 4  are, the received signal is still D 1 , until at time t 5  if signal D 5  is still 0, the received signal will then be changed from 1 to 0.  
         [0005]     This method is usually applied for slower speed signals from general purpose input output (GPIO) ports, but can also be applied to higher speed signals, such as transmission signals between a CPU and a south bridge chip in a computer.  
         [0006]     Please refer to  FIG. 2 .  FIG. 2  is a schematic drawing of prior art technology processing changing time points for three pins P 1 , P 2 , P 3 . When the signal changes, after a period of delay, the signal can be confirmed.  FIG. 2  shows that the signal changing time points of the three pins are usually different, and the traditional method of utilizing a delay time count for each pin P 1 , P 2 , P 3  requires hardware resources and software that makes use of a timer. However, since there may be hundreds of GPIO pins, the computer must waste resources on support for the pins. Furthermore, when a GPIO pin is added, additional programs will be added, which is inefficient and which may cause numerous errors.  
         [0007]     Therefore, it is desirable to provide a method of signal noise reduction to mitigate and/or obviate the aforementioned problems.  
       SUMMARY OF THE INVENTION  
       [0008]     A main objective of the present invention is to provide a method of signal noises reduction which can reduce numbers of program code.  
         [0009]     Another objective f the present invention is to provide a method of signal noises reduction which can perform signal confirmation on a plurality of pins.  
         [0010]     In order to achieve the above-mentioned objectives, a method of signal noise reduction for a digital chip to prevent errors when signal noise occurs, the method comprising: 
        step A: checking whether a received recent signal and n previous signals are all consistent with digital logical operations, wherein n previous signals provide a first signal to an nth signal prior to the received recent signal, and 1≦n≦5;     step B: determining a new confirmed signal with digital logical operations according to a previous confirmed signal and a result from step A as follows: 
            condition 1: when the result from step A indicates the received recent signal and the n previous signals are consistent, the new confirmed signal is set to the received recent signal; and     condition 2: when the result from step A indicates the received recent signal and the n previous signals are not consistent, the new confirmed signal is set to a previous confirmed signal.    
               
 
         [0015]     In order to achieve step A and step B, it is not necessary to have a logical “if” operation; for example, in the embodiments, performing AND and OR logical operations to the received recent signals and n previous signals can also achieve step A and step B.  
         [0016]     Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]      FIG. 1  is a schematic drawing of prior art technology processing signals.  
         [0018]      FIG. 2  is a schematic drawing of prior art technology processing three pins.  
         [0019]      FIG. 3  shows a computer.  
         [0020]      FIG. 4  shows a first embodiment of a signal noise reduction system in a computer according to the present invention.  
         [0021]      FIG. 5  is a flowchart of a method of signal noise reduction according to the present invention.  
         [0022]      FIG. 6  is a schematic drawing of logical operations according to the present invention.  
         [0023]      FIG. 7  is another schematic drawing of logical operations according to the present invention.  
         [0024]      FIG. 8  shows a second embodiment of a signal noise reduction system in a computer according to the present invention.  
         [0025]      FIG. 9  shows a third embodiment of a signal noise reduction system in a computer according to the present invention.  
         [0026]      FIG. 10  shows a signal noise reduction system performing logical operations to a plurality of pins. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0027]     Please refer to  FIG. 3 . A typical computer  10  has a screen  15 , a keyboard device  31 , some function keys  33 , a motherboard (not shown), a memory (not shown), etc. Please refer to  FIG. 4 .  FIG. 4  shows a first embodiment of a signal noise reduction system  20  in the computer  10 . The signal noise reduction system  20  comprises a signal generating element  30  and a digital chip  40 . The signal generating element  30 , such as the keyboard device  31  or the function keys  33 , is electrically connected to the at least one digital chip  40  (such as a keyboard control chip  41 , which is basically pins of a GPIO).  
         [0028]     Please refer to  FIG. 5 .  FIG. 5  is a flowchart of a method of signal noise reduction according to the present invention. This flowchart describes the signal processing performed by the signal generating element  30  and a connection line  21  of the digital chip  40 . Samples shown in  FIG. 1  indicate the signals generated by the signal generating element  30 ; “Sample 1” indicates the first signal, “Sample 2” indicates the second signal, and so on. DebounceHigh, DebounceLow and StableSignal are variables of the logical operations, wherein StableSignal indicates signals confirmed by the digital chip  40 . Please refer to  FIG. 6  and  FIG. 7  for further description of the signal processing.  
         [0000]     Step  301 :  
         [0029]     An AND logical operation is performed on the received recent signal and “n” previous signals; in this embodiment, n=2, so 3 Samples are selected; the corresponding formula is: 
 
DebounceHigh=(Sample 1) AND (Sample 2) AND (Sample 3) 
 
         [0030]     Please refer to  FIG. 6 . In the logical operation for Sample 1, Sample 2 and Sample 3, since each of Sample 1, Sample 2 and Sample 3 are “1”, DebounceHigh( 3 )=1.  
         [0031]     In the logical operation for Sample 2, Sample 3 and Sample 4, since Sample 4=0, DebounceHigh( 4 )=0.  
         [0032]     Step  301  indicates that only when all Samples are “1”, then DebounceHigh is “1”; under any other condition DebounceHigh is “0”.  
         [0033]     The above-mentioned “n” can be other values, but is preferably between 1 and 5. For example, when n=1, the corresponding formula is: 
 
DebounceHigh=(Sample 1) AND (Sample 2) 
 
 Step  302 : 
 
         [0034]     An OR logical operation is performed on the received recent signal and “n” previous signals; the corresponding formula is: 
 
DebounceLow=(Sample 1) OR (Sample 2) OR (Sample 3) 
 
         [0035]     Please refer to  FIG. 6 . In the operation for Sample 1, Sample 2 and Sample 3, since all of Sample 1, Sample 2 and Sample 3 are “1”, DebounceHigh( 3 )=1.  
         [0036]     In the operation for Sample 4, Sample 5 and Sample 6, since Sample 4, Sample 5 and Sample 6 are all “0”, DebounceLow ( 6 )=0.  
         [0037]     Step  302  indicates that only when all Samples are “0”, then DebounceLow is “0”, and under any other condition DebounceLow is “1”.  
         [0000]     Step  303 :  
         [0038]     An OR logical operation is performed with the previous confirmed signal and result from step  301 , and then an AND logical operation is performed on the result from logical operation  302  and the result from step  302 ; the corresponding formula is 
 
StableSignal=(StableSignal OR DebounceHigh) AND (DebounceLow) 
 
         [0039]     Please refer to  FIG. 6 . For example, in order to calculate StableSignal( 3 ), assuming StableSignal( 2 )=1 (which means the previous confirmed signal was “1”), StableSignal( 3 )=( 1  OR  1 ) AND ( 1 )=1, so the new confirmed signal is 1.  
         [0040]     By way of further example, StableSignal( 6 )=( 1  OR  0 ) AND ( 0 )=0, which indicates that the previous confirmed signal was “1”, and the new confirmed signal is 0.  
         [0041]     The formulas in the above-mentioned description may be explained as follows.  
         [0042]     Step  301  and step  302  may be explained as: checking whether received recent signals and “n” previous signals are all consistent digital logical operations.  
         [0043]     DebounceHigh is used for checking whether all Samples are 1, and DebounceLow is used for checking whether all Samples are 0. When all Samples are 1 (the signals are consistent), DebounceHigh=1 and DebounceLow=1; when all Samples are 0 (the signals are consistent), DebounceHigh=0 and DebounceLow=0.  
         [0044]     When the signals are not consistent (some Samples are “1”, some Samples are “0”), DebounceHigh=0 and DebounceLow=1.  
         [0045]     Step  303  may be described as determining a new confirmed signal with digital logical operations based upon the previous confirmed signal and the results from step  301  and step  302 , using the following two conditions:  
         [0046]     Condition 1: If step  301  and step  302  find consistent signals, then the new confirmed signal is set to the recent signals and the previous confirmed signal is ignored.  
         [0000]     For example, when all Samples are 1 (DebounceHigh=1, DebounceLow=1),  
         [0000]     then StableSignal= 
         [0047]     (StableSignal OR DebounceHigh) AND (DebounceLow)  
         [0048]     =(StableSignal OR  1 ) AND  1 =1,  
         [0049]     and regardless of whether StableSignal (the previous confirmed signal) is “1” or “0”, the new confirmed signal is “1”.  
         [0050]     When all Samples are 0  
         [0051]     (DebounceHigh=0, DebounceLow=0), then  
         [0000]     StableSignal= 
         [0052]     (StableSignal OR  0 ) AND  0 =0,  
         [0053]     and regardless of whether StableSignal (the previous confirmed signal) is “1” or “0”, the new confirmed signal is “0”.  
         [0054]     Condition 2: If step  301  and step  302  find non-consistent signals, the new confirmed signal is set to the previous confirmed signal. That is,  
         [0000]     StableSignal=(StableSignal OR DebounceHigh) AND (DebounceLow)  
         [0055]     =(StableSignal OR  0 ) AND  1 =StableSignal  
         [0056]     It is noted that, since the signals are not consistent, DebounceHigh=0 and DebounceLow=1 may be assumed.  
         [0057]     Please refer to  FIG. 6 . When the signals are not consistent, such as when Sample 2=1, Sample 3=1 and Sample 4=0:  
         [0058]     StableSignal( 4 )=StableSignal( 3 )=1  
         [0059]     Please refer to  FIG. 7 . When the signals are not consistent, such as when Sample 2=0, Sample 3=0 and Sample 4=1:  
         [0060]     StableSignal( 4 )=StableSignal( 3 )=0.  
         [0061]     Please refer to  FIG. 8 .  FIG. 8  shows a second embodiment of a signal noise reduction system in a computer according to the present invention. A difference between this embodiment and the first embodiment is that there is more than one signal generating element; for example, three signal generating elements  30   a ,  30   b ,  30   c  are all connected to the same digital chip  40 .  
         [0062]     Please refer to  FIG. 9 .  FIG. 9  shows a third embodiment of a signal noise reduction system in a computer according to the present invention. A difference between this embodiment and the first embodiment is that the signal generating element  30  may be a south bridge chip  32  (or a north bridge chip), which means that non-GPIO pins can be used in the technology of the present invention.  
         [0063]     Please refer to  FIG. 10 .  FIG. 10  shows a signal noise reduction system performing logical operations to a plurality of pins. For example, when processing eight pins p 1 ˜p 8 , StableSignal for each pin can be calculated simultaneously. For example, an 8 bit system can calculate 8 pins simultaneously, and a 16 bit system can calculate 16 pins simultaneously, which is an advantage of the present invention.  
         [0064]     The above-mentioned logical operations can be executed by the digital chip  40 .  
         [0065]     Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed. For example, when DebounceHigh=1, there is no need to calculate DebounceLow, and StableSignal may simply be set to “1”; and when DebounceLow=0, StableSignal may be directly set to “0”. Of course, utilizing a logical “if” operation may reduce efficiencies, therefore, the embodiment of the present invention do not use the logical “if” operation.

Technology Category: h