Patent Document

RELATED APPLICATIONS 
       [0001]    The present application is based on, and claims priority from, Taiwan Application Serial Number 95121086, filed Jun. 13, 2006, the disclosure of which is hereby incorporated by reference herein in its entirety. 
       BACKGROUND 
       [0002]    1. Field of Invention 
         [0003]    The present invention relates to a method of manufacturing an array substrate of a liquid crystal display (LCD). More particularly, the present invention relates to a method of manufacturing an array substrate of a transflective LCD. 
         [0004]    2. Description of Related Art 
         [0005]    Recently, the progress of opto-electronic technology and the rapid development of digital technology push forward the expansion of the LCD market. Because the LCD has many advantages such as high display quality, small size, light weight, low driving voltage and low power consumption, it has been widely applied to many electronics products such as PDAs, mobile phones, digital videos, notebooks, desk-top displays, digital cameras and projection TVs. Nowadays, LCDs are gradually replacing traditional cathode ray tube (CRT) displays and becoming the mainstream product in the display market. 
         [0006]    The manufacturing processes of manufacturing an array substrate of a LCD mainly comprise three kinds of different manufacturing processes, the deposition process, the lithography process and the etching process. Among these processes, the lithography process has the highest production cost. Therefore, many LCD manufacturers tried to reduce LCD production cost by reducing the number of photo-masks needed in the lithography process. 
       SUMMARY 
       [0007]    It is therefore an aspect of the present invention to provide a method of manufacturing an array substrate of a transflective liquid crystal display. This method only uses three to four photo-masks to manufacture transflective LCDs. 
         [0008]    In accordance with the foregoing and other aspects of the present invention, a method of manufacturing an array substrate of a transflective LCD is provided. Firstly, a transparent conductive layer and a first metal layer are sequentially formed on a substrate. Secondly, the first metal layer and the transparent conductive layer are defined to allow the first metal layer to form complementary patterns of a gate electrode, a first conducting wire, a capacitance line and a penetrating region of a pixel region and to allow the transparent conductive layer to form a pixel electrode. Thirdly, a first passivation layer and a second metal layer are sequentially formed on the substrate. Fourthly, the second metal layer is defined to form the gate electrode, the first conducting wire and the capacitance line. The capacitance line, and the first passivation layer and the transparent conductive layer constitute a storage capacitance. Fifthly, a dielectric layer is formed on the substrate. Sixthly, the dielectric layer and the second metal layer on a penetrating region of the pixel region, the first passivation layer on sides of the penetrating region and the first passivation layer surrounding an end of the first conductive line are removed. Seventhly, a channel region is formed on the dielectric layer on the gate electrode. Eighthly, a third metal layer is formed on the substrate. Ninthly, the third metal layer is defined to form a second conductive line, a source electrode and a drain electrode. The source electrode and the drain electrode are at two sides of the channel region. The drain electrode is electrically connected to the transparent conductive layer. Tenthly, a second passivation layer is formed on the substrate. Finally, the second passivation layer and the first passivation layer are defined to remove the second passivation layer and the first passivation layer on the penetrating region on the pixel region. 
         [0009]    In a preferred embodiment of the present invention, the step of defining the first metal layer and the transparent conductive layer is performed by using a half-tone photo-mask. The second metal layer is defined by backward exposure. The step of removing the dielectric layer and the second metal layer on the penetrating region of the pixel region is performed by using a half-tone photo-mask. The second passivation layer and the first passivation layer are defined by backward exposure. 
         [0010]    In accordance with the foregoing and other aspects of the present invention, a method of manufacturing an array substrate of a transflective LCD is provided. Firstly, a transparent conductive layer and a first metal layer are sequentially formed on a substrate. Secondly, the first metal layer and the transparent conductive layer are defined to allow the first metal layer to form complementary patterns of a gate electrode, a first conducting wire, a capacitance line and a penetrating region of a pixel region and to allow the transparent conductive layer to form a pixel electrode. Thirdly, a first passivation layer and a second metal layer are sequentially formed on the substrate. Fourthly, the second metal layer is defined to form the gate electrode, the first conducting wire and the capacitance line. The capacitance line, and the first passivation layer and the transparent conductive layer constitute a storage capacitance. Fifthly, a dielectric layer and a semiconductor layer are formed on the substrate. Sixthly, the semiconductor layer, the dielectric layer and the second metal layer on a penetrating region of the pixel region, the first passivation layer on sides of the penetrating region, the semiconductor layer, the dielectric layer and the first passivation layer surrounding an end of the first conductive line are removed. At the same time, a channel region is formed on the dielectric layer on the gate electrode. Seventhly, a third metal layer is formed on the substrate. Eighthly, the third metal layer is defined to form a second conductive line, a source electrode and a drain electrode. The source electrode and the drain electrode are at two sides of the channel region. The drain electrode is electrically connected to the transparent conductive layer. Ninthly, a second passivation layer is formed on the substrate. Finally, the second passivation layer and the first passivation layer are defined to remove the second passivation layer and the first passivation layer on the penetrating region on the pixel region. 
         [0011]    In another preferred embodiment of the present invention, the step of defining the first metal layer and the transparent conductive layer is performed by using a half-tone photo-mask. The second metal layer is defined by backward exposure. The step of removing the semiconductor layer, dielectric layer and the second metal layer on the penetrating region of the pixel region is performed by using a half-tone photo-mask. The second passivation layer and the first passivation layer are defined by backward exposure. 
         [0012]    In according to the present invention, half-tone photo-masks and back exposures are used to reduce the number of photo-masks needed in the lithography process. Therefore, only three to four photo-masks are needed in manufacturing a transflective LCD. Besides, The storage capacitances connect in series, not only the capacitance value per unit of area can be increased but also the overall area on the substrate occupied by the storage capacitance can be reduced. Moreover, the aperture rate of the penetrating region of the pixel region and the brightness of the LCD are increased. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
           [0014]      FIGS. 1A-1G  are cross-section views of an array substrate of a transflective LCD in process steps according to the first embodiment; and 
           [0015]      FIGS. 2A-2D  are cross-section views of an array substrate of a transflective LCD in process steps according to the second embodiment. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
       [0016]      FIGS. 1A-1G  are cross-section views of an array substrate of a transflective LCD in process steps according to the first embodiment of the present invention. In  FIG. 1A , regions from left to right are a thin film transistor (TFT) region A, a pixel region B, a storage capacitance region C and a gate pad region D, respectively. First, a transparent conductive layer  110  and a fist metal layer  120  are formed sequentially on a substrate  100 . Then, a first half-tone photo-mask is used to define the first metal layer  120  and the transparent conductive layer  110  simultaneously. The first metal layer  120  is defined to form complementary patterns  120   a,    120   c  and  120   d  and a reflective layer  120   b,  which is on a penetrating portion of the pixel region B. The complementary patterns  120   a,    120   c  and  120   d  are the complementary patterns of a gate electrode, a capacitance line and a gate pad, respectively. A complementary pattern of a scan line is also formed in the first metal layer  120  but not shown in  FIG. 1A . The transparent conductive layer  110  is defined to form a pixel electrode. The first metal layer  120  with complementary patterns of the gate electrode  120   a,  the capacitance line  120   c,  the scan line (not shown) and the gate pad  120   d  is used as a photo-mask for the following backward exposure process. The reflective layer  120   b  on the penetrating portion of the pixel region B is used to reflect external light which enters into the LCD. 
         [0017]    In  FIG. 1B , a passivation layer  130  and a second metal layer  140  are sequentially formed on the substrate  100 . Then, the first metal layer  120  with complementary patterns is used as a photo-mask to define the second metal layer  140  by means of a backward exposure. Therefore, the second metal layer  140  is defined to form a gate electrode  140   a,  a capacitance line  140   c,  a scan line (not shown) and a gate pad  140   d.  At the same time, a sacrifice metal layer  140   b  is formed on the penetrating portion of the pixel region B in the second metal layer  140 . The capacitance line  140   c,  the underlying first passivation layer  130  and transparent conductive layer  110  constitute a first storage capacitance  141 . 
         [0018]    In  FIG. 1C , a dielectric layer  150  is formed on the substrate  100 . 
         [0019]    In  FIG. 1D , a second photo-mask is used to define the dielectric layer  150 , the second metal layer  140  and the first passivation layer  130  simultaneously. The second photo-mask is a half-tone photo-mask. Because different regions of the half-tone photo-mask have different light transmittances, photo resist with different thicknesses on different regions is formed after exposure and development processes. After an etching process, several layers underlying the photo resist can be defined simultaneously. In the first embodiment, the photo resist has the highest thickness on a reflective portion of the pixel region B and regions outside the gate pad region D, second highest thickness on the gate pad  140   d,  and zero thickness on the penetrating portion of the pixel region B and regions surrounding the gate pad  140   d.  Because no photo resist is on the penetrating portion of the pixel region B and regions surrounding the gate pad  104   d,  the sacrifice metal layer  140   b  on the penetrating region of the pixel region B and a portion of the first passivation layer  130  surrounding the sacrifice metal layer are removed in the etching process, at the same time, the dielectric layer  150  and the first passivation layer  130  surrounding the gate pad  140   d  are also removed to expose the gate pad  140   d.  After the etching process, the dielectric layer  150  on the gate electrode  140   a  can be used as the gate isolation layer  150   a.  The dielectric layer  150  on the capacitance line  140   c  and the scan line (not shown) can be used to protect conducting wires and to provide electrical isolation for conducting wires. 
         [0020]    In  FIG. 1E , a semiconductor layer is formed on the substrate  100 , and then a third photo-mask is used to define the semiconductor layer to form a channel region  160   a  on the dielectric layer  150  on the gate electrode  140   a.  In a preferred embodiment, the semiconductor layer comprises an amorphous silicon layer and an N-type doped amorphous silicon layer thereon. 
         [0021]    The second photo-mask of  FIG. 1D  and the third photo-mask of  FIG. 1E  can be combined as a single half-tone photo-mask. First, a dielectric layer  150  and a semiconductor layer  160  are sequentially formed on the substrate  100 . Then, a half-tone photo-mask is used to define the semiconductor layer  160 , the dielectric layer  150 , the second metal layer  140  and the first passivation layer  130  simultaneously. Therefore, the number of the photo-masks used in manufacturing the array substrate of a transflective LCD can further be reduced. After exposure and development processes, the photo resist has the highest thickness on the channel region  160   a,  second highest thickness on the gate pad  140   d,  zero thickness on the penetrating portion of the pixel region B and regions surrounding the gate pad  140   d,  and the photo resist on other regions has thickness between the thickness on the channel region  160   a  and the thickness on the gate pad  140   d.    
         [0022]    In  FIG. 1F , a third metal layer  170  is formed on the substrate  100 . Then, a fourth photo-mask is used to define the third metal layer  170  to form a source electrode  170   a,  a drain electrode  171   a,  an expanded gate pad  170   d,  a signal line (not shown) and a signal pad (not shown). The source electrode  170   a  and the drain electrode  171   a  are on two sides of the channel region  160   a.  The drain electrode  171   a  is electrically connected to the transparent conductive layer  110 . The expanded gate pad  170   d  is directly connected to the gate pad  140   d  to reduce impedance of the gate pad  140   d.  The structure of the expanded gate pad  170   d  is similar to the structure of the signal pad. Therefore, an expanded signal pad with a structure similar to the gate pad  140   d  can be selectively formed under the signal pad to reduce impedance of the signal pad. 
         [0023]    In  FIG. 1G , a second passivation layer  180  is formed on the substrate  100 . Then, the second passivation layer  180  is defined by back exposure to remove the second passivation layer  180  and the first passivation layer  130  on the penetrating portion of the pixel region B. 
       Second Embodiment 
       [0024]      FIGS. 2A-2D  are cross-section views of an array substrate of a transflective LCD in process steps according to the second embodiment. From the process step of forming the transparent conductive layer  110  to the process step of forming the dielectric layer  150 , the second embodiment is the same as the first embodiment. Therefore, the description about these process steps can be directly referred to the first embodiment. 
         [0025]    In  FIG. 2A , a second photo-mask is used to define the dielectric layer  150 , the second metal layer  140  and the first passivation layer  130  after forming the dielectric layer  150 . In this process step, the sacrifice metal layer  140   b  on the penetrating portion of the pixel region B and the dielectric layer  150  thereon are removed, at the same time, the dielectric layer  150  and the first passivation layer  130  on a side of the first storage capacitance  141  is removed to form a contact window  151 . Moreover, the dielectric layer  150  and the first passivation layer  130  surrounding the gate pad  140   d  are removed to expose the gate pad  140   d  at the same time. 
         [0026]    In  FIG. 2B , a semiconductor layer is formed after forming the contact window  151 . A third photo-mask is used to define the semiconductor layer to form a channel region  160   a  on the dielectric layer  150  on the gate electrode  140   a.  The same as the first embodiment, the second photo-mask of  FIG. 2A  and the third photo-mask of  FIG. 2B  can be combined as a single half-tone photo-mask. The half-tone photo-mask used here is very similar to the half-tone photo-mask in the first embodiment except the photo-mask of the second embodiment has a contact window pattern thereon. 
         [0027]    In  FIG. 2C , a third metal layer  170  is formed on the substrate  100 . A fourth photo-mask is used to define the third metal layer  170  to form a source electrode  170   a,  a drain electrode  171   a,  an expanded capacitance  170   c,  an expanded gate pad  170   d,  a signal line (not shown) and a signal pad (not shown). The source electrode  170   a  and the drain electrode  171   a  are on two sides of the channel region  160   a.  The drain electrode  171   a  is electrically connected to the transparent conductive layer  110 . The expanded capacitance line  170   c  is on the dielectric layer  150  on the capacitance line  140   c.  The expanded capacitance line  170   c  is electrically connected to the transparent conductive layer  110  through the contact window  151 . The expanded capacitance  170   c,  the underlying dielectric layer  150  and capacitance line  140   c  constitute a second storage capacitance  171 . The second storage capacitance  171  and the first capacitance  141  connect in series, not only the capacitance value per unit of area can be increased but also the overall area on the substrate occupied by the storage capacitance can be reduced. Moreover, the aperture rate of the penetrating region of the pixel region and the brightness of the LCD are increased. 
         [0028]    As shown in  FIG. 2D , a second passivation layer  180  on the substrate  100  is formed. The second passivation layer  180  is defined by means of back exposure, and at the same time the second passivation layer  180  and the first passivation layer  130  on the penetrating region of the pixel region B are removed. 
         [0029]    Accordingly, the present invention, as shown and described, has at least the following advantages. 
         [0030]    (1) In preferred embodiments, only three to four photo-masks are needed to manufacture a transflective LCD. Therefore, not only the production cost can be greatly reduced but also the production volume can be increased. 
         [0031]    (2) The gate pad and the expanded gate pad are directly connected to reduce impedance of the gate pad. 
         [0032]    (3) The storage capacitances connect in series, not only the capacitance value per unit of area can be increased but also the overall area on the substrate occupied by the storage capacitance can be reduced. Moreover, the aperture rate of the penetrating region of the pixel region and the brightness of the LCD are increased. 
         [0033]    The preferred embodiments of the present invention described above should not be regarded as limitations to the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the scope or spirit of the invention, as defined in the appended claims.

Technology Category: h