Patent Document

RELATED PATENT APPLICATION 
     This application is a continuation-in-part of and claims priority to commonly owned U.S. patent applications Ser. No. 12/206,122; filed Sep. 8, 2008; now U.S. Pat. No. 7,800,408; issued Sep. 21, 2010; entitled “High Speed Transient Active Pull-Up I 2 C,” by Veto Stephens and Bret Walters, and is hereby incorporated by reference herein for all purposes. 
    
    
     TECHNICAL FIELD 
     The present disclosure relates to Inter-IC (I 2 C) bus compatible devices, and more particularly, to improving I 2 C-bus protocol speed and average power consumption of I 2 C-bus compatible devices. 
     BACKGROUND 
     Interconnecting together integrated circuit (IC) devices with a simple low cost bus arrangement was desired so Royal Philips Electronics of the Netherlands developed a simple bi-directional 2-wire bus for efficient inter-IC control. This bus is called the Inter-IC or I 2 C bus. All I 2 C-bus compatible devices incorporate an on-chip interface that allows them to communicate directly with each other via the I 2 C-bus. The PC-bus uses open collector (drain) arrangements that depend on passive pull-up resistors to overcome the connected bus capacitance. Thus, charging the bus capacitance to a logic high has a time constant determined by a combination of the connected pull-up resistance and bus capacitance, e.g., RC time constant. Faster bus speeds require pull-up resistors having lower resistance for a given bus capacitance, however, lower resistance increases the average power demand of the I 2 C-bus compatible devices. The I 2 C-Bus Specifications, Version 1.0-1992, Version 2.0-1998, and Version 2.1-2000 by Royal Philips Electronics of the Netherlands are incorporated by reference herein for all purposes. 
     SUMMARY 
     What is needed is a way to increase I 2 C-bus speed while reducing average power consumption of the I 2 C-bus compatible devices when utilizing the I 2 C-bus. According to the teachings of this disclosure, an I 2 C-bus compatible device when functioning as a clock master may comprise a transient active pull-up I 2 C (“TAP-I 2 C”) module having high side driver transistors, e.g., P-channel field effect transistors (FETs), coupled between a positive supply voltage, e.g., Vdd, and respective serial data (“SDA”) and serial clock (“SCL”) lines on the I 2 C bus. The high side output driver transistors for the SDA and SCL lines are sequentially pulsed on by the TAP I 2 C module for brief periods to first precharge the capacitance of the SDA line and then precharge the capacitance of the SCL line during low to high logic level transitions. Precharging the capacitances of the I 2 C bus lines will accelerate bus transfer operations for all of the I 2 C compatible devices connected thereto on the normally open drain (resistive pull-up) I 2 C bus since the voltage level rise time during the low to high logic level transition is so much shorter when using the TAP-I 2 C pulse then just depending upon on the RC time constant of the I 2 C-bus. 
     I 2 C devices, even those not equipped with the TAP-I 2 C module enhancement would thereby be accelerated as well, even to speeds of 5-10 MHz, assuming the other devices were not speed limited due to other reasons, e.g., internal logic speed constraints. After the precharge pulse period, the output I 2 C bus driver resumes its normal open drain configuration which allows the pull-up resistor to simply maintain the voltage (charge) on the SCL and SDA lines of the I 2 C bus. 
     In addition to precharging the bus, TAP-I 2 C module may also reduce the need for additional external pull-up resistors on the SCL and SDA lines of the I 2 C bus. Because of this, the resistance value of the pull-up resistors on the SDA and SCL lines of the I 2 C bus can be increased in resistance values, thus reducing power consumption for all of the connected I 2 C-bus compatible devices. In prior technology I 2 C systems, faster data transfer applications required stronger (lower resistance value) pull-up resistors to charge the I 2 C bus lines (SDA and SCL) faster (RC time constant) which created a higher power demand during operation of the I 2 C-bus compatible devices. However, according to the teachings of this disclosure, a pull-up resistor now is merely used to maintain the logic level state, not to substantially charge the bus capacitance during a transition to a logic high. 
     According to a specific example embodiment of this disclosure, an apparatus for rapidly charging I 2 C bus lines comprises: a first time delay circuit; a second time delay circuit; an SDA line driver coupled to an SDA line of an I 2 C bus; an SCL line driver coupled to an SCL line of the I 2 C bus; wherein: the first time delay circuit generates a first pulse upon detection of an internal SDA signal at a first logic level, the first pulse having a first pulse time duration, the second time delay circuit generates a second pulse upon detection of completion of the first pulse and detection of an internal SCL signal at the first logic level, the second pulse having a second pulse time duration, the first pulse time duration is shorter than a time duration of the internal SDA signal; the second pulse time duration is shorter than a time duration of the internal SCL signal; and whereby: the SDA line driver charges the SDA line capacitance through a low impedance circuit during the first pulse time duration, and the SCL line driver charges the SCL line capacitance through a low impedance circuit during the second pulse time duration. 
     According to another specific example embodiment of this disclosure, a method for rapidly charging I 2 C bus lines comprises the steps of: generating a first pulse at a first logic level upon detection of an internal SDA signal, the first pulse having a first pulse time duration that is shorter than a time duration of the internal SDA signal; generating a second pulse at the first logic level upon detection of completion of the first pulse and detection of an internal SCL signal, the second pulse having a second pulse time duration that is shorter than a time duration of the internal SCL signal; charging SDA line capacitance of an I 2 C bus through a low impedance SDA line driver during the first pulse time duration; and charging SCL line capacitance of the I 2 C bus through a low impedance SCL line driver during the second pulse time duration. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete understanding of the present disclosure thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein: 
         FIG. 1  illustrates a schematic timing diagram of a typical I 2 C data transfer; 
         FIG. 2  illustrates a schematic diagram of an output driver not using a transient active pulse (TAP) and the resulting output logic level transition rise time waveform; 
         FIG. 3  illustrates a schematic diagram of an output driver using a transient active pulse (TAP) and the resulting output logic level transition rise time waveform, according to the teachings of this disclosure; 
         FIGS. 4A and 4B  illustrate schematic logic and timing diagrams, respectively, of an experimental test TAP-I 2 C logic circuit used for operational evaluation, according to the teachings of this disclosure; 
         FIG. 5  illustrates a voltage versus time waveform of the output logic level transition of the circuit shown in  FIG. 4A  with the TAP feature disabled; 
         FIG. 6  illustrates is a voltage versus time waveform of the output logic level transition of the circuit shown in  FIG. 4A  with the TAP feature enabled; 
         FIG. 7  illustrates a voltage versus time waveform of output logic level transitions of the circuit shown in  FIG. 4A  running at about 5 MHz with the TAP feature enabled; 
         FIG. 8  illustrates a schematic logic diagram of a pipelined SCL implementation of a TAP-I 2 C logic module, according to a specific example embodiment of this disclosure; 
         FIG. 9  illustrates a schematic timing diagram of the operation of the TAP-I 2 C logic module shown in  FIG. 8 ; 
         FIG. 10  illustrates a graph of signal rise time versus capacitive load on a signal line of the I 2 C bus when using the TAP-I 2 C logic, according to the teachings of this disclosure; 
         FIG. 11  illustrates a schematic block diagram of a TAP-I 2 C system incorporating the TAP-I 2 C logic module shown in  FIG. 8 , according to the teachings of this disclosure; and 
         FIG. 12  illustrate schematic diagrams of specific example embodiments of the selectable dual delay circuits shown in  FIG. 8 . 
     
    
    
     While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims. 
     DETAILED DESCRIPTION 
     Referring now to the drawings, the details of example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix. 
     Referring to  FIG. 1 , depicted is a schematic timing diagram of a typical I 2 C data transfer. Logic levels of the SDA line are sampled on the rising logic level edges of the SCL line. Since the I 2 C-Bus Specification specifies open collector (drain) drivers with pull-up resistors, the rising edge of a logic level change is dependent upon the resistance of the pull-up resistor and the capacitance of the SDA and SCL bus lines. 
     Referring to  FIG. 2 , depicted is a schematic diagram of an output driver not using a transient active pulse (TAP) and the resulting output logic level transition rise time waveform. This RC time constant (e.g., pull-up resistor  206  and line capacitance  208 ) controlled rise time  210  is illustrated in  FIG. 2  where the P-channel FET  202  is held in the off state at all times. 
     Referring to  FIG. 3 , depicted is a schematic diagram of an output driver using a transient active pulse (TAP) and the resulting output logic level transition rise time waveform, according to the teachings of this disclosure. When a transient active pulse (TAP)  204  is introduced to control the on time of the P-channel FET  202 , the P-channel FET  202  substantially shorts out the pull-up resistor  206  and effectively charges the capacitance  208  much faster since the on resistance (e.g., shorter RC time constant) of the P-channel FET  202  is substantially lower than the pull-up resistor  206 . The TAP  204  need only be a very short duration pulse, e.g., 24 to 42 nanoseconds, depending upon the desired data rate of the I 2 C bus. By controlling the P-channel FET  202  with the TAP  204  so as to quickly charge the capacitance  208 , I 2 C bus operating speed may be significantly increased and the I 2 C bus power usage reduce by increasing the resistance of the pull-up resistor  206  (one for the SDA line and one for the SCL line). For example, a higher resistance pull-up resistor  206  will effectively reduce the average operating power from an I 2 C compatible device sending data onto the I 2 C bus. 
     Referring to  FIGS. 4A and 4B , depicted are schematic logic and timing diagrams, respectively, of an experimental test TAP-I 2 C circuit used for operational evaluation, according to the teachings of this disclosure. A short delay circuit  302 , e.g., 40 nanoseconds, may be used to sequentially generate the TAP signals on the SDA and SCL bus lines.  FIG. 4B  shows typical timing waveforms for respective signals of the schematic logic diagram of  FIG. 4A  are shown. 
     Referring to  FIG. 5 , depicted is a voltage versus time waveform of the output logic level transition of the circuit shown in  FIG. 4A  with the TAP feature disabled. The rise time of a logic low to high transition shows a typical RC time constant gradual rise for a 400 kHz waveform on an open drain controlled bus line having a capacitance of about 100 picofarads and a pull-up resistor of about 2,000 ohms. 
     Referring to  FIG. 6 , depicted is a voltage versus time waveform of the output logic level transition of the circuit shown in  FIG. 4  with the TAP feature enabled. The rise time of a logic low to high transition as shown in  FIG. 6  is for a 400 kHz waveform on a “pseudo-open” drain controlled bus line having a capacitance of about 100 picofarads and a pull-up resistor of about 10,000 ohms, with a TAP circuit enabled for a short period of time at the beginning of a logic low to high transition. As may be readily observed, the waveform shown in  FIG. 6  has a much faster rise time then the rise time of the waveform shown in  FIG. 5 . This is because the pull-up resistor  206  is effectively shorted out for a very brief time period, eg., 50 nanoseconds, thus charging the capacitance  208  much faster then could be charged through only a pull-up resistor. After the bus line capacitance  408  has been charged, the 10,000 ohm pull-up resistor merely maintains the voltage level on the bus line. Therefore average power is reduced while faster rise times may be accomplished, according to the teachings of this disclosure. 
     Referring to  FIG. 7 , depicted is a voltage versus time waveform of output logic level transitions of the circuit shown in  FIG. 4  running at about 5 MHz with the TAP feature enabled. A TAP of about 50 nanosecond duration was used to produce the logic signal waveforms shown in  FIG. 7 , wherein the bus line capacitance  408  was about 100 picofarads and the pull-up resistor  206  was about 10,000 ohms. 
     Referring now to  FIG. 8 , depicted is a schematic logic diagram of a pipelined SCL implementation of a TAP-I 2 C logic module, according to a specific example embodiment of this disclosure. Also referring to  FIG. 9 , depicted is a schematic timing diagram of the operation of the TAP-I 2 C logic module shown in  FIG. 8 . An I 2 C input-output (I/O) logic for driving and receiving an SDA signal on the I 2 C bus is generally represented by the numeral  850 . An I 2 C input-output (I/O) logic block for driving and receiving an SCL signal on the I 2 C bus is generally represented by the numeral  852 . The SDA and SCL signals on the I 2 C bus are represented by the numerals  812  and  818 , respectively. 
     An internal SDA signal  802  is generated from the I 2 C logic (not shown) then an internal SCL signal  804  is subsequently generated from the I 2 C logic (not shown). The logic level (state) of the SDA signal  802  is determined at the time the SCL signal  804  changes logic levels (transitions states). Shown in  FIGS. 8 and 9  is an inverted internal SCL signal  804 . An SCL transition detector  854  detects when the SCL signal  804  transitions from one logic level to the other logic level (binary logic has two logic level states) and will generate a first pulse  806  having a duration shorter than the duration of the SDA signal  802 . This first pulse  806  causes the SDA TAP-I 2 C driver transistor  202  ( FIG. 3 ) to precharge the capacitance of the SDA line through the low on impedance of the driver transistor  202  when the SDA signal  812  is at a high logic level. When the SDA signal  812  is at a low logic level no precharge of the capacitance of the SDA line is necessary since the driver transistor  208  ( FIG. 3 ) is on and has a low on impedance. 
     After the SDA signal  812  I 2 C bus line has been substantially precharged to a high logic level, when appropriate, the SCL signal  818  I 2 C bus line is precharged to a high logic level by using a low on impedance driver transistor  202  controlled from the SCL I/O driver logic  852 . A transition detector  856  detects when the first pulse  806  goes from a logic high to a logic low, then a second pulse  816  is generated by the transition detector  856 . The second pulse  816  controls the pulse timing occurrence and duration during charging of the SCL signal  818  I 2 C bus line. 
     Since SDA signal  812  data is read when the SCL signal  818  transitions for a low to a high logic level, it is important that the SDA signal  812  logic level has settled to a stable logic level before the associated SCL signal  818  changes (transitions) from one logic level to the other. This is accomplished, according to the teachings of this disclosure, by “pipelining” the internal SCL signal  804  so that the SCL TAP-I 2 C driver transistor  202   b  turns on at a desired time after the TAP-I 2 C driver transistor  202   a  associated with the SDA signal  802  has turned on. 
     The length of time that the TAP-I 2 C driver transistor  202  may precharge the I 2 C bus capacitance is dependant upon the I 2 C data rate, and may be for example but is not limited to, about 24 nanoseconds (ns) or 42 ns. In the exemplary embodiment shown in  FIG. 8 , low speed, high speed and extra high speed data rates may be provided for by using the I 2 CCON&lt;XHS&gt; and I 2 CCON&lt;HS&gt; control lines for selection of either the 24 ns or 42 ns delay, respectively, and for the TAP-I 2 C pulse widths. Once the TAP-I 2 C pulse has charged the I 2 C bus line, according to the teachings of this disclosure, the normal pull-up resistor will maintain that logic level until the next logic level transition. The TAP-I 2 C logic module is compatible in operation with prior technology I 2 C devices and will enhance the operational speeds of all I 2 C devices operating on an I 2 C bus having at least one TAP-I 2 C device connected thereto. 
     The SCL transition detector  854  and the transition detector  856  both include selectable dual delay circuits  858 , e.g., 24 nanoseconds (ns) or 42 ns. Referring now to  FIG. 12 , depicted are schematic diagrams of specific example embodiments of these selectable dual delay circuits. Signal propagation delays may be implemented as shown in (a) with inherent logic gate delays by series connecting logic buffers  1204  and using a multiplexer  1202  to switch between a first or a second delay, e.g., 24 ns or 42 ns, etc. More than two selectable delays may be implemented as shown by increasing the number of inputs to the multiplexer  1202  and associated taps to the series connected logic buffers  1204 . Signal propagation delays may also be implemented with selectable resistor-capacitor (RC) time delay circuits as shown in (b). It is contemplated and within the scope of this disclosure that other delay circuit implementations would be readily apparent to one of ordinary skill in the art of digital circuit design and having the benefit of this disclosure. 
     Referring to  FIG. 10 , depicted is a graph of signal rise time versus capacitive load on a signal line of the I 2 C bus when using the TAP-I 2 C logic module, according to the teachings of this disclosure. 
     Referring to  FIG. 11 , depicted is a schematic block diagram of a TAP-I 2 C system incorporating the TAP-I 2 C logic module, according to the teachings of this disclosure. The TAP-I 2 C logic module, as shown in  FIG. 8 , is represented by the numeral  1100 , and is integrated into a TAP-I 2 C system, according to the teachings of this disclosure. 
     While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.

Technology Category: 4