Patent Document

FIELD OF THE INVENTION 
     The present application claims priority of Italian Patent Application No. TO2008A000934 filed Dec. 15, 2008, which is incorporated herein in its entirety by this reference. 
     FIELD OF THE INVENTION 
     This disclosure relates to low-dropout linear regulators (LDOs). LDOs are used in a wide variety of applications in electronics to apply to a load a signal regulated as a function of a reference signal. 
     DESCRIPTION OF THE RELATED ART 
     The diagram of  FIG. 1  is exemplary of the circuit layout of a conventional low-dropout linear regulator. The LDO of  FIG. 1  is essentially comprised of a cascaded arrangement of an error amplifier  100  (in turn including a differential amplifier  102  receiving the reference signal VREF followed by a gain stage  104 ) and an output stage  106 . The output stage  106  includes a Power MOS which receives from the gain stage  104  a voltage VGATE at its gate and applies an output voltage VOUT to a load including a resistive component Rload and a capacitive component Cload. 
     AN LDO as exemplified in  FIG. 1  may use an adaptive bias  108  in the differential amplifier  102  in order to decrease quiescent current and consequently improve efficiency for low load currents. Frequency compensation elements (such as e.g. a RC stage including a resistor R 1  and a capacitor C 1 ) are usually connected to the output of the differential amplifier  102  (voltage VO 1 ). In fact this is a high impedance node and the compensation is very effective. 
     Load transient response is a designation for the response of output voltage (VOUT) to rapid changes in the load current. Rapid changes in the load current may produces undershoots and overshoots in the output voltage VOUT. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to dispense with the undesired effects of rapid changes in a load current described above, it being noted that the claims are an integral part of the disclosure of the invention provided herein. 
     According to the present invention, such an object is achieved by means of a low-dropout linear regulator comprising (a) an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage having a frequency compensation network interposed therebetween for a loading current to flow therethrough, and (b) a current limiter inserted the flow-path of the loading current for the compensation network. 
     In one embodiment, an improvement of load transient response of a low-dropout regulator (LDO) is provided based on slew rate increase of the differential amplifier output by dispensing with the capacitive load created by the frequency compensation elements. 
     In another embodiment, the present invention is used in LDOs with an adaptively biased differential pair. 
     A method of improving load transient response in a low-dropout linear regulator which includes an error amplifier having a cascaded arrangement of a differential amplifier and a gain stage having interposed therebetween a frequency compensation network with a capacitive load, the method includes increasing the slew rate of the output of said differential amplifier by dispensing with the capacitive load during load transients in the inear regulator. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will now be described, by way of example only, with reference to the enclosed views, wherein: 
         FIG. 1  has been already described in the foregoing, 
         FIG. 2  is representative of a possible embodiment of the arrangement described herein, and 
         FIG. 3  further details the embodiment of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     In the following description, numerous specific details are given to provide a thorough understanding of embodiments. The embodiments can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments. 
     Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. 
     The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments. 
     The embodiment described herein is a proposed modification of the general layout of an LDO as illustrated in  FIG. 1 , consequently the detailed description of the embodiments described herein will not repeat those elements that are common with the arrangement of  FIG. 1 . 
     It will be otherwise understood that components/elements that are identical or equivalent are indicated with the same references. 
     Also, it will be appreciated that the embodiment described herein is applicable to any LDO layout including an error amplifier including a cascaded arrangement of a differential amplifier and a gain stage having interposed therebetween a frequency compensation network, irrespective of the constructional details of these amplifiers, stage and network. Referring to the constructional details of the LDO layout of  FIG. 1  is thus merely for exemplary, non-limiting purposes. 
     The embodiment described herein is based on the recognition that a critical point for load transient response in an LDO as portrayed in  FIG. 1  is the VO 1  output node of the error amplifier  102 . 
     The compensation capacitor C 1  connected to this node is not assumed to create any dominant pole; its capacitance is thus selected at a very small value and has not a marked influence on the bandwidth of the regulator (in a small signal model). On the other hand, the capacitor C 1  is charged by a current I C1  drawn from the output of the differential amplifier  102  and this current is limited by the bias current of the adaptive bias  108 . If the bias current is very small (a common situation if adaptive bias is used) then charging of the compensation capacitor C 1  is very slow. As a result, the slew rate of the error amplifier  102  is reduced and the load transient response (large signal) is impaired. 
     Experimentally observing the load transient response of LDO with and without adaptive bias shows that undershoot in the output voltage is much larger in the case adaptive bias is present. This may be explained by noting that, because the LDO is in low bias current state before a transition in the output current I OUT , then all responses of the regulator are slow. A more detailed analysis of undershoot shows that, after a transition in the output current I OUT , the output voltage V OUT  starts to decrease (the slope is determined by the values of I OUT  and C LOAD ). The regulation error causes an increase in the output voltage VO 1  of the differential amplifier  102 , and the speed of this increase is limited by the bias current of the differential amplifier  102  that flows into the compensation capacitor C 1  (I C1 ˜I BIAS ˜dVO 1 /dt). Since an LDO with adaptive bias starts with low bias current, the delay that appears on VO 1  causes a larger undershoot. 
     The embodiment described herein leads to an improvement of load transient by increasing the slew rate of the output of differential amplifier  102 . This can be achieved by dispensing with the influence on the output of differential amplifier  102  of the capacitive load created by frequency compensation elements. This operating principle is suitable especially for LDOs with adaptively biased differential pair. 
     It is possible to reduce the effect of the frequency compensation network during the time when the output voltage V OUT  is out of desired range of values and the regulator is in state of large regulation error. 
     As illustrated in  FIG. 2 , this result can be obtained by inserting a current limiter  200  in the path of the load current I C1  that flows through the frequency compensation network R 1 , C 1 . In that way, the compensation network R 1 , C 1  will work normally with small signals but will in fact be disconnected for large signals. 
     During a load transient process (large signal) the output of the differential amplifier (i.e. the VO 1  node) will be loaded only by a DC current defined by the current limiter  200  and by the input capacitance of the gain stage  104  (the MOSFET M 1  in the exemplary embodiment considered here). 
     Experimental analysis of the resulting load transient response indicates that, with the arrangement of  FIG. 2 , the lower capacitive load at the output of the differential amplifier  102  allows VO 1  to change much faster, while the current I C1  into the compensation network, as determined by the current limiter  200 , may be set to be much lower than the minimum bias current of the differential pair. 
     With the arrangement of  FIG. 2 , the capacitor C 1  is charged by a low current, so that charging thereof takes a time longer that the recovery time after load transient. As a result, the compensation network R 1 , C 1  is in fact kept inactive while the regulator is already in the minimum regulation error condition (with an otherwise negligible error on V OUT  due to the offset of the differential amplifier  102  caused by the current load on VO 1 ). 
     Any potential stability problems may however be overcome by charging C 1  faster and bringing the compensation network R 1 , C 1  into a normal state. This result can be achieved by using an adaptive current limiter to take into account that as the VO 1  voltage and bias current increase, the VO 1  node can be loaded by a higher current, thus speeding up the charging process of C 1 , so that the charging time of C 1  can be effectively minimized while retaining the desired load transient performance. 
       FIG. 3  (where elements/components identical or equivalent to those already described in connection with  FIGS. 1 and 2  are indicated with the same references already appearing therein) is exemplary of an embodiment of such an adaptive current limiter. Essentially, in the embodiment of  FIG. 3  a first MOSFET M 2  is coupled in common gate arrangement with the MOSFET M 1  of the gain stage  104  to perform the adaptive action (i.e. sensing the voltage and bias current increase at V 01 ), while the MOSFET M 3  operates as a buffer with limited output current capability that gradually “restores” the load current of the capacitor C 1  as the VO 1  voltage and bias current increase as sensed via the MOSFET M 2  thus speeding up the charging process of C 1 . 
     Without prejudice to the underlying principles of the invention, the details and the embodiments may vary, even appreciably, with respect to what has been described by way of example only, without departing from the scope of the invention as defined by the annexed claims.

Technology Category: 3