Patent Document

BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a maximum likelihood decoding method and a maximum likelihood decoder for obtaining original information by decoding a reproduced signal reproduced from a recording medium or a signal obtained through a transmission medium. In particular, the present invention relates to a maximum likelihood decoding method and a maximum likelihood decoder applying partial response maximum likelihood decoding. 
   2. Description of the Related Art 
   In general, a reproducing apparatus used in a data recording/reproducing technique using various recoding media includes a pickup device for reading a signal recorded in a recording medium as a reproduced signal and a decoder for decoding the reproduced signal read by the pickup device so as to obtain original binary data. 
   Also, with an increase in the recording density in such a recording/reproducing technique, a partial response maximum likelihood (PRML) decoding method, which realizes high decoding reliability, has been adapted in decoders for decoding a reproduced signal so as to obtain original recorded data. 
   The PRML technique is realized by combining a partial response method, in which data sequences are associated with predetermined levels in units of bits, and a maximum likelihood decoding method, in which a data sequence is selected from among all possible data sequences so that a reference signal generated by a partial response becomes most approximate to an actual reproduced signal. 
   That is, in the partial response method, data sequences are compiled in units of sequential bits so as to associate a possible bit pattern to a reproduced-signal level. 
   For example, data is represented by d n  and a sample generated by sampling a reproduced signal is represented by r n . n is the number of data. In this case, d n  corresponds to the input of partial response and r n  corresponds to the output of partial response. In the partial response, four sequential bits are associated with the level of the reproduced signal. 
   In order to obtain the output of partial response, the input four sequential bits are added in order by multiplying the four bits by weights a, b, b, and a, respectively. This can be represented by the following equation.
 
 r   n   =ad   n   +bd   n+1   +bd   n+2   +ad   n+3   (1)
 
This partial response is represented by PR (a b b a).
 
   On the other hand, in the maximum likelihood decoding method, all possible data sequences are converted into reference signals of a reproduced signal through a predetermined partial response. Then, from among the reference signals, a reference signal that is the most approximate to a sample sequence of an actually detected reproduced signal is selected, and then the selected reference signal is decoded. Herein, the reference signals generated from the data sequences are ideal reproduced signals without noise. 
   The maximum likelihood decoding is an algorithm for selecting a reference signal that is the most likely to be an original reference signal from among all possible data sequences, in the condition that a detected reproduced signal is a reference signal to which noise is added (conditional probability). The conditional probability is calculated based on a metric, which can be obtained by the following equation.
 
 m   n =( r˜   n   −r   n ) 2   (2)
 
   Herein, r˜ n  is a sample value of a reproduced signal detected at time n, and r n  is a sample value of a reference signal at time n. 
   In actual maximum likelihood decoding, the sum of metrics is obtained instead of the conditional probability, and a data sequence for minimizing the sum is output. Also, instead of calculating metrics of all data sequences, a data sequence is selected or not selected at each channel clock so as to determine a final data sequence. Such a data sequence searching algorithm is realized by a Viterbi algorithm. 
   The above-described PRML is effective for random noise. However, noise in a recording/reproducing channel includes not only random noise but also noise having a frequency characteristic. Accordingly, measures should be taken to control such noise. 
     FIG. 12  is a block diagram showing a recording/reproducing system of a known art and noise generated therefrom. As shown in  FIG. 12 , media noise is caused at a recording medium  12 A and system noise is caused at a pickup  12 B and a maximum likelihood decoder  12 C. The noise caused in the recording/reproducing system includes two types of noise: the system noise and the media noise. Therefore, the following equation can be obtained.
   N   total   =N   system   +N   media   (3) 
Herein, N total  represents total noise, N system  represents system noise, and N media  represents media noise.
 
   The system noise is generated from noise caused by a detector, an electrical circuit, and deviation of the level of PRML, and is usually considered to be random noise. In the known PRML, decoding which is effective for such random noise can be realized. 
   On the other hand, the media noise is considered to be caused mainly by defects of a medium, crosstalk, and fluctuation of reflectivity. In general, media noise is different from system noise, and is added to a reproduced signal through a transmission medium having a frequency characteristic. Therefore, the media noise is random noise on media, but the media noise becomes noise having a frequency characteristic and a temporal correlation in a reproduced signal. 
   For example, when media noise passes through a system for realizing the above-described PR (a b b a), if the noise at an n-th channel bit on a medium is represented by n n , noise N n  in an n-th sample of a reproduced signal is represented by the following equation.
 
 N   n   =an   n   +bn   n+1   +bn   n+2   +an   n+3   (4)
 
In this case, even if the media noise n n  itself is random noise, that media noise in the reproduced signal has an emphasized low-frequency component.
 
     FIGS. 13A and 13B  show examples of the waveforms of a signal containing media noise and a signal containing system noise. 
     FIG. 13A  shows a signal generated by adding the media noise represented by the equation (4) to the above-described equation (1). Also,  FIG. 13B  shows a signal generated by adding random noise to the equation (1). Herein, the SN ratio of media noise to a data signal is equal to the SN ratio of system noise to a reproduced signal. Also, an ideal signal without noise is indicated by a solid line. 
   By comparing the waveforms in  FIGS. 13A and 13B , it can be found that the signal with media noise maintains the original state better than the signal with system noise. This is because the media noise becomes noise having a low-frequency and is virtually offset, and as a result, a relative level can be maintained. 
   In general, noise in a recording/reproducing system is temporarily correlated noise due to the frequency characteristic of the channel, and thus the signal waveform can be maintained relatively well compared to the case where random noise of the same S/N ratio exists. 
   However, the known PRML is effective to random noise, but is not so effective to offset noise. Also, even if noise has a frequency characteristic, the characteristic cannot be used positively. 
   That is, the known PRML is not the optimal decoding method in case noise has a frequency characteristic. Accordingly, a more appropriate decoding method is required to be developed for controlling noise with a frequency characteristic. 
   The noise which is obtained after processing of partial response PR (a b b a) having a characteristic of attenuating a high-frequency band has an emphasized low-frequency component, and thus the noise is offset. As a result, the signal level is relatively maintained, as described above. 
   Accordingly, a partial response having a frequency characteristic for attenuating a low-frequency band such as a differential waveform is proposed as a partial response in which relative levels can be compared. 
   If the partial response PR (a b b a) can be realized compared to the frequency characteristic in a step of transferring data, a partial response PR (a b−a 0 a−b −a), which is a differential response between the partial response PR (a b b a) and a response shifted by 1 clock, can also be realized. 
   Further, a reproduced signal generated by the PR (a b−a 0 a−b −a) can be represented by the following equation.
 
 r   n   =a ( d   n   −d   n+4 )+( b−a )( d   n+1   −d   n+3 )   (5)
 
   The response of the equation (5) is generated by subtraction by shifting the response of PR (a b b a) by 1 clock. Therefore, if the reproduced signal can be equalized to PR (a b b a), the reproduced signal can also be equalized to PR (a b−a 0 a−b −a). 
   Accordingly, by comparing the relative level of amplitude by using a partial response obtained as a temporal difference of the above-described partial response, more effective maximum likelihood decoding can be realized. 
   However, if the noise in an n-th sample of a reproduced signal is represented by Nn, the media noise n n  obtained through partial response PR (a b−a 0 a−b −a) processing contributes like this:
 
 N   n   =a ( n   n   −n   n+4 )+( b−a )( n   n+1   −n   n+3 )   (6)
 
   Therefore, a higher frequency component is emphasized in the noise obtained through the partial response PR (a b−a 0 a−b −a), compared to the partial response PR (a b b a). 
   Also, by obtaining a difference, a high-frequency component of random noise is amplified. Therefore, maximum likelihood decoding using a partial response generated by using a temporal difference is not always more effective than maximum likelihood decoding using an original partial response. Accordingly, maximum likelihood decoding using an original partial response and maximum likelihood decoding using a partial response using a temporal difference are combined. 
   The followings are summary of the above-description.
     (1) Noise caused in a recording/reproducing system includes random system noise and non-random media noise. Therefore, PRML which is effective for the non-random noise is required.   (2) In the original partial response, a low-frequency component of media noise is emphasized, and thus the noise in a reproduced signal has many low-frequency components.   (3) By obtaining a time difference of the original partial response, noise of a low-frequency component is attenuated, while noise of a high-frequency component is emphasized.   (4) Accordingly, by developing maximum likelihood decoding using both of the original partial response and the time-differential partial response, effects can be expected.   

   SUMMARY OF THE INVENTION 
   Accordingly, it is an object of the present invention to provide a maximum likelihood decoding method and a maximum likelihood decoder which can effectively solve a problem of noise in a recording/reproducing system, including random system noise and non-random media noise. 
   In order to achieve the above-described object, according to an aspect of the present invention, a maximum likelihood decoding method for obtaining original information by decoding a reproduced signal from a recording medium or a reproduced signal obtained through a transmission medium is provided. The method includes a first-metric generating step for generating a metric of a reproduced signal generated based on a first partial response, the metric being a first metric; a second-metric generating step for generating a metric of a reproduced signal generated based on a second partial response, the metric being a second metric; and a maximum likelihood decoding step for realizing maximum likelihood decoding by using the first metric and the second metric. 
   According to another aspect of the present invention, a maximum likelihood decoder for obtaining original information by decoding a reproduced signal from a recording medium or a reproduced signal obtained through a transmission medium is provided. The maximum likelihood decoder includes a first-metric generator for generating a metric of a reproduced signal generated based on a first partial response, the metric being a first metric; a second-metric generator for generating a metric of a reproduced signal generated based on a second partial response, the metric being a second metric; and a maximum likelihood decoding unit for realizing maximum likelihood decoding by using the first metric and the second metric. 
   In the maximum likelihood decoding method and the maximum likelihood decoder of the present invention, a metric between a reproduced signal generated based on a first predetermined response and a reference value generated based on the response is generated. Also, a metric between a reproduced signal generated based on a second predetermined response and a reference value generated based on the response is generated. By using a synthetic metric generated by combining these two metrics at a predetermined ratio, maximum likelihood decoding can be realized while effectively controlling various types of noise having different characteristics. 
   For example; the first partial response has a predetermined frequency characteristic which can be realized by adjusting a frequency characteristic of a channel for generating a reproduced signal based on a data signal. The first partial response is generated by equalizing a reproduced signal, which is reproduced by transferring a data signal, by using a waveform equalizer. 
   Also, the first-metric generator generates the first metric by calculating a metric between a reproduced signal generated by equalizing a reproduced data signal to the first partial response and a reference signal obtained by inputting a data sequence which can serve as a decoded data sequence to the first partial response. 
   On the other hand, the second partial response is a differential partial response obtained by calculating a difference between the first partial response and a response generated by shifting the first partial response by 1 channel clock. 
   The second-metric generator generates the second metric by calculating a metric between a reproduced signal generated by equalizing a reproduced data signal to the second partial response and a reference signal obtained by inputting a data sequence which can serve as a decoded data sequence to the second partial response. 
   Herein, the metric is the square, absolute value, or function of a difference in an amplitude level between a sample of a reproduced signal generated by reproducing a data signal based on a predetermined partial response and a sample of a reference signal generated by using a data signal which can serve as a decoded data signal based on the partial response. 
   Further, the maximum likelihood decoding unit includes a metric synthesizer for synthesizing the first metric and the second metric at a predetermined ratio; and a Viterbi decoder for obtaining original data by using the synthetic metric by maximum likelihood decoding. The ratio of the first metric and the second metric is adjusted in accordance with the frequency characteristic of noise contained in a reproduced signal reproduced by transferring a data signal. 
   The maximum likelihood decoding unit uses a Viterbi algorithm, and a data pattern representing states which form the Viterbi algorithm includes pieces of data whose number is the same as the number of pieces of data required for generating the first partial response. 
   Also, in order to specifically realize maximum likelihood decoding, a data pattern representing states which form the Viterbi algorithm includes pieces of data whose number is smaller by one than the number of pieces of data required for generating the second partial response. Alternatively, a data pattern representing states which form the Viterbi algorithm includes pieces of data whose number is the same as the number of pieces of data required for generating the second partial response. 
   Herein, the first metric is defined to each state of Viterbi decoding, and the second metric is defined to each branch of Viterbi decoding. Alternatively, the first metric and the second metric are defined to each branch of Viterbi decoding. Alternatively, the first metric is defined to each branch of Viterbi decoding, and the second metric is defined to each state of Viterbi decoding. 
   In the Viterbi decoding for realizing maximum likelihood decoding by setting the metrics, a survival path to each state has the smallest path metric in paths to each state. Also, the path metric of a path in each state can be obtained by multiplying a metric to the first predetermined response by a predetermined constant and then adding the result to the path metric of a survival path to each state. Further, the path metric of a path in each branch can be obtained by multiplying a metric to the second predetermined response by a predetermined constant and then adding the result to the path metric of a survival path to each branch. 
   With this configuration, by performing maximum likelihood decoding by using the synthetic metric generated by combining the two metrics at a predetermined ratio, maximum likelihood decoding for decoding data effectively at a low error rate can be realized, even if noise has a temporal correlation and a specific frequency characteristic. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram showing the outline of a recorded-information reproducing apparatus to which a maximum likelihood decoding method of an embodiment of the present invention is applied; 
       FIG. 2  is a block diagram showing an example of the configuration of a maximum likelihood decoder in the recorded-information reproducing apparatus shown in  FIG. 1 ; 
       FIG. 3  is a block diagram showing an example of the configuration of a waveform equalizer in the maximum likelihood decoder shown in  FIG. 2 ; 
       FIG. 4  is a block diagram showing an example of the configuration of a first-metric generator in the maximum likelihood decoder shown in  FIG. 2 ; 
       FIG. 5  is a block diagram showing an example of the configuration of a differential-signal generator of a second-metric generator in the maximum likelihood decoder shown in  FIG. 2 ; 
       FIG. 6  is a block diagram showing an example of the configuration of a differential-reference-value generator of the second-metric generator in the maximum likelihood decoder shown in  FIG. 2 ; 
       FIG. 7  is a block diagram showing an example of the configuration of a differential-metric generator of the second-metric generator in the maximum likelihood decoder shown in  FIG. 2 ; 
       FIG. 8  is a block diagram showing an example of the configuration of a metric synthesizer in the maximum likelihood decoder shown in  FIG. 2 ; 
       FIG. 9  is a block diagram showing an example of the configuration of a path metric updating device of a Viterbi decoder in the maximum likelihood decoder shown in  FIG. 2 ; 
       FIG. 10  is a block diagram showing an example of the configuration of a path memory updating device of the Viterbi decoder in the maximum likelihood decoder shown in  FIG. 2 ; 
       FIG. 11  is a block diagram showing an example of the configuration according to a modification of the maximum likelihood decoder shown in  FIG. 2 , in which an adaptive table is used; 
       FIG. 12  is a block diagram showing noise generated in a known recording/reproducing system; and 
       FIGS. 13A and 13B  show waveforms of a signal containing media noise and a signal containing system noise of a reproduced signal in the recording/reproducing system shown in  FIG. 12 . 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Hereinafter, an embodiment of a maximum likelihood decoding method and a maximum likelihood decoder according to the present invention will be described. 
   In the embodiment, a first metric is generated based on an original partial response and a second metric is generated based on a differential response of the original partial response. Then, the two metrics are combined at a predetermined ratio so as to perform maximum likelihood decoding. 
   That is, high-frequency media noise is attenuated by the original partial response. On the other hand, low-frequency media noise is attenuated by the time-differential partial response. Accordingly, by combining the two partial responses, maximum likelihood decoding can be realized while effectively attenuating high-frequency media noise and low-frequency media noise. 
   In the embodiment, maximum likelihood decoding is realized by using a synthetic metric generated by combining the first metric obtained from the original partial response and the second metric obtained from the time-differential partial response at a predetermined ratio. Therefore, data decoding can be performed more effectively than in the known art, while solving a problem of noise in a recording/reproducing system, the noise having a temporal correlation and a frequency characteristic. 
     FIG. 1  is a block diagram showing the overview of a recorded-information reproducing apparatus to which the maximum likelihood decoding method according to the embodiment of the present invention is applied. 
   The recorded-information reproducing apparatus includes a recording medium  1 A containing information; a pickup  1 B for reading a signal recorded in the recording medium  1 A so as to obtain a reproduced signal; an AD converter  1 C which AD-converts the reproduced signal read by the pickup  1 B so as to sample the signal; and a maximum likelihood decoder  1 D for decoding sample sequences of the reproduced signal obtained from the AD converter  1 C so as to obtain data sequences. 
     FIG. 2  is a block diagram showing an example of the configuration of the above-described maximum likelihood decoder  1 D. 
   As shown in  FIG. 2 , the maximum likelihood decoder  1 D includes a waveform equalizer  2 A; a first-metric generator  2 B; a second-metric generator  2 C; a metric synthesizer  2 D; and a Viterbi decoder  2 E. 
   The reproduced signal input to the maximum likelihood decoder  1 D is first input to the waveform equalizer  2 A. The waveform equalizer  2 A outputs an equalized signal u n  which has been equalized to a predetermined target partial response PR (a b b a), and the equalized signal u n  is input to the first-metric generator  2 B and the second-metric generator  2 C. 
   The first-metric generator  2 B generates a first metric based on a first partial response and outputs the first metric. 
   The second-metric generator  2 C generates a second metric based on a second partial response and outputs the second metric. 
   The metric synthesizer  2 D receives the first metric output from the first-metric generator  2 B and the second metric output from the second-metric generator  2 C and combines the metrics at a predetermined ratio, so that a synthetic metric is output therefrom. 
   The synthetic metric output from the metric synthesizer  2 D is input to the Viterbi decoder  2 E, which decodes the synthetic metric by a Viterbi algorithm so as to output decoded bit data. 
     FIG. 3  is a block diagram showing an example of the configuration of the waveform equalizer  2 A. 
   The waveform equalizer  2 A serves as a filter including amplifiers  3 A to  3 D; flip-flops  3 E to  3 H; and an adder  31 . 
   The reproduced signal input to the waveform equalizer  2 A is delayed by 1 channel-clock by the flip-flop  3 E, is further delayed by 1 clock by the flip-flop  3 F, is further delayed by 1 clock by the flip-flop  3 G, and is further delayed by 1 clock by the flip-flop  3 H. 
   Further, the reproduced signal output from the flip-flop  3 E is amplified to −k times by the amplifier  3 A, the reproduced signal output from the flip-flop  3 F is amplified to 1+k times by the amplifier  3 B, the reproduced signal output from the flip-flop  3 G is amplified to 1+k times by the amplifier  3 C, and the reproduced signal output from the flip-flop  3 H is amplified to −k times by the amplifier  3 D. 
   The four reproduced signals are output from the amplifiers  3 A to  3 D, respectively, and are added by the adder  31 . Further, the output from the adder  31  is output from the waveform equalizer  2 A as an equalized signal. 
   Herein, k, which determines the coefficient of each of the amplifiers  3 A to  3 D, is adjusted so as to minimize the noise of the equalized signal. 
     FIG. 4  is a block diagram showing an example of the configuration of the first-metric generator  2 B. 
   The first-metric generator  2 B includes predicted sample value (reference value) registers  4 A to  4 J; metric registers  4   a  to  4   j ; and a flip-flop  4 L. 
   The equalized signal u n  input to the first-metric generator  2 B is input to the flip-flop  4 L, which delays the equalized signal u n  by 1 channel clock so as to output an equalized signal u n−1 . 
   Also, the register  4 A stores a reference value r 0000  corresponding to a data sequence 0000. The register  4 B stores a reference value r 0001  corresponding to a data sequence 0001. The register  4 C stores a reference value r 1000  corresponding to a data sequence 1000. The register  4 D stores a reference value r 1001  corresponding to a data sequence 1001. The register  4 E stores a reference value r 0011  corresponding to a data sequence 0011. The register  4 F stores a reference value r 1100  corresponding to a data sequence 1100. The register  4 G stores a reference value r 0110  corresponding to a data sequence 0110. The register  4 H stores a reference value r 0111  corresponding to a data sequence 0111. The register  4 I stores a reference value r 1110  corresponding to a data sequence 1110. The register  4 J stores a reference value r 1111  corresponding to a data sequence 1111. 
   Further, a metric ms 0000  between the equalized signal u n−1  and the reference value r 0000  is stored in the register  4   a . A metric ms 0001  between the equalized signal u n−1  and the reference value r 0001  is stored in the register  4   b . A metric ms 1000  between the equalized signal u n−1  and the reference value r 1000  is stored in the register  4   c . A metric ms 1001  between the equalized signal u n−1  and the reference value r 1001  is stored in the register  4   d . A metric ms 0011  between the equalized signal u n−1  and the reference value r 0011  is stored in the register  4   e.    
   A metric ms 1100  between the equalized signal u n−1  and the reference value r 1100  is stored in the register  4   f . A metric ms 0110  between the equalized signal u n−1  and the reference value r 0110  is stored in the register  4   g . A metric ms 0111  between the equalized signal u n−1  and the reference value r 0111  is stored in the register  4   h . A metric ms 1110  between the equalized signal u n−1  and the reference value r 1110  is stored in the register  4   i . A metric ms 1111  between the equalized signal u n−1  and the reference value r 1111  is stored in the register  4   j.    
   Adders  41  and multipliers  42  are provided between the registers  4 A and  4   a , the registers  4 B and  4   b , the registers  4 C and  4   c , the registers  4 D and  4   d , the registers  4 E and  4   e , the registers  4 F and  4   f , the registers  4 G and  4   g , the registers  4 H and  4   h , the registers  4 I and  4   i , and the registers  4 J and  4   j , respectively. 
   The adders  41  receive the equalized signal u n−1  and the reference signals r 0000 , r 0001 , r 1000 , r 1001 , r 0011 , r 1100 , r 0110 , r 0111 , r 1110 , and r 1111  obtained from the registers  4 A to  4 J, respectively, and output error signals thereof. Also, the multipliers  42  square the error signals output from the respective adders  41 , so as to output the generated signals. Absolute-value calculators may be used instead of the multipliers  42 . 
   In this way, the values in the registers  4   a  to  4   j  are output at every channel bit clock. 
     FIGS. 5 to 7  are block diagrams showing an example of the configuration of the second-metric generator  2 C. 
   The second-metric generator  2 C includes a differential-signal generator  5  shown in  FIG. 5 ; a differential-reference-value generator  6  shown in  FIG. 6 ; and a differential-metric generator  7  shown in  FIG. 7 . 
   The differential-signal generator  5  shown in  FIG. 5  includes a flip-flop  5 A and an adder  5 B. 
   The equalized signal u n  input to the differential-signal generator  5  is input to the flip-flop  5 A. The flip-flop  5 A delays the equalized signal u n  by a channel bit clock and outputs an equalized signal u n−1 . 
   The equalized signal u n  input to the differential-signal generator  5  and the delayed equalized signal u n−1  are input to the adder  5 B. The adder  5 B outputs a differential signal v n =u n −u n−1 . In this way, the reproduced signal is equalized to the partial response PR (a b−a 0 a−b −a). 
   The differential-reference-value generator  6  shown in  FIG. 6  includes registers  6 A to  6 J and registers  6   a  to  6   p.    
   The register  6 A stores the reference value r 0000 , equal to the value in the register  4 A. The register  6 B stores the reference value r 0001 , equal to the value in the register  4 B. The register  6 C stores the reference value r 1000 , equal to the value in the register  4 C. The register  6 D stores the reference value r 1001 , equal to the value in the register  4 D. The register  6 E stores the reference value r 0011 , equal to the value in the register  4 E. The register  6 F stores the reference value r 1100 , equal to the value in the register  4 F. The register  6 G stores the reference value r 0110 , equal to the value in the register  4 G. The register  6 H stores the reference value r 0111 , equal to the value in the register  4 H. The register  6 I stores the reference value r 1110 , equal to the value in the register  4 I. The register  6 J stores the reference value r 1111 , equal to the value in the register  4 J. 
   Also, adders  61  for obtaining differential reference values are provided between the registers  6 A to  6 J and the registers  6   a  to  6   p.    
   The register  6   a  stores a differential reference value d 00000 =r 0000 −r 0000 . The register  6   b  stores a differential reference value d 00001 =r 0000 −r 0001 . The register  6   c  stores a differential reference value d 00011 =r 0001 −r 0011 . The register  6   d  stores a differential reference value d 10000 =r 1000 −r 0000 . The register  6   e  stores a differential reference value d 10001 =r 1000 −r 0001 . The register  6   f  stores a differential reference value d 10011 =r 1001 −r 0011 . The register  6   g  stores a differential reference value d 00110 =r 0011 −r 0110 . The register  6   h  stores a differential reference value d 00111 =r 0011 −r 0111 . The register  6   i  stores a differential reference value d 11000 =r 1100 −r 1000 . 
   The register  6   j  stores a differential reference value d 11001 =r 1100 −r 1001 . The register  6   k  stores a differential reference value d 01100 =r 0110 −r 1100 . The register  6   l  stores a differential reference value d 01110 =r 0111 −r 1110 . The register  6   m  stores a differential reference value d 01111 =r 0111 −r 1111 . The register  6   n  stores a differential reference value d 11100 =r 1110 −r 1100 . The register  6   o  stores a differential reference value d 11110 =r 1111 −r 1110 . The register  6   p  stores a differential reference value d 11111 =r 1111 −r 1111 . 
   In this way, reference levels of the partial response PR (a b−a 0 a−b −a) are generated. 
   The differential metric generator  7  shown in  FIG. 7  includes reference-value registers  7 A to  7 P and differential metric registers  7   a  to  7   p.    
   The register  7 A stores the differential reference value d 00000  of the register  6   a . The register  7 B stores the differential reference value d 00001  of the register  6   b . The register  7 C stores the differential reference value d 00011  of the register  6   c . The register  7 D stores the differential reference value d 10000  of the register  6   d . The register  7 E stores the differential reference value d 10001  of the register  6   e . The register  7 F stores the differential reference value d 10011  of the register  6   f . The register  7 G stores the differential reference value d 00110  of the register  6   g . The register  7 H stores the differential reference value d 00111  of the register  6   h.    
   The register  7 I stores the differential reference value d 11000  of the register  6   i . The register  7 J stores the differential reference value d 11001  of the register  6   j . The register  7 K stores the differential reference value d 01100  of the register  6   k . The register  7 L stores the differential reference value d 01110  of the register  6   l . The register  7 M stores the differential reference value d 01111  of the register  6   m . The register  7 N stores the differential reference value d 11100  of the register  6   n . The register  7 O stores the differential reference value d 11110  of the register  6   o . The register  7 P stores the differential reference value d 11111  of the register  6   p.    
   Also, the register  7   a  stores a metric mb 00000  between the differential signal v n  and the differential reference value d 00000 . The register  7   b  stores a metric mb 00001  between the differential signal v n  and the differential reference value d 00001 . The register  7   c  stores a metric mb 00011  between the differential signal v n  and the differential reference value d 00011 . The register  7   d  stores a metric mb 10000  between the differential signal v n  and the differential reference value d 10000 . The register  7   e  stores a metric mb 10001  between the differential signal v n  and the differential reference value d 10001 . The register  7   f  stores a metric mb 10011  between the differential signal v n  and the differential reference value d 10011 . The register  7   g  stores a metric mb 00110  between the differential signal v n  and the differential reference value d 00110 . The register  7   h  stores a metric mb 00111  between the differential signal v n  and the differential reference value d 00111 . 
   The register  7   i  stores a metric mb 11000  between the differential signal v n  and the differential reference value d 11000 . The register  7   j  stores a metric mb 11001  between the differential signal v n  and the differential reference value d 11001 . The register  7   k  stores a metric mb 01100  between the differential signal v n  and the differential reference value d 01100 . The register  7   l  stores a metric mb 01110  between the differential signal v n  and the differential reference value d 01110 . The register  7   m  stores a metric mb 01111  between the differential signal v n  and the differential reference value d 01111 . The register  7   n  stores a metric mb 11100  between the differential signal v n  and the differential reference value d 11100 . The register  7   o  stores a metric mb 11110  between the differential signal v n  and the differential reference value d 11110 . The register  7   p  stores a metric mb 11111  between the differential signal v n  and the differential reference value d 11111 . 
   Adders  71  and multipliers  72  are provided between the registers  7 A and  7   a , the registers  7 B and  7   b , the registers  7 C and  7   c , the registers  7 D and  7   d , the registers  7 E and  7   e , the registers  7 F and  7   f , the registers  7 G and  7   g , the registers  7 H and  7   h , the registers  7 I and  7   i , the registers  7 J and  7   j , the registers  7 K and  7   k , the registers  7 L and  7   l , the registers  7 M and  7   m , the registers  7 N and  7   n , the registers  7 O and  7   o , and the registers  7 P and  7   p , respectively. 
   The adders  71  receive the differential signal v n  and the reference values d 00000 , d 00001 , d 00011 , d 10000 , d 10001 , d 10011 , d 00110 , d 00111 , d 11000 , d 11001 , d 01100 , d 01110 , d 01111 , d 11100 , d 11110 , and d 11111  in the registers  7 A to  7 P, respectively, and output error signals thereof. Also, the multipliers  72  square the error signals output from the respective adders  71  and output the generated signals. Absolute-value calculators may be used instead of the multipliers  72 . 
   In this way, the values in the registers  7   a  to  7   p  are output at every channel bit clock. 
     FIG. 8  is a block diagram showing an example of the configuration of the metric synthesizer  2 D. 
   The metric synthesizer  2 D receives 10 metrics (ms) output from the registers  4   a  to  4   j  of the first-metric generator  2 B and 16 metrics (mb) output from the registers  7   a  to  7   p  of the second-metric generator  2 C, and outputs 16 metrics (mp) obtained from registers  8 A to  8 P. 
   The first metric ms 0000  and the second metric mb 00000  are input to the register  8 A, which generates a synthetic metric mp 00000 =ms 0000 +k*mb 00000  by using a predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 0000  and the second metric mb 00001  are input to the register  8 B, which generates a synthetic metric mp 00001 =ms 0000 +k*mb 00001  by using the predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 0001  and the second metric mb 00011  are input to the register  8 C, which generates a synthetic metric mp 00011 =ms 0001 +k*mb 00011  by using the predetermined constant k as coefficient and stores the synthetic metric. 
   The first metric ms 1000  and the second metric mb 10000  are input to the register  8 D, which generates a synthetic metric mp 10000 =ms 1000 +k*mb 10000  by using the predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 1000  and the second metric mb 10001  are input to the register  8 E, which generates a synthetic metric mp 10001 =ms 1000 +k*mb 10001  by using the predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 1001  and the second metric mb 10011  are input to the register  8 F, which generates a synthetic metric mp 10011 =ms 1001 +k*mb 10011  by using the predetermined constant k as coefficient and stores the synthetic metric. 
   The first metric ms 0011  and the second metric mb 00110  are input to the register  8 G, which generates a synthetic metric mp 00110 =ms 0011 +k*mb 00110  by using the predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 0011  and the second metric mb 00111  are input to the register  8 H, which generates a synthetic metric mp 00111 =ms 0011 +k*mb 00111  by using the predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 1100  and the second metric mb 11000  are input to the register  8 I, which generates a synthetic metric mp 11000 =ms 1100 +k*mb 11000  by using the predetermined constant k as coefficient and stores the synthetic metric. 
   The first metric ms 1100  and the second metric mb 11001  are input to the register  8 J, which generates a synthetic metric mp 11001 =ms 1100 +k*mb 11001  by using the predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 0110  and the second metric mb 01100  are input to the register  8 K, which generates a synthetic metric mp 01100 =ms 0110 +k*mb 01100  by using the predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 0111  and the second metric mb 01110  are input to the register  8 L, which generates a synthetic metric mp 0110 =ms 0111 +k*mb 01110  by using the predetermined constant k as coefficient and stores the synthetic metric. 
   The first metric ms 0111  and the second metric mb 01111  are input to the register  8 M, which generates a synthetic metric mp 01111 =ms 0111 +k*mb 01111  by using the predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 1110  and the second metric mb 11100  are input to the register  8 N, which generates a synthetic metric mp 11100 =ms 1110 +k*mb 11100  by using the predetermined constant k as coefficient and stores the synthetic metric. 
   The first metric ms 1111  and the second metric mb 11110  are input to the register  8 O, which generates a synthetic metric mp 11110 =ms 1111 +k*mb 11110  by using the predetermined constant k as coefficient and stores the synthetic metric. The first metric ms 1111  and the second metric mb 11111  are input to the register  8 P, which generates a synthetic metric mp 11111 =ms 1111 +k*mb 11111  by using the predetermined constant k as coefficient and stores the synthetic metric. 
   In this way, the metric values in the registers  8 A to  8 P are output at every channel bit clock. 
     FIGS. 9 and 10  are block diagrams showing an example of the configuration of the Viterbi decoder  2 E. 
   The Viterbi decoder  2 E includes a path metric updating device  9  shown in  FIG. 9  and a path memory updating device  10  shown in  FIG. 10 . 
   As shown in  FIG. 9 , the path metric updating device  9  includes path metric registers  9 A to  9 J and  9 A′ to  9 J′ and flip-flops  9   a  to  9   j.    
   The register  9 A stores a path metric pm 0000  of a survival path in a state S 0000 . In the register  9 A′, the smaller value is selected from among path metrics pm 00000 =pm 0000 +mp 00000  and pm 10000 =pm 1000 +mp 10000  of the paths to the state S 0000 . Herein, the metrics mp 00000  and mp 10000  used for calculating the path metrics are input from the metric synthesizer  2 D. The value of the register  9 A′ is latched by the flip-flop  9   a  and is stored as the value of the register  9 A. 
   The register  9 B stores a path metric pm 0001  of a survival path in a state s 0001 . In the register  9 B′, the smaller value is selected from among path metrics pm 00001 =pm 0000 +mp 00001  and pm 10001 =pm 1000 +mp 10001  of the paths to the state S 0001 . Herein, the metrics mp 00001  and mp 10001  used for calculating the path metrics are input from the metric synthesizer  2 D. The value of the register  9 B′ is latched by the flip-flop  9   b  and is stored as the value of the register  9 B. 
   The register  9 C stores a path metric pm 1000  of a survival path in a state s 1000 . The register  9 C′ stores a path metric pm 11000 =pm 1100 +mp 11000  of the path to the state S 1000 . The metric mp 11000  used for calculating the path metric is input from the metric synthesizer  2 D. The value of the register  9 C′ is latched by the flip-flop  9   c  and is stored as the value of the register  9 C. 
   The register  9 D stores a path metric pm 1001  of a survival path in a state s 1001 . The register  9 D′ stores a path metric pm 11001 =pm 1100 +mp 11001  of the path to the state S 1001 . The metric mp 11001  used for calculating the path metric is input from the metric synthesizer  2 D. The value of the register  9 D′ is latched by the flip-flop  9   d  and is stored as the value of the register  9 D. 
   The register  9 E stores a path metric pm 0011  of a survival path in a state s 0011 . In the register  9 E′, the smaller value is selected from among path metrics pm 00011 =pm 0001 +mp 00011  and pm 10011 =pm 1001 +mp 10011  of the paths to the state S 0011 . Herein, the metrics mp 00011  and mp 10011  used for calculating the path metrics are input from the metric synthesizer  2 D. The value of the register  9 E′ is latched by the flip-flop  9   e  and is stored as the value of the register  9 E. 
   The register  9 F stores a path metric pm 1100  of a survival path in a state s 1100 . In the register  9 F′, the smaller value is selected from among path metrics pm 01100 =pm 0110 +mp 01100  and pm 11100 =pm 1110 +mp 11100  of the paths to the state S 1100 . Herein, the metrics mp 01100  and mp 11100  used for calculating the path metrics are input from the metric synthesizer  2 D. The value of the register  9 F′ is latched by the flip-flop  9   f  and is stored as the value of the register  9 F. 
   The register  9 G stores a path metric pm 0110  of a survival path in a state s 0110 . The register  9 G′ stores a path metric pm 00110 =pm 0011 +mp 00110  of the path to the state S 0110 . The metric mp 00110  used for calculating the path metric is input from the metric synthesizer  2 D. The value of the register  9 G′ is latched by the flip-flop  9   g  and is stored as the value of the register  9 G. 
   The register  9 H stores a path metric pm 0111  of a survival path in a state s 0111 . The register  9 H′ stores a path metric pm 00111 =pm 0011 +mp 00111  of the path to the state S 0111 . The metric mp 00111  used for calculating the path metric is input from the metric synthesizer  2 D. The value of the register  9 H′ is latched by the flip-flop  9   h  and is stored as the value of the register  9 H. 
   The register  9 I stores a path metric pm 1110  of a survival path in a state s 1110 . In the register  9 I′, the smaller value is selected from among path metrics pm 01110 =pm 0111 +mp 01110  and pm 11110 =pm 1111 +mp 11110  of the paths to the state S 1110 . Herein, the metrics mp 01110  and mp 11110  used for calculating the path metrics are input from the metric synthesizer  2 D. The value of the register  9 I′ is latched by the flip-flop  9   i  and is stored as the value of the register  9 I. 
   The register  9 J stores a path metric pm 1111  of a survival path in a state s 1111 . In the register  9 J′, the smaller value is selected from among path metrics pm 01111 =pm 0111 +mp 01111  and pm 11111 =pm 1111 +mp 11111  of the paths to the state S 1111 . Herein, the metrics mp 01111  and mp 11111  used for calculating the path metrics are input from the metric synthesizer  2 D. The value of the register  9 J′ is latched by the flip-flop  9   j  and is stored as the value of the register  9 J. 
   As shown in  FIG. 10 , the path memory updating device  10  includes path memory registers  10 A to  10 J and  10 A′ to  10 J′ and flip-flops  10   a  to  10   j.    
   The register  10 A stores a path memory M 0000  of the survival path in the state s 0000 . In the register  10 A′, a path memory of the path having a smaller path metric is selected from among pass memories M 0000  and M 1000  of the two paths to the state s 0000 . The selected memory value is doubled and 0 is added thereto. The value of the register  10 A′ is latched by the flip-flop  10   a  and is stored as the value of the register  10 A. 
   The register  10 B stores a path memory M 0001  of the survival path in the state s 0001 . In the register  10 B′, a path memory of the path having a smaller path metric is selected from among pass memories M 0000  and M 1000  of the two paths to the state s 0001 . The selected memory value is doubled and 0 is added thereto. The value of the register  10 B′ is latched by the flip-flop  10   b  and is stored as the value of the register  10 B. 
   The register  10 C stores a path memory M 1000  of the survival path in the state s 1000 . In the register  10 C′, a path memory M 1100  of the path to the state s 1000  is doubled and 0 is added thereto. The value of the register  10 C′ is latched by the flip-flop  10   c  and is stored as the value of the register  10 C. 
   The register  10 D stores a path memory M 1001  of the survival path in the state s 1001 . In the register  10 D′, a path memory M 1100  of the path to the state s 1001  is doubled and 1 is added thereto. The value of the register  10 D′ is latched by the flip-flop  10   d  and is stored as the value of the register  10 D. 
   The register  10 E stores a path memory M 0011  of the survival path in the state s 0011 . In the register  10 E′, a path memory of the path having a smaller path metric is selected from among pass memories M 0001  and M 1001  of the two paths to the state s 0011 . The selected memory value is doubled and 1 is added thereto. The value of the register  10 E′ is latched by the flip-flop  10   e  and is stored as the value of the register  10 E. 
   The register  10 F stores a path memory M 1100  of the survival path in the state s 1100 . In the register  10 F′, a path memory of the path having a smaller path metric is selected from among pass memories M 0110  and M 1110  of the two paths to the state s 1100 . The selected memory value is doubled and 0 is added thereto. The value of the register  10 F′ is latched by the flip-flop  10   f  and is stored as the value of the register  10 F. 
   The register  10 G stores a path memory M 0110  of the survival path in the state s 0110 . In the register  10 G′, a path memory M 0011  of the path to the state s 0110  is doubled and 0 is added thereto. The value of the register  10 G′ is latched by the flip-flop  10   g  and is stored as the value of the register  10 G. 
   The register  10 H stores a path memory M 0111  of the survival path in the state s 0111 . In the register  10 H′, a path memory M 0011  of the path to the state s 0111  is doubled and 1 is added thereto. The value of the register  10 H′ is latched by the flip-flop  10   h  and is stored as the value of the register  10 H. 
   The register  10 I stores a path memory M 1110  of the survival path in the state s 1110 . In the register  10 I′, a path memory of the path having a smaller path metric is selected from among pass memories M 0111  and M 1111  of the two paths to the state s 1110 . The selected memory value is doubled and 0 is added thereto. The value of the register  10 I′ is latched by the flip-flop  10   i  and is stored as the value of the register  10 I. 
   The register  10 J stores a path memory M 1111  of the survival path in the state s 1111 . In the register  10 J′, a path memory of the path having a smaller path metric is selected from among pass memories M 0111  and M 1111  of the two paths to the state s 1111 . The selected memory value is doubled and 1 is added thereto. The value of the register  10 J′ is latched by the flip-flop  10   j  and is stored as the value of the register  10 J. 
   The most significant bit (MSB) of any of the path memory registers  10 A′ to  10 J′ of the path memory updating device  10  is externally output as decoded data. 
   As a result, decoded bit information is output from the Viterbi decoder  2 E. 
   In the above-described embodiment, a reference value includes a 4-bit partial response. However, the reference value may include a partial response of less than 4 bits. Alternatively, the reference value may include a partial response of more than 4 bits. 
   Further, the reference values in the embodiment may be applied by a learning type table, in which a sampling level is adaptively fed back in accordance with decoded data. 
     FIG. 11  is a block diagram showing an example of the configuration of the maximum likelihood decoder  1 D in which the adaptive table is used. 
   In the decoder  1 D shown in  FIG. 11 , the waveform equalizer  2 A, the first-metric generator  2 B, the second-metric generator  2 C, the metric synthesizer  2 D, and the Viterbi decoder  2 E are common with the configuration shown in  FIG. 2 . In  FIG. 11 , however, decoded data output from the Viterbi decoder  2 E is input to adaptive level feedback units  11 A and  11 B, reference values according to the decoded data are found by the internal tables of the adaptive level feedback units  11 A and  11 B, and the reference values are fed back to the first-metric generator  2 B and the second-metric generator  2 C, respectively, so that the reference values are reflected to generation of metrics. 
   In the above-described embodiment, the present invention is applied to a reproducing system for optical-disk-type recording media. However, the present invention can be widely applied to various systems correlated with noise, such as a system for reproducing magnetic disks and a system to which similar reproduced signals are input through a network or the like. 
   As described above, according to the maximum likelihood decoding method and the maximum likelihood decoder of the present invention, a metric between a reproduced signal generated based on a first partial response and a reference value generated based on the first partial response is generated. Also, a metric between a reproduced signal generated based on a second partial response and a reference value generated based on the second partial response is generated. By using a synthetic metric generated by combining these two metrics at a predetermined ratio, maximum likelihood decoding can be realized while effectively controlling various types of noise having different characteristics.

Technology Category: g