Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention relates to electronic circuitry and, in particular, to a fully differential large swing variable gain amplifier.  
       BACKGROUND OF THE INVENTION  
       [0002]     In data communication or linear applications, it is crucial to develop circuits with high bandwidth and low jitter. Additionally, having an amplifier with variable gain allows for circuit topologies which can handle large input dynamic ranges without performance degradation. To this end, fully differential circuits are well known for realizing low jitter circuits due to their inherent common-mode rejection and supply rejection characteristics.  
         [0003]     Standard five transistor transconductor circuits have been used as differential to single ended converters (current mode logic (CML) to CMOS converters), but due to their inherent imbalances the jitter performance suffers since the current source will usually be pulled in and out of saturation. These transconductors are very simple, well understood, small, and low-power though, so it is preferable to try and use these circuits.  
       SUMMARY OF THE INVENTION  
       [0004]     A fully differential large swing variable gain amplifier circuit includes: a first 5-transistor transconductor having a common mode node; and a second 5-transistor transconductor having a common mode node coupled to the common mode node of the first 5-transistor transconductor, wherein the second 5-transistor transconductor operates 180 degrees out of phase with the first 5-transistor transconductor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     In the drawings:  
         [0006]      FIG. 1  is a circuit diagram of a preferred embodiment fully differential large swing variable gain amplifier, according to the present invention circuit;  
         [0007]      FIG. 2  is the same as the circuit of  FIG. 1 , except the cross coupling nodes are changed to the output nodes;  
         [0008]      FIG. 3  is the same as the circuit of  FIG. 1 , except that the gates of the cross coupling devices are pulled out as separate bias nodes;  
         [0009]      FIG. 4  is the same as the circuit of  FIG. 2 , except that the gates of the cross coupling devices are pulled out as separate bias nodes.  
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0010]     The present invention solves the problems noted above and gives the added benefit of gain control and large output swings. By setting two 5 transistor transconductors in a single circuit sharing the common mode node and running them 180 degrees out of phase, we can achieve a balanced function which leaves the current source in saturation under all conditions. Thus we have a low power circuit with good jitter performance and large output swings. Further, by either cross-coupling the PMOS loads or by using an externally generated reference, the forward gain can be either increased or decreased giving added functionality.  
         [0011]     The circuit in  FIG. 1  is a preferred embodiment fully differential large swing variable gain amplifier, according to the present invention. The circuit can be functionally viewed as two five transistor transconductors which share a bias current source (transistor MN 21  coupled to source voltage VSS). The first transconductor is composed of transistors MN 18 , MN 19 , MP 14 , and MP 15  while the second transconductor is composed of transistors MN 262 , MN 266 , MP 73 , and MP 74 . These two transconductor circuits are operated 180 degrees out of phase (by differential inputs IN and IP) to form a balanced, fully-differential, high gain, large output swing amplifier. Transistors MP 29  and MP 30  are used as cross-coupled loads. Cross coupling in the fashion shown in  FIG. 1  serves to increase the gain in a fixed ratio fashion where the gain increase is determined by the ratio of transistors MP 29  to MP 14  and MP 30  to MP 74 .  
         [0012]     Transistor MN 21  sets a fixed bias current for the circuit. The amount of current is user selectable and is controlled through the gate connection to transistor MN 21  at node VBIASN. The drain of MN 21  forms the common mode node needed for proper differential functionality of the two circuits.  
         [0013]     Two differential pairs are formed by transistor pairs MN 18 /MN 19  and MN 262 /MN 266  respectively. Current mirror pairs are formed by transistor pairs MP 14 /MP 15  and MP 73 /MP 74  respectively. Circuit operation is as follows, the logic value of output node OP follows input node IP and output node ON follows input node IN. When node IP is ‘high’ and node IN is ‘low’, the bias current provided by the current source flows in transistors MN 266 /MP 74  and MN 19 . No current is flowing in transistors MN 18 /MP 14  and MN 262 . The result is that the current flowing through transistor MP 74  is mirrored to transistor MP 73 . Since node IN is ‘low’ no current is flowing in transistor MN 262 , therefore current flows through transistor MP 73  long enough to pull output node OP ‘high’ or to source voltage VDD. Similarly, no current is flowing in transistors MN 18 /MP 14  since node IN is ‘low’, therefore current flows through transistor MP 19  long enough to pull node ON ‘low’ or to the common mode voltage at node CM. For this circuit, ‘low’ is defined as the voltage on the common mode node CM defined by the drain of transistor MN 21  and the sources of transistors MN 18 /MN 19 /MN 262 /MN 266 .  
         [0014]     Additionally as current begins flowing through transistor MP 74  during a switching event, this current is mirrored through transistor MP 30 . As the current in transistor MP 30  increases it draws remaining current out of transistor MN 18 . This ‘steals’ some of the current that would normally be flowing into transistor MP 14  thereby shutting off transistors MP 14  and MP 15  more quickly. This is how the gain is increased by this configuration.  
         [0015]     After the circuit stabilizes, all the bias current sourced by transistor MN 21  is flowing through the leg containing transistors MN 266 /MP 74 . This function keeps the current flowing properly through the current source.  
         [0016]     When node IP switches to ‘low’ and thus node IN switches to ‘high’, the bias current begins to flow through transistors MN 18 /MP 14  and MN 262 . Current is being shut off in transistors MN 19  and MN 266 /MP 74 . Therefore the current in transistor MP 14  is being mirrored to transistor MP 15 . This pulls output node ON ‘high’. Similarly, the current through transistor MP 73  is cut off so that the current flows through transistor MN 262  long enough to pull node OP ‘low’ or to the common mode node voltage. Similarly, the cross coupled device MP 29  begins to draw current and the current rapidly switches state.  
         [0017]     After the circuit stabilizes, all the bias current sourced by transistor MN 21  is flowing through the leg containing transistors MN 18 /MP 14 . This function keeps the current flowing properly through the current source.  
         [0018]     The circuit of  FIG. 2  is the same as the circuit of  FIG. 1 , except the cross coupling nodes are changed to the output nodes. This configuration acts as an attenuator amplifier. Note that as node IP goes high, current begins flowing in transistors MN 19  and MP 30 . The gain reduction will be a ratio of transconductances between transistors MN 19  and MP 30 . The same function exists between transistors MN 262  and MP 29  as node IN goes high.  
         [0019]     Lastly, the circuits in  FIGS. 3 and 4  are the same circuits depicted in  FIGS. 1 and 2 , respectively, except that the gates of the cross coupling devices MP 29  and MP 30  are pulled out as separate nodes VB 1  and VB 2 . These are generic depictions of the circuits being proposed.  FIGS. 1 and 2  show specific implementations where fixed ratios of devices are implemented.  FIGS. 3 and 4  allow for infinite tuning ranges which is the most generic implementation for these circuits.  
         [0020]     The problems solved by this circuit are: 
    1. Figuring out a way to keep the current flowing through the current source without interruption. This increases the bandwidth and improves jitter performance.     2. Keeping the circuit in fully differential operation to take advantage of common mode rejection and power supply rejection.     3. Maintaining large output swings while achieving the above. Output swings from common mode to source voltage VDD.     4. Introducing cross-coupled devices in two effective configurations to give the circuit variable gain capabilities.    
 
         [0025]     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Technology Category: h