Patent Document

FIELD 
     Certain embodiments of the disclosure relate to page programming sequences and assignment schemes for a memory device. 
     BACKGROUND 
     Resistive RAMs (ReRAMs) have emerged as leading candidates to displace conventional Flash memories due to their high density, good scalability, low power and high performance. Previous ReRAM designs demonstrating high performance have done so on low density arrays (such as those less than one Gigabit) while those reporting high-density arrays (such as greater than eight Gigabits) were accompanied by relatively low read and write performance. 
       FIG. 1  illustrates an exemplary embodiment of ReRAM array architecture of a memory device  100 . Each chip may comprise several memory blocks.  FIG. 1  illustrates memory block  102 , comprising memory banks  104 . Each memory bank comprises Y-strips  106 , or vertical groups of tiles with a common global bitline (CBL). The Y-strip  108  comprises sixteen tiles and one redundant tile, where each tile is a matrix of 8,192 by 256 local bitlines and 2,048 wordlines. The tile  110  comprises 4 subtiles. During a sense operation and a program operation in a bank, 8 tiles (one per Y-strip) are activated simultaneously, each accessing a sub-page for a total sense/program concurrency of 512+16 cells. Since the page size is four times the number of sense/program circuits, there are 4 nibbles, where a nibble is defined as serial accesses to successive bitline addresses during the sense and program sequence performed by the sense and program circuits  112 . The complete sense/program unit is a page of 8 sub-pages. 
     However, during the program operation performed by the sense and program circuits  112 , if a page of a sub-tile is activated, the current applied to perform the operation may cause a thermal disturbance to memory cells in neighboring pages, increasing the temperature of the memory cells in the neighboring pages. While program operations can be performed on these neighboring pages, performance (number of verify loops) and reliability (data retention) are significantly degraded by the temperature increase. Consequently, a period of time elapses, generally, before operations are performed on the neighboring pages, thus increasing the program operation time. 
     Therefore, there is a need in the art for page programming sequences and assignments in memory devices that reduce program operation time in accordance with exemplary embodiments of the present invention. 
     SUMMARY 
     Page programming sequences and assignment schemes for a memory device are provided as set forth more completely in the claims. 
     These and other features and advantages of the present disclosure may be appreciated from a review of the following detailed description of the present disclosure, along with the accompanying figures in which like reference numerals refer to like parts throughout. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts an exemplary array architecture for ReRAM in accordance with exemplary embodiments of the present invention; 
         FIG. 2  depicts the column select circuit for a single sub-tile in a memory tile in accordance with exemplary embodiments of the present invention; 
         FIG. 3  depicts an addressing sequence for performing operations on memory cells using the column select circuit depicted in  FIG. 2  in accordance with exemplary embodiments of the present invention; 
         FIG. 4  depicts an addressing sequence for performing operations on the memory cells using the column select circuit depicted in  FIG. 2  for page assignment in the X direction in accordance with exemplary embodiments of the present invention; 
         FIG. 5  depicts an addressing sequence for performing operations on the memory cells using the column select circuit depicted in  FIG. 2  for page assignment in the Y direction in accordance with exemplary embodiments of the present invention; 
         FIG. 6  depicts another embodiment of a column select circuit for single sub-tile in a memory tile in accordance with exemplary embodiments of the present invention; and 
         FIG. 7  depicts an addressing sequence for performing operations on the memory cells using the column select circuit depicted in  FIG. 6  in accordance with exemplary embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain implementations of the invention may be found in several program operation sequences and addressing for a memory device. According to one embodiment, program (or, set) operations are performed on pages of the memory device by skipping adjacent pages. For example, the pulse issued by the sense and program circuit will control a column select circuit so that every other page is programmed sequentially, as opposed to adjacent pages being programmed sequentially. Accordingly, no thermal disturbance will be observed in the adjacent pages because the set operation is not applied until after the cells within the page have cooled. Similarly, other embodiments of the present invention modify the column select circuit such that a page is formed using non-adjacent cells. 
       FIG. 2  depicts the column select circuit  201  for a single sub-tile  111  in the memory tile  110  in accordance with exemplary embodiments of the present invention. 
     Sub-tile  111  comprises a finite number of wordlines; those shown in  FIG. 2  include  200   n− 2 to  200   n+ 1 (collectively, wordlines  200 ). Those of ordinary skill in the art will recognize that each subtile may contain many wordlines to access a variety of different cells on the memory device. The sub-tile  111  comprises a plurality of memory cells, the cells aggregated into eight “pages” p 0  to p 7 . The sense and program circuit  112  issues pulses to perform operations such as programming memory cells, sensing the value stored in memory cells and the like. The pulses are issued to the various memory cells via the common bit line (CBL)  202 . The column select circuit  201  comprises a level one select (I 1   y ) and a level 2 select (I 2   y ). The CBL  202  is coupled to the I 2   y  column selects respectively via switches  204 - 0  to  204 - 3 . The wordlines  200  select a “row” of cells. The level 2 select (I 2   y ) selects a group of four cells (one page) while the level 1 select (I 1   y ) selects a particular cell. For example, an operation on the first cell of page p 0  will be performed if wordline  200   n+ 1 is selected, I 2   y&lt; 0&gt; is selected and I 1   y&lt; 0&gt; is selected. Similarly, an operation on the first cell of page p 1  will be performed if wordline  200   n+ 1 is selected, and I 2   y&lt; 1&gt; and I 1   y&lt; 1&gt; are selected. 
     However, if the set of cells in page p 0  are programmed (i.e., set to a value), a thermal disturbance may be caused to cells in adjacent pages p 4  and p 1 . Similarly, if the cells in page p 1  are programmed, a thermal disturbance may be caused to cells in adjacent pages p 0 , p 5  and p 6 . To avoid such a thermal disturbance, the addressing sequences shown in  FIG. 3  are employed. 
       FIG. 3  depicts an addressing sequence for performing operations on memory cells using the column select circuit depicted in  FIG. 2  in accordance with exemplary embodiments of the present invention. 
     During the reset operation depicted in diagram  300 , at a time t 0  to t 4 , wordline n is selected, while the level 2 column select (I 2   y ) sequentially selects I 2   y &lt;0&gt; to I 2   y &lt;3&gt;, respectively, at times t 0 , t 1 , t 2  and t 3 . I 1   y &lt;0&gt; remains selected from time t 0  to t 4 . The common source line (CSL) is set to Vss, while the CBL is raised to a voltage required for a reset operation, Vreset, to select the first memory cell from each page p 0 . After time t 4 , the next wordline (e.g.,  200   n+ 1) is selected and the next level 1 column select is selected (e.g., I 1   y &lt;1&gt; to I 1   y &lt;3&gt;) and so on until all the required cells are programmed, reset or sensed. Effectively, by modifying conventional addressing methods, a new page is formed using the first memory cells in page p 0  to p 4 . Similarly, a second page is formed using the second memory cells in page p 0  to p 4 , and so on. 
     During a set operation depicted in diagram  320 , wordline n is selected from time t 0  to t 4 . Similarly, I 2   y&lt; 0&gt; to I 2   y &lt;3&gt; are sequentially selected respectively at times t 0  to t 3 , while I 1   y &lt;0&gt; is selected from time t 0  to t 4  by raising the common bit line. At time t 0 , the CSL is raised to Vset (the voltage required to perform the set operation), while the CBL is raised to Vset or lowered from Vset to select each I 2   y  select depending on its current value. The sequential selection of I 2   y &lt;0&gt; to I 2   y &lt;3&gt; while selecting I 1   y &lt;0&gt; results in a set operation being performed on each of the memory cells in p 4  to p 7 . Effectively, by modifying conventional addressing methods, a new page is formed using the first memory cells in page p 4  to p 7 . Similarly, a second page is formed using the second memory cells in page p 4  to p 7 , a third page is formed using the third memory cells in page p 4  to p 7 , and so on. 
       FIG. 4  depicts an addressing sequence for performing operations on the memory cells using the column select circuit depicted in  FIG. 2  for page assignment in the X direction in accordance with exemplary embodiments of the present invention. In the addressing sequence shown in  FIG. 4 , an assumption is made that pages and memory cells neighboring each other in the “X-Direction”, e.g. between cells sharing a wordline, is negligible. 
     In the reset operation depicted in diagram  400 , at time t 0 , wordline  200   n , I 2   y &lt;0&gt; and I 1   y &lt;0&gt; are selected. CSL remains at Vss, while CBL is raised to Vreset. From time t 0  to t 1 , time t 1  to t 2 , t 2  to t 3 , and t 3  to t 4 , I 1   y &lt;0&gt; to I 1   y&lt; 3&gt; are sequentially selected. CBL initially is at Vss, but is raised after time t 0  to Vreset and lowered back to set for each I 1   y &lt;0&gt; to I 1   y&lt; 3&gt; selection. Effectively, each cell in each of pages p 0  to p 7  is selected sequentially and a reset operation is performed sequentially. Those of ordinary skill in the art will recognize that thermal disturbance is negligible in the X-direction (e.g., among those cells sharing a wordline). 
     In the set operation depicted in diagram  420 , at time t 0 , wordline n, I 2   y &lt;0&gt; and I 1   y &lt;0&gt; are selected. CSL goes to Vset, while CBL is raised to Vset. From time t 0  to t 1 , time t 1  to t 2 , t 2  to t 3 , and t 3  to t 4 , I 1   y &lt;0&gt; to I 1   y&lt; 3&gt; are sequentially selected. CBL is lowered after time t 0  to Vss and then raised to Vset for each I 1   y &lt;0&gt; to I 1   y&lt; 3&gt; selection. Effectively, each cell in each of pages p 0  to p 7  is selected sequentially and a set operation is performed sequentially. 
       FIG. 5  depicts an addressing sequence for performing operations on the memory cells using the column select circuit depicted in  FIG. 2  for page assignment in the Y direction in accordance with exemplary embodiments of the present invention. In the addressing sequence shown in  FIG. 5 , an assumption is made that pages and memory cells neighboring each other in the “Y-Direction”, e.g. between cells sharing a bitline, is negligible. 
     In the reset operation depicted in diagram  500 , at time t 0 , wordline n, I 2   y &lt;0&gt; and I 1   y &lt;0&gt; are selected. CSL remains at Vss, while CBL is raised to Vreset shortly after time t 0 . From time t 0  to t 1 , time t 1  to t 2 , t 2  to t 3 , and t 3  to t 4 , I 2   y &lt;0&gt; to I 2   y &lt;3&gt; are sequentially selected. At time t 4  to time t 8 , wordline n+1 is selected. From time t 4  to t 5 , time t 5  to t 6 , t 6  to t 7 , and t 7  to t 8 , I 2   y &lt;0&gt; to I 2   y &lt;3&gt; are sequentially selected. CBL is lowered after time t 0  from Vset to Vss and then raised to Vset for each between each time interval t 0  to t 1 , t 1  to t 2 , t 3  to t 4  and so on. Effectively, a first page is formed by addressing the first memory cells in each of pages p 0  to p 7 . 
     Similarly, in the set operation depicted in diagram  520 , at time t 0 , wordline  0 , I 2   y&lt; 0&gt; and I 1   y&lt; 0&gt; are selected. CSL goes to Vset at time t 0 , while CBL is raised to Vset at time t 0 . At time t 0  to time t 4 , wordline n is selected. From time t 0  to t 1 , time t 1  to t 2 , t 2  to t 3 , and t 3  to t 4 , I 2   y &lt;0&gt; to I 2   y &lt;3&gt; are sequentially selected. At time t 4  to time t 8 , wordline n+1 is selected. From time t 4  to t 5 , time t 5  to t 6 , t 6  to t 7 , and t 7  to t 8 , I 2   y&lt; 0&gt; to I 2   y &lt;3&gt; are sequentially selected. CBL is lowered after time t 0  from Vset to Vss and then raised to Vset prior to t 1 , for each time interval t 0  to t 1 , t 1  to t 2 , t 3  to t 4  and so on. Effectively, a first page is formed by addressing the first memory cells in each of pages p 0  to p 7  without modifying the circuit. 
       FIG. 6  depicts another embodiment of a column select circuit  601  for a single sub-tile  111  in a memory tile  110  in accordance with exemplary embodiments of the present invention. 
     Sub-tile  111  comprises a finite number of wordlines; those shown in  FIG. 6  include  600   n− 2 to  600   n+ 1 (collectively, wordlines  600 ). Those of ordinary skill in the art will recognize that each subtile may contain many wordlines to access a variety of different cells on the memory device. The sub-tile  111  comprises a plurality of memory cells, the cells aggregated into eight (for example) “pages” p 0  to p 7 . The sense and program circuit  112  issues pulses to perform operations such as programming memory cells, sensing the value stored in memory cells and the like. The pulses are issued to the various memory cells via the common bit line (CBL) 602. The column select circuit  601  comprises a level one select (I 1   y ) and a level 2 select (I 2   y ). The CBL  602  is coupled to the I 2   y  column selects respectively via switches  604 - 0  to  604 - 3 . The wordlines  600  select a “row” of cells. The level 2 select (I 2   y ) selects a group of four cells (one page) while the level 1 select (I 1   y ) selects a particular cell. For example, an operation on the first cell of page p 0  will be performed if wordline  600   n+ 1 is selected, I 2   y &lt;0&gt; is selected and I 1   y &lt;0&gt; is selected. Similarly, an operation on the first cell of page p 1  will be performed if wordline  600   n+ 1 is selected, and I 2   y&lt; 1&gt; and I 1   y&lt; 0&gt; are selected. 
     Column select circuit  601  differs from column select circuit  201  in that each I 2   y  selects non-adjacent memory cells. For example, the memory cells associated with page  0  are now located 3 cells away from each other, where in  FIG. 2  the memory cells for page  0  were directly adjacent to each other. 
     Accordingly, the addressing performed by the sense &amp; program circuit  112  is a conventional addressing shown in  FIG. 7 , as the circuit  601  is modified. 
       FIG. 7  depicts an addressing sequence for performing operations on the memory cells using the column select circuit depicted in  FIG. 6  in accordance with exemplary embodiments of the present invention. 
     In diagram  700  of a reset operation, at time t 0  to time t 4 , wordline n and I 2   y&lt; 0&gt; are selected. The level 1 column select I 1   y  sequentially selects I 1   y&lt; 0&gt; at time t 0 , I 1   y&lt; 1&gt; at time t 1 , I 1   y&lt; 2&gt; at time t 2 , and I 1   y&lt; 3&gt; at time t 3 . CSL remains at Vss, while CBL  602  goes to Vreset after time t 0  and drops to Vss before time t 1 , and similarly for time t 1  to t 2 , t 2  to t 3  and t 3  to t 4 . 
     In diagram  700  of a reset operation, at time t 0  to time t 4 , wordline n and I 2   y&lt; 0&gt; are selected. The level 1 column select I 1   y  sequentially selects I 1   y&lt; 0&gt; at time t 0 , I 1   y&lt; 1&gt; at time t 1 , I 1   y&lt; 2&gt; at time t 2 , and I 1   y&lt; 3&gt; at time t 3 . CSL goes to Vset at time t 0 , while CBL  602  goes to Vset at time t 0  and drops to Vss shortly after time  0 , and returns to Vset before time t 1 , and similarly for time t 1  to t 2 , t 2  to t 3  and t 3  to t 4 . Effectively, every fourth bit is selected to form a page to avoid thermal disturbance of adjacent pages. 
     While the present disclosure has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, it is intended that the present disclosure not be limited to the particular embodiment disclosed, but that the present disclosure will include all embodiments falling within the scope of the appended claims.

Technology Category: 3