Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention relates to power converters with means, devices and apparatus for adjusting power factor. More specifically, although of course not solely limited thereto, the present invention relates to a single stage power factor corrected power converter (SSPFC).  
       BACKGROUND OF THE INVENTION  
       [0002]     Power converters, for example, AC/DC converters, are usually equipped with power factor correction means or circuits. An intermediate storage capacitor is typically used to provide the necessary power factor correction or adjustment. However, the intermediate storage capacitor for power factor correction is usually subject to a high voltage stress as the voltage of the intermediate storage capacitor is usually left uncontrolled and can vary widely with respect to the line voltage and the load current. Consequently, the storage capacitor voltage can be substantially higher than the peak line voltage.  
         [0003]     For example, while the ordinary line input voltage ranges from 90 to 265 Vrms, the voltage across the intermediate storage capacitor can vary between 140V to 2500V. If the DC/DC regulator stage operates in the continuous conduction mode (“CCM”) and at a decreasing load, the storage capacitor voltage can go up even higher due to power imbalance between the input and output.  
         [0004]     As a result, a bulkier storage capacitor with a higher voltage rating as well as other high-voltage-rating devices (such as power switches and diodes) which inevitably lead to an increase of the size and the total costs will have to be used.  
         [0005]     Furthermore, as single-stage power-factor-corrected converters (SSPFC) aiming at reducing the cost and simplifying the power stages and control of the converter have been developed by integrating a power factor correction (PFC) circuit with a DC/DC regulator circuit and is becoming more useful, there is therefore an urging need to devise improved power factor corrected power converters so that the demand on the voltage rating of the intermediate storage capacitor can be lessened so that a less bulky storage capacitor with a lower voltage rating can be used.  
         [0006]     In order to alleviate the above problems, various schemes and methodologies such as the use of variable frequency control, bus voltage feedback control and series-charging-parallel-discharging techniques have been reported. In addition, it has been suggested to alleviate the problems by inserting a direct power transfer path to the input stage of a converter to raise conversion efficiency and to lower the voltage stress on the storage capacitor. However, the large storage capacitor voltage swing due to line voltage variation remains a largely unresolved problem. In particular, the voltage across the storage capacitor of the known power-factor-corrected power converters always exceed the peak line input voltage due to the presence of a boost converter in such topologies which inevitably steps up the voltage across the storage capacitor. Garcia et al in “ AC/DC Converters with tight output voltage regulation and with a single control loop,” in IEEE Power Electronics Specialists Conf.,  1999, pp. 1098-1104, and Lazaro et al, in “ New family of single - stage PFC converters with series inductance interval,” in IEEE Power Electronics Specialists Conf,  200, pp. 1357-1362 attempted to reduce the storage capacitor voltage below the peak line voltage by using flyback-buckboost and flyback-boost converters respectively. However, such converters require two switches and are less attractive for low-power applications.  
       OBJECT OF THE INVENTION  
       [0007]     Hence, it is an object of the present invention to provide power-factor-corrected converters with a less stringent demand on the voltage rating of the intermediate storage capacitor so that a less bulky storage capacitor can be utilized for power factor correction. At a minimum, it is an object of the present invention to provide the public with a useful choice of power-factor-corrected converters and circuit topologies and schemes for PFC converters.  
       SUMMARY OF THE INVENTION  
       [0008]     According to the present invention, there is provided A power converter for operating with an alternate current power source, including a storage capacitive means and a transformer, said storage capacitive means being adapted for power factor correction, said transformer including an input for connecting to an alternating current power source and at least a first output and a second output respectively for connecting to said storage capacitive means and the load, said transformer including input windings, first output windings and second output windings which are respectively connected to said input, said first and second outputs wherein said transformer and said storage capacitive means being adapted that the voltage across said storage capacitive means being related to the voltage of said first output of said transformer.  
         [0009]     According to a second aspect of the present invention, there is provided a single-stage power-factor-corrected power converter including a dual-output flyback transformer, an intermediate storage capacitor, an electronic switching means and an output transformer for coupling power to a load, said intermediate storage capacitor being adapted for power factor correction, said flyback transformer including an input for connecting to an alternate current power source and at least a first output and a second output respectively for connecting to said storage capacitive means and the load, said transformer including input windings, first output windings and second output windings respectively connected to said input and said first and second outputs, said first output windings of said flyback transformer and said intermediate storage capacitor being both connected to said electronic switching means, said second output windings of said flyback transfer being connected to the output of said power connection.  
         [0010]     Preferably, the windings in association with said input and first output terminals of said transformer being adapted that the voltage across said storage capacitive means does not exceed the voltage appearing at said input terminal during normal operation.  
         [0011]     Preferably, said input windings and said first output windings being in series connection with a common switching means, said storage capacitive means be charged and discharged when said switching means being turned on and off.  
         [0012]     Preferably, an electronic switching means being connected simultaneously to first and second circuit loops which respectively contain the input windings of said input terminal and first output windings of said first output terminal of said transformer, wherein, during normal operation when said switching means being in the “on” state, said storage capacitive means being charged up and, when said switching means being in the “off” state, the energy stored in said capacitive storage means being transferred to a load.  
         [0013]     Preferably, during normal operation, the voltage across said storage capacitive means being tied to the output voltage of said second output of said transformer.  
         [0014]     Preferably, the voltage of said storage capacitive means being generally proportional to the output voltage of said second output of said transformer.  
         [0015]     Preferably, the ratio between the voltage across said capacitive means and the output voltage of said second output of said transformer being proportional to the turns ratio between the number of windings.  
         [0016]     Preferably, said transformer being configured as a flyback transformer. 
     
    
     BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]     Preferred embodiments of the present invention will be explained in further detail below by way of examples and with reference to the accompanying drawings, in which:  
         [0018]      FIG. 1  shows a schematic circuit diagram of single-switch flyback power-factor-corrected AC/DC power converter (SSPFC) as an example of a preferred embodiment of the present invention,  
         [0019]      FIG. 2  shows an operation and timing diagram of the SSPFC of  FIG. 1  in a line cycle,  
         [0020]      FIG. 3  shows the more salient switching waveforms of T 1  primary and secondary currents within a switching period T S  at different modes,  
         [0021]      FIGS. 4   a  and  4   b  respectively show the measured storage capacitor voltage V B  (upper), line input voltage (middle) and current (lower) at 90 Vrms and different output power (time base+5 ms/div).  
         [0022]      FIG. 5  is a graph showing the measured storage capacitor voltage V B  versus output power at different V in ,  
         [0023]      FIG. 6  is a graph showing the comparison of V B  against V in  on different converter topologies. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0024]     In the description below, a preferred embodiment of a power-factor-corrected power converter will be explained in more detail by reference to the circuitry of a single-stage power-factor-corrected power converter (SSPFC). The power-factor-corrected power converter includes a dual-output transformer, which is configured as a dual-output flyback transformer T 1 , a storage capacitive means which is an intermediate storage capacitor C B  in the present example, an electronic switching means S 1  which is a MOSFET switch in the present example and an isolating output transformer T 2 . The dual-output flyback transformer T 1  includes an input, a first output and a second output which are respectively connected to input windings, first output windings and second output windings respectively with the respective winding ratios 1:n1:n3.  
         [0025]     The transformer T 1  is configured in a flyback topology so that the transformer can simultaneously serve as a filter, a power transferring transformer and a storage element which at the same time provides circuit isolation between the input and the output. This flyback topology is in contrast to the forward topology in which the transformer only serves to transfer power and to provide isolation between the input and the outputs. In the forward transformer configuration, an additional inductor is required to implement the filter and storage functions. Furthermore, the flyback transformer topology has the further benefit of accepting a wider range of input voltage because it can either step up or step down the input voltage while the forward transformer topology is generally for stepping down input voltage. In this example, flyback transformer is used as a preferred example.  
         [0026]     The intermediate storage capacitor C B  is used primarily for buffering the power imbalance between the alternating current (AC) input power and the output power. That is, when the AC input power is less than the output power, the storage capacitor means, namely, the intermediate storage capacitor C B  in the present example, will deliver the extra energy required to maintain a substantially constant output power. On the other hand, the intermediate storage capacitor C B  will store excess energy when the input power exceeds the output power. In addition, the intermediate storage capacitor C B  is also adapted to provide a sufficient hold-up time for the power supply to maintain a short period of power output when the input is cut off momentarily.  
         [0027]     Hence, the transformer and the intermediate storage capacitor co-operate as the primary components to achieve power factor correction as well as controlled output voltage regulation as to be described below.  
         [0028]     An electronically controllable switching device, such as, for example, a MOSFET, an IGBT or other appropriate switching devices is included to enable the alternative power charging on the intermediate storage capacitor and power output to the load. In this specific configuration, the two switching terminals of the switching device S 1  are connected in series to the input winding and the first output of the dual-output flyback transformer. As can be seen from the schematic circuit diagram of  FIG. 1 , the switching means S 1  is included in a loop containing the first output winding of the dual-output transformer, a diode D 2 , windings L P2  of the output transformer and another diode D 1 . In addition, it also forms part of the loop containing the intermediate storage capacitor C B , the diode D 2  and the winding L P2 . Furthermore, the switching device also forms part of the loop containing the input windings of the flyback transformer T 1  and the power source.  
         [0029]     As can be noted from the circuit diagram, the input of the input windings of the flyback transformer T 1  is for connection to an alternating power source and the output of the input windings L P1  is connected to a node intermediate between the windings L P2  of the output transformer and the switching means S 1 . Hence, it would be appreciated from the circuit diagram and the description above that a single or common switching device is simultaneously connected in series with the input windings and the first output windings of the flyback transformer, thereby alleviating the need of two separate switches as is required by the known flyback-buckboost or flyback-boost converters.  
         [0030]     The dual-output flyback transformer T 1  includes a second output which is connected with the second output windings. This second output windings are connected to the output or a load via a diode D 3 . The connection between the second output winding of the flyback transformer and the output provides a feedback path so that the output voltage V 0  is fed back to the first output windings by the ratio N3/N1 in a perfectly coupled transformer, although a more detailed analysis of the coupling will be described below. By this feedback arrangement via the second output windings of the flyback transformer, the voltage across the intermediate storage capacitive means or the intermediate storage capacitor C B  will be controlled with reference to the magnitude of the output voltage, V 0  and the turns ratio N3/N1.  
         [0031]     The output transformer T 2  is provided for coupling power from the primary circuit (including the flyback transformer and the intermediate power capacitor) to the load. Of course, the output voltage V 0  can be adjusted by varying the turns ratio N2 in the output transformer without loss of generality.  
         [0032]     Furthermore, the output transformer T 2  also provides the necessary isolation to enable paths that can be selectively isolated by means of electronic switching for power transfer to the load and, alternatively, for power storage.  
         [0033]     Detailed operation of the present preferred embodiment of a SSPFC will be explained below.  
         [0000]     Operation  
         [0034]     Referring to the schematic circuit diagram of  FIG. 1 , the dual-output flyback transformer T 1  is connected to the line to shape the input current (it works in the Discontinuous Conduction Mode DCM for PFC function), to deliver energy to the intermediate storage capacitor C B , to provide a direct power transfer path to output for the converter and, more importantly, to control the voltage of C B . C B  delivers power through the flyback transformer T 2 , which operates in either DCM or CCM.  
         [0035]     The operation of the flyback SSPFC is described generally below. When the power switch S 1  is turned on, L p1  and L p2  are charged up linearly by the rectified input voltage V in  and the voltage across the storage capacitor V B  respectively. Diodes D 1 , D 3  and D 4  are reverse biased at this instant and are therefore not conducting. The output capacitor C o  sustains the output voltage V o . After the period d 1 T s  has lapsed, the switch S 1  is turned off as shown in  FIG. 3 , the diode D 4  is forward biased and the energy stored in T 2  will be coupled to the load. Meanwhile, the energy stored in T 1  is transferred to C B  and R o  through D 1  and D 3  respectively. Before S 1  is turned on again to begin the next switching cycle, all the energy stored in T 1  would have normally been completely transferred to the load and C B  (thus, i D1  and i D3  will fall to zero). If T 2  runs in CCM, V o  is maintained by the energy delivered from T 2  through D 4 . On the other hand, if T 2  operates in DCM, no current will flow in T 2  before S 1  is turned on. V o  is then sustained by C o . To repeat the operation cycle, S 1  is switched on again.  
         [0036]     When IV in l sis going through a half line cycle, the transformer T 2  enters into different conduction modes, as shown in  FIG. 2 . Although transformer T 1  works in DCM, the inevitable leakage inductance in T 1  will alter the downslopes and shapes of the secondary currents. Typically, there are three modes of operation and they are described below with reference to  FIG. 2 .  
         [0037]     Mode  1 : during this mode, T 2  runs in CCM. As the input power is lower than the output power, T 2  handles most of the output power. The major portion of stored energy in T 1  will be coupled to C B  through D 1 . i D1  has a generally trapezoidal waveform while i D3  has a generally triangular waveform, as shown in  FIG. 3 ( a ). In addition, because the duty ratio of S 1  is substantially constant within this interval, more input power as well as more output power will be handled by T 1  as input voltage increases. On one hand, this pushes T 2  towards DCM as T 1  provides more output current. On the other hand, the current in D 1  becomes smaller.  
         [0038]     Mode  2 : In this mode, T 2  runs in DCM and T 1  handles most of the output power. i D3  now has a trapezoidal shape and i D1  has a triangular shape, as shown in  FIG. 3 ( b ). When T 2  runs in CCM, it automatically corrects the current difference in D 3  and D 4  by shifting the level of CCM. But when both transformers T 1  and T 2  work in DCM, the duty ratio has to be decreased to maintain a constant output power, as the line voltage increases.  
         [0039]     Mode  3 : As input voltage reduces, T 2  again handles the major part of the output power as the input power becomes smaller. The duty ratio remains constant as in Mode  1 . The only difference is that the distribution of the secondary currents of T 1  are maintained substantially the same as that in Mode  2 .  
         [0040]     It should be noted that V o  is substantially free from low frequency components of the line voltage at both operation modes (DCM and CCM) of T 2 . When T 2  runs in CCM, the duty ratio of S 1  is constant due to fast self-adjustment of the transformer current. When T 2  runs in DCM (Mode  2  in  FIG. 2 ), the transformer current adjustment disappears but the fast feedback loop of V o  gives a valley-shape duty ratio of S 1  which maintains the output constant.  
         [0000]     Analysis of Storage Capacitor Voltage  
         [0041]     For ideal coupling transformer (i.e. in the absence of leakage inductance), the storage capacitor voltage V B  will be merely controlled by the turns ratio of transformer T 1  as the output voltage V o  is tightly regulated and it is given by equation (1) below:  
               V   B     =         n   1       n   3       ⁢     V   o               (   1   )             
 
         [0042]     However, in practice, the wiring inductance and the leakage inductance of transformer degrade the cross regulation of the converter. Equation (1) is no longer valid. By inspecting the current waveforms in Mode  1  and using input-output power balance between T 1 , T 2  and V o , the steady state expression of the storage capacitor voltage during this mode can be found.  
               V   B     =         n   1       n   3       ⁢         K   2     +         K   2   2     -     4   ⁢     K   1     ⁢     K   3               2   ⁢     K   1         ⁢     V   o     ⁢           ⁢   where             (   2   )                 K   1     =       1   16     ⁡     [       16   ⁢   π   ⁢           ⁢     n   3     ⁢     M   1   2     ⁢           k   c     ⁡     (     2   -   k     )       2     /     d   1   2         -     8   ⁢     n   1     ⁢       M   1     ⁡     (     2   -   k     )       ⁢     (     3   -     2   ⁢   k       )       +     π   ⁢           ⁢       n   3     ⁡     (     1   -   k     )       ⁢     (     2   -   k     )     ⁢     (     3   -   k     )         ]               (   3   )                 K   2     =       1   16     ⁡     [       16   ⁢   π   ⁢           ⁢     n   3     ⁢     M   1   2     ⁢         k   c     ⁡     (     2   -   k     )       /     d   1   2         -     8   ⁢         M   1     ⁡     (     3   -   k     )       2       +     π   ⁢           ⁢       n   3     ⁡     (     1   -   k     )       ⁢     (     3   -   k     )         ]               (   4   )                 K   3     =       1   2     ⁡     [       2   ⁢   π   ⁢           ⁢     n   3     ⁢     M   1   2     ⁢       k   c     /     d   1   2         -       M   1     ⁢   k       ]               (   5   )             
 
         [0043]     In the above equations, M 1  is the ratio of output voltage to peak input voltage, k is the coupling coefficient of T 1  and k c =Lp1/(R o T s ). Equation (2) holds provided that T 2  operates in CCM throughout the entire line cycle. Otherwise, the equation of steady state V B  over a half line cycle will involve different modes of operation and complex calculation. However, from equation (2) it is enough for one to predict that V B  will be controlled not only by the turns ratio and V O1  by the peak input voltage. When the peak input voltage increases, V B  will also increase.  
         [0000]     Analysis of Input Current  
         [0044]     The average input current &lt;i in &gt; of the proposed converter within one switching period equals the average primary current of T 1 &lt;i in &gt;L p1  and is given by  
               〈     i   in     〉     =           d   1   2     ⁢   Ts       2   ⁢     L   p1         ⁢            V   in     ⁡     (   t   )                      (   6   )             
 
         [0045]     This resembles the input current of a normal flyback converter serving as a power factor correction circuit. Hence, the proposed flyback SSPFC inherits unity factor property provided that T 2  is working in CCM throughout the line cycle so that the duty ratio d 1  can be kept constant. It is observed from  FIG. 2  that T 2  may enter DCM in Mode  2 , resulting in distorted input current as the third current harmonic component increases (and higher odd harmonics but of smaller quantity). The longer the duration of Mode  2 , the poorer the power factor will be. In fact when the output power becomes light, T 2  has larger tendency to enter DCM.  
         [0000]     Experimental Results  
         [0046]     In order to verify the operation of the proposed SSPFC shown in  FIG. 1 , a 28 Vdc-70 W hardware prototype with input voltage range 90-240 Vrms and 100 kHz switching frequency has been implemented and tested. The circuit parameters used for the experiment are L p 1=70 μH, n 1 =0.31, n 3 =1.54; L p2 =900 μH, n 2 =3.3; C B =200 μF; C o =1000 μF; S 1 : MTW14N50E, D 1 : MUR4100E, D 2 : MUR460, D 3  and D 4 :MUR860.  FIG. 4  shows the waveforms of the storage capacitor voltage, the input line voltage and the line current at 90 Vrms for a light load (30 W) and at full load (70 W). The measured power factor is 0.946 at 30 W and 0.997 at 70 W. The storage capacitor voltage V B  throughout the load range at different line voltages is recorded in  FIG. 5 . In theory, V B  equals (1.54/0.31)*28=139V according to equation (1). In practice, due to inevitable wiring and leakage inductances, V B  increases as input voltage increases, as have been predicted in (2). However, the increment of V B  of the proposed single-switch SSPFC (around 50-75V for 90-240 Vrms input) is much smaller than that of the existing single-stage topologies (at least 200V difference). It can also be seen that the variation of V B  is small even for large changes of output power (or load current). Furthermore, it is shown that V B  can be loosely regulated at a voltage lower than the peak input voltage at high line (240 Vrms in this case), so that a smaller voltage-rating capacitor can be used (e.g. 250V). When comparing with existing converter topologies,  FIG. 6  shows that the proposed SSPFC has the lowest V H  at high line voltage.  FIG. 7  shows that the measured efficiency of the SSPFC at different input voltages is around 80% at output power above 20 W.  
         [0047]     While the present invention has been explained by reference to the preferred embodiments described above, it will be appreciated that the embodiments are illustrated as examples to assist understanding of the present invention and are not meant to be restrictive on the scope and spirit of the present invention. The scope of this invention should be determined from the general principles and spirit of the invention as described above. In particular, variations or modifications which are obvious or trivial to persons skilled in the art, as well as improvements made on the basis of the present invention, should be considered as falling within the scope and boundary of the present invention.  
         [0048]     Furthermore, while the present invention has been explained by reference to a single stage power factor correction power converter, it should be appreciated that the invention can apply, whether with or without modification, to other multiple stage power converters without loss of generality.

Technology Category: 4