Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a multiplier oscillator that multiplies a clock signal. 
         [0003]    2. Description of Related Art 
         [0004]    A ring oscillator is generally known as a circuit that generates an internal clock signal with a high frequency (see Japanese Patent Application Laid-open No. 2010-192976). The ring oscillator includes odd numbers of inverter circuits cyclically-connected to generate a clock signal with a predetermined frequency depending on not only the number of stages of the inverter circuits, but also characteristics of transistors included in the inverter circuits, an operating voltage, and the like. The clock signal generated by the ring oscillator is supplied to, for example, a PLL (Phase-Locked Loop) circuit, so that an internal clock signal having higher frequency than that of an external clock signal supplied from outside can be obtained. 
         [0005]    However, in the PLL circuit using the ring oscillator, a generable frequency of the internal clock signal is limited by the oscillation frequency of the ring oscillator and thus the oscillation frequency of the ring oscillator needs to be increased to generate the internal clock signal with a higher frequency. Accordingly, in some cases, a boosted potential needs to be used as the operating voltage of the ring oscillator, which increases the circuit scale. 
         [0006]    In recent years, the operating voltage of a semiconductor device tends to be lowered from a viewpoint of reducing power consumption or decreasing jitter. Meanwhile, a threshold voltage of a transistor is sometimes designed to be sufficiently high to reduce an off-leakage current of the transistor. A decrease in the operating voltage or an increase in the transistor threshold voltage increases a delay amount of each stage of the inverter circuits included in the ring oscillator, which increases difficulty in increasing the oscillating frequency of the ring oscillator. 
         [0007]    In the PLL circuit using the ring oscillator, when there is a slightest difference between the frequency of the external clock signal and the oscillating frequency of the ring oscillator, the difference is accumulated little by little and consequently a large phase difference maybe caused. To reduce such a phase difference, a correction operation for the oscillating frequency needs to be constantly performed, which increases the power consumption. 
         [0008]    With this background, a semiconductor device including a multiplier oscillator that can generate an internal clock signal with a high frequency without using a ring oscillator has been demanded. 
       SUMMARY 
       [0009]    In one embodiment, there is provided a semiconductor device that comprises: a plurality of delay circuits connected in series, the delay circuits including an input-stage delay circuit receiving an input clock signal and an output-stage delay circuit outputting an output clock signal, each of the delay circuits representing a delay amount responsive to an operating voltage supplied thereto; a regulator circuit controlling the operating voltage to be supplied to each of the delay circuits in response to a phase relationship between the input clock signal and the output clock signal; and a synthesizing circuit configured to synthesize clock signals supplied to selected ones of the delay circuits to generate an internal clock signal. 
         [0010]    In another embodiment, there is provided a method that comprises: electrically connecting N delay circuits in series, N being two or more integers; controlling a level of an operating voltage to be supplied to each of the delay circuits so that a delay amount of each of the delay circuits becomes 1/N of a cycle of an input clock signal supplied to a leading one of the delay circuits; and responding to signals to be respectively delayed by the delay circuits to generate an internal clock signal having a frequency that is N/2 times as large as the input clock signal. 
         [0011]    In still another embodiment, such a device is derived that comprises: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, the delay circuits being coupled in series such that the output node of a preceding one of the delay circuits is coupled to the input node of the succeeding one of the delay circuits, the input node of a leading one of the delay circuits receiving a first clock signal, the output node of a last one of the delay circuits producing a second clock signal, the first power node of each of the delay circuits being connected to a first power line, and the second power node of each of the delay circuits being connected to a second power line; and a control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention; 
           [0013]      FIG. 2  is a block diagram showing a configuration of the multiplier oscillator shown in  FIG. 1 ; 
           [0014]      FIG. 3  is a circuit diagram of the variable delay circuit shown in  FIG. 2 ; 
           [0015]      FIG. 4  is a circuit diagram of the delay circuits shown in  FIG. 3 ; 
           [0016]      FIGS. 5A to 5D  are explanatory diagrams of operations of the variable delay circuit shown in  FIG. 2 ; 
           [0017]      FIG. 6  is a circuit diagram of the waveform synthesis circuit shown in  FIG. 2 ; 
           [0018]      FIG. 7  is a waveform chart for explaining an operation of the waveform synthesis circuit; 
           [0019]      FIGS. 8A to 8D  are waveform charts for explaining an influence in a case where the clock signal CLK 0  and the clock signal CLK 8  are out of phase; 
           [0020]      FIGS. 9A to 9F  are a waveform charts for explaining a problem occurred in the case where the target edge is more than one clock cycle after source edge; 
           [0021]      FIG. 10  is a circuit diagram of the reference-edge detection circuit shown in  FIG. 2 ; 
           [0022]      FIGS. 11A to 11C  are waveform charts for explaining an operation of the reference-edge detection circuit; 
           [0023]      FIG. 12  is a block diagram showing a configuration of a DLL circuit using the multiplier oscillator; 
           [0024]      FIG. 13  is a circuit diagram of the delay line shown in  FIG. 12 ; 
           [0025]      FIGS. 14A and 14B  are waveform charts for explaining rise time and the fall time of the inverter circuit shown in  FIG. 13 ; 
           [0026]      FIG. 15  is a waveform chart for explaining a problem in a case where a clock signal has high frequency; and 
           [0027]      FIG. 16  is a block diagram showing a configuration of another DLL circuit using the multiplier oscillator. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0028]    Referring now to  FIG. 1 , the semiconductor device according to the embodiment of the present invention is a DRAM (Dynamic Random Access Memory) that performs a prefetch operation and includes a memory cell array  10  having a plurality of memory cells and a peripheral circuit unit  20  that controls an operation of the memory cell array  10 . Although not particularly limited thereto, the number of bits to be prefetched is two in the case of a DDR (Double Date Rate) type, four in the case of a DDR2 type, and eight in the case of a DDR3 type. Because the DDR to DDR3 DRAMs perform input/output of data synchronously with both of a rise edge and a fall edge of a clock signal, a part of the peripheral circuit unit  20  needs to operate at a frequency twice as high as that of the memory cell array  10  in the case of the DDR2 type and at a frequency four times higher than that of the memory cell array  10  in the case of the DDR3 type. 
         [0029]    The memory cell array  10  and the peripheral circuit unit  20  operate synchronously with internal clock signals ICLK 0  and ICLK 1  supplied from a clock generator  32 , respectively. The clock generator  32  generates the internal clock signals ICLK 0  and ICLK 1  based on an external clock signal CK supplied from outside via a clock terminal  30  and an input first-stage circuit  31 . The frequency of the internal clock signal ICLK 1  is set to be the same frequency as that of the internal clock signal ICLK 0  in the case of the DDR type, twice as high as that of the internal clock signal ICLK 0  in the case of the DDR2 type, and four times higher than that of the internal clock signal ICLK 0  in the case of the DDR3 type. 
         [0030]    An address signal ADD and a command signal CMD supplied via an address terminal  41  and a command terminal  42 , respectively, are supplied to the peripheral circuit unit  20  via an input first-stage circuit  43 . Accordingly, when the command signal CMD indicates a read operation, the peripheral circuit unit  20  performs a read operation for the memory cell array  10 , so that read data is read from a memory cell indicated by the address signal ADD. Read data DQ read from the memory cell array  10  is output to outside via a data input/output circuit  51  and a data input/output terminal  50 . When the command signal CMD indicates a write operation, the peripheral circuit unit  20  performs a write operation for the memory cell array  10 , so that write data DQ supplied from outside via the data input/output terminal  50  and the data input/output circuit  51  is written in a memory cell indicated by the address signal ADD. 
         [0031]    A low-speed test and a high-speed test are performed for the semiconductor device of this embodiment before shipment. The low-speed test is performed for detecting defective memory cells included in the memory cell array  10  and replacing the detected defective memory cells with auxiliary memory cells. Because the low-speed test is performed for many semiconductor devices in parallel in a wafer state, a tester that enables a high-speed operation is impractical and thus a low-speed tester is used. Therefore, an external clock signal CK with a low frequency is used at the time of the low-speed test. After the defective memory cells are replaced with the auxiliary memory cells in the low-speed test, the wafer is diced to singulate semiconductor chips, the semiconductor chips are packaged, and then the high-speed test is performed. The high-speed test is an operation test using a high-speed external clock signal CK as at the time of a practical operation and is mainly performed to check whether the peripheral circuit unit  20  correctly operates at a high speed. 
         [0032]    The high-speed test needs to use an expensive tester that can operate at a high speed, which is a factor of an increase in the manufacturing cost of a semiconductor device. To solve this problem, in the semiconductor device according to the present embodiment, the high-speed test can be also performed at the time of the low-speed test by using a multiplier oscillator  100  and a test-signal generation circuit  200 . 
         [0033]    The multiplier oscillator  100  generates the internal clock signal ICLK 1  with a higher frequency than that of the external clock signal CK by multiplying the external clock signal CK supplied via the input first-stage circuit  31  at the time of the low-speed test. The test-signal generation circuit  200  is a circuit that internally generates the address signal ADD, the command signal CMD, and the write data DQ and supplies the address signal ADD, the command signal CMD, and the write data DQ to the peripheral circuit unit  20  at the time of the low-speed test. By including the multiplier oscillator  100  and the test-signal generation circuit  200 , the semiconductor device according to the present embodiment enables the peripheral circuit unit  20  to operate at a high speed synchronously with the high-speed internal clock signal ICLK 1  also at the time of the low-speed test. Accordingly, a part of or the entirety of the high-speed test performed using an expensive tester can be omitted. 
         [0034]    When the low-speed test is first performed, the multiplier oscillator  100  and the test-signal generation circuit  200  are deactivated, the external clock signal CK, the address signal ADD, the command signal CMD, and the write data DQ are supplied to the terminals  30 ,  41 ,  42 , and  50 , respectively, and a test on the memory cell array  10  is performed. The frequency of the external clock signal CK is sufficiently lower than that to be used at the time of the practical operation and the address signal ADD, the command signal CMD, and the write data DQ are also supplied synchronously with the external clock signal CK. The result of the test is compressed by a test-result confirmation circuit  210  and is supplied to the tester via the data input/output terminal  50 . 
         [0035]    Meanwhile, when the high-speed test is performed, the multiplier oscillator  100  and the test-signal generation circuit  200  are activated and a low-speed external clock signal CK is supplied to the clock terminal  30 . The address signal ADD, the command signal CMD, and the write data DQ are not supplied. The multiplier oscillator  100  receives the low-speed external clock signal CK and generates the high-speed internal clock signal ICLK 1  by multiplying the external clock signal CK. The test-signal generation circuit  200  internally generates the address signal ADD, the command signal CMD, and the write data DQ synchronously with the internal clock signal ICLK 1  and supplies the address signal ADD, the command signal CMD, and the write data DQ to the peripheral circuit unit  20 . Accordingly, the peripheral circuit unit  20  can operate at the same speed as at the time of the practical operation. The internal clock signal ICLK 0  having the same frequency as that of the low-speed external clock signal CK is supplied to the memory cell array  10 . The result of the test is slowed down by a test-result slowing circuit  220  and supplied to the tester via the test-result confirmation circuit  210  and the data input/output terminal  50 . Slowing down by the test-result slowing circuit  220  can be achieved, for example, by conversion of read data serially output from the peripheral circuit unit  20  into parallel read data, and the parallel read data can be compressed by the test-result confirmation circuit  210 . 
         [0036]    At the time of a normal operation, the multiplier oscillator  100  and the test-signal generation circuit  200  are deactivated. A conventional high-speed test can be also performed in the same operation condition as at the time of the normal operation. 
         [0037]    A specific circuit configuration of the multiplier oscillator  100  and an operation thereof are explained below in detail. 
         [0038]    Turning to  FIG. 2 , the multiplier oscillator  100  includes a variable delay circuit  110  that receives an input clock signal CLK 0  and generates a phase determination signal PD and clock signals CLK 0  to CLK 7  with different phases. The multiplier oscillator  100  further includes a regulator circuit  120  that generates an operating voltage Vdly of the variable delay circuit  110  based on the phase determination signal PD, and a waveform synthesis circuit  130  that generates the internal clock signal ICLK 1  by synthesizing the clock signals CLK 0  to CLK 7 . 
         [0039]    Turning to  FIG. 3 , the variable delay circuit  110  includes eight delay circuits  111  to  118  that are cascade-connected and a phase discrimination circuit (or a phase comparator)  119  that compares phases of the clock signals CLK 0  and CLK 8  with each other. The delay circuits  111  to  118  receive the clock signals CLK 0  to CLK 7  and delay the received clock signals to output clock signals CLK 1  to CLK 8 , respectively. The delay circuits  111  to  118  have the same circuit configuration as one another and all operate with the same operating voltage Vdly. 
         [0040]    Turning to  FIG. 4 , each of the delay circuits  111  to  118  includes two inverter circuits INV 1  and INV 2  that are cascade-connected. The operating voltage Vdly is supplied to a source of a P-channel MOS transistor included in each of the inverter circuits INV 1  and INV 2 , and a ground potential VSS is supplied to a source of an N-channel MOS transistor included in each of the inverter circuits INV 1  and INV 2 . With this configuration, a delay amount of one delay circuit can be controlled by the level of the operating voltage Vdly. Specifically, the delay amount of one delay circuit becomes smaller when the operating voltage Vdly has a higher level, and the delay amount of one delay circuit becomes larger when the operating voltage Vdly has a lower level. The circuit configuration of the delay circuits  111  to  118  is not limited to that shown in  FIG. 4  and, for example, a circuit including four inverter circuits cascade-connected can be used. 
         [0041]    An operation of the variable delay circuit  110  and the regulator circuit  120  will be explained with reference to  FIGS. 5A to 5D .  FIG. 5A  shows a waveform of the clock signal CLK 0  and  FIGS. 5B ,  5 C and  5 D show waveforms of the clock signal CLK 8 . 
         [0042]    First, when the clock signal CLK 8  has a phase shown in  FIG. 5B , that is, when the phase of the clock signal CKL 8  is delayed with respect to that of the clock signal CLK 0 , the phase discrimination circuit  119  shown in  FIG. 3  sets the phase determination signal PD to a high level. This determination is performed based on a fact that the clock signal CLK 8  has a low level at a timing when the clock signal CLK 0  changes from a low level to a high level. When the phase determination signal PD has a high level, the regulator circuit  120  increases the level of the operating voltage Vdly. As a result, the delay amount of one delay circuit is decreased and thus the phase of the clock signal CLK 8  is advanced. 
         [0043]    On the contrary, when the clock signal CLK 8  has a phase shown in  FIG. 5C , that is, the phase of the clock signal CLK 8  is advanced with respect to that of the clock signal CLK 0 , the phase discrimination circuit  119  sets the phase determination signal PD to a low level. This determination is performed based on a fact that the clock signal CLK 8  has a high level at a timing when the clock signal CLK 0  changes from a low level to a high level. When the phase determination signal PD has a low level, the regulator circuit  120  decreases the level of the operating voltage Vdly. As a result, the delay amount of one delay circuit is increased and thus the phase of the clock signal CLK 8  is delayed. 
         [0044]    By repeating this operation, the phase of the clock signal CLK 8  is controlled to match with the phase of the clock signal CLK 0  as shown in  FIG. 5D . A state where the phases of the clock signal CLK 0  and the clock signal CLK 8  match, that is, a state where the phases are locked means that a delay amount obtained by the delay circuits  111  to  118  is equal to an integral multiple of a cycle of the clock signal CLK 0 . When the delay amount obtained by the delay circuits  111  to  118  is equal to one cycle of the clock signal CLK 0  in this case, the phases of the clock signals CLK 0  to CLK 7  output from the variable delay circuit  110  are shifted from one another by ⅛ clock cycle. While the clock signals CLK 0  to CLK 7  are extracted from the variable delay circuit  110  in the present embodiment, the clock signals CLK 1  to CLK 8  may be extracted instead of the clock signals CLK 0  to CLK 7 . 
         [0045]    Turning to  FIG. 6 , the waveform synthesis circuit  130  includes one-shot-pulse generation circuits OP 0  to OP 7  to which the clock signals CLK 0  to CLK 7  are supplied, respectively. Each of the one-shot-pulse generation circuits OP 0  to OP 7  generates a low-level one-shot pulse synchronously with a rise edge of corresponding one of the clock signals CLK 0  to CLK 7 . Output signals of the one-shot-pulse generation circuits OP 0 , OP 2 , OP 4 , and OP 6  are supplied to an NAND gate circuit  131 . An output signal of the NAND gate circuit  131  is supplied to a gate electrode of a P-channel MOS transistor  134  via an inverter circuit  132  and a timing adjustment circuit  133 . A power supply potential VPERI is supplied to a source of the transistor  134  and accordingly the transistor  134  functions as a driver circuit that drives the internal clock signal ICLK 1  to a high level. Similarly, output signals of the one-shot-pulse generation circuits OP 1 , OP 3 , OP 5 , and OP 7  are supplied to a NAND gate circuit  135 . An output signal of the NAND gate circuit  135  is supplied to a gate electrode of an N-channel MOS transistor  138  via inverter circuits  136  and  137 . A ground potential VSS is supplied to a source of the transistor  138  and accordingly the transistor  138  functions as a driver circuit that drives the internal clock signal ICLK 1  to a low level. 
         [0046]    The timing adjustment circuit  133  includes transistors P 1  and N 1  having the same sizes as those of transistors P 2  and N 2 , respectively, included in the inverter circuit  137 . An output signal of the inverter circuit  132  is supplied to sources of the transistors P 1  and N 1 . Because the ground potential VSS is supplied to agate electrode of the transistor P 1  and the power supply potential VPERI is supplied to a gate electrode of the transistor N 1 , the transistors P 1  and N 1  are always in an on-state. Therefore, when the output signal from the inverter circuit  132  has a high level, the output signal from the inverter circuit  132  is supplied to the gate electrode of the transistor  134  via the transistor P 1 . This flow of the output signal has the same condition as that of a signal flowing to the gate electrode of the transistor  138  via the transistor P 2  when an output signal of the inverter circuit  136  changes to a low level. Similarly, when the output signal from the inverter circuit  132  has a low level, the output signal from the inverter circuit  132  is supplied to the gate electrode of the transistor  134  via the transistor N 1 . This flow of the output signal has the same condition as that of a signal flowing to the gate electrode of the transistor  138  via the transistor N 2  when the output signal of the inverter circuit  136  changes to a high level. In this way, operation timings of the transistors  134  and  138  are matched with each other. 
         [0047]    In an example shown in  FIG. 7 , the clock signal CLK 8  is delayed with respect to the clock signal CLK 0  by one cycle. That is, the delay amount obtained by the delay circuits  111  to  118  shown in  FIG. 3  corresponds to one cycle of the clock signal CLK 0 . In this case, the phases of the clock signals CLK 0  to CLK 7  are shifted from one another by ⅛ clock cycle as shown in  FIG. 7 . This means that rise edges of the clock signals CLK 0  to CLK 7  appear every ⅛ clock cycle. As mentioned above, when the clock signals CLK 0  to CLK 7  rise, a one-shot pulse is generated by the corresponding one-shot-pulse generation circuits OP 0  to OP 7 , respectively. 
         [0048]    Specifically, when one of the clock signals CLK 0 , CLK 2 , CLK 4 , and CLK 6  changes from a low level to a high level, a low-level one-shot pulse is output from corresponding one of the one-shot-pulse generation circuits OP 0 , OP 2 , OP 4 , and OP 6  and thus the transistor  134  is turned on in response thereto. Accordingly, the internal clock signal ICLK 1  rises to a high level. On the other hand, when one of the clock signals CLK 1 , CLK 3 , CLK 5 , and CLK 7  changes from a low level to a high level, a low-level one-shot pulse is output from corresponding one of the one-shot-pulse generation circuits OP 1 , OP 3 , OP 5 , and OP 7  and thus the transistor  138  is turned on in response thereto. Accordingly, the internal clock signal ICLK 1  falls to a low level. 
         [0049]    Therefore, when the clock signals CLK 0  to CLK 7  rise in this order as shown in  FIG. 7 , the logic level of the internal clock signal ICLK 1  changes synchronously therewith. That is, the logic level of the internal clock signal ICLK 1  changes every ⅛ clock cycle, so that the internal clock signal ICLK 1  having four times faster than the clock signal CLK 0  is generated. 
         [0050]    If the clock cycle of the internal clock signal ICLK 1  becomes slightly longer than the fourfold cycle of the clock signal CLK 0 , the phase of the clock signal CLK 8  is delayed with respect to that of the clock signal CLK 0  and accordingly the operating voltage Vdly is increased by the regulator circuit  120  shown in  FIG. 2 , which decreases the delay amount of one delay circuit. In this way, the clock cycle of the internal clock signal ICLK 1  is controlled to be reduced. On the contrary, if the cycle of the internal clock signal CILK 1  becomes slightly shorter than the fourfold cycle of the clock signal CLK 0 , the phase of the clock signal CLK 8  is advanced with respect to that of the clock signal CLK 0  and accordingly the operating voltage Vdly is decreased by the regulator circuit  120 , which increases the delay amount of one delay circuit. In this way, the clock cycle of the internal clock signal ICLK 1  is controlled to be increased. By repeating this operation, the cycle of the internal clock signal ICLK 1  is correctly controlled to be four times faster than that of the clock signal CLK 0  and the phase of the internal clock signal ICLK 1  exactly matches with that of the clock signal CLK 0 . 
         [0051]    Turning to  FIGS. 8A to 8D ,  FIG. 8A  shows a waveform of the clock signal CLK 0  having a cycle of 2500 ps (picoseconds), for example. Ideally, in this case, the cycle of the internal clock signal ICLK 1  is expected to be 625 ps as shown in  FIG. 8B . However, if the delay amount obtained by the delay circuits  111  to  118  is slightly longer than one cycle of the clock signal CLK 0  and 2525 ps, for example, as shown in  FIG. 8C , the cycle of the internal clock signal ICLK 1  actually obtained is 631.25 ps. In this case, a difference between an edge of the ideal internal clock signal ICLK 1  and an edge of the internal clock signal ICLK 1  actually obtained increases with passage of the time from appearance of a rise edge of the clock signal CLK 0  and reaches 21.875 ps at the last edge E 0  as shown in  FIG. 8D . However, this phase difference is reset at the next rise edge of the clock signal CLK 0 . Therefore, a phenomenon in which a phase difference is accumulated little by little as in the PLL circuit using the ring oscillator does not occur. 
         [0052]    While the case where the delay amount obtained by the delay circuits  111  to  118  is equal to one cycle of the clock signal CLK 0  has been explained above, the variable delay circuit  110  shown in  FIG. 3  locks the phases if the delay amount obtained by the delay circuits  111  to  118  is an integral multiple of the cycle of the clock signal CLK 0 . The lock means a state where a control is executed to keep a state where a rise edge of the clock signal CLK 0  and a rise edge of the clock signal CLK 8  match with each other. 
         [0053]    For example, when the delay amount obtained by the delay circuits  111  to  118  is 3.25 cycles of the clock signal CLK 0  as shown in  FIG. 9A , the variable delay circuit  110  adversely executes a control to match the delay amount obtained by the delay circuits  111  to  118  with three cycles (3T) of the clock signal CLK 0 . A waveform shown in  FIG. 9A  indicates the clock signal CLK 0  and waveforms shown in  FIGS. 9B and 9C  indicate the clock signal CLK 8  before and after the control, respectively. That is,  FIG. 9C  shows a state where the clock signal CLK 8  is locked with the clock signal CLK 0  shown in  FIG. 9A  in a delay of three cycles with respect thereto. In this case, the waveform of the obtained internal clock signal ICLK 1  is as shown in  FIG. 9D  and is quite different from an intended frequency (four times that of the clock signal CLK 0 ). 
         [0054]    To obtain the intended frequency, the delay amount obtained by the delay circuits  111  to  118  needs to be controlled in such a manner that the clock signal CLK 8  is delayed with respect to the clock signal CLK 0  by one clock cycle (1T) as shown in  FIG. 9E .  FIG. 9F  shows the internal clock signal ICLK 1  locked at the intended frequency. 
         [0055]    To avoid the problem explained with reference to  FIGS. 9A to 9D , that is, the problem that the delay amount obtained by the delay circuits  111  to  118  is locked at n clock cycles (n is an integer equal to or larger than two) of the clock signal CLK 0 , the multiplier oscillator  100  according to the present embodiment includes a reference-edge detection circuit  140 . 
         [0056]    Turning to  FIG. 10 , the reference-edge detection circuit  140  includes eight latch circuits FF 1  to FF 8  that are cascade-connected. Among these circuits, each of the latch circuits FF 1  to FF 7  receives input data from a latch circuit at the previous stage synchronously with a rise edge of corresponding one of the clock signals CLK 1  to CLK 7 . Input data D 0  supplied to the latch circuit FF 1  at the first stage is fixed to a high level. The latch circuit FF 8  at the last stage receives input data D 7  from the latch circuit FF 7  at the previous stage synchronously with a rise edge of the clock signal CLK 0 . A determination signal S output from the latch circuit FF 8  at the last stage is supplied to the regulator circuit  120  shown in  FIG. 2 . 
         [0057]    Each of the latch circuits FF 1  to FF 8  has a reset node. When the reset node is activated, the latch data is reset to a low level. As shown in  FIG. 10 , the output signal of the one-shot-pulse generation circuit OP that generates a one-shot pulse synchronously with a rise edge of the clock signal CLK 0  is supplied to the reset nodes of the latch circuits FF 1  to FF 7 . Accordingly, the latch circuits FF 1  to FF 7  are reset each time the clock signal CLK 0  changes to a high level. A reset signal RB activated at the time of an initialization operation is supplied to the reset node of the latch circuit FF 8 . 
         [0058]      FIG. 11A  shows a waveform of the clock signal CLK 0  and  FIGS. 11B and 11C  show waveforms of the internal clock signal ICLK 1  generated in cases where the delay amount obtained by the delay circuits  111  to  118  is three clock cycles and one clock cycle of the clock signal CLK 0 , respectively. 
         [0059]    First, in the case where the delay amount obtained by the delay circuits  111  to  118  is three clock cycles of the clock signal CLK 0 , output signals D 1  to D 7  of the latch circuits FF 1  to FF 7  are excepted to change to a high level at timings shown in  FIG. 11B , respectively, assuming that the latch circuits FF 1  to FF 7  are not reset. However, all of the latch circuits FF 1  to FF 7  are actually reset each time the clock signal CLK 0  rises and thus a high-level output signal D 7  never reaches the latch circuit FF 8  at the last stage. That is, after being reset at the initialization operation, the latch circuit FF 8  at the last stage keeps the initial state and accordingly the determination signal S is kept at a low level. 
         [0060]    When the determination signal S is kept at the low level, the regulator circuit  120  shown in  FIG. 2  increases the operating voltage Vdly regardless of the phase determination signal PD. This is because the delay amount obtained by the delay circuits  111  to  118  is far beyond one clock cycle of the clock signal CLK 0  and thus the delay amount needs to be forcibly reduced to prevent erroneous locking at n clock cycles (n is an integer equal to or larger than two) of the clock signal CLK 0 . 
         [0061]    When the delay amount obtained by the delay circuits  111  to  118  is forcibly reduced in this way, the delay amount is shortened to near one clock cycle of the clock signal CLK 0 . In this case, before the latch circuits FF 1  to FF 7  are reset, the output signals D 1  to D 7  of the latch circuits FF 1  to FF 7  change to a high level at timings shown in  FIG. 11C , respectively, and thus a high-level output signal D 7  reaches the latch circuit FF 8  at the last stage. As a result, the determination signal S changes to a high level. When the determination signal S changes to the high level, the regulator circuit  120  starts the operation based on the phase determination signal PD. The operation of the regulator circuit  120  based on the phase determination signal PD is as explained above and the operating voltage Vdly is controlled to match the delay amount obtained by the delay circuits  111  to  118  with one clock cycle of the clock signal CLK 0 . 
         [0062]    With this operation, the multiplier oscillator  100  according to the present embodiment controls the delay amount obtained by the delay circuits  111  to  118  to delay the phase of the clock signal CLK 8  with respect to that of the clock signal CLK 0  exactly by one clock cycle, so that the phenomenon in which locking is performed at an unintended frequency can be prevented. 
         [0063]    As described above, with the multiplier oscillator  100  according to the present embodiment, the internal clock signal ICLK 1  being a signal obtained by correctly multiplying the input clock signal CLK 0  can be generated. Furthermore, a correct internal clock signal can be generated with lower power consumption than in an oscillation circuit using a ring oscillator. 
         [0064]    While the internal clock signal ICLK 1  having a frequency four times higher than that of the clock signal CLK 0  is generated using the eight delay circuits  111  to  118  in the present embodiment, the frequency of an internal clock signal to be generated can be arbitrarily set according to the number of delay circuits to be used. Specifically, when N delay circuits are used, an internal clock signal having N/2 times the frequency (2/N times the clock cycle) of the clock signal CLK 0  can be generated. 
         [0065]    The multiplier oscillator  100  according to the present embodiment can be applied also to a DLL (Delay-Locked Loop) circuit. 
         [0066]    Turning to  FIG. 12 , the DLL circuit  300  according to the first example includes a frequency division circuit  310  that generates a frequency-divided clock signal DCLK by frequency-dividing the external clock signal CK and a delay line  320  that delays the frequency-divided clock signal DCLK. The delay line  320  generates an input clock signal CLK 0  that is phase-controlled. The input clock signal CLK 0  is supplied to the multiplier oscillator  100 . 
         [0067]    The input clock signal CLK 0  is supplied also to a replica buffer circuit  330 . A replica clock signal RCLK, which is an output signal from the replica buffer circuit  330 , is fed back to a delay adjustment circuit  340 . The delay adjustment circuit  340  performs a phase comparison operation between the replica clock signal RCLK and the frequency-divided clock signal DCLK to control a delay amount of the delay line  320  based on the result of the phase comparison operation. 
         [0068]    The delay line  320  has a configuration including a plurality of inverter circuits that are cascade-connected as shown in  FIG. 13  and the clock signal CLK 0  is extracted from any one of the inverter circuits selected by the delay adjustment circuit  340 . Specifically, when the phase of the replica clock signal RCLK is delayed with respect to that of the frequency-divided clock signal DCLK, the clock signal CLK 0  is extracted from an inverter circuit at a more previous stage because the delay amount needs to be smaller. One the contrary, when the phase of the replica clock signal RCLK is advanced with respect to that of the frequency-divided clock signal DCLK, the clock signal CLK 0  is extracted from an inverter circuit at a more subsequent stage because the delay amount needs to be larger. By repeating this operation, the phase of the replica clock signal RCLK is matched with that of the frequency-divided clock signal DCLK. 
         [0069]    In this case, a problem occurs that, when a clock signal to be supplied to the delay line  320  has a higher frequency, signal quality is greatly deteriorated if a delay amount of each stage of the inverter circuits included in the delay line  320  is not set smaller. That is, as shown in  FIG. 14A , the inverter circuits have a threshold voltage and, each time the level of the input signal shown in  FIG. 14A  exceeds the threshold voltage, an output signal shown in  FIG. 14B  is inverted. However, a change in the input signal or the output signal requires a certain time. In the waveform shown in  FIG. 14A , tR denotes a time required for arise of the input signal and tF denotes a time required for a fall of the input signal. If lengths of the rise time tR and the fall time tF are sufficiently shorter than the clock cycle of the clock signal passing through the delay line  320 , no problem occurs. 
         [0070]    However, when the clock signal passing through the delay line  320  is faster, the clock cycle thereof is shorter and thus influences of the rise time tR and the fall time tF become negligible. It is found that a clock signal having a cycle shorter than 800 ps cannot be correctly transmitted when the rise time tR and the fall time tF are both 400 ps, for example, as shown in  FIG. 15 . 
         [0071]    This problem can be solve by arranging the frequency division circuit  310  at the previous stage of the delay line  320  as in the DLL circuit  300  shown in  FIG. 12 . That is, when the frequency division circuit  310  is arranged at the previous stage of the delay line  320 , a clock signal passing through the delay line  320  has a frequency reduced to one-fourth or one-eighth, for example, and thus the problem mentioned above does not occur. The frequency reduced by the frequency division circuit  310  can be then regenerated by multiplying the clock signal CLK 0  output from the delay line  320  with the multiplier oscillator  100 . 
         [0072]    When the multiplier oscillator  100  according to the present embodiment is applied to the DLL circuit in this way, the phase control can be correctly executed even when the external clock signal CK has a high frequency. 
         [0073]    Turning to  FIG. 16 , the DLL circuit  350  according to the second example is different from the DLL circuit  300  shown in  FIG. 12  in that the frequency division circuit  310  is omitted. Because other elements are the same as those in the DLL circuit  300  shown in  FIG. 12 , like elements are denoted by like reference characters and redundant explanations will be omitted. According to the DLL circuit  350  shown in  FIG. 16 , the internal clock signal ICLK 1  having a higher frequency than that of the external clock signal CK can be correctly phase-controlled. Furthermore, because the multiplier oscillator  100  is arranged at the subsequent stage of the delay line  320 , not at the previous stage thereof, the frequency of a clock signal passing through the delay line  320  never become higher than that of the external clock signal CK. 
         [0074]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.

Technology Category: 5