Patent Document

FIELD OF INVENTION  
       [0001]     The field of invention relates generally to the computing sciences, and, more specifically, to a low power display mode.  
       BACKGROUND  
       [0002]      FIG. 1  shows a prior art computing system architecture. According to the architecture of  FIG. 1 , a memory controller  101  is responsible for presenting data in system memory  102  to both one or more processors  103  and a display controller  104 . The particular memory controller  101  observed in  FIG. 1  also includes one or more graphics controllers  116 , a front side bus interface  107 , a system memory interface  106  and core logic  108 . The front side bus interface  107  has logic circuitry that controls the memory controller&#39;s signaling between the processor(s)  103 . The system memory interface  106  has logic circuitry that controls the memory controller&#39;s signaling between system memory  111 .  
         [0003]     The system memory interface  106  is coupled to the system memory  102  with a data bus wiring  110  and memory clock (I/O_MCLK) wiring  111 . The memory clock signal that appears on the memory clock wiring  111  is provided by the memory controller  101  and is used to control the rate at which operations are performed by the system memory  102 . The memory clock signal is taken directly (or derived from) an output of Memory Interface Clock (MIC) circuitry  109 . In an implementation, the MIC circuitry  109  is implemented as a delay locked loop (DLL) that imposes precise delay between a reference clock (not shown in  FIG. 1 ) and one or more output clocks.  
         [0004]     The front side bus interface  107  is coupled to the processor(s)  103  by front side bus wiring that carries transactions (e.g., for reads/writes from/to system memory  102 ) between the memory controller  101  and the processor(s)  103 . The memory controller&#39;s core logic  108  includes logic circuitry that performs the memory controller&#39;s “core” function, namely, responding to requests to read/write data from/to system memory  101  that are sent by the processor(s)  103 , the graphics controller(s)  116 , the display controller  104  and perhaps one or more “I/O devices” (e.g., a disk drive, a network interface, a bus for attachment to a peripheral device (e.g., a printer) such as the Universal Serial Bus (USB), etc.).  
         [0005]     Both the front side bus interface  107 , the graphics controller(s)  116  and the core logic  108  of the memory controller  101  are clocked by Memory Controller Core (MCC) clock circuitry  112 . In an implementation, the MCC clock circuitry is implemented as a phase locked loop (PLL) that “multiplies up” the frequency of a reference clock. The reference clock of the MCC clock circuitry  112  and the reference clock of the MIC circuitry  109  are typically different such that the memory controller  101  has both a “core side” clock domain and a “memory side” clock domain.  
         [0006]     The display controller  104  is coupled to the memory controller (typically, through a “display port” interface designed into the memory controller  101  that has not been drawn in  FIG. 1  for illustrative convenience). The display controller  104  includes a first, “display” FIFO  113  that stores data that was read from system memory  102  and that will be processed by the display controller&#39;s core logic  114  so that it can ultimately be rendered on the display  105  (such as a “flat panel” display (e.g., a thin film transistor (TFT) display)). The display controller&#39;s core logic  114  performs the “core” function of the display controller, namely, the processing of data so that it can be “rendered” on the display  105 . The display controller  104  also includes a second “clock domain transition” FIFO  115  that permits the data produced by the display controller&#39;s core logic  114  to be driven toward the display  105  with a clock that is derived from a different source than the clock used to drive the display core logic  114 . The display FIFO  113  fill rate is supposed to be no less than the display FIFO  113  empty rate. The display FIFO  113  empty rate requirement is determined by the display  105  configuration (e.g., display type, pixel resolution, and display refresh rate).  
         [0007]     Prior art computing systems (and in particular mobile, battery operated computing systems such as laptop and notebook computers) are designed so as to operate according to different operational states that scale in both functional performance level and electrical power consumption. For instance, according to a “highest” performance and power consumption state (e.g., in which a processor is actively executing instructions), a processor will use its highest possible internal clock speed and will “activate” all of its internal circuitry regions. In a lower performance and power consumption state (e.g., in which a processor is “idling”), the processor will use a lower internal clock speed and may even have certain regions of its circuitry “deactivated”. In an even lower performance and power consumption state (e.g., in which a processor is “hibernated” or “sleeping”), the processor reduces to a lowest possible internal clock speed and deactivates significant portions of its internal circuitry.  
         [0008]     The system memory  101  can also scale performance and electrical power consumption in order to support the computing system&#39;s various performance and power scaled operational states. For instance, system memory  101  may have a higher “auto-refresh” performance and power consumption state in which the system memory  101  needs an active memory clock  111  signal in order to prevent it from losing its internally stored data. The system memory  101  may also have a lower “self refresh” performance and power consumption state in which the system memory  101  does not need an active memory clock  111  signal in order to prevent it from losing its internally stored data.  
         [0009]     The display  105 , when illuminated with content, also needs to be continuously “refreshed” with data to be displayed. Here, the operation of rendering content on a display  105  can be viewed as the repeated displaying of a “screen&#39;s worth” of data. The screen&#39;s worth of data may change from screen view to screen view in order to effect visual changes in the matter that appears on the display  105  (and/or, the screen&#39;s worth of data may not change, but, still needs to be provided to the display  205  because displays are generally designed so that their visual content will degrade in appearance if they are not resent “new data” that corresponds to the same, continuously displayed imagery ). At least when “new content” is continuously being presented on the display  105 , the memory controller  101  may need to continuously read new data from system memory  101  and present it to the display controller  104  (which enters it into the display FIFO  113 ) at a rate high enough to prevent FIFOs  113  and  115  from starving. Note that the data being read from system memory  102  may previously have been processed by the graphics controller(s)  216  and written into system memory  102 .  
         [0010]     An operational mode of the memory controller  101  and display controller  104 , referred to as “display mode” (because the display controller  104  is essentially given a sufficiently high bandwidth connection through the memory controller  101  to the system memory  102 ), is used to support the continuous (“streaming”) presentation of new content on the display  105 . It is moreover possible that, while the memory controller  101  and display controller  104  are in the display mode, the processor(s)  103  are in a reduced performance and power consumption state in which requests will not be presented to the memory controller  101  over the front side bus for reads/writes from/to system memory  102 . Here, the display  105  should be kept updated even if the processor(s)  103  are in a low performance and power consumption mode (such as no clocks, or very low frequency clocks, running, and/or many functional blocks disabled)  
         [0011]     Unfortunately, the memory controller  101  and display controller  104  of the prior art computing system of  FIG. 1  were not specifically designed to substantially reduce the power consumption of the computing system&#39;s integrated graphics mode when the memory controller&#39;s front side bus was essentially inactive. Specifically, the MCC clock  112  was “always on” which essentially caused the memory controller&#39;s graphics controller(s)  116  and core logic circuitry  108  as well as the display controller&#39;s display FIFO  113  (and perhaps parts its core logic  114 ) to continuously consume electrical power.  
     
    
     FIGURES  
       [0012]     The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:  
         [0013]      FIG. 1  shows a prior art computing system;  
         [0014]      FIG. 2  shows an improved computing system;  
         [0015]      FIG. 3  shows a timeline of a process performed by the improved computing system of  FIG. 2 ;  
         [0016]      FIG. 4  shows a process performed by the improved computing system;  
         [0017]      FIG. 5  shows a discrete graphics controller implementation.  
     
    
     DETAILED DESCRIPTION  
       [0018]      FIG. 2  shows one embodiment of an improved memory controller  201  and display controller  204  design that strives to optimize the power consumption efficiency of the display mode when little or no memory read/write requests are expected over the front side bus (except perhaps those targeted for the display  205 ). According to the design of  FIG. 2 , the display FIFO  213  of the graphics controller  204  is designed to be large enough so that the memory controller  201  and system memory  202  can be kept in reduced power consumption states for long periods of time while the display FIFO  213  feeds the display controller&#39;s core logic circuitry  214 .  
         [0019]     Specifically (according to one embodiment), over the expanse of a single display refresh cycle, except for a relatively brief period of time in which an entire display refresh cycle&#39;s worth of data is read from system memory  201  and entered into the display FIFO  213 , the memory controller&#39;s core logic circuitry  208  is deactivated through the disabling of the MCC clock  212  and the system memory  202  is placed in “self refresh” mode. The graphics controller(s)  216  may also be deactivated. During the relatively brief period of time in which an entire refresh cycle&#39;s worth of data is entered into the display FIFO  213 , the MCC clock  212  is enabled and the system memory is placed in “auto refresh” mode.  
         [0020]     An embodiment of the scheme can be better understood in reference to FIGS.  2  and  FIG. 3  together. Referring to  FIGS. 2 and 3 , at time T 0 , the display FIFO  213  is “full” or otherwise contains enough data to refresh an entire screen&#39;s worth of visual content. Starting in this state, note that the MCC clock  212 ,  312  is “off”, the MIC clock  209 ,  309  is “off”, the memory clock  211 ,  311  is “off”, and the memory&#39;s data bus  210 ,  310  is quiet (i.e., substantive data is not being read from system memory  202 ).  
         [0021]     Because the MCC clock  212 ,  312  is “off” the memory controller&#39;s core logic  208  and graphics controller(s)  216  are not consuming large amounts of electrical power. Because the MIC clock  209 ,  309  is also “off” and because the memory clock  211 ,  311  is derived from the MIC clock  209 ,  309 , a memory clock  211 ,  311  is not being supplied to the system memory  202  by the memory controller  201 . Because the memory clock  211 ,  311  is “off”, the system memory  202  is in “self-refresh” mode (i.e., the system memory  202  does not use an external clock in preventing its internal data from being lost). Therefore as of time T 0 , the display FIFO  213  is “full” (or otherwise contains enough data to refresh an entire screen&#39;s worth of visual content), the memory controller&#39;s core logic  208  and graphics controller(s)  216  are in a reduced power consumption state, and, the system memory  202  is in “self refresh” mode. This essentially corresponds to a situation where both the memory controller  201  and the system memory  202  are in reduced power consumption states.  
         [0022]     From time T 0  to T 1  data is read from the display FIFO  213  for the purposes of refreshing the content rendered on the display  205 . During this time period, the memory controller  201  and system memory  202  are in their reduced power consumption states as described above. At time T 1 , however, FIFO state detection logic circuitry  216  detects that the display FIFO  213  state has fallen to a first “watermark level” WM 1 . The WM 1  level essentially indicates that the display FIFO  213  is becoming sufficiently empty and will soon need more data if it is to continue supporting the rendering of new content on the display  205 .  
         [0023]     As such, notice of the WM 1  level being reached is directed from the FIFO state detection logic circuitry  216  to clock control logic circuitry  217  on the memory controller  201 . In response, the clock control logic circuitry  217  “wakes up” the MCC clock  212 ,  312  such that it emits its one or more clock signals. In the particular implementation being discussed herein, the MCC clock  212 ,  312  and the logic circuitry that runs from the MCC clock  212 ,  312  (the front side bus interface logic circuitry  207 , the graphics controller(s)  216  and core logic  208 ) take a longer amount of time to wake up” than the MIC clock  209 ,  309  and the logic circuitry that runs from the MIC clock  209 ,  309  (the system memory interface logic circuitry  206  and the system memory  201  (when in auto-refresh mode)).  
         [0024]     As such, the system memory  202  is allowed to stay in its lower power state (self refresh mode) for a longer period of time (T 0  to T 2 ) than the memory controller core logic circuitry  208  and graphics controller(s)  216  (T 0  to T 1 ). At time T 2 , a second watermark level WM 2  is detected by the FIFO state detection logic circuitry  216 . Notification of the second watermark level WM 2  is sent to the clock control circuitry  217 . In response, the clock control circuitry  216  “wakes up” the MIC clock  209 ,  309 ; which, in turn, causes the memory clock  211 ,  311  to be generated at time T 3 . The generation of the memory clock  211 ,  311  at time T 3  is at least part of the system memory&#39;s exit from self refresh mode and entry into auto refresh mode after the second watermark WM 2  is detected.  
         [0025]     Therefore, after time T 4 , the memory controller  201  and system memory  202  will have both been converted from a lower performance and power consumption state to a higher performance and power consumption state. From time T 4  to T 5 , data is read from the system memory  201  (signified by the data bus  210 ,  310  being “busy”) sufficient to re-fill the display FIFO  213  by time T 5 . At this point, the MCC clock  212 ,  312  and MIC clock  209 ,  309  are turned “off” and the process repeats. Note that from time T 0  to time T 5  data to be processed and displayed is continuously being read from the display FIFO  213  (e.g., if the display FIFO  213  was not refilled between times T 4  and T 5 , it would run out of data by time T 5 ).  
         [0026]     Note also that the particular description above was oriented toward a particular implementation in which the amount of data read from time T 4  and T 5  and the size of the display FIFO  213  corresponds to an entire refresh cycle&#39;s worth of data (i.e., a screen&#39;s worth of data). Said another way, time T 0  to time T 5  corresponds to the refresh cycle time of the display  205  such that there is one display  205  re-fill procedure per display refresh cycle. In alternative implementations there may be less than one display FIFO re-fill per display refresh cycle (e.g., time T 0  to T 5  corresponds to two refresh cycles and the display FIFO  213  is large enough to hold two refresh cycles worth of data), or, more than one display FIFO re-fill per display refresh cycle (e.g., time T 0  to T 5  corresponds to one half of a refresh cycle and the display FIFO  213  is large enough to hold one half of a refresh cycle&#39;s worth of data).  
         [0027]     Note also that, other than activating/deactivating the MCC and MIC clocks as described above, the MCC and MIC clocks themselves may be permitted to continuously operate, but, one or more output clock signals generated from them are “squelched” so as not to reach the circuitry there are designed to time the operation of (e.g., a logic gate could be inserted between the MCC clock circuitry  212  and the core logic circuitry  208  that squelches the core logic&#39;s clock input). Also, given that the display mode process may be performed while the processor(s)  203  are not supposed to send system memory read requests or system memory write requests to the memory controller  201 , additional logic circuitry on the memory controller (not shown in  FIG. 2 ) may be used to detect the operational state(s) of the processor(s)  203  (e.g., through the processor(s) broadcasting of entry into such state(s)) that correspond to this behavior on the part of the processor(s).  
         [0028]      FIG. 4  shows one embodiment of a high level methodology of the processing described above. It can be assumed that data is being continuously read from the display FIFO through the process of  FIG. 4 . According to the process of  FIG. 4 , when a display FIFO is recognized  401  as being below a certain threshold (e.g., the first watermark level WM 1  of  FIG. 3 ), one or more memory controller clocks are enabled or their output clock signals are otherwise permitted to reach the circuitry they are designed to drive  402 . These one or more clocks may drive one or more of: a memory controller&#39;s graphics controller(s), core logic circuitry (or a portion thereof), system memory interface circuitry, front side bus interface circuitry and a system memory. Data to be processed by a display controller and displayed by a display is then read from the system memory and loaded into the FIFO  403 . Once the FIFO state reaches a higher threshold (e.g., it is filled up)  404 , the process returns to monitoring for the FIFO state to reach the lower threshold  401 .  
         [0029]     It is also possible that the front side bus logic circuitry could be replaced with data-link layer and physical layer networking circuitry in computing systems where the processor(s)  203  are coupled to the memory controller  201  by way of a network containing point-to-point links.  
         [0030]      FIG. 2  depicts one embodiment of a memory controller  201  having an integrated graphics controller  216 . Graphics controllers that, architecturally speaking, are not integrated with a memory controller exist and are presently in use, and, may be referred to as discrete graphics controllers.  FIG. 5  shows an embodiment of an implementation of the present teachings that is adapted for a discrete graphics controller  501 .  
         [0031]     A graphics controller, whether integrated with a memory controller or discrete, is typically capable of processing graphics related instructions so that the processor(s) of the corresponding computing system do not have to. That is, a purpose of the graphics controller is to “off-load” graphics related work from the processor(s) so that the processor(s)  103  can entertain other tasks.  
         [0032]     According to the depiction of  FIG. 3 , such instructions are received by the graphics controller  501  (either directly from the processor(s) or indirectly from a memory controller  503 ) through a bus interface  507 . The core logic  508  of the graphics controller  501  is responsible for processing graphics related instructions received through bus interface  507  and writing them into local memory  502 . Here, local memory  502  is often implemented as the graphics controller&#39;s own “private” memory. After the data processed by the graphics controller&#39;s core logic  508  is written into local memory  502 , it is eventually read back from local memory  502  by the core logic  508  which then enters it into the display FIFO  513  of a display controller  504 .  
         [0033]     In this respect, a design and process can be effected which is analogous to that described above with respect to  FIGS. 2, 3  and  4 . Specifically, it is altogether possible that new instructions are not received at bus interface  507  for extended periods of time thereby permitting core logic  508  to be essentially deactivated save for brief moments of time while data is read from local memory  502  and entered into display FIFO  513 , where, the amount of data and the size of FIFO  513  is sufficient to supply an entire display  505  refresh cycle (or, e.g., two display refresh cycles, half a refresh cycle, etc.).  
         [0034]     During the brief moment of time while data is being read from local memory  502 , the graphics controller clock circuitry  512  and memory interface clock circuitry  509  are activated by the clock control circuitry  517  (responsive to one or more watermark levels detected by detection circuitry  516 ) such that, similar to the approach described above with respect to  FIGS. 2, 3  and  4 , the graphics controller  501  and local memory  502  are in a high performance, high power consumption state. After this brief period of time (when display FIFO  513  has been supplied with a sufficient amount of data to feed the display for an extended period of time and the detection circuitry  516  detects this event), the clock control circuitry  501  triggers the deactivation of the graphics controller clock circuitry  512  and the memory interface clock circuitry  509 .  
         [0035]     Note also that embodiments of the present description may be implemented not only within a semiconductor chip but also within machine readable media. For example, the designs discussed above may be stored upon and/or embedded within machine readable media associated with a design tool used for designing semiconductor devices. Examples include a circuit description formatted in the VHSIC Hardware Description Language (VHDL) language, Verilog language or SPICE language. Some circuit description examples include: a behaviorial level description, a register transfer level (RTL) description, a gate level netlist and a transistor level netlist. Machine readable media may also include media having layout information such as a GDS-II file. Furthermore, netlist files or other machine readable media for semiconductor chip design may be used in a simulation environment to perform the methods of the teachings described above.  
         [0036]     Thus, it is also to be understood that embodiments of this invention may be used as or to support a software program executed upon some form of processing core (such as the Central Processing Unit (CPU) of a computer) or otherwise implemented or realized upon or within a machine readable medium. A machine readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine readable medium includes read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; etc.  
         [0037]     In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Technology Category: g