Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 13/279,513, filed Oct. 24, 2011, pending, which is a divisional of U.S. patent application Ser. No. 12/042,518, filed Mar. 5, 2008, now U.S. Pat. No. 8,045,416 issued Oct. 25, 2011, the disclosure of each of which is hereby incorporated herein by this reference in its entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates to semiconductor memory integrated circuits. More particularly, one or more embodiments of the present invention relate to an architecture for reducing the quantity of inputs to a memory device, including synchronous random access memories, such as synchronous dynamic random access memories. 
       BACKGROUND 
       [0003]    Memory devices require a plurality of inputs and outputs through which data enters and exits the memory cells contained therein. Included among the various inputs and outputs are command, addressing and data signals. These signals are used to identify and access data storage locations (e.g., memory cells) within the memory device. As the quantity of memory cells increases, the number of input signals necessary to uniquely identify a memory cell also increases. Specifically, an address bus includes a sufficiently large quantity of address lines for uniquely identifying each of the memory cells in the memory device. Therefore, as the quantity of memory cells increases on the memory device, the quantity of inputs necessary for accessing the memory cells also increases. 
         [0004]    Furthermore, since each of the input and output signals needs to be externally accessible for interfacing with external components such as memory controllers and the like, the periphery around the memory device must remain sufficiently large to accommodate external interconnections (e.g., pins) that are coupled to the input and output signals. As is readily appreciated, an increase in the quantity of interconnection pins to adequately address or select an increased density of memory cells creates a conflict with design motivations of further circuit miniaturization and integration. Therefore, there is a need for a memory device interface architecture that reduces the quantity of external interconnections required for input and output signals without introducing significant delay in accessing the memory cells in a memory device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIGS. 1A and 1B  illustrate a block diagram of an SDRAM circuit. 
           [0006]      FIG. 2  represents an address bus configuration during various memory commands for accessing the memory system described herein. 
           [0007]      FIGS. 3A and 3B  illustrate a block diagram of an SDRAM circuit, in accordance with an embodiment of the present invention. 
           [0008]      FIG. 4  represents an address bus configuration during various memory commands for accessing the memory system, in accordance with an embodiment of the present invention. 
           [0009]      FIG. 5  is a timing diagram illustrating timing signals of a command and address bus of a memory device, in accordance with an embodiment of the present invention. 
           [0010]      FIG. 6  is a timing diagram illustrating timing signals of a command and address bus of a memory device, in accordance with an embodiment of the present invention. 
           [0011]      FIG. 7  is a block diagram of a system, in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    While the various embodiments described herein find application to various types of paged or segmented array architectures, this specification utilizes a synchronous dynamic random access memory (SDRAM) for purposes of illustration. Nevertheless, it will be understood by those of ordinary skill in the art that the various embodiments apply to memory architectures such as video random access memories (VRAMs) synchronous graphic random access memories (SGRAMs), Rambus memory systems, Synchlink memory systems, and double or multiple data rate memories. 
         [0013]    Synchronous memories such as SDRAMs are designed to operate in a synchronous memory system, where input and output signals are synchronized to an active edge of a system clock (one exception in a SDRAM being a clock enable signal as used during power-down and self-refresh modes). The address operations of a SDRAM are somewhat different from those of an asynchronous DRAM. In an asynchronous DRAM, once row and column addresses are issued to the DRAM and the row and column address strobe signals are deactivated, the DRAM&#39;s memory is automatically precharged and available for another access. A SDRAM, on the other hand, requires a separate command to precharge a row of storage cells within a memory array. Assuming one of the memory cells in a SDRAM has been addressed, that page remains active even after the cell has been accessed. This occurs because an internal row address strobe is generated and maintains the active state of the addressed page. As a result, the page remains open until a PRECHARGE command is used to deactivate the open page and put the memory device into a standby mode. 
         [0014]    Thus, to accomplish a SDRAM data transfer operation, an ACTIVE command is issued to register a row address designated by the ADDRESS signals (e.g., A 0 -A 14  for a 2 15 -page memory device), and a memory page is selected to be accessed. Data is then transferred to or from the memory page by registering the column address through a WRITE or READ command, respectively. Other memory pages may be subsequently accessed, but a PRECHARGE command is needed with the present embodiment before registering another row or page in that memory device. As used herein, a “page” is that portion of a row of memory cells that are accessed at a given time, which in some embodiments, could consist of the entire row. Further, a “row” refers to cells whose access devices are commonly coupled, and does not require a particular physical relationship between the cells of the row (e.g., they do not have to be in a straight line or in a particular orientation on a die). Columns may also be similarly configured. 
         [0015]    Conventionally, the width of the ADDRESS bus of the memory device has been determined by the number of rows or pages in the memory device. Generally, the quantity of rows tends to be greater than the quantity of columns in the memory device. As stated, as a memory device increases in density or quantity of memory cells, the quantity of external interconnections (e.g., pins) that are required to implement the input and output interface with the memory device also increases. Furthermore, an increase in the quantity of external interconnections forming the external interface creates further burdens on controllers and other devices that electrically couple with the external interconnections. 
         [0016]    In order to describe the embodiments, it is necessary to go into some detail with respect to one nonlimiting example of a memory system in which the various embodiments find application.  FIGS. 1A and 1B , for example, depict a block diagram of a SDRAM  20  including, for example, storage cells forming a memory array  22  organized in 32,768 rows and thirty-two 8-bit columns. Much of the circuitry of SDRAM  20  is similar to the circuitry in known SDRAMs. Power is supplied to SDRAM  20  through pins V CC  and V SS  (not shown). A system clock signal CLK is provided through a CLK input pin, and a clock enable signal CKE is provided through a CKE pin of SDRAM  20 . The CLK signal activates and deactivates based on the state of the CKE signal. For purposes of explaining the present invention, it is assumed that all input and output signals of SDRAM  20 , with the exception of the CKE signal during power-down and self-refresh modes, are synchronized to the positive-rising edge of the CLK signal. 
         [0017]    A chip select signal (CS*) is input through a CS* input pin. When CS* is low, it enables a command decoder  30 . Command decoder  30  is included as a part of control logic circuitry  32  and receives control signals on a command bus  10 . These control signals on command bus  10  include a row address strobe (RAS*), a column address strobe (CAS*), and a write enable signal (WE*). The command decoder  30  decodes RAS*, CAS*, and WE* to place the control logic circuitry  32  in a particular command operation mode. 
         [0018]    Address bits are provided by inputs A 0 -A 14  for row addresses and inputs A 0 -A 14  are stored in an address register  42  before they are sent to other portions of the SDRAM  20 . During a WRITE operation, data to be stored is supplied to SDRAM  20  through input/output pins DQ 0 -DQ 15 . During a READ operation, data is clocked out of SDRAM  20  through DQ 0 -DQ 15 . An input/output mask signal DQM is provided as an input mask signal for write operations and as an output enable signal during read operations. 
         [0019]    Mode register  34  is a part of control logic circuitry  32  that defines the specific mode of operation of SDRAM  20 . Based on the state of input signals CS*, RAS*, CAS*, and WE*, the mode register  34  will determine whether SDRAM  20  is in an ACTIVE, WRITE, READ, PRECHARGE, or REFRESH mode. 
         [0020]    In conjunction with  FIGS. 1A and 1B ,  FIG. 2  depicts a partial command structure for accessing the memory system described herein. Before any READ or WRITE commands can be issued to a memory array such as that disclosed in the present embodiment, a row in that array is activated. This is accomplished through the ACTIVE command, which is initiated, for example, by low CS* and RAS* signals in combination with high CAS* and WE* signals occurring during the rising edge of the CLK signal. During the ACTIVE command, a value representing the row address is indicated by inputs A 0 -A 14  as illustrated in  FIG. 2  and provided to row address multiplexer  36 , again by way of address register  42 . The row address multiplexer  36 , in turn, provides the row address inputs to latch and decoder circuitry  38  corresponding to the appropriate memory page. Accordingly, the latch and decoder circuitry  38  will latch the row address identified by inputs A 0 -A 14 , decode the row address, and activate one of the memory device&#39;s 32,768 pages or row lines corresponding to that address. According to the present embodiment, a subsequent ACTIVE command to a different page or row in the same memory array  22  can only be issued after the previous active page or row has been closed with a PRECHARGE command. 
         [0021]    In operation, a valid WRITE command is initiated, for example, with the CS*, CAS*, and WE* signals low and the RAS* signal high on the rising edge of a CLK signal. Upon receiving a WRITE command, a column address counter/latch  40  receives through the address register  42  a value representing a column address C 0 -C 7  as indicated by the state of inputs A 0 -A 7 . This value is sent to the column decoder  46  which activates the relevant columns along with the sense amps  50  and I/O gating circuitry. This is accomplished through circuit block  48 , which contains I/O gating, read data latch, and write driver circuitry. The data to be written to the cell addressed by the active row and column lines comes from data signals DQ 0 -DQ 15  of data bus  24  through a data input register  54  as depicted in  FIG. 1B . Circuit block  48 , however, also contains DQM mask logic. As a result, writing to the memory array  22  is subject to the state of the DQM input. Specifically, if the DQM signal is low, the corresponding data will be written to memory. Alternatively, if the DQM is high, the corresponding data inputs will be ignored, and a write to the memory array  22  will not be executed to the particular byte/column location. 
         [0022]    In operation, a valid READ command is used to initiate, for example, a burst read access to an active page or row. The READ command is initiated, for example, with low CS* and CAS* signals and high RAS* and WE* signals on the rising edge of the CLK signal. In response to a READ command, the column address counter/latch  40  receives column address bits from inputs A 0 -A 9  and holds that column address. In response to the next CLK signal after the READ command, the column address counter/latch  40  latches the column address to the appropriate column decoder  46 . The column decoder  46 , in turn, activates the relevant columns in the memory array  22  along with the appropriate sense amps  50  and I/O gating circuitry in circuit block  48 . As known in the art, the sense amps  50  and the I/O gating circuitry in circuit block  48  operate to sense the data stored in the cells addressed by the active row and column decoder lines and to provide the selected sixteen bits of data from the chosen memory array to a data output register  52  ( FIG. 1B ). With each progressive clock cycle, the column address counter/latch  40  increases the address by one, and the reading cycle begins again with the selected memory location. This cycle continues until the burst read access is completed or another command has been initiated to halt the burst READ. Data addressed by the READ command appears on pins DQ 0 -DQ 15  and is subject to the status of the DQM signal. Specifically, in the present embodiment, DQM is low for DQ 0 -DQ 15  to provide valid data. 
         [0023]    The control logic initiates a PRECHARGE command in response to low CS*, WE* and RAS* signals along with a high CAS* signal on the rising edge of a CLK signal. The PRECHARGE command deactivates and precharges the memory array  22  at the time PRECHARGE is initiated. This makes the address bits a “don&#39;t care” (illustrated as reserved “res” bits) during the PRECHARGE command as illustrated in  FIG. 2 . Thus, a previously accessed row in the memory array  22  can be deactivated and precharged so that another page or row in that memory array  22  may be refreshed or activated. However, because a page or row in the memory array  22  activates in response to an ACTIVE command and remains active until receiving a PRECHARGE command, consecutive READ and WRITE commands to the same page or row in the memory array  22  do not require intervening PRECHARGE commands. Once the memory array  22  has been precharged, it is in an idle state and needs to be reactivated before another READ or WRITE command is issued to the memory array. 
         [0024]    A REFRESH command is also used during normal operation of the SDRAM  20  and is initiated, for example, by registering CS*, RAS* and CAS* low with WE* high. The REFRESH command is non-persistent, and therefore, in the present embodiment, needs to be issued each time a refresh is required. Addressing is accomplished through the use of a refresh controller (not shown) and a refresh counter  56  in a known manner. This also makes the address bits a “don&#39;t care” (illustrated as reserved “res” bits) during the REFRESH command as illustrated in  FIG. 2 . The exemplary SDRAM  20  depicted in  FIGS. 1A and 1B  requires one REFRESH cycle for every page or row, for example, 32,768 REFRESH cycles every refresh period of the memory array  22 . As a result, the SDRAM  20  provides a distributed REFRESH command once every refresh period to ensure that each row is properly refreshed. Alternatively, 32,768 REFRESH commands could be issued in a burst once every refresh period. 
         [0025]    As apparent in  FIG. 1A , an increase in the density of memory array  22  results in an increase in the quantity of external interconnections (e.g., pins) for routing address inputs A 0 -A 14 . Such an increase in the quantity of interconnections undesirably results in an increase in the size of the overall memory device and the dimension of the interface that is supported by other interfacing components, such as other members of a chip set. Accordingly, the various embodiments provide a method and apparatus for reducing the quantity of external interconnections (e.g., pins) that are used to support a memory device interface without significantly impacting the performance of the memory device. 
         [0026]      FIGS. 3A and 3B  depict a block diagram of a representative memory system including an SDRAM, in accordance with an embodiment of the present invention. SDRAM  120  includes, for example, storage cells forming a memory array  122  organized in 32,768 rows and thirty-two 8-bit columns. Like the embodiment described above, a system clock signal CLK is provided through a CLK input pin, and a clock enable signal CKE is provided through a CKE pin of SDRAM  120 . Furthermore, a chip select signal (CS*) is input through a CS* input pin. When CS* is low, for example, it enables a command decoder  130 . Command decoder  130  is included as a part of control logic circuitry  132  and receives control signals. These control signals include a row address strobe (RAS*), a column address strobe (CAS*), and a write enable signal (WE*). The command decoder  130  decodes RAS*, CAS*, and WE* to place the control logic circuitry  132  in a particular command operation mode, as described above. 
         [0027]    With respect to  FIG. 1A , the address bits included an interconnection pin for each of the address signals, for example address signals A 0 -A 14 , requiring a total of fifteen dedicated interconnection pins. In contrast, the embodiment illustrated in  FIG. 3A  requires a lesser number of address interconnection pins, for example, nine dedicated address signals, namely, A 0 /A 9 , A 1 /A 10 , A 2 /A 11 , A 3 /A 12 , A 4 /A 13 , A 5 /A 14 , A 6 , A 7 , and A 8 . While external interconnections (e.g., pins) are shared between a portion of the address signals, all of the address signals A 0 -A 14  are internally provided for page or row addresses. During a WRITE operation, data to be stored is supplied to SDRAM  120  through input/output pins DQ 0 -DQ 15 . During a READ operation, data is clocked out of SDRAM  120  through DQ 0 -DQ 15 . An input/output mask signal DQM is provided as an input mask signal for write operations and as an output enable signal during read operations. 
         [0028]    According to various embodiments, the activation process is partitioned into two phases. Generally, one phase provides an upper portion of the address signals to the memory device from a controller while a second phase provides the lower portion of the address signals to the memory device from a controller. While increasing the activation process to include an additional phase may appear to increase the duration of the activation process thereby introducing latency, various embodiments generally embed one of the phases in an existing command such as a PRECHARGE or REFRESH without introducing any additional latency in the activation process. Specifically, various embodiments include an ACTIVE_UPPER (ACT_U) command and an ACTIVE_LOWER (ACT_L) command. These commands are decoded by a mode register  134  is a part of control logic circuitry  132  that defines the specific mode of operation of SDRAM  120 . Based on the state of input signals CS*, RAS*, CAS*, and WE*, the mode register  134  will determine whether the SDRAM  120  is in an ACTIVE_UPPER, ACTIVE_LOWER, WRITE, READ, PRECHARGE, or REFRESH mode. 
         [0029]    According to various embodiments, the ACTIVE_UPPER, PRECHARGE and REFRESH commands transmit the upper portion of the page or row address, which is latched within the SDRAM  120  during first phase of the activation process. Since the conventional PRECHARGE and REFRESH commands are sparsely populated in the concurrent signals input on the address bus, various embodiments utilize unused portions of the address bus for inputting the upper portion of the address signals utilizing these commands. 
         [0030]    In conjunction with  FIGS. 3A and 3B ,  FIG. 4  depicts a partial command structure for accessing the memory system, according to the various embodiments described herein. As stated, in the present embodiment, before any READ or WRITE command can be issued to a memory array, a row in that array must be activated. This is accomplished through a two-cycle activation process. For an activation process following a period of memory array inactivity, the ACTIVE_UPPER command, which is initiated by a combination of control signals such as CS*, RAS*, CAS* and WE* signals occurs during the rising edge of the CLK signal. During the first phase of the activation process, the ACTIVE_UPPER command and address values representing the upper portion of the page or row address, for example, address inputs A 9 -A 14 , as illustrated in  FIG. 4 , are sent to upper address portion register  144  through address register  142  and latched into the upper address portion register  144 . 
         [0031]    In the second phase of the activation process, the ACTIVE_LOWER command, which is initiated by a combination of control signals such as CS*, RAS*, CAS* and WE* signals, occurs during the rising edge of the CLK signal. During the second phase of the activation process, the ACTIVE_LOWER command and address values representing the lower portion of the page or row address, for example, address inputs A 0 -A 8  and are sent to row address multiplexer  136 , again by way of address register  142 . The row address multiplexer  136 , in turn, provides the lower portion of page or row address inputs to latch and decoder circuitry  138 , corresponding to the appropriate memory page. Accordingly, the latch and decoder circuitry  138  will latch the upper and lower portions of the row address identified by inputs A 0 -A 14 , decode the row address, and activate one of the memory device&#39;s 32,768 pages or row lines, for example, corresponding to that address. According to the present embodiment, a subsequent activation process to a different page or row in the same memory array  122  is issued after the previous active page or row has been closed with a PRECHARGE command. 
         [0032]    In operation, a valid WRITE command is initiated, for example, with the CS*, CAS*, and WE* signals low and the RAS* signal high on the rising edge of a CLK signal. Upon receiving a WRITE command, a column address counter/latch  140  receives through the address register  142  a value representing a column address as indicated by the state of inputs A 0 -A 7 . This value is sent to a column decoder  146  which activates the relevant columns along with the sense amps  150  and I/O gating circuitry. This is accomplished through circuit block  148 , which contains I/O gating, read data latch, and write driver circuitry. The data to be written to the cell addressed by the active page or row and column lines comes from data signals DQ 0 -DQ 15  of data bus  124  through a data input register  154  as depicted in  FIG. 3B . Circuit block  148 , however, also contains DQM mask logic. As a result, writing to the memory array  122  is subject to the state of the DQM input. Specifically, if the DQM signal is low, the corresponding data will be written to memory. Alternatively, if the DQM is high, the corresponding data inputs will be ignored, and a WRITE will not be executed to the particular byte/column location. 
         [0033]    In operation, a valid READ command is used to initiate, for example, a burst read access to an active page or row. The READ command is initiated, for example, with low CS* and CAS* signals and high RAS* and WE* signals on the rising edge of the CLK signal. In response to a READ command, the column address counter/latch  140  receives column address bits from inputs A 0 -A 9  and holds that column address. In response to the next CLK signal after the READ command, the column address counter/latch  140  latches the column address to the appropriate column decoder  146 . The column decoder  146 , in turn, activates the relevant columns in the memory array  122  along with the appropriate sense amps  150  and I/O gating circuitry in circuit block  148 . As known in the art, the sense amps  150  and the I/O gating circuitry in circuit block  148  operate to sense the data stored in the cells addressed by the active row and column decoder lines and to provide the selected sixteen bits of data to a data output register  152  ( FIG. 3B ). With each progressive clock cycle, the column address counter/latch  140  increases the address by one, and the reading cycle begins again with the selected memory location. This cycle continues until the burst is completed or another command has been initiated to halt the burst READ. Data addressed by the READ command appears on pins DQ 0 -DQ 15  subject to the status of the DQM signal. Specifically, in the present embodiment, DQM is low for DQ 0 -DQ 15  to provide valid data. 
         [0034]    The control logic initiates a PRECHARGE command in response to low CS*, WE* and RAS* signals along with a high CAS* signal on the rising edge of a CLK signal. The PRECHARGE command deactivates and precharges the memory array  122  at the time PRECHARGE is initiated. Since a PRECHARGE command is issued in anticipation of a subsequent change in page or row in the memory array, the address bits in the present embodiments are utilized to concurrently send the upper portion of the memory address A 9 -A 14 , for example, as illustrated in  FIG. 4 . Thus, a previously accessed row in the memory array  122  can be deactivated and precharged so that another page or row in that memory array  122  may be refreshed or activated. However, because a page or row in the memory array  122  activates in response to an activate command and remains active until receiving a PRECHARGE command, consecutive READ and WRITE commands to the same page or row in the memory array  122  do not require intervening PRECHARGE commands. Once the memory array  122  has been precharged with the upper portion of the memory address A 9 -A 14 , for example, and latched into the upper address portion register  144 , in the present embodiment, the memory array is in an idle state and is reactivated with an ACTIVE_LOW command including the lower portion of the memory address A 0 -A 8 , for example, before another READ or WRITE command is issued to the memory array. 
         [0035]    A REFRESH command is also used during normal operation of the SDRAM  120  and is initiated by asserting CS*, RAS* and CAS* low with WE* high. The REFRESH command is non-persistent, and therefore in the present embodiment, is issued each time a refresh is required. Addressing is accomplished through the use of a refresh controller (not shown) and a refresh counter  156  in a known manner. Since a REFRESH command is issued in anticipation of a subsequent change in page or row in the memory array, the address bits in the present embodiments are utilized to concurrently send the upper portion of the memory address A 9 -A 14 , for example, as illustrated in  FIG. 4 . The SDRAM  120  depicted in  FIGS. 3A and 3B  requires one REFRESH cycle for every page or row, for example, 32,768 REFRESH cycles every refresh period of the memory array  122 . 
         [0036]    As apparent in  FIG. 3A , an increase in the density of memory array  122  does not necessarily result in an increase in the quantity of interconnections (e.g., pins) for routing address inputs A 0 -A 14  since portions of the address inputs are sent in reserved (“res”) or “don&#39;t care” fields of existing commands. Accordingly, various embodiments provide a method and apparatus for reducing the quantity of interconnections (e.g., pins) that are necessary to support a memory device interface without significantly impacting the performance of the memory device. 
         [0037]      FIG. 5  is a timing diagram  200  illustrating an initial activation following an idle period, in accordance with an embodiment. As stated, when a page or row of memory cells is accessed, in the present embodiment, an ACTIVE command for that page or row must first be asserted. Various embodiments utilize a two-cycle activation process. For an activation process following a period of memory array inactivity, any ACTIVE_UPPER command  202  occurs during the first phase of the activation process. The ACTIVE_UPPER command  202 , on the command bus  110  of  FIG. 3A , is concurrently issued with address values  204 , on the address bus  112  of  FIG. 3A , representing the upper portion of the page or row address. The address inputs A 9 -A 14 , for example, are sent to upper address portion register  144  through address register  142  and latched into the upper address portion register  144  of  FIG. 3A . 
         [0038]    In the second phase of the activation process, the ACTIVE_LOWER command  206  occurs during the second phase of the activation process. The ACTIVE_LOWER command  206 , on the command bus  110  of  FIG. 3A , is concurrently issued with address values  208 , on the address bus  112  of  FIG. 3A , representing the lower portion of the page or row address. The address inputs A 0 -A 8 , for example, are sent to row address multiplexer  136 , again by way of address register  142  of  FIG. 3A . The row address multiplexer  136 , in turn, provides the lower portion of page or row address inputs to latch and decoder circuitry  138  corresponding to the appropriate memory page. Accordingly, the latch and decoder circuitry  138  will latch the upper and lower portions of the row address inputs identified by inputs A 0 -A 14 , decode the row address, and activate one of the memory device&#39;s 32,768 pages or row lines corresponding to that address. Once the page or row of lines are activated, one or more WRITE or READ commands  210 - 214  are sequentially issued on the command bus  112  of  FIG. 3A  with column C 0 -C 7  values  216 - 220  representing the bytes of data along the page of memory cells in the memory device being concurrently issued on the address bus  112  of  FIG. 3A . 
         [0039]    In the precharge process, a PRECHARGE command  222  occurs and deactivates and precharges the memory array  122  of  FIG. 3A . Since a PRECHARGE command  222  is issued in anticipation of a subsequent change in page or row in the memory array, the address values  224 , on the address bus  112  of  FIG. 3A , are concurrently issued and represent the upper portion of the page or row address of the next page that is to be written to or read from. As stated, the address inputs A 9 -A 14 , for example, are sent to upper address portion register  144  through address register  142  and latched into the upper address portion register  144  of  FIG. 3A . Therefore, the PRECHARGE command  222  in various embodiments serves as an ACTIVE_UPPER command  202  to provide the upper portion of the page or row address of the next page of memory of the activation process. 
         [0040]    In the second phase of the activation process, the ACTIVE_LOWER command  226  occurs during the second phase of the activation process. The ACTIVE_LOWER command  226 , on the command bus  110  of  FIG. 3A , is concurrently issued with address values  228 , on the address bus  112  of  FIG. 3A , representing the lower portion of the page or row address of the next page of memory to be activated. Once the page or row of lines of the next page are activated, one or more WRITE or READ commands  230  is issued on the command bus  112  of  FIG. 3A  with column C 0 -C 7  values  232  representing the bytes of data along the page of memory cells in the memory device being concurrently issued on the address bus  112  of  FIG. 3A . 
         [0041]      FIG. 6  is a timing diagram  300  illustrating an activation following a refresh process, in accordance with an embodiment. As stated, in the present embodiment, when a page or row of memory cells is accessed, an activation command for that page or row must first be asserted. Various embodiments utilize a two-cycle activation process. For an activation process following a refresh process, a REFRESH command  302  is utilized as the first phase of the activation process. The REFRESH command  302 , on the command bus  110  of  FIG. 3A , is concurrently issued with address values  304 , on the address bus  112  of  FIG. 3A , representing the upper portion of the page or row address. The address inputs A 9 -A 14 , for example, are sent to upper address portion register  144  through address register  142  and latched into the upper address portion register  144  of  FIG. 3A . The refresh process then continues to completion. 
         [0042]    In the second phase of the activation process, an ACTIVE_LOWER command  306  occurs during the second phase of the activation process. The ACTIVE_LOWER command  306 , on the command bus  110  of  FIG. 3A , is concurrently issued with address values  308 , on the address bus  112  of  FIG. 3A , representing the lower portion of the page or row address. The address inputs A 0 -A 8 , for example, are sent to row address multiplexer  136 , again by way of address register  142  of  FIG. 3A . The row address multiplexer  136 , in turn, provides the lower portion of page or row address inputs to latch and decoder circuitry  138  corresponding to the appropriate memory page. Accordingly, the latch and decoder circuitry  138  will latch the upper and lower portions of the row address identified by inputs A 0 -A 14 , decode the row address, and activate one of the memory device&#39;s 32,768 pages or row lines corresponding to that address. Once the page or row of lines are activated, one or more WRITE or READ commands  310 - 314  are sequentially issued on the command bus  110  of  FIG. 3A  with column C 0 -C 7  values  316 - 320  representing the bytes of data along the page of memory cells in the memory device being concurrently issued on the address bus  112  of  FIG. 3A . 
         [0043]    In the precharge process, a PRECHARGE command  322  occurs and deactivates and precharges the memory array  122  of  FIG. 3A . Since a PRECHARGE command  322  is issued in anticipation of a subsequent change in page or row in the memory array, address values  324 , on the address bus  112  of  FIG. 3A , are concurrently issued and represent the upper portion of the page or row address of the next page that is to be written to or read from. As stated, the address inputs A 9 -A 14 , for example, are sent to upper address portion register  144  through address register  142  and latched into the upper address portion register  144  of  FIG. 3A . Therefore, the PRECHARGE command  322  in various embodiments also serves like the REFRESH command  302  or an ACTIVE_UPPER command  202  of  FIG. 5  to provide the upper portion of the page or row address of the next page of memory of the activation process. 
         [0044]    In the second phase of the activation process, the ACTIVE_LOWER command  326  occurs during the second phase of the activation process. The ACTIVE_LOWER command  326 , on the command bus  110  of  FIG. 3A , is concurrently issued with address values  328 , on the address bus  112  of  FIG. 3A , representing the lower portion of the page or row address of the next page of memory to be activated. Once the page or row of lines of the next page are activated, one or more WRITE or READ commands  330  is issued on the command bus  112  of  FIG. 3A  with column C 0 -C 7  values  332  representing the bytes of data along the page of memory cells in the SDRAM  120  being concurrently issued on the address bus  112  of  FIG. 3A . 
         [0045]      FIG. 7  illustrates an embodiment of an electronic system  400  that incorporates the SDRAM  120 , or some other memory device including an embodiment of the memory device command structure, for reducing the quantity of inputs of a memory device as described herein. The electronic system  400  includes a processor  402  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor  402  includes a processor bus  404  that conventionally includes an address bus, a control bus, and a data bus. In addition, the electronic system  400  includes one or more input devices  414 , such as a keyboard or a mouse, coupled to the processor  402  to allow an operator to interface with the electronic system  400 . As is conventional, the electronic system  400  also includes one or more output devices  416  coupled to the processor  402 , such output devices typically being a printer or a video terminal. One or more data storage devices  418  are also coupled to the processor  402  to store data or retrieve data from external storage media (not shown). The processor  402  is also coupled to a cache memory  426  and to the SDRAM  120  through a memory controller  430 . The memory controller  430  includes a bus coupled to the address bus  112  ( FIG. 3A ) to couple row addresses and column addresses to the memory device  120 , as previously explained. The memory controller  430  also includes a control bus that couples control signals to a command bus  110  ( FIG. 3A ) of the SDRAM. The data bus  124  ( FIG. 3B ) of the memory device  120  is coupled to the data bus of the processor  402 , either directly or through the memory controller  430 . The memory controller  430  applies appropriate control signals (e.g., ACTIVE_UPPER, ACTIVE_LOWER, WRITE, READ, PRECHARGE, or REFRESH) to the memory device  120  to cause the memory device  120  to operate as described hereinabove. 
         [0046]    Although the present invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims and their legal equivalents.

Technology Category: g