Patent Document

BACKGROUND 
     This invention relates generally to the fabrication of integrated circuits and, particularly, to the fabrication of integrated circuits with extremely low dielectric constants. 
     Low dielectric constant materials are used as interlayer dielectrics in semiconductor devices to reduce the RC delay and improve device performance. As device sizes continue to shrink, the dielectric constant of the material between metal lines must also decrease to maintain the improvement. The eventual limit for dielectric constant is k=1, which is the value for a vacuum. This can only be obtained by producing a void space between metal lines, equivalent to creating a so-called air gap. The air itself has a dielectric constant very near 1. 
     One major issue facing air gap technology is how to remove sacrificial material to facilitate multi-layer structures. Plasmas may be destructive to the metal lines. Wet etches have many problems including capillary forces that can break the lines apart, difficulty in removing material from small features, and difficulty in removing the wet etch chemical once it has been introduced. Thermal decomposition presents a challenge in that the sacrificial material must remain stable during high temperature fabrication steps, but then decompose rapidly at temperatures that will not destroy the rest of the device. 
     Thus, there is a need for better ways to form openings within integrated circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an enlarged cross-sectional view of one embodiment of the present invention; 
     FIG. 2 is an enlarged cross-sectional view at an early stage of manufacturing the embodiment as shown in FIG. 1 in accordance with one embodiment of the present invention; 
     FIG. 3 is an enlarged cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention; 
     FIG. 4 is an enlarged cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention; 
     FIG. 5 is an enlarged cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention; 
     FIG. 6 is an enlarged cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention; 
     FIG. 7 is an enlarged cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention; 
     FIG. 8 is an enlarged cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention; and 
     FIG. 9 is an enlarged cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention; 
    
    
     DETAILED DESCRIPTION 
     Referring to FIG. 1, a multilevel integrated circuit device  10 , according to one embodiment of the present invention, includes a first level  12  that includes a substrate  100 , an ultraviolet absorbing etch stop/diffusion layer  104 , a via-level interlayer dielectric  105 , open areas or air gaps  109 , metal lines  102 , and a hard mask  103 . 
     A second layer  14  may include a via-level interlayer dielectric  105   a , an air gap  109   a , a metal line  102   a , and a hard mask  103   a . Of course, additional layers may be used in some embodiments of the present invention. 
     As indicated in FIG. 1, the air gaps  109 ,  109   a  may be formed within the semiconductor structure. These air gaps then provide a very low dielectric constant close to or equal to one in some embodiments of the present invention. Thus, the air gaps  109  isolate between lines in the same layer, reducing line-to-line capacitance and, therefore, cross-talk and RC delays. 
     The manufacture of the device  10 , shown in FIG. 1, may begin with the layer  12  as indicated in FIG. 2 in one embodiment. An ultraviolet absorbing etch stop/diffusion layer  104  may be formed on a semiconductor substrate  100 . A via-level interlayer dielectric may be formed over the etch stop/diffusion layer  104 . An ultraviolet sensitive sacrificial material  101  may be formed on top of the dielectric  105 . The material  101  may be a polyketoester, polyketoamide, or any other material that decomposes readily upon exposure to ultraviolet light. For example, the material  101  may be polyketoester-polyphenylene or polyketoamide-polyphenylene block copolymer. 
     Ultraviolet light decomposes polymers that contain certain ketone groups. In one embodiment, the material  101  may include the ketone groups incorporated into a cross-linked aromatic polymer to produce a thermally stable material that is susceptible to degradation by ultraviolet light. Additionally, oxygen may be used in combination with ultraviolet light to aid decomposition through oxidation by O 2  or ozone. Ozone is a powerful oxidant that is formed when ultraviolet light interacts with O 2 . 
     The hard mask  103  may be formed on top of the material  101 . The hard mask  103  may be porous or non-porous. The resulting structure is then patterned and etched to form metal lines  102  as indicated in FIG.  2 . The structure shown in FIG. 2 may be described as a dual damascene structure which forms the layer  12  of FIG.  1 . 
     Moving to FIG. 3, the sacrificial material  101  is removed through the hard mask  103  by exposing the structure  12  to ultraviolet light. This may be done in the presence of O 2  in some embodiments. This results in the formation of the air gaps  109 . In some embodiments, the destabilized material  101  exhausts through the hard mask  103  which may be porous in some embodiments. In other embodiments, suitable openings may be provided to exhaust the decomposed material. 
     Turning to FIG. 4, atop the layer  12  is the ultraviolet absorbing etch stop/diffusion barrier  104   a , the via-level interlayer dielectric  105   a , the ultraviolet sensitive sacrificial material  101 , the hard mask  103   a , and the ultraviolet absorbing etch stop/diffusion layer  104   b  that form the upper layer  14  in accordance with one embodiment of the present invention. The light absorbing layer  104   b  protects the sacrificial material  101  during patterning of the upper layer  14 . 
     As shown in FIG. 5, an opening  111  is patterned in the etch stop/diffusion layer  104   b . Then, the photoresist  106  is deposited, filling the trench  111  formed in the etch stop/diffusion layer  104   b . Next, the photoresist  106  is patterned and removed to form the trench  108 . As indicated at  110 , some of the sacrificial material  101  is exposed to the ultraviolet light during photolithography. However, the material  110  will be removed completely during a subsequent trench etch anyway. 
     The hard mask  103   a  is not light absorbing since sacrificial material  101  would be removed through it in subsequent steps. The hard mask  103   a  remains for mechanical support of upper layers. Through the imposition of the layers  105   a  and  104   b , the region  110  is appropriately shaped to be part of a larger area that must be entirely removed when an L-shaped metal line  102  is formed through the material  101  and the layers  105   a  and  104   b.    
     As shown in FIG. 6, the trench  108  is utilized to expose an additional region  117  which is then etched all the way down to the etch stop/diffusion barrier  104   a  thereafter. The resulting trench  117  is caused to extend through the hard mask  103   a  through the exposed portion  110 , the layer  105   a , and stopping on the etch stop/diffusion barrier  104   a . Next, the photoresist is removed. An etch is done which widens the opening  117  just created by extending through the hard mask  103   a  and the rest of the exposed material  110  stopping on the layer  104   a , as shown in FIG.  7 . An etch is also done through the hard mask  104   a . As shown in FIGS. 7 and 8, this creates an L-shaped opening for the metal line  102   a  having a wider upper portion  118  and a narrower lower portion  117 . 
     Next, the metal  102   a  is deposited to fill the opening portions  117  and  118 , overlying the top of the layer  103   a , as shown in FIG.  8 . In one embodiment, the metal may be copper. Thus, a barrier, seed, and copper may be deposited in one embodiment of the present invention. 
     Referring to FIG. 9, following a chemical mechanical planarization, in accordance with one embodiment of the present invention, the metal line  102   a  is formed generally having an upper surface coincident with the upper surface of the hard mask  103   a . Then, the sacrificial material  101  is removed through the hard mask  103   a  by exposing it to ultraviolet light to form the structure shown in FIG.  1 . 
     In some embodiments of the present invention, the sacrificial materials are more stable toward normal thermal processing in device fabrication than those utilized in connection with thermally decomposing material. Plasma exposure to metal lines may be avoided. There are no issues from wet etching such as capillary action and surface tension. 
     While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Technology Category: h