Patent Document

FIELD OF INVENTION 
   The present invention relates in general to mixed analog-digital circuit techniques, and in particular, to clock management circuits and methods for reducing noise in mixed-signal systems. 
   BACKGROUND OF INVENTION 
   Many audio applications, such as audio analog to digital converters (ADCs) and audio encoder-decoders (CODECs), utilize a serial data port to transmit digitized audio data to other devices in a system. A typical serial data port outputs bits of a serial audio data ( SDATA ) stream on the selected edges of an associated serial clock ( SCLK ) signal. In a stereo system, two channels of audio data are time-multiplexed onto the  SDATA  stream with a left-right clock ( LRCK ) signal. A master clock ( MCLK ) signal, which is typically received from an external source, is divided-down to generate internal  MCLK  signals, which time the operations of the various internal circuits. Advantageously, the utilization of serial ports minimizes the number of pins and associated on-chip driver circuitry. 
   A typical serial data port can operate in either a master mode or a slave mode. In the master mode, the  SCLK  and  LRCK  clock signals are generated internally, in response to the received  MCLK  signal, and output to the destination of the  SDATA  stream. In the slave (asynchronous) mode, the  SCLK  and  LRCK  clock signals are received from the destination of the  SDATA  stream. 
   In an ADC operating in the slave mode, the analog input signal is typically sampled on the rising edge of an internal  MCLK  signal, which may have an arbitrary phase relationship with the  SCLK  signal. If the digital data at the  SDATA  output transitions after the analog data has been sampled at the analog inputs, no noise problems typically result. However, if the digital output data transitions slightly before the analog data has been sampled, then noise can couple into other circuitry on-chip, particularly the analog circuitry, thereby degrading the quality of the output signal. This problem is particularly acute when an ADC is operating in response to an  SCLK  signal frequency which is close to, or the same as, the frequency of the internal  MCLK  signal. In this case, every falling edge of  SCLK  may cause a noisy transition at the  SDATA  output just prior to analog sampling at the next rising edge of the  MCLK  signal. 
   Typical serial audio systems have utilized retiming circuits to delay or otherwise retime  SCLK  signal such that the digital data transitions at the  SDATA  output occur after the critical sampling edges of the associated  MCLK  signal. However, this technique has not performed well, especially when the frequency of the  SCLK  signal approaches that of the  MCLK  signal. In particular, as the frequency of the  SCLK  signal approaches the frequency of the  MCLK  signal, the timing window within which the  SCLK  signal can be retimed becomes small. If  SCLK  signal, and hence the data at the  SDATA  out, is delayed beyond this timing window, a setup time violation may occur at the destination device, resulting in the reception of incorrect data. 
   Consequently, new techniques are required for reducing noise at the serial output of and ADC operating in the slave mode. Such techniques should be particularly applicable to ADCs in which the  SCLK  signal frequency approaches the frequency of the associated  MCLK  signal. 
   SUMMARY OF INVENTION 
   The principles of the present invention are embodied in circuits and methods for clock signal management, which assist in the minimization of on-chip noise in mixed-signal integrated circuits. According to one representative embodiment, clock signal control circuitry is disclosed which includes a selector for selecting between a first clock signal and an inverse of the first clock signal. A phase detector determines a phase relationship between the first clock signal and the second clock signal and in response causes the selector to select between the first clock signal and the inverse of the first clock signal. 
   Embodiments of the present principles are particularly advantageous an an input signal is sampled with a clock signal and the resulting output signal is output from an output driver with another clock signal. Advantageously, these principles ensure that the sampling and output operations are sufficiently spaced in time to minimize sampling of noise generated by the output driver. The inventive concepts are particularly advantageous when applied to audio integrated circuits operating in a slave mode, in which a master clock signal sampling the input stream and a serial clock signal driving the output stream are received from an external device with an arbitrary phase relationship. For example, when analog audio input data is sampled on the rising edges of the master clock signal and digital data are output on the falling edges of the serial clock signal, embodiments of the inventive concepts ensure that the falling edges of the serial clock signal and the rising edge of the master clock signal are spaced in time such that noise coupling from the digital output driver to the analog input circuitry is minimized. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a high level block diagram of a single-chip audio analog-to-digital converter (ADC) suitable for demonstrating the principles of the present invention; 
       FIG. 2  is a high level block diagram of serial port timing circuitry including a clock phase inverter circuit embodying the principles of the present invention and suitable for controlling the phase relationship between the serial clock ( SCLK ) and master clock ( MCLK ) signals shown in  FIG. 1 ; 
       FIG. 3  is a block diagram of one exemplary implementation of the  MCLK / SCLK  phase detector shown in  FIG. 2 ; 
       FIGS. 4A–4C  illustrate representative phase relationships between the  MCLK  and  SCLK  signals in which the  MCLK  signal is not inverted by the clock phase inverter circuit  FIG. 2 ; 
       FIGS. 4D–4F  illustrate representative phase relationships between the  MCLK  and  SCLK  signals in which the  MCLK  signal is inverted by the clock phase inverter circuit  FIG. 2 ; 
       FIG. 5  is a block diagram of an alternate  MCLK / SCLK  phase detector embodying the principles of the present invention; 
       FIGS. 6A–6C  illustrate exemplary phase relationships between the  MCLK  and  SCLK  signals in which the  MCLK  signal is not inverted by the alternate  MCLK / SCLK  phase detector of  FIG. 5 ; 
       FIG. 6D  illustrates exemplary phase relationships between the  MCLK  and  SCLK  signals in which the  MCLK  signal is inverted by the alternate  MCLK / SCLK  phase of  FIG. 5 ; 
       FIG. 7  is a block diagram of exemplary MCLK selection circuitry suitable for utilization in the clock phase inverter circuit of  FIG. 2 , 
       FIG. 8  is a block diagram of representative control signal blocking circuitry suitable for utilization in the clock phase inverter circuit of  FIG. 2 ; and 
       FIG. 9  is a timing diagram illustrating the operation of the MCLK selection circuit of  FIG. 7  and the control signal blocking circuitry of  FIG. 8 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in  FIGS. 1–9  of the drawings, in which like numbers designate like. 
     FIG. 1  is a high level functional block diagram of a single-chip audio analog-to-digital converter (ADC)  100  suitable for describing the principles of the present invention. ADC  100  is only one of a number of possible applications in which the principles can advantageously be utilized. Other examples include general purpose ADCs, digital to analog converters (DACs), and encoder-decoders (Codecs). 
   ADC  100  includes n-number of conversion paths, two of which,  101   a  and  101   b , are shown for reference, for converting n-number of channels of analog audio data respectively received at left and right analog differential inputs AINi+/−, where i is the channel number from 1 to n. The analog inputs for each channel are passed through an input gain stage  110  and then to a delta-sigma modulator  102 . 
   Each delta-sigma modulator  102  is represented in  FIG. 1A  by a summer  102 , low-pass filter  104 , comparator (quantizer)  105  and a DAC  106  in the feedback loop. The outputs from the delta-sigma modulators are passed through a decimation filter  107 , which reduces the sample rate, and a high pass filter  108 . 
   The resulting digital audio data are output through a single serial port  SDATA  of serial output interface  109 , timed with a serial clock ( SCLK ) signal and a left-right clock ( LRCK ) signal. In the slave mode, the  SCLK  and  LRCK  signals are generated externally and input to converter  100 , along with the  MCLK  signal. In the master mode, the  SCLK  and  LRCK  signals generated on-chip, along with the associated data, in response to a received master clock  MCLK.    
     FIG. 2  is a high level block diagram of serial port timing circuitry  200 , according to one embodiment of the inventive principles. Serial port timing circuitry  200  includes an inverter  201  which generates the inverted  MCLK  signal,  MCLK   —   INV , an  MCLK / SCLK  phase detector  202 , and a multiplexer  203 . Generally, MCLK/ SCLK  phase detector  202  and multiplexer  203  select either the received  MCLK  signal or the  MCLK   —   INV  signal as an  MCLK   —   OUT  signal which provides a sufficient time window between analog sampling and transitions of the  SDATA  output signal. In particular, when the  SCLK  and  MCLK  signals are within a window around zero (0) degrees out-of-phase, the non-inverted  MCLK  signal is selected as the  MCLK   —   OUT  signal. Otherwise, when the  SCLK  and  MCLK  signals are within a complementary window around one hundred and eighty (180) degrees out-of-phase, the  MCLK   —   INV  signal is selected as the  MCLK   —   OUT  signal. The  MCLK   —   OUT  signal is then presented to analog clock generator  204  to generate the corresponding analog clocks driving the analog circuitry of ADC  100  shown in  FIG. 1 , as well as passed to the digital circuitry  205  of ADC  100 , to time operations in the digital domain. 
   One exemplary implementation of  MCLK / SCLK  phase detector  202  is shown in further detail in  FIG. 3 . In this embodiment, the true (un-delayed)  SCLK  signal is sampled in a first D flip-flop  302   a  as the signal  SCLK   —   S   0 . A delayed version of the  SCLK  signal,  SCLK   —   D   1 , is generated by a delay circuit  301  and sampled onto a second D flip-flop  302   b  as the  SCLK   —   S   1  signal. The delay introduced by delay circuitry  301  one sets the window between the edges of the  SCLK  and  MCLK  signals in which the  MCLK  signal must be inverted. Specifically, if the  SCLK  signal phase relationship with the  MCLK  signal is close to either zero (0) or one hundred and eighty (180) degrees, then  MCLK / SCLK  phase detector  202  detects either rising or falling edges of the  SCLK  signal, respectively. Otherwise,  MCLK / SCLK  phase detector  202  detects either the high phase or the low phase of the  SCLK  signal. 
   The operation of the embodiment of  MCLK / SCLK  phase detector  202  shown in  FIG. 2  is illustrated in the timing diagrams of  FIGS. 4A–4F . For discussion purposes, analog data is being sampled in ADC  100  of  FIG. 1  on the rising edges of the  MCLK   —   OUT  signal and noise is being generated at the  SDATA  output on the falling edges of the  SCLK  signal, although the present inventive principles are not limited to these conditions. For example, in alternate embodiments, input data may be sampled on the on falling edges of the  MCLK   —   OUT  signal and/or output data output on the rising edges of the  SCLK  signal. 
     FIGS. 4A–4C  illustrate the phase relationships between the  MCLK  signal and the  SCLK  in which true (un-inverted)  MCLK  signal is selected by  MCLK / SCLK  phase detector  202  and multiplexer  203  of  FIG. 2 . Generally, in each of these cases, the rising edges of the  SCLK  signal occur before the next rising edge of the  MCLK  signal. 
   In  FIG. 4A , the rising edge of  FIG. 3  of the  SCLK  signal is detected. For example, prior to time t 1 , the  SCLK   —   S   0  and  SCLK   —   S   1  signals at the outputs of D flip-flops  302   a  and  302   b  of  FIG. 3  are both in a don&#39;t care state. Before the rising edge of the  MCLK  signal at time t 1 , the  SCLK  signal transitions to a logic high state, while the  SCLK   —   D   1  signal remains in a logic low state. In this case, after the rising edge of the  MCLK  signal, the  SCLK   —   S   0  signal is in a logic high state and the  SCLK   —   S   1  signal is in logic low state (i.e. together representing a logic 10), and multiplexer  203  of  FIG. 2  passes the true (non-inverted)  MCLK  signal. 
     FIGS. 4B and 4C  illustrate two cases in which the high phase of the  SCLK  signal is detected. In the example of  FIG. 4B , the  SCLK  signal is in a logic high state, and the  SCLK   —   D   1  signal has just transitioned to a logic high state, when the next rising edge of the  MCLK  signal occurs at time t 1 . As a result, both the  SCLK   —   S   0  and  SCLK   —   S   1  signals at the outputs of flip-flops  302   a  and  302   b  of  FIG. 3  transition to the logic high state with the rising edge of the  MCLK  signal (i.e. together representing a logic 11). For these states of the  SCLK   —   S   0  and  SCLK   —   S   1  SIGNALS, multiplexer  203  of  FIG. 2  again passes the true  MCLK  signal as the  MCLK   —   OUT  signal for driving analog clock generator  204 . The example shown in  FIG. 4C  is similar to that of  FIG. 4B , with the exception that the  SCLK  and  SCLK   —   D   1  signals transition to the logic high state well before the arrival of the next rising edge of the  MCLK  signal. 
     FIGS. 4D–4F  are timing diagrams illustrating exemplary phase relationships between the  MCLK  and  SCLK  signals under which the  MCLK   —   INV  signal is selected by multiplexer  203  of  FIG. 2  as the  MCLK   —   OUT  signal. In particular,  FIG. 4C  depicts the detection of the falling edges of the  SCLK  signal, and  FIGS. 4E and 4F  depict the detection of the low phases of the  SCLK  signal. 
   As shown in  FIG. 4D , at time t 1 , the  SCLK  signal has already transitioned to a logic low level, while the  SCLK   —   D   1  signal is still in the logic high state with the rising edge of the  MCLK  signal. Consequently, the  SCLK   —   S   0  and  SCLK   —   S   1  signals are respectively set to logic low and logic high states by D flip-flops  302   a  and  302   b  of  FIG. 3 , thereby together representing a logic 01. For a logic 01 state, multiplexer  203  of  FIG. 2  selects the  MCLK   —   INV  signal generated by inverter  201  as the  MCLK   —   OUT  signal for driving analog clock generator  204 . 
   In both the close low phase detection case of  FIG. 4E  and the low phase detection case of  FIG. 4F , the  SCLK  and  SCLK   —   D   1  signals both transition to the logic low state prior to the arrival of the next rising edge of the  MCLK  signal at time t 1 . In these examples, flip-flops  302   a  and  302   b  of  FIG. 3  output  SCLK   —   S   0  and  SCLK   —   S   1  signals both in the logic low state (i.e. a logic 00). For these conditions, multiplexer  203  of  FIG. 2  also selects the inverted  MCLK  signal generated by inverter  201  as the  MCLK   —   OUT  signal. 
   An exemplary alternate  MCLK / SCLK  phase detector  500  for controlling the selection of the  MCLK   —   OUT  signal by multiplexer  203  of  FIG. 2  is shown in the block diagram of  FIG. 5 . In the illustrated embodiment, the  MCLK   —   OUT  signal selected by multiplexer  203  is fed-back to the input of alternate  MCLK / SCLK  phase detector  500 , as the  MCLK  signal, and is inverted by inverter  201  to become the  MCLK   —   INV  signal. 
   In  MCLK / SCLK  phase detector  500 , a delay  501  generates the delayed  SCLK  signal,  SCLK   —   D   1 , which is sampled in a first D flip-flop  502   a  on rising edges of the  MCLK   —   OUT  signal to generate the intermediate signal  SCLK   —   S   1 . A second D flip-flop  502   b  samples either the un-delayed  SCLK  signal or a logic 1 blocking signal ( B   1 ), as selected by multiplexer  503 , on the rising edges of the  MCLK   —   RET  signal. Specifically, if the intermediate  SCLK   —   S   1  signal is in a logic low state, multiplexer  503  selects the  B   1  blocking signal, otherwise multiplexer  503  selects the un-delayed  SCLK  signal. An output gate  504  generates the output signal  MCLK   —   ERR  from the  SCLK   —   S   0  signal sampled onto second D flip-flop  502   b  or the  SCLK   —   S   1  SIGNAL output from first flip-flop  502   a.    
     FIGS. 6A–6C  illustrate exemplary phase relationships between the  MCLK   —   OUT  signal and the  SCLK  signal in which the true  MCLK   —   OUT  signal is selected by alternate  MCLK / SCLK  phase detector  500 . In particular,  FIG. 6A  illustrates the detection of a rising edge of the  SCLK  signal by  MCLK / SCLK  phase detector  500 . In this case, the rising edge of the  MCLK   —   OUT  signal samples the logic low level of the  SCLK   —   D   1  SIGNAL into first D flip-flop  502   a  at time t 1 , such that multiplexer  203  selects the  B   1  blocking signal. At time t 2 , the next rising edge of the  MCLK   —   RET  signal clocks the  B   1  blocking signal to the output of second D flip-flop  502   b  as the logic high  SCLK   —   S   0  signal. Gate  504  then outputs the  MCLK   —   ECC  signal at a logic low level, such that multiplexer  203  selects the un-inverted true  MCLK   —   OUT  signal. 
     FIG. 6B  illustrates the detection of the high phase of the  SCLK  signal by  MCLK / SCLK  phase detector  500 . In this case, the rising edge of the  MCLK   —   OUT  signal samples the logic high level of the  SCLK   —   D   1  signal into first D flip-flop  502   a  at time t 1 , such that multiplexer  203  selects the logic high phase of un-delayed  SCLK  signal as the  S   0  signal. With the next rising edge of the  MCLK   —   RET  signal, the  SCLK   —   S   0  signal at the output of second D flip-flop  502   b  transitions to a logic high state and the gate  504  again outputs the  MCLK _ERR  SIGNAL  in a logic low state to select the un-inverted  MCLK   —   OUT  signal, as shown in  FIG. 2 . 
     FIG. 6C  illustrates the detection of the low phase of the  SCLK  signal by  MCLK / SCLK  phase detector  500 . Here, the rising edge of the  MCLK   —   OUT  signal samples the logic low level of the  SCLK   —   D   1  signal into first D flip-flop  502   a  at time t 1 , and the  SCLK _S 1   SIGNAL  correspondingly transitions to a logic low state. In response, multiplexer  203  selects the  B   1  blocking signal and the  S   0  signal transitions to a logic high state. On the next rising edge of the  MCLK   —   RET , at time t 2 , signal, the  SCLK _S 0   SIGNAL  transitions to a logic high state such that gate  504  outputs the  MCLK _ERR  SIGNAL  in a logic low state to select the un-inverted  MCLK   —   OUT  signal, as shown in  FIG. 2 . 
     FIG. 6D  illustrates exemplary phase relationships between the  MCLK   —   OUT  signal and the  SCLK  signal in which the  MCLK   —   INV  signal is selected by  MCLK / SCLK  phase detector  500  of  FIG. 5  and multiplexer  203  of  FIG. 2 . Specifically,  FIG. 6D  depicts the detection of the falling edges of the  SCLK  signal. The rising edge of the  MCLK  signal samples the logic high level of the  SCLK _D 1   SIGNAL  into first D flip-flop  502   a  at time t 1 , such that the 50 signal initially transitions to a logic high state. Initially, the  S   0  signal then transitions low, as it tracks the phases of the  SCLK  signal. At time t 2 , the next rising edge of the  MCLK   —   RET  signal clocks the logic low state of the  S   0  signal to the output of second D flip-flop  502   b  as the logic low  SCLK _S 0   SIGNAL . Gate  504  then outputs the  MCLK _ECC  SIGNAL  at a logic high level, such that multiplexer  203  selects the MCLK —   INV  signal as the  MCLK   —   OUT  signal. 
     FIG. 7  is a block diagram of exemplary MCLK selection circuitry  700 , suitable for utilization in multiplexer  203  of  FIG. 2 , and  FIG. 8  is a block diagram of control signal blocking circuitry  800 , suitable for utilization in associated MCLK/SCLK phase detector  202 . The operation of MCLK selection circuitry  700  and control signal blocking circuitry  800  is described by the corresponding signals depicted in the timing diagram of  FIG. 9 . 
   MCLK selection circuitry  700  ensures that when multiplexer  203  of  FIG. 2  switches between the  MCLK  and  MCLK   —   INV SIGNALS , such that glitches do not appear at the multiplexer  203  output. In particular, MCLK selection circuitry  700  temporarily blocks the output of multiplexer  203  while the  MCLK _ECC  MULTIPLEXER  selection signal of  FIG. 5  and  FIGS. 6A–6D  is changing state. Control signal blocking circuitry  800  blocks selected control signals during switching of multiplexer  203 , to eliminate control oscillation, which may occur in embodiments in which the  MCLK _OUT  SIGNAL  is feedback to MCLK/SCLK phase detector  202  as the new  MCLK  signal. 
   Although the invention has been described with reference to specific embodiments, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed might be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
   It is therefore contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention.

Technology Category: 5