Patent Document

BACKGROUND 
   1. Field of the Invention 
   The disclosure generally relates to a method and apparatus for devising a high density superconductor. More specifically, the disclosure relates to a method and apparatus for reducing inductor footprint in a superconducting circuit while increasing inductance. 
   2. Description of Related Art 
   With recent developments in superconductor technology, superconductor devices using the Josephson junction effect are replacing conventional devices based on semiconductor technology for high performance and low power. Digital circuits that employ superconductor technology are often desirable because such devices can consume very little power while operating at very high clock speeds as compared with their semiconductor counterparts. Because of low power consumption, it is possible to make systems very compact. Other benefits for signal transmission using superconducting devices include reduced signal attenuation and noise. Digital circuits that employ superconductor devices can operate at clock speeds exceeding 100 GHz. 
   A Josephson junction is a weak link between two superconducting materials where carriers tunnel across the junction. As long as the current through the junction is less than a critical current (I c ), the junction will be superconducting. A bias current is applied to the junction that is below the critical current. When additional current, for example, from an analog signal, is applied to the junction so that the current exceeds the critical current, the junction will generate a voltage pulse. The voltage pulse corresponds to a quantum leap in the magnetic phase of the junction, which will create a single flux quantum (SFQ) voltage pulse across the junction. The area of the SFQ voltage pulse generated at the junction is determined by fundamental physical constants and is Φ 0 =h/2e, where h is the Planks constant (6.6262×10 −34  Joule seconds), and e is the fundamental electrical charge (1.602×10 −19  Coulombs). 
   The SFQ pulses can be used to transmit data at very high frequencies. The SFQ pulses are transmitted by coupling a series of Josephson junctions together to provide a Josephson transmission line (JTL). When a particular Josephson junction in a JTL receives an SFQ pulse from a preceding Josephson junction, the pulse causes the junction to emit a voltage pulse, such that the SFQ pulse is recreated to continue propagating along the JTL. A discussion of JTLs operating in this manner can be found in U.S. Pat. No. 6,507,234, issued Jan. 14, 2003 to Johnson et al., assigned to the Assignee of this application, and herein incorporated by reference for background information. 
   JTL serves as interconnect for Josephson logic gates. Both JTL and logic gates use inductive interconnects. At lower temperature, lower power can be achieved with reduced Josephson junction critical current, which requires proportional increase in inductance of interconnect. The conventional inductive element is a strip. According to the conventional methods increasing inductance requires extending the length of the inductor. A bigger inductor requires a larger footprint on the micro circuit which is defeating to the concept of using Josephson junctions to miniaturize the circuit. Thus, there is a need for method and apparatus for high density superconductor inductive element with relatively smaller footprint. 
   SUMMARY 
   In one embodiment, the disclosure relates a single flux quantum digital logic circuit comprising: a first Josephson junction having a first critical current (I c1 ); a second Josephson junction having a second critical current (I c2 ); a series of intermediate Josephson junctions interposed between the first Josephson junction and the second Josephson junction, the series of intermediate Josephson junctions converting the voltage pulse from the first Josephson junction into a working current and directing the working current to the second Josephson junction; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions. 
   More generally, the disclosure relates a method for providing an inductive logic circuit element, the method comprising: arranging one or more Josephson junctions in series, wherein the working current applied to the inductive element is sufficiently high to create a desirable inductive flux in the series of intermediate Josephson junctions. 
   In still another embodiment, the disclosure relates to a method for conducting a logic circuit, the method comprising: arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (I c1 ) and the second Josephson junction having a second critical current (I c2 ); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to create a desirable signal at the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The representative embodiments of the disclosure will be described in relation with the following exemplary and non-limiting drawings in which: 
       FIG. 1  is a circuit diagram for a conventional superconducting Josephson Transmission Line; 
       FIG. 2A  is a circuit schematic for the inductive loop of a conventional superconducting Josephson transmission line using a typical parameter value; 
       FIG. 2B  shows physical layout (magnified) of the inductive loop of a conventional JTL; 
       FIG. 3A  is a circuit schematic for the conventional JTL loop with decreased Josephson junction critical current and proportionate increased loop inductance for performance at lower operating temperature; 
       FIG. 3B  shows a conventional JTL loop physical layout (magnified) with increased loop inductance for performance at lower operating temperature; 
       FIG. 4A  is a circuit schematic for the JTL loop according to an embodiment of the disclosure; 
       FIG. 4B  shows the JTL loop physical layout (magnified) according to an embodiment of the disclosure; 
       FIG. 5A  is a circuit schematic for a conventional logical gate (i.e. T flip flop); 
       FIG. 5B  shows physical layout (magnified) of a conventional logic gate; 
       FIG. 6A  is a circuit schematic for a conventional logic gate (T flip flop) with increased loop inductance for performance at lower operating temperature; 
       FIG. 6B  shows physical layout (magnified) of the conventional logic gate with increased loop inductance for performance at lower operating temperature; 
       FIG. 7A  is a circuit schematic for the logic gate according to an embodiment of the disclosure; and 
       FIG. 7B  shows the logic gate physical layout (magnified) according to an embodiment of the disclosure. 
   

   DETAILED DESCRIPTION 
   As stated, the Josephson effect is the phenomenon of current flow across two weakly coupled superconductors, separated by a very thin insulating barrier. In this arrangement, the two superconductors linked by a non-conducting barrier define the Josephson junction and the current that crosses the barrier is the Josephson current. 
     FIG. 1A  is a circuit diagram for an inductive loop of a conventional superconducting JTL. The circuit of  FIG. 1A  comprises Josephson junctions  110  and  120  connected through inductive line  130 . Each of Josephson junctions  110  and  120  is rated at a critical current of 100 μA and inductor  130  provides inductance of about 20 pH. The conventional JTLs also include a shunt resistor is placed in parallel with each of Josephson junctions  110  and  120 . Finally, a bias current (not shown) must also be applied to the Josephson junctions. 
   The Josephson junction circuits  180  and  190  of the JTL  100  are spaced apart at predetermined intervals along the JTL  100  to regenerate the SFQ pulses at each stage. Each Josephson junction circuit  180  and  200  is shown as an equivalent circuit of a resistor and Josephson junction in a parallel array. The equivalent elements of the JTL segment  110  and the Josephson junction circuit  180  will be described with the understanding that all of the Josephson junction circuits in the JTL  100  have substantially the same elements. The Josephson junction circuit  180  includes a Josephson junction  181  that is connected in series with a first parasitic inductor  182 . The Josephson junction  181  and the first parasitic inductor  182  are connected in parallel with a damping resistor  183  and a second parasitic inductor  184 . The first and second parasitic inductors  182  and  184  are connected to a reference ground  130  opposite the Josephson junction  181  and the damping resistor  183 . The damping resistor  183  shunts the Josephson junction  181  and helps define its response to incoming signals. The damping resistor  183  is chosen such that the so-called Stewart-McCumber parameter, which dictates how a Josephson junction is damped, falls between 1 and 2. 
   When operated at very high clock frequencies, timing between clock pulses and data pulses is critical. For example, in a digital circuit is operated at a 100 GHz clock, any given data pulse must arrive at its destination logic gate within a time interval of less than ten picoseconds in order to be correctly processed by that gate. Because of their high frequency, clock and data pulses arriving at any particular circuit element must be closely synchronized or errors will occur. The timing uncertainty of the SFQ pulses discussed above increases the need for greater timing synchronization. Therefore, superconductor circuits typically operate well below their potential speed so that the pulse timing uncertainty is less important. 
     FIG. 2A  is a circuit schematic for the inductive loop of a conventional superconducting Josephson transmission line (JTL), using typical parameter values. More specifically,  FIG. 2A  shows a conventional SFQ digital logic circuit element. The SFQ logic circuit of  FIG. 2A  includes Josephson junctions  210  and  220  separated by controlled inductance  230 . The SFQ logic circuit of  FIG. 2A  can define a superconducting quantum interference device (“SQUID”).  FIG. 2B  shows physical layout (magnified) of the inductive loop of a conventional JTL. As shown in  FIG. 2B , Josephson junctions  210  and  220  have a critical current of about 100 μA. Inductor  230  provides an inductance of about 20 pH, at about 4.2° K. As is known in the art, to obtain higher inductance values, the geometric shape of inductor  330  must be changed. Thus, the so-called β L  value can be estimated with Equation (1):
 β L =( Ic×L )/Φ 0 =100 μA×20 pH/Φ 0 ≈1  (1) 
     FIG. 3A  is a circuit schematic for a conventional JTL loop with decreased Josephson junction critical current and proportionate increased loop inductance for performance at lower operating temperature. As in  FIG. 3A , Josephson junctions  310  and  320  are connected by inductor  330 . To obtain the desired inductance, a significantly larger inductor  330  is used. The circuit of  FIG. 3A  is designed to operate at the milli-Kelvin range. 
     FIG. 3B  is equivalent circuit representation for the SFQ logic device of  FIG. 3A . At 10-100 mK, loop inductance of logic circuit of  FIG. 3A  is about 700 pH. In  FIG. 3B , Josephson junctions  310  and  320  are coupled together through inductive circuit  330 . Inductive circuit  330  provides about 700 pH of inductance which corresponds to about 700 geometric inductance squares. This is a rather large inductance footprint occupying a substantial area on the chip. As in the circuit of  FIGS. 3A and 3B , the β L  value can be estimated as:
 β L =( Ic×L )/Φ 0 =3 μA×700 pH)/Φ 0 ≈1  (2) 
   It can be seen that the β L  values from equations (1) and (2) are to be kept relatively close. However, the inductor size of the circuit of  FIG. 3A  is substantially larger than that of  FIG. 2A . 
     FIG. 4A  is a circuit schematic for an improved JTL loop according to an embodiment of the disclosure. In the embodiment of  FIG. 4A , the geometric inductance is replaced with one or more Josephson inductance. Replacing the geometric inductance with the Josephson inductance provided the unexpected result of providing the same β L  regardless of the designed operating temperature. In other words, the same physical layout applies to 4.2° K as in the 10-100 mK range. Moreover, the geometric size and footprint is invariant with respect to temperature. 
     FIG. 4B  shows the JTL Loop physical layout according to an embodiment of the disclosure. As stated with regard to  FIG. 4A , this implementation is scale-invariant. That is, the design applies equally well to all operating temperatures. 
   Referring again to  FIG. 4A , junction  410  represents a first Josephson junction having a first critical current (I c1 ). The critical current (I c ) of a Josephson junction is the current above which the Josephson junctions (and by extension, the SFQ logic circuit) fails to act as a superconductor, and becomes active, generating SFQ pulse. Junction  420  is the second Josephson junction having a second critical current (I c2 ). 
   Josephson junctions  410  and  420  are separated by intermediate connectors  430 - 490 . The intermediate Josephson junction connectors  430 - 490  are arranged in series. In one embodiment, the intermediate Josephson junction connectors are defined by larger junctions larger than the first Josephson junction  410  and/or the second Josephson junction  420 . Thus, the critical current for the intermediate Josephson junction  430 - 490  can be higher than the first critical current (I c1 ) and/or the second critical current (I c2 ). In this manner, even though current flows through each intermediate junction, it does not exceed the junction&#39;s critical current thereby allowing the intermediate junction to operate as a superconductor. The intermediate junction connectors  430 - 490  may be equal to or smaller than Josephson junctions  410  and  420 , so long as the signal current does not exceed the critical current of the intermediate junctions. This is possible because the current can be arranged such that junctions  410  and  420  get bias current, whereas the intermediate junctions do not. 
   In another embodiment of the disclosure, at least one of the intermediate junctions  530 - 570  comprises a pair of Josephson junctions. The Josephson junction pair can be organized as a two junction SQUID, whose inductance is determined by means of a contral line. For example, intermediary junction  530  can comprise a pair of Josephson junctions connected in parallel. 
   According to one embodiment, the first Josephson junction and the second Josephson junction are connected by intermediary Josephson junctions having the same relative size and critical current as the first and/or the second intermediary Josephson junctions. In a preferred implementation, current is limited through the intermediary Josephson junctions such that it remains below the first critical current and/or the second critical current. 
   As stated, one advantage of the embodiments disclosed herein is the ability to limit the size of the geometric inductance using Josephson junctions. That is, the circuit is scale-invariant with respect to junction critical current and operating temperature. The representative embodiment of  FIG. 5  provides this advantage by using a plurality of intermediary Josephson junctions which require a substantially smaller footprint as compared to the traditional inductive circuits. 
   The disclosed inductive circuits can be used as a component of a larger circuit. The disclosed inductive circuits is substantially smaller than the equivalent conventional circuits. The disclosed inductive circuits can be used in any temperature range. However, the superconductivity of Josephson junctions require a temperature below the critical temperature of the device. In a preferred embodiment, the operating temperature is in the milli-Kelvin range. 
     FIGS. 5-7  show application of the disclosed embodiments to various circuits. Specifically,  FIG. 5A  shows a circuit schematic for a prior art logic gate T-type flip flop and  FIG. 5B  shows the physical layout of the logic gate of  FIG. 5A . A t-type flip flop changes its output for each clock edge, giving an output which is half of the frequency signal of the T input. Referring to  FIG. 5A , Josephson junctions  510  and  520  are coupled through inductor  530 . Josephson junction  520  has a critical current of about 100 μA and is coupled to inductor  530  which has 20 pH inductance. A bias is applied to junction  532 . Josephson junctions  540  and  550  form the balance of the T-Flip flop circuit. 
     FIG. 6A  is a circuit schematic for a conventional logic gate (T-type flip flop) with increased loop inductance for performance at lower operating temperature.  FIG. 6B  shows the physical layout of the logic gate of  FIG. 6B . In  FIG. 6A , Josephson junctions  610  and  620  are connected via inductor  630 . Josephson junction  620  has a critical current of about 3 μA and inductor  630  has an inductance of about 700 pH. The increased inductance value is calculated to allow operating at a much lower temperature. The physical dimensions of inductor  630  is represented in  FIG. 6B . While the increased loop inductance  630  of  FIG. 6B  allows performance at lower operating temperature, the increased dimensions consume more chip area. 
     FIG. 7A  is a circuit schematic for the logic gate according to one embodiment of the disclosure. In the embodiment of  FIG. 7A , Josephson junctions  710  and  720  are coupled through Josephson junctions  730 . Josephson junctions  730  replace inductive circuit  630  in  FIG. 6A .  FIG. 7B  shows the logic gate physical layout for the embodiment of  FIG. 7A . In  FIG. 7B , Josephson junctions  710  and  720  are connected through a plurality of Josephson junctions  730 . As can be seen from  FIGS. 7A and 7B , the circuit of  FIG. 7B  is substantially more compact and space efficient than that of  FIG. 6B . Thus, the inventive embodiments provided herein are advantageous in promoting chip efficiency. The disclosed principles are equally applicable to all other SFQ gates, all of which typically have inductive loops. 
   While the specification has been disclosed in relation to the exemplary embodiments provided herein, it is noted that the inventive principles are not limited to these embodiments and include other permutations and deviations without departing from the spirit of the disclosure.

Technology Category: h