Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    1. Field of Invention 
         [0002]    The present invention relates to a phase-locked loop (PLL), and more particularly to a PLL capable of rapid lock-in. 
         [0003]    2. Related Art 
         [0004]    A PLL is an automatic control circuit system capable of tracing the frequency and phase of an input signal, which mainly traces and locks the phase and frequency of an output signal and an input signal such that the phase and frequency of the output signal and the input signal tend to be the same, and at this moment, they are referred to as being locked. 
         [0005]    PLLs may be generally classified into analog PLLs and digital PLLs. Taking the system architecture of a common digital PLL as an example, referring to  FIG. 1 , it is a system block diagram of a conventional digital PLL. As shown in  FIG. 1 , the digital PLL  10  includes a phase-frequency detector (PFD)  100 , a phase difference quantizer  110 , and a digital controlled oscillator (DCO)  120 , and a divider  130  is further added if different multiple frequencies are required. Since the basic concept of the conventional analog PLL is similar to that of the digital PLL and is well known by those skilled in the art, it will not be described herein. 
         [0006]    Referring to  FIG. 2 , it is a corresponding diagram of frequency to period of the reference signal, wherein the horizontal axis represents time, and the vertical axis represents frequency. During rising time of a square wave, a conventional analog PLL or a digital PLL will reach a lock-in state generally after generating a plurality of oscillation periods  201 . For operating frequencies above MHz, a time period of several microseconds (μs) or even less is required to achieve a lock-in state, and also being closely related to the reference signal frequency. Even with greater bandwidth, the conventional PLL locks-in after oscillating scores or hundreds of periods. Therefore, even for some practical applications with low reference signal frequency such as video systems and display systems, the stability and operating speed of the PLL still do not meet their needs, which is a problem yet to be solved. 
       SUMMARY OF THE INVENTION 
       [0007]    It is an object of the present invention to provide a PPL for rapid lock-in, and it is another object of the present invention to provide a method applicable to a PPL for rapid lock-in that a phase-locked output signal may directly be forced into the lock-in state. 
         [0008]    In the present invention, where an analog, digital, or hybrid PLL is provided, a lock-in actuator circuit receives a reference signal and a phase-locked output signal, generates a lock-in signal accordingly, and outputs the lock-in signal to the loop filter or/and VCO/ICO/DCO. 
         [0009]    In another aspect of the present invention, where a method applicable to the PLL for rapidly achieving a lock-in state is provided, includes first making a temporal feature measurement and then providing a lock-in signal according to the temporal feature. 
         [0010]    The present invention achieves the object of rapidly entering into a lock-in state by using a lock-in actuator circuit. Features and practices related to the present invention will be illustrated in detail below with preferred embodiments with accompanying drawings. 
         [0011]    Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The present invention will become more fully understood from the detailed description given herein below for illustration only, and which thus is not limitative of the present invention, and wherein: 
           [0013]      FIG. 1  is a system block diagram of a conventional digital PLL; 
           [0014]      FIG. 2  is a diagram of frequency to period of the reference signal; 
           [0015]      FIG. 3  is a system block diagram of an analog PLL for rapid lock-in; 
           [0016]      FIG. 4  is a diagram of frequencies of a reference voltage signal and a phase-locked output signal; 
           [0017]      FIG. 5  is a diagram of frequency to period of the reference signal; 
           [0018]      FIG. 6  is a diagram of frequency to period of the reference signal; 
           [0019]      FIG. 7  is a system block diagram of a digital PLL for rapid lock-in; and 
           [0020]      FIG. 8  is a system block diagram of a hybrid digital-analog PLL for rapid lock-in. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    Please refer to  FIG. 3 , which is an embodiment of an analog PLL for rapid lock-in. As shown in  FIG. 3 , the analog PLL  30  includes a PFD  300 , a VCO/ICO  320 , a charge pump  340 , a loop filter  350 , a divider  330 , and a lock-in actuator circuit  360 . 
         [0022]    The PFD  300  is used to compare a phase difference between a feedback signal F i  and a reference signal F r  and output a phase difference signal S 1  according to the phase/frequency of the input signals. Generally the phase difference signal S 1  may be classified as an UP signal or a DOWN signal whose signal value and time difference represent the magnitude of phase difference of the feedback signal F i  and reference signal F r . Representation is not limited to the UP signal and DOWN signal, but since the meanings of other representations are similar, they will not be described herein. 
         [0023]    The charge pump  340  is used to output a signal S 2  according to the phase difference signal S 1 , the signal S 2  corresponding to the phase difference between the feedback signal F i  and reference signal F r . 
         [0024]    The loop filter  350  comprising capacitance elements and resistance elements is mainly used for filtering. It also receives a lock-in signal S 31  from the lock-in actuator circuit  360 , and outputs a corresponding reference voltage signal S 4  according to the lock-in signal S 31  (and the signal S 2  if necessary). The VCO/ICO  320  outputs a corresponding phase-locked output signal F o  according to the reference voltage signal S 4 . 
         [0025]    The divider  330  is used to divide the phase-locked output signal F o  into the feedback signal F i  according to a frequency division control signal S 5  generated from the lock-in actuator circuit  360 , when a relationship of multiple frequency exists between frequencies of the phase-locked output signal F o  and reference signal F r . In some cases, when frequencies of the phase-locked output signal F o  and the reference signal F r  are meant to be the same, this divider  330  is a redundant element and may be omitted. 
         [0026]    Since an intended voltage signal is directly given by using the operation to get a target operating frequency, the oscillations in the PLL system may be reduced, such that the lock-in state may be achieved rapidly. 
         [0027]    The lock-in actuator circuit  360  is additionally added for feedback mechanisms. The phase-locked output signal F o  generated by the VCO/ICO  320  returns to the lock-in actuator circuit  360  via the loop, i.e. signal S Fo , and the lock-in signals S 31 , S 32  will then be generated by the lock-in actuator circuit  360 . The lock-in signal S 31  may generate the reference voltage signal S 4  corresponding to the lock-in signals through the loop filter  350 . After the reference voltage signal S 4  inputs VCO/ICO  320 , a corresponding phase-locked output signal F o  is then generated. By performing appropriate circuit design modifications, the VCO/ICO  320  may also be controlled directly by using the lock-in signal S 32  to generate the corresponding phase-locked output signal F o . The numerous modifications should be well known to those skilled in the art, and are thus omitted herein. 
         [0028]    Please refer to  FIG. 4 , which is a corresponding diagram of frequencies of the reference voltage signal and the phase-locked output signal. In the drawing, there are two reference voltage signals V 1  and V 2  on the horizontal axis, which respectively correspond to frequencies f 1  and f 2  of the phase-locked output signal on the vertical axis, and a line may be obtained by linearly connecting intersection points (V 1 , f 1 ) and (V 2 , f 2 ). A desired operating frequency, that is, the frequency f o  of the phase-locked output signal F o , may be found by using interpolation or extrapolation, and the frequency f o  of the phase-locked output signal corresponds to a voltage value, i.e. a desired target reference voltage signal (V VCO/ICO ) according to the linear relationship in the drawing. Thus, the phase-locked output signal F o  of the operating frequency may be directly obtained after a reference voltage signal V VCO/ICO  passes through the VCO/ICO  320 . The interpolation or extrapolation used here will not be limited to linear ones, since according to individual circuit characteristics, using curvilinear interpolation/extrapolation, look-up tables, or even pre-calculations of provided parameters that include voltage, frequency, . . . etc., should also fall within the scope of the present invention. 
         [0029]    Since the rapid lock-in function provided by the present invention may perform an auto-calibration to adapt changes due to temperature and voltage shift during process, the system may be able to achieve the lock-in state without having to experience many oscillation periods. Please refer to  FIG. 5 , which is a corresponding diagram of frequency to period of a reference signal. In  FIG. 5 , the horizontal axis represents the time, and the vertical axis represents the frequency, and comparing with what is shown in  FIG. 2 , the rapid lock-in function of the present invention enters into the lock-in state immediately within an extremely short period of time, that is, to directly reach frequency f o  to which the set voltage corresponds. 
         [0030]    Please refer to  FIG. 6 , which is a corresponding diagram of frequency to period of a reference signal. Similar to  FIG. 5 , the originally set voltage enters into the re-set voltage directly, that is, the frequency is directly set from f 1  to f 2 . 
         [0031]    The lock-in actuator circuit  360  as shown in  FIG. 3 , is used to perform a temporal feature measurement according to the reference signal F r . A desired frequency or phase is calculated according to the result of the temporal feature measurement. Since the purpose of the temporal feature measurement is only to obtain temporal features of the reference signal F r , length of the captured reference signal need not be limited in the process of sampling. Whether shorter than, equal to, or longer than one period, a signal length capable of providing adequate feature meanings may substantially be considered as a reference for the capturing length. Furthermore, changes can be made according to different accuracy requirements, such that the desired value of the lock-in frequency may be obtained to enter into the lock-in state rapidly. 
         [0032]    In addition to the above mentioned calculating mechanism, another method for frequency setting is further provided in the PLL  30 . When pursuing a specific frequency, if possible upper and lower limits of the frequency have been known, the phase lock output frequency f o  to which the reference voltage signal V VCO/ICO  corresponds may be directly set as represented by formula (1). 
         [0000]        f   o =½( f   max   +f   min )  (1) 
         [0033]    In formula (1), f o  represents the set frequency of the phase-locked output signal; f max  represents the possible upper limit of the frequency; and f min  represents the possible lower limit of the frequency. 
         [0034]    Although achieving the lock-in state by using formula (1) will not be as rapid as the ones adopted in the lock-in actuator circuit  360  of the previous embodiments, however, the time used for achieving such a state can be effectively shortened. In the process of setting, a change in respective weightings of f max  and f min  may also be made according to personal experience, having no need of setting to an average value of f max  and f min . A specific frequency value between the possible upper limit f max  and lower limit f min  can be obtained by the circuit designer according to circuit characteristics and personal experience as the set frequency f o  of the desired phase-locked output signal. 
         [0035]    Please refer to  FIG. 7 , which is an embodiment of a digital PLL for rapid lock-in. As shown in  FIG. 7 , the digital PLL  70  includes a PFD  700 , a phase difference quantizer  710 , a DCO  720 , a divider  730 , and a lock-in actuator circuit  760 . The DCO  720  further includes a controller  721 , a clock generator  722 , and a phase switching unit  723 . The digital PLL shown in  FIG. 7  is only an embodiment of the invention, alterations like uniting PFD  700  and phase difference quantizer  710  as a single unit or providing only UP and DOWN signals to the DCO  720  should be well known to those skilled in the art, and are thus omitted herein. 
         [0036]    The PFD  700  is used to compare the feedback signal F i  with the reference signal F r  and output a level signal according to F i  and F r . The level signal is generally divided into an UP signal and a DOWN signal. The phase difference quantizer  710  is used to output the magnitude of the phase difference as a count signal PE in a manner of digital quantization according to the signal value and time difference of the reference signal F r  and the feedback signal F i . In the present embodiment, both the PFD  700  and the phase difference quantizer  710  are located in the same device, and thereby can receive both the reference signal F r  and the feedback signal F i  (i.e. the phase-locked output signal), and the UP level signal, the DOWN level signal, and the count signal PE may be simultaneously input to the DCO  720 . However, in another embodiment, the count signal PE can be derived from corresponding UP and DOWN signals, the phase difference quantizer  710  is thus neglected in such circumstances. 
         [0037]    Different from the analog PLL which uses the VCO/ICO, the digital PLL adopts the DCO  720  to process digital signals. In the DCO  720 , the UP level signal, the DOWN level signal, and the count signal PE are processed in a controller  721 . The controller  721  can be a proportional-integral (PI) controller or a proportional-integral-differential (PID) controller. The controller  721  receives a lock-in signal S 33  generated from the lock-in actuator circuit  760  to adjust the input UP signal, DOWN signal, and count signal PE, and convert them into an output signal CTRL to be provided to the phase switching unit  723 , which then outputs the phase-locked output signal F DCO  according to the output signal CTRL. Similar to the analog PLL, if there is a need of dividing the frequency, the frequency of the phase-locked output signal F DCO  may be divided by the divider  730 , and then the phase difference between the feedback signal F i  (the frequency divided phase-locked output signal) and the reference signal F r  is detected by the PFD  700 . A clock generator  722  may exist in the DCO  720  to provide a clock signal CLK for the operation of the phase switching unit  723 . The phase-locked output signal F DCO  output from the phase switching unit  723 , the parameters of the phase switching unit  723 , and the parameters of the clock generator  722  may all be fed back to the lock-in actuator circuit  760 , which can be referred to as S Fo , which is used as a reference for setting the lock-in signal. 
         [0038]    The function of the lock-in actuator circuit  760  here is similar to that of the aforementioned analog PLL, while the function of lock-in actuator circuit  760  of the digital PLL is to provide the lock-in signal S 33  to the controller  721  in the DCO  720  such that the DCO  720  may rapidly find out the required phase-locked output signal, wherein the lock-in signal S 33  can be a period control word (PCW) or a frequency control word (FCW). The PCW or FCW may be influenced by the parameters fed back from the clock generator  722  and the phase switching unit  723 , and the lock-in actuator circuit  760  then makes an optimum modification to perform an automatic aligning to the system, thereby, a digital lock-in state can be achieved without having to experience many oscillation periods. The lock-in actuator circuit  760  can also provide signals S 51  and S 52  respectively to the divider  730  and the phase switching unit  723 , for achieving the purpose of rapid lock-in. 
         [0039]    The divider  730  will be built only when there is a need of dividing the frequency, and when a one-multiple relationship exists between frequencies of the phase-locked output signal F o  and the reference signal F r , the divider  730  is substantially unnecessary. 
         [0040]    Please refer to  FIG. 8 , which is an embodiment of a rapid lock-in hybrid digital-analog PLL. As shown in  FIG. 8 , besides a lock-in actuator circuit  860 , the rapid hybrid digital-analog PLL  80  further includes a digital PLL  810 , an analog PLL  820 , and a divider  830 . The digital PLL  810 , analog PLL  820 , and divider  830  being similar to those in conventional PLLs. A series-connected sequence of the digital PLL  810  and the analog PLL  820  is not necessarily as shown in  FIG. 8 , and can also be changed to that the analog PLL  820  is in front of the digital PLL  810 . The lock-in function and method of the lock-in actuator circuit  860  are the same as those of the lock-in actuator circuits  360 ,  760  referred to in the above-mentioned embodiments of the digital PLL and analog PLL. The lock-in signals S 34 , S 35  generated by the lock-in actuator circuit  860  of the present embodiment are respectively used to set the digital PLL  810  and the analog PLL  820  such that a desired lock-in state can be achieved rapidly. The desired lock-in effect can be achieved by selecting both or either one of the lock-in signals S 34 , S 35 . 
         [0041]    Similarly in some cases, when a multiple frequency relationship exists between frequencies of the phase-locked output signal F o  and the reference signal F r , the phase-locked output signal F o  may be fed back after its frequency is divided by the divider  830 , while when a one-multiple relationship exists between frequencies of the phase-locked output signal F o  and the reference signal F r , such a divider  830  is a redundant element which may be omitted. 
         [0042]    The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Technology Category: 5