Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention is related to digital-to-analog conversion techniques, and is applicable to the digital control of certain types of analog systems.  
       BACKGROUND OF THE INVENTION  
       [0002]     Digital-to-analog conversion is required for many applications, including clock and data recovery (CDR) applications for digital communications.  FIG. 1  is a block diagram of a conventional digital-to-analog (D/A) converter  100 . As shown in  FIG. 1 , a digital-to-analog converter  100  translates a given digital word into an analog electrical signal, for example a voltage or a current. In a Phase Locked Loop (PLL) (or a Delay Locked Loop (DLL)), for example, a digital-to-analog converter  100  may convert a digital word representing a phase offset or time delay into an analog bias signal that controls the phase (or delay) of a clock signal.  
         [0003]     In general, the value of the analog output, Y, of a typical D/A converter with an N-bit binary input word is a fraction of a full-scale output value, this fraction being defined by the value of the binary input. Specifically, for an exemplary digital-to-analog converter  100 , the analog output, Y, is equal to  
             Y   =       (     X     2   N       )     ⁢     Y   MAX               (   1   )             
 
 where Y MAX  is the full-scale value of the D/A converter, and X is the decimal equivalent of the binary input word. For example, suppose that N equals 6, and that the D/A converter  100  generates a current with a full-scale value of 1 mA. If the digital input word is set to 100000, i.e., the binary representation of 32, then the output current of the D/A converter will be equal to 0.5 mA ((1 mA)×(32/64)). Similarly, if the digital input word is set to 010000, then the output current would be equal to 0.25 mA ((1 mA)×(16/64)). 
 
         [0004]     When the binary input to the D/A converter  100  increments or decrements by 1, the output, Y, changes by an amount equal to Y MAX /2 N , which is known as the step size of the D/A converter. The step size represents the maximum value of the error that occurs if the analog output of the D/A converter is used to approximate a continuously valued analog signal. This error, known as quantization error, must be taken into account in the design of any system that uses a D/A converter. In a standard D/A converter with a specified output range, the step size can only be reduced by increasing N, which results in an increase in the size, complexity, and cost of the converter.  
         [0005]     The step size of a conventional D/A converter is constant; thus, a single step change results in a much higher percentage change in the analog output, Y, near the low end of the D/A output range than it does at the high end of the range. For example, suppose that a given application requires the output of the D/A converter  100  to cover the range of 0.1×Y MAX  to 0.9×Y MAX , while also requiring that the step size be no larger than 1% of the instantaneous value of the output over the specified output range. Then, the step size of the D/A converter  100  must be no larger than 0.001×Y MAX , which would require the D/A converter  100  to be at least a 10-bit converter. Furthermore, when Y is close to the upper end of the specified output range, the step size would be significantly smaller than required by the specification. Thus, in many applications, the step size of a conventional D/A converter, and thus the complexity of the circuit, is set by the precision required at the low end of the output range.  
         [0006]     In many applications in which quantization error must be very small, the number of bits, N, in the digital control word of the conventional D/A converter would have to be quite large. In many such applications, it may be possible to first perform a coarse adjustment of the analog output signal, Y, and then when the value of this signal is within a predefined tolerance of a desired value, to perform either a one-time or a continuous fine adjustment of the analog output signal, Y.  
         [0007]     A need therefore exists for improved techniques for digital-to-analog conversion. A further need exists for a digital-to-analog converter that is comprised of two or more digital-to-analog converters that may each be employed during different operating modes.  
       SUMMARY OF THE INVENTION  
       [0008]     Generally, methods and apparatus are provided for improved digital-to-analog conversion. According to one aspect of the invention, the disclosed digital-to-analog converters comprise a master digital-to-analog converter that generates a master analog value, and a slave digital-to-analog converter that generates a slave analog value that is based on the master analog value. The analog values may be, for example, current values or voltage values. The slave analog value can be, for example, substantially proportional to the master analog value. In one exemplary implementation, the step size of the slave digital-to-analog converter is a fixed percentage of the master analog value.  
         [0009]     According to another aspect of the invention, the master D/A converter can be varied during a coarse tuning mode, while the input to the slave D/A can be fixed, for example, to an approximately mid-range value until the master analog value satisfies one or more predefined conditions. Thereafter, during a fine tuning mode, the slave D/A converter can be varied, while the master D/A converter is fixed, so that the output Y is equal to a desired value (within a specified tolerance).  
         [0010]     According to yet another aspect of the invention, the master digital-to-analog converter can optionally comprise a binary weighted digital-to-analog converter and the slave digital-to-analog converter can optionally comprise a thermometer encoded digital-to-analog converter.  
         [0011]     A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a block diagram of a conventional D/A converter;  
         [0013]      FIG. 2  is a block diagram of a master/slave digital-to-analog converter incorporating features of the present invention; and  
         [0014]      FIG. 3  is a Controlled Delay-Line transfer characteristic curve, illustrating the range of bias current required of a digital-to-analog converter. 
     
    
     DETAILED DESCRIPTION  
       [0015]      FIG. 2  is a schematic block diagram of a master/slave digital-to-analog converter  200  incorporating features of the present invention. As shown in  FIG. 2 , the master/slave D/A converter  200  comprises a master D/A converter  210  and a slave D/A converter  220 . In the exemplary embodiment shown in  FIG. 2 , the D/A converter  210  and D/A converter  220  are both current-mode D/A converters. It will be recognized by one skilled in the art, however, that either or both converters  210 ,  220  could be implemented with voltage outputs, without departing from the scope of the invention. Further, the master D/A converter  210  may cover a broad range, such as 0-150 μA of current, while the slave D/A converter  220  covers a small percentage, such as +/−20%, of the master D/A converter value. The analog output of the D/A converter  200 , Y, is generated by summation block  240 , which sums the outputs of the D/A converters  210 ,  220 , with the output of the slave D/A  220  scaled by a scaling block  230 .  
         [0016]     As shown in  FIG. 2 , bias currents, that determine the full-scale output value, and thus the size of the quantization level (i.e., step size) of each converter  210 ,  220 , are input to the D/A converters  210  and  220 . The master D/A converter  210  is biased by a fixed reference current, I BIAS , while the slave D/A converter  220  is biased by a slave bias current, I SBIAS , that is proportional to the master output current, I MAST  (not shown in  FIG. 2 ). Thus, each quantization step of the output current of the slave D/A converter  220  is substantially proportional to the output current of the master D/A converter  210 . In one implementation, each step of the slave D/A converter  220  generates an output current that is a fixed percentage of the current value generated by the master D/A converter  210  over the entire output range of the master.  
         [0017]     As shown in  FIG. 2 , the exemplary master/slave D/A converter  200  is driven by a circuit (not shown) that generates separate digital words to control the master and slave D/A converters  210 ,  220 . Typically, each of the digital words controlling the master and slave D/A converters  210 ,  220  is less than N bits long. In one exemplary embodiment, the digital input to the master D/A converter  210  is varied during a coarse tuning mode, while the input to the slave D/A  220  is fixed. Then, the digital input to slave D/A converter  220  is varied during a fine tuning mode, while the input to master D/A  210  is fixed, so that the output Y is, within a specified precision, equal to a desired value. The master D/A converter  210  can be configured to hold its state after one or more predefined requirements are met (that define a coarse tuning). Then, the slave D/A converter  220 , after being held at an appropriate mid-range value during the coarse tuning mode, can be configured for continuous fine tuning of the output with more precision than is possible with the master D/A converter  210 . Such coarse and fine tuning modes might be used, for example, in a DLL, to first coarsely tune the delay of the underlying delay line, and then to fine tune the delay to align the phases of the input and the output of the delay line.  
         [0018]     In this manner, the digital-to-analog converter  200  of the present invention efficiently provides both a wide operating range during a “coarse” locking mode, and a required level of precision during a “fine” locking mode.  
         [0019]     As discussed further below in conjunction with  FIG. 3 , the output of the slave D/A converter  220 , and thus both the range and step size of the D/A converter  200  in a fine tuning mode, can be scaled up or down by adjusting the gain or attenuation of the scaling stage  230 . This provides a means to change the precision of the D/A  200  in a fine tuning mode without increasing the size or complexity of the slave D/A  220 . For example, the effective step size of the slave D/A  220  can be reduced, at the expense of reduced output range in the fine tuning mode, by decreasing the gain of stage  230 .  
         [0020]     One embodiment of the present invention recognizes that a binary weighted current-mode D/A converter can introduce noise at major transitions in its input word (e.g., code is 01111111 switching to 10000000 or vice versa). Generally, an N-bit binary weighted D/A converter is implemented using N current sources, each of which is controlled by one bit of the digital input word. Further, the current controlled by bit i is 2 i  times the current controlled by the LSB, where i corresponds to 0 for the LSB and N−1 for the MSB. For example, in a three bit binary weighted D/A converter, the three current sources will have relative weights of 4, 2, and 1, respectively. When the digital input word is equal to 011, the two smallest current sources will be active, and summed together to form the output current If the digital input word changes to 100, the two smallest current sources will turn off and the largest current source will turn on. If the current sources do not all turn on and off at precisely the same time, a noise spike will be present in the output.  
         [0021]     It is well known in the literature that such noise spikes may be prevented by implementing the digital-to-analog converter using thermometer encoding. A thermometer-encoded N-bit D/A converter is comprised of 2 N -1 equal valued current sources. Returning to the previous example, a three bit thermometer encoded D/A converter is comprised of seven current sources. In this manner, a single LSB change in the digital input word turns on or off only a single current source, thus avoiding the aforementioned noise spike. Note that the number of current sources, and thus the size and complexity of the converter, increases exponentially with the number of bits, N. Thus, the technique of thermometer encoding is used sparingly in low-cost D/A converter designs.  
         [0022]     In one exemplary embodiment of the present invention, the master DIA converter  210  is embodied as a binary weighted D/A converter, and the slave D/A converter  220  is embodied as a thermometer encoded D/A converter.  
         [0023]     The proposed master/slave D/A converter  200  reduces the overall D/A converter size and power. In addition, when implemented using the thermometer encoded slave D/A converter and binary weighted master D/A converter combination, the MSB switching noise inherent in binary encoded D/A converters will not be present in fine tuning mode.  
         [0024]      FIG. 3  is a characteristic curve  300  illustrating the transfer characteristic of an electrical delay line, which has a time delay that is controlled by an input bias current. Generally, as the bias current is increased, the delay decreases in a non-linear manner. If the master/slave D/A converter  200  is used in this application to provide the bias current, then scaling stage  230  provides a means to linearize this characteristic. For example, in region  310  of the curve  300 , the slope of the delay versus bias current curve is relatively steep, and thus the gain of stage  230  can be reduced. Similarly, in region  320  of the curve  300 , the slope of the curve is relatively shallow, and thus the gain of stage  230  can be increased. In this manner, the gain/attenuation stage  230  allows for some linearization of the control loop properties.  
         [0025]     Continuing the above example, where the master D/A converter  210  covers a broad range, such as 150 μA of current, and the slave D/A converter  220  covers a more narrow range, such as +/−20% of the master D/A converter value, a “multiply by 2” gain allows the slave D/A converter  220  to cover a larger range (+/−40%) of the master D/A converter value, while a “divide by 2” attenuation allows the slave D/A converter  220  to cover a smaller range (+/−10%) of the master D/A converter value.  
         [0026]     At least a portion of the D/A converter of the present invention may be implemented in an integrated circuit. In forming integrated circuits, a plurality of identical die are typically formed in a repeated pattern on a surface of a semiconductor wafer. Each die includes a device described herein, and may include other structures or circuits. The individual die are cut or diced from the wafer, then packaged as an integrated circuit. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.  
         [0027]     It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.

Technology Category: 5