Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This is a continuation application of U.S. patent application Ser. No. 11/834,643, filed on Aug. 6, 2007, and all benefits of such earlier application are hereby claimed for this new continuation application. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a dielectric layer structure and manufacturing method thereof, and more particularly, to a dielectric layer structure having superior process control and stability and manufacturing method thereof. 
         [0004]    2. Description of the Prior Art 
         [0005]    Devices in semiconductor industry need to undergo several complicated processes such as photolithograph process, dry or wet etching process, ion implantation, and heat treatment, etc. to construct precise integrated circuits in layers. Among those complicated processes, the process control of dielectric layer etching has become a critical factor, particularly in some application such as damascene process or interconnection technique. For example, in a damascene process, a dielectric layer is etched to form patterns comprising trenches or via. Then the trenches or via are filled with copper, and a planarization process is performed to complete formation of damascene structure. Additionally, to satisfy requirements of low RC delay effects, low-K material, ultra low-k (ULK) material, or porous low-k material is used to be the dielectric layer in the damascene structure. 
         [0006]    Please refer to  FIGS. 1-5 , which are schematic drawings of a conventional trench-first dual damascene process. As shown in  FIG. 1 , a substrate  10  having at least a conductive layer  12  and a base layer  14  comprising silicon nitride sequentially formed thereon is provided. And a dielectric layer  16 , a cap layer  18 , a metal hard mask layer  20 , and a bottom anti-reflective coating (BARC) layer  22  are sequentially formed on the base layer  14 . Then, a photoresist layer  30  is formed and patterned to form an opening  32  by a well-known photolithography method. The opening  32  is used to define a trench pattern of a damascene structure. 
         [0007]    Please refer to  FIGS. 1 and 2 . Subsequently, an etching process is performed. Accordingly a trench recess  34  is etched into the metal hard mask layer  20  and the cap layer  18  through the opening  32 . The etching is stopped on the cap layer  18 . The remaining photoresist layer  30  and the BARC layer  22  are then stripped off. 
         [0008]    As shown in  FIG. 3 , another BARC layer  36  is deposited over the substrate  10  and fills the trench recess  34 . And another photoresist layer  40  is formed on the BARC layer  36 . The photoresist layer  40  has an opening  42  patterned by a conventional photolithography method. The opening  42  is situated directly above the trench recess  34  and the conductive layer  12 , and is used to define a via pattern of a damascene structure. As shown in  FIG. 4 , the BARC layer  36 , the cap layer  18 , and the dielectric layer  16  are etched through the opening  42  with the photoresist layer  40  being an etching mask. Thus, a partial via feature  44  is formed in an upper portion of the dielectric layer  16 . Then the remaining photoresist layer  40  and the BARC layer  36  are stripped off by an oxygen plasma. 
         [0009]    Please refer to  FIG. 5 . Next, the metal hard mask layer  20  serves as an etching hard mask in an etching process, which is performed to etch away the cap layer  18  and the dielectric layer  16  through the trench recess  34  and the partial via  44 , thereby a dual damascene pattern comprising a trench opening  52  and a via opening  54  is obtained. Then, the damascene pattern is filled with a conductive metal such as copper followed by a planarization process that is performed, thus a dual damascene structure is formed. It is noteworthy that the dielectric layer  16  possesses a low mechanical strength and a compressive stress which leads to line distortion occurring in the dielectric layer  16 . 
         [0010]    Furthermore, there is another phenomenon drawing attention in the conventional damascene formation process: Generally, the cap layer  18  is a silicon oxide layer such as a tetra-ethyl-ortho-silicate (TEOS) based silicon oxide layer with TEOS used as a precursor. Because the TEOS layer comprises lots of Si—OH bonds and Si—H dangling bonds, the TEOS layer is a hydrophilic layer which is apt to absorb moisture. And the absorbed moisture is then desported from the TEOS layer and into the dielectric layer  16  in following process, thus Kelvin via open are formed in the dielectric layer  16 . Kelvin via open reduces reliability of the process and influences electrical performance of the damascene interconnects formed following. 
         [0011]    To solve the problem mentioned above, those skilled in the art provide many approaches, for example, a multi-layered cap layer such as a tri-layered cap layer is provided. The tri-layered cap layer provides a tensile stress layer offering a tensile stress which is opposite to the compressive stress of the dielectric layer. The multi-layered cap layer also provides hermetical layers sandwiching the tensile stress layer to prevent the tri-layered cap layer itself from absorbing the moisture and to prevent the dielectric layer from the desported moisture. However, due to the multi-layered characteristic, the process for the multi-layered cap layer has inferior process control, for example, it is not easy to form openings or recesses in the multi-layered cap layer. And The multi-layered cap layer also has inferior process stability. Therefore, a simple layer capable of balancing stress in the dielectric layer and preventing itself from absorbing moisture is needed. 
       SUMMARY OF THE INVENTION 
       [0012]    Therefore the present invention provides a dielectric layer structure and a manufacturing method thereof to prevent line distortion and Kelvin via open formation in dielectric layer. 
         [0013]    According to the claimed invention, a method for manufacturing a dielectric layer structure is provided, the method includes providing a substrate, blanketly forming a low-k dielectric layer of an interlayer dielectric (ILD) layer, the low-k dielectric layer covering at least a first metal interconnect structure on the substrate, blanketly forming a single tensile film of the ILD layer having a thickness of 200-1500 angstroms on the low-k dielectric layer, and performing a moisture preventing treatment on the single tensile film. 
         [0014]    According to the claimed invention, a dielectric layer structure is provided. The dielectric layer structure comprises a low-k dielectric layer, and a single tensile hydrophobic film positioned on the low-k dielectric layer. 
         [0015]    According to the dielectric layer structure and the method manufacturing thereof, the single tensile hydrophobic film is used to be a cap layer on the dielectric layer structure. Therefore a tensile stress comparative to the stress of the dielectric layer is provided to prevent line distortion in the dielectric layer. And the hydrophobic characteristic of the single tensile hydrophobic film prevents itself from moisture absorption, thus the Kelvin via open in the dielectric layer resulted by water desorpted from the single tensile hydrophobic film in following processes is also avoided. 
         [0016]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIGS. 1-5  are schematic drawings of a conventional trench-first dual damascene process. 
           [0018]      FIGS. 6-12  are schematic drawings illustrating a preferred embodiment of the method for manufacturing a dielectric layer structure. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Please refer to  FIGS. 6-12 , which are schematic drawings illustrating a preferred embodiment of the method for manufacturing a dielectric layer structure according to the present invention. As shown in  FIG. 6 , a substrate  100  is provided. The substrate  100  comprises a metal layer  102  serving as a conductive layer and a base layer  104  comprising silicon nitride or SiCHN. Then a low-k dielectric layer  106  is sequentially formed thereon. The low-k dielectric layer  106  comprises porous low-k dielectric material or ultra low-K (ULK) material. A thickness of the low-k dielectric layer  106  is about 800-5000 angstroms. 
         [0020]    Please refer to  FIG. 7 . Next, a single tensile film  108  comprising tetra-ethyl-ortho-silicate (TEOS) is formed on the low-k dielectric layer  106  by a deposition process. The deposition process comprises a plasma-enhanced vapor deposition (PECVD) process, a sub-atmosphere chemical vapor deposition (SACVD) process, or an atmosphere chemical vapor deposition (APCVD) process. A high-frequency RF power and a low-frequency RF power of the deposition process can be adjusted to control the tensile stress of the single tensile film  108  according to the stress in the low-k dielectric layer  106 . For example, when the high-frequency RF power is about 750-850 Watts and the low-frequency RF power is about 100-200 Watts, the tensile stress of the single tensile film  108  is about 50-100 MPa. A thickness of the single tensile film  108  is also adjustable according to the thickness of the low-k dielectric layer  106 . For example, when the thickness of the low-k dielectric layer  106  is 800-5000 angstroms, the thickness of the single tensile film  108  is about 200-1500 angstroms. 
         [0021]    Silane (SiH 4 ), TEOS, tetra-methyl silane (4 MS), tetra-methyl cyclo tetra-siloxane (TMCTS), diethoxy-methyl-silane (DEMS) or other silicon-containing chemicals can be added in the deposition processes as a precursor, and CO 2 , N 2 O, O 2 , or O 3  can be added as an oxidizing agent. In addition, He, Ar, N 2 , NH 3 , CO 2 , or O 2  can be used in the preferred embodiment for a pre-treatment or a post-treatment. 
         [0022]    Please refer to  FIG. 8 . Then, a moisture preventing treatment is performed to the single tensile film  108 . The moisture preventing treatment comprises an UV treatment, an electromagnetic treatment, or an N-plasma treatment. The moisture preventing treatment is used to alter the polarity of the single tensile film  108  for enhancing moisture preventing effect of the single tensile film  108 . For example, the UV treatment is performed with an UV light  110  having a wavelength of 50-400 nanometers (nm) at a temperature of about 250-450° C. for 1-5 minutes. In the UV treatment, the UV light  110  is used to break the Si—OH bonds and the Si—H dangling bonds in the single tensile film  108 . Therefore the Si—OH bonds and the Si—H dangling bonds are eliminated and Si—O bonds or Si—Si bonds are formed. Thus the polarity of the single tensile film  108  is altered from hydrophilic into hydrophobic and a single tensile hydrophobic film  112  is obtained as shown in  FIG. 8 . Moreover, the N-plasma treatment is performed with an N-containing plasma for nitrifying a surface of the single tensile film  108 , and thus a hydrophobic surface  122  is obtained as shown in  FIG. 9 . 
         [0023]    Please refer to  FIG. 10 . After performing the moisture preventing treatment, a metal hard mask layer  130  comprising TiN is formed on the single tensile film  108 . When forming the metal hard mask layer  130 , the substrate  100  is placed in an nitrogen environment, then an N-plasma is introduced to bombard a Ti metal target, thus the metal hard mask layer  130  comprising TiN is formed. It is noteworthy that before bombarding the Ti metal target, said N-plasma can be used in the N-plasma treatment, therefore the hydrophobic surface  122  is obtained and the step of forming the metal hard mask layer  130  can be performed in the same apparatus. Thus it can be seen that the N-plasma treatment, which is one approach of the moisture preventing treatment, and the step of forming the metal hard mask layer  130  can be performed in-situ. Of course the moisture preventing treatment and the step of forming the metal hard mask layer  130  can be performed ex-situ. Furthermore, as shown in  FIG. 10 , the single tensile film  108  can be altered to be the single tensile hydrophobic film  112  with the UV treatment first, then its surface can be treated to be the hydrophobic surface  122  with the N-plasma treatment, and the metal hard mask layer  130  can be formed in the same apparatus. 
         [0024]    Please refer to  FIGS. 11-12 . Then, a photoresist layer  140  is formed on the metal hard mask layer  130 . Additionally, a bottom anti-reflective coating (BARC) layer (not shown) can be formed on the metal hard mask layer  130 . And a conventional photolithography method is performed to pattern the photoresist  140 , thus an opening  142  used to define a pattern is formed as shown in  FIG. 11 . Please refer to  FIG. 12 , an etching process is performed to etch the metal hard mask layer  130  to the single tensile hydrophobic film  112  through the opening  142  and to form an opening  144 . A depth of the opening  144  is not limited as shown in  FIG. 12  and is adjustable according to requirements of the process, even to penetrate the single tensile hydrophobic film  112 . 
         [0025]    According to the method for manufacturing dielectric layer structure provided by the present invention, the compressive stress of the low-k dielectric layer  106  can be balanced by the tensile stress provided by the single tensile film  108 , therefore pattern or line distortion in the low-k dielectric layer  106  due to the compressive stress is avoided effectively. And the single tensile film  108  which comprises hydrophilic TEOS is altered in to the single tensile hydrophobic film  112 , even to further comprise the hydrophobic surface  122  by the moisture preventing treatments, therefore the moisture absorption is effectively prevented. Thus problems of moisture absorption in the low-k dielectric layer  106  from the single tensile film  108  and moisture desorption from the low-k dielectric layer  106  in following processes which causes Kelvin via open are fundamentally prevented. Additionally, when the low-k dielectric layer  106  comprises porous low-k dielectric material or ULK material which is more susceptible to the contaminant and damage, the single tensile film  108  provided by the present invention can prevent defects such Kelvin via open more effectively. Therefore process stability is improved. What is noteworthy is that due to the single tensile hydrophobic film  112  comprising only one lamination, the entire process further benefits from simpler process control and superior process stability. 
         [0026]    Please refer to  FIGS. 8 and 9  again. As mentioned above, the present invention provides a dielectric layer structure comprising a low-k dielectric layer  106  and a single tensile hydrophobic film  112  positioned on the low-k dielectric layer  106 . The low-k dielectric layer  106  comprises porous low-k dielectric material or ULK material. A thickness of the low-k dielectric layer  106  is about 800-5000 angstroms. 
         [0027]    The single tensile hydrophobic film  112  comprises TEOS. A thickness of the single tensile hydrophobic film  112  can be adjusted according to the thickness of the low-k dielectric layer  106  therefore a range of the thickness of the single tensile hydrophobic film  112  is 200-5000 angstroms. The single tensile hydrophobic film  112  possess a tensile stress which is comparative to a compressive stress of the low-k dielectric layer  106 . The single tensile hydrophobic film  112  can comprise a nitrified surface serving as a hydrophobic surface  122 . 
         [0028]    According to the dielectric layer structure provided by the present invention, the compressive stress of the low-k dielectric layer  106  can be balanced by the tensile stress provided by the single tensile hydrophobic film  112 , therefore pattern or line distortion in the low-k dielectric layer  106  is avoided effectively. And since the single tensile hydrophobic film  112  has the hydrophobic feature, moisture will not be absorbed, therefore the moisture absorption is effectively prevented. Thus problems of moisture absorption in the low-k dielectric layer  106  from the single tensile film  108  and moisture desorption from the low-k dielectric layer  106  in following processes which causes Kelvin via open are fundamentally prevented. 
         [0029]    Additionally, the dielectric layer structure provided by the present invention further comprises a metal hard mask layer (shown in  FIG. 10 ) positioned on the single tensile hydrophobic film  112  for defining patterns and protecting the low-k dielectric layer  106 . 
         [0030]    As mentioned above, according to the dielectric layer structure and the method manufacturing thereof, the single tensile hydrophobic film is used to balance a comparative stress of the former layer such as the dielectric layer, therefore pattern or line distortion in the dielectric layer is prevented. And the hydrophobic characteristic of the single tensile hydrophobic film prevents itself from moisture absorption, thus the Kelvin via open in the dielectric layer resulted by water desorpted from the tensile hydrophobic film in following processes is also avoided. In other words, the dielectric layer structure provided by the present invention not only effectively improves the process control and process stability of the entire process, but also improves the process result. 
         [0031]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Category: 5