Patent Document

[0001]    The present application a Continuation Application of U.S. patent application Ser. No. 14/524,966, filed on Oct. 27, 2014, which is a Continuation Application of U.S. patent application Ser. No. 13/438,731, filed on Apr. 3, 2012,which is based on and claims priority from Japanese patent application No. 2011-087972, filed on Apr. 12, 2011, now U.S. Pat. No. 8,908,455, the entire contents of which are incorporated herein by reference. 
     
    
     BACKGROUND 
       [0002]    The present invention concerns a semiconductor integrated circuit device and it particularly relates to a semiconductor integrated circuit device having a plurality of transistors formed over one identical diffusion layer. 
         [0003]    In the semiconductor integrated circuit device, reduction in the circuit area directly leads to reduction in the manufacturing cost. Particularly, in a case of semiconductor memory devices, etc., when the area of a circuit portion that is used repetitively in an identical layout pattern can be reduced even at the slightest, a significant effect of decreasing the cost can be obtained. 
         [0004]    A sense amplifier circuit is used repetitively as a circuit portion in a dynamic semiconductor memory device. In the dynamic semiconductor memory device, a plurality of sense amplifier circuits are coupled to a memory cell array in which memory cells are arranged in a matrix.  FIG. 1  is a circuit diagram showing the configuration of one sense amplifier circuit in a general dynamic semiconductor memory device. 
         [0005]    Referring to the constitutional elements of the sense amplifier circuit in  FIG. 1 , the sense amplifier circuit includes a first bit line BLT, a second bit line BLN, a sense amplifier SA, a precharge/balance device Q, an equalize signal input portion EQ, and a half power source voltage input portion HVC. The precharge/balance device Q includes a first transistor Q 1  as a balance device, a second transistor Q 2  as a first precharge device, and a third transistor Q 3  as a second precharge device. As the most general sense amplifier SA, a simple flip-flop circuit is used. 
         [0006]    The coupling relation for the constitutional elements in the sense amplifier circuit in  FIG. 1  is to be described. One end of the sense amplifier SA is coupled to a first bit line BLT. The other end of the sense amplifier SA is coupled the second bit line BLN. One of the source and the drain of the first transistor Q 1  is coupled to the first bit line BLT. The other of the source and the drain of the first transistor Q 1  is coupled to the second bit line BLN. Gates of the respective first to third transistors Q 1  to Q 3  are coupled in common to the equalize signal input portion EQ. One of the source and the drain of the second transistor Q 2  is coupled to the first bit line BLT. One of the source and the drain of the third transistor Q 3  is coupled to the second bit line BLN. The other of the source and the drain of the respective second and third transistors Q 2  and Q 3  are coupled to the half power source voltage input portion HVC. 
         [0007]    The operation of the sense amplifier circuit shown in  FIG. 1  is to be described briefly. At first, the potential difference between the first and second bit lines BLT and BLN is decided depending on the state of a memory cell coupled to one of the bit lines thereof and selected by a word line. 
         [0008]    The half power source voltage input portion HVC supplies a half power source voltage as one-half of a power source voltage VCC to the source-drain coupling portion of the second and third transistors Q 2  and Q 3 . As a result, the second and third transistors Q 2  and Q 3  precharge the half power source voltage to the first and the second bit lines BLT and BLN. Since the second and third transistors Q 2  and Q 3  operate as two precharge devices, they are generally designed with an identical size of the gate width and in a symmetrical layout. 
         [0009]    Finally, the sense amplifier SA amplifies the voltages of the first and second bit lines BLT and BLN to complementary potentials in accordance with the difference between the potentials and the half power source voltage respectively. 
         [0010]    Then, the gates of the first, second, and third transistors Q 1 , Q 2 , and Q 3  are provided an equalize signal from the equalize signal input portion, respectively. As a result, the source and the drain are conducted in each of the first, second, and third transistors Q 1 , Q 2 , and Q 3 , and the voltages-of the first and second bit lines BLT and BLN become identical. While the same effect can be obtained only by the second and third transistors Q 2  and Q 3 , if the first transistor is added, a potential is supplied to the first and second bit lines BLT and BLN and the potentials of the BLT and BLN can be equalized at a higher speed by the first transistor when it is intended to equalize the voltages between them. As described above, since the first transistor Q 1  operates as a balance device, the gate width is generally designed to be longer than the gate width of the second or third transistor Q 2  or Q 3  so that a larger current flows at once. 
         [0011]      FIG. 2A  is a plan view showing a layout of a semiconductor integrated circuit portion that schematically illustrates the precharge/balance device Q shown in  FIG. 1 .  FIG. 2B  is a plan view showing another layout of a semiconductor integrated circuit portion that schematically illustrates the precharge/balance device Q in  FIG. 1 . 
         [0012]    Each of the semiconductor integrated circuit portions in  FIG. 2A  and  FIG. 2B  includes first to third transistors Q 1  to Q 3  in the same manner as the precharge/balance device Q in  FIG. 1 . In the layout of  FIG. 2A  and  FIG. 2B , the first bit line BLT, the second bit line BLN, the equalize signal input portion EQ, and the half power source voltage input portion HVC are drawn as contacts that can be coupled to respective wirings. 
         [0013]    In the layout of  FIG. 2A , the first, second, and third transistors Q 1 , Q 2 , and Q 3  are formed over one identical diffusion layer  11 . The first, second, and third transistors Q 1 , Q 2 , and Q 3  have a gate in common, and the gate is coupled to the contact for the equalize signal input portion EQ. The first and second transistors Q 1  and Q 2  also have the source or the drain in common, and the source or the drain is coupled to the contact for first bit lines BLT. The first and third transistor Q 1  and Q 3  also have the source or the drain in common and the source or the drain is coupled to the contact for the second bit lines BLN. The second and third transistors Q 2  and Q 3  also have the source or the drain in common and the source or the drain is coupled to the-contact for the half power source voltage input portion HVC. The second and third transistors Q 2  and Q 3  are arranged such that the directions of the respective gate width are arranged on one extension line. Further, the first transistor Q 1  is arranged such that the direction of the gate width is different from the direction of the gate width of the second or third transistor Q 2  or Q 3 . 
         [0014]    In the layout of  FIG. 2B , the layout of  FIG. 2A  is rotated by 90° and, further, the position of the contact for the equalize signal input portion EQ is changed to the top of the gate protrusion portion of the first transistor Q 1 . Either the layout of  FIG. 2A  or  FIG. 2B  has been generally used so far. 
         [0015]    In connection with the above technique, Japanese Patent No. 3787500 contains disclosure regarding a write/read circuit. The write/read circuit evaluates at least one of bit lines (BL, BBL) in a DRAM memory. The write/read circuit includes at least two transistor pairs (T 1 /T 2 , T 4 /T 5 ) and two transistors (T 3 /T 6 ) for evaluation. The two transistor pairs (T 1 /T 2 , T 4 /T 5 ) for evaluation have transistors of an identical channel type respectively. The two transistors (T 3 /T 6 ) apply voltages (VDD; GND) to the transistor pairs (T 1 /T 2 , T 4 /T 5 ). The transistors used in the transistor pairs (T 1 /T 2 , T 4 /T 5 ) are vertical MOS transistors (T 1 , T 2 , T 4 , and T 5 ). The vertical MOS transistors (T 1 , T 2 , T 4 , and T 4 ) in each of the transistors pairs (T 1 /T 2 , T 4 /T 5 ) and the transistors (T 3 , T 6 ) used for applying the voltage (VDD; GND) have respective common source/drain regions ( 59 ,  63 ). 
         [0016]    Further, Japanese Unexamined Patent Publication No. 2004-87074 discloses a semiconductor integrated circuit device. The semiconductor integrated circuit device includes a sense amplifier, a first precharge MOSFET, a selection switch MOSFET, a second precharge MOSFET, and a dynamic memory cell. The sense amplifier includes a CMOS latch circuit for amplifying and holding a pair of input/output node siynals corresponding to an operation timing signal. The first precharge MOSFET includes a pair of transistors disposed to input/output nodes, put to an on-state in a precharge period, and supplying a precharge voltage to respective complementary bit line pairs of the input/output nodes. The selection switch MOSFET couples the input/output node and the complementary bit line pair corresponding to a selection signal. The second precharge MOSFET is disposed between the pair of complementary bit lines for short circuiting the same. The dynamic memory cell is disposed between one of the pair of complementary bit lines and a word line crossing the same and includes an address selection MOSFET and a memory capacitor. The semiconductor integrated circuit device has a feature of including a memory circuit in which the gate insulation film of the second precharge MOSFET is formed to a smaller thickness than that of the gate insulation film-of the selection MOSFET. 
         [0017]    Further, Japanese Unexamined Patent Publication No. 2005-340367 discloses a semiconductor integrated circuit device. The semiconductor integrated circuit device includes a sense amplifier, precharge MOSFETs including paired transistors, a selection switch MOSFET, a first equalize MOSFET, and a dynamic memory cell. The sense amplifier includes a CMOS latch circuits for amplifying and holding signals of a pair of input/output node signals corresponding to an operation timing signal. The paired precharge MOSFET are disposed to the pair of input/output nodes, put to an on state during a precharge period and supplies a precharge voltage to each of the input/output nodes. The selection switch MOSFET couples the pair of input/output nodes and the complementary bit line pair corresponding to a selection signal. The first equalize MOSFET is disposed between the pair of complementary bit lines for short circuiting the same during a precharge period. The dynamic memory cell is disposed between one of the pair of complementary bit lines and a word line crossing the same, and includes an address selection MOSFET and a memory capacitor. The gate insulation film of the selection switch MOSFET and the first equalize MOSFET is formed with a gate insulation film of a first thickness. The gate insulation film of the precharge MOSFET is formed with a gate insulation film of a second thickness which is smaller than the first thickness. A precharge signal corresponding to a power source voltage is supplied to the precharge MOSFET. The first equalize MOSFET and the selection switch MOSFET include a memory circuit which is supplied with an equalize-signal corresponding to an elevated voltage defined to higher than the power source voltage and a selection signal. 
       SUMMARY 
       [0018]    In general dynamic semiconductor memory devices, integration has advanced and the cell array has been divided. Then, for higher speed operation, a sense amplifier is disposed on every divided array and the occupying area of the sense amplifier is also increased, particularly in products such as built-in DRAM (eDRAM). In such situation, it is desired for the layout of the sense amplifier that the sense amplifier is formed such that the height in the extending direction of the bit line is reduced. 
         [0019]      FIG. 3A  is a plan view showing the size of the precharge/balance device Q shown in  FIG. 2A  when arranged in a vertical direction. In this case, the longitudinal size L 3 A in the precharge/balance device Q is determined as described below. L 3 A=L 1 +WQ 1 +LQ 2 +L 2  where L 1  represents a gate protrusion length, WQ 1  represents the gate width of the first transistor Q 1 , LQ 2  represents a gate length of the second transistor Q 2 , L 2  represents the minimum source-drain width with contact. The gate length LQ 2  of the second transistor Q 2  is equal with the gate length LQ 3  of the third transistor Q 3 . 
         [0020]      FIG. 3B  is a plan view showing the size of the precharge/balance device Q shown in  FIG. 2B  when arranged in the lateral direction. In this case, the longitudinal size L 3 B in the precharge/balance device Q is determined as described below. L 3 B=(L 1 ×2)+WQ 2 +WQ 3  where L 1  represents the gate protrusion length in the same manner as described above, WQ 2  represents the gate width of the second transistor Q 2 , and WQ 3  represents the gate width of the third transistor Q 3 . 
         [0021]    The lateral size of the precharge/balance device Q in  FIG. 3A  is equal wither the longitudinal size L 3 B of the precharge/balance device Q in  FIG. 3B . In the same manner, the lateral size of the precharge/balance device Q in  FIG. 3B  is equal with the longitudinal size L 3 A of the precharge/balance device Q in  FIG. 3A . 
         [0022]    Accordingly, when both of the two sizes L 3 A and L 3 B are within a range of a width occupied by the two rows of memory cells, the shape of the precharge/balance device Q is generally selected such that the shorter side is in the longitudinal direction. However, the gate width of the first transistor Q 1  is often designed actually longer than the gate width of the second or third transistor Q 2  or Q 3 , and the gate protrusion length from the diffusion layer has to be ensured sufficiently in each of the first to third transistors Q 1  to Q 3 . Accordingly, it is desired that the difference between the two sizes L 3 A and L 3 B is not so great and the longitudinal size for the precharge/balance device Q is further decreased. 
         [0023]    Then, means for solving the subject are to be described below with reference to numerical numbers used in preferred embodiments of the invention. The numerical numbers are attached for clarifying the corresponding relation between claims and the preferred embodiments of the invention. However, such numerical numbers should not be used for construing the technical range of the invention described in the claims. 
         [0024]    A semiconductor integrated circuit device according to the invention includes a diffusion layer  11 , a first transistor Q 2 , and a second transistor Q 3 . The diffusion layer  11  is formed over a semiconductor substrate. The first transistor Q 2  is formed over the diffusion layer  11 . The second transistor Q 3  is formed over the diffusion layer  11 . One of the source and the drain of the first transistor Q 2  is coupled to one of the source and the drain of the second transistor Q 3 . The gate of the first transistor Q 2  is coupled to the gate of the second transistor Q 3 . The lateral direction of the gate of the first transistor Q 2  is different from the lateral direction of the gate of the second transistor Q 3 . 
         [0025]    The semiconductor integrated circuit device according to the invention equalizes two signal lines (BLN, BLT) extending in a first direction by at least three devices (Q 1 , Q 2 , and Q 3 ). The semiconductor integrated circuit device according to the invention includes the diffusion layer  11  and a gate. The diffusion layer  11  is in common with the three devices Q 1 , Q 2 , and Q 3 . The gate is formed over the diffusion layer  11 . The gate includes a first region (corresponding to Q 1  and Q 2 ) and a second region (corresponding to Q 3 ). The first region (corresponding to Q 1  and Q 2 ) extends across the diffusion layer  11  in a direction crossing the first direction. The second region (corresponding to Q 3 ) branches from the first region (corresponding to Q 1  and Q 2 ) only in the direction of one side of the diffusion layer  11  in the first direction. Two devices Q 1  and Q 2  among three devices are formed in the first region such that the gate width is different from each other. The remaining one device Q 3  among the three devices is formed in a second region (corresponding to Q 3 ) such that the gate width is substantially equal with that of one element Q 2  of shorter gate width in the two devices Q 1  and Q 2 . 
         [0026]    According to the invention, since two transistors generally arranged in one identical extension line are intentionally arranged in different directions, the size of the semiconductor integrated circuit device can be reduced further, particularly, in one direction. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0027]      FIG. 1  is a circuit diagram showing the configuration of a sense amplifier circuit in a general dynamic semiconductor memory device; 
           [0028]      FIG. 2A  is a plan view showing a layout of a semiconductor integrated circuit portion that schematically illustrates the precharge/balance device in  FIG. 1 ; 
           [0029]      FIG. 2B  is a plan view showing another layout of a semiconductor integrated circuit portion that schematically illustrates the precharge/balance device in  FIG. 1 ; 
           [0030]      FIG. 3A  is a plan view showing the size of the precharge/balance device shown in  FIG. 2A  when arranged in a vertical direction; 
           [0031]      FIG. 3B  is a plan view showing the size of the precharge/balance device shown in  FIG. 2B  when arranged in a vertical direction; 
           [0032]      FIG. 4  is a plan view showing a layout of a semiconductor integrated circuit device according to a first embodiment of the invention; 
           [0033]      FIG. 5  is a plan view showing a layout of a semiconductor integrated circuit device according to a second embodiment of the invention; and 
           [0034]      FIG. 6  is a plan view showing a layout of a semiconductor integrated circuit device according to a third embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0035]    Preferred embodiments of a semiconductor integrated circuit device according to the invention are to be described below with reference to the accompanying drawings. 
       First Embodiment 
       [0036]      FIG. 4  is a plan view showing a layout of a semiconductor integrated circuit device according to a first embodiment of the invention. The semiconductor integrated circuit device in  FIG. 4  corresponds to a portion of the precharge/balance device Q in the sense amplifier circuit shown in the circuit diagram of  FIG. 1  described above. Then, the circuit diagram of  FIG. 1  is at first explained again. 
         [0037]    Constitutional elements in the sense amplifier circuit in  FIG. 1  are to be described. The sense amplifier circuit in  FIG. 1  includes the first bit line BLT, the second bit line, the sense amplifier SA, the precharge/balance device Q, the equalize signal input portion EQ, and the half power source voltage input portion HVC. The precharge/balance device Q includes the first transistor Q 1  as the balance device, the second transistor Q 2  as the first precharge device, and the third transistor Q 3  as the second precharge device. As the sense amplifier SA, a latch circuit or the like having a plurality of transistors in combination is generally used. 
         [0038]    The coupling relation for the constitutional elements in the sense amplifier circuit in  FIG. 1  is to be described. One end of the sense amplifier SA is coupled to the first bit line BLT. The other end of the sense amplifier SA is coupled to the second bit line BLN. One of the source and the drain of the first transistor Q 1  is coupled to the first bit line BLT. The other of the source and the drain of the first transistor Q 1  is coupled to the second bit line BLN. The gate of each of the first to third transistors Q 1  to Q 3  is coupled in common to the equalize signal input portion EQ. One of the source and the drain of the second transistor Q 2  is coupled to the first bit line BLT. One of the source and the drain of the third transistor Q 3  is coupled to the second bit line BLN. The other of the source and the drain of each of the second and third transistors Q 2  and Q 3  is coupled to the half power source voltage input portion HVC. 
         [0039]    Then, the constitutional elements of the semiconductor integrated circuit device in  FIG. 4  are to be described. A semiconductor integrated circuit device in  FIG. 4  includes a first bit line BLT, a second bit line BLN, a precharge/balance device Q, an equalize signal input portion EQ, a half power source voltage input portion HVC, and a diffusion layer  11 . The precharge/balance device Q includes a first transistor Q 1  as a balance device, a second transistor Q 2  as a first precharge device, and a third transistor Q 3  as a second precharge device. In  FIG. 4 , contacts that can be coupled to the respective wirings for the first bit line BLT, the second bit line BLN, the equalize signal input portion EQ, and the half power source voltage input portion HVC are shown by solid lines. Further, for the first bit line BLT and the second bit line BLN, an example of arrangement for the wirings in the upper layer is shown by broken lines. 
         [0040]    The positional relation and the coupling relation of the constitutional elements of the semiconductor integrated circuit device in  FIG. 4  are to be described. In the semiconductor integrated circuit device shown in  FIG. 4 , the first, second, and third transistors Q 1 , Q 2 , and Q 3  are formed over an identical diffusion layer  11 . The first, second, and third transistors Q 1 , Q 2 , and Q 3  have a gate in common, and the gate is coupled to the contact for an equalize signal input portion EQ. The first and second transistors Q 1  and Q 2  have a source or a drain in common, and the source or the drain is coupled to the contact for the first bit line BLT. Also the first and third transistors Q 1  and Q 3  have the source or the drain in common, and the source or the drain is coupled to a contact for the second bit line BLN. Also the second and third transistors Q 2  and Q 3  have the source or the drain in common, and the source or the drain is coupled to a contact for the half power source voltage input portion HVC. The first and second transistors Q 1  and Q 2  are arranged such that the respective gates are arranged in on one straight line. Further, the third transistor Q 3  is arranged such that the lateral direction of the gate is different from the lateral direction of gate of the first or second transistor Q 1  or Q 2 . 
         [0041]    Wirings for the first and second bit lines BLT and BLN can be arranged optionally by way of a plurality of contacts provided respectively in a layer upper than the layout in  FIG. 4 . However, it is preferred that the wirings for the first and second bit lines BLT and BLN are arranged in the direction of coupling the sense amplifier circuit and the memory cell array, that is, in the vertical direction in  FIG. 4 . Further, wirings coupled to the equalize signal input portion EQ are arranged in the upper layer preferably in the direction different from that of the first and second bit lines BLT and BLN and, more preferably, in the direction perpendicular thereto. 
         [0042]    The operation of the semiconductor integrated circuit device in  FIG. 4  is to be described. Since a general precharge/balance device Q in the circuit diagram in  FIG. 4  is provided also by a layout in  FIG. 4 , an identical function is obtainable as the matter of fact. The operation of the sense amplifier in  FIG. 1  is to be described schematically again. 
         [0043]    At first, the potential difference between the first and second bit lines BLT and BLN is determined depending on the state of a memory cell coupled to one of the bit lines and selected by a word line. 
         [0044]    Then, the half power source voltage input portion HVC supplies a half power source voltage which is one-half of the power source voltage VCC to the source-drain coupling portion of the second and third transistors Q 2  and Q 3 . As a result, the second and third transistors Q 2  and Q 3  precharge the half power source voltage to the first and second bit lines BLT and BLN. As described above, the second and third transistors Q 2  and Q 3  operate as two precharge devices. 
         [0045]    Then, the sense amplifier SA amplifies the difference between the voltage on the first and second bit lines BLT and BLN, and the half power source voltage to a predetermined reference voltage in accordance with a control signal from the outside. 
         [0046]    Then, the equalize signal input portion EQ supplies an equalize signal to the gate of the first, second, and third transistors Q 1 , Q 2 , and Q 3 . As a result, the source and the drain are conducted in each of the first, second, and third transistors Q 1 , Q 2 , and Q 3 , and the voltages of the first and second bit lines BLT and BLN become equal. In this case, while a similar effect can be obtained only by the second and third transistors Q 2  and Q 3 , when the first transistor is added, the state where the voltages of the first and second bit lines BLT and BLN become identical is attained more rapidly. Thus, the first transistor Q 1  operates as a balance device. 
         [0047]    According to this embodiment, the vertical size L 4  in  FIG. 4  is determined as below. L 4 =L 1 +WQ 3 +LQ 1 +L 2  where L 1  represents a gate protrusion length, WQ 3  represents a gate width of the third transistor Q 3 , LQ 1  represents a gate length of the first transistor Q 1 , and L 2  represents a minimum source-drain width with contact. The gate width WQ 3  of the third transistor Q 3  is equal with the gate width WQ 2  of the second transistor Q 2 , and the gate length LQ 1  of the first transistor Q 1  is equal with the gate length LQ 2  and LQ 3  of the second and third transistors Q 2  and Q 3 . That is, according to this embodiment, the vertical size L 4  in  FIG. 4  is shortened by so much as the gate protrusion length L 1  compared with the case of  FIG. 3A  or  FIG. 3B  described above. 
         [0048]    The gate protrusion length L 1  is indispensable so that the gates of the first to third transistors Q 1  to Q 3  are formed appropriately in the diffusion layer  1 , and this is a length not negligible compared with the size of the diffusion layer  11 . Further, in a dynamic semiconductor memory device, etc., the sense amplifier circuit containing the precharge/balance device Q in  FIG. 4  is periodically arranged in the vertical direction of  FIG. 4 . Accordingly, reduction of the size in the vertical direction in  FIG. 4  according to this embodiment can provide an outstanding effect as the entire semiconductor integrated circuit device. 
         [0049]    In general dynamic semiconductor memory devices, etc., an identical equalize signal is supplied simultaneously to all of a plurality of sense amplifier circuits arranged along one side of a memory cell array. In such a case, when the layout in  FIG. 4  is arranged as one unit circuit in plurality in the lateral direction in  FIG. 4 , such unit circuits may be coupled in the lateral direction. That is, in a case of unit circuits adjacent in the right-to-left direction, the contact for the equalize signal input portion EQ arranged to the right end of the unit circuit on the left may be coupled to the gate protrusion portion of the second transistor Q 2  arranged to the left end of the unit circuit on the right. Further, input wirings to the diffusion layer  11  for the respective BLT and BLN in  FIG. 4  shown by dotted lines are only the schematic expression and they may also be formed, for example, by wide input wirings having a width for several contacts. 
       Second Embodiment 
       [0050]      FIG. 5  is a plan view showing a layout of a semiconductor integrated circuit device according to the first embodiment of the invention. In the semiconductor integrated circuit device shown in  FIG. 5 , a precharge/balance device Q according to the first embodiment of the invention that has been described with reference to  FIG. 4  is arranged and combined by the number of two in the right-to-left direction. In this embodiment, the precharge/balance device on the right has a layout identical with that in  FIG. 4 , while the precharge/balance device on the left has a layout mirror inverted left to right relative to the layout in  FIG. 4 . In the following description, the precharge/balance device on the left is referred to as a first precharge/balance device and the precharge/balance device on the right is referred to as a second precharge/balance device. 
         [0051]    Constitutional elements of the first and second precharge/balance devices are to be described. The first precharge/balance device includes a first diffusion layer  11 , first, second, and third transistors Q 1 , Q 2 , and Q 3 , a contact for a first bit line BLT 0 , a contact for a second bit line BLT 0 , a contact for an equalize signal input portion EQ, and a contact for a half power source voltage input portion HVC. The second precharge/balance device includes a second diffusion layer  12 , fourth, fifth, and sixth transistors Q 4 , Q 5 , and Q 6 , a contact for a third bit line BLT 1 , a contact for a fourth bit line BLN 1 , a contact for an equalize signal input portion EQ, and a contact for a half power source voltage input portion HVC. 
         [0052]    Description is to be made for the corresponding relation between each of the constituent elements in each of the first and second precharge/balance devices according to this embodiment shown in  FIG. 5 , and each of the constituent elements of the precharge/balance device according to the first embodiment of the invention shown in  FIG. 4 . The first and second diffusion layers  11  and  12  in  FIG. 5  correspond to the diffusion layer  11  in  FIG. 4 . The first and fourth transistors Q 1  and Q 4  in  FIG. 5  correspond to the first transistor Q 1  in  FIG. 4 . The second and fifth transistors Q 2  and Q 5  in  FIG. 5  correspond to the second transistor Q 2  in  FIG. 4 . The third and sixth transistors Q 3  or Q 6  in  FIG. 5  correspond to the third transistor Q 3  in  FIG. 4 . The contacts for the first and third bit lines BLT 0  and BLT 1  in  FIG. 5  correspond to the contacts for the first bit line BLT in  FIG. 4 . The contacts for the second and fourth bit lines BLN 0  and BLN 1  in  FIG. 5  correspond to the contact for the second bit line BLN in  FIG. 4 . The contact for the equalize signal input portion EQ in  FIG. 5  corresponds to the contact for the equalize signal input portion EQ in  FIG. 4 . The contact for the half power source voltage input portion HVC in  FIG. 5  corresponds to the contact for the half power source voltage input portion HVC in  FIG. 4 . 
         [0053]    Further, when more precharge/balance devices are arranged in the lateral direction in  FIG. 5 , the total number of the contacts for the equalize signal input portions EQ can be sometimes decreased to one severalth of the number of the precharge/balance devices. As has been described also for the first embodiment of the invention, this is a case where a plurality of sense amplifiers arranged in one row along one side of the memory cell array have an identical equalize signal in common. In this case, the pitch in the direction of arranging a plurality of precharge/balance devices can be further decreased. Alternatively, in a case where the lateral pitch in  FIG. 5  is fixed for the sake of the memory cell array, the gate width of the first and fourth transistors Q 1  and Q 4  that operate as the balance device can be further extended to also improve the performance of the balance device. 
         [0054]    Since the relation of arrangement and the coupling relation of other constituent elements in each of the first and second precharge/balance devices in  FIG. 5  as well as the operation thereof are identical with those of the first embodiment of the invention, further detailed explanation is to be omitted. 
       Third Embodiment 
       [0055]      FIG. 6  is a plan view showing a layout of a semiconductor integrated circuit device according to the first embodiment of the invention. For the first and second embodiments of the invention, while description has been made to the case of laterally arranging a plurality of diffusion layers, description is to be made for this embodiment to a case of vertically arranging a plurality of diffusion layers. 
         [0056]    The semiconductor integrated circuit device in  FIG. 6  includes a second diffusion layer  13  in addition to the precharge/balance device according to the first embodiment of the invention described with reference to  FIG. 4 . In a second diffusion layer  13 , a seventh transistor Q 7 , a contact BLT 2  for first bit line BLT, and contacts BLN 2  for a second bit line BLN are formed. A contact BLT 2  for the first bit lines BLT is coupled to the first bit lines BLT. A contact BLN 2  for a second bit line BLN is coupled to the second bit lines BLN. 
         [0057]    The contacts for the first bit lines BLT formed in the first and second diffusion layers  11  and  13  are coupled by way of wirings for the first bit line BLT in the upper layer. In the same manner, the contacts for the second bit lines BLN formed in the first and second diffusion layers  11  and  13  are coupled by way of wirings for the second bit line BLN in the upper layer. That is, the seventh transistor Q 7  can operate also as a sense amplifier SA or a portion thereof shown in the circuit diagram in  FIG. 1 . The semiconductor integrated circuit device in  FIG. 6  is hereinafter explained such that it corresponds to the entire sense amplifier shown in the circuit diagram in  FIG. 1 . 
         [0058]    The first and second diffusion layers  11  and  13  are arranged vertically in  FIG. 6 , and spaced apart by a predetermined distance. By arranging the gate protrusion portions of the third and seventh transistors Q 3  and Q 7  in a staggered pattern, the distance between the first and second diffusion layers  11  and  13  can be designed shorter than twice of the gate protrusion length L 1 . 
         [0059]    As described above, according to the layout of the semiconductor integrated circuit device of this embodiment, the vertical size in  FIG. 6  can be shortened further. 
         [0060]    Since the relation of arrangement and the coupling relation of other constituent elements in the semiconductor integrated circuit device according in this embodiment, as well as the operation thereof are identical with those of the first embodiment of the invention, further detailed explanation is to be omitted. 
         [0061]    The respective features in each of the preferred embodiments described above can be optionally combined within a range not technically conflicting with each other. For example, a plurality of diffusion layers can be naturally laid out by arranging them in the lateral direction as described for the first and second embodiments, and also in the vertical direction as described in the third embodiment. Further, in this case, the unit circuits according to the first to third embodiments may be partially or entirely invented vertically or laterally, or may be rotated clockwise or counterclockwise. 
         [0062]    While the description has been made mainly to the example of the sense amplifier circuit of the dynamic semiconductor memory device, the invention is applicable to any other semiconductor integrated circuit device and the embodiments described above do not restrict the invention. For example, the gate width of the first transistor Q 1  may not always be longer than the gate width of the second and third transistors Q 2  and Q 3 . Further, the gate width may not always be identical between the second and third transistors Q 2  and Q 3 .

Technology Category: g