Patent Document

RELATED APPLICATION DATA  
       [0001]     This application claims priority to U.S. patent application Ser. No. 09/839,376, filed Apr. 20, 2001 which claims priority to U.S. Provisional Patent Application No. 60/257,923, filed Dec. 21, 2000. 
     
    
     TECHNICAL FIELD  
       [0002]     The present invention relates generally to behavioral synthesis tools for creating integrated circuits, and more particularly relates to behavioral synthesis tools that allow for interactive interface allocation during the design of integrated circuits.  
       BACKGROUND  
       [0003]     The design of complex computer hardware no longer begins with a circuit diagram. Instead, it begins with a software program that describes the behavior or functionality of a circuit. This software program is written in a hardware description language (HDL)(e.g. VHDL or Verilog) that defines an algorithm to be performed with limited implementation details. Designers direct behavioral synthesis tools to generate alternate architectures by modifying constraints (such as clock period, number and type of data path elements, and desired number of clock cycles). A simulation tool (e.g., Modelsim by Mentor Graphics) simulates the functionality of the system prior to generating a physical implementation of the circuit.  
         [0004]     The HDL program is converted into a register transfer level (RTL) description. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.  
         [0005]     Although describing a system design in HDL provides great flexibility to designers, it is desirable to provide a greater level of abstraction to describe the system functionality. For example, programming languages like C and C++ are now being used as a starting point to describe the function of a circuit. The description of the system in C or C++ is then used by synthesis tools to generate a HDL description of the circuit.  
         [0006]     Unfortunately, certain aspects of the system&#39;s design cannot be described using conventional ANSI C and C++. For example, C and C++ cannot be used to describe hardware interfaces of the function, which are required to interact with the rest of the integrated circuit. Thus, a designer is forced to describe the functionality of a system design using C and then use HDL constructs to describe the interfaces. However, such a process is time consuming and costly.  
         [0007]     Several attempts have been made to adapt conventional C and C++ to add the capability to describe interface components. For example, SystemC is an adaptation of C++ that adds the capability of describing interface elements. However, languages such as SystemC suffer from the same inefficiencies as other HDLs. For example, the programmer is forced to learn the specific language commands, which takes away the benefits of using a generic language such as C or C++.  
         [0008]     Thus, there is a need for a tool that allows a designer to use a generic language, such as C or C++, but allows the designer to easily add hardware interfaces.  
       SUMMARY  
       [0009]     The present invention provides a behavioral synthesis tool that allows a designer to design an integrated circuit using a generic programming language, such as ANSI C or C++, without the need to include timing information into the source code. In one aspect, the source code is read into the behavioral synthesis tool and the user may dynamically allocate interface resources to the design. In another aspect, the dynamic allocation is accomplished through user input, such as a GUI, a command line, or a file. In another aspect, the behavioral synthesis tool automatically analyzes variables in the source code description and assigns the variables to interface resources. In yet another aspect, the variables and interface resources associated with the variables may be displayed in a hierarchical format in a GUI. In still another aspect, the GUI may allow for expanding and collapsing of different layers in the hierarchy. The GUI may also allow for drag-and-drop operations to modify the variable/interface resource allocation.  
         [0010]     These and other aspects will become apparent from the following detailed description, which makes references to the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is a block diagram of an integrated circuit including multiple IP cores, wherein an IP core includes logic and at least one interface resource.  
         [0012]      FIG. 2  shows a behavioral synthesis tool that allows a user to interactively modify interface resource allocation.  
         [0013]      FIG. 3  is a flow chart of a method for interactively modifying the interface resource allocation.  
         [0014]      FIG. 4  is a flow chart of a method for displaying interfaces and variables in a hierarchical format.  
         [0015]      FIG. 5  is an example of a graphical user interface showing a hierarchical display of variables and interface resources associated with those variables.  
         [0016]      FIG. 6  is an example of a variable selected in the hierarchical display and options for modifying the variable.  
         [0017]      FIG. 7  shows a hierarchical display with an interface resource selected and various options for modifying the interface resource.  
         [0018]      FIG. 8  shows reallocation of variables to interface resources through drag-and-drop operations.  
         [0019]      FIG. 9  shows the mapping of variables to an interface resource after a drag-and-drop operation.  
         [0020]      FIG. 10  is a client server network environment that may be used to implement the invention.  
         [0021]      FIG. 11  is an example flow chart of a method that may be used to implement the invention on a client server network.  
         [0022]      FIGS. 12A-12F  show various types of interface resources. 
     
    
     DETAILED DESCRIPTION  
       [0023]      FIG. 1  shows an integrated circuit  10  that includes multiple intellectual property (IP) cores shown generally at  12 . A particular IP core is shown at  14  and includes internal logic  16  and one or more interface resources shown generically at  18 . As described further below, the logic  16  is generated using a source code description of its functionality programmed in C, C++, or any other high-level programming language. The interface resources  18  are used to couple the logic  16  to the other IP cores  12  or the pins (not shown) of the integrated circuit  10 . The interface resource  18  includes an interface  20  and an I/O hardware component  22 . As described further below, the I/O hardware component  22  is a component written in a programming language (e.g., RTL). The interface  20  is a set of signals (e.g., control and data signals) used to communicate with the I/O hardware component  22 . There are generally three kinds of interface resources: inputs, outputs and inouts. If an input and output variable are mapped to the same resource, it becomes an inout resource.  
         [0024]     Turning briefly to  FIG. 12 , several examples are shown of possible interface resources that may be used. FIGS.  12 A-F are illustrated under the assumption that logic  16  is oriented left of the interface resource, while other IP cores  12  or other components communicating with the IP core are oriented on the right side. Also, the I/O hardware components  22  are shown as included by dashed lines, whereas the interface  20  represents the signals for communicating with the I/O hardware components.  
         [0025]      FIG. 12A  shows an I/O hardware component  22  that is simply a wire.  FIG. 12B  shows an I/O hardware component  22  that is a register. In this example the interface  20  includes the set of signals needed to write to the register.  FIG. 12C  shows registers  30 ,  32  which may be included in the logic  16  and which are used in combination with request line  34  to output data on register  32  and to provide a handshake mechanism through data available register  30  and request line  34 .  FIG. 12D  shows the I/O hardware component  22  as including a register  36  and a feedback multiplexer  38 . The interface  20  includes the set of signals necessary for enabling the register  36 , resetting the register, clocking the register, etc. and controlling the multiplexer  38 .  FIG. 12E  shows the I/O hardware component  22  as including a tri-state gate  46 , a data-in line (Din) and a data-out line (Dout), wherein a register  48  is within the logic  16 . The interface  20  includes the signals for communicating with the I/O component  22  including the control line (Ctl) and data on the Din line. Finally,  FIG. 12F  shows a I/O hardware component  22  that can receive data through a more complicated handshaking mechanism. A request register  50  is within the logic  16  and is used to request data from other IP cores  12  or from pins within the integrated circuit. Data may then be received on the Din line when available as indicated by the Data Avail line.  FIG. 12  shows only a few examples of possible interface resources  18  and others may readily be used as one skilled in the art would readily understand. More complicated interface resources could be designed to handle complete bus protocols. This would keep designers from having to deal with this kind of low-level timing in their high-level behavioral input. Additional buffering or queuing in the interface component may increase parallelism in the design and improve design performance.  
         [0026]      FIG. 2  shows a system  56 , wherein a user may interactively modify the interface resources. Block  60  represents source code describing the behavior of the hardware without including timing information. For example, a typical source code description is programmed in C or C++ or any other high-level programming language and describes the behavior of logic  16  within the IP core  14 . The source code is read into an intermediate database  64  within the behavioral synthesis tool  58 . This intermediate database may be modified by the user before generating RTL code shown at  66 . An interface resource library  68  is also read into the intermediate database  64  and includes the I/O hardware components  22  and interfaces  20  associated with those components. A user interface  70  allows for interactive modification of the interface resources in the intermediate database  64 . The user interface may take many forms, such as a graphical user interface, a command line displayed on a monitor, or a file input. Other techniques for inputting data may also be used as is well known in the art.  
         [0027]      FIG. 3  shows a flow chart of a method for interactively modifying the interface resource allocation without having to modify the source code. In process block  80 , the source code description of the logic  16  is provided without timing information. In process block  82 , the source code description is read into the intermediate database  64  ( FIG. 2 ). In process block  84 , the behavioral synthesis tool  58  analyzes variables within the source code description by parsing the source code description and searching for variable types that are pointers on the function interface or pointers to arrays. Pointers generally are associated with interface resources that need to communicate with other components outside of the logic  16 . Once such variables are automatically found within the source code description, an interface resource is obtained and automatically associated with an IO component from the interface resource library  68  and also automatically associated with the variable. To perform this type of assignment, the synthesis tool  58  determines a type associated with the variable. For example, if the variable is read and written, then the interface type is an inout. Thus, a memory that can be both read and written is selected from the interface resource library and assigned to that variable. In process block  86 , input is received from the user to update or modify the intermediate database  64 . In process block  88 , the user interactively modifies the interface resource allocation, as further described below, and such a modification is used to update the intermediate database at  86 . It should be noted that interface resources can be allocated to the source code description without modifying the original source code. Thus, a user can interactively modify the interface resources without having to reload the source code and without having to perform an additional compile of the source code that can be time consuming. In process block  90 , the RTL code is generated based on the updated intermediate database. In process block  92 , the RTL code is simulated and if desired, the user can return (not shown) to the intermediate database and interactively modify the interface resources again if the results of the simulation were not as desired. However, if the user is satisfied with the simulation, then a RTL synthesis is performed at  94 . Finally, the gate level design is generated, verified, and analyzed at  96 .  
         [0028]      FIG. 4  shows an example of a flowchart for displaying interface resources in a graphical user interface. In process block  110 , the source code description is read into the intermediate database  64  as previously described. In process block  112 , the source code is searched for input and output variables (pointers) and inout variables that require the assignment of interface resources. In process block  114 , the interface resource library  68  is searched for the possible interface resources that may be used with each variable. In process block  116 , if the user chooses to modify an interface resource, the synthesis tool  58  displays a list of candidate interface resources obtained from the interface resource library  68 . It should be noted that the candidate interface resources that are displayed are only a subset of the resource library because only resources are displayed which can work with the variable selected by the user. In process block  118 , when the user selects a particular interface resource out of the list of candidate resources, the behavioral synthesis tool displays the variables and interfaces associated with the variables in a hierarchical format, as further described below. Under the hierarchical format, one or more variables may be assigned to an interface resource. Each interface resource is then mapped to an interface component.  
         [0029]      FIG. 5  shows a graphical user interface (GUI)  140  that shows the interface resources and variables associated with those interface resources in a hierarchical format. The GUI allows a user to map each interface resource to a specific hardware element. In the example of  FIG. 5 , a source code description (not shown) of a fir filter was read into the behavioral synthesis tool  58 . The GUI has two panes shown at  142  and  144 . Pane  142  shows the interface resources and variables from the source code in hierarchical format. Pane  144  is used for optionally modifying the interface resource allocation or configuration. At the top of the hierarchy is the design for a filter shown at  146 . As shown at  148 , the design may be expanded or collapsed using standard GUI techniques. In this example, there are three or more child layers under a parent layer of  146 , including ports shown at  150 , arrays shown at  152  and one or more processes shown at  153 . Each of these child layers typically has additional sub-layers. For example, at  154 , an interface resource is shown and, at  156 , a variable is associated with that interface resource. Notably the variable  156  (in this example coeffs [2×11]) is shown as a sub-layer under the interface resource  154 . An array-type interface resource is shown at  158  with its associated variable shown at  160 . In the right hand pane  144 , there are several check boxes  162  associated with settings for the process fir filter. As further described below, the right hand pane  144  changes based on the currently-selected element in the hierarchical display  142 . Thus, pane  142  displays (for a process) interface resources associated with the process and variable assignments to the interface resources.  
         [0030]      FIG. 6  shows an example of a variable  170  selected from the hierarchical pane  142 . In pane  144 , a title is shown at  172  indicating that the modifiable options displayed in the right pane  144  are associated with the variable “coeffs”. For this particular variable, the word width may be modified using the up/down arrows shown at  174  or by typing in the desired value. The word width determines the number of bits in each memory word used to store the variable and allows the user to explore different memory architectures. Thus, using the hierarchical display and GUI, a user can modify a parameter of the variable defined in the source code  60 . Instead of updating the source code itself, the user modifies the parameter through the intermediate database  64 .  
         [0031]      FIG. 7  shows an example where the user selects an interface resource at  180 . In the right hand pane  144 , the title for the resource is shown at  182  and various tabs  184  are displayed organizing the modifiable parameters associated with the resource. For this particular resource, the resource type is modifiable, as shown by field  186 . By selecting arrow  188 , a drop-down window  190  is displayed showing the different resources that may be used. Only a subset of the resource types available from the interface resource library  68  are displayed. The resource types are automatically selected based on the types from the library  68  that are possible given the variable(s) associated with the resource. In this particular example, the resource may be mapped to a bank of registers or a dedicated memory element like the Virtex II BlockRAM or distributed RAM.  
         [0032]      FIGS. 8 and 9  show the drag-and-drop feature of the present invention to reassign variables to other resources. For example, if a user selects a variable as shown in  FIG. 8  at  200 , the user may drag it as indicated at  202  to a different resource shown at  204 . In  FIG. 8 , it should be noted that the resource  204  only has one variable associated with it. After the drag-and-drop operation, the result is shown in  FIG. 9  with the resource  204  now having two variables associated with it. The right-hand pane  144  is shown in  FIG. 9  as having a mapping tab at  206 . The mapping tab  206  shows the packing mode for each of the respective variables within the resource. For example, in this case, the variable “coeffs” is stored in memory (the resource) as shown at  208  whereas “fir_filter_regs” is stored at  210 .  
         [0033]      FIG. 10  shows that the system may be distributed over a client server network  230 . For example, a server computer  232  may have a database  234  associated therewith. One or more client computers shown at  236 ,  238  may communicate over a network  240 , such as the Internet.  
         [0034]      FIG. 11  shows a possible scenario for implementing the behavioral synthesis tool over the client-server network  230 . For example, in process block  250 , the source code description of the process is sent to the server from the client computer. The server may then parse and analyze the source code (process block  252 ) and generate a list of variables and interfaces associated with those variables (process block  254 ). The server computer may then send back to the client computer over the network  240  the information necessary to display the variables and interfaces in a hierarchical display (process block  256 ). In process block  258 , the user may modify the interface allocation through drag-and-drop operations or other GUI operations, as previously described, and send those changes back to the server computer  232 . The server computer then modifies the intermediate database as shown at  260  and generates the RTL code at  262 . The client then may receive the finalized RTL code from the server as indicated at  264 .  
         [0035]     The interface resource library  68  may be designed in a wide variety of ways. An example is shown below having two parts: first, an I/O Hardware component is generated in RTL code; second, an interface describes the signals for communicating with the component.  
         [0036]     Interface Library (Internal Format):  
                                   component ( “mgc_out_reg” ) {        parameter ( “width” ) { 1 to ; }        parameter ( “ph_clk” ) { 0 to 1; }        parameter ( “ph_en” ) { 0 to 1; }        parameter ( “ph_arst” ) { 0 to 1; }        parameter ( “ph_srst” ) { 0 to 1; }        interface {         pin ( “clk” ) { direction: in ; bit_width: 1; }         pin ( “en”  ) { direction: in ; bit_width: 1; value: ph_en; }         pin ( “arst” ) { direction: in ; bit_width: 1; value: 1-ph_arst; }         pin ( “srst” ) { direction: in ; bit_width: 1; value: 1-ph_srst; }         pin ( “ld”  ) { direction: in ; bit_width: 1; value: 0; }         pin ( “d”  ) { direction: in ; bit_width: width; input_reg; }         pin ( “lz”  ) { direction: out; bit_width: 1; }         pin ( “z”  ) { direction: out; bit_width: width; }        }        binding ( “write_port” ) {         pin_mapping {         pin_association ( “clk” ) { opr_pin: signal; name: “[CLOCK]” ;         phase: ph_clk; }         pin_association ( “en”  ) { opr_pin: signal; name: “[ENABLE]”;         phase: ph_en; }         pin_association ( “arst” ) { opr_pin: signal; name: “[A_RST]” ;         phase: ph_arst; }         pin_association ( “srst” ) { opr_pin: signal; name: “[S_RST]” ;         phase: ph_srst; }         pin_association ( “ld” ) { opr_pin: constant; value: 1; }         pin_association ( “d” ) { opr_pin: “D”; }         pin_association ( “lz” ) { opr_pin: signal; name: “[EXTERNAL]”; }         pin_association ( “z” ) { opr_pin: signal; name: “[EXTERNAL]”; }         }        }        binding ( “all” ) {         property_mapping {         SeqDelay := 0;         InitDelay := 1;         Delay := 0;         Area := 0;         }        }       }                  
 
         [0037]     Hardware Component in RTL (VHDL):  
                                                                                                                                                                                                                                                                                                   COMPONENT mgc_out_reg            GENERIC (                 width   : NATURAL;            ph_clk   : NATURAL RANGE 0 TO 1;            ph_en   : NATURAL RANGE 0 TO 1;            ph_arst   : NATURAL RANGE 0 TO 1;            ph_srst   : NATURAL RANGE 0 TO 1                 );            PORT (                 clk   : IN std_logic;            en   : IN std_logic;            arst   : IN std_logic;            srst   : IN std_logic;            ld   : IN std_logic;            d   : IN std_logic_vector(width−1 DOWNTO 0);            lz   : OUT std_logic;            z   : OUT std_logic_vector(width−1 DOWNTO 0)                 );           END COMPONENT;           LIBRARY ieee;           USE ieee.std_logic_1164.all;           ENTITY mgc_out_reg_pos IS            GENERIC (                 width   : NATURAL;            ph_en   : NATURAL RANGE 0 TO 1;            ph_arst   : NATURAL RANGE 0 TO 1;            ph_srst   : NATURAL RANGE 0 TO 1                 );            PORT (                 clk   : IN std_logic;            en   : IN std_logic;            arst   : IN std_logic;            srst   : IN std_logic;            ld   : IN std_logic;            d   : IN std_logic_vector(width−1 DOWNTO 0);            lz   : OUT std_logic;            z   : OUT std_logic_vector(width−1 DOWNTO 0)                 );           END mgc_out_reg_pos;           ARCHITECTURE beh OF mgc_out_reg_pos IS            FUNCTION active(lval: std_logic; ph: NATURAL            RANGE 0 TO 1) RETURN BOOLEAN IS            BEGIN            CASE lval IS            WHEN ‘0’ | ‘L’ =&gt;             RETURN ph = 0;            WHEN ‘1’ | ‘H’ =&gt;             RETURN ph = 1;            WHEN OTHERS =&gt;             RETURN true;            END CASE;            END active;           BEGIN            PROCESS ( clk, arst )            BEGIN            IF active(arst, ph_arst) THEN             lz &lt;= ‘0’;             z  &lt;= (others =&gt; ‘Z’);            ELSIF clk&#39;EVENT AND clk = ‘1’ THEN             IF active(srst, ph_srst) THEN             lz &lt;= ‘0’;             z  &lt;= (others =&gt; ‘Z’);             ELSIF active(en, ph_en) THEN             lz &lt;= ld;             z  &lt;= d;             END IF;            END IF;            END PROCESS;           END beh;           LIBRARY ieee;           USE ieee.std_logic_1164.all;           ENTITY mgc_out_reg_neg IS            GENERIC (                 width   : NATURAL;            ph_en   : NATURAL RANGE 0 TO 1;            ph_arst   : NATURAL RANGE 0 TO 1;            ph_srst   : NATURAL RANGE 0 TO 1                 );            PORT (                 clk   : IN std_logic;            en   : IN std_logic;            arst   : IN std_logic;            srst   : IN std_logic;            ld   : IN std_logic;            d   : IN std_logic_vector(width−1 DOWNTO 0);            lz   : OUT std_logic;            z   : OUT std_logic_vector(width−1 DOWNTO 0)                 );           END mgc_out_reg_neg;           ARCHITECTURE beh OF mgc_out_reg_neg IS            FUNCTION active(lval: std_logic; ph: NATURAL            RANGE 0 TO 1) RETURN BOOLEAN IS            BEGIN            CASE lval IS            WHEN ‘0’ | ‘L’ =&gt;             RETURN ph = 0;            WHEN ‘1’ | ‘H’ =&gt;             RETURN ph = 1;            WHEN OTHERS =&gt;             RETURN true;            END CASE;            END active;           BEGIN            PROCESS ( clk, arst )            BEGIN            IF active(arst, ph_arst) THEN             lz &lt;= ‘0’;             z  &lt;= (others =&gt; ‘Z’);            ELSIF clk&#39;EVENT AND clk = ‘0’ THEN             IF active(srst, ph_srst) THEN             lz &lt;= ‘0’;             z  &lt;= (others =&gt; ‘Z’);             ELSIF active(en, ph_en) THEN             lz &lt;= ld;             z  &lt;= d;             END IF;            END IF;            END PROCESS;           END beh;           LIBRARY ieee;           USE ieee.std_logic_1164.all;           ENTITY mgc_out_reg IS            GENERIC (                 width   : NATURAL;            ph_clk   : NATURAL RANGE 0 TO 1;            ph_en   : NATURAL RANGE 0 TO 1;            ph_arst   : NATURAL RANGE 0 TO 1;            ph_srst   : NATURAL RANGE 0 TO 1                 );            PORT (                 clk   : IN std_logic;            en   : IN std_logic;            arst   : IN std_logic;            srst   : IN std_logic;            ld   : IN std_logic;            d   : IN std_logic_vector(width−1 DOWNTO 0);            lz   : OUT std_logic;            z   : OUT std_logic_vector(width−1 DOWNTO 0)                 );           END mgc_out_reg;           ARCHITECTURE beh OF mgc_out_reg IS           BEGIN           GENPOS: IF ph_clk = 1 GENERATE            REGPOS: work.mgc_ioport_comps.mgc_out_reg_pos            generic map (             width =&gt; width,             ph_en =&gt; ph_en,             ph_arst =&gt; ph_arst,             ph_srst =&gt; ph_srst            )            port map (                  clk   =&gt; clk,             en   =&gt; en,             arst   =&gt; arst,             srst   =&gt; srst,             ld   =&gt; ld,             d   =&gt; d,             lz   =&gt; lz,             z   =&gt; z                 );           END GENERATE;            GENNEG: IF ph_clk = 0 GENERATE            REGNEG: work.mgc_ioport_comps.mgc_out_reg_neg             generic map (             width =&gt; width,             ph_en =&gt; ph_en,             ph_arst =&gt; ph_arst,             ph_srst =&gt; ph_srst             )             port map (                  clk   =&gt; clk,             en   =&gt; en,             arst   =&gt; arst,             srst   =&gt; srst,             ld   =&gt; ld,             d   =&gt; d,             lz   =&gt; lz,             z   =&gt; z                  );            END GENERATE;           END beh;                      
 
         [0038]     Having illustrated and described the principles of the illustrated embodiments, it will be apparent to those skilled in the art that the embodiments can be modified in arrangement and detail without departing from such principles.  
         [0039]     For example, one skilled in the art will recognize that a non-array pointer can be mapped to a memory interface and an array pointer can be mapped to a non-memory interface. Additionally, a pointer to an array can be mapped to a memory interface.  
         [0040]     Although the user input is described as coming from a command line, GUI, or file, those skilled in the art also understand that other user input techniques may be used. For example, the source code may be annotated through the use of pragmas or other means. For example, the source file could be annotated with a pragma such as:  
                                                   int main_design(           #pragma resource mgc_out_reg            int *bus_out           );                      
 
 This pragma is similar to a comment in the source code read by the tool and allows the user to use the same simple mechanism of resource selection. The pragma has no defined meaning in the language C, so has no effect on the C compiler. Therefore it is not required to change the input to model the actual behavior of the interface component, which would be impossible (or requires extensions) in C and other high-level languages. Adding pragmas to the source file does not change the behavior of the source, but is simply another way to access functionality of the tool. Pragma statements may also be used in higher-level languages other than C. 
 
         [0041]     Although the source code description is described without timing information, timing information may also be included in the source code in certain embodiments.  
         [0042]     In view of the many possible embodiments, it will be recognized that the illustrated embodiments include only examples and should not be taken as a limitation on the scope of the invention. Rather, the invention is defined by the following claims. I therefore claim as the invention all such embodiments that come within the scope of these claims.

Technology Category: g