Patent Document

BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a ferroelectric memory, and particularly to a ferroelectric memory having a circuit structure for selecting a defective memory cell, and a method of efficiently selecting a defective memory cell lying within the ferroelectric memory with low power consumption.  
           [0003]    This application is a counterpart of Japanese patent application, Serial Number 299875/2001, filed Sep. 28, 2001, the subject matter of which is incorporated herein by reference.  
           [0004]    2. Description of the Related Art  
           [0005]    A FeRAM (Ferroelectric Random Access Memory) has been known as a conventional ferroelectric memory. For instance, a 2-transistor 2-capacitor/one-bit type is known as the FeRAM. The 2-transistor 2-capacitor/one-bit type FeRAM is a FeRAM which stores one binary information by means of two memory cells, i.e., two transistors and two capacitors.  
           [0006]    As a reference that has disclosed the FeRAM, there is known, for example, “Low Power Consumption and High-Speed LSI Technology issued by Realize Co., Ltd, p.234-p.236”;  
           [0007]    A memory cell array of a general FeRAM is provided with memory cell groups arranged in matrix form. FIG. 12 shows a structure of such a memory cell array, corresponding to one sequence thereof. As shown in FIG. 12, a first memory cell M 0  and a second memory cell M 1  of a ferroelectric memory  2200  are respectively equipped with a first selection transistor T 0 , a second selection transistor T 1 , a first ferroelectric capacitor C 0  and a second ferroelectric capacitor C 1 . The first ferroelectric capacitor C 0  and the second ferroelectric capacitor C 1  respectively store binary data therein as polarization directions. In a 2-transistor 2-capacitor/1-bit type ferroelectric memory, binary or digitized data different in value are respectively stored in ferroelectric capacitors (e.g., the first ferroelectric capacitor C 0  and the second ferroelectric capacitor C 1 ) of one memory cell pair (e.g., a pair of the first memory cell M 0  and the second memory cell M 1 ).  
           [0008]    [0008]FIG. 13 is a timing chart for describing a data read operation of the ferroelectric memory  2200 . In FIG. 13, ‘L’ indicates a ground voltage, and ‘H’ indicates a source voltage Vcc. Further, ‘Vh’ indicates a voltage which is higher than the source voltage Vcc and is increased by about a threshold voltage Vt of each of the first and second selection transistors T 0  and T 1 .  
           [0009]    At a time t 1 , the voltage applied to a precharge control line PCHG is first rendered L to turn off a first precharge transistor PCT 0  and a second precharge transistor PCT 1 . Thus a first bit line BL 0  and a second bit line BL 1  are respectively brought to a floating state.  
           [0010]    Next, the voltages applied to a first word line WL 0  and a second word line WL 1  are respectively set to the Vh to turn on the first selection transistor T 0  and the second selection transistor T 1 .  
           [0011]    When the voltage applied to a first plate line PL 0  is brought to the H at a time t 3 , the voltage of the plate line PL 0  is applied to the first bit line BL 0  and the second bit line BL 1  through the first ferroelectric capacitor C 0 , the second ferroelectric capacitor C 1 , the first selection transistor T 0  and the second selection transistor T 1 , so that read voltages are developed in the first bit line BL 0  and the second bit line BL 1 . Since the first ferroelectric capacitor C 0  and the second ferroelectric capacitor C 1  are different in capacitance according to the direction of polarization, the read voltages developed in the first bit line BL 0  and the second bit line BL 1  are also different in value from each other according to the polarization direction.  
           [0012]    When the voltage applied to an activation signal line SAE is brought to the H at a time t 4 , a sense amplifier SA is activated. Thus the voltages of the first bit line BL 0  and the second bit line BL 1  are amplified.  
           [0013]    The voltage of the first plate line PL 0  is returned to the L at a time t 5 . Simultaneously, the voltage applied to a select line SEL is brought to the H. Consequently, a first bit line selection transistor SET 0  and a second bit line selection transistor SET 1  are turned on to output the read voltages of the first bit line BL 0  and the second bit line BL 1  onto a data bus  2210 .  
           [0014]    The voltage applied to the precharge control line PCHG is brought to the H at a time t 6 , and the voltages applied to the activation signal line SAE and the select line SEL are respectively brought to the L. Thus the first precharge transistor PCT 0  and the second precharge transistor PCT 1  are turned on, so that the first bit line BL 0  and the second bit line BL 1  are grounded and the sense amplifier SA does not output read data.  
           [0015]    Finally, the voltages applied to the first word line WL 0  and the second word line WL 1  are brought to the L at a time t 7  to turn off the first selection transistor T 0  and the second selection transistor T 1 .  
           [0016]    [0016]FIG. 14 is a conceptual diagram for describing transition of state a ferroelectric capacitor. The horizontal axis indicates a voltage V [volt], and the vertical axis indicates polarization Pr [μC/cm 2 ]. As shown in FIG. 14, the relationship between the voltage V and the polarization Pr plots or represents a hysteresis curve H. The inclination of the hysteresis curve H is equivalent to the capacitance [q/V] of the ferroelectric capacitor.  
           [0017]    In FIG. 14, the coordinates of a point A where the hysteresis curve H and a Pr axis (region of Pr&gt;0) intersect, is defined as (0, p0). A straight line S 1  is plotted which intersects, at an angle θ, a straight line formed by connecting the point A (0, p0) and a point B (Vcc, p0). The coordinates of a point C where the straight line S 1  and an upward curve of the hysteresis curve H intersect, is defined as (v1, p1). The angle θ is determined according to the capacitance of each bit line. The V coordinate v1 of the point C coincides with a terminal-to-terminal voltage of the ferroelectric capacitor, and the difference Vcc-v1 between the V coordinates of the points B and C coincides with a bit line voltage. Thus when Pr&gt;0 (when a stored value is given as ‘0’), a voltage V 0  outputted onto the corresponding bit line is represented as Vcc-V 1 .  
           [0018]    In FIG. 14, the coordinates of a point D where the hysteresis curve H and the Pr axis (region of Pr&lt;0) intersect, is defined as (0, p2). A straight line S 2  is plotted which intersects, at the angle θ, a straight line formed by connecting the point D (0, p2) and a point E (Vcc, p2). The coordinate of a point F where the straight line S 2  and an upward curve of the hysteresis curve H intersect, is defined as (v2, p3). Even in this case, the V coordinate v2 of the point F coincides with a terminal-to-terminal voltage of the ferroelectric capacitor, and the difference Vcc-v2 between the V coordinates of the points E and F coincides with a bit line voltage. Thus when Pr&lt;0 (when a stored value is given as ‘1’), a voltage V 1  outputted onto the corresponding bit line is represented as Vcc-v2.  
           [0019]    As is understood from FIG. 14, V 0 &lt;V 1 , and the difference therebetween V 1 −V 0  results in a read margin ΔV, V 0 , V 1  and ΔV greatly depend on the angle θ, i.e., bit line capacitance Cbl.  
           [0020]    [0020]FIG. 15 is one example of a graph showing the relationship between a ratio Cbl/Cs between the capacitance Cbl of each bit line and capacitance Cs of the ferroelectric capacitor, and the read margin ΔV. As is understood from FIG. 15, the read margin ΔV can be maximized by adjusting the ratio Cbl/Cs. Increasing the read margin ΔV makes it possible to improve the reliability of read data and enhance the yield of a FeRAM.  
           [0021]    The capacitances Cbl of the first bit line B 10  and the second bit line BL 1  are made up of junction capacitances of the first selection transistor T 0 , the second selection transistor T 1 , the first precharge transistor PCT 0  and the second precharge transistor PCT 1  connected to the first bit line BL 0  and the second bit line BL 1 , parasitic capacitances of the first bit line BL 0  and the second bit line BL 1 , etc. However, the majority thereof results from the junction capacitances of the first selection transistor T 0  and the second selection transistor T 1 . In the normal FeRAM, several hundreds of selection transistors are connected to one bit line, thereby increasing the capacitances Cbl of the first bit line BL 0  and the second bit line BL 1 .  
           [0022]    The ferroelectric memory using the ferroelectric capacitors as described above determines the stored states of the individual memory cells according to the voltages applied to the bit lines respectively connected thereto. It is therefore necessary to ensure the voltage margins upon data reading, i.e., optimize the capacitance of each bit line. The more the read margin increases, the more misreading decreases.  
           [0023]    Variations essentially occur in the characteristics of individual ferroelectric capacitors formed on a wafer as physical necessity of a semiconductor device. Thus a test on electric characteristics of each manufactured ferroelectric memory by means of a high voltage or the like, a durability test for activating it by an arbitrary number of times, and a thermal characteristic test for confirming its operation under the condition of a temperature higher than a normal working temperature are carried out or overloads such as a high temperature, a high voltage, etc. are applied thereto to thereby accelerate the degradation of the ferroelectric memory. In this condition, a test for allowing defects of memory cells that will be deteriorated with time in proportion as it is used, to become manifest or obvious immediately after its manufacture, thereby carrying out the selection of each memory cell is performed, followed by selection of an initial defective memory cell or a memory cell found out as defective due to its deterioration with time.  
           [0024]    However, problems arise in that, for example, any of the tests needs to have a very long test time, a severe load must be imposed on each memory cell to be selected, and an effective degradation accelerated test cannot be carried out due to a problem about a voltage or the like depending on the specifications of a device.  
           [0025]    The present invention has been made to solve the foregoing problems. The present invention aims to provide a ferroelectric memory provided with a circuit structure capable of selecting a defective memory cell in a very short period of time without applying an excessive load to a memory cell to be selected, and a method of efficiently selecting a defective memory cell lying within the ferroelectric memory with low power consumption.  
         SUMMARY OF THE INVENTION  
         [0026]    A summary of a typical one of the inventions disclosed in the present application will be described in brief as follows:  
           [0027]    A ferroelectric memory according to the present invention includes a plurality of memory cell pairs placed in matrix form and for respectively storing complementary digitized data therein as polarization states of ferroelectric capacitors, a plurality of bit line pairs respectively connected to the memory cell pairs lying in the same column, a plurality of word line pairs and a plurality of plate lines for respectively voltage-controlling the memory cell pairs in column units to thereby output voltages corresponding to the complementary digitized data to their corresponding bit line pairs, sense amplifiers for respectively amplifying voltages outputted to the bit line pairs, and switch transistors respectively provided for bit lines of the bit line pairs to electrically connect a predetermined number of memory cells to the respective bit line of the bit line pairs and electrically disconnect them therefrom upon selection of defective memory cells.  
           [0028]    According to the present invention, the capacitance of each bit line can be increased upon reading data into the bit line. Since a read margin for each defective memory cell becomes extremely small apparently with the increase in the capacitance of the bit line upon the data reading, a conventionally hard-to-detect defective memory cell that will be estimated to degrade with time according to its use, can be detected and selected. Since the ferroelectric memory has a simple structure wherein the switch transistors are simply added to a circuit, the above-described effect can be obtained under a reduction in the area of the memory. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]    While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:  
         [0030]    [0030]FIG. 1 is a circuit diagram illustrating a configuration of a ferroelectric memory according to a first embodiment;  
         [0031]    [0031]FIG. 2 is a timing chart showing the operation of the ferroelectric memory according to the first embodiment;  
         [0032]    [0032]FIG. 3 is a conceptual diagram depicting the manner of state shifts of the ferroelectric memory and read voltages thereof;  
         [0033]    [0033]FIG. 4 is a conceptual diagram showing the manner of state shifts of the ferroelectric memory and read voltages used in a selection mode;  
         [0034]    [0034]FIG. 5 is a timing chart showing another example of the operation of the ferroelectric memory according to the first embodiment;  
         [0035]    [0035]FIG. 6 is a circuit diagram illustrating a configuration of a ferroelectric memory according to a second embodiment;  
         [0036]    [0036]FIG. 7 is a timing chart depicting the operation of the ferroelectric memory according to the second embodiment;  
         [0037]    [0037]FIG. 8 is a timing chart showing a further example of the operation of the ferroelectric memory according to the second embodiment;  
         [0038]    [0038]FIG. 9 is a circuit diagram illustrating a configuration of a ferroelectric memory according to a third embodiment;  
         [0039]    [0039]FIG. 10 is a timing chart depicting the operation of the ferroelectric memory according to the third embodiment;  
         [0040]    [0040]FIG. 11 is a timing chart showing another example of the operation of the ferroelectric memory according to the third embodiment;  
         [0041]    [0041]FIG. 12 is a circuit diagram illustrating a configuration of a conventional ferroelectric memory;  
         [0042]    [0042]FIG. 13 is a timing chart showing the operation of the conventional ferroelectric memory;  
         [0043]    [0043]FIG. 14 is a conceptual diagram for describing state shifts of a ferroelectric memory capacitor; and  
         [0044]    [0044]FIG. 15 is a graph for describing the characteristic of a ferroelectric memory. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0045]    Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings. Incidentally, ones having the same functions are respectively identified by the same reference numerals in all the drawings for describing the embodiments of the present invention, and their repetitive description will be omitted.  
         [0046]    Incidentally, respective components of structure, waveforms, etc. shown in the drawings are merely schematically illustrated to such an extent that the present invention can be understood. It should be understood that numerical conditions to be described later are merely illustrative examples.  
         [0047]    &lt;First Preferred Embodiment&gt; 
         [0048]    A ferroelectric memory according to a first embodiment of the present invention will hereinafter be described with a 2-transistor 2-capacitor/one-bit type ferroelectric memory as an illustrative example.  
         [0049]    [0049]FIG. 1 is a circuit diagram typically showing a structure of a memory cell array, corresponding to one sequence of memory cell groups placed in matrix form, of the ferroelectric memory according to the present embodiment.  
         [0050]    As shown in FIG. 1, the memory cell array of the ferroelectric memory  100  has a first memory cell block  110  (hereinafter also called “first block”) and a second memory cell block  120  (hereinafter also called “second block”) provided as two, a first switch transistor SWT 0  and a second switch transistor SWT 1 .  
         [0051]    In the present embodiment, the number of a plurality of first memory cell MU 0 , second memory cell MU 1 , . . . of the first block  110 , and the number of a plurality of first memory cell ML 0 , second memory cell ML 1 , . . . of the second block  120  are regarded as identical to each other. Thus the numbers of memory cell transistors connected to first to fourth bit lines BLU 0 , BLU 1 , BLL 0  and BLL 1  become identical. Since most of the capacitances of the respective bit lines result from the junction capacitance of each memory cell transistor as described above, these bit lines become equal to one another in capacitance.  
         [0052]    Thus a description will be made of an example in which the numbers of the memory cells in the respective blocks are respectively set as two in FIG. 1.  
         [0053]    The first block  110  placed in each sequence includes a first memory cell MU 0  and a second memory cell MU 1  provided as a memory cell pair, a first precharge transistor PCTU 0 , a second precharge transistor PCTU 1 , a first bit line selection transistor SETU 0 , a second bit line selection transistor SETU 1 , a first sense amplifier SAU, and a first bit line (partial line) BLU 0  and a second bit line BLU 1  provided as a pair. On the other hand, the second block  120  placed in each sequence includes a first memory cell ML 0  and a second memory cell ML 1  provided as a memory cell pair, a third precharge transistor PCTL 0 , a fourth precharge transistor PCTL 1 , a third bit line selection transistor SETL 0 , a fourth bit line selection transistor SETL 1 , a second sense amplifier SAL, and a third bit-line (partial line) BLL 0  and a fourth bit line BLL 1  provided as a pair.  
         [0054]    A first word line WLU 0  and a second word line WLU 1  provided as a pair, a first plate line PLU 0 , a precharge control line PCHGU, a first select line SELU and a first activation signal line SAEU are provided as control lines commonly used in the first block  110  placed in each sequence. On the other hand, a first word line WLL 0  and a second word line WLL 1  provided as a pair, a first plate line PLL 0 , a second precharge control line PCHGL, a second select line SELL and a second activation signal line SAEL are provided as control lines common to the second block  120  placed in each sequence. In addition, a first switch control line SW 0  is provided as a control line for the first switch transistor SWT 0  of each sequence, and a second switch control line SW 1  is provided as a control line for the second switch transistor SWT 1  thereof.  
         [0055]    The first word line WLU 0 , the second word line WLU 1  and the first plate line PLU 0  of the first block  110  are arranged in parallel along a row direction of the memory cell array. The first word line WLU 0  and the second word line WLU 1  are disposed with two as one pair, and one plate line is placed between these two word lines. Similarly, the first word line WLL 0 , the second word line WLL 1  and the fist plate line PLL 0  of the second block  120  are arranged in parallel along the row direction of the memory cell array. The first word line WLL 0  and the second word line WLL 1  are disposed with two as one pair, and one plate line is placed between these two word lines.  
         [0056]    The first bit line BLU 0  and the second bit line BLU 1  of the first block  110  are placed in parallel with two as one pair along a column direction of the memory cell array. Similarly, the third bit line BLL 0  and the fourth bit line BLL 1  of the second block  120  are placed in parallel with two as one pair along the column direction of the memory cell array.  
         [0057]    The first memory cell MU 0  and the second memory cell MU 1  of the fist block  110  are respectively placed in positions where the first word line WLU 0  and second word line WLU 1 , and the first bit line BLU 0  and second bit line BLU 1  intersect. The first memory cell MU 0  and the second memory cell MU 1  are respectively provided with a first MOS transistor TU 0  and a second MOS transistor TU 1 , and a first ferroelectric capacitor CU 0  and a second ferroelectric capacitor CU 1  one by one. The first MOS transistor TU 0  and the second MOS transistor TU 1  respectively have gates connected to their corresponding word lines, drains connected to their corresponding bit lines, and sources connected to one ends of their corresponding ferroelectric capacitors CU 0  and CU 1 . The other ends of the ferroelectric capacitors CU 0  and CU 1  are connected to their corresponding plate lines. Similarly, the first memory cell ML 0  and the second memory cell ML 1  of the second block  120  are respectively placed in positions where the first word line WLL 0  and second word line WLL 1 , and the third bit line BLL 0  and fourth bit line BLL 1  intersect. The first memory cell ML 0  and the second memory cell ML 1  are respectively provided with a first MOS transistor TL 0  and a second MOS transistor TL 1 , and a first ferroelectric capacitor CL 0  and a second ferroelectric capacitor CL 1  one by one. The first MOS transistor TL 0  and the second MOS transistor TL 1  respectively have gates connected to their corresponding word lines, drains connected to their corresponding bit lines, and sources connected to one ends of their corresponding ferroelectric capacitors CL 0  and CL 1 . The other ends of the ferroelectric capacitors CL 0  and CL 1  are connected to their corresponding plate lines.  
         [0058]    The first precharge control line PCHGU, the first select line SELU and the first activation signal SAEU of the first block  110  are placed so as to intersect the first bit line BLU 0  and the second bit line BLU 1 . Similarly, the second precharge control line PCHGL, the second select line SELL and the second activation signal line SAEL of the second block  120  are disposed so as to intersect the third bit line BLL 0  and the fourth bit line BLL 1 .  
         [0059]    The first precharge transistor PCTU 0  and the second precharge transistor PCTU 1  of the first block  110  respectively have gates connected to the first precharge control line PCHGU, sources connected to their corresponding bit lines, and drains which are grounded. Similarly, the third precharge transistor PCTL 0  and the fourth precharge transistor PCTL 1  of the second block  120  respectively have gates connected to the second precharge control line PCHGL, sources connected to their corresponding bit lines, and drains which are grounded.  
         [0060]    The first bit line selection transistor SETU 0  and the second bit line selection transistor SETU 1  of the fist block  110  respectively have gates connected to the first select line SELU, sources connected to their corresponding bit lines, and drains connected to a data bus  130 . Similarly, the third bit line selection transistor SETL 0  and the fourth bit line selection transistor SETL 1  of the second block  120  respectively have gates connected to the second select line SELL, sources connected to their corresponding bit lines, and drains connected to a data bus  140 .  
         [0061]    When the first activation signal line SAEU is of an H level, the first sense amplifier SAU of the first block  110  is activated to amplify the difference in potential between the first bit line BLU 0  and the second bit line BLU 1 . Similarly, when the second activation signal line SAEL is H in level, the second sense amplifier SAL of the second block  120  is activated to amplify the difference in potential between the third bit line BLL 0  and the fourth bit line BLL 1 . In the present embodiment, the amplification of the potential difference by the first sense amplifier SAU-of the first block  110  is carried out where stored data are respectively read from the first memory cell MU 0  and the second memory cell MU 1  of the first block  110 . On the other hand, the amplification of the potential difference by the second sense amplifier SAL of the second block  120  is carried out where stored data are respectively read from the first memory cell ML 0  and the second memory cell ML 1  of the second block  120 . Incidentally, since the type of each of the first and second sense amplifiers SAU and SAL is not limited in the present embodiment, the description of its detailed internal configuration will be omitted.  
         [0062]    The first switch transistor SWT 0  has a gate connected to the first switch control line SW 0 , one of a source or a drain thereof, which is connected to its corresponding bit line of the first block  110 , and the other thereof connected to its corresponding bit line of the second block  120 . Similarly, the second switch transistor SWT 1  has a gate connected to the second switch control line SW 1 , one of a drain or a source, which is connected to its corresponding bit line of the fist block  110 , and the other thereof connected to its corresponding bit line of the second block  120 .  
         [0063]    A read operation example 1 in a selection mode for selecting a defective or fail memory cell in the ferroelectric memory  100  provided with the circuit structure shown in FIG. 1 will next be explained by using a timing chart shown in FIG. 2. A description will be made here of, as one example, a case in which the data stored in each of the first memory cell MU 0  and the second memory cell MU 1  is read to select whether each memory cell is defective. In FIG. 2, ‘L’ indicates a ground voltage, and ‘H’ indicates a source voltage Vcc, respectively. ‘Vh’ indicates a voltage which is higher than the source voltage Vcc and is increased by about a threshold voltage Vt of each of the first and second MOS transistors TU 0  and TU 1  of the memory cells.  
         [0064]    Let&#39;s first consider where “1” indicative of one of complementary digitized or binary data is written into a memory cell to be selected, i.e., the MU 1  herein. The other complementary data “0” is written into the MU 0 . Here, “1” indicates the side inverted in polarization at a ferroelectric capacitor upon reading.  
         [0065]    In an initial state (at a time t 0 ), the voltages applied to the first switch control line SW 0  and the second switch control line SW 1  are respectively of the L level.  
         [0066]    Upon reading the data stored in the first memory cell MU 0  and the second memory cell MU 1  of the memory cell pairs, the voltages applied to the first precharge control line PCHGU and the second precharge control line PCHGL are respectively brought to the L level at a time t 1 . Thus, since the first precharge transistor PCTU 0 , second precharge transistor PCTU 1 , third precharge transistor PCTL 0  and fourth precharge transistor PCTL 1  are turned off, the first through fourth bit lines BLU 0 , BLU 1 , BLL 0  and BLL 1  are respectively brought to a floating state.  
         [0067]    Next, the first word line WLU 0  and the second word line WLU 1  are respectively brought to the Vh level at a time t 2 . Thus the first MOS transistor TU 0  and the second MOS transistor TU 1  of the first memory cell MU 0  and the second memory cell MU 1  are turned on so that one terminals of the first ferroelectric capacitor CU 0  and the second ferroelectric capacitor CU 1  are respectively rendered conductive to the first bit line BLU 0  and the second bit line BLU 1 . Further, when the second switch control line SW 1  is brought to the H level, the second bit line BLU 1  and the fourth bit line BLL 1  are electrically connected to each other. The reason why the first word line WLU 0  and the second word line WLU 1  are respectively brought to the Vh level other than the H level, is that the output voltages (drain voltages) of the first MOS transistor TU 0  and second MOS transistor TU 1  are reduced by Vt as compared with their input voltages (gate voltages).  
         [0068]    Subsequently, the first plate line PLU 0  is brought to the H level at a time t 3 . Consequently, the voltage applied to the plate line PLU 0  is applied to the first bit line BLU 0  and the second bit line BLU 1  through the first ferroelectric capacitor CUP, the second ferroelectric capacitor CU 1 , and the first MOS transistor TUO and the second MOS transistor TU 1 . Therefore, a read voltage (V 0  or V 1 ) corresponding to the direction of polarization is developed in both bit lines, i.e., the first bit line BLU 0  and the second bit line BLU 1  electrically connected to the fourth bit line BLL 1 . Since the second switch transistor SWT 1  is turned on as described above, the second bit line BLU 1  is connected to the second bit line BLU 1  and the fourth bit line BLL 1 . Accordingly, the parasitic capacitances of the second bit line BLU 1  and the fourth bit line BLL 1  sufficiently increase according to the plurality of selection transistors connected to the second bit line BLU 1  and the fourth bit line BLL 1 .  
         [0069]    At a time t 5 , the first activation signal line SAEU is brought to the H level to activate the first sense amplifier SAU. Thus the voltages applied to the first bit line BLU 1 , the second bit line BLU 1  and the fourth bit line BLL 1  are amplified.  
         [0070]    Subsequently, the first select line SELU is brought to the H level at a time t 6 . Consequently, the first bit line selection transistor SETU 0  and the second bit line selection transistor SETU 1  are turned on so that the voltages of the first bit line BLU 0 , the second bit line BLU 1  and the fourth bit line BLL 1  are outputted to the data bus  130 .  
         [0071]    Next, the voltage applied to the fist plate line PLU 0  is returned to the L level at a time t 7 .  
         [0072]    At a time t 8 , the voltages applied to the first precharge control line PCHGU and the second precharge control line PCHGL are respectively returned to the H level, and the voltages applied to the first activation signal line SAEU and the first select line SELU are respectively brought to the L level. Thus the first precharge transistor PCTU 0 , the second precharge transistor PCTU 1 , the third precharge transistor PCTL 0  and the fourth precharge transistor PCTL 1  are turned on, so that the first bit line BLU 0 , the second bit line BLU 1 , the third bit line BLL 0  and the fourth bit line BLL 1  are grounded and no read data are outputted. At the time t 8  as well, the second switch control line SWT 1  is returned to the L level. Thus, since the second switch transistor SWT 1  is turned off, the second bit line BLU 1  and the fourth bit line BLL 1  are electrically disconnected from each other.  
         [0073]    At a time t 9 , the voltages on the first word line WLU 0  and the second word line WLU 1  are respectively brought to the L level to turn off the first MOS transistor TU 0  and the second MOS transistor TU 1 . Thus the read operation is completed.  
         [0074]    According to the configuration of the present invention, the above-described read voltages are detected to select the corresponding defective memory cell.  
         [0075]    Incidentally, the operation of reading stored data from other memory cells (no shown) of the first block  110  is substantially identical to the operation of reading the data from the above-described memory cell MU 1 . Even if each block includes three or more memory cells, the operation of reading data from each of the memory cells is carried out in the same manner as described above.  
         [0076]    On the other hand, when it is desired to read stored data from either one of the first memory cell ML 0  and the second memory cell ML 1  of the second block  120 , the second switch transistor SWT 1  is turned on (see t 2  in FIG. 2) and thereafter the second sense amplifier SAL of the second block  120  is activated (this being equivalent to the time t 5 ) to amplify the read data. The post-amplification data is outputted to the data bus  140  through the third bit line selection transistor SETL 0  and the fourth bit line selection, transistor SETL 1  (this being equivalent to the time t 6 ). Namely, the sense amplifier (sense amplifier connected to each memory cell to be read after the second switch transistor SWT 1  has been turned on) corresponding to the memory cell to be read is used to amplify the read data.  
         [0077]    When it is desired to use the ferroelectric memory according to the present embodiment in a normal mode, the first switch control line SW 0  and the second switch control line SW 1  are always kept in an L state, whereby the writing or reading of data can be carried out as usual.  
         [0078]    Thus the ferroelectric memory  100  according to the present embodiment has a circuit structure capable of selecting a defective memory cell that will be degraded with time according to its use. When it is desired to read stored data from a transistor of a memory cell to be selected and select it, for instance, the first switch transistor SWT 0  and the second switch transistor SWT 1  are selectively and exclusively turned on to electrically connect the first bit line BLU 0  and the third bit line BLL 0 , and the second bit line BLU 1  and the fourth bit line BLL 1  respectively. It is therefore possible to sufficiently increase the capacitance of each bit line upon reading (see the time t 3 ). Thus a reading margin for each defective memory cell that will be degraded with time according to the use thereof, can be extremely reduced apparently. Therefore, the conventional difficult selection of each defective memory cell that will be degraded with time according to the use thereof, can easily be carried out in a short time in accordance with a degradation accelerated test or the like without an excessive load being imposed on each memory cell to be selected.  
         [0079]    A logical background for selecting each defective memory cell that will be degraded with time according to its use, will now be described with reference to FIGS.  3  and  4  according to the configuration of the first embodiment.  
         [0080]    [0080]FIGS. 3 and 4 are respectively graphs showing hysteresis characteristics (GCf 0  and GCf 1 ) of a ferroelectric capacitor having satisfactory characteristics, hysteresis characteristics (NGCf 0  and NGCf 1 ) of a ferroelectric capacitor degraded in characteristic due to its defect or the like, and capacitance straight lines (Cbl and CblS) of bit lines. The horizontal axis indicates a voltage V [Volt], and the vertical axis indicates polarization Pr [μC/cm 2 ], respectively. As evident from both drawings, the difference between the graphs due to the characteristic degradation of the ferroelectric capacitor, i.e., the difference between read voltages is hard to appear on each bit line on the polarization “0” side in general. This is apt to appear on each bit line on the polarization “1” side.  
         [0081]    [0081]FIG. 3 is a graph showing the manner of read voltages in a normal mode of the ferroelectric memory described in the first embodiment of the present invention. As is apparent from this graph, the difference between a read margin ΔV for a satisfactory ferroelectric capacitor and a read margin ΔV′ for a ferroelectric capacitor including a defect is extremely slight in the normal mode. Thus, since the read margin ΔV′ for the ferroelectric capacitor that has potential or underlying defects and will be degraded in characteristic with time according to its use, exceeds a voltage margin of the corresponding sense amplifier, which is indicated by ΔSA, the sense amplifier is activated. Thus when the ferroelectric capacitor is regarded as the ferroelectric memory, it seems to be normally activated while containing underlying defects. However, there is a very high possibility that the deterioration of the ferroelectric capacitor will become manifest with the repetition of write and read operations, and some failure in operation will occur.  
         [0082]    [0082]FIG. 4 is a graph showing the manner of read voltages in a selection mode of the ferroelectric memory according to the first embodiment of the present invention. A description thereof will be made while referring to FIG. 1. By turning on the second switch transistor SWT 1  upon data reading, the second bit line (partial line) BLU 1  and fourth bit line BLL 1  on the polarization “1” side are connected to increase the capacitance, i.e., make the inclination of the capacitance straight line CblS steep, whereby the difference between a voltage margin ΔVS of a satisfactory ferroelectric capacitor and a voltage margin ΔVS′ of a ferroelectric capacitor which has underlying defects and whose degradation is accelerated with time according to its use, can be rendered large. In this case in particular, ΔVS′ becomes smaller than the voltage margin ΔSA of the sense amplifier. Namely, since ΔVS′&lt;ΔSA, the sense amplifier does not operate. Thus each ferroelectric memory cell that will be made defective in the future, which could not be selected as an initial failure since its defect was not made evident, can be selected with, for example, the operation or non-operation of the corresponding sense amplifier as an index. However, the construction of the present invention is not limited to it. For instance, another means for carrying out the direct detection of a voltage of ΔVS′, etc. is suitably selected and a defective ferroelectric memory cell may be selected.  
         [0083]    Another operation example 2 of the ferroelectric memory according to the first embodiment will be explained with reference to FIG. 5. FIG. 5 is a timing chart for describing the operation example 2 of the ferroelectric memory according to the first embodiment. The operation to be described by the operation example  2  is different from the operation described according to the timing chart shown in FIG. 2, i.e., the operation example 1 of the first embodiment in that the operation for turning off the second switch transistor SWT 1  at a time t 4  in FIG. 5 to thereby electrically isolate the second bit line BLU 1  and the fourth bit line BLL 1  electrically connected to each other is added. Thus the capacitance at the amplification of data by the corresponding sense amplifier (see a time t 5 ) can be set to one-half the capacitance at data reading. Accordingly, the first sense amplifier SAU can be reduced in power consumption.  
         [0084]    In the present embodiment as described above, the number of the memory cells in the first block  110  and the number of the memory cells in the second block  120  are rendered identical and set to 2 respectively. However, the numbers of the memory cells in these blocks  110  and  120  may not be made identical and may be three or more. If the ratio between the number of the memory cells in the first block  110  and the number of the memory cells in the second block  120  is set as 1:2, for example, then the ratio between the capacitance of each of the bit lines BLU 0  and BLU 1  of the first block  110  and that of each of the bit lines BLL 0  and BLL 1  of the second block  120  becomes approximately 1:2 (most of the capacitances of the bit lines correspond to the junction capacitance of each memory cell transistor as described above). Thus power consumed or used up where the data are read from the first memory cell MU 0  and the second memory cell MU 1  lying within the first block  110 , reaches about one-third the conventional power consumption. Further, power consumed where the data are read from the first memory cell ML 0  and the second memory cell ML 1  lying within the second block  120 , is brought to about two-third the conventional power consumption. Accordingly, data high in read frequency are respectively stored in the first memory cell MU 0  and the second memory cell MU 1  in the first block  110 , and data low in read frequency are respectively stored in the fist memory cell ML 0  and the second memory cell ML 1  in the second block  120 . Consequently, the power consumption can further be reduced as compared with the case where the numbers of the memory cells in the blocks  110  and  120  are identical. When a program storage area and a data storage area are provided within one FeRAM, for example, power consumption is reduced if the area in which the number of memory cells per bit line is low, is set as the program storage area and the area in which the number thereof is great, is set as the data storage area. This is because the program storage area generally becomes high in access frequency.  
         [0085]    Second Preferred Embodiment  
         [0086]    A ferroelectric memory according to a second embodiment of the present invention will hereinafter be described with a 2-transistor 2-capacitor/one-bit type ferroelectric memory as an illustrative example.  
         [0087]    The present embodiment is different from the first embodiment in that sense amplifiers, etc. of respective blocks are used in common.  
         [0088]    [0088]FIG. 6 is a circuit diagram showing a structure equivalent to one sequence, of a memory cell array of the ferroelectric memory according to the present embodiment.  
         [0089]    As shown in FIG. 6, a memory cell array of a ferroelectric memory  300  comprises two first and second memory cell blocks  310  and  320 , a first precharge transistor PCT 0 , a second precharge transistor PCT 1 , a sense amplifier SA, a first bit line selection transistor SET 0 , a second bit line selection transistor SET 1 , a first global bit line GBL 0 , and a second global bit line GBL 1 , which are provided for each sequence. The first memory cell block  310  includes a first memory cell MU 0  and a second memory cell MU 1  and is further provided with a first switch transistor SWUT 0 , a second switch transistor SWUT 1 , a first bit line (partial line) BLU 0 , and a second bit line BLU 1 . Similarly, the second memory cell block  320  includes a first memory cell ML 0  and a second memory cell ML 1  and is provided with a third switch transistor SWLT 0 , a fourth switch transistor SWLT 1 , a third bit line (partial line) BLL 0 , and a fourth bit line BLL 1 .  
         [0090]    In the present embodiment, the numbers of the first memory cell MU 0 , second memory cell MU 1 , . . . in the first memory cell block  310 , and the numbers of the first memory cell ML 0 , second memory cell ML 1 , . . . in the second memory cell block  320  are considered as identical in the present embodiment. Thus these bit lines become identical in capacitance.  
         [0091]    A first word line WLU 0 , a second word line WLU 1 , a first plate line PLU 0 , a first switch control line SWU 0  and a second switch control line SWU 1  are provided as control lines common to the first memory cell block  310  placed in each sequence. Similarly, a first word line WLL 0 , a second word line WLL 1 , a first plate line PLL 0 , a third switch control line SWL 0  and a fourth switch control line SWL 1  are provided as control lines common to the second memory cell block  320  placed in each sequence. A precharge control line PCHG, an activation signal line SAE and a select line SEL are provided as control lines common to the first precharge transistor PCT 0 , the second precharge transistor PCT 1 , the sense amplifier SA, the first bit line selection transistor SET 0 , and the second bit line selection transistor SET 1  placed in each sequence.  
         [0092]    The first word line WLU 0 , the second word line WLU 1  and the first plate line PLU 0  common to each first memory cell block  310  are arranged in parallel along a row direction of the memory cell array. The first word line WLU 0  and the second word line WLU 1  are disposed with two as one pair, and one plate line is placed between these two word lines. Similarly, the first word line WLL 0 , the second word line WLL 1  and the fist plate line PLL 0  common to each second memory cell block  320  are also arranged in parallel along the row direction of the memory cell array. The first word line WLL 0  and the second word line WLL 1  are disposed with two as one pair, and one plate line is placed between these two word lines.  
         [0093]    The first bit line BLU 0  and the second bit line BLU 1  of the first memory cell block  310  are placed in parallel with two as one pair along a column direction of the memory cell array. Similarly, the third bit line BLL 0  and the fourth bit line BLL 1  of the second memory cell block  320  are also placed in parallel with two as one pair along the column direction of the memory cell array.  
         [0094]    The first global bit line GBL 0  and the second global bit line GBL 1  are respectively connected to the first bit line BLU 0  and the second bit line BLU 1  of the first memory cell block  310  through the first switch transistor SWUT 0  and the second switch transistor SWUT 1 . Further, they are respectively connected to the third bit line BLL 0  and the fourth bit line BLL 1  of the second memory cell block  320  through the third switch transistor SWLT 0  and the fourth switch transistor SWLT 1 . The gates of the first switch transistor SWUT 0  and the second switch transistor SWUT 1  are respectively connected to the first switch control line SWUO and the second switch control line SWU 1 . The gates of the third switch transistor SWLT 0  and the fourth switch transistor SWLT 1  are respectively connected to the third switch control line SWL 0  and the fourth switch control line SWL 1 .  
         [0095]    The first memory cell MU 0  and the second memory cell MU 1  of the first memory cell block  310  are respectively placed in positions where the first word line WLU 0  and the second word line WLU 1 , and the first bit line BLU 0  and the second bit line BLU 1  intersect respectively. The first memory cell MU 0  and the second memory cell MU 1  are respectively provided with a first MOS transistor TU 0 , a second MOS transistor TU 1 , a first ferroelectric capacitor CU 0 , and a second ferroelectric capacitor CU 1  one by one. The first MOS transistor TU 0  and the second MOS transistor TU 1  respectively have gates connected to their corresponding word lines, drains connected to their corresponding bit lines, and sources connected to one ends of their corresponding first and second ferroelectric capacitors CU 0  and CU 1 . The other ends of the first and second ferroelectric capacitors CU 0  and CU 1  are connected to their corresponding plate lines. Similarly, the first memory cell ML 0  and the second memory cell ML 1  of the second memory cell block  320  are respectively placed in positions where the first word line WLL 0  and second word line WLL 1 , and the third bit line BLL 0  and fourth bit line BLL 1  intersect respectively. The first memory cell ML 0  and the second memory cell ML 1  are respectively provided with a first MOS transistor TL 0  and a second MOS transistor TL 1 , and a first ferroelectric capacitor CL 0  and a second ferroelectric capacitor CL 1  one by one. The first MOS transistor TL 0  and the second MOS transistor TL 1  respectively have gates connected to their corresponding word lines, drains connected to their corresponding bit lines, and sources connected to one ends of their corresponding first and second ferroelectric capacitors CL 0  and CL 1 . The other ends of the first and second ferroelectric capacitors CL 0  and CL 1  are connected to their corresponding plate lines.  
         [0096]    The first precharge transistor PCT 0  and the second precharge transistor PCT 1  respectively have gates connected to the precharge control line PCHG, sources connected to their corresponding global bit lines, and drains which are grounded.  
         [0097]    The first bit line selection transistor SET 0  and the second bit line selection transistor SET 1  respectively have gates connected to the select line SEL, sources connected to their corresponding global bit lines, and drains connected to a data bus  330 .  
         [0098]    When a signal SAE is high in level, the sense amplifier SA is activated to amplify voltages on the global bit lines GBL 0  and GBL 1 . Incidentally, since the type of the sense amplifier SA is not limited in the present embodiment, the description of a detailed internal configuration will be omitted.  
         [0099]    A read operation example 1 in a selection mode for selecting a defective or fail memory cell in the ferroelectric memory  300  provided with the circuit structure shown in FIG. 6 will next be explained by using a timing chart shown in FIG. 7. A description will be made here of, as one example, a case in which the data stored in each of the first memory cell MU 0  and the second memory cell MU 1  is read to select whether each memory cell is defective. In FIG. 7, ‘L’ indicates a ground voltage, and ‘H’ indicates a source voltage Vcc, respectively. ‘Vh’ indicates a voltage which is lower than the source voltage Vcc and is increased by about a threshold voltage Vt of each of the first and second MOS transistors TU 0  and TU 1  of the memory cells.  
         [0100]    Let&#39;s consider where “1” indicative of one of complementary digitized or binary data is written into a memory cell to be selected, i.e., the MU 1  herein. “0” indicative of the other complementary data is written into the MU 0 . Here, “1” indicates the side inverted in polarization at a ferroelectric capacitor upon reading.  
         [0101]    In an initial state (at a time t 0 ), the voltages applied to the first switch control line SWU 0 , the second switch control line SWU 1 , the third switch control line SWL 0  and the fourth switch control line SWL 1  are respectively given as the Vh level. Thus the first bit line BLU 0  and the third bit line BLL 0 , and the second bit line BLU 1  and the fourth bit line BLL 1  are respectively connected to the first precharge transistor PCT 0  and the second precharge transistor PCT 1  by means of the first switch transistor SWUT 0 , the second switch transistor SWUT 1 , the third switch transistor SWLT 0  and the fourth switch transistor SWLT 1 , where they are precharged.  
         [0102]    Upon reading the data stored in the memory cells MU 0  and MU 1  to be selected, the voltages applied to the precharge control line PCHG and the third switch control line SWL 0  are respectively brought to the L level at a time t 1 . Thus, since the first precharge transistor PCT 0  and the second precharge transistor PCT 1  are turned off, the first global bit line GBL 0  and the second global bit line GBL 1  are respectively brought to a floating state. Further, since the third switch transistor SWLT 0  is turned off, the third bit line BLL 0  is separated from the second global bit line GBL 1 .  
         [0103]    Next, the first word line WLU 0  and the second word line WLU 1  are respectively brought to the Vh level at a time t 2 . Thus the first MOS transistor TU 0  and the second MOS transistor TU 1  of the first memory cell MU 0  and the second memory cell MU 1  are turned on so that one terminals of the first ferroelectric capacitor CU 0  and the second ferroelectric capacitor CU 1  are respectively rendered conductive to the first bit line BLU 0  and the second bit line BLU 1 . The reason why the first word line WLU 0  and the second word line WLU 1  are respectively brought to the Vh level other than the H level, is that the output voltages (drain voltages) of the first MOS transistor TU 0  and second MOS transistor TU 1  are reduced by Vt as compared with their input voltages (gate voltages).  
         [0104]    Subsequently, the first plate line PLU 0  is brought to the H level at a time t 3 . Consequently, the voltage applied to the first plate line PLU 0  is applied to the first bit line BLU 0  and the second bit line BLU 1  through the first ferroelectric capacitor CU 0 , the second ferroelectric capacitor CU 1 , and the first MOS transistor TU 0  and the second MOS transistor TU 1 . Therefore, a read voltage of V 0  is developed in the first bit line BLU 0 , and a read voltage of VS 1  is developed in the second bit line BLU 1 . Since the second bit line BLU 1  and the fourth bit-line BLL 1  remain connected to the second global bit line GBL 1  as described above, the second global bit line GBL 1  becomes sufficiently large in parasitic capacitance. Therefore, a read margin ΔV=VS 1 −V 0  also becomes great sufficiently.  
         [0105]    At a time t 5 , the activation signal line SAE is brought to the H level to activate the sense amplifier SA. Thus the voltages applied to the first global bit line GBL 0  and the second global bit line GBL 1  are amplified.  
         [0106]    Subsequently, the select line SEL is brought to the H level at a time t 6 . Consequently, the first bit line selection transistor SET 0  and the second bit line selection transistor SET 1  are turned on so that the voltages of the first global bit line GBL 0  and the second global bit line GBL 1  are outputted to the data bus  330 .  
         [0107]    Next, the voltage on the fist plate line PLU 0  is returned to the L level at a time t 7 .  
         [0108]    At a time t 8 , the voltage applied to the precharge control line PCHG is returned to the H level, and the voltages applied to the activation signal line SAE and the select line SEL are respectively brought to the L level. Consequently, the first precharge transistor PCT 0  and the second precharge transistor PCT 1  are turned on so that the first global bit line CBL 0 , the second global bit line GBL 1  are grounded and no read data are outputted from the sense amplifier SA. At the time t 8  as well, the third switch control line SWL 0  is returned to the Vh level. Thus, since the third switch transistor SWLT 0  is turned on, the third bit line BLL 0  and the fourth bit line BLL 1  are connected to the first global bit line GBL 0 .  
         [0109]    At a time t 9 , the voltages on the first word line WLU 0  and the second word line WLU 1  are respectively brought to the L level to turn off the first MOS transistor TU 0  and the second MOS transistor TU 1 . Thus the read operation is completed.  
         [0110]    By detecting such read potentials, the corresponding defective memory cell is selected.  
         [0111]    Incidentally, the operation of reading stored data from other memory cells (no shown) of the first memory cell block  310  is also substantially identical to the operation of reading the data from the above-described memory cell MU 1 . Even if each block includes three or more memory cells, the operation of reading data from each of the memory cells is carried out in the same manner as described above.  
         [0112]    On the other hand, when it is desired to read stored data from the first memory cell ML 0  and the second memory cell ML 1  of the second memory cell block  320 , the first switch transistor SWUT 0  and the second switch transistor SWUT 1  is turned off after the charging of the first global bit line GBL 0  and the second global bit line GBL 1 . Namely, the first bit line BLU 0  and second bit line BLU 1  of the first memory cell block  310  are respectively disconnected from the first global bit line GBL 0  and the second global bit line GBL 1  upon amplification of the read data.  
         [0113]    When it is desired to use the ferroelectric memory according to the present embodiment in a normal mode, only the switch transistors (SWUT 0  and SWUT 1  or SWLT 0  and SWLT 1 ) on the accessing side are respectively held in the ‘H’ state, thereby making it possible to perform the writing or reading of data as usual.  
         [0114]    Thus each ferroelectric memory cell that will be made defective with time according to its use, which could not be selected as an initial failure since its defect was not made evident so far, can be selected with, for example, the operation or non-operation of the corresponding sense amplifier as an index. However, the construction of the present invention is not limited to it. For instance, another means for carrying out the direct detection of voltages of V 0  and VS 1  at the time t 3  of the timing chart shown in FIG. 7, etc. is suitably selected and thereby a defective ferroelectric memory cell may be selected.  
         [0115]    According to the ferroelectric memory according to the present embodiment in addition to the above, since the sense amplifier and the like are used in common, the whole area of integrated circuit can be reduced as compared with the first embodiment referred to above.  
         [0116]    Another operation example 2 of the ferroelectric memory according to the second embodiment will be explained with reference to FIG. 8. FIG. 8 is a timing chart showing the operation example 2 of the ferroelectric memory according to the second embodiment. The operation to be described by the operation example 2 is different from the operation described according to the timing chart shown in FIG. 7 in that the operation of turning off the fourth switch transistor SWLT 1  at a time t 4  in FIG. 8 to thereby isolate the second bit line BLU 1  and the fourth bit line BLL 1  connected to each other is added. Thus the capacitance of each bit line at the amplification of data by the corresponding sense amplifier (see a time t 5 ) can be set to one-half the capacitance at data reading. Accordingly, the sense amplifier SA can be reduced in power consumption.  
         [0117]    In the present embodiment as described above, the number of the memory cells in the first memory cell block  310  and the number of the second memory cell block  320  are rendered identical. However, the numbers of the memory cells in these blocks  310  and  320  may not be made identical. Data low in read frequency are respectively stored in the block large in the number of the memory cells, and data high in read frequency are respectively stored in the block small in the number of the memory cells, whereby power consumption can be further reduced.  
         [0118]    Third Preferred Embodiment  
         [0119]    A ferroelectric memory according to a third embodiment of the present invention will hereinafter be described with a 2-transistor 2-capacitor/one-bit type ferroelectric memory as an illustrative example.  
         [0120]    The present embodiment is different from the second embodiment in that a memory cell array corresponding to one sequence is divided into three or more memory cell blocks, for example.  
         [0121]    [0121]FIG. 9 is a circuit diagram showing a structure equivalent to one sequence of the memory cell array of the ferroelectric memory according to the present embodiment.  
         [0122]    As shown in FIG. 9, a memory cell array of a ferroelectric memory  700  comprises three or more first, second and third memory cell blocks  710 -A,  710 -B and  710 -C, a first precharge transistor PCT 0 , a second precharge transistor PCT 1 , a sense amplifier SA, a first bit line selection transistor SET 0 , a second bit line selection transistor SET 1 , a first global bit line GBL 0 , and a second global bit line GBL 1 , which are provided for each sequence. The first memory cell block  710 -A includes a first memory cell MA 0 , a second memory cell MA 1 , a first switch transistor SWAT 0 , a second switch transistor SWAT 1 , a first bit line (partial line) BLA 0 , and a second bit line BLA 1 . As control lines common to the first memory cell block  710 -A placed in each sequence, there are provided a first word line WLA 0 , a second word line WLA 1 , a first plate line PLA 0 , a first switch control line SWA 0  and a second switch control line SWA 1 . The blocks subsequent to the second block are similar to the above. In addition, a precharge control line PCHG, an activation signal line SAE and a select signal SEL are provided as control lines common to the first precharge transistor PCT 0 , the second precharge transistor PCT 1 , the sense amplifier SA, the first bit line selection transistor SET 0 , and the second bit line selection transistor SET 1  provided in each sequence.  
         [0123]    In the present embodiment, the numbers of memory cells in the respective memory cell blocks  710 -A,  710 -B and  710 -C are regarded as identical. Thus the bit lines of these blocks are substantially identical in capacitance.  
         [0124]    The first word line WLA 0 , the second word line WLA 1  and the first plate line PLA 0  common to each first memory cell block  710 -A are arranged in parallel along a row direction of the memory cell array. The first word line WLA 0  and the second word line WLA 1  are disposed with two as one pair, and one plate line is placed between these two word lines. The word lines and the plate lines of other memory cell blocks  710 -B and  710 -C are similar to the above.  
         [0125]    The first bit line BLA 0  and the second bit line BLA 1  of the first memory cell block  710 -A are placed in parallel with two as one pair along a column direction of the memory cell array. The bit lines in other memory cell blocks  710 -B and  710 -C are similar to the above. A parasitic capacitance of each bit line is determined according to a junction capacitance of each transistor or wiring capacitance. In the present embodiment, the parasitic capacitances of these bit lines are set in such a manner that the sum of the capacitances of the same bit lines reaches such a value as to obtain a sufficient read margin ΔV (see FIG. 15).  
         [0126]    The first global bit line GBL 0  and the second global bit line GBL 1  are respectively connected to the first bit line BLA 0  and the second bit line BLA 1  of the first memory cell block  710 -A through the first switch transistor SWAT 0  and the second switch transistor SWAT 1 . Here, the first global bit line GBL 0  and the second global bit line GBL 1  are wired so as to overlap with a layer different from that for the first bit line BLA 0  and the second bit line BLA 1 . The gate of the first switch transistor SWAT 0  is connected to the first switch control line SWA 0 , and the gate of the second switch transistor SWAT 1  is connected to the second switch control line SWA 1 . Other memory cell blocks  720 -B and  720 -C are similar to the above.  
         [0127]    The first memory cell MA 0  and the second memory cell MA 1  of the first memory cell block  710 -A are respectively placed in positions where the first word line WLA 0  and the second word line WLA 1 , and the first bit line BLA 0  and the second bit line BLA 1  intersect respectively. The first memory cell MA 0  and the second memory cell MA 1  are respectively provided with a first MOS transistor TA 0 , a second MOS transistor TA 1 , a first ferroelectric capacitor CA 0 , and a second ferroelectric capacitor CA 1  one by one. The first MOS transistor TA 0  and the second MOS transistor TA 1  respectively have gates connected to their corresponding word lines, drains connected to their corresponding bit lines, and sources connected to one ends of their corresponding first and second ferroelectric capacitors CA 0  and CA 1 . The other ends of the first and second ferroelectric capacitors CA 0  and CA 1  are connected to their corresponding plate lines. The respective memory cells of other memory cell blocks  710 -B and  710 -C are similar to the above.  
         [0128]    The first precharge transistor PCT 0  and the second precharge transistor PCT 1  respectively have gates connected to the precharge control line PCHG, sources. connected to their corresponding bit lines, and drains which are grounded.  
         [0129]    The first bit line selection transistor SET 0  and the second bit line selection transistor SET 1  respectively have gates connected to the select line SEL, sources connected to their corresponding bit lines, and drains connected to a data bus  720 .  
         [0130]    When the activation signal line SAE is H in level, the sense amplifier SA is activated to amplify and output potentials on the first global bit line GBL 0  and the second global bit line GBL 1 . Incidentally, since the type of the sense amplifier SA is not limited in the present embodiment, the description of a detailed internal configuration will be omitted.  
         [0131]    A read operation example 1 in a selection mode for selecting a defective memory cell in the ferroelectric memory  700  provided with the circuit structure shown in FIG. 9 will next be explained by using a timing chart shown in FIG. 10. A description will be made here of, as an example, a case in which the data stored in each of the first memory cell MA 0  and the second memory cell MA 1  is read. In FIG. 10, ‘L’ indicates a ground voltage, and ‘H’ indicates a source voltage Vcc, respectively. ‘Vh’ indicates a voltage which is lower than the source voltage Vcc and is increased by about a threshold voltage Vt of each of the first and second MOS transistors TA 0  and TA 1  of the memory cells.  
         [0132]    In an initial state (at a time t 0 ), the voltages applied to the first through sixth switch control lines SWA 0 , SWA 1 , SWB 0 , SWB 1 , SWC 0  and SWC 1  are respectively of the H level. Thus, since the first switch transistor SWAT 0 , the third switch transistor SWBT 0  and the fifth switch transistor SWCT 0 , and the second switch transistor SWAT 1 , the fourth switch transistor SWBT 1  and the sixth switch transistor SWCT 1  are being turned on, the first bit line BLA 0 , the third bit line BLB 0 , and the fifth bit line BLC 0  are respectively connected to the first global bit line GBL 0 . Further, the second bit line BLA 1 , the fourth bit line BLB 1  and the sixth bit line BLC 1  are connected to the second global bit line GBL 1 . Thus the second bit line BLA 1 , the fourth bit line BLB 1  and the sixth bit line BLC 1  are connected to the first precharge transistor PCT 0  and the second precharge transistor PCT 1 , where they are precharged.  
         [0133]    Let&#39;s assume that “1” indicative of one of complementary digitized or binary data is written into a memory cell to be selected, i.e., the second memory cell MA 1  herein. The other complementary data “0” is written into the first memory cell MA 0 . Here, “1” indicates the side inverted in polarization at a ferroelectric capacitor upon reading.  
         [0134]    Upon reading the data stored in the memory cell MA 1  to be selected, the voltages applied to the precharge control line PCHG is first brought to the L level at a time t 1 . Thus, since the first precharge transistor PCT 0  and the second precharge transistor PCT 1  are turned off, the first global bit line GBL 0  and the second global bit line GBL 1  are respectively brought to a floating state. At this time, the third switch transistor SWBT 0  and the fifth switch transistor SWCT 0  are turned off.  
         [0135]    Consequently, the second memory cell block  710 -B and the third memory cell block  710 -C are separated from the first global bit line GBL 0 .  
         [0136]    Next, the first word line WLA 0  and the second word line WLA 1  are respectively brought to the Vh level at a time t 2 . Thus the first MOS transistor TA 0  and the second MOS transistor TA 1  of the first memory cell MA 0  and the second memory cell MA 1  are turned on so that one terminals of the first ferroelectric capacitor CA 0  and the second ferroelectric capacitor CA 1  are respectively rendered conductive to the first bit line BLA 0  and the second bit line BLA 1 . The reason why the first word line WLA 0  and the second word line WLA 1  are respectively brought to the Vh level other than the H level, is that the output voltages (drain voltages) of the first MOS transistor TA 0  and second MOS transistor TA 1  are reduced by Vt as compared with their input voltages (gate voltages).  
         [0137]    Subsequently, the first plate line PLA 0  is brought to the H level at a time t 3 . Consequently, the voltage on the first plate line PLA 0  is applied to the first bit line BLA 0  and the second bit line BLA 1  through the first ferroelectric capacitor CA 0 , the second ferroelectric capacitor CA 1 , and the first MOS transistor TA 0  and the second MOS transistor TA 1 . Thus a read voltage (V 0  or VS 1 ) is developed in each of the first bit line BLA 0  and the second bit line BLA 1 . Since the bit lines on the second global bit line GBL 1  side, of the bit lines of the respective memory cell blocks  710 -A,  710 -B and  710 -C, are connected to the global bit line, the second global bit line GBL 1  is sufficiently large in parasitic capacitance. Therefore, a read margin ΔV=VS 1 −V 0  becomes great too.  
         [0138]    At a time t 5 , the activation signal line SAE is brought to the H level to activate the sense amplifier SA. Thus the voltages applied to the first global bit line GBL 0  and the second global bit line GBL 1  are amplified.  
         [0139]    Subsequently, the select line SEL is brought to the H level at a time t 6 . Consequently, the first bit line selection transistor SET 0  and the second bit line selection transistor SET 1  are turned on so that the voltages of the first global bit line GBL 0  and the second global bit line GBL 1  are outputted to the data bus  720 .  
         [0140]    Next, the voltage applied to the fist plate line PLA 0  is returned to the L level at a time t 7 .  
         [0141]    At a time t 8 , the voltage applied to the precharge control line PCHG is returned to the H level, and the voltages applied to the activation signal line SAE and the select line SEL are respectively brought to the L level. Consequently, the first precharge transistor PCT 0  and the second precharge transistor PCT 1  are turned on so that the first global bit line GBL 0  and the second global bit line GBL 1  are grounded and the sense amplifier SA does not output read data. At the time t 8  as well, the third switch control line SWB 0  and the fifth switch control line SWC 0  are respectively returned to the H level. Thus, since the third switch transistor SWBT 0  and the fifth switch transistor SWCT 0  are turned on, the third bit line BLB 0  and the fifth bit line BLC 0  are connected to the first global bit line GBL 0 .  
         [0142]    At a time t 9 , the voltages on the first word line WLA 0  and the second word line WLA 1  are respectively brought to the L level to turn off the first MOS transistor TA 0  and the second MOS transistor TA 1 . Thus the read operation is completed.  
         [0143]    The above-described read voltages are detected to select the corresponding defective memory cell.  
         [0144]    Incidentally, the operation of reading stored data from other memory cells (no shown) of the first memory cell block  710 -A is also substantially identical to the operation of reading the data from the above-described memory cell MA 1 .  
         [0145]    On the other hand, when it is desired to read stored data from other memory cell blocks  710 -B and  710 -C, the operation of reading the data therefrom is similar to the operation of reading the data from the above-described memory cell MA 1  except that the bit line selection transistor, etc. are different.  
         [0146]    In order to use the ferroelectric memory according to the present embodiment in a normal mode, only the switch transistors (SWAT 0  and SWAT 1  or SWBT 0  and SWBT 1 ) on the accessing side are kept in an H state, whereby the writing or reading of data can be carried out as usual.  
         [0147]    Thus, owing to the reason similar to the ferroelectric memory according to the first embodiment, the ferroelectric memory according to the present embodiment is capable of increasing the capacitance of each bit line on the storage side of “1” data to thereby apparently reduce a read margin of each memory cell that will be degraded with time according to its use. Accordingly, each memory cell that will be rendered defective with time although its defect is not pronounced in the initial stage, can be selected without carrying out a long-time degradation accelerated test or the like.  
         [0148]    Further, according to the ferroelectric memory of the present embodiment, the pairs of memory cells are respectively blocked according to the sets of respective two switch transistors, whereby the capacitance of a desired bit line (partial line) can be controlled arbitrarily and adjustably. Thus, since selective conditions can be set finely, each defective memory cell can be selected more accurately.  
         [0149]    Another operation example 2 of the ferroelectric memory according to the third embodiment will be explained with reference to FIG. 11. FIG. 11 is a timing chart showing the operation example 2 of the ferroelectric memory according to the third embodiment. The operation to be described by the operation example 2 is different from the operation described according to the timing chart shown in FIG. 10 in that the operation of turning off the fourth switch transistor SWBT 1  and the sixth switch transistor SWCT 1  at a time t 4  in FIG. 11 to thereby isolate the fourth bit line BLB 1  and the sixth bit line BLC 1  connected to each other from the global bit line GBL 1  is added. Thus the capacitance of each bit line at the amplification of data by the corresponding sense amplifier (see a time t 5 ) can be set to one-half the capacitance at data reading or ½ under the control of the number of blocks to be separated. Accordingly, the sense amplifier SA can greatly be reduced in power consumption.  
         [0150]    In the present embodiment as described above, the numbers of the memory cells in the respective memory cell blocks  710 -A,  710 -B and  710 -C are set identical to each other. However, the numbers of the memory cells in the these blocks may not be made identical.  
         [0151]    While all the embodiments mentioned above have been described with the 2T2C/bit type memory cells as examples, the construction of the present invention can be of course applied even to a 1T1C/bit type memory cell, for example.  
         [0152]    According to the present invention as described above in detail, a ferroelectric memory is provided which includes a circuit structure capable of selecting a defective ferroelectric memory cell that could not be selected as a defective or fail cell without depending on a long-time accelerated degradation test since its defect has not heretofore been manifested immediately after its manufacture. Further, a method of carrying out a defective memory cell selection efficiently by use of the ferroelectric memory equipped with the aforementioned circuit structure is provided.  
         [0153]    While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Technology Category: 3