Patent Document

TECHNICAL FIELD 
     The present invention relates generally to the field of integrated circuits and, in particular, to detecting and configuring the required polarity of a circuit pin. 
     BACKGROUND ART 
     An integrated circuit or “chip” is generally installed or mounted on a system board which is ultimately installed in an end product. Commonly, an integrated circuit may be purchased for use in several (or many) different end products, often by different manufacturers. It will be appreciated that it may be impractical to use separate chip designs for similar applications. However, in the past, it has also been impractical to automatically modify chips so as to function with a variety of different system boards. 
     For example, audio devices such as DVD units and audio/video (A/V) receivers include a digital audio integrated circuit having, among other functional components, a digital-to-analog converter (DAC) for outputting an analog audio reproduction of a digital signal. The integrated circuit is mounted on a system board which generally includes a mute circuit to disable the analog audio output during unit power-on, reset or other predetermined events. Absent such mute, the listener would hear clicks and pops which are both distracting to the listener and potentially damaging to the audio device or speakers. And, even if only 0s are input into the DAC in an attempt to reduce the noise, clicks and pops may still be generated downstream from the DAC, especially as there may be some brief, but finite, time delay after the 0s begin to be input to the DAC. 
     FIGS. 1A-1D are examples of mute circuits commonly used on system boards. The circuits of FIGS. 1A and 1C are activated when the mute signal (actually the inverted mute signal) to the “mute node” is in a low state, driving the mute node to ground; these circuits are said to have an “active low mute”. In contrast, the circuits of FIGS. 1B and 1D have an active high mute and are activated when the control signal to the mute node is in a high state. 
     The mute circuit is activated by mute driver circuitry on the audio chip which, in turn, is enabled by a mute_control signal  202 . FIG. 2 is an illustration of a typical prior art mute driver circuit  200 . As will be understood, when the mute_control signal  202  is in a low state, transistor M 0  is off and M 1  is on, driving the mute node  204  high. And, when the mute_control signal  202  is in the high state, transistor M 0  is on and M 1  is off, driving the mute node  204  low. Depending upon whether the particular mute circuit on the system board is active high or active low, the signal to the mute node  204  must either be high or low. Consequently, the designer of the audio chip must either know in advance with which type of mute circuit the chip will be used and make available the appropriate chip or the system board designer must decide in advance which chip will be used and conform the mute circuit to the chip (and then be limited as to second or future sources of the chip). Alternatively, the chip may be designed with configurable polarity. However, configurable polarity requires either an extra and dedicated pin or a register which can be set through a control port whenever the chip goes through a power-on or reset. One disadvantage to using a register is that there may still be a delay after the chip exits the reset state until the register is configured. During this time the mute node may be in the unmute state, resulting in the undesirable clicks and pops which were to be eliminated. 
     Consequently, there remains a need for an integrated circuit having an inexpensive and efficient method for detecting the type of circuitry to which it is connected and having the ability to automatically configure itself with the appropriate polarity. 
     SUMMARY OF THE INVENTION 
     The present invention provides an integrated circuit mountable on a system board used, for example, in a digital audio device (such as a DVD or A/V receiver). The integrated circuit includes a digital-to-analog converter, possibly in conjunction with a CODEC, and the system board may include circuitry to, for example, mute the analog output of the device under certain predefined conditions. Because it may not be known in advance by the designer of the integrated circuit whether the circuit is activated by a signal in a high state (polarity) or a low state, the integrated circuit further includes a detector which detects and stores the required polarity (although it will be appreciated that certain of the components of the detector may also be placed off-chip). When it is necessary for the circuit to be activated, the detector provides a signal of the correct polarity. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A-1D are examples of mute circuits commonly used on system boards; 
     FIG. 2 is a prior art mute circuit driver; 
     FIG. 3 is a logic diagram of the present invention incorporated in a mute polarity detector; and 
     FIG. 4 is a logic diagram an alternative embodiment of a mute polarity detector of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 3 is a high level logic diagram of a polarity detector  300  of the present invention included in an exemplary integrated circuit which also includes a DAC. The chip is mountable on a system board having, for example, a mute circuit, preferably of the type illustrated in FIG. 1C or  1 D (if a circuit of FIG. 1A or  1 B are used and the input line is left floating, either circuit will self-bias to an undesirable un-muted state). The invention is described herein as being employed in conjunction with a mute circuit and mute node; however, such description should not be deemed as limiting and it will be understood that the invention may be used in conjunction with other types of circuits in which the polarity of a node is not known in advance but is determined at power-up or other type of reset. A driver circuit  302  is also included on the chip and is similar to the driver circuit illustrated in FIG.  2 . However, rather than the control gates of both switches (such as transistors M 0  and M 1 ) being tied to a mute_control signal node as in the prior art of FIG. 2, they are coupled to separate outputs of the detector  300 . Inputs to the detector  300  include the mute_control signal  202 , a detect_enable signal  304  and a mute_node_status  306  coupled to the mute node  204  (preferably through a buffer  308 ). Outputs include a mute_polarity signal  310  and signals  312  and  314  to the control gates of the switches M 0  and M 1 , respectively. Optionally, a pull-up resistor  326 , or its functional equivalent, may be coupled to the mute node  204  such that, if the mute node  204  is disconnected from the mute circuitry, the resistor  326  will prevent the mute node  204  from floating. It will be appreciated that a pull-down resistor may be used instead of the pull-up resistor  326 . 
     The detector  300  includes an OR gate  316 , an AND gate  318 , an XOR gate  320 , a latch  322  and an inverter  324 . It will be appreciated, of course, that any of these logic devices may be replaced by a functional equivalent. The mute_control signal  202  is coupled to an input to the XOR gate  320 , the detect_enable signal  304  is inverted by the inverter  324  and coupled to an input to the AND gate  318  (alternatively, an inverted detect_enable signal may be generated elsewhere in the chip). The detect_enable signal  304  is also coupled to a clock input to the latch  322  and to an input to the OR gate  316 . The outputs from the AND gate  318  and the OR gate  316  are coupled to the control gates of the switches M 0  and M 1 , respectively. The mute_node_status  306  is coupled to the input to the latch  322 . The mute_polarity signal  310  is coupled to the output of the latch  322 . The inverted output of the latch  322  is coupled to a second input to the XOR gate  320  whose output is coupled to a second input to the OR gate  316  and to a second input of the AND gate  318 . 
     In operation, when the chip is powered-on or undergoes a reset, the mute_detect signal  304  is asserted (goes to a high state), enabling the latch  322 . Simultaneously, the output of the OR gate  316  goes high and the output of the AND gate  318  goes low. The switches M 0  and M 1  thus both turn off, thereby preventing the mute node  204  from being pulled high or low and effectively isolating the mute node  204  from any of the control signals from the detector circuit  300 . Consequently, the polarity (or state) of the mute node  204  is determined only by the mute circuitry on the system board and this polarity is detected by the latch  322 . After the reset is complete, the mute_enable signal  304  is deasserted and the mute polarity is retained in the latch  322 . 
     Subsequently, when the mute_control signal  202  is asserted, the output of the XOR gate  320  will be high if the mute polarity was high and will be low if the mute polarity was low. The mute node  204  will thus be pulled high or low as required to properly activate the mute circuitry. 
     FIG. 4 is a logic diagram an alternative embodiment of a polarity detector  400  of the present invention, also used to configure as a mute node. The detector  400  includes an XOR gate  402  and a latch  404 . The detect_enable signal  304  is inverted by an inverter  406  and also coupled to an input to the detect_enable signal  304 . The mute_node_status  306  is coupled to the input to the latch  404 . The mute_polarity signal  310  is coupled to the output of the latch  404 . The mute_control signal  202  is coupled to an input to the XOR gate  402 . The output of the inverter  406  is coupled to the enable input of a non-overlap driver  408  (which prevents both transistors of the mute driver circuit  302  from being on simultaneously). The inverted output of the latch  404  is coupled to the other input of the XOR gate  402  and the output of the XOR gate  402  is coupled to the data input of the driver  408 . The outputs of the driver  408  are coupled to inputs of the mute driver circuit  302  and the output of the mute driver circuit  302  is the mute node  204 . A pull-up resistor  326  (or its functional equivalent) is coupled to the mute node  204  to prevent the mute node  204  from floating in the event mute circuitry is not connected to the mute node  204 . 
     In operation, when the detect_enable signal  304  is asserted, the outputs of the non-overlap driver  408  are disabled and, as in the previous embodiment, the input to the latch  404  receives the logic level of the mute node  204 . This level is latched into the latch  404 . When the detect_enable signal  304  is deasserted and the mute_control signal  202  is asserted, the inverted mute level (from the inverted output of the latch  404 ) is XORed with the mute_control signal  202  and the output is input to the non-overlap driver  408  to provide the correct polarity to the mute node  204 . 
     The objects of the invention have been fully realized through the embodiments disclosed herein. Those skilled in the art will appreciate that the various aspects of the invention may be achieved through different embodiments without departing from the essential function of the invention. For example, one or more of the elements of the detector of the present invention may be placed “off-chip”. The invention may also be incorporated with other types of integrated circuits and other off-chip circuitry in order to control the output of the integrated circuit where the polarity is determined at power-up or other type of reset. And, it will be appreciated that functional equivalents may be used in place of any of the elements of the invention. The particular embodiments are illustrative and not meant to limit the scope of the invention as set forth in the following claims.

Technology Category: 5