Patent Document

FIELD OF THE INVENTION 
     The present invention generally relates to methods and apparatuses for testing integrated circuit devices under various environmental and stress conditions, and, in particular, methods and apparatuses for reliability testing of interconnections and transistor structures in integrated circuits at ultra-high frequencies and under dynamically varying stress conditions. 
     BACKGROUND OF THE INVENTION 
     Integrated circuit reliability test systems have been devised to test the reliability of structures for interconnections or transistors in integrated circuit devices. The structures are placed under various dynamically varied environmental and stress conditions. For example, in order to design and implement a CPU to run at ultra-high frequencies (faster clock speeds), the interconnection structures and transistor structures for the CPU must be able to perform at these ultra-high frequencies and under the various dynamic stress conditions. Thus, before these structures are used in integrated circuit designs, they are specifically laid out in integrated circuit devices made specifically for testing purposes, where they are commonly referred to as devices-under-test (DUTs). The devices are then placed on a board where a number of signals can be fed to these DUTs. The board is then placed in a test chamber where the chamber can be programmed to create various environmental stress conditions such as variation in temperature and variation in electromagnetic field strength. While the board is in the chamber under programmed stress conditions, different types of signals at various frequencies can be provided to the DUTs to test the structures. Various characteristics of the structures within the DUTs can be monitored to appreciate the performance of the structures. 
     Referring to FIG. 1 a , prior art systems provide a board  2  with a number of sockets for the placement of the DUTs (DUT 1 -DUT 14 ). In routing the input signals to the DUTS, there is a connector  4  on the board to receive the input signals and to route the signals to each DUT via the data bus  6 . The output signals generated by the DUTs are also passed back to the system via the data bus  6  and connector  4 . One of the problems with this prior art system is that the input signal degrades when it travels down the data bus such that the input signal wave form at DUT 1  is not the same as the input signal wave form at DUT 7 . This problem becomes particularly acute when the input signal is at a very high frequency such that a square wave form may become progressively less square the further away from the connector. FIG. 1 b  illustrates the wave form at DUT 1  (FIG. 1 a ,  9 ) where the signal fairly resembles a square wave form input signal. FIG. 1 c  illustrates the wave form at DUT 7  (FIG. 1 a ,  10 ) where the input signal has deteriorated such that it does not resemble the square wave form at all. A result of this phenomenon is that the input signals to the DUTs are not uniform and the results generated are therefore non-uniform and unreliable. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a method and apparatus for uniformly and reliably testing of DUTs. 
     It is another object of the present invention to provide a method and apparatus for uniformly and reliably monitoring of DUTs. 
     It is yet another object of the present invention to provide a method and apparatus for uniformly and reliably delivering of input signals to the DUTs. 
     Briefly, a presently preferred embodiment provides a method and apparatus for monitoring and controlling devices under test. The preferred embodiment includes a computer based controller, a temperature control module, a power supply controller, a chamber interface module, a driver card and a DUT board. The computer-based controller responding to preprogrammed instructions (software) operates and coordinates the temperature control module, the chamber interface module, the power supply controller, and the driver card. The driver card, receiving commands and data from the computer-based controller, sends and receives a number of signals to and from the DUTs on the DUT board. These signals include voltage sources for operating the DUTs, a load voltage, DC current sources for setting duty and frequency cycles, switch signals, voltage measurement signals, and resistance measurement signals. The DUT board is a printed circuit board for holding a number of DUTs. Each of the DUTs is an integrated circuit containing one or more sets of circuitry for testing specifically designed test structures. 
     The circuitry of the DUT generally includes an oscillator with controllable duty cycle and frequency to excite the test structure. Measurement traces are provided on two sides of the test structure for measuring the characteristics of the test structure. The measured signals are then sent back to the driver card and to the computer-based controller for processing. In this manner, each DUT receives control signals in the form of DC current levels which control the duty cycle and the frequency of the wave form in testing the test structure. Since electrical DC current levels are fairly simple to control and can be uniformly delivered to each of the DUTs, the DUTs can be uniformly operated and tested. Therefore, the results generated by DUTs provide a higher level of consistency, uniformity, and reliability. 
     An advantage of the present invention is that it provides a method and apparatus for uniformly and reliably testing of DUTs. 
     Another advantage of the present invention is that it provides a method and apparatus for uniformly and reliably monitoring of DUTs. 
     Yet another advantage of the present invention is that it provides a method and apparatus for uniformly and reliably delivering of input signals to the DUTs. 
     These and other features and advantages of the present invention will become well understood upon examining the figures and reading the following detailed description of the invention. 
    
    
     IN THE DRAWINGS 
     FIG. 1 a  illustrates a general layout of a DUT board having a data bus connecting a number DUTs; 
     FIG. 1 b  illustrates the wave form of a signal delivered to a DUT at a point near the connector of the DUT board; 
     FIG. 1 c  illustrates the wave form of a signal delivered to a DUT at a point away from the connector of the DUT board and the deterioration of the wave form; 
     FIG. 2 illustrates the general block diagram of a preferred embodiment of the present invention; 
     FIG. 3 illustrates the components of the driver card for the DUT board; 
     FIG. 4 illustrates a layout of the DUT board of the preferred embodiment; 
     FIG. 5 illustrates an embodiment of the internal circuitry and the test structure that are within a DUT; and 
     FIGS. 6 a - 6   e  illustrate some of the test structures that may be tested with a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 2, a preferred embodiment of the present invention includes a computer-based controller  10 , a chamber controller  11  including a temperature control module  12  and a chamber interface module  14 , a power supply controller  16 , a power supply  18 , a driver card  20 , and a DUT board  22  which is placed inside a chamber  24 . The chamber  24  is equipped to generate and produce stress conditions in response to the signals from the temperature control module  12  and the chamber interface module  14 , where both of these modules are controlled and operated by the computer  10  via communication links  21  and  23 . Specifically, the temperature control module  12  controls the temperature  13  in the test chamber  24  and the chamber interface module  14  controls the electromagnetic field  15  in the test chamber  24 . The computer  10  also controls and operates the power supply controller  16  and the driver card  20 . The driver card  20  in turn sends and receives signals to and from the DUT board  22 . Although two communication links are illustrated herein, one communication link is sufficient. 
     FIG. 3 provides a block diagram of the driver card. Here, there are a number of input signals and blocks of circuitries receiving the signals for carrying out specific tasks. A programmable voltage regulator  30  receives an auxiliary control signal from the data bus  32  and regulates the power from power source  34  accordingly. It generates and delivers a load voltage through a relay  38  to the DUTs for biasing the DUTS. 
     The power source  34  also provides power to a voltage regulator  40  which is controlled by a programmable voltage controller  42 . The voltage regulator  40 , in response to the programmable voltage controller  42 , generates  2  voltages, V +  and V drive  at  44 , for the DUTs. To ensure consistent voltage delivery, the two voltages are remote sensed read back and monitored by the voltage regulator  40  via lines  46 . 
     The driver card receives various types of information from the computer where the information is stored or processed accordingly by the various components, including the data buffer  50 , the decoder  52 , the control data buffer  54 , the ID register  56  or the mode register  58 . The ID register  56  identifies the tray (or board) ID number, and the mode register places the board in the testing mode or the measurement mode. The data buffer  50  is connected to the driver card data bus  60 . The decoder  52  reading from the data buffer  50  and the control data buffer  54  provides instructions and data to other modules, including the programmable voltage controller  42 , the load gate controller  62 , the programmable frequency and duty cycle controller  64 , the switch controller  66 , the current source controller  68  for measurement purposes, and the multiplexer decoder  70  for operating multiplexer  72 . 
     The programmable voltage controller  42 , as explained previously, controls the voltage regulator  40  which provides power to the DUTs. The load gate controller  62  operates to open or close the relay  38  for introducing the load potential to the DUTs. This relay  38  can be controlled by the programmable voltage controller  42  as well. The programmable frequency and duty cycle controller  64  provides a first current level for controlling the desired duty cycle and a second current level for controlling the desired frequency. The current levels are provided to amplifier sets  74 , where a set of amplifiers is provided for each of the DUTs such that there is at least an amplifier for amplifying the duty cycle current level and an amplifier for amplifying the frequency current level. In the preferred embodiment, there are eighteen DUTs on the DUT board and therefore eighteen sets of DUT amplifiers for a total of thirty-six amplifiers. 
     For establishing the connections for measuring the test structures of the DUTs, referring to measurement subcircuit  51 , there are two control switches which are CMOS switches operated by the switch controller  66 . The current source controller  68  provides a reference current for measurement purposes. It is a constant voltage output device that converts the readings for the DUT devices into a current measurement to determine the resistance of the structure being tested or measured. 
     For each DUT, there are four monitor points for the high side  74  and four monitor points for the low sides  77  for monitoring the four test structures within each DUT. All of the signals from the monitored points are selectively provided via multiplexer  72  to a differential amplifier  78  and passed to an analog multiplexer  80 . Multiplexer  72  is operated by mux decoder  70  which receives instructions and data via the data bus  60  as to which of the DUTs and which of the test structures within the selected DUT is to be monitored. The analog multiplexer  80  is operated by switch  88  and receives a number of signals as inputs for monitoring/feedback purposes, including the supplied voltage levels as indicated at  82 , frequency and duty current levels at  84 , and reference current source at  86 . The output of the analog multiplexer  80  is amplified via amplifier  87  and selected via a signal from the data bus  32  through switch CMOS controller  88 . In effect, the analog measurement is multiplexed and amplified (buffered) for the system. 
     As is illustrated, the DUT board is provided with a load voltage potential  39 , V +  and V drive  voltage levels indicated at  44 , current levels indicated at  76  for setting the frequency and duty cycle, and switch signals at  67 . In operating the DUTs, the driver card monitors the voltage signal  46  and measures signals generated by the test structures of the DUTs  74  and  77 . 
     Referring to FIG. 4, the general layout of a preferred DUT board is illustrated. In the preferred embodiment, there are eighteen sockets for placement of DUTs on the board  100  where each DUT is connected to a data bus  102  via auxiliary circuitries (A 101 -A 118 ). The data bus is connected to a connector  104  for connection to the driver card. It should be noted that unlike the prior art, there is no limit as to the number of DUTs that can be placed on a board because of the advantageous method of the present invention in controlling and operating the DUTs. 
     Referring to FIG. 5, the connections to a DUT  110  for one test structure is illustrated along with its auxiliary circuitry  111 , noting that a DUT may contain several test structures and additional monitor lines would be needed in those cases. The DUT  110  is connected to the signal bus  102  via a number of signal lines. There is a line for receiving signal, I d , for controlling the duty cycle to be generated by the oscillator  106 , and a line for receiving signal I f  for controlling the frequency of the duty cycle of the oscillator  106 . The oscillator  106  is powered by V + , a DC voltage. The output of the oscillator  106  is provided to an amplifier  108  powered by V drive , and the output of the amplifier is connected to the test structure  109 . Traces for measuring the two ends of the test structure is connected when switches S H  and S L  are closed. The switches are CMOS switches with respective drain, source, and gate terminals. The signal obtained from the test structure via the CMOS switch is passed to or through a multi-purpose analog-to-digital (A/D) converter  107 , where the signal can be passed through without alteration or it can be converted to digital format and passed on to the bus. The advantage of converting the signal to digital format is to avoid the deterioration of the signal when it reaches the driver card. The A/D converter in response to a control signal from line  124  can process the signal from the test structure and generate digital information such as frequency count, duty cycle, etc. The digital output is delivered to the bus via lines  120  and  122 , where each line can consist of several data bus signal lines for the deliverance of the digital data. A voltage potential, V L , can be applied to the test structure to bias it. 
     In operation, I f  and I d  dictates the duty cycle and the frequency to be generated by the oscillator  106 . The output of the oscillator  106  is amplified and provided to the test structure  109 , which can be biased by applying a voltage potential, V L . With this method where I d  and I f  are at steady DC levels, the test structure can be precisely excited to the desired state without having to be concerned with deterioration of the signal for exciting the test structure. 
     Test Structure Types 
     There are many different types of test structures that may be examined. FIG. 6 a  illustrates a simple interconnection with two measurement points, M L  and M H , where there is a slight amount of resistance within the interconnection. The concern here is with electromigration. Electromigration (EM) is the transport of metal ions through a conductor resulting from the passage of direct electrical current. It is a combination of thermal and electrical effects on mass motion. The higher the temperature, the easier it is for the metal ions to electromigrate. The presence of electric field further pushes the ions in the test structure. By examining the test structures under various conditions, the median time to failure (MTF) of the test structure can be determined. 
     Other types of test structures maybe tested as well, including testing for hot carrier effect and time-dependent dielectric breakdown condition of the transistors. 
     Hot Carrier Effect 
     In the reverse-bias drain-to-substrate junction, the electric field may be quite high in short-channel devices. Carriers that are injected into the depletion layer are accelerated by the high field, and some of them may gain enough energy to cause impact ionization. These carriers have higher energy than the thermal energy and are called hot carriers. The holes generated by multiplication can flow to the substrate, giving rise to a large substrate current. Some of the holes may find their way to the source, effectively lowering the source barrier to induce electron injection. The electrons generated in the drain depletion layer are attracted to the positive gate voltage. If these electrons exceeds certain eV, they may be able to tunnel into the oxide or to surmount the silicon-oxide potential barrier to produce a gate current. In either case, electrons can be trapped inside the gate oxide, thus changing the threshold voltage and the current-voltage characteristics. This is not desirable and should be avoided. The drain current can be easily measured by using the method of the present invention by first exciting the transistor to certain threshold and measuring the resistance at the appropriate terminals of the transistor. FIGS. 6 b  and  6   c  illustrate two ways of connecting to a transistor structure to measure for the hot carrier effect. 
     Time-Dependent Dielectric Breakdown Condition 
     Oxide breakdown is an important process reliability subject in the development of MOS and CMOS technologies. Oxide breakdown is described by the test methods used to cause the dielectric breakdown. In time-dependent dielectric breakdown (TDDB) a constant voltage is applied across the gate oxide at a given temperature. The leakage current across the gate oxide is monitored, and the time to breakdown is recorded when the current exceeds some value. 
     FIGS. 6 d  and  6   e  illustrate two ways of connecting to a transistor for measuring for the TDDB condition. 
     While the present invention has been described with reference to a certain preferred embodiment, it is to be understood that the present invention is not to be limited to such specific embodiments. Rather, it is the inventor&#39;s intention that the invention be understood and construed in its broadest meaning as reflected by the following claims. Thus, these claims are to be understood as incorporating and not only the preferred embodiment described herein but all those other and further alterations and modifications as would be apparent to those of ordinary skill in the art.

Technology Category: g