Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 61/242,399, filed Sep. 15, 2009, the entire contents of which are hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a memory management system and method thereof, and more particularly to a memory management system and method thereof for efficiently managing data transfer. 
     2. Description of Related Art 
     Most present day computer systems implement virtual memory to accelerate the computer systems and reduce the systems&#39; loading. By utilizing virtual memory, the computer systems are able to operate more efficiently in multi-tasking environments, and the computer systems are able to do so at accelerated rates. 
     However, because of the technology being updated so rapidly, data processed by the computer system tends, tirelessly, to grow larger and larger while becoming more and more complicated. Owing to the size of the data becoming larger and larger and the virtual memory being accessed very frequently, the virtual memory in the computer system often reaches an overloaded state, which reduces the efficiency of the computer system and wastes power. In the Universal Serial Bus (USB) 2.0 standard, the speed of the data transfer is 480 Mbps (Megabyte per second). However, the speed of the data transfer is over Gbps (Gigabyte per second) and is more than 4 Gbps in the USB 3.0 standard. Because the speed of the data transfer is so fast, it is necessary to provide an effective method for the virtual memory access to reduce loading of the computer system. 
     Therefore, there is a need to design a better memory access management scheme to effectively control memory access so as to reduce loading of the computer system and power consumption. 
     SUMMARY OF THE INVENTION 
     A memory management system is disclosed in the present invention to include a cache buffer, a memory mapping table, a data backup cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses corresponding to the data structures, and the data backup cache is configured to store the base addresses of the data structure. The memory controller is configured to control the data structures reading and writing in the cache buffer and the data backup cache. 
     A memory management method is disclosed in the present invention to include a step of receiving an instruction in a memory controller and a step of comparing a plurality of addresses of data structures in a memory mapping table with the instruction by the memory controller. The method further includes a step of reading the data structure in a cache buffer when an address corresponding to the instruction is available in the memory mapping table, and a step of selecting a writable entry from the memory mapping table and reading the data structure in a system memory and writing the data structure to the cache buffer when the address corresponding to the instruction is not available in the memory mapping table. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block diagram illustrating a memory management system of a preferred embodiment of the present invention; 
         FIG. 2  is a flow chart illustrating memory reading and writing functions in the memory management system of the present invention; 
         FIG. 3  is a state diagram illustrating states of the memory management method in the present invention; and 
         FIG. 4A ,  FIG. 4B ,  FIG. 4C ,  FIG. 4D  and  FIG. 4E  are schematic diagrams illustrating the memory mapping table of the memory management system in the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A detailed description of the present invention will now be provided with reference to the following embodiments, which are not intended to limit the scope of the present invention and which can be adapted for other applications. While the drawings are illustrated in detail, it is appreciated that the quantity of the disclosed components may be greater or less than that disclosed, except for instances expressly restricting the amount of the components. 
       FIG. 1  is a schematic block diagram showing a memory management system in a preferred embodiment of the present invention. According to the illustrated embodiment, the memory management system  10  comprises components including a cache buffer (such as a pipe table look-aside buffer, pipe TLB)  102 , a memory mapping table (such as pipe mapping table)  104 , a data backup cache (such as Scratchpad Buffer Address Cache)  106 , and a memory controller  108 . The cache buffer  102  is configured to store data structures (such as endpoint data structures) with 8 double words. In one embodiment, there are 32 endpoint data structures stored in the cache buffer  102  with those endpoint data structures being full association data structures. The memory mapping table  104  is configured to store the data addresses and other control information of the system memory corresponding to the endpoint data structures in the cache buffer  102 . In one embodiment, there are 32 entries corresponding to the endpoint data structures of the cache buffer  102 . The data backup cache  106  is configured to store a plurality of base addresses of all endpoint data structures such as the scratchpad buffer array base addresses and the scratchpad buffer entry base addresses. The memory controller  108  is configured to manage the reading and the writing of the endpoint data structures in the cache buffer  102  and the data backup cache  106  and search the correct endpoint data structures in an effective way according to the external signal request of the memory management system  10 . 
     Still referring to  FIG. 1 , the memory management system  10  further includes a first channel  110 , a second channel  112 , and an arbitrator  114 . The first channel  110  and the second channel  112  are configured to transfer an instruction  116  which includes address information of an endpoint data structure. In one embodiment, the first channel  110  is a super speed channel, and the second channel  112  is a high speed channel. The first channel  110  and the second channel  112  are selected in accordance with the data transfer speed of the instruction  116 . The arbitrator  114  is configured to determine which instructions  116  (the instruction  116  in the first channel  110  or the instruction  116  in the second channel  112 ) to execute first in accordance with the priority of the instruction  116 . When the instruction  116  is transmitted to the memory controller  108 , the memory controller  108  will compare the addresses of the endpoint data structures in the memory mapping table  104  with the instruction  116  to search out (e.g., locate) an address corresponding to the instruction  116 . If the address corresponding to the instruction  116  is available in the memory mapping table  104 , the endpoint data structure corresponding to the instruction  116  has been stored in the cache buffer  102  and the endpoint data structure is sent back to the memory controller  108  for further executing. If the address corresponding to the instruction  116  is not available in the memory mapping table  104 , the memory controller  108  will select an empty entry or a replaceable entry in the memory mapping table  104 . In accordance with the instruction  116  and the corresponding scratchpad buffer array base address and the corresponding scratchpad buffer entry base address stored in the data backup cache  106 , the memory controller  108  will find the endpoint data structure in the system memory, the address and other control information of the endpoint data structure will be written in the empty entry or the replaceable entry in the memory mapping table  104 , and the endpoint data structure will be stored in the cache buffer  102 . In addition, when the data flow control described above is finished or some error(s) has occurred in the memory management system of the present invention, the endpoint data structure stored in the cache buffer  102  is also in need of being updated. 
     However, it should be noted that the data addresses shown in  FIG. 1  are updated according to a Least Recently Used (LRU) algorithm to refresh the entry of the memory mapping table  104 . There are four bits in the memory mapping table  104  configured as in-active counter (IACTCNT), and those bits are configured to memorize the access records of the entries. According to the access records of the entries in the memory mapping table  104 , the LRU algorithm is able to determine which entries is/are replaceable. As the LRU algorithm is well-known in the prior art by those persons skilled in the art, a detailed description of the LRU algorithm is omitted herein. In addition, the memory management system  10  further includes a microprocessor  118 , which is configured to update the addresses of the endpoint data structures stored in each of the entries of the memory mapping table  104  according to the different conditions for the memory operation. 
       FIG. 2  is a flow chart illustrating memory reading and writing functions in the memory management system of the present invention. As shown in the depicted process, a starting step  202  in which an initial status of the cache buffer  102  is idle is followed by step  204  in which an instruction  116  (PIPEREQ) is read in the memory controller  108  succeeded by the memory controller  108  comparing the addresses of the endpoint data structures in the memory mapping table  104  with the instruction  116 . At step  206 , if the address corresponding to the instruction  116  is available in the memory mapping table  104 , the endpoint data structure corresponding to the instruction  116  has been stored in the cache buffer  102  and the endpoint data structure is read from the cache buffer  102 , and the memory reading steps are finished. At step  208 , if the address corresponding to the instruction  116  is not available in the memory mapping table  104 , an empty entry or a replaceable entry in the memory mapping table  104  is selected as a writable entry. At step  210 , the endpoint data structure is read from the system memory in accordance with the instruction  116  and the scratchpad buffer array base address and the scratchpad buffer entry base address stored in the data backup cache  106 , and the address of the endpoint data structure is written in the writable entry of the memory mapping table  104  found at step  208 . The endpoint data structure is written into the cache buffer  102 . 
       FIG. 3  is a state diagram illustrating the states of the memory management method in the present invention. As indicated in the exemplary implementation, an idle state  302  is followed by states  304  and  306 , in which the scratchpad buffer array base addresses and the scratchpad buffer entry base addresses of all the endpoint data structures are read from the system memory and stored in the data backup cache  106 . Progression from the initial states  302 ,  304  and  306  leads to state  308 , in which the cache buffer  102  in working state is made ready to read and write. In state  310 , the addresses of the endpoint data structures in the memory mapping table  104  are compared with the instruction  116 . In state  312 , if the address corresponding to the instruction  116  is available in the memory mapping table  104 , the 8 double words endpoint data structure has been stored in the cache buffer  102  and the 8 double words endpoint data structure is read from the cache buffer  102 , and then the state is returned to state  308 . In state  314 , if the address corresponding to the instruction  116  is not available in the memory mapping table  104 , an empty entry is sought and/or identified in the memory mapping table  104 . If the empty entry exists in the memory mapping table  104 , the empty entry is selected to be the writable entry followed by movement to state  318 . If the empty entry does not exist in the memory mapping table  104 , a replaceable entry in the memory mapping table  104  is selected to be the writable entry followed by movement to state  316 . In state  316 , the endpoint data structure in the cache buffer  102  corresponding to the writable entry in the memory mapping table  104  is written into the system memory, with the progression then going to state  318 . In state  318 , the endpoint data structure is read from the system memory and written in the cache buffer  102 , and the address of the endpoint data structure is written into the writable entry in the memory mapping table  104 , with the progression then returning to state  308 . In state  320 , the microprocessor  118  will request to (and/or will) update the next link pointer of the endpoint data structures. In state  322 , the microprocessor  118  requests to (and/or will) read the 8 double words endpoint data structure. In state  324 , according to an example in which “doorbell ring” is one of the addresses in the mapping table  104 , when the address of doorbell ring is 1, the microprocessor  118  will request to (and/or will) update the address of DBPV (an address name or mark, in the example) in the memory mapping table  104 . In state  326 , the microprocessor  118  will request to (and/or will) remove an 8 double words endpoint data structure in the cache buffer  102  when the endpoint data structure should be removed from the asynchronous or periodic time table. When the instruction  116  has been executed or an error exists or occurs during executing the instruction  116 , the endpoint data structure in the cache buffer  102  will be updated. In state  328 , the microprocessor  118  will request to (and/or will) write the updated endpoint data structure in the cache buffer  102  back to the system memory. 
       FIG. 4A ,  FIG. 4B ,  FIG. 4C ,  FIG. 4D  and  FIG. 4E  are schematic diagrams illustrating an implementation of the memory mapping table of the memory management system according to an embodiment of the present invention. As shown in  FIG. 4A , the data in addresses  0 ˜ 12  is the address of the endpoint data structure in the system memory. The data in addresses  13 ˜ 16  is configured for the microprocessor to control or confirm whether the entry in the memory mapping table is ready, whether the entry is available, and whether the entry is locked. The data in addresses  17 ˜ 20  is the In-Active Counter and configured to record the LRU algorithm. The addresses  21 ˜ 31  are the reserved addresses.  FIG. 4B  is a schematic diagram illustrating the address arrangement in the memory mapping table when the next link pointer of the endpoint data structure needs to be updated when the endpoint data structure is in asynchronous status, and  FIG. 4C  is a schematic diagram illustrating the address arrangement in the memory mapping table when the address in the DBPV needs to be updated. The schematic diagram of  FIG. 4D  illustrates the address arrangement in the memory mapping table when the endpoint data structures in the memory endpoint data structure need to be removed.  FIG. 4E  is a schematic diagram illustrating the address arrangement in the memory mapping when the endpoint data structure in the cache buffer needs to be read. 
     Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.

Technology Category: g