Patent Document

FIELD OF THE INVENTION 
       [0001]    This invention relates generally to the cell structure, device configuration and fabricating method of power semiconductor devices. More particularly, this invention relates to an improved cell configuration to manufacture trench shielded gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with Schottky rectifier diode, Gate-Drain (GD) and Gate-Source (GS) clamp diode on single chip for device shrinkage and performance improvement. 
       BACKGROUND OF THE INVENTION 
       [0002]    Please refer to  FIG. 1 , normally for high efficiency DC/DC application, a Schottky rectifier is externally added in parallel with a MOSFET device to prevent a parasitic P/N body diode in the MOSFET from turning on in order to achieve higher speed and efficiency. The requirement for clamping effect is that the forward voltage of the Schottky rectifier Vf is less than the parasitic P/N body diode (˜0.7V). Besides, for providing effective ESD (electrostatic discharge) protection between gate (G, as illustrated in  FIG. 1 ) and source (S, as illustrated in  FIG. 1 ) and between gate and drain (D, as illustrated in  FIG. 1 ), plurality poly-silicon Zener diodes are respectively implemented therein with breakdown voltage lower than that of the MOSFET device for clamping voltage between gate and source, and between gate and drain for avalanche protection. However, assembly of those separate structures into single package with extra interconnection wires results in higher manufacturing cost, and poor performance due to increase in inductance from the extra interconnection wires. 
         [0003]    Accordingly, it would be desirable to provide more integrated MOSFET device with embedded Schottky rectifier diode, Gate-Drain and Gate-Source clamp diodes on single chip for device shrinkage and performance improvement. 
       SUMMARY OF THE INVENTION 
       [0004]    It is therefore an aspect of the present invention to provide improved semiconductor power device configuration for providing an integrated circuit comprising trench MOSFET with embedded Schottky rectifier, Gate-Drain clamp diode and Gate-Source clamp diode on single chip to achieve reduced die size, lower cost and improved performance. According to the present invention, the integrated circuit comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate; a trench MOSFET comprising a plurality of shielded trenched gates in the epitaxial layer, wherein each the shielded trenched gate comprising a gate electrode disposed in the upper portion and a shielded electrode disposed in the lower portion of a first type gate trench, wherein the gate electrode and the shielded electrode insulated from each other by an inter-electrode insulation layer; each the shielded trenched gate comprising a first type gate oxide surrounding bottom and sidewalls of the shielded electrode and a second type gate oxide along sidewalls of the gate electrode, wherein the first type gate oxide having thickness greater than the second type gate oxide; the gate electrode in the first gate trench being surrounded by a source region of the first conductivity type encompassed in a body region of a second conductivity type, the gate electrode being connected to a gate metal; the shielded electrode in the first type gate trench being surrounded by the epitaxial layer and being connected to a source metal; a Schottky rectifier extending into the epitaxial layer and having a Schottky barrier layer lined in a trenched anode contact filled with a contact metal plug; a Gate-Drain clamp diode comprising multiple back to back poly-silicon Zener diodes with alternating doped regions of the first conductivity type next to the second conductivity type, connected with the gate metal on one side and with a drain metal on another side through a plurality of metal stripes cross over a termination area; and a Gate-Source clamp diode comprising multiple back to back poly-silicon Zener diodes with alternating doped regions of the first conductivity type next to the second conductivity type, connected with the gate metal on one side, and with the source metal on another side. 
         [0005]    It is therefore another aspect of the present invention to provide improved semiconductor power device configuration for providing an integrated circuit comprising trench MOSFET with embedded Schottky rectifier and Gate-Source clamp diode on single chip to achieve reduced die size, lower cost and improved performance. According to the present invention, the integrated circuit comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate; a trench MOSFET comprising a plurality of shielded trenched gates in the epitaxial layer, wherein each the shielded trenched gate comprising a gate electrode disposed in the upper portion and a shielded electrode disposed in the lower portion of a first type gate trench, wherein the gate electrode and the shielded electrode insulated from each other by an inter-electrode insulation layer; each the shielded trenched gate comprising a first type gate oxide surrounding bottom and sidewalls of the shielded electrode and a second type gate oxide along sidewalls of the gate electrode, wherein the first type gate oxide having thickness greater than the second type gate oxide; the gate electrode in the first gate trench being surrounded by a source region of the first conductivity type encompassed in a body region of a second conductivity type, the gate electrode being connected to a gate metal; the shielded electrode in the first type gate trench being surrounded by the epitaxial layer and being connected to a source metal; a Schottky rectifier extending into the epitaxial layer and having a Schottky barrier layer lined in a trenched anode contact filled with a contact metal plug; and a Gate-Source clamp diode comprising multiple back to back poly-silicon Zener diodes with alternating doped regions of the first conductivity type next to the second conductivity type, connected with the gate metal on one side, and with the source metal on another side. 
         [0006]    It is therefore another aspect of the present invention to provide improved semiconductor power device configuration for providing an integrated circuit comprising trench MOSFET with embedded Schottky rectifier, and Gate-Drain clamp diode on single chip to achieve reduced die size, lower cost and improved performance. According to the present invention, the integrated circuit comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate; a trench MOSFET comprising a plurality of shielded trenched gates in the epitaxial layer, wherein each the shielded trenched gate comprising a gate electrode disposed in the upper portion and a shielded electrode disposed in the lower portion of a first type gate trench, wherein the gate electrode and the shielded electrode insulated from each other by an inter-electrode insulation layer; each the shielded trenched gate comprising a first type gate oxide surrounding bottom and sidewalls of the shielded electrode and a second type gate oxide along sidewalls of the gate electrode, wherein the first type gate oxide having thickness greater than the second type gate oxide; the gate electrode in the first gate trench being surrounded by a source region of the first conductivity type encompassed in a body region of a second conductivity type, the gate electrode being connected to a gate metal; the shielded electrode in the first type gate trench being surrounded by the epitaxial layer and being connected to a source metal; a Schottky rectifier extending into the epitaxial layer and having a Schottky barrier layer lined in a of trenched anode contact filled with a contact metal plug; and a Gate-Drain clamp diode comprising multiple back to back poly-silicon Zener diodes with alternating doped regions of the first conductivity type next to the second conductivity type, connected with the gate metal on one side and with a drain metal on another side through a plurality of metal stripes cross over a termination area. 
         [0007]    It is therefore another aspect of the present invention to provide improved semiconductor power device configuration for providing an integrated circuit comprising trench MOSFET with Gate-Drain clamp diode and Gate-Source clamp diode on single chip to achieve reduced die size, lower cost and improved performance. According to the present invention, the integrated circuit comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate; a trench MOSFET comprising a plurality of shielded trenched gates in the epitaxial layer, wherein each the shielded trenched gate comprising a gate electrode disposed in the upper portion and a shielded electrode disposed in the lower portion of a first type gate trench, wherein the gate electrode and the shielded electrode insulated from each other by an inter-electrode insulation layer; each the shielded trenched gate comprising a first type gate oxide surrounding bottom and sidewalls of the shielded electrode and a second type gate oxide along sidewalls of the gate electrode, wherein the first type gate oxide having thickness greater than the second type gate oxide; the gate electrode in the first gate trench being surrounded by a source region of the first conductivity type encompassed in a body region of a second conductivity type, the gate electrode being connected to a gate metal; the shielded electrode in the first type gate trench being surrounded by the epitaxial layer and being connected to a source metal; a Gate-Drain clamp diode comprising multiple back to back poly-silicon Zener diodes with alternating doped regions of the first conductivity type next to the second conductivity type, connected with the gate metal on one side and with a drain metal on another side through a plurality of metal stripes cross over a termination area; and a Gate-Source clamp diode comprising multiple back to back poly-silicon Zener diodes with alternating doped regions of the first conductivity type next to the second conductivity type, connected with the gate metal on one side, and with the source metal on another side. 
         [0008]    It is therefore another aspect of the present invention to provide improved semiconductor power device configuration for providing an integrated circuit comprising trench MOSFET with Gate-Source clamp diode on single chip to achieve reduced die size, lower cost and improved performance. According to the present invention, the integrated circuit comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate; a trench MOSFET comprising a plurality of shielded trenched gates in the epitaxial layer, wherein each the shielded trenched gate comprising a gate electrode disposed in the upper portion and a shielded electrode disposed in the lower portion of a first type gate trench, wherein the gate electrode and the shielded electrode insulated from each other by an inter-electrode insulation layer; each the shielded trenched gate comprising a first type gate oxide surrounding bottom and sidewalls of the shielded electrode and a second type gate oxide along sidewalls of the gate electrode, wherein the first type gate oxide having thickness greater than the second type gate oxide; the gate electrode in the first gate trench being surrounded by a source region of the first conductivity type encompassed in a body region of a second conductivity type, the gate electrode being connected to a gate metal; the shielded electrode in the first type gate trench being surrounded by the epitaxial layer and being connected to a source metal; and a Gate-Source clamp diode comprising multiple back to back poly-silicon Zener diodes with alternating doped regions of the first conductivity type next to the second conductivity type, connected with the gate metal on one side, and with the source metal on another side. 
         [0009]    It is therefore another aspect of the present invention to provide improved semiconductor power device configuration for providing an integrated circuit comprising trench MOSFET with Gate-Drain clamp diode on single chip to achieve reduced die size, lower cost and improved performance. According to the present invention, the integrated circuit comprising: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate; a trench MOSFET comprising a plurality of shielded trenched gates in the epitaxial layer, wherein each the shielded trenched gate comprising a gate electrode disposed in the upper portion and a shielded electrode disposed in the lower portion of a first type gate trench, wherein the gate electrode and the shielded electrode insulated from each other by an inter-electrode insulation layer; each the shielded trenched gate comprising a first type gate oxide surrounding bottom and sidewalls of the shielded electrode and a second type gate oxide along sidewalls of the gate electrode, wherein the first type gate oxide having thickness greater than the second type gate oxide; the gate electrode in the first gate trench being surrounded by a source region of the first conductivity type encompassed in a body region of a second conductivity type, the gate electrode being connected to a gate metal; the shielded electrode in the first type gate trench being surrounded by the epitaxial layer and being connected to a source metal; a Gate-Drain clamp diode comprising multiple back to back poly-silicon Zener diodes with alternating doped regions of the first conductivity type next to the second conductivity type, connected with the gate metal on one side and with a drain metal on another side through a plurality of metal stripes cross over termination area. 
         [0010]    In some other preferred embodiments, the present invention can be implemented including one or more following features: the trench MOSFET further comprising a second type gate trench being filled with a single shielded electrode having same conductive material as the shielded electrode in the shielded trenched gates in the trench MOSFET, padded by the first type gate oxide, wherein the single shielded electrode in the second type gate trench being connected to the source metal through a trenched shielded electrode contact filled with the contact metal plug; the Schottky rectifier is a trench Schottky rectifier having a Schottky barrier layer lined in the trenched anode contact filled with the contact metal plug, and disposed between a pair of adjacent third type gate trenches, each of the third type gate trenches filled with a single shielded electrode having same conductive material as the shielded electrode in the shielded trenched gates in the trench MOSFET, padded by the first type gate oxide; the Schottky rectifier is a trench Schottky rectifier having a Schottky barrier layer lined in the trenched anode contact filled with the contact metal plug, and disposed between a pair of adjacent third type gate trenches, each of the third type gate trenches filled with a gate electrode and a shielded electrode having same conductive material and structure as the shielded trenched gates in the trench MOSFET; the Schottky rectifier is a Junction Barrier Schottky (JBS) rectifier having a Schottky barrier layer lined in the trenched anode contact filled with the contact metal plug and between a pair of the adjacent body regions; the Schottky rectifier further comprising a Schottky barrier enhancement region of the first conductivity type surrounding sidewalls and bottom of each the trenched anode contact in the epitaxial layer, the Schottky barrier height enhancement region having doping concentration lower than the epitaxial layer; the Schottky rectifier further comprises a Schottky barrier height enhancement region of the second conductivity type surrounding sidewalls and bottom of each the trenched anode contact in the epitaxial layer; the Gate-Source clamp diode being connected to the source metal through a first trenched diode contact filled with the contact metal plug, and being connected to the gate metal through a second trenched diode contact filled with the contact metal plug; the Gate-Drain clamp diode being connected to the gate metal through a third trenched diode contact filled with the contact metal plug, and being connected to the drain metal through a forth trenched diode contact filled with the contact metal plug; the integrated circuit further comprises etch-buffer trenched gates disposed in the epitaxial layer underneath each of the first, second, third and forth trenched diode contacts to serve as buffer layers for prevention of gate-body shortage. 
         [0011]    These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: 
           [0013]      FIG. 1  is a conventional application circuit of the MOSFET power device with integration of Schottky rectifier, Gate-Drain and Gate-Source clamp diodes in single package. 
           [0014]      FIG. 2A  is a preferred A-B cross-sectional view of an integrated circuit according to the present invention disclosed in  FIG. 2C . 
           [0015]      FIG. 2B  is a preferred C-D cross-sectional view of an integrated circuit according to the present invention disclosed in  FIG. 2C . 
           [0016]      FIG. 3  is a normalized measurement result of the relationship between breakdown voltage and metal width across over field plate termination. 
           [0017]      FIG. 4  is another preferred A-B cross-sectional view of an integrated circuit according to the present invention disclosed in  FIG. 2C . 
           [0018]      FIG. 5  is another preferred A-B cross-sectional view of an integrated circuit according to the present invention disclosed in  FIG. 2C . 
           [0019]      FIG. 6  is another preferred A-B cross-sectional view of an integrated circuit according to the present invention disclosed in  FIG. 2C . 
           [0020]      FIG. 7  is another preferred A-B cross-sectional view of an integrated circuit according to the present invention disclosed in  FIG. 2C . 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0021]    Please refer to  FIG. 2A  and  FIG. 2B  for a preferred embodiment of this invention which is respective A-B and C-D cross-sectional view of  FIG. 2C . In  FIG. 2A , an N-channel trench MOSFET  100  is implemented with Junction Barrier Schottky rectifier  101  (JBS, as illustrated), a Gate-Source clamp diode  102  (GIS clamp diode, as illustrated) and a Gate-Drain clamp diode  103  (G/D clamp diode, as illustrated) in an N epitaxial layer  104  above an N+ substrate  105  which is coated with back metal of Ti/Ni/Ag on rear side as drain metal  106 . The trench MOSFET  100  further comprises a plurality of first type gate trenches  107  for shielded trenched gates and a second type gate trench  108  for shielded electrode contact, wherein each the first type gate trench  107  is filled with a gate electrode  109  in the upper portion and a shielded electrode  110  in the lower portion, wherein the gate electrode  109  is insulated from the shielded electrode  110  by an inter-electrode insulation layer  111 . Besides, each the shielded trenched gate comprises a first type gate oxide  112  surrounding sidewalls and bottom of the shielded electrode  110  and a second type gate oxide  113  surrounding sidewalls of the gate electrode  109 , wherein the first type gate oxide  112  has a thickness greater than the second type gate oxide  113 . Furthermore, each the gate electrode  109  being connected to a gate metal  116  is surrounded by an n+ source region  114  encompassed in a P body region  115 , wherein the n+ source region  114  and the P body region  115  is connected to a source metal  117  over a contact insulation layer  118  via a trenched source-body contact  119  filled with a contact metal plug, for example, tungsten plug, which has bottom surrounded by a p+ body contact region  181  to reduce contact resistance between the contact metal plug and the P body region  115 . Meanwhile, each the shielded electrode  110  is surrounded by the N epitaxial layer  104  and connected to the source metal  117 . The second type gate trench  108  is filled with a single shielded electrode  120  and padded by the first type gate oxide  112 , wherein the single shielded electrode  120  has same conductive material as the shielded electrode  110  and is connected to the source metal  117  via a trenched shielded electrode contact  121  filled with the contact metal plug. 
         [0022]    The Junction Barrier Schottky rectifier  101  comprises a Schottky barrier layer lined in a trenched anode contact  122  filled with the contact metal plug extending into the N epitaxial layer  104  between a pair of the P body regions  115  which is connected to the source metal  117 . The Gate-Source clamp diode  102  comprises multiple back to back poly-silicon Zener diodes with alternating n+ doped regions and p doped regions, wherein the n+ doped region  123  on one side of the poly-silicon Zener diodes is connected to the source metal  117  through a first trenched diode contact  125  filled with the contact metal plug, while the n+ doped region  124  on another side of the poly-silicon Zener diodes is connected to the gate metal  116  through a second trenched diode contact  126  filled with the contact metal plug. The Gate-Drain clamp diode  103  comprises multiple back to back poly-silicon Zener diodes with alternating n+ doped regions and p doped regions, wherein the n+ doped region  127  on one side of the poly-silicon Zener diode is connected to the gate metal  116  through a third trenched diode contact  129  filled with the contact metal plug, while the n+ doped region  128  on another side of the 
         [0023]    Zener diode is connected to a metal stripe  131  as filed plate cross over a termination area through a forth trenched diode contact  130  which is finally connected to the drain metal  106  through a trenched drain contact  132  filled with the contact metal plug. Furthermore, underneath each of the first, second, third, and forth trenched diode contacts, a etch-buffer trenched gate having same structure as the one in the second type gate trench  108  in the trench MOSFET  100  is formed in the N epitaxial layer  104  to serve as buffer layer for prevention of gate-body shortage. 
         [0024]    Please refer to  FIG. 2B  for a preferred C-D cross section of  FIG. 2C . Comparing to  FIG. 2A ,  FIG. 2B  further comprises an open area  140  between the metal stripes where from electrical field comes out to avoid avalanche degradation. 
         [0025]      FIG. 2C  is a top view of a preferred embodiment showing the Gate-Drain clamp diode across the termination area with the open area  140  and metal width W. Please refer to  FIG. 3  for a normalized measurement result of the relationship between breakdown voltage and the metal width W showing that the breakdown voltage will be degraded when the metal width W is greater than Sum, which means that the electrical field underneath the filed plate can not effectively go through the open area  140  if the metal width is larger than 5 um. 
         [0026]      FIG. 4  is another preferred A-B cross section of  FIG. 2C  which has a similar configuration to  FIG. 2A , except that, the integrated circuit in  FIG. 4  comprises a trench Schottky rectifier  201  having a Schottky barrier layer lined in the trenched anode contact  222  filled with the contact metal plug and disposed between a pair of third type gate trenches  233 . Each the third type gate trench  233  is filled with the gate electrode  209  in the upper portion and the shielded electrode  210  in the lower portion, having same conductive material and structure as the shielded trenched gates in the first type gate trenches  207  in the trench MOSFET  200 . Meanwhile, the gate electrode  209  in the third type gate trench  233  is connected to the source metal  217 . 
         [0027]      FIG. 5  is another preferred A-B cross section of  FIG. 2C  which has a similar configuration to  FIG. 4 , except that, the trench Schottky rectifier  301  in  FIG. 5  further comprises an n− Schottky barrier height enhancement region  334  surrounding sidewalls and bottom of the trenched anode contact  322  in the N epitaxial layer  304 , wherein the n− Schottky barrier height enhancement region  334  has a lower doping concentration than the N epitaxial layer  304 . 
         [0028]      FIG. 6  is another preferred A-B cross section of  FIG. 2C  which has a similar configuration to  FIG. 4 , except that, the trench Schottky rectifier  401  in  FIG. 6  further comprises a p− Schottky barrier height enhancement region  434  surrounding sidewalls and bottom of the trenched anode contact  422  in the N epitaxial layer  404 . 
         [0029]      FIG. 7  is another preferred A-B cross section of  FIG. 2C  which has a similar configuration to  FIG. 2A , except that, the integrated circuit in  FIG. 7  comprises a trench Schottky rectifier  501  having a Schottky barrier layer lined in the trenched anode contact  522  filled with the contact metal plug and disposed between a pair of third type gate trenches  533 . Each the third type gate trench  533  is filled with the single shielded electrode  520  padded by the first type gate oxide  512 , having same conductive material and structure as the trenched gate for shielded electrode contact in the second type gate trenches  508  in the trench MOSFET  500 . Meanwhile, the single shielded electrode  520  in the third type gate trench  533  is connected to the source metal  517 . 
         [0030]    Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.

Technology Category: h