Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention is generally related to hard disk drives, and more particularly to preamplifier write drivers.  
       BACKGROUND OF THE INVENTION  
       [0002]     A recent requirement from all of the disk drive manufacturers is that the preamplifier write driver must now be symmetric. This means that the common-mode output voltage of the write driver must stay around ground over a high frequency pattern. This is driven by head reliability as the new generation of magnetoresistive (MR) heads are much more sensitive to accumulation of differential and single-ended voltages, and the primary mechanism for this damage is capacitive coupling from the write driver.  
         [0003]     Symmetrical writers have been developed to address this problem. While traditional symmetrical writers do reduce the problem substantially compared to traditional write driver architectures, there are several factors that prevent this problem from being minimized even more to the fullest potential. First, the IC process components within the preamplifier are subject to wide variation. In addition, modeling of the entire system (preamplifier write driver, write head, transmission line from write driver to write head) is very complex and subject to errors, both internal and external to the preamplifier. These IC process variations and modeling errors can cause significant deviation from the performance expected through simulation, resulting in excessive asymmetry and coupling to the MR head.  
       SUMMARY OF THE INVENTION  
       [0004]     The present invention achieves technical advantages as a preamplifier write driver having a varying common-mode output voltage. This varying common-mode output voltage also adjusts the derivative of the common-mode voltage, which is proportional to the amount of current coupled onto the MR head through parasitic capacitance. This parasitic capacitance is located mainly along the transmission line and within the read/write head structure itself.  
         [0005]     In one embodiment of the invention, the bottom write driver output devices of the write driver preamplifier are controllably and selectively driven to nominally match and follow the top write driver output devices. In another embodiment of the invention, the top output devices are driven to match and follow the bottom output devices. In both embodiments, top and bottom output device currents are matched to overcome process variations and modeling errors.  
         [0006]     The write driver varies the drive current to the controlled write driver output devices in a programmable fashion through a serial interface. The invention also provides the ability to either increase or decrease the drive to the controlled output devices, which enables the current of the controlled output device to be set in such a way as to counteract effects of process variations and modeling errors in either direction. Advantageously, the drive currents from the top and bottom output devices can be made nearly identical even in the presence of these variations and errors. This advantageously avoids deviations from expected performance as the common-mode voltage is kept close to GND, and the amount of current coupling to the MR head is minimized.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]      FIG. 1  is an electrical schematic of one embodiment of the invention; and  
         [0008]      FIG. 2  is an electrical schematic of one embodiment of digitally controlled resistors adapted to select a resistance of resistor R 2 .  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0009]      FIG. 1  shows a preamplier write driver  10  according to the present invention in a symmetrical write driver application. The outputs of the write driver  10  are OUTP and OUTN, which are driven by transistors Q 0 -Q 3  and some impedance match circuitry forming an H-bridge driver circuit. Transistors Q 0  and Q 3  are the top output devices, and transistors Q 1  and Q 2  are the bottom output devices. Transistors Q 1  and Q 2  are driven by respective transresistance amplifiers  12 , which each receive an input current at respective input  14  and drive an output voltage at respective output  16 . The transresistance amplifiers  12  are driven by transistors Q 4  and Q 5 . It is through this path from transistors Q 4 , Q 5  to the respective transresistance amplifiers  12  to transistors Q 1 , Q 2  that the bottom output devices, transistors Q 1 , Q 2 , are driven to match and follow the top output devices, transistors Q 0 , Q 3 .  
         [0010]     As mentioned earlier, the principles of the first embodiment described here applies in a second embodiment (opposite situation) where the top output devices transistors Q 0 , Q 3  are driven to match and follow the bottom output devices, transistors Q 1 , Q 2 .  
         [0011]     For power savings, the current output from transistors Q 4  and Q 5  to respective inputs  14  can be reduced compared to the current output Q 0  and Q 3 , with the transresistance amplifiers  12  providing gain such that the currents of transistors Q 1  and Q 2  are identical to the currents of transistors Q 0  and Q 3 . Transistors Q 4 , Q 0 , Q 3 , and Q 5  are driven by the write data input voltages VINN and VINP.  
         [0012]     In one aspect of the invention, a key component in  FIG. 1  is the variable resistor R 2 . By increasing the resistance value of resistor R 2 , the drive current to the bottom output devices, transistors Q 1  and Q 2  is reduced. By reducing the value of resistor R 2 , the drive current to the bottom output devices, transistors Q 1  and Q 2 , is increased. The present invention advantageously compensates for and counteracts the effects of IC process variations and modeling errors allowing the drive currents from the top output devices (Q 0 ,Q 3 ) and the bottom output devices (Q 1 ,Q 2 ) to be nearly identical, even in the presence of these variations and errors. This, in turn, keeps the common-mode voltage close to GND, and minimizes the amount of coupling to the MR head.  
         [0013]      FIG. 2  shows one implementation used to make resistor R 2  variable. This is just one possible implementation. SYM 1 , SYM 0  are CMOS digital signals from a preamplifier serial interface (not shown, and these 2 bits of programmability provide 4 different resistance values for resistor R 2 . This number of bits is arbitrary and could be set higher if desired for more selectivity of the resistor R 2  resistance value. The programmable bits SYM 1 , SYM 0  control the respective PMOS devices transistors M 0  and M 1 , which are in series with resistors R 3  and R 4 , respectively. If a high voltage is placed on transistor M 0 &#39;s gate (or M 1 ), then transistor M 0  (or M 1 ) is turned off and resistor R 3  (or R 4 ) is not placed in parallel with resistor R 2 ′, leaving the overall resistance unchanged. When a low voltage is placed on transistor M 0 &#39;s gate (or M 1 ), then transistor M 0  (or M 1 ) is turned on which places resistor R 3  (or R 4 ) in parallel with resistor R 2 ′. This selective enabling of transistors M 0  and M 1  changes the overall resistance of the resistor R 2  and provides the ability for selecting variable resistance. The default power-up value of bits SYM 1 , SYM 0  is low. Thus, upon resistor power up, transistor M 1  is off and transistor M 0  is on, which places resistor R 3  in parallel with resistor R 2 . Having the nominal default resistance include a programmable path that is on allows the overall resistance to be varied in either direction should the common-mode voltage or coupling need to be adjusted due to process variations or modeling errors. With transistor M 1  off in the default state, turning transistor M 0  off by programming bit SYM 1  high increases the overall resistance. With transistor M 0  on in the default state, turning transistor M 1  on by programming bit SYM 0  high decreases the overall resistance. The last remaining state is when both bits SYM 0  and SYM 1  are programmed high. The values of resistors R 4  and R 3  can be chosen such that one has a greater effect than the other, providing an even spread of 4 different possible programmable values.  
         [0014]     There are 3 states that each write data input voltage will cycle through continuously. These states are off, overshoot (pulse), and settled DC write data. When one input write data voltage is in the off state, the other will go through the overshoot and settled DC write data states. The point is that there is AC performance as well as DC performance, with the AC performance having more importance since this is when the coupling to the MR head will occur. The invention described here affects both AC and DC performance, since both AC (overshoot) and DC (settled) current flow through variable resistor R 2  and transistors Q 4  and Q 5  to drive the bottom output devices.  
         [0015]     Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.

Technology Category: h