Patent Document

BACKGROUND OF THE INVENTION 
   1. Field of Invention 
   The present invention relates to a fin field effect transistors (FinFETs) and a method for manufacturing the FinFETs. More particularly, the present invention relates to a FinFET with a fully silicidated gate electrode and a method for manufacturing thereof. 
   2. Description of Related Art 
   FinFETs have been demostrated to have better scalibility than traditional bulk transistors. Generally, the operations of digital circuit depend on the ability to switch MOS devices from an ON state to an OFF state and vice versa. If the threshold voltage for N-type MOS is not much difference from that for P-type MOS even the margin of the ON and OFF state of the N-type MOS seriously overlap with that of the P-type MOS under general operating current, the circuit will be malfunction under specific operating voltage range. 
     FIG. 1  shows the Id-Vg (drain current versus gate voltage) plots for the conventional FinFETs. It is well known in the art that while a positive voltage, which is higher than the threshold voltage of the N-type MOS, is applied on the gate of the N-type MOS, an N-channel is formed under the gate and between the source and drain, and then the N-type MOS is turned on under a proper bias. Similarly, while a negative voltage, which is lower than the threshold voltage of the P-type MOS, is applied on the gate of the P-type MOS, a P-channel is formed under the gate and between the source and drain, and then the P-type MOS is turned on under a proper bias. However, as shown in  FIG. 1 , while a positive voltage of about 0.25V is applied on the gate, not only the N-type MOS is turned on, but also there is current of about 10 −7  Amp passing through the drain of the P-type MOS. That is, the P-type MOS is also turned on. Similarly, while a negative voltage of about −0.25V is applied on the gate, the P-type MOS is turned on and the N-type MOS is turned on as well. Therefore, it is easily to induce circuit malfunction under this kind of circumstance. Even while the drain current is about of 10 −6 , which is a general drain current under the normal circuit operation, it is also possible to turn on the P-type MOS and the N-type MOS at the same gate voltage. 
   SUMMARY OF THE INVENTION 
   The invention provides a method for manufacturing a fin field effect transistor having a fully silicidated gate electrode. The method is suitable for a substrate having a fin structure, a straddle gate and a source/drain region formed thereon, wherein the straddle gate straddles over the fin structure and the source/drain region is located in a portion of the fin structure exposed by the straddle gate. The method comprises steps of performing a first salicide process to form a first salicide layer on the top of the straddle gate and a second salicide layer on the source/drain region. A dielectric layer is formed over the wafer and then a planarization process is performed to remove a portion of the dielectric layer and the first salicide layer until the surface of the straddle gate is exposed. Moreover, a second salicide process is performed to convert the straddle gate into a fully silicidated gate electrode. 
   The present invention further provides a fin field effect transistor having a fully silicidated gate electrode suitable for a substrate having a fin structure formed thereon. The fin field effect transistors comprises a fully silicidated gate electrode, a source/drain region and a salicide layer. The fully silicidated gate electrode straddles over a portion of the fin structure and the source/drain region is located in the fin structure exposed by the fully silicidated gate electrode and adjacent to the fully silicidated gate electrode. In addition, the salicide layer is located on the source/drain region. 
   Because the straddle gate of the fin field effect transistor is fully silicidated into a fully silicidated gate electrode, the result workfunction of the fin field effect transistor is properly adjusted so that the margin of ON/OFF voltage of the N-type MOS is apparently distinguished from that of the P-type MOS. Therefore, the device having N-type and P-type FinFETs formed by the method according to the present invention possesses relatively better functionality and performance. Hence, the malfunction problem caused by simultaneously turn on both N-type and P-type FinFETs can be overcome. 
   It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
       FIG. 1  shows the Id-Vg (drain current versus gate voltage) plots for the conventional FinFETs. 
       FIGS. 2-3  and  5 - 10  are perspective views showing the steps for manufacturing FinFETs according to one preferred embodiment of the present invention. 
       FIG. 4  is a  3 -D schema of a FinFET. 
       FIG. 4A  is a cross-sectional view along line I-I of  FIG. 4 . 
       FIG. 4B  is a cross-sectional view along line II-II of  FIG. 4 . 
       FIG. 11  shows the Id-Vg (drain current versus gate voltage) plots for the FinFETs according to one embodiment of the present invention. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
   As shown in  FIG. 2 , an initial structure is provided for fabricating FinFETs according to one embodiment of the present invention. The initial structure shown in  FIG. 2  is divided into a region  200   a  and a region  200   b  and comprises a substrate  202 , an insulating layer  204  and a plurality of fin structures. Moreover, in the region  200   a , the fin structure comprises a top cap layer  208  and a raised fin  206   a  with a first conductive type. Similarly, in the region  200   b , the fin structure comprises a top cap layer  208  and a raised fin  206   b  with a second conductive type. Notably, the first conductive type and the second conductive type can be, for example but not limited to, P type and N type, respectively. The method for forming the initial structure comprises the steps of providing a silicon-on-insulating (SOI) material (not shown) including, for example, a bottom Si-containing layer (substrate  202 ), the insulating layer  204  and a top Si-containing layer (not shown). Then, a pattern process is performed to form the fin structures after a dielectric layer (not shown) is formed over the SOI material. The insulating layer  204 , such as buried oxide layer, electrically isolates the bottom Si-containing layer from the top Si-containing layer. The Si-containing layer can be semiconductor material including at least silicon. The semiconductor material can be, example but not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), polysilicon, epitaxial silicon, amorphous silicon and multi-layers formed thereof. Further, the dielectric layer can be, for example, a nitrided thermal oxide layer. Moreover, the pattern process for forming the fin structure comprises the steps of forming a patterned photoresist layer (not shown) over the SOI material and then patterning the dielectric layer and the SOI material until the surface of the insulating layer  204  is exposed to form the raised-undoped fin and the cap layer  208 . Then, a patterned photoresist layer (not shown) is formed over the region  200   b  to expose the region  200   a . Thereafter, an ion implantation process is performed to implant ions with the first conductive type into the raised-undoped fin in the region  200   a  and the raised-undoped fin in region  200   a  is transformed into the fin  206   a . The ions for forming fin  206   a  can be, for example but not limited to, boron ions. Then the patterned photoresist layer is removed. After, a patterned photoresist layer (not shown) is formed over the region  200   a  to expose the region  200   b . Thereafter, an ion implantation process is performed to implant ions with the second conductive type into the raised-undoped fin in the region  200   b  and the raised-undoped fin in region  200   b  is transformed into the fin  206   b . The ions for forming fin  206   b  can be, for example but not limited to, phosphorous ions. Then, the patterned photoresist layer is removed. Before the steps for forming the fin  206   a  and the fin  206   b , it can comprises, for example, a step of forming a sacrificial oxide layer (not shown) on the sidewall of the raised fin to protect the raised-undoped fin from being damaged by subsequent performed implantation process. Thereafter, a gate material layer  210  is formed over the region  200   a  and the region  200   b . The gate material layer  210  can be, for example but not limited to, an undoped polysilicon layer. 
   As shown in  FIG. 3 , a patterned photoresist layer (not shown) is formed over the region  200   b  to expose the region  200   a . An ion implantation process is performed to implant ions with the second conductive type into a portion of the gate material layer  210  in the region  200   a  and transform the portion of the gate material layer  210  into a doped gate material layer  210   a . The ions used in the ion implantation process can be, for example, phosphorous ions. Next, the patterned photoresist layer is removed. After the ion implantation process is performed, it further comprises, for example, a step of annealing process. The annealing process can be, for example, a rapid thermal process performing at temperature of about 850 centigrade for about 20 seconds. 
   A pattern process is performed to pattern the gate material layer  210   a  in region  200   a  and the gate material layer  210  in the region  200   b  to form a straddle gates  212   a  and  212   b , respectively.  FIG. 4  is a 3-D schema of one of FinFETs comprising the straddle gate  212   a / 212   b  and the fin  206   a / 206   b  after the pattern process is performed.  FIG. 4A  is a cross-sectional view along line I-I of  FIG. 4 .  FIG. 4B  is a cross-sectional view along line II-II of  FIG. 4 . 
     FIG. 5  shows the cross-sectional view after the following processes are performed on the structure shown in  FIG. 4B . As shown in  FIG. 5 , a spacer structure  216  is formed on the sidewall constructed by straddle gate  212   a / 212   b  and a cap layer  209 . Simultaneously, a spacer structure  214  is formed on the sidewalls of fin  206   a  and  206   b . The method for forming the spacer structures  216  and  214  comprises the steps of forming an oxide layer (not shown) and a silicon nitride layer (not shown) over the regions  200   a  and  200   b  sequentially and performing an etching process to remove a portion of the silicon nitride layer and the oxide layer to form the spacer structures  214  and  216 . The thickness of the oxide layer can be, for example, of about 80˜100 angstroms and the thickness of the silicon nitride layer can be, for example, of about 500 angstroms. Thereafter, by using the straddle gates  212   a  and  212   b  and spacer structure  216  as a mask, a portion of the cap layer  208  (as shown in  FIG. 4 ) in both regions  200   a  and  200   b  is removed to expose a portion of the fin  206   a  and fin  206   b  (as shown in  FIG. 5 ), wherein the cap layer  208  is converted into the cap layer  209 . A patterned photoresist layer  218  is formed over the region  200   b  to expose the region  200   a . By using the straddle gate  212   a  and the spacer  216  as a mask, an ion implantation process  220  is performed on the region  200   a  to form a source/drain region  222  with the second conductive type in the fin  206   a  and to increase the density of the second conductive type ions in the straddle gate  212   a . Therefore, the straddle gate  212   a  (as shown in  FIG. 5 ) is converted into a straddle gate  212   c  (as shown in  FIG. 6 ). The ion implantation process comprises the steps of implanting phosphorous ions of about 6×10 13  ions/cm 2  and implanting arsenic ions of about 3×10 15  ions/cm 2 , subsequently. 
   As shown in  FIG. 6 , the patterned photoresist layer  218  is removed. Another patterned photoresist layer  224  is formed over the region  200   a  to expose the region  200   b . By using the undoped straddle gate  212   b  and the spacer  216  as a mask, an ion implantation process  226  is performed on the region  200   b  to form a source/drain region  228  with the first conductive type in the fin  206   b  and to convert the undoped straddle gate  212   b  into a straddle gate  230  with the first conductive type. The ion implantation process comprises a step of implanting boron ions of about 5×10 13  ions/cm 2 -3×10 15  ions/cm 2 . 
   As shown in  FIG. 7 , the pattermed photoresist layer  224  is removed. A first salicide process is performed to form a salicide layer  234  on the top of the straddle gates  212   c  and  230  and to form a salicide layer  232  on the source/drain regions  222  and  228 . The first salicide process comprises the steps of forming a metal layer, such as a Nickel layer or a Cobalt layer, over the entire structure and performing silicide sintering to form the salicide layers  232  and  234  and then removing the unreacted metal layer. Thereafter, an isolation dielectric layer  236  is formed over the regions  200   a  and  200   b . The method for forming the isolation dielectric layer  236  comprises, for example but not limited to, the steps of forming an undoped silicon glass, of about 2000 angstroms, made of oxide over the regions  200   a  and  200   b  and forming a phosphosilicate glass of about 5000 angstroms over the regions  200   a  and  200   b . In addition, the isolation dielectric layer  236  can be, for example but not limited to, a composite layer comprising a nitride layer and an oxide layer. Further, the thickness of the nitride layer of the composite layer is of about 380 angstroms. Also, the oxide layer can be, for example but not limited to, an undoped silicate glass (USG) layer with a thickness of about 2000˜4000 angstroms or phosphate silicate glass (PSG) layer or the composition thereof. 
   As shown in  FIG. 8 , a planarization process is performed to remove a portion of the upper isolation dielectric layer  236 , the salicide  234  and a portion of the straddle gates  230  and  212   c . Therefore, the straddle gates  230  and  212   c  are converted into straddle gates  231  and  213 , respectively. Notably, the exposed surfaces of the straddle gates  231  and  213  are treated as fully silicidated reaction windows in the following salicide process. The planarization process can be, for example, a two step chemical mechanical polishing (CMP) process including a first step of oxide polishing and a second step of polysilicon polishing. Furthermore, the planarization process can be, for example but not limited to, a fixed time-mode CMP for performing the polishing process for a pre-determined period of time. 
   As shown in  FIG. 9 , a second salicide process is performed to convert the straddle gates  231  and  213  into fully silicidated gate electrodes  231   a  and  213   a  respectively. The second salicide process, for example but not limited to, comprises the steps of forming a metal layer, such as a Nickel layer or a Cobalt layer, over the entire structure by sputtering and performing a fully silicidation to covert the straddle gates  231  and  213  into fully silicidated gate electrodes  231   a  and  213   a  respectively and then removing the unreacted metal layer. It should be noticed that the fully silicidation comprises the step of performing a thermal process. Therefore, because of the thermal process, the metal atoms can thermally diffuse from the top of the straddle gates  231  and  213  to the bottom of the straddle gates  231  and  213 . Then, the metal atoms fully react with the whole the straddle gates  231  and  213  to convert the straddle gates  231  and  213  into the fully silicidated gate electrodes  231   a  and  213   a  respectively. Furthermore, the thermal process can be, for example but not limited to, a rapid thermal process. Moreover, when the metal layer is a Nickel layer, the temperature for performing the thermal process is of about 450 centigrade. Alternatively, when the metal layer is a Cobalt layer, the temperature for performing the thermal process is of about 750 centigrade. Further, the fully silicidated gate electrodes  231   a  and  213   a  can be, for example but not limited to, a Cobalt fully silicide gate electrode or a Nickel fully silicide gate electrode. In addition, after the unreacted metal layer is removed, another thermal process is performed to further transform the low conductivity metal silicide phase into high conductivity metal silicide phase. 
   As shown in  FIG. 10 , a cap layer  250  is formed over the regions  200   a  and  200   b  to seal the fully silicidated gate electrodes  231   a  and  213   a . The cap layer  250  can be, for example but not limited to, a composite layer comprising a nitride layer and an oxide layer. Further, the thickness of the nitride layer of the composite layer is of about 380 angstroms. Also, the oxide layer can be, for example but not limited to, an undoped silicate glass (USG) layer with a thickness of about 2000˜4000 angstroms or phosphate silicate glass (PSG) layer or the composition thereof. 
   Since the straddle gates  231  and  213  are converted into the fully silicidated gate electrodes  231   a  and  213   a  respectively, the workfunction of the device including both FinFETs formed in regions  200   a  and  200   b  respectively is properly adjusted.  FIG. 11  shows the Id-Vg plots for the FinFETs according to one embodiment of the present invention. As shown in  FIG. 9 , when a negative voltage is applied on the gates, none of the N-type MOS is turned on but only the P-type MOS is turned on. Similarly, when a positive voltage is applied on the gates, only N-type MOS is turned on. Notably, under the normal operating current of about 10 −6  Amp, the margin of ON/OFF voltage of the N-type MOS is apparently distinguished from that of the P-type MOS. Therefore, the device having N-type and P-type FinFETs formed by the method according to the present invention possesses relatively better functionality and performance. Hence, the malfunction problem caused by simultaneously turn on both N-type and P-type FinFETs can be overcome. 
   It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.

Technology Category: 5