Patent Document

CROSS-REFERENCES TO RELATED APPLICATIONS 
     NOT APPLICABLE 
     BACKGROUND OF THE INVENTION 
     This invention relates generally to power semiconductor devices, and more particularly the invention relates to a power semiconductor current limiting device and a method of making same. 
     It is known to protect electrical circuits against high input currents by means of a current limiter. A current limiting device works in series with an electrical circuit, contributing a low serial resistance, R on , below a given specification. When the circuit is overloaded or malfunctioning, such as output short circuit, resulting in a high current mode outside of normal operation, the current limiting device serves to clamp the current flowing through the circuit, I lim , within a given allowance, ΔI lim , until the voltage across the current limiting device exceeds its specified operating limit, V br . When made by the method taught in the present application, the device provides low R on , high I lim , low ΔI lim , and high V br  with a wide range of desired I lim  that is easy to adjust by controlling certain implant energy or dose. FIG. 1 shows these critical parameters in graphical form. 
     The present invention is directed to a current limiting device having improved current-voltage characteristics including a lower R on , higher I lim , lower±ΔI lim , and higher V br . 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with the invention, a vertical MOS current limiting device has a modified dopant implant. More particularly, in one embodiment serial resistance, R on , can be controlled by a shallow P dopant implant and the current limit, I lim , can be controlled by a deeper P-dopant implant. The current limiting function is achieved by the overlap of depletion regions by biasing the P-dopant implanted regions. 
     The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a graph illustrating current—voltage characteristics of a current limiting device. 
     FIG. 2 is a section view illustrating a conventional double-diffused MOSFET (DMOSFET) that can be used as power MOSFET. 
     FIG. 3 is a section view illustrating a triple-diffused current limiting device in accordance with the invention. 
     FIGS. 4-17 are section views illustrating steps in fabricating a current limiting device in accordance with embodiments of the invention. 
     FIGS. 18-23 are top views illustrating alternative configurations of the cells and plugs in a device in accordance with the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In accordance with the invention, a vertical MOS current limiting structure has a modified P-dopant implant to control forward limiting current. Specifically, the serial resistance R on  can be controlled by a shallow P-dopant implant, and the current limits, I lim , can be controlled by a deep P-dopant implant with a dopant profile minimizing the current limit allowance, ΔI lim . 
     FIG. 2 is a section view illustrating the doping profile of a standard DMOSFET. Note that the P-type doping profile is formed through a first diffusion, and the separation of the P-region increases monotonically below the device surface. Hence, the channel requires higher voltage to pinch. Further, the current pinch is softer and results in higher allowance for current limit. 
     FIG. 3 is a section view of a MOS current limiting device in accordance with the invention illustrating the unique P-dopant profile created by a double P-dopant (e.g. boron) implantation at different dose, energy and/or angle of implantation. The pinching of the conduction channel is achieved at a lower voltage, and the pinching is harder, thus resulting in a superior current limiter. 
     Consider now steps in fabricating a current limiting device in accordance with the invention as illustrated in the section views of FIGS. 4-17. As shown in FIG. 4, the starting material is an N+substrate  100  including an N-epitaxial layer  102  with a field oxide  104  grown or deposited to a thickness of about 300-1,000 microns. In FIG. 5, a photoresist pattern  106  is formed to define the guard ring and plug areas. The exposed field oxide  104  is then etched and boron is implanted at  108 . Thereafter, as shown in FIG. 6, the photoresist  106  is removed and boron  108  is driven in to form deep P-regions  108  for the guard ring and plugs. A BF 2  implant for high surface concentration is then made to form good ohmic contacts, followed by rapid thermal annealing to activate the BF 2  dopant. 
     In FIG. 7, a photoresist pattern  112  is formed to expose the active area so that the field oxide  104  can be removed as shown in FIG.  8 . Thereafter, as shown in FIG. 9, photoresist  112  is removed and a 3-50 nm gate oxide  114  is grown and thereafter 10-100 nm of in-situ doped polysilicon or undoped polysilicon with implant is deposited. This polysilicon layer is optional if a metal gate MOS cell structure is acceptable. A 0.25-3 micron wide photoresist pattern  116  is then formed to define MOS cell units followed by removal of the exposed polysilicon and gate oxide. The removal of the gate oxide can be delayed until after steps  11 A and  11 B, infra. 
     Thereafter, as shown in FIG. 10, a deep boron implant forms regions  118  extending from the guard ring and plugs, which are therefore all electrically connected. The boron implant energy must be high enough to cause some lateral scattering or alternatively the implant can be executed at an angle. Following this step, the steps of FIGS. 11A-12A or alternatively the steps of  11 B- 12 B are carried out. In FIG. 11A, a four-way or continuous rotation angled (0°-50°) shallow boron implant is made to create regions  120 , which contact regions  118 , and for threshold voltage adjustment. For higher current devices, this implant is not necessary. 
     In FIG. 12A the exposed gate oxide is etched, if not done so in FIG. 9, and then optional photoresist  121  is formed to cover the guard ring and plug areas. Photoresist  116  can also be removed prior to formation of photoresist  121 . An N-type dopant (arsenic) is then implanted in a portion of regions  120  of sufficient concentration to form a good ohmic contact. If photoresist  121  is not formed, the arsenic dose should be about one order of magnitude lower than the BF 2  implant dose so that the net surface concentration in the guard ring and the plug area is still P+ with a value that is high enough to form a good P-type ohmic contact. 
     As an alternative to steps  11 A and  12 A, steps  11 B and  12 B can be utilized. In FIG. 11B an isotropic O 2  plasma etch is applied to remove about 0-300 nm of hotoresist  116 , and then shallow boron implants create the regions  120  and for a threshold voltage adjustment. Next, as shown in FIG. 12B, the exposed gate oxide is etched if not done in FIG. 9, and then an optional photoresist  122  is patterned to cover the guard ring and plug areas. Photoresist  116  can be removed also prior to formation of photoresist  122 . Arsenic is implanted in a portion of regions  120  with a sufficient dosage to form a good P-type ohmic contact. If photoresist  122  is not formed, again, the arsenic dosage should be about one order of magnitude lower than the BF 2  implant dosage so that the net service concentration in the guard and plug area is still P+ with a value that is high enough to form a good P-type ohmic contact. 
     Thereafter, as shown in FIG. 13, the photoresist is removed and rapid thermal annealing is employed to activate all implant, including the N+ regions  124 . Alternatively, separate thermal annealing can be applied after each individual implant. The steps of FIGS. 12A and 12B will result in a similar doping profile after activation. 
     In FIG. 14 a 10-70 nm optional layer of oxide or nitride or polysilicon is deposited and then anisotropically etched to form spacers  126 . Thereafter, as shown in FIG. 15, a top electrode  128  is formed in ohmic contact with guard ring and plugs  108 , N+ regions  124 , and gate  115 . Similarly, a bottom electrode  130  is formed on the surface of substrate  100 . The materials for the top and bottom electrodes can be a refractory metal such as Ti, W, Ni, or other ohmic materials such Ag, Au, Cu, and Al, for example, or combinations of two or more materials. 
     FIGS. 16 and 17 illustrate current flow through the device with a forward bias and with a reverse bias, respectively. In FIG. 19, the forward bias increases the depletion  130  to pinch-off, thus limiting current flow, and limiting the ΔI lim , and increasing V br , The forward bias illustrated in FIG. 17 limits the current. 
     FIGS. 18-23 are top views of the finished device showing alternative arrangements. In FIG. 18 the unit cells  24  are hexagonal, in FIGS. 19 and 22 the unit cells are stripes, and in FIGS. 20-22, the plugs  30  comprise a grid between groupings of unit cells  24 . 
     The boron doping profile to provide a higher dopant concentration within the device body and spaced from the overlying P-doped channel region enhances device current-voltage characteristics by facilitating pinch-of of the current path. 
     While the invention has been described with reference to specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true and scope of the invention as defined by the appended claims.

Technology Category: 5