Patent Document

RELATED APPLICATIONS 
       [0001]    This application is a continuation application of U.S. patent application Ser. No. 14/607,783, filed Jan. 28, 2015, which is a continuation application of U.S. patent application Ser. No. 14/469,107, filed Aug. 26, 2014, now U.S. Pat. No. 9,029,923, which is a continuation of U.S. patent application Ser. No. 14/177,459, filed Feb. 11, 2014, now U.S. Pat. No. 8,823,066, which is a divisional patent application of U.S. patent application Ser. No. 13/891,655, filed May 10, 2013, now U.S. Pat. No. 8,697,511, which claims benefit pursuant to 35 U.S.C. §119(e) of U.S. Provisional Patent Application Ser. No. 61/648,817, filed May 18, 2012. The entire contents of which are hereby incorporated by reference. 
     
    
     BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    Semiconductor integrated circuits, in particular, integrated circuits that use MOS transistors, are becoming more and more highly integrated. As the circuits achieve higher integration, the size of MOS transistors used therein is reduced to a nanometer range. With smaller MOS transistors, it sometimes becomes difficult to suppress leak current and to decrease the area occupied by the circuit since a particular amount of current is required. Under these circumstances, a surrounding gate transistor (hereinafter referred to as SGT), which includes a source, a gate, and a drain arranged in perpendicular to a substrate, the gate surrounding a pillar-shaped semiconductor layer, has been proposed (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761). 
         [0006]    Using a metal in the gate electrode instead of polysilicon helps suppress depletion and decrease the resistance of the gate electrode. However, this requires a production process that always takes into account metal contamination caused by the metal gate in the steps subsequent to formation of the metal gate. 
         [0007]    To produce existing MOS transistors, a metal-gate-last process in which a metal gate is formed after a high temperature process is put into practice so as to avoid incompatibility between the metal gate process and the high temperature process (for example, refer to A 45 nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-free Packaging, IEDM2007 K. Mistry et. al, pp 247-250). 
         [0008]    That is, a MOS transistor has been made by forming a gate with polysilicon, depositing an interlayer insulating film on the polysilicon, exposing the polysilicon gate by chemical mechanical polishing (CMP), etching the polysilicon gate, and depositing a metal. In order to avoid incompatibility between the metal gate process and the high temperature process, it is also necessary for producing a SGT to employ a metal-gate-last process with which a metal gate is formed after a high temperature process. Since the upper part of a pillar-shaped silicon layer of a SGT is located at a position higher than the gate, some adjustment must be made in employing the metal-gate-last process. 
         [0009]    An existing MOS transistor uses a first insulating film in order to decrease the parasitic capacitance between the gate line and the substrate. For example, in making a FINFET (refer to High performance 22/20 nm FinFET CMOS devices with advanced high-K/metal gate scheme, IEDM2010, CC. Wu, et. al, 27.1.1-27.1.4, for example), a first insulating film is formed around one fin-shaped semiconductor layer and then etched back so as to expose the fin-shaped semiconductor layer and to decrease the parasitic capacitance between the gate line and the substrate. In making a SGT also, a first insulating film is needed to reduce the parasitic capacitance between the gate line and the substrate. Since a SGT includes not only a fin-shaped semiconductor layer but also a pillar-shaped semiconductor layer, some adjustment must be made in order to form a pillar-shaped semiconductor layer. 
         [0010]    According to a known SGT manufacturing process, a contact hole for a pillar-shaped silicon layer is formed by etching through a mask and then contact holes for a gate line and a planar silicon layer are formed by etching through a mask (for example, refer to Japanese Unexamined Patent Application Publication No. 2011-258780). That is, conventionally, two masks have been used for forming contacts. 
       SUMMARY 
       [0011]    The present invention has been made under the above-described circumstances. An object of the present invention is to provide a semiconductor device having reduced parasitic capacitance between a gate line and a substrate. 
         [0012]    A method for producing a semiconductor device according to a first aspect of the present invention includes: 
         [0013]    a first step of forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer so that a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer; 
         [0014]    the second step of implanting an impurity to an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer to form diffusion layers, the second step being performed after the first step; 
         [0015]    the third step of forming a gate insulating film, a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad so that the gate insulating film covers the periphery and an upper portion of the pillar-shaped silicon layer and the polysilicon gate electrode covers the gate insulating film, that, after the formation of the polysilicon gate electrode, the polysilicon gate line, and the polysilicon gate pad, an upper surface of the polysilicon is located at a position higher than the gate insulating film located on the diffusion layer in the upper portion of the pillar-shaped silicon layer, and that the width of the polysilicon gate electrode and the width of the polysilicon gate pad are larger than the width of the polysilicon gate line, the third step being performed after the second step; 
         [0016]    the fourth step of forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer, the fourth step being performed after the third step; 
         [0017]    the fifth step of depositing an interlayer insulating film, exposing the polysilicon gate electrode, polysilicon gate line, and the polysilicon gate pad, and etching the polysilicon gate electrode, polysilicon gate line, and the polysilicon gate pad, and depositing a metal layer so as to form a metal gate electrode, a metal gate line, and a metal gate pad, the metal gate line extending in a direction perpendicular to the fin-shaped silicon layer and being connected to the metal gate electrode, the fifth step being performed after the fourth step; and 
         [0018]    the sixth step of forming a contact directly connected to the diffusion layer in the upper portion of the pillar-shaped silicon layer, the sixth step being performed after the fifth step. 
         [0019]    Preferably, a first resist for forming the fin-shaped silicon layer on the silicon substrate is formed, the silicon substrate is etched by using the first resist so as to form the fin-shape silicon layer, and then the first resist is removed. 
         [0020]    Preferably, the first insulating film is deposited around the fin-shaped silicon layer and the first insulating film is etched back to expose the upper portion of the fin-shaped silicon layer. 
         [0021]    Preferably, a second resist is formed so as to perpendicularly intersect the fin-shaped silicon layer, the fin-shaped silicon layer is etched by using the second resist, and the second resist is removed so that the part where the fin-shaped silicon layer and the second resist intersect forms the pillar-shaped silicon layer. 
         [0022]    Preferably, a second oxide film is deposited from above a structure that includes the fin-shaped silicon layer formed on the silicon substrate, the first insulating film formed around the fin-shaped silicon layer, and the pillar-shaped silicon layer formed in the upper portion of the fin-shaped silicon layer, a first nitride film is formed on the second oxide film, and the first nitride film is etched so as to be left as a sidewall. 
         [0023]    Preferably, an impurity is then implanted so as to form the diffusion layers in the upper portion of the pillar-shaped silicon layer and the upper portion of the fin-shaped silicon layer, the first nitride film and the second oxide film are removed, and then a heat-treatment is performed. 
         [0024]    In a structure that includes the fin-shaped silicon layer formed on the silicon substrate, the first insulating film formed around the fin-shaped silicon layer, the pillar-shaped silicon layer formed in the upper portion of the fin-shaped silicon layer, the diffusion layer formed in the upper portion of the fin-shaped silicon layer and the lower portion of the pillar-shaped silicon layer, and the diffusion layer formed in the upper portion of the pillar-shaped silicon layer, 
         [0025]    preferably, a gate insulating film is formed, polysilicon is deposited and planarized, and an upper surface of the planarized polysilicon is located at a position higher than the gate insulating film on the diffusion layer in the upper portion of the pillar-shaped silicon layer; and 
         [0026]    preferably, a second nitride film is deposited, a third resist for forming the polysilicon gate electrode, the polysilicon gate line, and the polysilicon gate pad is formed, the second nitride film and the polysilicon are etched by using the third resist so as to form the polysilicon gate electrode, the polysilicon gate line, and the polysilicon gate pad, the gate insulating film is etched, and then the third resist is removed. 
         [0027]    Preferably, a third nitride film is deposited and etched so as to be left as a sidewall, a metal layer is deposited, and a silicide is formed in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer. 
         [0028]    Preferably, a fourth nitride film is deposited, an interlayer insulating film is deposited and planarized, the polysilicon gate electrode, the polysilicon gate line, and the polysilicon gate pad are exposed, the polysilicon gate electrode, the polysilicon gate line, and the polysilicon gate pad are removed, and spaces where the polysilicon gate electrode, the polysilicon gate line, and the polysilicon gate pad had existed are filled with a metal, and the metal is etched to expose the gate insulating film on the diffusion layer in the upper portion of the pillar-shaped silicon layer and to form the metal gate electrode, the metal gate line, and the metal gate pad. 
         [0029]    Preferably, a fifth nitride film thicker than a half of the width of the polysilicon gate line and thinner than a half of the width of the polysilicon gate electrode and a half of the width of the polysilicon gate pad is deposited to form contact holes on the pillar-shaped silicon layer and the metal gate pad. 
         [0030]    A semiconductor device according to a second aspect of the present invention includes a fin-shaped silicon layer on a silicon substrate;
       a first insulating film around the fin-shaped silicon layer;   a pillar-shaped silicon layer on the fin-shaped silicon layer, a width of the pillar-shaped silicon layer being equal to a width of the fin-shaped silicon layer;   a first diffusion layer in an upper portion of the fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer;   a second diffusion layer in an upper portion of the pillar-shaped silicon layer;   a gate insulating film around the pillar-shaped silicon layer;   a metal gate electrode around the gate insulating film;   a metal gate line extending in a direction perpendicular to the fin-shaped silicon layer and connected to the metal gate electrode;   a metal gate pad connected to the metal gate line;   a contact on the metal gate line; and   a nitride film on an entire top surface of the metal gate electrode and the metal gate line except the bottom of the contact   and a nitride film on the sidewall of the metal gate electrode and gate line;   wherein a verticle thickness of the nitride film on the entire top surface of the metal gate electrode and the metal gate line relative to the substrate is greater than a horizontal thickness of the nitride film on the sidewall of the metal gate electrode and gate line relative to the substrate, and   wherein a height of the top surface of the metal gate electrode is equal to a height of the top surface of the metal gate line relative to the substrate.       
 
         [0044]    According to the present invention, a method for producing a semiconductor device, the method being a gate-last process capable of reducing the parasitic capacitance between the gate line and the substrate and a semiconductor device produced through this method can be provided. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0045]      FIG. 1A  is a plan view of a semiconductor device according to the present invention,  FIG. 1B  is a cross-sectional view taken along line X-X′ in  FIG. 1A , and  FIG. 1C  is a cross-sectional view taken along line Y-Y′ in  FIG. 1A ; 
           [0046]      FIG. 2A  is a plan view of a semiconductor device according to the present invention,  FIG. 2B  is a cross-sectional view taken along line X-X′ in  FIG. 2A , and  FIG. 2C  is a cross-sectional view taken along line Y-Y′ in  FIG. 2A ; 
           [0047]      FIG. 3A  is a plan view of a semiconductor device according to the present invention,  FIG. 3B  is a cross-sectional view taken along line X-X′ in  FIG. 3A , and  FIG. 3C  is a cross-sectional view taken along line Y-Y′ in  FIG. 3A ; 
           [0048]      FIG. 4A  is a plan view of a semiconductor device according to the present invention,  FIG. 4B  is a cross-sectional view taken along line X-X′ in  FIG. 4A , and  FIG. 4C  is a cross-sectional view taken along line Y-Y′ in  FIG. 4A ; 
           [0049]      FIG. 5A  is a plan view of a semiconductor device according to the present invention,  FIG. 5B  is a cross-sectional view taken along line X-X′ in  FIG. 5A , and  FIG. 5C  is a cross-sectional view taken along line Y-Y′ in  FIG. 5A ; 
           [0050]      FIG. 6A  is a plan view of a semiconductor device according to the present invention,  FIG. 6B  is a cross-sectional view taken along line X-X′ in  FIG. 6A , and  FIG. 6C  is a cross-sectional view taken along line Y-Y′ in  FIG. 6A ; 
           [0051]      FIG. 7A  is a plan view of a semiconductor device according to the present invention,  FIG. 7B  is a cross-sectional view taken along line X-X′ in  FIG. 7A , and  FIG. 7C  is a cross-sectional view taken along line Y-Y′ in  FIG. 7A ; 
           [0052]      FIG. 8A  is a plan view of a semiconductor device according to the present invention,  FIG. 8B  is a cross-sectional view taken along line X-X′ in  FIG. 8A , and  FIG. 8C  is a cross-sectional view taken along line Y-Y′ in  FIG. 8A ; 
           [0053]      FIG. 9A  is a plan view of a semiconductor device according to the present invention,  FIG. 9B  is a cross-sectional view taken along line X-X′ in  FIG. 9A , and  FIG. 9C  is a cross-sectional view taken along line Y-Y′ in  FIG. 9A ; 
           [0054]      FIG. 10A  is a plan view of a semiconductor device according to the present invention,  FIG. 10B  is a cross-sectional view taken along line X-X′ in  FIG. 10A , and  FIG. 10C  is a cross-sectional view taken along line Y-Y′ in  FIG. 10A ; 
           [0055]      FIG. 11A  is a plan view of a semiconductor device according to the present invention,  FIG. 11B  is a cross-sectional view taken along line X-X′ in  FIG. 11A , and  FIG. 11C  is a cross-sectional view taken along line Y-Y′ in  FIG. 11A ; 
           [0056]      FIG. 12A  is a plan view of a semiconductor device according to the present invention,  FIG. 12B  is a cross-sectional view taken along line X-X′ in  FIG. 12A , and  FIG. 12C  is a cross-sectional view taken along line Y-Y′ in  FIG. 12A ; 
           [0057]      FIG. 13A  is a plan view of a semiconductor device according to the present invention,  FIG. 13B  is a cross-sectional view taken along line X-X′ in  FIG. 13A , and  FIG. 13C  is a cross-sectional view taken along line Y-Y′ in  FIG. 13A ; 
           [0058]      FIG. 14A  is a plan view of a semiconductor device according to the present invention,  FIG. 14B  is a cross-sectional view taken along line X-X′ in  FIG. 14A , and  FIG. 14C  is a cross-sectional view taken along line Y-Y′ in  FIG. 14A ; 
           [0059]      FIG. 15A  is a plan view of a semiconductor device according to the present invention,  FIG. 15B  is a cross-sectional view taken along line X-X′ in  FIG. 15A , and  FIG. 15C  is a cross-sectional view taken along line Y-Y′ in  FIG. 15A ; 
           [0060]      FIG. 16A  is a plan view of a semiconductor device according to the present invention,  FIG. 16B  is a cross-sectional view taken along line X-X′ in  FIG. 16A , and  FIG. 16C  is a cross-sectional view taken along line Y-Y′ in  FIG. 16A ; 
           [0061]      FIG. 17A  is a plan view of a semiconductor device according to the present invention,  FIG. 17B  is a cross-sectional view taken along line X-X′ in  FIG. 17A , and  FIG. 17C  is a cross-sectional view taken along line Y-Y′ in  FIG. 17A ; 
           [0062]      FIG. 18A  is a plan view of a semiconductor device according to the present invention,  FIG. 18B  is a cross-sectional view taken along line X-X′ in  FIG. 18A , and  FIG. 18C  is a cross-sectional view taken along line Y-Y′ in  FIG. 18A ; 
           [0063]      FIG. 19A  is a plan view of a semiconductor device according to the present invention,  FIG. 19B  is a cross-sectional view taken along line X-X′ in  FIG. 19A , and  FIG. 19C  is a cross-sectional view taken along line Y-Y′ in  FIG. 19A ; 
           [0064]      FIG. 20A  is a plan view of a semiconductor device according to the present invention,  FIG. 20B  is a cross-sectional view taken along line X-X′ in  FIG. 20A , and  FIG. 20C  is a cross-sectional view taken along line Y-Y′ in  FIG. 20A ; 
           [0065]      FIG. 21A  is a plan view of a semiconductor device according to the present invention,  FIG. 21B  is a cross-sectional view taken along line X-X′ in  FIG. 21A , and  FIG. 21C  is a cross-sectional view taken along line Y-Y′ in  FIG. 21A ; 
           [0066]      FIG. 22A  is a plan view of a semiconductor device according to the present invention,  FIG. 22B  is a cross-sectional view taken along line X-X′ in  FIG. 22A , and  FIG. 22C  is a cross-sectional view taken along line Y-Y′ in  FIG. 22A ; 
           [0067]      FIG. 23A  is a plan view of a semiconductor device according to the present invention,  FIG. 23B  is a cross-sectional view taken along line X-X′ in  FIG. 23A , and  FIG. 23C  is a cross-sectional view taken along line Y-Y′ in  FIG. 23A ; 
           [0068]      FIG. 24A  is a plan view of a semiconductor device according to the present invention,  FIG. 24B  is a cross-sectional view taken along line X-X′ in  FIG. 24A , and  FIG. 24C  is a cross-sectional view taken along line Y-Y′ in  FIG. 24A ; 
           [0069]      FIG. 25A  is a plan view of a semiconductor device according to the present invention,  FIG. 25B  is a cross-sectional view taken along line X-X′ in  FIG. 25A , and  FIG. 25C  is a cross-sectional view taken along line Y-Y′ in  FIG. 25A ; 
           [0070]      FIG. 26A  is a plan view of a semiconductor device according to the present invention,  FIG. 26B  is a cross-sectional view taken along line X-X′ in  FIG. 26A , and  FIG. 26C  is a cross-sectional view taken along line Y-Y′ in  FIG. 26A ; 
           [0071]      FIG. 27A  is a plan view of a semiconductor device according to the present invention,  FIG. 27B  is a cross-sectional view taken along line X-X′ in  FIG. 27A , and  FIG. 27C  is a cross-sectional view taken along line Y-Y′ in  FIG. 27A ; 
           [0072]      FIG. 28A  is a plan view of a semiconductor device according to the present invention,  FIG. 28B  is a cross-sectional view taken along line X-X′ in  FIG. 28A , and  FIG. 28C  is a cross-sectional view taken along line Y-Y′ in  FIG. 28A ; 
           [0073]      FIG. 29A  is a plan view of a semiconductor device according to the present invention,  FIG. 29B  is a cross-sectional view taken along line X-X′ in  FIG. 29A , and  FIG. 29C  is a cross-sectional view taken along line Y-Y′ in  FIG. 29A ; 
           [0074]      FIG. 30A  is a plan view of a semiconductor device according to the present invention,  FIG. 30B  is a cross-sectional view taken along line X-X′ in  FIG. 30A , and  FIG. 30C  is a cross-sectional view taken along line Y-Y′ in  FIG. 30A ; 
           [0075]      FIG. 31A  is a plan view of a semiconductor device according to the present invention,  FIG. 31B  is a cross-sectional view taken along line X-X′ in  FIG. 31A , and  FIG. 31C  is a cross-sectional view taken along line Y-Y′ in  FIG. 31A ; 
           [0076]      FIG. 32A  is a plan view of a semiconductor device according to the present invention,  FIG. 32B  is a cross-sectional view taken along line X-X′ in  FIG. 32A , and  FIG. 32C  is a cross-sectional view taken along line Y-Y′ in  FIG. 32A ; 
           [0077]      FIG. 33A  is a plan view of a semiconductor device according to the present invention,  FIG. 33B  is a cross-sectional view taken along line X-X′ in  FIG. 33A , and  FIG. 33C  is a cross-sectional view taken along line Y-Y′ in  FIG. 33A ; 
           [0078]      FIG. 34A  is a plan view of a semiconductor device according to the present invention,  FIG. 34B  is a cross-sectional view taken along line X-X′ in  FIG. 34A , and  FIG. 34C  is a cross-sectional view taken along line Y-Y′ in  FIG. 34A ; 
           [0079]      FIG. 35A  is a plan view of a semiconductor device according to the present invention,  FIG. 35B  is a cross-sectional view taken along line X-X′ in  FIG. 35A , and  FIG. 35C  is a cross-sectional view taken along line Y-Y′ in  FIG. 35A ; 
           [0080]      FIG. 36A  is a plan view of a semiconductor device according to the present invention,  FIG. 36B  is a cross-sectional view taken along line X-X′ in  FIG. 36A , and  FIG. 36C  is a cross-sectional view taken along line Y-Y′ in  FIG. 36A ; 
           [0081]      FIG. 37A  is a plan view of a semiconductor device according to the present invention,  FIG. 37B  is a cross-sectional view taken along line X-X′ in  FIG. 37A , and  FIG. 37C  is a cross-sectional view taken along line Y-Y′ in  FIG. 37A ; 
           [0082]      FIG. 38A  is a plan view of a semiconductor device according to the present invention,  FIG. 38B  is a cross-sectional view taken along line X-X′ in  FIG. 38A , and  FIG. 38C  is a cross-sectional view taken along line Y-Y′ in  FIG. 38A ; and 
           [0083]      FIG. 39A  is a plan view of a semiconductor device according to the present invention,  FIG. 39B  is a cross-sectional view taken along line X-X′ in  FIG. 39A , and  FIG. 39C  is a cross-sectional view taken along line Y-Y′ in  FIG. 39A . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0084]    A method for producing a semiconductor device according to an embodiment of the present invention and a semiconductor device obtained by the method will now be described with reference to drawings. 
         [0085]    A production method that includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer is described below. 
         [0086]    First, as shown in  FIGS. 2A-2C , a first resist  102  for forming a fin-shaped silicon layer is formed on a silicon substrate  101 . 
         [0087]    Next, as shown in  FIGS. 3A-3C , the silicon substrate  101  is etched to form a fin-shaped silicon layer  103 . Although a fin-shaped silicon layer is formed by using a resist as a mask here, a hard mask such as an oxide film or a nitride film may be used instead of the resist. 
         [0088]    Next, as shown in  FIGS. 4A-4C , the first resist  102  is removed. 
         [0089]    Then, as shown in  FIGS. 5A-5C , a first insulating film  104  composed of an oxide is formed around the fin-shaped silicon layer  103  by deposition. The first insulating film may be an oxide film formed by a high-density plasma process or an oxide film formed by a low-pressure chemical vapor deposition process instead of one made by such a deposition method. 
         [0090]    As shown in  FIGS. 6A-6C , the first insulating film  104  is etched back to expose an upper portion of the fin-shaped silicon layer  103 . The process up to here is the same as the process of making a fin-shaped silicon layer in PTL 2. 
         [0091]    As shown in  FIGS. 7A-7C , a second resist  105  is formed to perpendicularly intersect the fin-shaped silicon layer  103 . The part where the fin-shaped silicon layer  103  and the second resist  105  intersect forms a pillar-shaped silicon layer. Since a line-shaped resist can be used as such, the possibility of the break of the resist after formation of a pattern is low and the process becomes stable. 
         [0092]    Then, as shown in  FIGS. 8A-8C , the fin-shaped silicon layer  103  is shaped by etching. As a result, the part where the fin-shaped silicon layer  103  and the second resist  105  intersect forms a pillar-shaped silicon layer  106 . Accordingly, the width of the pillar-shaped silicon layer  106  is equal to the width of the fin-shaped silicon layer  103 . As a result, a structure in which the pillar-shaped silicon layer  106  is formed in the upper portion of the fin-shaped silicon layer  103  and the first insulating film  104  is formed around the fin-shaped silicon layer  103  is formed. 
         [0093]    As shown in  FIGS. 9A-9C , the second resist  105  is removed. 
         [0094]    A method for forming diffusion layers by implanting an impurity into an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer is described below. 
         [0095]    That is, as shown in  FIGS. 10A-10C , a second oxide film  107  is formed by deposition and a first nitride film  108  is formed. In order to prevent the impurity from being implanted into the sidewall of the pillar-shaped silicon layer, the first nitride film  108  need be formed only on the sidewall of the pillar-shaped silicon layer so as to have a sidewall shape. Since the upper part of the pillar-shaped silicon layer will be covered with a gate insulating film and a polysilicon gate electrode in the subsequent steps, it is desirable to form a diffusion layer in the upper portion of the pillar-shaped silicon layer before the pillar-shaped silicon layer is covered as such. 
         [0096]    Then, as shown in  FIGS. 11A-11C , the first nitride film  108  is etched so as to be left as a sidewall. 
         [0097]    Next, as shown in  FIGS. 12A-12C , an impurity such as arsenic, phosphorus, or boron is implanted to form a diffusion layer  110  in the upper portion of the pillar-shaped silicon layer and diffusion layers  109  and  111  in the upper portion of the fin-shaped silicon layer  103 . 
         [0098]    Then, as shown in  FIGS. 13A-13C , the first nitride film  108  and the second oxide film  107  are removed. 
         [0099]    Referring now to  FIGS. 14A-14C , a heat-treatment is performed. The diffusion layers  109  and  111  in the upper portion of the fin-shaped silicon layer  103  come into contact with each other so as to form a diffusion layer  112 . As a result of the above-described steps, an impurity is implanted into the upper portion of the pillar-shaped silicon layer  106 , the upper portion of the fin-shaped silicon layer  103 , and the lower portion of the pillar-shaped silicon layer  106  so as to form the diffusion layers  110  and  112 . 
         [0100]    A method for preparing a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad by using polysilicon will now be described. According to this method, an interlayer insulating film is first deposited and then a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad are exposed by chemical mechanical polishing (CMP). Thus, it is essential that the upper portion of the pillar-shaped silicon layer remain unexposed despite CMP. 
         [0101]    In other words, as shown in  FIGS. 15A-15C , a gate insulating film  113  is formed, a polysilicon  114  is deposited, and the surface thereof is planarized. The upper surface of the polysilicon  114  after planarization is to come at a position higher than the gate insulating film  113  on the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106 . In this manner, the upper portion of the pillar-shaped silicon layer can remain unexposed despite CMP, during which a polysilicon gate electrode  114   a,  a polysilicon gate line  114   b,  and a polysilicon gate pad  114   c  become exposed and which is performed after deposition of the interlayer insulating film. 
         [0102]    Next, a second nitride film  115  is deposited. The second nitride film  115  prevents formation of a silicide in the upper portions of the polysilicon gate electrode  114   a,  polysilicon gate line  114   b,  and polysilicon gate pad  114   c  during the process of forming a silicide in the upper portion of the fin-shaped silicon layer  103 . 
         [0103]    Next, as shown in  FIGS. 16A-16C , a third resist  116  for forming the polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c  is formed. The polysilicon gate pad  114   c  is preferably arranged so that the part that forms a gate line perpendicularly intersects the fin-shaped silicon layer  103  in order to decrease the parasitic capacitance between the gate line and the substrate. The width of the polysilicon gate electrode  114   a  and the width of the polysilicon gate pad  114   c  are preferably larger than the width of the polysilicon gate line  114   b.    
         [0104]    Then, as shown in  FIGS. 17A-17C , the second nitride film  115  is formed by etching. 
         [0105]    Then, as shown in  FIGS. 18A-18C , the polysilicon  114  is etched to form the polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c.    
         [0106]    Then, as shown in  FIGS. 19A-19C , the gate insulating film  113  is etched so as to remove the bottom portion of the gate insulating film  113 . 
         [0107]    Then, as shown in  FIGS. 20A-20C , the third resist  116  is removed. 
         [0108]    The polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c  are thus formed through the steps described above. 
         [0109]    The upper surface of the polysilicon after forming the polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c  is located at a position higher than the gate insulating film  113  on the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106 . 
         [0110]    A method for forming a silicide in the upper portion of the fin-shaped silicon layer will now be described. This method is characterized in that no silicide is formed in the upper portions of the polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c,  and the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106 . It is not preferable to form a silicide in the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106  since the number of steps in the method will increase. 
         [0111]    First, as shown in  FIGS. 21A-21C , a third nitride film  117  is deposited. 
         [0112]    Next, as shown in  FIGS. 22A-22C , the third nitride film  117  is etched to be left as a sidewall. 
         [0113]    Then, as shown in  FIGS. 23A-23C , a metal such as nickel or cobalt is deposited to form a silicide  118  in the upper portion of the diffusion layer  112  in the upper portion of the fin-shaped silicon layer  103 . Since the polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c  are covered with the third nitride film  117  and the second nitride film  115  and the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106  is covered with the gate insulating film  113 , the polysilicon gate electrode  114   a,  and the polysilicon gate line  114   b,  no silicide is formed in these parts. 
         [0114]    Through the steps described above, a silicide is formed in the upper portion of the fin-shaped silicon layer  103 . 
         [0115]    Next, a gate-last production process in which, after an interlayer insulating film is deposited on the structure obtained through the steps described above, the polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c  are exposed by CMP and removed by etching and then a metal is deposited is described. 
         [0116]    First, as shown in  FIGS. 24A-24C , a fourth nitride film  119  is deposited to protect the silicide  118 . 
         [0117]    Next, as shown in  FIGS. 25A-25C , an interlayer insulating film  120  is deposited and the surface thereof is planarized by CMP. 
         [0118]    Then, as shown in  FIGS. 26A-26C , the polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c  are exposed by CMP. 
         [0119]    Then, as shown in  FIGS. 27A-27C , the polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c  are etched. They are preferably wet-etched. 
         [0120]    Then, as shown in  FIGS. 28A-28C , a metal  121  is deposited and the surface thereof is planarized so as to fill the spaces where the polysilicon gate electrode  114   a,  the polysilicon gate line  114   b,  and the polysilicon gate pad  114   c  had existed with the metal  121 . Atomic layer deposition is preferably employed to fill the spaces. 
         [0121]    Then, as shown in  FIGS. 29A-29C , the metal  121  is etched to expose the gate insulating film  113  on the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106 . As a result, a metal gate electrode  121   a,  a metal gate line  121   b,  and a metal gate pad  121   c  are formed. 
         [0122]    The steps described above constitute the method for producing a semiconductor device by a gate-last technique of depositing metal layers after etching the polysilicon gate exposed by CMP after deposition of the interlayer insulating film. 
         [0123]    A method for forming contacts will now be described. Here, since no silicide is formed in the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106 , the contact is directly connected to the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106 . 
         [0124]    That is, first, as shown in  FIGS. 30A-30C , a fifth nitride film  122  is deposited so that the fifth nitride film  122  is thicker than a half of the width of the polysilicon gate line  114   b  and thinner than a half of the width of the polysilicon gate electrode  114   a  and a half of the width of the polysilicon gate pad  114   c.  As a result, contact holes  123  and  124  are formed on the pillar-shaped silicon layer  106  and the metal gate pad  121   c.  The fifth nitride film  122  and the gate insulating film  113  at the bottom portions of the contact holes  123  and  124  will be removed by a subsequent step of etching the nitride film. Accordingly, a mask for forming the contact hole  123  on the pillar-shaped silicon layer and the contact hole  124  on the metal gate pad  121   c  is not needed. 
         [0125]    Next, as shown in  FIGS. 31A-31C , a fourth resist  125  for forming a contact hole  126  on the fin-shaped silicon layer  103  is formed. 
         [0126]    Then, as shown in  FIGS. 32A-32C , the fifth nitride film  122  and the interlayer insulating film  120  are etched to form the contact hole  126 . 
         [0127]    Then, as shown in  FIGS. 33A-33C , the fourth resist  125  is removed. 
         [0128]    Then, as shown in  FIGS. 34A-34C , the fifth nitride film  122 , the fourth nitride film  119 , and the gate insulating film  113  are etched to expose the silicide  118  and the diffusion layer  110 . 
         [0129]    Then, as shown in  FIGS. 35A-35C , a metal is deposited to form contacts  127 ,  128 , and  129 . 
         [0130]    Through the steps described above, the contacts  127 ,  128 , and  129  can be formed in the semiconductor device. According to this production method, no silicide is formed in the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106  and thus the contact  128  is directly connected to the diffusion layer  110  in the upper portion of the pillar-shaped silicon layer  106 . 
         [0131]    The method for forming metal wiring layers will now be described. 
         [0132]    First, as shown in  FIGS. 36A-36C , a metal  130  is deposited. 
         [0133]    Next, as shown in  FIGS. 37A-37C , fifth resists  131 ,  132 , and  133  for forming metal wirings are formed. 
         [0134]    Then, as shown in  FIGS. 38A-38C , the metal  130  is etched to form metal wirings  134 ,  135 , and  136 . 
         [0135]    Then, as shown in  FIGS. 39A-39C , the fifth resists  131 ,  132 , and  133  are removed. 
         [0136]    Through the steps described above, the metal wirings  134 ,  135 , and  136  which constitute metal wiring layers are formed. 
         [0137]    A semiconductor device produced by the production method described above is shown in  FIGS. 1A-1C . 
         [0138]    The semiconductor device shown in  FIGS. 1A-1C  includes the fin-shaped silicon layer  103  formed on the silicon substrate  101 , the first insulating film  104  formed around the fin-shaped silicon layer  103 , the pillar-shaped silicon layer  106  formed on the fin-shaped silicon layer  103 , the width of the pillar-shaped silicon layer  106  being equal to the width of the fin-shaped silicon layer  103 , and the diffusion layer  112  formed in the upper portion of the fin-shaped silicon layer  103  and in the lower portion of the pillar-shaped silicon layer  106 . 
         [0139]    The semiconductor device shown in  FIGS. 1A-1C  further includes the diffusion layer  110  formed in the upper portion of the pillar-shaped silicon layer  106 , the silicide  118  formed in the upper portion of the diffusion layer  112  in the upper portion of the fin-shaped silicon layer  103 , the gate insulating film  113  formed around the pillar-shaped silicon layer  106 , the metal gate electrode  121   a  formed around the gate insulating film, the metal gate line  121   b  extending in a direction perpendicular to the fin-shaped silicon layer  103  and being connected to the metal gate electrode  121   a,  and the metal gate pad  121   c  connected to the metal gate line  121   b.  The width of the metal gate electrode  121   a  and the width of the metal gate pad  121   c  are larger than the width of the metal gate line  121   b.    
         [0140]    The semiconductor device shown in  FIGS. 1A-1C  has a structure in which the contact  128  is formed on the diffusion layer  110  and the diffusion layer  110  is directly connected to the contact  128 . 
         [0141]    In sum, according to this embodiment of the present invention, a method for producing a SGT, which is a gate-last process capable of decreasing the parasitic capacitance between the gate line and the substrate and which uses only one mask for forming contacts is provided. A SGT structure obtained by this method is also provided. 
         [0142]    Since the method for producing a semiconductor device of the embodiment is based on a known method for producing FINFET, the fin-shaped silicon layer  103 , the first insulating film  104 , and the pillar-shaped silicon layer  106  can be easily formed. 
         [0143]    According to a known method, a silicide is formed in the upper portion of a pillar-shaped silicon layer. Since the polysilicon deposition temperature is higher than the temperature for forming the silicide, the silicide needs to be formed after forming the polysilicon gate. Thus, in the case where a silicide is to be formed in the upper portion of a silicon pillar, the steps of forming a polysilicon gate, forming a hole in the upper portion of the polysilicon gate electrode, forming a sidewall with an insulating film on the sidewall of that hole, forming a silicide, and filling the hole with an insulating film are needed. Thus, there is a problem in that the number of steps in the method will increase. 
         [0144]    In contrast, according to the embodiment described above, diffusion layers are formed before forming the polysilicon gate electrode  114   a  and the polysilicon gate line  114   b  and the pillar-shaped silicon layer  106  is covered with the polysilicon gate electrode  114   a  so that the silicide is formed in the upper portion of the fin-shaped silicon layer  103  only. Then a gate is formed with a polysilicon, the interlayer insulating film  120  is deposited, the polysilicon gate is exposed by chemical mechanical polishing (CMP), and then the polysilicon gate is etched, followed by deposition of a metal. Such a metal-gate-last production method can be used in this embodiment. Thus, according to this method for producing a semiconductor device, a SGT having a metal gate can be easily produced. 
         [0145]    The width of the polysilicon gate electrode  114   a  and the width of the polysilicon gate pad  114   c  are larger than the width of the polysilicon gate line  114   b.  Furthermore, the fifth nitride film  122  thicker than a half of the width of the polysilicon gate line  114   b  and thinner than a half of the width of the polysilicon gate electrode  114   a  and a half of the width of the polysilicon gate pad  114   c  are deposited in a hole formed by etching the polysilicon gate after forming the metal gate. Thus, the contact holes  123  and  124  can be formed on the pillar-shaped silicon layer  106  and the metal gate pad  121   c,  and thus a conventionally required etching step that forms a contact hole in the pillar-shaped silicon layer through a mask is no longer needed. In other words, only one mask is needed to form contacts. 
         [0146]    It should be understood that various other embodiments and modifications are possible without departing from the spirit and scope of the present invention in a broad sense. The embodiment described above is merely illustrative and does not limit the scope of the present invention.

Technology Category: h