Patent Document

BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention generally relates to electronic circuits, and more particularly to flip-flops, latches, and/or other forms of logic circuits as well as methods of controlling the same.  
           [0003]    2. Description of the Related Art  
           [0004]    Logic devices are important components of integrated circuits. They are used, for example, as registers for storing data and instructions as well as for performing logical operations on a variety of signals. Two common logic devices uses in microprocessor design are flip-flops and latches.  
           [0005]    Flip-flops may be classified as static or dynamic. Dynamic flip-flops operate in two stages, namely a precharge stage followed by an evaluate stage. In the precharge stage, a capacitor is precharged to high. In the evaluate stage, its output is evaluated and if the actual output is low the capacitor discharges. Dynamic flip-flops have the advantage of speed, however they consume a significant amount of power and have circuit complexity. Static latches, on the other hand, consume less power, have a simpler design, and possess better noise immunity, clock skew and tolerance compared with dynamic flip-flops. However, they tend to be slower.  
           [0006]    Static flip-flops may be classified into several types, one of which is referred to as a master-slave flip-flop. Master-Slave flip-flops include two identical, cascaded flip-flop stages with complementary clock inputs. The first stage is referred as the “master” and the second stage the “slave.” In a first portion of a clock cycle, the master is activated to receive a data input value. The slave is disabled during this time, maintaining its previous output value. In a second portion of a clock cycle, the master is disabled and the slave is activated. During this time, the slave receives the output of the master and this value is passed as the output of the flip-flop. General speaking, master-slave flip-flops have better race immunity and consume lesser power than edge-triggered and other types of flip-flops.  
           [0007]    Latches are made from the same basic circuit as flip-flops. However, the two differ based on the manner in which they are activated. For example, a latch may be a level-triggered device while a flip-flop may be an edge-triggered based on the transitions of an input clock signal.  
           [0008]    Improving efficiency of flip-flops, latches, and other forms of logic circuits is a primary concern for VLSI design engineers. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 is a diagram showing a flip-flop having a data-enabled control circuit in accordance with one embodiment of the present invention.  
         [0010]    [0010]FIG. 2 is a timing diagram illustrating one way in which the flip-flop of FIG. 1 operates based on exemplary input values.  
         [0011]    [0011]FIG. 3 is a diagram showing a flip-flop having a data-enable control circuit in accordance with another embodiment of the present invention.  
         [0012]    [0012]FIG. 4 is a diagram showing a processing system which may include a data-enabled control circuit in accordance with the embodiment of the invention shown in FIG. 1. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0013]    Referring to FIG. 1, a static flip-flop circuit in accordance with one embodiment of the present invention includes a master stage  10 , a slave stage  20 , and a data-enable control circuit. The master stage includes a transmission gate  2  and a keeper circuit  3 . The transmission gate has an input connected to an inverter  1  which inverts an input data signal. The output of this gate is connected to the keeper circuit which is formed from inverters  6  and  8  connected in a loop. While in this embodiment the master stage is implemented using a transmission gate, those skilled in the art can appreciate that alternative designs are possible. For example, the master stage may be implemented entirely in CMOS logic or may have a totem-pole configuration, the latter of which is illustratively shown in FIG. 4 discussed in greater detail below.  
         [0014]    The slave stage includes a transmission gate  12 , an inverter  14 , and a keeper circuit  16 . Transmission gate  12  has an input connected to the keeper circuit of the master stage and an output which corresponds to an output of the flip-flop circuit. The keeper circuit is formed from inverters  17  and  18  connected in a loop. One node d 2  of the keeper is connected to the output of transmission gate  12 , and an opposing inverted node d 2   b  is connected to the output of a transmission gate included in the data-enable control circuit.  
         [0015]    The data-enable control circuit synchronizes operation of the master and slave stages of the flip-flop circuit in association with a clock signal input along signal line  30 . The data-enable control circuit includes a logic gate  40  and an inverter  42 . The logic gate is preferably a NOR gate which includes as inputs a data enable signal and the input clock signal from line  30 . Inverter  42  inverts the output of the NOR gate. Together, the outputs of the NOR gate and inverter  42  control whether transmission gate  2  passes the inverted data input signal for storage into the master keeper circuit. Put differently, the respective states of the data enable and clock signals control the operation of the master stage of the flip-flop circuit. The clock signal also controls when transmission gate  12  passes the logical value stored in the master keeper to the flip-flop output. This function may be performed independently from the data-enable signal. While the logic gate of the data-enable control circuit is shown as a NOR gate, those skilled in the art can appreciate that other logic gates or circuits may be used provided they perform at least a substantially equivalent function.  
         [0016]    The flip-flop circuit may also include a feedback control circuit  50  which connects the slave keeper to the master keeper. The feedback control circuit includes an inverter  55  and a transmission gate  57 , the operation of which is controlled by the data enable signal input into the data-enable control circuit. This transmission gate has an input connected to the d 2   b  node of the slave keeper and an output connected to the d 1  node of the master keeper.  
         [0017]    In the foregoing embodiment, the transmission gate may be any type conventionally known. For example, the transmission gate may be made from NMOS and PMOS transistors with their sources and drains connected.  
         [0018]    The keeper circuits described above effectively function as memory elements. The feedback structure of these circuits ensures that whatever value is written to a corresponding node when the transmission gate is on does not disappear when the transmission gate is turned off. For example, in keeper circuit  3  if the value output from transmission gate  2  corresponds to a logical zero, node d 1  will also be pulled down to zero when the transmission gate turns off. This, in turn, causes node d 1   b  to rise to a logical one value, which then feeds back through inverter  8  which again produces a logical zero at node d 1 . Through this keeper structure, the value output from the transmission gate will be maintained even after this gate is turned off. The inverters in the keeper structure may be made very weak (e.g., small transistor sizes) so that they can be overpowered by the transmission gate and therefore the value stored at its node can be changed. On the other hand, the inverters are made strong enough so that even if there is leakage at node d 1  or d 1   b , or noise coupled to these nodes from other circuits, the stored value will not be corrupted.  
         [0019]    Operation of the static flip-flop circuit will now be discussed for each of the four possible logical values the data enable and clock signals may assume.  
         [0020]    When the clock and data enable signals are both low (e.g., logical zero), the output of NOR gate  40  is high (e.g., logical one). This value is input into the non-inverting terminal of transmission gate  2  and a logical zero value is input into the inverting terminal of this transmission gate as a result of the output from inverter  42 . These values cause the transmission gate to pass the inverted data signal output from inverter  1  to node d 1 , where it is maintained by keeper circuit  3  of the master portion of the flip-flop. Because the clock signal is low, transmission gate  12  is not activated and thus does not pass the inverted logical value stored at node d 1   b  to the output of the flip-flop. Also, because the data-enable signal is low, transmission gate  55  is not activated and thus does not pass the logical value stored at keeper circuit  16  of the slave portion of the flip-flop to node d 1 .  
         [0021]    When the clock signal transitions from low to high while the data enable signal is low, the output of the NOR gate is a logical zero which causes the transmission gate  2  to become de-activated. However, a logical value of one is input into the non-inverting terminal of transmission gate  12  and a logical value of zero is input into the inverting terminal of this gate. As a result, the inverted logical value stored at node d 1   b  is passed from the slave portion of the circuit to node d 2 , which corresponds to the output of the flip-flop. The logical value at node d 2  is stored in keeper circuit  16  of the slave, however because the data enable signal is low transmission gate  55  remains de-activated and the logical value stored in the slave keeper is not fed back to node d 1  of the master keeper.  
         [0022]    When the clock signal transitions from low to high while the data enable signal is high, the output the NOR gate is a logical zero which causes the transmission gate to become de-activated. However, a logical value of 1 is input into the non-inverting terminal of transmission gate  12  and a logical value of zero is input into the inverting terminal of this gate. As a result, the inverted logical value stored at node d 1   b  is passed from the slave portion of the circuit to node d 2 , which corresponds to the output of the flip-flop. The logical value at node d 2  is stored in keeper circuit  16  of the slave. Because the data enable signal is high, a logical one is input into the non-inverting terminal of transmission gate  55  is activated and a logical zero is input into the inverting terminal of this gate. As a result, transmission gate  55  is activated, thereby feeding back the inverted value stored in slave keeper circuit  16  to node d 1  of the master keeper.  
         [0023]    When the clock signal transitions from high to low while the data enable signal is high, the output of the NOR gate is a logical zero which causes the transmission gate to remain de-activated. Also, because the clock signal is low transmission gate  12  is de-activated and consequently no signal is output from the flip-flop. However, because the data enable signal is high, transmission gate  55  is activated to feedback the inverted value stored at node d 2   b  in the slave keeper circuit to node d 1  of the master keeper. This value is stored at node d 1  until the clock transitions to high once again, at which time the inverted value at node d 1   b  is passed as the output of the flip-flop  
         [0024]    [0024]FIG. 2 is a timing diagram showing the logical states of the static flip-flop circuit at various stages based on exemplary input values. In this diagram, the data enable signal is shown in its complementary form, namely Enable#. The timing diagram is partitioned into three operational cycles. During the first cycle, it is noted that data is set up before transition of the clock signal takes place. Since Enable # is low (the data enable signal is active) at the rising edge of the clock signal (at point A), the output of the flip-flop transitions to the data-captured state (at point B). During the second cycle, data changes from a high to a low logical value (a point C), but since the Enable# signal was deactivated (data enable signal transitions to high at point D), the output does not track the input. During the third cycle, it is noted that the Enable# signal went low (data enable signal transmissions to high) before the rising clock edge at the beginning of this cycle. As a result, the output transitions to the value captured on the rising clock edge.  
         [0025]    The aforementioned embodiment of the static flip-flop of the present invention thus establishes a data-to-output path having two inversions and two pass gates in series. The data-enable control for this flip-flop gates a clock input with a data-enable input through a logical gate such as a NOR gate. This will ensure that the master transmission gate is only enabled when the data-enable signal is low. Under these circumstances, the slave portion of the circuit is enabled and the master is disabled on an up-going transition of the clock signal (e.g., when the clock signal transitions from low to high). Conversely, the slave portion is disabled and the master is enabled on a down-going transition of the clock signal (e.g,. when the clock signal transitions from high to low).  
         [0026]    Also, in the aforementioned embodiment the logical value stored at sustain node d 2   b  is fed back from the slave keeper to the master state node d 1  through a transmission gate which is controlled by the data enable signal. Thus, when the data enable signal is high, the signal value in the slave is recycled into the storage node of the master portion of the circuit. Through this embodiment of the present invention, a static flip-flop may be modified to include a data-enable control circuit without adding any delay stages along the path connecting the data input and data output. As an advantageous result, data signals captured by this flip-flop are not delayed to any extent and thus the flip-flop circuit in accordance with the aforementioned embodiment of the present invention is well-suited to speed-critical applications.  
         [0027]    [0027]FIG. 3 shows a static flip-flop circuit in accordance with another embodiment of the present invention. This circuit includes a master stage  50 , a slave stage  60 , and a data-enable control circuit. The master stage includes a totem-pole arrangement  51  of transistors connected to a keeper circuit  52 , which is formed from inverters  56  and  58  connected in a loop. The slave stage includes a transmission gate  61 , an inverter  62 , and a keeper circuit  63 . Transmission gate  61  has an input connected to the keeper circuit of the master stage and an output which corresponds to an output of the flip-flop circuit. The keeper circuit is formed from inverters  64  and  65  connected in a loop. One node d 2  of the keeper is connected to the output of transmission gate  61 , and an opposing inverted node d 2   b  is connected to the output of a transmission gate included in the data-enable control circuit.  
         [0028]    The data-enable control circuit synchronizes operation of the master and slave stages of the flip-flop circuit in association with a clock signal input along signal line  90 . The data-enable control circuit includes a logic gate  95  and an inverter  96 . The logic gate is preferably a NOR gate which includes as inputs a data enable signal and the input clock signal from line  90 .  
         [0029]    The flip-flop circuit may also include a feedback control circuit  85  which connects the slave keeper to the master keeper. The feedback control circuit includes a transmission gate  86  and an inverter  87 . Operation of transmission gate  86  is controlled by the data enable signal input into the data-enable control circuit. This transmission gate has an input connected to the d 2   b  node of the slave keeper and an output connected to the d 1  node of the master keeper.  
         [0030]    The flip-flop circuit of the second embodiment is similar to the first embodiment except that the transmission gate in the master stage is replaced by the totem-pole arrangement of transistors. This totem-pole arrangement includes two PMOS transistors  52  and  53  and two NMOS transistors  54  and  55  connected in series. The gates of transistors  52  and  55  are connected to the data signal input through an inverter  80 , the gate of transistor  53  is connected to the output of NOR gate  95 , and the gate of transistor  54  is connected to the output of inverter  96 , which inverts the output of the NOR gate. Transistor  52  may be connected to a reference potential  97  such as ground and transistor  55  may be connected to a supply potential  98 .  
         [0031]    Operation of the second embodiment of the static flip-flop circuit will now be discussed for each of the four possible logical values the data enable and clock signals may assume.  
         [0032]    When the clock and data enable signals are both low (e.g., logical zero), the output of NOR gate  40  is high (e.g., logical one). This value is input into the non-inverting terminal of transistor  53  and a logical zero value is input into the inverting terminal of transistor  54  as a result of the output from inverter  96 . These values cause a voltage corresponding to a logical value of the data signal to pass to node d 1 , where it is maintained by keeper circuit  52  of the master portion of the flip-flop. Specifically, if the data signal has a logical zero value, inverter  80  outputs a logical one value, which switches transistor  52  on and transistor  55  off. As a result, a value based on reference potential  97  (which is a logical zero value) is input into node d 1 . Conversely, if the data signal has a logical one value, inverter  80  outputs a logical zero value, which switches transistor  55  on and transistor  52  off. As a result, a value based on supply potential  98  is input into node d 1 . Because the clock signal is low, transmission gate  61  does not pass the inverted logical value stored at node d 1   b  to the output of the flip-flop. Also, because the data-enable signal is low, transmission gate  86  is not activated and thus does not pass the logical value stored at keeper circuit  63  of the slave portion of the flip-flop to node d 1 .  
         [0033]    When the clock signal transitions from low to high while the data enable signal is low, the output of the NOR gate is a logical zero which switches transistor  53  off and the output of inverter  96  is a logical one which switches transistor  54  off However, a logical value of one is input into the non-inverting terminal of transmission gate  61  and a logical value of zero is input into the inverting terminal of this gate. As a result, the inverted logical value stored at node d 1   b  is passed from the slave portion of the circuit to node d 2 , which corresponds to the output of the flip-flop. The logical value at node d 2  is stored in keeper circuit  63  of the slave. However, because the data enable signal is low transmission gate  86  remains de-activated and the logical value stored in the slave keeper is not fed back to node d 1  of the master keeper. Incidentally, it is noted that the low value of the data enable signal switches transistor  55  off and transistor  52  on. These transistors, however, are effectively disconnected from node d 1  by the deactivation of transistors  53  and  54 .  
         [0034]    When the clock signal transitions from low to high while the data enable signal is high, the output of the NOR gate is a logical zero which switches transistor  53  off and the output of inverter  96  is a logical one which switches transistor  54  off. However, a logical value of 1 is input into the non-inverting terminal of transmission gate  61  and a logical value of zero is input into the inverting terminal of this gate. As a result, the inverted logical value stored at node d 1   b  is passed from the slave portion of the circuit to node d 2 , which corresponds to the output of the flip-flop. The logical value at node d 2  is stored in keeper circuit  63  of the slave. Because the data enable signal is high, a logical one is input into the non-inverting terminal of transmission gate  86  is activated and a logical zero is input into the inverting terminal of this gate. As a result, transmission gate  86  is activated, thereby feeding back the inverted value stored in slave keeper circuit  63  to node d 1  of the master keeper.  
         [0035]    When the clock signal transitions from high to low while the data enable signal is high, the output of the NOR gate is a logical zero which causes transistor  53  to switch off and the output of the inverter  96  is a logical one which causes transistor  54  to switch off. Also, because the clock signal is low transmission gate  61  is de-activated and consequently no signal is output from the flip-flop. However, because the data enable signal is high, transmission gate  86  is activated to feedback the inverted value stored at node d 2   b  in the slave keeper circuit to node d 1  of the master keeper. This value is stored at node d 1  until the clock transitions to high once again, at which time the inverted value at node d 1   b  is passed as the output of the flip-flop.  
         [0036]    [0036]FIG. 4 shows a processing system in accordance with one embodiment of the present invention. The processing system includes a processor  100  such as but not limited to a microprocessor, an optional cache  102 , an optional chipset  104 , a memory  106  such as but not limited to a random access memory, an optional network interface  110 , an optional graphical interface  112 , and a power supply  114 . The processor may contain, for example, an arithmetic logic unit (ALU)  120  and an internal cache  125 . As shown, any one or more of the ALU, cache, chipset, graphical interface, and network interface may include a flip-flop  400  in accordance with any of the embodiments of the present invention described herein for purposes of, for example, performing a static-storage function, with condition control through the data enable (or Enable#) signal.  
         [0037]    Other modifications and variations to the invention will be apparent to those skilled in the art from the foregoing disclosure. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.

Technology Category: 5