Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation as to all subject matter common to U.S. application Ser. No. 851,912 filed Nov. 16, 1977 now abandoned by Avilino Sequeira, Jr., John D. Begnaud and Frank. L. Barger, and assigned to Texaco Inc., assignee of the present invention, and a continuation-in-part for additional subject matter. 
    
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to control systems and methods in general and, more particularly, to control systems and methods for oil refining units. 
     SUMMARY OF THE INVENTION 
     A furfural refining unit treats heavy sweet charge oil with a furfural solvent in a refining tower to yield raffinate and extract mix. The furfural is recovered from the raffinate and from the extract mix and returned to the refining tower. A system controlling the refining unit includes a gravity analyzer, a flash point temperature analyzer, a sulfur analyzer and viscosity analyzers. The analyzers analyze the heavy sweet charge oil and provide corresponding signals. Sensors sense the flow rates of the charge oil and the furfural flowing into the refining tower and the temperature of the extract mix and provide corresponding signals. The flow rate of the heavy sweet charge oil of the furfural is controlled in accordance with the signals provided by all the sensors and the analyzers while the other flow rate of the heavy sweet charge oil and the furfural flow rates is constant. 
     The objects and advantages of the invention will appear more fully hereinafter from a consideration of the detailed description which follows, taken together with the accompanying drawings wherein one embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawings are for illustration purposes only and are not to be construed as defining the limits of the invention. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a furfural refining unit in partial schematic form and a control system, constructed in accordance with the present invention, in simple block diagram form. 
     FIG. 2 is a detailed block diagram of the control means shown in FIG. 1. 
     FIGS. 3 through 14 are detailed block diagrams of the H computer, the K signal means, the H signal means, the KV computer, the VI signal means, the SUS computer, the SUS 210  computer, the W computer, the VI DWCO  computer, the VI DWCP  computer, the A computer and the J computer, respectively, shown in FIG. 2. 
    
    
     DESCRIPTION OF THE INVENTION 
     An extractor 1 in a furfural refining unit is receiving heavy sweet charge oil by way of a line 4 and furfural solvent by way of a line 7 and providing raffinate to recovery by way of a line 10, and an extract mix to recovery by way of a line 14. 
     Heavy sweet charge oil is a charge oil having a sulfur content less than a predetermined sulfur content and having a kinematic viscosity, corrected to a predetermined temperature, greater than a predetermined kinematic viscosity. Preferably, the predetermined sulfur content is 1.0%, the predetermined temperature is 210° F., and the predetermined kinematic viscosity is 15.0, respectively. The temperature in extractor 1 is controlled by cooling water passing through a line 16. A gravity analyzer 20, flash point analyzer 22 and viscosity analyzers 23 and 24, and a sulfur analyzer 28 sample the charge oil in line 4 and provide signals API, FL, KV 210 , KV 150  and S, respectively, corresponding to the API gravity, the flash point, the kinematic viscosity at 210° F. &amp; 150° F., and sulfur content, respectively. 
     A flow transmitter 30 in line 4 provides a signal CHG corresponding to the flow rate of the charge oil in line 4. Another flow transmitter 33 in line 7 provides a signal SOLV corresponding to the furfural flow rate. A temperature sensor 38, sensing the temperature of the extract mix leaving extractor 1, provides a signal T corresponding to the sensed temperature. All signals hereinbefore mentioned are provided to control means 40. 
     Control means 40 provides signal C to a flow recorder controller 43. Recorder controller 43 receives signals CHG and C and provides a signal to a valve 48 to control the flow rate of the charge oil in line 4 in accordance with signals CHG and C so that the charge oil assumes a desired flow rate. Signal T is also provided to temperature controller 50. Temperature controller 50 provides a signal to a valve 51 to control the amount of cooling water entering extractor 1 and hence the temperature of the extract-mix in accordance with its set point position and signal T. 
     The following equations are used in practicing the present invention for heavy sweet charge oil: 
     
         H.sub.210 =1n1n(KV.sub.210 +C.sub.1)                       (1) 
    
     where H 210  is a viscosity H value for 210° F., KV 210  is the kinematic viscosity of the charge oil at 210° F. and C 1  is a constant having a preferred value of 0.6. 
     
         H.sub.150 =1n1n(KV.sub.150 +C.sub.1)                       (2) 
    
     where H 150  is a viscosity H value for 150° F., and KV 150  is the kinematic viscosity of the charge oil at 150° F. 
     
         K.sub.150 =[C.sub.2 -1n(T.sub.150 +C.sub.3 ]/C.sub.4       (3) 
    
     where K 150  is a constant needed for estimation of the kinematic viscosity at 100° F., T 150  is 150, and C 2  through C 4  are constants having preferred values of 6.5073, 460 and 0.17937, respectively. 
     
         H.sub.100 =H.sub.210 +(H.sub.150 --H.sub.210)/K.sub.150    (4) 
    
     where H 100  is a viscosity H value for 100° F. 
     
         KV.sub.100 =exp[exp(H.sub.100)]--C.sub.1                   (5) 
    
     where KV 100  is the kinematic viscosity of the charge oil at 100° F. ##EQU1## where SUS is the viscosity in Saybolt Universal Seconds and C 5  through C 12  are constants having preferred values of 4.6324, 1.0, 0.03264, 3930.2, 262.7, 23.97, 1.646 and 10 -5 , respectively. 
     
         SUS.sub.210 =[C.sub.13 +C.sub.14 (C.sub.15 -C.sub.16)]SUS  (7) 
    
     where SUS 210  is the viscosity in Saybolt Universal Seconds at 210° F. and C 13  through C 16  are constants having preferred values of 1.0, 0.000061, 210 and 100, respectively. ##EQU2## where W is the percent wax in the charge oil, and C 43  through C 49  are constants having preferred values of 51.17 4.3135, 182.83, 5.2388, 0.101, 6.6106 and 0.19609, respectively. ##EQU3## where C 67  through C 73  are constants having preferred values of 168.538, 0.0468, 3.63863, 0.17523, 0.41542, 0.00106 and 0.21918, respectively. 
     
         VI.sub.DWCP =VI.sub.DWCO +(Pour) [C.sub.21 -C.sub.22 1nSUS.sub.210 +C.sub.23 (1nSUS.sub.210).sup.2 ]                         (10) 
    
     where VI DWCP  and Pour are the viscosity index of the dewaxed charge at a predetermined temperature and the Pour Point of the dewaxed product, respectively, and C 21  through C 23  are constants having preferred values of 2.856, 1.18 and 0.126, respectively. 
     
         ΔVI=VI.sub.RO -VI.sub.DWCO =VI.sub.RP -VI.sub.DWCP   (11) 
    
     where VI RO  and VI RP  are the VI of the refined oil at 0° F., and the predetermined temperature, respectively. ##EQU4## where C 74  through C 79  are constants having preferred values of 503.518, 0.04423, 54.58305, 0.00055, 0.03745 and 1.38869. 
     
         J=(ΔVI-C.sub.80 -C.sub.81 √T)/[-C.sub.82 T+C.sub.83 (A)(T)], (13) 
    
     where J is the furfural dosage and C 80  through C 83  are constants having preferred values of 10.272, 1.0194, 0.00067611 and 0.000004029, respectively. 
     
         C=(SOLV) (100)/J                                           (14) 
    
     where C is the new charge oil flow rate. 
     Referring now to FIG. 2, signal KV 210  is provided to an H computer 50 in control means 40, while signal KV 150  is applied to an H computer 50A. It should be noted that elements having a number and a letter suffix are similar in construction and operation as to those elements having the same numeric designation without a suffix. All elements in FIG. 2, except elements whose operation is obvious, will be disclosed in detail hereinafter. Computers 50 and 50A provide signals E 1  and E 2  corresponding to H 210   and H 150 , respectively, in equations 1 and 2, respectively, to H signal means 53. K signal means 55 provides a signal E 3  corresponding to the term K 150  in equation 3 to H signal means 53. H signal means 53 provides a signal E 4  corresponding to the term H 100  in equation 4 to a KV computer 60 which provides a signal E 5  corresponding to the term KV 100  in accordance with signal E 4  and equation 5 as hereinafter explained. 
     Signals E 5  and KV 210  are applied to VI signal means 63 which provides a signal E 6  corresponding to the viscosity index. 
     An SUS computer 65 receives signal KV 210  and provides a signal E 7  corresponding to the term SUS in accordance with the received signals and equation 6 as hereinafter explained. 
     An SUS 210 computer 68 receives signal E 7  and applies signal E 8  corresponding to the term SUS 210  in accordance with the received signal and equation 7 as hereinafter explained. 
     A W computer 69 receives signals KV 210 , S and API and provides a signal E 9  corresponding to the term W in equation 8 in accordance with the received signals and equation 8 as hereinafter explained. 
     A VI DWCO  computer 70 receives signal RI, E 9 , API, FL and E 6  and provides a signal E 10  corresponding to the term VI DWCO  in accordance with the received signals and equation 9 as hereinafter explained. 
     A VI DWCP  computer 72 receives a signal E 8  and E 10  and provides a signal E 11  corresponding to the term VI DWCP  in accordance with the received signals and equation 10. Subtracting means 76 performs the function of equation 11 by subtracting signal E 11  from a direct current voltage V 9 , corresponding to the term VI RP , to provide a signal E 12  corresponding to the term ΔVI in equation 11. 
     An A computer 79 receives signals KV 210 , API,S and FL and provides a signal A corresponding to the term A in equation 12, in accordance with the received signals and equation 12 as hereinafter explained. 
     A J computer 80 receives signals T, A and E 2  and provide a signal E 13  corresponding to the term J in accordance with the received signals and equation 13 as hereinafter explained to a divider 83. 
     Signal SOLV is provided to a multiplier 82 where it is multiplied by a direct current voltage V 2  corresponding to a value of 100 to provide a signal corresponding to the term (SOLV) (100) in equation 14. The product signal is applied to divider 83 where it is divided by signal E 13  to provide signal C corresponding to the desired new charge oil flow rate. 
     It would be obvious to one skilled in the art that if the charge oil flow rate was maintained constant and the furfural flow rate varied, equation 14 would be rewritten as 
     
         SO=(J) (CHG)/100                                           (15) 
    
     where SO is the new furfural flow rate. Control means 40 would be modified accordingly. 
     Referring now to FIG. 3, H computer 50 includes summing means 112 receiving signal KV 210  and summing it with a direct current voltage C 1  to provide a signal corresponding to the term [KV 210  +C 1  ] shown in equation 1. The signal from summing means 112 is applied to a natural logarithm function generator 113 which provides a signal corresponding to the natural log of the sum signal which is then applied to another natural log function generator 113A which in turn provides signal E 10 . 
     Referring now to FIG. 4, K signal means 55 includes summing means 114 summing direct current voltages T 150  and C 3  to provide a signal corresponding to the term [T 150  +C 3  ] which is provided to a natural log function generator 113B which in turn provides a signal corresponding to the natural log of the sum signal from summing means 114. Subtracting means 115 subtracts the signal provided by function generator 113B from a direct current voltage C 2  to provide a signal corresponding to the numerator of equation 3. A divider 116 divides the signal from subtracting means 115 with a direct current voltage C 4  to provide signal E 3 . 
     Referring now to FIG. 5, H signal means 53 includes subtracting means 117 which subtracts signal E 1  from signal E 2  to provide a signal corresponding to the term H 150  -H 210 , in equation 4, to a divider 118. Divider 118 divides the signal from subtracting means 117 by signal E 3 . Divider 114 provides a signal which is summed with signal E 1  by summing means 119 to provide signal E 4  corresponding to H 100 . 
     Referring now to FIG. 6, a direct current voltage V 3  is applied to a logarithmic amplifier 120 in KV computer 60. Direct current voltage V 3  corresponds to the mathematical constant e. The output from amplifier 120 is applied to a multiplier 122 where it is multiplied with signal E 4 . The product signal from multiplier 122 is applied to an antilog circuit 125 which provides a signal corresponding to the term exp (H 100 ) in equation 5. The signal from circuit 125 is multiplied with the output from logarithmic amplifier 120 by a multiplier 127 which provides a signal to antilog circuit 125A. Circuit 125A is provided to subtracting means 128 which subtracts a direct current voltage C 1  from the signal from circuit 125A to provide signal E 5 . 
     Referring now to FIG. 7, VI signal means 63 is essentially memory means which is addressed by signals E 5 , corresponding to KV 100 , and signal KV 210 . In this regard, a comparator 130 and comparator 130A represent a plurality of comparators which receive signal E 5  and compare signal E 5  to reference voltages, represented by voltages R 1  and R 2 , so as to decode signal E 5 . Similarly, comparators 130B and 130C represent a plurality of comparators receiving signal KV 210  which compare signal KV 210  with reference voltages RA and RB so as to decode signal KV 210 . The outputs from comparators 130 and 130B are applied to an AND gate 133 whose output controls a switch 135. Thus, should comparators 130 and 130B provide a high output, AND gate 133 is enabled and causes switch 135 to be rendered conductive to pass a direct current voltage V A  corresponding to a predetermined value, as signal E 6  which corresponds to VI. Similarly, the outputs of comparators 130 and 130C control an AND gate 133A which in turn controls a switch 135A to pass or to block a direct current voltage V B . Similarly, another AND gate 133B is controlled by the outputs from comparators 130A and 130B to control a switch 135B so as to pass or block a direct current voltage V C . Again, an AND gate 133C is controlled by the outputs from comparators 130A and 130C to control a switch 135C to pass or to block a direct current voltage V D . The outputs of switches 135 through 135C are tied together so as to provide a common output. 
     Referring now to FIG. 8, the SUS computer 65 includes multipliers 136, 137 and 138 multiplying signal KV 210  with direct current voltages C 9 , C 7  and C 5 , respectively, to provide signals corresponding to the terms C 9  (KV 210 ), C 7  (KV 210 ) and C 5  (KV 210 ), respectively in equation 6. A multiplier 138 effectively squares signal KV 210  to provide a signal to multipliers 140, 141. Multiplier 140 multiplies the signal from multiplier 139 with a direct current voltage C 10  to provide a signal corresponding to the term C 10  (KV 210 ) 2  in equation 6. Multiplier 141 multiplies the signal from multiplier 139 with signal KV 210  to provide a signal corresponding to (KV 210 ) 3 . A multiplier 142 multiplies the signal from multiplier 141 with a direct current voltage C 11  to provide a signal corresponding to the term C 11  (KV 210 ) 3  in equation 6. Summing means 143 sums the signals from multipliers 136, 140 and 142 with a direct current voltage C 8   to provide a signal to a multiplier 144 where it is multiplied with a direct current voltage C 12 . The signal from multiplier 137 is summed with a direct current voltage C 6  by summing means 145 to provide a signal corresponding to the term [C 6  +C 7  (KV 210  ]. A divider 146 divide the signal provided by summing means 145 with the signal provided by multiplier 144 to provide a signal which is summed with the signal from multiplier 138 by summing means 147 to provide signal E 7 . 
     Referring now to FIG. 9, SUS 210  computer 68 includes subtracting means 148 which subtracts a direct current voltage C 16  from another direct current voltage C 16  from another direct current voltage C 15  to provide a signal corresponding to the term (C 15  -C 16 ) in equation 7. The signal from subtracting means 148 is multiplied with a direct current voltage C 14  by a multiplier 149 to provide a product signal which is summed with another direct current voltage C 13  by summing means 150. Summing means 150 provides a signal corresponding to the term [C 13  +C 14  (C 15  -C 16  ] in equation 7. The signal from summing means 150 is multiplied with signal E 7  by a multiplier 152 to provide signal E 8 . 
     Referring now to FIG. 10, there is shown W computer 69 having multipliers 155, 156 and 157 receiving signal API. Multiplier 155 multiplies signal API with signal S to provide a product signal to another multiplier 160 where it is multiplied with a direct current voltage C 49  to provide a signal corresponding to the term C 49  (S) (API) in equation 8. Multiplier 156 effectively squares signal API and provides a signal to another multiplier 163 where it is multiplied with a direct current voltage C 47  to provide a signal corresponding to the term (C 47 ) (API) 2 . Multiplier 157 multiplies signal API with a direct current voltage C 44  to provide a signal corresponding to the term C 44  (API). A divider 166 divides signal API with signal KV 210  to provide another signal to a multiplier 168 where it is multiplied with a direct current voltage C 48  which in turn provides a signal corresponding to the term [C 48  (API)/(KV 210 )] in equation 8. A divider 170 divides a direct current voltage C 45  with signal KV 210  to provide a signal corresponding to the term C 45  /(KV 210 ). A multiplier 173 multiplies signal S with a direct current voltage C 46 . Summing means 175 sums a direct current voltage C 43  with the signals provided by multipliers 160, 163 and divider 170. Other summing means 176 sums the signals provided by multipliers 157, 168 and 173. Subtracting means 179 subtracts the signal provided by summing means 176 from the signal provided by summing means 175 to provide signal E 9 . 
     Referring now to FIG. 11, VI DWCO  computer 70 includes a multiplier 180 which effectively squares signal KV 210  and provides it to a multiplier 181 where it is multiplied direct current voltage C 68 . Multiplier 181 provides a signal corresponding to the term C 68  (KV 210 ) 2  in equation 9. A multiplier 182 multiplies signals KV 210 , E 9  to provide a signal to another multiplier 183 where it is multiplied with direct current voltage C 73 . Multiplier 183 provides a signal corresponding to the term C 73  (W) (KV 210 ) in equation 9. A multiplier 184 multiplies signal E 6  with a direct current voltage C 69  to provide a signal corresponding to the term C 69  (VI) in equation 9. Another multiplier 185 multiplies signals E 6 , FL to provide a signal to a multiplier 186 where it is multiplied with a direct current voltage C 72 . Multiplier 186 provides a signal corresponding to the term C 72  (FL) (VI) in equation 9. A multiplier 188 multiplies signals E 6 , API to provide a signal to another multiplier 189 where it is multiplied with direct current voltage C 70 . Product signals provided by multipliers 183, 189 are summed with another direct current voltage C 67  by summing means 192 to provide a signal corresponding to the term -C 67  -C 70  (API) (VI)-C 73  (W) (KV 210 ). A multiplier 193 effectively squares signal API and provides it to a multiplier 194 where it is multiplied with a direct current voltage C 71 . Multiplier 194 provides a signal corresponding to the term C 71  (API) 2  in equation 9. Summing means 197 sums the signal from multipliers 181, 184, 186 and 196. Subtracting means 199 subtracts the signal provided by summing means 192 from the signal provided by summing means 197 to provide signal E 10 . 
     VI DWCP  computer 72 shown in FIG. 12, includes a natural logarithm function generator 200 receiving signal E 8  and providing a signal corresponding to the term 1nSUS 210  to multipliers 201 and 202. Multiplier 201 multiplies the signal from function generator 200 with a direct current voltage C 22  to provide a signal corresponding to the term C 22  1n SUS 210  in equation 10. Multiplier 202 effectively squares the signal from function generator 200 to provide a signal that is multiplied with the direct current voltage C 23  by a multiplier 205. Multiplier 205 provides a signal corresponding to the term C 23  (1n SUS 210 ) 2  in equation 10. Subtracting means 206 subtracts the signals provided by multiplier 201 from the signal provided by multiplier 205. Summing means 207 sums the signal from subtracting means 206 with a direct current voltage C 21 . A multiplier 208 multiplies the sum signals from summing means 207 with a direct current voltage POUR to provide a signal which is summed with signal E 9  by summing means 210 which provides signal E 11 . 
     FIG. 13 shows A computer 78 having a multiplier 215 effectively squaring signal KV 210  to provide a signal which is multiplied with a direct current voltage C 75  by a multiplier 216 which provides a signal corresponding to the term C 75  (KV 210 ) 2  in equation 12. Multiplier 218 multiplies signals KV 210 , S to provide a signal that is multiplied with a direct current voltage C 79  by a multiplier 220. Multiplier 220 provides a signal corresponding to the term C 79  (KV 210 ) (S) in equation 12. A multiplier 223 multiplies signals API, FL to provide a signal to another multiplier 224 where it multiplies a direct current voltage C 78 . Multiplier 224 provides a signal corresponding to the term C 78  (FL) (API) in equation 12. Summing means 226 essentially sums all of the negative terms in equation 12 by summing the signals from multipliers 216, 220 and 224. A multiplier 229 multiplies signal S with a direct current voltage C 76  to provide a signal corresponding to the term C 76  (S) in equation 12. Another multiplier 230 effectively squares signal FL and provides it to yet another multiplier 231 where it is multiplied with a direct current voltage C 77 . Multiplier 231 provides a signal corresponding to the term C 77  (FL) 2 . Summing means 235 essentially sums the positive terms of equation 12 by summing a direct current voltage C 74  with the signals provided by multipliers 229 and 231. Subtracting means 237 subtracts the signal provided by summing means 236 from the signal provided by summing means 235 to provide signal A. 
     Referring now to FIG. 14, J computer 80 includes a square root circuit 240 receiving signal T and providing a signal to a multiplier 241 where it is multiplied with a direct current voltage C 81  to provide a signal to subtracting means 242. Subtracting means 242 subtracts a signal provided by multiplier 241 from signal E 12  to provide a signal corresponding to the term ΔVI-C 81  √T in equation 13. Subtracting means 242 provides a signal to another subtracting means 243 which subtracts a direct current voltage C 80  to provide a signal corresponding to the term (ΔVI-C 80  -C 81  √T) in equation 13. A multiplier 246 multiplies signal T with a direct current voltage C 82  to provide a signal corresponding to the term C 82  T in equation 13. Another multiplier 250 multiplies signal T with signal A to provide a signal to another multiplier 252 where it is multiplied with a direct current voltage C 83 . Multiplier 252 provides a signal corresponding to the term C 83  (A) (T) in equation 13. Subtracting means 255 subtracts the product signal from multiplier 246 from the signal provided by multiplier 252 to provide a signal which is divided into the signal provided by subtracting means 243 by a divider 257. Divider 257 provides signal E 13 . 
     The present invention as hereinbefore described controls a furfural refining unit receiving heavy sweet charge oil to achieve a desired charge oil flow rate for a constant furfural flow rate. It is also within the scope of the present invention, as hereinbefore described, to control the furfural flow rate while the heavy sweet charge oil flow is maintained at a constant rate.

Technology Category: 8