Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims the benefit of the priority date of U.S. Provisional patent application serial No. 60/374,280, filed Apr. 19, 2002. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    This invention relates to powering of kinescopes, and more particularly to focus tracking in the presence of ultor voltage variation.  
         BACKGROUND OF THE INVENTION  
         [0003]    Video displays, such as are used for television viewing and computer operation, often use kinescopes, picture tubes, or cathode ray tubes (CRTs) as the display device. A picture tube is a vacuum tube which has a phosphorescent display screen and control terminals for directing a focussed electron beam toward the screen to generate the desired image. In general, a picture tube requires a relatively high anode or “ultor” voltage to accelerate the electron beam toward the screen, a cathode and a grid which coact for modulating the intensity of the electron beam in accordance with the image to be generated, and a focus electrode to which a focus voltage is applied to cause the electron beam to be focussed at the screen. In addition, a picture tube is associated with a deflection arrangement for deflecting the electron beam both vertically and horizontally. The ultor or anode voltage of the picture tube is often regulated in order to reduce voltage changes attributable to interaction between the internal impedance of the ultor voltage source and the varying cathode or beam current required to generate an image. “Static” focus voltage is applied to the focus terminal of the picture tube in order to focus the electron beam at a given location, such as the center of the screen. It is well understood that the value of the “static” focus voltage is desirably a fixed proportion of the ultor voltage. Dynamic focus control is often provided for adjusting the value of the focus voltage applied to the picture tube in accordance with the position of the electron beam, in order to keep the electron beam focussed on the screen notwithstanding the changing length of the electron beam path attributable to deflection.  
         SUMMARY OF THE INVENTION  
         [0004]    A video imaging apparatus according to an aspect of the invention comprises a first cathode-ray tube having a first ultor electrode and a first focus electrode, and a second cathode-ray tube having a second ultor electrode and a second focus electrode. A power supply for generating an ultor voltage is coupled to the first and second ultor electrodes. The ultor voltage may have a fluctuating voltage component produced by beam current variations. A high voltage amplifier generates a dynamic focus voltage component at a frequency related to a deflection frequency. A combining network combines the fluctuating voltage component and the dynamic focus voltage component to develop a combined, dynamic focus voltage. The combined, dynamic focus voltage is coupled to each of the first and second focus electrodes for developing from the combined, dynamic focus voltage each of a first dynamic focus voltage at the first focus electrode and a second dynamic focus voltage at the second focus electrode.  
           [0005]    According to another aspect of the invention, a video imaging apparatus comprises a first cathode-ray tube having a first ultor electrode and a first focus electrode, and a second cathode-ray tube having a second ultor electrode and a second focus electrode. A power supply generates an ultor voltage coupled to the first and second ultor electrodes having a fluctuating voltage component produced by beam current variations. A high voltage amplifier generates a dynamic focus voltage component at a frequency related to a deflection frequency. A combining network combines the fluctuating voltage component and the dynamic focus voltage component to develop a combined, dynamic focus voltage. A first voltage divider is responsive to the combined, dynamic focus voltage for developing from the combined, dynamic focus voltage a first dynamic focus voltage at the first focus electrode, and a second voltage divider is responsive to the combined, dynamic focus voltage for developing from the combined, dynamic focus voltage a second focus voltage at the second focus electrode.  
           [0006]    A video imaging apparatus according to another aspect of the invention comprises a first cathode-ray tube having a first ultor electrode and a first focus electrode, and a second cathode-ray tube having a second ultor electrode and a second focus electrode. A power supply for generating an ultor voltage is coupled to the first and second ultor electrodes. The ultor voltage may have a fluctuating voltage component produced by beam current variations. A high voltage amplifier generates a dynamic focus voltage component at a frequency related to a deflection frequency. A combining network combines the fluctuating voltage component and the dynamic focus voltage component to develop a combined, dynamic focus voltage. The combined, dynamic focus voltage is coupled to each of the first and second focus electrodes for developing from the combined, dynamic focus voltage each of a first dynamic focus voltage at the first focus electrode and a second dynamic focus voltage at the second focus electrode.  
           [0007]    According to yet another aspect of the invention, a video imaging apparatus comprises a first cathode-ray tube having a first ultor electrode and a first focus electrode, and a second cathode-ray tube having a second ultor electrode and a second focus electrode. A power supply generates an ultor voltage coupled to the first and second ultor electrodes having a fluctuating voltage component produced by beam current variations. A high voltage amplifier generates a dynamic focus voltage component at a frequency related to a deflection frequency. A combining network combines the fluctuating voltage component and the dynamic focus voltage component to develop a combined, dynamic focus voltage. A first voltage divider is responsive to the combined, dynamic focus voltage for developing from the combined, dynamic focus voltage a first dynamic focus voltage at the first focus electrode, and a second voltage divider is responsive to the combined, dynamic focus voltage for developing from the combined, dynamic focus voltage a second focus voltage at the second focus electrode. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0008]    [0008]FIG. 1 a  is a simplified diagram in block and schematic form illustrating inter alia a dynamic focus and high voltage-related focus signal combiner according to an aspect of the invention;  
         [0009]    [0009]FIG. 2 is a simplified equivalent diagram of an arrangement according to an aspect of the invention in which three picture tubes are used;  
         [0010]    [0010]FIGS. 3 a  and  3   b  are frequency plots of the phase and amplitude components, respectively, of the transfer of dynamic focus signals through the combiner of FIG. 1 a ; and  
         [0011]    [0011]FIGS. 4 a  and  4   b  are frequency plots of the phase and amplitude components, respectively, of the transfer of high voltage signals through the combiner of FIG. 1 a.   
     
    
     DESCRIPTION OF THE INVENTION  
       [0012]    In FIG. 1 a , a television apparatus designated generally as  10  includes at lower right a cathode-ray tube (CRT) or kinescope  12  which includes a screen  12   s , an ultor or high voltage (anode) terminal  12 U, a focus terminal  12 F, and a cathode  12 C. Cathode  12 C of CRT  12  is illustrated as being connected to a source of image signal in the form of video source  14 . As noted in FIG. 1 a , CRT  12  may be one of three similar CRTs, as might be used, for example, in a projection television arrangement.  
         [0013]    The ultor or high voltage terminal  12   u  of CRT  12  of FIG. 1 a  is connected by way of a conductor  9  to an ultor or high voltage and focus voltage source illustrated as a block  49 . Block 49 is illustrated in more detail in FIG. 1 b . In FIG. 1 b , elements corresponding to those of FIG. 1 a  are designated by like reference numerals. Structure  49  of FIG. 1 b  includes an integrated high voltage/focus voltage transformer/rectifier arrangement designated generally as  50 , which includes a primary winding  50   p  having one end connected to a source of regulated B+ and another end connected to a horizontal output transistor illustrated as a block  218 , which is a part of deflection block  18  at upper left of FIG. 1 a . Transformer  50  of FIG. 1 b  also includes a distributed secondary winding made up of secondary sections designated  50   s , with a rectifier or diode, some of which are designated  52 , located between each pair of secondary sections. The uppermost secondary winding  50   s  in transformer  50  is connected by way of the serial combination of an inductor  50   i  and a further rectifier or diode  52 ′ to high voltage conductor  9 , from which the high voltage is coupled to ultor terminal  12   u  of FIG. 1 a . The lowermost secondary winding  50   s  of transformer  50  of FIG. 1 b  is connected by way of the series combination of an inductor  50   i   2  and a diode  52 ″ to ground. Resistor  4 R′ represents the distributed resistance of the secondary windings  52  lying above tap  50 , and a capacitor C′ connected between transformer terminal  9  and tap  50   t  represents the distributed capacitance of the windings lying above tap  50   t.  Similarly, resistor  2 R′ represents the distributed resistance of windings  52  and inductor  50   i   2 , lying below tap  50   t  of transformer  50 , and capacitor  2 C′ represents the distributed capacitance. Tap  50   t  of transformer  50  of FIG. 1 b  is connected by way of a focus voltage conductor  11  to input terminal  26   i   2  of focus control  26  of FIG. 1 a . Within focus control  26  of FIG. 1 a , the focus voltage from transformer  50  is coupled to focus terminal  12 F by means of a focus control  26  voltage divider designated as  28 . Voltage divider  28  includes resistors R 101  and R 102 , with a tap  28   t  therebetween. Tap  28   t  is connected to focus terminal  12 F of CRT  12 . Focus control  26  includes an input port  26   i   1  to which other focus signals may be applied.  
         [0014]    Also in FIG. 1 a , a deflection arrangement (Defl) illustrated at upper left as a block  16  receives composite video or at least separated synchronization signals at a port  16   i . Deflection arrangement  16  produces vertical and horizontal deflection signals, illustrated together as being generated at an output terminal  16   o  and applied by way of a path  19  to deflection windings, illustrated together as  12 W, which is or are associated with the CRT  12 , all as known in the art. Deflection arrangement  16  also includes a deflection processor  18 , which for example is a Toshiba TA1317AN deflection processor. Deflection processor  18  produces horizontal dynamic focus signals at an output port  18 H, and vertical dynamic focus signals at an output port  18 V.  
         [0015]    A dynamic focus combining circuit and amplifier, designated generally as  20  in FIG. 1 a , includes a differential amplifier  22  including NPN transistors Q 5  and Q 6 , together with a common emitter resistor. R 10  and base resistors R 504  and R 505 . Vertical dynamic focus signals from terminal  18 V of deflection processor  18  are applied by way of an AC-gain determining resistor R 301  and a dc blocking capacitor C 301  to a first input port  22   i   1  of differential amplifier  22 . A voltage divider including resistors R 11  and R 12  provides bias and additional AC gain control for input terminal  22   i   1  of differential amplifier  22 . Horizontal dynamic focus signals produced at terminal  18 H of deflection processor  18 , contain, or are associated with, a retrace parabola. The retrace parabola is removed from the horizontal dynamic focus signals in order to limit the bandwidth of the signals so that following slew-rate-limited circuits can respond usefully. The horizontal rate dynamic focus signals are applied from output terminal  18 H of deflection processor  18  to an input port  24   i  of a retrace parabola removal circuit  24 . The retrace parabola is removed from the horizontal dynamic focus signal by retrace parabola removal circuit  24 , which includes transistors Q 201  and Q 202 , diodes D 201 , D 201 , and D 203 , capacitor C 201 , and resistors R 16 , R 201 , R 202 , R 203 , and R 204 .  
         [0016]    In FIG. 1 a , retrace parabola removal circuit  24  includes the series combination of a resistor R 16  and a coupling capacitor C 201  electrically connected between input port  24   i  and output port  24   o , so that in the absence of the remainder of the parabola removal circuit  24 , the horizontal-rate dynamic focus signals are coupled from input port  24   i  to output port  24   o  without change. A source  24 H of horizontal retrace pulses couples positive-going pulses by way of a resistor R 204  to the base of a grounded-emitter NPN transistor Q 202 . Transistor Q 202  is nonconductive during the horizontal trace interval, and conductive during the horizontal retrace interval. When transistor Q 202  is nonconductive during the horizontal trace interval, PNP transistor Q 201  receives no base bias, and is nonconductive. During horizontal retrace, when transistor Q 202  is conductive, a voltage divider including resistors R 202  and R 203  applies a forward bias to the base-emitter junction of transistor Q 201 , as a result of which transistor Q 201  turns ON. The emitter current of transistor Q 201  flows through a diode D 201  to the +V 1  supply voltage, so the emitter of transistor Q 201  is held at a voltage which is one semiconductor junction voltage drop (one VBE) below or more negative than the +V 1  source voltage. Transistor Q 201  also saturates or achieves a state of little collector-to-emitter voltage drop, so the collector of Q 201 , and therefore output port  24   o , rises to within one VBE of the +V 1  source. Thus, the output voltage of retrace parabola removal circuit  24  is set to a fixed voltage during horizontal retrace, regardless of the magnitude of the horizontal dynamic focus signal applied to input port  24   i . A diode D 202  and a resistor R 201  together form a voltage divider that provides a reference voltage two (2) diode voltage drops (2VBE) below or more negative than the +V 1  voltage source applied to the anode of D 201 . Thus, the cathodes of diodes D 202  and D 203  are 2VBE below +V 1 . Diode D 203  together with capacitor C 201  clamps the most positive portion of the horizontal dynamic focus waveform to the voltage at the emitter of transistor Q 201 . The voltage drops across diodes D 202  and D 203  cancel each other, and minimize changes in the clamped output signal due to temperature-dependent changes in the diode VBE. Similarly, diode  201  cancels the VBE drop in transistor Q 401  such that the collector current from Q 401  is zero during the most positive portion of the waveform at the base of transistor Q 401 . This clamps to ground the most negative portion of the waveform appearing in inverted form across resistor R 402 , including that portion or part eliminated during horizontal retrace by switching transistor Q 201 . The ground clamping action maintains a predictable direct voltage or DC if the horizontal dynamic focus waveform amplitude changes, as for example by bus control of Deflection Processor IC  18 .  
         [0017]    The horizontal dynamic focus signals with retrace parabola removed are generated at an output port  24   o  of retrace parabola removal circuit  24  of FIG. 1 a , and are applied to the base of an inverting amplifier including PNP transistor Q 401  and resistors R 401  and R 402 . The amplified horizontal dynamic focus signals (with retrace parabola removed) are capacitively coupled from the collector of transistor Q 401  by way of the series-parallel combination of an AC gain determining resistor R 17  and capacitors C 24  and C 401  to the second input port  22   i   2  of differential amplifier  22 . Differential amplifier  22  produces collector currents from both transistors which are related to the combination of the vertical and horizontal dynamic focus signals. The currents in the collector of transistor Q 6  flow to direct voltage supply V 1  without any effect. The current flow in the collector of Q 5  represents the desired combined dynamic focus signals.  
         [0018]    The “dynamic focus amplifier” designated generally as  17  in FIG. 1 a  includes differential amplifier  22 , a Q 1  Protection Circuit designated as a block  25 , a Q 1  Bias Detector circuit  32 , feedback components R 2  and C 504 , direct-current (DC) gain determining resistors R 5 , R 11 , and R 12 , vertical gain determining components R 301 , C 301 , R 11 , and R 12 , horizontal gain determining components C 401 , C 24 , and R 17 , and surge limiting resistors R 503  and R 25 , all of which are discussed below. Terminal  17   o  is the output port of the dynamic focus amplifier  17 .  
         [0019]    A transistor Q 20  of FIG. 1 a  is connected in a cascode arrangement with transistor Q 5  of differential amplifier  22 , with a low-value surge-protection resistor R 506  therebetween. Transistor Q 20  is a high-voltage transistor with low current gain and high voltage gain. The base of transistor Q 20  is connected by a surge protection resistor R 25  to direct voltage source V 1 , so the emitter of transistor Q 20  can never rise above voltage V 1 . This arrangement also maintains constant voltage at the collector of transistor Q 5 , so there is no voltage change at the collector which can be coupled through the collector-to-base “Miller” capacitance to act as degenerative feedback at higher frequencies, so that transistor Q 5  maintains a broad bandwidth.  
         [0020]    Transistors Q 1  and Q 20  of FIG. 1 a , and their ancillary components, together constitute a portion of high-voltage dynamic focus signal amplifier  17  for amplification of the combined dynamic focus signals. The load on the dynamic focus signal amplifier  17  is largely capacitive and equal to the parallel combination of capacitors C 602 , Cwire, and CT 1  in the CRT(s) which is (are) driven with amplified dynamic focus signal. This parallel capacitance is charged through transistor Q 1  and discharged through transistor Q 20 . In FIG. 1 a , the collector of NPN transistor Q 1  is connected by way of a diode D 501  to receive supply voltage V 2 , and its emitter is connected by way of a resistor R 501  and a zener diode D 4  to the collector of transistor Q 20 . The base of transistor Q 1  is connected by a conductor  60  to the collector of transistor Q 20 . The base of transistor Q 1  is also connected by way of a resistor R 502  to the junction of a capacitor C 501  and the cathode of a diode D 502 . The other end of capacitor C 501 , and the cathode of a zener diode D 503 , are connected to the junction of resistor R 501  with the anode of zener diode D 4 . The cathode of diode D 502  and the anode of zener diode D 503  are connected to output terminal  17   o  of Q 1  bias detector  32 . Resistor R 2  in parallel with capacitor C 504  provide degenerative feedback from a location near the output terminal  17   o  to input port  22   i   2  of differential amplifier  22 .  
         [0021]    In operation of dynamic focus signal amplifier  17  of FIG. 1 a , the collector current of transistor Q 5  is coupled through The emitter-to-collector path of transistor Q 20 , diode D 4 , capacitor C 501  and diode D 502  to the output  17   o  of dynamic focus amplifier  17 . As a result of the current flow from transistor Q 20  to output terminal  17   o , capacitor C 501  charges. The charging continues until the zener or breakdown voltage of zener diode D 503  is reached, after which time D 503  conducts so as to hold the voltage across capacitor C 501  constant and equal to the zener voltage. A small fraction of the collector current of Q 20  flows through resistor R 502 . During conduction of collector current in transistor Q 20 , transistor Q 1  is maintained OFF or nonconductive because the voltage drop across zener diode D 4  reverse-biases the base-emitter junction of transistor Q 1 .  
         [0022]    When collector current in transistor Q 20  of FIG. 1 a  decreases to zero during a portion of the operating cycle of dynamic focus signal amplifier  17 , transistor Q 1  is turned ON or rendered conductive by discharge of capacitor C 501  through resistor R 502 , the base-emitter junction of transistor Q 1 , and resistor R 501  back to capacitor C 501 . With Q 1  conductive, a substantial Q 1  current tends to flow from supply V 2  through diode D 501 , the collector-to-emitter path of transistor Q 1 , resistor R 501 , and forward-biased diode D 503  to the amplifier output terminal  17   o . Overcurrent damage to transistor Q 1  is prevented by a feedback voltage developed across emitter resistor R 501 , which limits the collector current to a value established by the zener voltage of diode D 4  (minus one base-emitter junction voltage) felt across the emitter resistor R 501 , so that Q 1  operates at constant current when the zener voltage is reached. Capacitor C 501  stores sufficient charge to keep Q 1  ON during that entire portion of the amplifier cycle during which Q 20  is OFF, and also to keep Q 1  ON when the collector-to-emitter voltage of Q 1  is low. This allows the maximum positive amplifier voltage to closely approach the voltage of supply V 2 . Resistor R 1 , connected between the positive V 2  supply and output terminal  17   o , precharges capacitor C 501  at start-up so that the cyclic AC pumping operation can start. Diode D 501  in conjunction with resistor R 502  tend to protect transistor Q 1  from overcurrent through its collector-to-base junction in the event of an internal arc in picture tube  12  between the high voltage or ultor terminal  12 U and the focus terminal  12 F.  
         [0023]    Amplifier  17  of FIG. 1 a  may be considered to be a high voltage operational amplifier, at least from the point of view of its output terminal  17   o . In this operational amplifier, resistor R 2  and capacitor C 504  provide feedback from output to input, and resistors R 5 , R 11 , and R 12  set the direct (DC) operating point. Resistor R 17  and capacitor C 24  set the dynamic or AC gain for horizontal-rate dynamic focus signals, while resistors R 301 , R 11 , and R 12  together with capacitor C 301  set the dynamic or AC gain for vertical-rate dynamic focus signals.  
         [0024]    The amplified combined vertical and horizontal dynamic bias signals produced at output port  17   o  of Q 1  Bias Detector  32  of FIG. 1 a  may be viewed as being produced by a low-impedance source. The signals are applied from port  17   o  through a surge limiting resistor R 503  to a first input port  34   i , of a beam current load sensing focus tracking circuit  34  (“combining” circuit  34 ). A second input port  34   i   2  is connected to the ultor terminal  12 U of picture tube  12 , for receiving the ultor voltage. An output port  34   o  of beam current load sensing focus tracking or combining circuit  34  is connected to input port  26   i   1  of focus control block  26 , and possibly to other corresponding focus controls associated with other picture tubes than picture tube  12 , all illustrated together as a block  36 . A cost saving according to one aspect of the invention is achieved over regulated high voltage sources by allowing the high voltage to vary in response to beam current. Thus, high voltage source  49  is not regulated.  
         [0025]    As illustrated in FIG. 1 a , a resistor R 601  is connected in parallel with a capacitor C 601 , and the parallel combination of R 601  with C 601  is connected at one end to input port  34   i , of combining circuit  34 . The other end of the parallel combination of R 601  with C 601  is connected to output port  34   o  of combining circuit  34 . Combining circuit  34  also contains the series combination of a resistor R 602  with a capacitor C 602 , and one end of the series combination is connected to second input port  34   i   2 , while the other end of the series combination is connected to output port  34   o.    
         [0026]    Beam current load sensing focus tracking circuit  34  of FIG. 1 a  may be viewed as a frequency-sensitive combiner, which combines the combined vertical and horizontal dynamic focus signals applied to its first input terminal  34   i   1  with components of the high voltage applied to its second input port  34   i   2 . The resulting combined signals are applied to input port  26   i   1  of focus control block  26  for combination with a “static” component of the focus voltage.  
         [0027]    The focus control  26  and the beam current load sensing focus tracking circuit  34  of FIG. 1 a  can be made by using the following values of components  
                                           R101   50   Megohms       R102   80   Megohms       R601   5.6   Megohms       R602   940   Kilohms       C101   1000   picofarads       C601   470   picofarads       C602   2[00   picofarads                  
 
         [0028]    The stray wiring capacitance is designated as Cwire and has a value of 10 picofarads, and the capacitance CT 1  of the focus electrode of a single picture tube, such as picture tube  12 , is about 25 picofarads. The output impedance of the Q 1  Bias Detector  32  and the resistance of R 503  are ignored as being too small relative to other values to affect the results. Those skilled in the art will recognize that the series capacitor C 602  connected between second input port  34   i   2  and output terminal  34   o  of combining circuit  34  allows only variations or changes (“sag”) in the high voltage to be coupled to output port  34   o . Similarly, the presence of capacitor C 101  connected between input port  26   i   1  of focus control block  26  and tap  28   t  of voltage divider  28  prevents the coupling of direct signal components to the tap  28   t . Capacitor C 101  together with the parallel combination of resistors R 101  and R 102  constitutes a high-pass filter having a cutoff or break frequency of about 5 Hertz (Hz).  
         [0029]    [0029]FIG. 2 is a simplified equivalent circuit or schematic diagram of a television or video display apparatus according to an aspect of the invention in which red, green, and blue cathode-ray or picture tubes are used for the display. The red, green and blue picture tubes are illustrated as blocks  12 R,  12 G, and  12 B, respectively, their ultor terminals are identified as  12 UR,  12 UG, and  12 UB, respectively, and their focus terminals are identified as  12 FR,  12 FG, and  12 FB, respectively. In FIG. 2, elements corresponding to those of FIG. 1 a  are designated by like reference numerals. Elements R 101 , R 102 , and C 101  have appended letters R, G or B to identify corresponding elements associated with the red, green and blue cathode-ray tube displays, respectively. In FIG. 2, a source V_DF represents the combined vertical and horizontal dynamic focus signal source applied to first input port  34   i   1  of combiner  34 .  
         [0030]    Source V_HV of FIG. 2 represents the high or ultor supply voltage source. Voltage source V_HV includes an integrated transformer  250  with a primary winding  250   p . Primary winding  250   p  is connected at one end to a source of regulated B+ and at the other end to a block representing a switching horizontal output transistor. Transformer  250  also includes a distributed secondary winding, including a plurality of windings, each of which is designated  250   s . The distributed secondary winding of transformer  250  is grounded at one end. A set of diodes, some of which are designated as  252 , is interspersed between the winding secondary sections  250   s , and act to rectify the high voltage produced on an output conductor illustrated as  209 . A “static” focus voltage is produced at a tap  250   t  of transformer  250 . In one embodiment of the invention, tap  250   t  is a ⅓ tap relative to the ultor voltage, so that the static focus voltage produced at tap  250   t  is about ⅓ of the high voltage produced on conductor  209 , and remains at a fixed percentage of the ultor voltage.  
         [0031]    The high or ultor voltage V_HV is coupled by way of conductor  209  to terminal  34   i   2  of combining circuit  34 , and to the ultor connections  12 UR,  12 UG, and  12 UB of the red, green, and blue picture tubes  12 R,  12 G, and  12 B, respectively, of FIG. 2, so that combiner  34  and all the cathode-ray tubes are fed in common from the ultor supply V_HV. The static focus voltage is coupled from tap  250   t  by way of a conductor illustrated as  211  to the red, blue and green focus terminals  12 FR,  12 FG, and  12 FB, respectively, by resistive voltage dividers  126 R,  126 G, and  126 B, respectively. Voltage divider  126 R includes series resistor R 101 R and shunt resistor R 102 R having a tap  126 Rt therebetween. Tap  126 Rt is coupled to red picture tube focus terminal  12 FR. Resistor R 101 R has a value of 50 Megohms and resistor R 102 R has a value of 80 Megohms. Similarly, voltage divider  126 G includes series resistor R 101 G and shunt resistor R 102 G having a tap  126 Gt therebetween. Tap  126 Gt is coupled to green picture tube focus terminal  12 FG. Resistor R 101 G has a value of 50 Megohms, and resistor R 102 G has a value of 80 Megohms. Also, voltage divider  126 B includes series resistor R 101 B and shunt resistor R 102 B having a tap  126 Bt therebetween. Tap  126 Bt is coupled to blue picture tube focus terminal  12 FB. Resistor R 101 B has a value of  50  Megohms and resistor R 102 B has a value of 80 Megohms. Thus, each focus terminal  12 FR,  12 FG, and  12 FB of the red, green, and blue picture tubes “sees” its static focus voltage as being sourced from an impedance of about 30 Megohms, just as in the arrangement of FIG. 1 a.    
         [0032]    Output terminal  34   o  of combiner  34  of FIG. 2 is coupled to each of the red, green and blue focus terminals  12 FR,  12 FG, and  12 FB, respectively, by a coupling capacitor C 101 R, C 101 G, and C 101 B, respectively. Each of capacitors C 101 R, C 101 G, and C 101 B has a value of 1000 pF. The capacitance of the red, green and blue picture tubes are designated as CT 1 R, CT 1 G, and CT 1 B, respectively.  
         [0033]    [0033]FIG. 3 b  illustrates a plot  312  of the amplitude of the transfer of the combined vertical and horizontal dynamic focus signal from input port  34   i , of combining circuit  34  to output port  34   o , and FIG. 3 a  illustrates a plot  310  of the relative phase, all over a frequency range extending from 10 Hz to 100 kiloHertz (kHz). As illustrated by plot  312  in FIG. 3 b , the amplitude transfer of the dynamic focus signals includes two major portions, designated as  312   a  and  312   b . Portion  312   a  extends up to about 1 kilohertz (kHz), and portion  312   b  extends above about 3 kHz. Within portion  312   a , about two-thirds (⅔) of the dynamic focus signals are coupled through the combining circuit  34 , and the dynamic focus signals are only slightly attenuated at frequencies above about 3 kHz.  
         [0034]    The vertical-rate dynamic focus parabola signal has a base frequency of 60 Hz, with harmonics extending higher in frequency. Most of the energy of the vertical-rate dynamic focus signals lies below about 1 kHz. In the 60 Hz to 1 kHz frequency range, it is desirable to have nearly flat amplitude response and a log-plot-linear phase response in order to maintain the wave shape. The horizontal base frequency is about 32 kHz (for at least some television displays), with harmonics extending upward in frequency nearly to 1 MHz. In the frequency range extending from about 30 kHz to about 1 MHz, the amplitude response of the dynamic focus signals is desirably to have nearly flat amplitude response, with log-plot-linear phase response, also to maintain wave shape. Phase errors in either the vertical or horizontal dynamic focus signals either distort the waveshape, or move the waveform away from the optimum timing position.  
         [0035]    [0035]FIG. 4 b  illustrates a plot  412  of the amplitude of the transfer of the high or ultor voltage from second input terminal  34   i   2  to output terminal  34   o . As illustrated, plot  412  represents by a portion  412   a  a transfer of about one fifth (⅕) of the high voltage variation or sag through the combining circuit for frequencies below about 1 kHz. Similarly, plot portion  412   b  of plot  412  show little or no transfer or frequencies above about 3 kHz. FIG. 4 b  illustrates by a plot  410  the phase variation of the transferred signal. It would be more desirable to transfer about one third (⅓ of the high voltage variation or sag rather than ⅕ as illustrated. However, the transfer of ⅕ still gives a pleasing picture. The percentage of high voltage sag which is coupled could be increased by making capacitor C 602  smaller, thereby allowing or causing more dynamic focus signal insertion loss below 1 kHz. Such an increased loss could be offset by increasing the gain of the vertical parabola at some point along its path, so long as the peak-to-peak sum of the vertical and horizontal dynamic focus signals is maintained below the V 2  supply voltage.  
         [0036]    Taken together, combining circuit  34  combines about ⅔ of the dynamic focus signal (plot  312   a ) with about ⅕ of the high voltage sag (plot  4   12   a ) at frequencies below about 1 kHz for application to the focus terminal or grid of each of the three picture tubes. The dynamic focus signal components lying below 1 kHz are deemed to be mostly vertical dynamic focus signal components. The high voltage sag signals lying below 1 kHz principally represent changes due to high contrast horizontal video elements.  
         [0037]    Among the features of the described arrangement are relatively low headroom requirements on the dynamic focus amplifier due to the addition of the video-dependent (high-voltage sag) components after or following the dynamic focus amplification, and maintenance of a relatively low impedance dynamic focus drive source so that wiring lead dress is not critical. Good transient response is provided for both dynamic focus signals and video related high voltage sag signals, and phase errors are small enough to prevent noticeable defocused areas in the picture.  
         [0038]    Taken together, combining circuit  34  passes the dynamic focus signals above 30 kHz to the focus terminals without significant attenuation, and essentially none of the high voltage sag. Taking into account that the dynamic focus signals having frequency components at or above 30 kHz are mainly horizontal rate dynamic focus signals, it will be clear that the horizontal dynamic focus signals are coupled without significant attenuation to the focus terminal(s). Such a low-loss coupling of the horizontal-rate dynamic focus signals is advantageous principally in that it allows the dynamic focus amplifier to operate with minimum headroom. The magnitudes of the vertical and horizontal dynamic focus signals at the picture tube terminals are set by the picture tube manufacturer&#39;s specifications. If a loss were to be inserted into the path between the dynamic focus amplifier and the focus terminal(s) of the picture tube(s), as might be occasioned by a filter, then the loss would have to be compensated for by an appropriate increase in dynamic focus amplifier gain and dynamic output range. The increased-magnitude output signal of such an amplifier places more stress on the amplifier components and produces more heat, and the increase in dynamic output voltage may require an increase in the magnitude of the amplifier supply voltage V 2  to avoid signal clipping.  
         [0039]    In addition, the arrangement of FIGS. 1 and 2 with three picture tubes or kinescopes uses but a single high voltage capacitor C 602  and a single high voltage resistor R 602  to couple the ultor source V_HV to the combiner  34 , rather than the three that might otherwise be used. This reduction in the number of expensive high voltage components is accompanied by a reduction in the volume of the potting container and potting compound which are required for use therewith.

Technology Category: 5