Patent Document

RELATED APPLICATIONS 
       [0001]    This application is related to the following: 
         [0002]    U.S. patent application Ser. No. 11/047543, titled “Hybrid-Fet and Its Application As SRAM,” by Mathew, assigned to the assignee hereof, and filed Jan. 31, 2005; and 
         [0003]    U.S. Patent application docket number SC14292TP, titled “A Method of Making an Inverted-T Channel Transistor,” by Mathew et al., assigned to the assignee hereof, and filed even date herewith. 
     
    
     FIELD OF THE INVENTION 
       [0004]    This invention relates to integrated circuits, and more particularly, to a method of making inverted-T channel transistors. 
       BACKGROUND OF THE INVENTION 
       [0005]    The use of FinFETs is very attractive for manufacturing for increasing the density and electrical characteristics of MOS transistors. The fin rises above a substrate to function as the channel so that a major portion of the transistor is vertical and not lateral. The channel direction is lateral but in a structure that is above the surface of the substrate. One of the difficulties, however, has been the ability to adjust the current drive of the transistors, especially to increase the current drive. In a lateral transistor, the current drive is easily adjusted by altering the channel width. One way to increase the channel width is to increase the fin height, but that is generally not practical because the fin height is generally selected to the maximum practical height and the difficulties with the methods that are able to alter fin heights. The generally accepted way to increase current drive is to use more than one fin. Thus, an increase in channel width is conveniently available only in increments of the fin height and requires additional space for each additional fin. The space between fins is desirably small but how small is limited by the pitch limitations of the lithography. 
         [0006]    For some of the same reasons, FinFETs have difficulty in being designed into memory arrays. Memory arrays in particular must be laid out efficiently. This begins with having a compact memory cell. This is particularly difficult with FinFETs because of the difficulty in FinFETs providing the different drive needs with an efficient use of space. 
         [0007]    Thus, there is a need for a technique for providing a more manufacturable FinFET with adjustable current drive, and preferably without having to be in increments of the fin height. Further the FinFets should provide sufficiently flexibility for efficient layout in a memory array. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0008]    The foregoing and further and more specific objects and advantages of the invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the following drawings: 
           [0009]      FIG. 1  is a cross section of a semiconductor device at a stage in a process that is according to an embodiment of the invention; 
           [0010]      FIG. 2  is a cross section of the semiconductor device of  FIG. 1  at a stage in the process subsequent to that shown in  FIG. 1 ; 
           [0011]      FIG. 3  is a cross section of the semiconductor at a stage in the process subsequent to that shown in  FIG. 2 ; 
           [0012]      FIG. 4  is a cross section of the semiconductor at a stage in the process subsequent to that shown in  FIG. 3 ; 
           [0013]      FIG. 5  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 4 ; 
           [0014]      FIG. 6  is a cross section of the semiconductor device at a stage in the process subsequent to that shown in  FIG. 5 ; 
           [0015]      FIG. 7  is a top view of the semiconductor device of  FIG. 6 ; 
           [0016]      FIG. 8  is a cross section of a semiconductor device structure at a stage in a process that is according to an alternative embodiment of the invention; 
           [0017]      FIG. 9  is a cross section of the semiconductor device structure of  FIG. 8  at a subsequent stage in the process; 
           [0018]      FIG. 10  is a cross section of the semiconductor device structure of  FIG. 9  at a subsequent stage in the process; 
           [0019]      FIG. 11  is a cross section of the semiconductor device structure of  FIG. 10  at a subsequent stage in the process; 
           [0020]      FIG. 12  is a cross section of a semiconductor device structure of  FIG. 11  at a subsequent stage in the process; and 
           [0021]      FIG. 13  is a cross section of the semiconductor device structure at a subsequent stage in the process; 
           [0022]      FIG. 14  is a circuit diagram of a 6 transistor SRAM cell that the process of  FIGS. 8-13  is useful in making; and 
           [0023]      FIG. 15  is a top view of a portion of the 6 transistor SRAM cell of  FIG. 14  that the process of  FIG. 8-13  is useful in making. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]    In one aspect a FinFET is made with a lateral extension of the channel so as to increase the current drive of the FinFET. A lateral extension extends adjacent to the fin of FinFET along the surface of the substrate. The gate that overlies the fin also overlies the lateral extension. The lateral extension is defined by a sidewall spacer. The fin is formed by an etch that leaves, in addition to the fin, a floor of semiconductor material that is left over the substrate. The sidewall spacer is formed on both sides of the fin to act as a mask in an etch of the floor of the semiconductor material to leave the lateral extension. The lateral extension is selectable within the range of sidewall spacers widths. Using conventional sidewall formation techniques, the width is easily adjustable from 50 to 1000 Angstroms. The lateral extension thus results in increased current drive that is selectable but not limited to increments corresponding to the fin height. This is better understood by reference to the drawings and the following description. 
         [0025]    Shown in  FIG. 1  is a semiconductor device structure  10  having a substrate  12 , a lateral semiconductor layer  14  over substrate  12 , a fin  16 , and a hard mask  18  overlying fin  16 . Substrate  12  provides physical support for transistors. Substrate  12  is preferably silicon oxide but may be another insulating material or composite of materials. The top of substrate  12  should be an electrical insulator. Fin  16  is formed by an etch using hard mask  18  as a mask. Hard mask  18  is preferably silicon nitride but could be another material or a combination of materials that is effective as an etch mask to the semiconductor material. Photoresist is not likely to be sufficient for this due to the relatively large thickness required for the photoresist. In this example, the semiconductor material is preferably silicon but could be another material such as silicon germanium or gallium arsenide. Lateral semiconductor layer  14  is etched back to leave a desired thickness. The thickness chosen is a design choice based on a variety of known criteria generally analogous to those for choosing the semiconductor thickness in an SOI substrate. The surface of substrate  12  can be considered a horizontal surface so that fin  16  will function as a vertical active region. Similarly, lateral semiconductor layer will function as a horizontal active region. 
         [0026]    Shown in  FIG. 2  is semiconductor device structure  10  after formation of liner  20  over lateral semiconductor layer  20 , hard mask  18 , and fin  20  and formation of sidewall spacer  22  around fin  16 . As is apparent from  FIG. 2 , sidewall spacer  22  is formed after liner  20 . Liner  20  is preferably silicon oxide that is thermally grown but could also be deposited. Sidewall spacer  22  is preferably silicon nitride but could be another material that can function as an etch mask. It does not necessarily have to be an insulator because it will be removed. 
         [0027]    Shown in  FIG. 3  is semiconductor device  10  after etching lateral semiconductor layer  14  using sidewall spacer  22  as a mask. This is preferably an anisotropic etch such as a chlorine plasma. This etch exposes sides of lateral semiconductor layer  14  that remains. 
         [0028]    Shown in  FIG. 4  is semiconductor device  10  after growing an oxide layer  24  on the sides of lateral semiconductor layer  14 . The purpose is to protect lateral semiconductor layer  14  during the subsequent sidewall spacer removal process. 
         [0029]    Shown in  FIG. 5  is semiconductor device  10  after removing sidewall spacer  22 , oxide layer  24 , liner  20 , and hard mask  18 . All of these removed features are selectable selectively etchable with respect to silicon. The etches are preferably wet etches because there is no need for an anisotropic etch. Dry etches that are isotropic or anistropic may also be used. 
         [0030]    Shown in  FIG. 6  is semiconductor device  10  after formation of a gate dielectric  26  and a gate  28  on gate dielectric  26 . Gate dielectric  26  is preferably formed by a high temperature growth of silicon oxide which is a common approach for forming a gate dielectric. Other gate dielectrics such as high k dielectrics such as hafnium oxide could also be used. Such high k dielectrics would be deposited rather than grown. The source and drain of semiconductor device  10  is formed in conventional fashion for a FinFET. 
         [0031]    Shown in  FIG. 7  is an orthogonal view of semiconductor device  10  of  FIG. 6  that shows a source/drain region  30  on one side of gate  28  that has the conventional elevated portion but in this example also includes a portion of lateral semiconductor layer  14 . Similarly a source/drain region  32  that is on the other side gate  28  has the conventional elevated portion but also a portion of lateral semiconductor layer  14 . This shows that the horizontal active region aspect of lateral semiconductor layer  14  is for source, drain, and channel. Gate dielectric  26 , not separately shown in  FIG. 7 , covers source/drains  30  and  32 , lateral semiconductor layer  14 , and fin  16 . 
         [0032]      FIGS. 6 and 7  thus show a transistor that has both a fin for a channel and a lateral portion as a channel. The lateral portion is adjustable by adjusting the width of sidewall spacer  22 . The greater the width of lateral semiconductor layer  14  that remains after the etch, the greater the current drive capability of the resulting transistor. The resulting transistor thus has a greater gain than just a single fin device but does not require all of the area over substrate  12  that would be required by adding an additional fin. Further the gain and the consequent current drive is selectable within any of the available sidewall spacer widths. In effect any gain is selectable because additional fins can still be added with only a certain one or certain ones having a lateral semiconductor layer with a selected width. 
         [0033]    Shown in  FIG. 8  is semiconductor device  50  having a substrate  52 , a lateral semiconductor layer  54 ; a fin  56 ; a fin  58 ; a fin  60 ; a hard mask  62  on fin  56 ; a hard mask  64  on fin  58 ; a hard mask  66  on fin  60 ; a liner  68  over fins  56 ,  58 , and  60 , lateral semiconductor layer  54 , and hard masks  62 ,  64 , and  66 ; a sidewall spacer  70  around fin  56 ; a sidewall spacer  72  around fin  58 , and a sidewall spacer  74  around fin  60 . The preferred materials and options for semiconductor device  50  of  FIG. 8  are the same as described for semiconductor device  10 . In effect at this point in the processing, there are three devices that are the same as shown in  FIG. 2 . 
         [0034]    Shown in  FIG. 9  is a semiconductor device structure  50  after performing an etch using sidewall spacers  70 ,  72 , and  74  as masks analogous to the transition from  FIG. 2  to  FIG. 3 . This results in three device structures each having a separate portion of lateral semiconductor layer  54 . Although the etch separates the three device structures, a photoresist mask can be used to prevent the etch of lateral semiconductor layer  54  in other locations not shown. For example, the area where lateral semiconductor layer  54  contacts source/drain regions may be an area that will contact a source/drain region of another transistor. In that area, a photoresist mask can be applied to maintain that contact. A subsequent silicide treatment is effective for ensuring an effective electrical contact between the joined source/drains. 
         [0035]    Shown in  FIG. 10  is semiconductor device structrure  10  after forming a mask  76  and a mask  78 . Mask  76  is formed over fin  56  and lateral semiconductor layer  54  thereunder so that sidewall spacer  70  on both sides of fin  56  are covered. Mask  78  is from fin  60  to one side of fin  60  extending over lateral semiconductor layer  54  and sidewall spacer  74  on the covered side. Thus sidewall spacer  74  on the other side of fin  60  is exposed. There is no mask over fin  58  so that sidewall spacer  72  is exposed. Fin  60  is preferably about 200 Angstroms so that alignment thereto is repeatably attainable. 
         [0036]    Shown in  FIG. 11  is shown semiconductor device structure  40  after removing the sidewall spacer  72  and a portion of sidewall spacer  74  on a side  80  of fin  60 . With sidewall spacer  72  removed, liner  68  is then removed and lateral semiconductor layer  54  that was under sidewall spacer  72  is then removed by etching. Similarly, liner  68  under the portion of sidewall spacer adjacent to side  80  is removed and lateral semiconductor layer  54  under the portion of sidewall spacer adjacent to side  80  is removed. Masks  76  and  80  are maintained during the etch of liner  68  and lateral semiconductor layer  54  because there may be other masks in other locations not shown in  FIG. 11  that are protecting against an etch of a portion of lateral semiconductor layer  54 . 
         [0037]    Shown in  FIG. 12  is a semiconductor device structure  50  after removal of sidewall spacer  70 , sidewall spacer  74  that remained, and liner  68 . Fins  56 ,  58 , and  60  and lateral semiconductor layer  54  that remains are thus exposed. 
         [0038]    Shown in  FIG. 13  is semiconductor device structure  50  after growing gate dielectrics  84 ,  86 , and  88  and forming gates  90  and  92 . This results in transistors  94 ,  96 , and  98 . Transistor  94  uses fin  56  as a vertical active region and lateral semiconductor layer  54  that is connected to fin  56  results in an inverted-T channel transistor analogous to semiconductor device  10  of  FIGS. 6 and 7 . Gate dielectric  84  coats the semiconductor structure of transistor  94 . Gate dielectric  86  coats fin  58 . Gate dielectric  88  coats the semiconductor structure of transistor  98 . Transistor  96  is has the resulting structure of a conventional FinFET made by a process integrated with the formation of transistors  94  and  96 . Transistors  94  and  96  share the same gate layer  90  that serves as the gates for both. Transistor  98  has a horizontal active region half that of transistor  94 . This is a particularly convenient combination for use as an SRAM cell. 
         [0039]    Shown in  FIG. 14  is a circuit diagram of a SRAM cell  100  using transistors made using transistors like transistors  94 ,  96 , and  98 . SRAM cell  100  comprises N channel transistors  102 ,  104 ,  110 , and  112  and P channel transistors  106  and  108 . The circuit configuration is conventional. Transistors  102  and  104  are pull-down transistors, transistors  106  and  108  are pull-up transistors, and transistors  110  and  112  are pass transistors. Transistors  102  and  106  are coupled together as one storage node, transistors  104  and  108  are coupled together at another storage node. Each pair of transistors sharing a storage node form an inverter. The storage portion of SRAM cell  100 , where a bit is maintained, comprises the two inverters being cross-coupled in a latching arrangement. Pass transistors  110  and  112  are both connected to a word line  111  and, when word line  111  is enabled, connect bit lines  114  and  116  to the storage portion of SRAM cell  100 . Transistors  110  and  112  are made to be like transistor  98  of  FIG. 13 . Transistors  106  and  108  are made to be like transistor  96 . Transistors  102  and  104  are made to be like transistor  94 . 
         [0040]    Shown in  FIG. 15  is a top view of a portion  120  of SRAM cell  100  showing transistors  102 ,  106 , and  110  connected as shown in the circuit diagram of  FIG. 14 . Portion  120  comprises fins  122 ,  124 , and  130 . Fins  122  and  130  are parallel. Fin  124  has one end connected to fin  122  and another end connected to an end of fin  130  where there is a contact region  128 . Contact regions for fins, in this example, are the same height as the fin but wider. A gate electrode  138 , analogous to gate electrode  92  of  FIG. 13 , passes over fin  122  between a contact region  134  and the location where fin  124  joins fin  122 . This gate electrode is connected to word line  111  which runs in a metal line in an interconnect layer above portion  120  so is not shown in  FIG. 15 . At the location where gate electrode  138  passes over fin  122 , a lateral semiconductor layer  142  extends laterally from fin  122  at the bottom of fin  122 . Lateral semiconductor layer  142  is analogous to lateral semiconductor layer  54  that adjoins fin  60  in  FIG. 13 . Thus, fin  122 , gate electrode  138 , and lateral semiconductor layer  142  are used to form transistor  110  to be like transistor  98 . Contact region  134  is used to make a contact to bit line  114  as shown in  FIG. 14 . Bit line  114  runs as a metal line in an interconnect layer above portion  120  so is not shown in  FIG. 15 . 
         [0041]    Transistors  102  and  106  are constructed similarly to achieve the types of transistors  94  and  96 , respectively. Fin  122  in the area below fin  124  has lateral semiconductor layer  142  on both sides. Fin  130 , on the other hand, does not have lateral semiconductor layer  142  adjoining it. A gate electrode  140 , analogous to gate electrode  90  of  FIG. 13 , passes over fins  130  and  122 . Gate electrode  140  passes over fin  122  in a location between fin  124  and a contact region  136  so it passes over lateral semiconductor layer  142  on both sides of fin  122 . Gate electrode  140  passes over fin  130  between contact region  128  and a contact region  132 . Gate electrode  140  passing over fin  122  and lateral semiconductor layer  142  on both sides of fin  122 , results in a transistor structure like transistor  94  in  FIG. 13 . Gate electrode  140  passing over fin  130 , which does not have a lateral semiconductor layer, results in a transistor structure like transistor  96  in  FIG. 13 . Contact region  136  is used to contact ground potential. Contact  132  is used to contact the positive power supply, VDD. Contact  128  is used to contact the gates of transistors  104  and  108 . Fin  124  provides the contact between the drains of transistors  102  and  106 . Thus, portion  120  efficiently provide the circuit connection for transistors  102 ,  106 , and  110  of  FIG. 14 . Further this layout can be propagated to form an SRAM layout using symmetrical representations of portion  120 . 
         [0042]    Portion  120  is one use of the three transistor types shown in  FIG. 13  to avoid having to use additional fins to achieve additional current drive. In the example of portion  120 , the N channel pass transistors  106  and  108  are increased in current drive from that of just a single fin by adding a lateral semiconductor layer on just one side of the fin. Generally it is considered desirable for the pull-down transistors  102  and  104  to have more current drive than the pass transistors. If the pass transistors need to have even less current drive in comparison to the pull-downs, the lateral semiconductor layer can be removed. Similarly, if the P channel pull-up transistors need more current drive, a lateral semiconductor layer can be added to the P channel fin on one side or even both sides. The three transistor types of  FIG. 13  thus give flexibility in adjusting the current drives of the three transistor types (pull-down, pull-up, and pass) that make up an SRAM cell to achieve the desired ratios of those current drives. The flexibility of the three transistor types of  FIG. 13  may alleviate the need for putting fins in parallel but even if the current drive requirements are so high as to require multiple fins, the three transistors types of  FIG. 13  can be used in conjunction with transistors requiring multiple fins to reduce the number of fins that need to be added and/or provide. current drive ratios that are closer to the ideal ratios. 
         [0043]    Various other changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. For example, a particular benefit was shown for SRAM cells, but other circuit types may also benefit. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.

Technology Category: h