Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims benefit from U.S. Provisional Patent Application Ser. No. 60/821,252 filed on Aug. 2, 2006, the entire content of which is incorporated herein by reference. 
     
     BACKGROUND OF THE INVENTION 
       [0002]    Full-duplex RF front-ends in WLAN networks require careful design to limit receive desensitization due to transmit noise and transmit error vector magnitude (EVM) degradation caused by receiver local oscillator (LO) leakage to the transmit path. In addition, frequency pulling is a concern in full duplex systems where receive and transmit voltage-controlled oscillators (VCOs) must operate simultaneously and be close in frequency. 
         [0003]    As a consequence, such full-duplex systems and many other applications, require two driving signals, typically referred to as I and Q or quadrature signals, having the same frequency and having their phases in quadrature with each other, i.e. presenting a relative phase offset of 90°. It is important that these quadrature signals I and Q are balanced in amplitude, i. e. have substantially the same amplitude, and that the phase error from the desired 90° phase shift is as small as possible. 
         [0004]    Such signals are commonly generated by frequency doublers. However, many state-of-the-art frequency doubling circuits introduce amplitude mismatch and quadrature phase offset between the quadrature signals. 
         [0005]      FIG. 1   a  illustrates a state-of-the-art frequency doubler producing quadrature signals. A voltage controlled oscillator (VCO)  100  is used to create a differential sinusoidal output  101  and  102 . These signals are input into a polyphase filter  110 , which is an arrangement of resistors and capacitors interconnected in such a way so as to produce two quadrature differential outputs. Outputs  120  and  121  are referred to as cos(ωt) and −cos(ωt), respectively, while outputs  122  and  123  are referred to as sin (ωt) and −sin(ωt), respectively. In mixer  130 , the cos(ωt) terms are multiplied together, yielding cos(2ωt). Since cos(2ωt)=2 cos(ωt)−1, the output of mixer  130  is equal to ½ cos(2ωt)+½. In this scheme, the mixing term resulting from squaring the polyphase filters in-phase signal (mixer A  130 ) will have a DC offset, preferably removed with a tuned load to ensure matched mixer bias conditions and minimal phase error. Unfortunately, tuned loads consume die space and limit circuit bandwidth. Also, the outputs of the polyphase filter are not equally loaded. This unbalanced loading leads to quadrature phase error. 
         [0006]    An attempt to address the issues of having a bulky tank circuit and an unbalanced polyphase filter load present with the doubler in  FIG. 1   a  are addressed via the topology shown in  FIG. 1   b . In this embodiment, mixer  140  multiplies cos(ωt) by itself, yielding cos 2 (ωt). Mixer  141  multiplies sin(ωt) by itself, yielding sin 2 (ωt). The output of mixer  141  is subtracted from the output of mixer  140 , yielding 
         [0000]        I =cos 2 (ω t )−sin 2 (ω t )=cos(2 ωt ) 
         [0007]    Similarly, mixer  142  and mixer  143  both multiply sin(ωt) by cos(ωt), yielding sin(ωt)cos(ωt). These terms are summed yielding 
         [0000]        Q =2 sin(ω t )cos(ω t )=sin(2 ωt ) 
         [0008]    However, the circuit in  FIG. 1   b  introduces considerable amplitude imbalance when mixer non-linearities are considered. This occurs because the conversion gain of each mixer is a function of the relative phase offset of its input signals. 
         [0009]    The dependence of the conversion gain on the relative phase offset can be explained by way of example considering a simple Gilbert mixer implementation as in  FIG. 2 . In this Gilbert mixer, the output voltage, V out  can be expressed as a function of the two input voltages, V quad  and V in , as follows: 
         [0000]        V out=( R   L   V   in   /R   E )tan  h ( V   quad /2 V   T ) 
         [0000]    where V T  is the thermal voltage of the transistor, given by kT/q. 
         [0010]    Returning to  FIG. 1   b,  assume that each of the mixers  140 - 143  is implemented as a Gilbert mixer. Mixers  140  and  141  each multiply a signal by itself thus their inputs are in-phase, while mixers  142  and  143  multiply two signals which are in quadrature. Thus the peak output of mixers  140  and  141  occurs when the input sinusoid achieves its peak value. At the input peak, the tan h(V quad /2V T ) term in (1) introduces compression due to the nonlinearity of the mixing quad devices M 1  to M 4  in  FIG. 2 , when V quad &gt;&gt;V T . 
         [0011]    On the other hand, mixers  142  and  143  reach their maximum value when each of its inputs are at 1/√2 of their peak value. The harmonics introduced by the mixing quad compression are dependent upon the input phase such that when vector summed to give the mixer output, the conversion gain will be higher for orthogonal inputs compared to when the two inputs are in-phase. The result is that the amplitude of the I output will be lower than the amplitude of the Q output, an unacceptable imbalance when used in a doubler design to provide the LO in an image reject mixer. 
         [0012]      FIG. 3  illustrates the simulated conversion gain (with respect to the input port, V in ) of the Gilbert mixer shown in  FIG. 2  as a function of the phase offset, θ, at its input ports. A q  is the peak differential drive level on the mixing quad while A i  is held constant at 100 mV. For low input levels where A q &lt;&lt;V T , tan h (V quad /2V T )=V quad /2V T  and the conversion gain shows minimal sensitivity to input phase. This implies drive levels too low to be useful for driving mixer LO ports, and subsequently a high noise floor. As A q  is increased, the conversion gain begins to saturate with respect to the quad drive level but exhibits increasing phase sensitivity. As shown, the worst case mismatch occurs when the input sinusoids are in quadrature, as used in the doubler topology shown in  FIG. 1   b.    
         [0013]    The zero crossings at each differential pair in the mixer are not affected by the mixing quad nonlinearity and hence a phase error is not introduced. In practice large signal effects in the presence of this nonlinearity will cause mixer imbalances resulting in slight phase offsets. 
         [0014]    If the topology in  FIG. 1   b  is used, the outputs will exhibit amplitude imbalance proportional to the drive level at the polyphase filter input owing to the aforementioned mixer nonlinearities. 
         [0015]    To minimize the mixer distortion, one approach has been to attempt to linearize each mixer&#39;s conversion gain with respect to the mixer quad inputs. Knowing that the output of the Gilbert mixer is proportional to tan h (V quad ), the mixer output can be linearized by applying an inverse tan h function to predistort the V quad  input. However, this approach presupposes a wide dynamic range predistortion circuit. Process variations will cause such a circuit to contribute to output phase and amplitude imbalance. 
         [0016]    Therefore, an improved frequency doubling circuit is needed to reduce the amplitude imbalance between quadrature signals. Such a circuit would minimize transmissions occurring at the image frequency, thereby improving the receiver performance of a wireless communication device. Additional, although amplitude mismatch is a major source of error, phase offset between the quadrature signals represents another source of error. Thus, a phase shifter circuit that reduces the phase error between two quadrature signals can further minimize transmissions occurring at the image frequency. A method of calibrating such a phase shifter to compensate for process, temperature and supply voltage variation would provide further advantages. 
       SUMMARY OF THE INVENTION 
       [0017]    A frequency doubler circuit and a frequency doubling method are provided. The frequency doubler circuit comprising an adder block, a first mixer block and a second mixer block. The adder block produces a plurality of intermediate phase shifted signals of frequency ω based on input differential quadrature signals of frequency ω. The two mixer blocks receive the intermediate phase shifted signals and produce in-phase signal I in  of frequency 2ω and quadrature signal Q in  of frequency 2ω. 
         [0018]    In accordance to a preferred embodiment, the frequency doubler of the present invention further comprises a phase shifter for further reducing phase errors between the two quadrature signals of frequency 2ω. 
         [0019]    A frequency doubling method and a phase shifting method are also provided. 
         [0020]    Advantageously, the frequency doubler circuit and frequency doubling method of the preferred embodiments of the invention produce quadrature signals of substantially same amplitude and with minimal phase error form the desired phase quadrature relationship. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIGS. 1   a  and  1   b  illustrate two embodiments of frequency doubling circuits in the prior art; 
           [0022]      FIG. 2  illustrates one embodiment of a Gilbert mixer in the prior art; 
           [0023]      FIG. 3  represents a graph illustrating the effect of phase offset to amplitude in the Gilbert mixer of  FIG. 2 ; 
           [0024]      FIG. 4  illustrates an embodiment of the frequency doubling circuit and phase shifter of the present invention; 
           [0025]      FIG. 5  illustrates an embodiment of the adder used in  FIG. 4 ; 
           [0026]      FIG. 6  illustrates an embodiment of the single-sideband mixer used in  FIG. 4 ; 
           [0027]      FIG. 7  illustrates an embodiment of the phase shifter used in  FIG. 4 ; and 
           [0028]      FIG. 8  illustrates the performance metrics of embodiments of the invention according to  FIGS. 4-7  compared to the circuit in  FIG. 1   b.    
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0029]    In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. 
         [0030]    Essentially, the present invention attempts to alleviate problems of the prior art in a manner with little sensitivity to manufacturing deviations, by providing a frequency doubling circuit and method for obtaining quadrature signals, in which inputs of substantially same phase offset are provided to mixers of the provided circuits or, equivalently, are mixed together within the provided method. 
         [0031]      FIG. 4  illustrates a representative embodiment of a frequency doubler  10  according to the present invention. Frequency doubler  10  comprises a voltage controlled oscillator (VCO)  200 , a polyphase filter  210 , an adder block  220  and mixer blocks  230 ,  231 . Preferably, it further comprises a phase shifter  240 . A VCO (voltage controlled oscillator)  200  having differential outputs is fed into a polyphase filter  210 . In  FIG. 4 , polyphase filter  210  is a two stage polyphase filter used to generate 2 pairs of differential quadrature signals. However, those skilled in the art are aware that other types of filters, and other circuits are also possible to carry out this function. For example, a quadrature VCO could be used at the expense of increased power consumption and an additional tank circuit. In  FIG. 4 , the two pairs of differential quadrature signals are: sin(ωt) and −sin(ωt), and cos(ωt) and −cos(ωt). These four signals are fed to adder block  220 , which creates four π/4 shifted signals, i.e. signals having their phases separated by 45° (or π/4). Specifically, these π/4 shifted signals are represented as sin(ωt), sin(ωt+π/4), cos(ωt), and cos(ωt+π/4). Advantageously, each output from the polyphase filter  210  is equally loaded, that is, each output is connected to the same effective impedance with respect to circuit ground, thereby reducing the phase offset commonly introduced by load imbalance. Within the adder block  220 , the four π/4 shifted signals are generated based on the following trigonometric identities: 
         [0000]      sin (ω t+π/ 4)=(cos(ω t )+sin(ω t ))/√2   (1) 
         [0000]      sin (ω t )=(sin(ω t )+sin(ω t ))/2   (2) 
         [0000]      cos (ω t )=(cos(ω t )+cos(ω t ))/2   (3) 
         [0000]      cos (ω t+π/ 4)=(cos(ω t )−sin(ω t ))/√2   (4) 
         [0032]    Within the adder block  220 , four adders  250 ,  251 ,  252  and  253  and four gain stage  254 ,  255 ,  256 ,  257  are used to implement equations (1)-(4) above. Specifically, adder  250  implements equation (1), and the gain stage  254  is used to reduce the amplitude of the adder  250  output by 1/√2. Similarly, adder  253  implements equation (4) above. To change the adder into a subtractor, the differential inputs associated with sin(ωt) are simply reversed. Adders  251  and  252  implement equations (2) and (3) respectively. Although adders  251  and  252  simply add a signal to itself and then divide it by two, they are advantageously used to match the delays introduced by adders  250  and  253 . 
         [0033]    Based on the four π/4 shifted signals, mixer blocks  230  and  231  generate in phase and quadrature outputs, I in  and Q in , respectively, based the following identities: 
         [0000]        I   in =cos(2ω t+π/ 4)=(cos(2 ωt )−sin(2 ωt ))/√2   (5) 
         [0000]        Q   in =sin(2 ωt+π/ 4)=(cos(2 ωt )+sin(2 ωt ))/√2   (6) 
         [0000]        I   in =cos(ω t )cos(ω t+π/ 4)−sin(ω t )sin(ω t+π/ 4)=(cos(2 ωt )−sin(2 ωt ))/√2   (7) 
         [0000]        Q   in =cos(ω t )sin(ω t+π/ 4)+sin(ω t )cos(ω t+π/ 4)=(cos(2 ωt )+sin(2 ωt ))/√2   (8) 
         [0034]    Equations (6) and (8) are implemented by mixer block  230 , comprising mixers  260  and  261 , while equations (5) and (7) are implemented by mixer block  231  comprising mixers  262  and  263 . The inputs to mixers  260 ,  261 ,  262  and  263  are all at the same relative phase offset, specifically 45° (or π/4). This implies that the non-linearity effects will be equal for all of the mixers, resulting in much less amplitude mismatch between the I in  and Q in  signals, especially as compared to the circuit in  FIG. 1   b.    
         [0035]    Note that the cos(ωt+π/4) input to mixer  261  is inverted, −cos(ωt+π/4) being used as input, in order to maintain the required phase offset. The output of mixer  261  is further subtracted from the output of mixer  260  to counter the effect of using −cos(ωt+π/4) term in mixer  261 . 
         [0036]    Although the preferred embodiment uses 45° phase offsets for all mixers, it should be noted that this is not essential. The same functionality is achievbed with mixer inputs of arbitrary phase offset θ provided the input phase offset is the same for each of mixers  260 ,  261 ,  262  and  263  and the relative phases between each of the four mixers is as given in (5)-(8). 
         [0037]    Additionally, in all of these cases, the maximum amplitude output level of the mixers is identical, as is the frequency content. Specifically, each mixer output contains a cos(2ωt) component a sin(2ωt) component and a DC offset. The outputs of mixers  260  through  263 , respectively, can be expressed as follows: 
         [0000]      (cos(2t)+sin(2ωt)+1)/2√2 
         [0000]      (cos(2ωt)+sin(2ωt)−1)/2√2 
         [0000]      (−cos(2ωt)+sin(2ωt)+1)/2√2 
         [0000]      (cos(2ωt)−sin(2ωt)+1)/2√2 
         [0038]      FIG. 5  illustrates a representative circuit embodiment of an adder, as used in the adder block  220 . In this embodiment, differential pair V in1  feeds the bases of transistors M 1  and M 2 . Similarly, the differential pair V in2  feeds the bases of transistors M 3  and M 4 . The gain of this adder is defined as G=R LA /R EA . Transistors M 5  and M 6  are emitter followers, used to make the adder insensitive to output loading. Ideally, the gain for adders  250  and  253  should be 1/√2, and the gain for adders  251  and  252  should be ½. However, more adder gain may be necessary when implementation loss is considered. The load R LA  is preferably the same for all four adders, and the gain ratio is set by varying R EA  as desired. This minimizes the variation in adder phase shift due to the RC filter formed by the load resistors and the parasitic output capacitances. 
         [0039]    While the adder block  220  of  FIG. 4 , and the implementation of the adder and gain stage shown in  FIG. 5  are the preferred embodiment, the invention is not so limited. Those skilled in the art are aware that other circuits can be utilized to create four signals whose phases are in 45° increments. 
         [0040]      FIG. 6  shows a representative implementation of mixer elements  230  and  231 . Transistors M 1  through M 4 , M 9  and M 10  form a typical Gilbert mixer, similar to that configuration shown in  FIG. 2 . Similarly, transistors M 5  through M 8 , M 11  and M 12  form a second Gilbert mixer. Transistors M 15  through M 18  are used to create constant current sources. By connecting the collectors of M 1 , M 3 , M 5  and M 7  together, and the collectors of M 2 , M 4 , M 6  and M 8  together, the outputs of these two mixers are then summed. A tuned load is not required since the input signal phases are such that no DC offset will be output by the circuit. Preferably, Ports A through D are biased with four separate high pass RC filter networks. Although the adder outputs (such as driven by the circuit of  FIG. 5 ) will have a common mode level suitable to drive ports A and D, ports B and C require level shifting to a higher voltage. (Note the higher DC offset required for the transistors M 1  through M 4  in the Gilbert mixer of  FIG. 2 ). Any level shifter used for ports B and C will introduce phase shift that must be matched at ports A and D. Alternatively, two sets of followers, one for each common mode level required, could be used at the expense of power consumption and increased common mode voltage mismatch. To minimize the effects of output loading, transistors M 13  and M 14  are used as emitter followers. 
         [0041]    In summary, within frequency doubler  10 , VCO  200 , polyphase filter  210 , adder block  220  and mixer blocks  230  and  231  combine to create quadrature outputs Q in =sin(2ωt+π/4) and I in   32  cos(2ωt+π/4) having far less amplitude mismatch between them, compared to prior art circuits, due to producing 45° shifted signals and using them as inputs to mixer blocks  230  and  231  as described above. 
         [0042]    In the preferred embodiment of  FIG. 4 , the polyphase filter  210  is the largest source of phase error. In an alternate embodiment, lower phase errors can be achieved when a quadrature VCO topology is used. In such a case, there would be no need for polyphase filter  210 , as the outputs from a quadrature VCO can be used directly as the inputs to adder block  220 . The consequence of this is an additional resonant tank circuit, regenerative cell and power consumption. 
         [0043]    It is possible to further reduce the phase error introduced, using the phase shifter  240  shown in  FIG. 4 . With careful layout, the typical quadrature output phase error will be less than 1°. Thus, some means of achieving programmable phase shifts on the order of ±5° are required to compensate for phase errors caused by device mismatch as well as variations in process, temperature and supply voltage. 
         [0044]    As described above, the output from mixer element  230  is Q in =sin(2ωt+π/4), while the output from mixer element  231  is I in =cos(2ωt+π/4). Assume that the phase error between the quadrature signals is represented by θ. To bring these signals back to exactly 90° separation, the phase of one signal can be increased by θ/2, while the phase of the other signal can be decreased by θ/2. Thus, the required outputs from the phase shifter can be expressed as: 
         [0000]        Q   out =sin(2 ωt+π/ 4+θ/2) 
         [0000]        I   out =cos(2 ωt+π/ 4−θ/2) 
         [0045]    Expanding the above expressions yields: 
         [0000]        Q   out =sin(2 ωt+π/ 4)cos(θ/2)+cos(2 ωt+π/ 4)sin(θ/2) 
         [0000]        I   out =cos(2 ωt+π/ 4)cos(θ/2)+sin(2 ωt+π/ 4)sin(θ/2) 
         [0046]    At very small values of w (consistent with small phase errors), it can be approximated that sin(θ) ˜θ, and cos(θ) ˜1. Thus, these expressions can be rewritten as: 
         [0000]        Q   out =sin(2 ωt+π/ 4)+cos(2 ωt+π/ 4)(θ/2) 
         [0000]        I   out =cos(2 ωt+π/ 4)+sin(2 ωt+π/ 4)(θ/2) 
         [0047]    Renaming the terms in the above equations yields: 
         [0000]        Q   out   =Q   in   +I   in (θ/2) 
         [0000]        I   out   =I   in   +Q   in (θ/2) 
         [0048]    Therefore, the required phase shift can be introduced by adding a small fractional portion of the quadrature signal to the inphase signal and vice versa. This is illustrated in phase shifter  240  of  FIG. 4 . Iin passes through a gain stage  273 , and the resulting output is then added to Qin as shown in adder  270  to generate Q out . Similarly, Q in  passes through a gain stage  272 , and the resulting output is then added to I in  as shown in adder  271  to generate I out . 
         [0049]      FIG. 7  shows the preferred embodiment of the phase shifter  240  of  FIG. 4 . Q in  feeds the bases of transistors Q 1  and Q 2 . The collectors of these transistors are connected to a power rail through matched resistors, RL. The collector of Q 1  is also connected to the collectors of Q 3  and Q 5 , while the collector of Q 2  is connected to the collectors of Q 4  and Q 6 . The bases of Q 3  and Q 6  are fed by one polarity of I in , while the bases of Q 4  and Q 5  are fed by the opposite polarity of I in . Thus, transistor pairs Q 3 /Q 4  and Q 5 /Q 6  are set up as a subtraction circuit, such that Q 3 /Q 4  adds a first portion of I in  to Qin, while Q 5 /Q 6  subtracts a second portion of I in  from Q in . Rather than having a constant current source, the emitters of Q 3  through Q 6  are connected to a variable current source. A voltage is applied to the collector and base of transistor Q 7 , which generates a specific current. Transistors Q 8  and Q 17  are set up as current mirrors. In the preferred embodiment, Rd2 is larger than the value of Rd1. Thus, the current passing through Q 8  and Q 17  is a portion of the current passing through Q 7 . Alternatively, instead of using a ratio of base resistors to create the necessary small current flows, a smaller voltage can be delivered from the DAC. 
         [0050]    A similar current mirror also exists with transistors Q 9 , Q 10  and Q 18 . In the case where the voltage applied to the base of Q 7  is equal to that of Q 10 , the outputs from the transistor pairs cancel, thus leaving Q out =Q in . However, if the voltage applied to the base of Q 7  is slightly greater than that applied to the base of Q 10 , the net result is that a small portion of the I in  signal will be added to Q in . Conversely, if the voltage applied to the base of Q 7  is slightly smaller than that applied to the base of Q 10 , the net result is that a small portion of the I in  signal will be subtracted from Q in . For the lower transistor quad, if the voltage applied to the base of Q 7  is slightly greater than that applied to the base of Q 10 , the net result is that a small portion of the Q in  signal will be added to I in . Conversely, if the voltage applied to the base of Q 7  is slightly smaller than that applied to the base of Q 10 , the net result is that a small portion of the Q in  signal will be subtracted from I in . 
         [0051]    In the preferred embodiment, these voltages applied to the bases of Q 7  and Q 10  are created using a DAC (digital-analog converter). However, those skilled in the art will appreciate that other methods of generating variable currents are well known and the present invention is not limited to this embodiment. For example, in another embodiment, an analog feedback loop may be used to autozero the phase error. 
         [0052]    In the preferred embodiment shown in  FIG. 7 , a static 5-bit current steering DAC is used to create binary weighted currents, ΔI and −ΔI, which are added to a constant bias current I DAC . A small phase step and adequate range is desirable if the doubler is used to provide the oscillator for a single sideband mixer. If the tuning range is too wide and discrete steps are used, the reciprocal dependence of the mixer sideband rejection on phase error can considerably lower the average achievable sideband rejection. 
         [0053]    The phase shifter is a major source of amplitude variation and harmonic distortion due to the non-linear input pairs Q 1 , Q 2  and Q 11 , Q 12 . This configuration yields the tan h relationship described above. If a constant output level is desired, these input pairs can be degenerated by the addition of resistors between the emitters of these transistors and the constant current source IB. 
         [0054]      FIG. 8  illustrates some advantages provided by embodiments of the present invention, such as the circuits in  FIGS. 4-7  (with corresponding curves referred to as “proposed” in the drawing) with respect to the circuit in  FIG. 1   b  (with corresponding curves referred to as “Topology B”, in the drawing). The horizontal axis of the three graphs represents the VCO drive level, expressed as volts peak differential. The vertical axis of the bottom graph represents phase error in degrees, the middle graph represents output level in dB, while the horizontal axis of the top graph represents the amplitude mismatch between the quadrature signals, expressed in dB. 
         [0055]    Calibration of the circuit in  FIG. 7  is possible, even during normal operation. Amplitude mismatch and phase error of the quadrature signals affect the amplitude of the image frequency in full-duplex wireless circuits. Therefore, by monitoring the amplitude of the image frequency transmitted, the circuit can determine the optimal setting for the phase shifter circuit. Specifically, the amplitude of the image frequency is sampled, such as by a baseband processor. The phase offset is then altered, preferably by changing the DAC input. The amplitude is then sampled again. This process can be repeated for each possible value of the DAC. Once this has been completed, the system can determine which DAC value, and therefore which phase setting, created the image frequency with the smallest amplitude. This value is then stored in the DAC and used. This calibration routine can be performed once, such as when power is first applied to the device, or can be performed periodically to adapt to changes in operating conditions. 
         [0056]    Referring first to the top graph of  FIG. 8 , it can be seen that the circuit shown in  FIG. 1   b  has only one VCO drive level at which the quadrature signals have equal amplitude. Thus, the VCO input level needs to be tightly controlled for this circuit. Also, referring to the bottom graph, at VCO input levels above 0.3V, the phase error of the circuit in  FIG. 1   b  increases proportional to the input amplitude. In contrast, embodiments of the invention according to the circuits in  FIGS. 4-7  demonstrates substantially no amplitude mismatch or phase error over the entire range of VCO input voltages. In addition, the output level for the “proposed” circuits is constant at VCO input levels greater than 0.18V. 
         [0057]    In the preferred embodiment, the frequency doubling circuit and the phase shifter are incorporated into a single integrated circuit. This integrated circuit is then utilized in wireless communication products, such as wireless access points. 
         [0058]    Although the present invention has been described in considerable detail with reference to certain preferred embodiments thereof, other versions are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred embodiments contained herein.

Technology Category: 5