Patent Document

[0001]    This application claims priority to U.S. Provisional Application No. 61/056,709 filed May 28, 2008. 
     
    
     BACKGROUND 
       [0002]    The present invention relates generally to bipolar devices, and more particularly to bipolar devices compatible with CMOS process technology, and implemented in a mesh structure to enhance the performance. 
         [0003]    Although CMOS devices have advantages of low power consumption and high input impedance, they often need some specially designed I/O devices and circuits to protect them from high voltage signals. Those I/O devices and circuits usually require extra masks in the course of semiconductor processing. One way to simplify the semiconductor processing is to use bipolar devices as the I/O devices. The bipolar devices are able to sustain high voltages, easy to manufacture, and fully compatible with conventional CMOS process technologies. In addition, bipolar devices have many advantages over CMOS devices in designing analog circuitry. For example, bipolar devices can offer a higher current gain, lower noise, a higher driving capability, and less device mismatch than MOS devices for the same current. It would be desirable to use bipolar devices together with CMOS devices in certain circuits to achieve better and balanced performance for circuitries. 
         [0004]      FIG. 1  illustrates a conventional PNP bipolar transistor  10  compatible with CMOS process technologies. The LOCal Oxidation of Silicon (LOCOS) isolations  11  define three active areas  12 ,  13  and  14  on N well  15  in a semiconductor substrate. The active areas  12  and  13  doped with P-type impurities form an emitter  16  and collector  17 , respectively. The LOCOS isolation  11  between the emitter  16  and collector  17  defines an intrinsic base  18  thereunder in the N well  15 . An extrinsic base  19  is electrically connected to the intrinsic base  18  via the body of the N well  15 . The extrinsic base  19  is doped with N type of impurities to improve its conductivity. When the emitter  16 , collector  17  and extrinsic base  19  are properly biased, carriers would flow between the emitter  16  and the collector  17  to produce amplification of currents. Such bipolar transistor can be found in U.S. Patent Application Publication No. US 2006/0197185. 
         [0005]    The performance of the PNP bipolar transistor  10  greatly depends on the width of the intrinsic base  18  and its distance to the extrinsic base  19 . Conventionally, its current gain β, about 1-5, is too small to satisfy many circuit designs. Furthermore, if a Shallow Trench Isolations (STI) instead of a LOCOS isolation is used, it is almost impossible for carriers to travel between the collector and emitter over the STI. This further degrades the bipolar transistor&#39;s performance. 
         [0006]      FIG. 2  illustrates a layout view of a conventional bipolar device  20  proposed to address the above issues. The bipolar device  20  is constructed on an N well  22 , which is implemented on a semiconductor substrate (not shown in the figure). An isolation region  24 , such as LOCOS or shallow trench isolation, is formed on the N well  22  to define an active area  26 . A conductive gate  28  is formed across the active area  26 . P+ doped regions  30   a  and  30   b  are formed adjacent to the conductive gate  28  on the N well  22  within the isolation region  24 . N+ doped regions  32   a  and  32   b  with dosage higher than that of the N well  32  are implemented partially overlapping the N well  22  underneath the conductive gate  28  at the two longitudinal ends thereof. Extrinsic base contacts  34   a  and  34   b  are constructed on the N+ doped regions  32   a  and  32   b , respectively, and together with the N well  22  underneath the conductive gate  28  forming the base of the bipolar device  20 . 
         [0007]    In operation, one of the P+ doped regions  30   a  and  30   b  functions as an emitter and the other as a collector. The base of the bipolar device  20  is comprised of the intrinsic base, the portion of the N well  22  underneath the conductive gate  28 , and the extrinsic base including both the N+ dope regions  32   a  and  32   b . Since the N+ doped regions  32   a  and  32   b  are placed at two longitudinal ends of the conductive gate  28 , the distance between the intrinsic base and the extrinsic base is shortened, and the resistance there between is reduced as opposed to that of the prior art as shown in  FIG. 1 . As a result, the bipolar device  20  can achieve a higher current gain, compared to about 1 to 5 produced by the conventional bipolar device shown in  FIG. 1 . 
         [0008]      FIG. 3  illustrates a conventional layout view of a bipolar device array  40  disclosed in the U.S. Patent Application Publication No. US 2007/0105301. The bipolar device array  40  is constructed on an N well  44 , which is implemented on a semiconductor substrate (not shown in the figure). Rows and columns of conductive gates  42   a  and  42   b  are constructed on the N well  44 . The conductive gates  42   a  and  42   b  are formed together with the gates of MOS transistor on the semiconductor substrate. The conductive gates  42   a  include a set of parallel lines crossing another set of parallel lines designated by  42   b . P+ doped regions  46  are implemented on the N well  44  in areas between the conductive gates  42   a  and  42   b , except for the N+ doped regions  48  designated by the broken lines. The N well  44  underneath the conductive gates  42   a  and  42   b  has an N-type polarity, without being affected during the formation of the P+ doped regions  46 , as the conductive gates  42   a  and  42   b  shield off the P-type ions during the ion implantation process when forming the P+ doped regions  46 . Contacts  49  are constructed on the P+ doped regions  46  and the N+ doped regions  48 . 
         [0009]    Every two adjacent P+ doped regions  46  function as a collector and an emitter, respectively. The N well  44  underneath the conductive gates  42   a  and  42   b  functions as intrinsic bases, whereas the N+ doped regions  48  function as extrinsic bases. Each emitter and its surrounding collectors and bases function together as a PNP bipolar device, and rows and columns of such bipolar devices make up the bipolar device array  40 . The bipolar device array  40  has the advantages of reduced base resistance and increased device layout density. 
         [0010]    In view of the foregoing, there is still room for improvement on the architecture and the layout of the conventional bipolar devices in order to increase the current gain and the device layout density. 
       SUMMARY 
       [0011]    The present invention is directed to a bipolar device. In one embodiment of the present invention, the bipolar device includes: an emitter of a first polarity type constructed on a semiconductor substrate; a collector of the first polarity type constructed on the semiconductor substrate; a gate pattern in a mesh configuration defining the emitter and the collector; an intrinsic base of a second polarity type underlying the gate pattern; and an extrinsic base constructed atop the gate pattern and coupled with the intrinsic base, for functioning together with the intrinsic base as a base of the bipolar device. 
         [0012]    In another embodiment of the present invention, a bipolar device array is disclosed, which includes: an emitter of a first polarity type constructed on a semiconductor substrate; a collector of the first polarity type constructed on the semiconductor substrate; a gate pattern in a mesh configuration defining the emitter and the collector; an intrinsic base of a second polarity type underlying the gate pattern; an extrinsic base constructed atop the gate pattern and coupled with the intrinsic base, for functioning together with the intrinsic base as a base of the bipolar device, and an emitter contact constructed on the emitter, wherein a distance between the emitter contact and the collector is shorter than that between the emitter contact and the extrinsic base. 
         [0013]    The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  illustrates a cross-sectional view of a conventional bipolar device. 
           [0015]      FIG. 2  illustrates a layout view of a conventional bipolar device. 
           [0016]      FIG. 3  illustrates a layout view of a conventional bipolar device array. 
           [0017]      FIG. 4A  illustrates a layout view of a bipolar device array in accordance with one embodiment of the present invention. 
           [0018]      FIG. 4B  illustrates a cross-sectional view of the bipolar device array in accordance with the embodiment of the present invention. 
           [0019]      FIG. 4C  illustrates a cross-sectional view of the bipolar device array in accordance with the embodiment of the present invention. 
           [0020]      FIG. 4D  illustrates a cross-sectional view of the bipolar device array in accordance with the embodiment of the present invention. 
           [0021]      FIG. 5  illustrates a layout view of a bipolar device array in accordance with another embodiment of the present invention. 
           [0022]      FIG. 6  illustrates a layout view of a bipolar device array in accordance with yet another embodiment of the present invention. 
           [0023]      FIG. 7  illustrates a layout view of a bipolar device array in accordance with yet another embodiment of the present invention. 
           [0024]      FIG. 8  illustrates a layout view of a bipolar device array in accordance with yet another embodiment of the present invention. 
       
    
    
     DESCRIPTION 
       [0025]    This invention describes a bipolar device array having improved current gain and compatible with CMOS processing technology. The following merely illustrates various embodiments of the present invention for purposes of explaining the principles thereof. It is understood that those skilled in the art will be able to devise various equivalents that, although not explicitly described herein, embody the principles of this invention. 
         [0026]      FIG. 4A  illustrates a layout view of a bipolar device array  60  in accordance with one embodiment of the present invention. Rows of conductive gates  62   a  and columns of conductive gates  62   b  are disposed on an N-well  64 , and define P+ doped regions  66  functioning as collectors or emitters there between. The N well  64  underneath the conductive gates  62   a  and  62   b  functions as the intrinsic bases doped with N type impurities. The extrinsic bases  68  are formed by heavily doping the cross areas of the conductive gates  62   a  and  62   b  with N-type impurities, so as to form ohmic contact with its underlying intrinsic base. Contacts  65  are constructed on the P+ doped regions  66  and contacts  67  are constructed on the extrinsic bases  68 . The extrinsic base  68 , the intrinsic bases underlying the conductive gates  62   a  and  62   b , and its neighboring emitter and collector together function as a bipolar device. 
         [0027]    One consideration in constructing the bipolar device array  60  is that the distance d 1  between the emitter and the collector should be shorter than the distance d 2  between the emitter contact  65  and the extrinsic base  68 .  FIG. 4B  illustrates a partially cross-sectional view of the bipolar device array  60  along the distance d 1  between the emitter contact  65  and the collector adjacent to the conductive gate  62   b , whereas  FIG. 4C  illustrates a partially cross-sectional view of the bipolar device array  60  along the distance d 2  between the emitter contact  65  and the extrinsic base  68 . As clearly shown in those figures, the distance d 1  between the emitter and the collector is shorter than the distance d 2  between the emitter and the extrinsic base  68 . When the emitter and the base are forward biased, this configuration ensures that most of the carriers would flow between the emitter and the collector, instead of flowing directly between the emitter and the extrinsic base, thereby allowing the bipolar device to function properly. 
         [0028]    The materials of the conductive gates  62   a  and  62   b  can be polysilicon, tungsten or other metal alloys. However, it is noted that since the conductive gates  62   a  ad  62   b  are designed as dummy structures that do not function as active parts of the bipolar device array  60 , as an alternative, they can also be made of non-conductive materials, trading off the compatibility with the conventional CMOS process. The conductive gates  62   a  and  62   b  are merely used to define intrinsic base from lithography standpoint. The conductive gates may be etched away, otherwise an MOS device may be turned on when the bipolar device is active. The extrinsic base contacts needs to be ohmic, otherwise the performance of a bipolar device may be degraded substantially. As an embodiment, an ohmic contact can be formed by heavy ion implantation of such N+ dopants as phosphorus or arsenic ions after the extrinsic base contacts are opened. 
         [0029]    The density of the bipolar devices is increased, thereby rendering more bipolar devices in a unit area of the silicon real estate. Instead of constructing the bipolar device with one elongated intrinsic base, each bipolar device in the array  60  has four intrinsic bases surrounding an emitter, such that it can be made in a more compact manner. As a result, the proposed bipolar device array can be scaled up to provide an enlarged current gain. For example, the current gain of the proposed bipolar device array can exceed 100, which is sufficient for most of the applications in circuit designs. 
         [0030]      FIG. 4D  illustrates a cross-sectional view of a bipolar device along the line A-A′ in the array  60  shown in  FIG. 4A . The collector  66   a  and the emitter  66   b  are constructed on the N well  64 , and separated by the intrinsic base the area underneath the conductive gate  62   b . The lightly doped drain of the emitter  66   b  and the pocket implants of the collector  66   a  and the emitter  66   b  are eliminated in order to increase the emitter efficiency. This architecture can be used as a basic structure to construct the bipolar device array  60  as shown in  FIG. 4A , and also other various arrays that will be described in following paragraphs. 
         [0031]      FIG. 5  illustrates a layout view of a bipolar device array  70  in accordance with another embodiment of the present invention. The bipolar device array  70  is constructed on an N well  74 , which is implemented on a semiconductor substrate (not shown in the figure). Conductive gates  72  are constructed on the N well  74  in a configuration comprised of square-shaped gates  72   a  and bridges  72   b  that link the square-shaped gates  72   a  together. The areas within the boundary of the square-shaped gate  72   a  are doped with P-type impurities to form P+ doped regions functioning as emitters. The areas defined by the boundary of the square-shaped gate  72   a  and the bridges  72   b  are doped with P-type impurities to form P+ doped regions functioning as collectors. The N well  74  underneath the conductive gates  72 , both the square-shaped gates  72   a  and the bridges  72   b  functions as intrinsic bases. Parts of the bridges  72   b  are doped with N type impurities to form N+ doped regions  76  functioning as extrinsic bases, on which their corresponding base contacts  78  are formed. It is noted that although a square-shaped conductive gates is disclosed, as alternatives, it can be made in any polygonal shapes or geometrical shapes. 
         [0032]      FIG. 6  illustrates a layout view of a bipolar device array  80  in accordance with yet another embodiment of the present invention. The bipolar device array  80  has a configuration similar to that of the array  60  shown in  FIG. 4A , expect that the conductive gates  62   a  and  62   b  are removed with the extrinsic base  68  remained, as opposed to an otherwise merged MOS/bipolar device where the MOS gate and the extrinsic base are connected. 
         [0033]      FIG. 7  illustrates a layout view of a bipolar device array  90  in accordance with yet another embodiment of the present invention. In the array  90 , the conductive gates  92   a ,  92   b  and  92   c  are arranged in three directions representing three sides of a triangle. P+ doped regions  94  are formed within the triangular areas defined by adjacent segments of the conductive gates  92   a ,  92   b  and  92   c  to function as emitters and collectors. N+ doped regions  96  are formed at the cross points of the conductive gates  92   a ,  92   b  and  92   c  to function as extrinsic bases. Each set of neighboring emitters, collectors and extrinsic bases functions as a bipolar device within the array  90 . 
         [0034]      FIG. 8  illustrates a layout view of a bipolar device array  100  in accordance with yet another embodiment of the present invention. In the array  100 , the conductive gates  102  are arranged in a hexagonal shape. P+ doped regions  104  are formed within the hexagons defined by the conductive gates  102  to function as emitters and collectors. N+ doped regions  106  are formed at the corners of the conductive gates  102  to function as extrinsic bases. Each set of neighboring emitters, collectors and extrinsic bases functions as a bipolar device within the array  100 . 
         [0035]    It is noted that the bipolar device arrays shown in  FIG. 4A ,  FIG. 7  and  FIG. 8  have a common feature in the sense that the extrinsic bases are formed at the intersections of the conductive gates, and scattered around the emitters and the collectors. This configuration allows the bipolar devices to be constructed in a compact manner, thereby increasing the device density in a unit layout area. 
         [0036]    It is understood by people skilled in the art of semiconductor technology that although the above embodiments are directed to PNP bipolar devices, the principles explained by the above embodiment can be applied to construct NPN bipolar devices by inverting the polarity of the collector, the emitter and the base of the bipolar device. 
         [0037]    The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims. 
         [0038]    Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.

Technology Category: 5