Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-269333, filed Sep. 29, 2006, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device and a method of fabricating the same. 
         [0004]    2. Description of the Related Art 
         [0005]    To increase the driving current of a transistor in a semiconductor device, it is desirable to use a Material having high stress as an insulating film covering source/drain regions and gate electrodes, and deposit this insulating film as a thicker layer. 
         [0006]    If a narrow spacing between the gate electrodes is closed by increasing the thickness of this insulating film, however, it becomes difficult to maintain films formed as sidewall spacers of the gate electrodes, since the thickness of the gate electrode film is added to an effective film thickness to be removed when forming different insulating films in nMOS and pMOS transistors. In addition, if films formed as stoppers of the sidewall spacer films are also removed, etching damage enters source/drain extension regions as well, and this degrades the junction leakage characteristic. 
         [0007]    If a thin film that does not close the narrow spacing between the gate electrodes is formed as the insulating film in order to avoid the above problem, insufficient stress is applied to the channel portion of the transistor, so the desired driving current cannot be obtained. 
         [0008]    Note that Jpn. Pat. Appln. KOKAI Publication No. 2003-273240 describes steps of forming insulating films having different stresses in an nMOSFET and pMOSFET. 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    According to an aspect of the invention, there is provided a semiconductor device comprising: a first semiconductor element formed on a semiconductor substrate and using electrons as carriers, and a second semiconductor element formed on the semiconductor substrate and using holes as carriers; a first insulating film and a second insulating film formed on source/drain regions and gate electrodes of the first semiconductor element and the second semiconductor element, the first insulating film having tensile stress with respect to the first semiconductor element, and the second insulating film having compression stress with respect to the second semiconductor element; and sidewall spacers of the gate electrodes of the first semiconductor element and the second semiconductor element, at least portions of the sidewall spacers being removed, wherein at least one of the first insulating film and the second insulating film does not close a spacing between the gate electrodes of the first semiconductor element and the second semiconductor element. 
         [0010]    According to another aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming, on a semiconductor substrate, a first semiconductor element using electrons as carriers, and a second semiconductor element using holes as carriers; forming sidewall spacers of gate electrodes of the first semiconductor element and the second semiconductor element; removing at least portions of the sidewall spacers of the gate electrodes of the first semiconductor element and the second semiconductor element; depositing a first insulating film having one of tensile stress and compression stress on source/drain regions and the gate electrodes of the first semiconductor element and the second semiconductor element, the first insulating film not closing a spacing between the gate electrodes of the first semiconductor element and the second semiconductor element; depositing a second insulating film on the first insulating film; removing the first insulating and the second insulating film deposited on one of the first semiconductor element and the second semiconductor element; depositing a third insulating film having the other one of tensile stress and compression stress on the source/drain regions and the gate electrodes of the first semiconductor element and the second semiconductor element; and removing the third insulating film deposited on the other one of the first semiconductor element and the second semiconductor element. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0011]      FIG. 1  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0012]      FIG. 2  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0013]      FIG. 3  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0014]      FIG. 4  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0015]      FIG. 5  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0016]      FIG. 6  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0017]      FIG. 7  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0018]      FIG. 8  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0019]      FIG. 9  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0020]      FIG. 10  is a sectional view showing a semiconductor device fabrication step according to the first embodiment; 
           [0021]      FIG. 11  is a sectional view showing a semiconductor device fabrication step according to the second embodiment; 
           [0022]      FIG. 12  is a sectional view showing a semiconductor device fabrication step according to the second embodiment; 
           [0023]      FIG. 13  is a sectional view showing a semiconductor device fabrication step according to the third embodiment; 
           [0024]      FIG. 14  is a sectional view showing a semiconductor device fabrication step according to the third embodiment; 
           [0025]      FIG. 15  is a sectional view showing a semiconductor device fabrication step according to the third embodiment; 
           [0026]      FIG. 16  is a sectional view showing a semiconductor device fabrication step according to the third embodiment; 
           [0027]      FIG. 17  is a sectional view showing a semiconductor device fabrication step according to the third embodiment; and 
           [0028]      FIG. 18  is a sectional view showing a semiconductor device fabrication step according to the third embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0029]    Embodiments will be explained below with reference to the accompanying drawing. 
         [0030]    In a semiconductor device comprising an active element such as a MOSFET, the current drivability improves when a film having tensile stress and a film having compression stress are respectively used in a transistor (nMOS) in which electrons are carriers and a transistor (pMOS) in which holes are carriers, as an insulating film covering source/drain regions and gate electrodes. The embodiments avoid the above-mentioned problems arising when forming different insulating films in nMOS and pMOS transistors in order to improve the current drivability of both the nMOS and pMOS transistors. 
         [0031]      FIGS. 1 to 10  are sectional views showing semiconductor device fabrication steps according to the first embodiment. The semiconductor device fabrication steps according to the first embodiment will be explained below with reference to  FIGS. 1 to 10 . 
         [0032]    First, as shown in  FIG. 1 , an element isolation region  102  is formed in an Si substrate (bulk Si substrate, SiGe substrate, or SOI substrate) by burying an insulating film in a trench about 300 nm deep, and an impurity serving as a well and channel is doped. After that, a gate insulating film  103  about 1 nm thick is deposited on the Si substrate  101 , and a gate electrode film  104  about 100 nm thick is deposited on the entire surface. 
         [0033]    Then, as shown in  FIG. 2 , the gate insulating film  103  is used as a stopper to process the gate electrode film  104  by lithography and dry etching, and an impurity serving as source/drain extensions is doped by ion implantation. 
         [0034]    In addition, to ensure the transistor characteristics and reliability, sidewall spacers are formed to separate a source and drain by about 30 nm. To avoid etching damage from entering the Si substrate  101  during this sidewall spacer processing, as shown in  FIG. 3 , it is possible to form thin L-shaped first SiO 2  films  105  on the gate electrode film  104 , deposit first SiN films  106  whose film thickness is adjusted to obtain a desired sidewall width, process the first SiN films  106  by using the first SiO 2  films  105  as stoppers, and remove the remaining first SiO 2  films  105 . 
         [0035]    After the sidewall spacers are processed, as shown in  FIG. 4 , an impurity serving as a source and drain are doped and activated, and a metal  107  such as Ti, Co, or Ni is deposited and alloyed in order to decrease the interconnection resistance of source/drain regions and gate electrodes. 
         [0036]    After this alloying, a barrier film serving as an etching stopper in later contact formation is deposited. When a film having tensile stress and a film having compression stress are respectively used as the barrier films in a transistor (nMOS) in which electrons are carriers and a transistor (pMOS) in which holes are carriers, the current drivability of both transistors can increase. 
         [0037]    In this state, as shown in  FIG. 5 , the first SiN films  106  processed as sidewall spacers are entirely or partially removed by wet or dry etching. 
         [0038]    After that, as shown in  FIG. 6 , a second SiN film  108  having tensile stress is deposited to have a film thickness that does not close a narrow spacing between the gate electrodes (letting W be this film thickness, 2×(W+thickness X of stopper film [SiO 2  film  105 ])&lt;space Y between gate electrodes [GC]), and a second SiO 2  film  109  about 20 nm thick is deposited. Subsequently, as shown in  FIG. 7 , a first resist  110  is deposited and patterned to expose only the pMOS region by lithography. 
         [0039]    After the pMOS region is exposed by lithography, the first resist  110  is used as a mask to remove the second SiO 2  film  109 . 
         [0040]    In addition, as shown in  FIG. 8 , after the first resist  110  is removed, the second SiN film  108  is partially or entirely removed while maintaining the second SiO 2  film  109  in the nMOS region and the first SiO 2  films  105  as stoppers in the pMOS region. 
         [0041]    As shown in  FIG. 9 , after a third SiN film  111  having compression stress is formed, a second resist  112  is deposited and patterned to expose only the nMOS region by lithography, and the third SiN film  111  on the nMOS is removed by using the second SiO 2  film  109  as a stopper. 
         [0042]    After that, as shown in  FIG. 10 , the second resist  112  is removed, a third SiO 2  film  113  is deposited and planarized by CMP, and a semiconductor device is completed by forming contact holes, an interlayer dielectric film  117 , and a metal interconnection  118 . 
         [0043]    Note that each of the second SiN film  108  having tensile stress and the third SiN film  111  having compression stress is made of a silicon oxide film, silicon nitride film, silicon oxynitride film, hafnium oxide film, aluminum oxide film, aluminum nitride film, tantalum oxide film, or titanium oxide film. When the film thickness is 10 to 200 nm, the film has sufficient stress to increase the driving current of the transistor. 
         [0044]      FIGS. 11 and 12  are sectional views showing semiconductor device fabrication steps according to the second embodiment. The semiconductor device fabrication steps of the second embodiment will be explained below with reference to  FIGS. 11 and 12 . 
         [0045]    First, steps up to  FIG. 9  are performed in the same manner as in the first embodiment. That is, an alloy layer  107  is formed on source/drain regions and gate electrodes, first SiN films  106  processed as sidewall spacers are removed, a second SiN film  108  and second SiO 2  film  109  are deposited, the second SiN film  108  and second SiO 2  film  109  in a pMOS region are removed by lithography and dry etching, a third SiN film  111  and second resist  112  are deposited, and the third SiN film iii deposited in an nMOS region is removed by using the second resist  112 . 
         [0046]    In addition, as shown in  FIG. 11 , the second SiO 2  film  109  is removed by using the second resist  112  as a mask and the second SiN film  108  as a stopper. 
         [0047]    After that, as shown in  FIG. 12 , the second resist  112  is removed, a third SiO 2  film  113  is deposited and planarized by CMP, and a semiconductor device is completed by forming contact holes, an interlayer dielectric film  117 , and a metal interconnection  118 . 
         [0048]      FIGS. 13 to 18  are sectional views showing semiconductor device fabrication steps according to the third embodiment. The semiconductor device fabrication steps of the third embodiment will be explained below with reference to  FIGS. 13 to 18 . 
         [0049]    First, the steps shown in  FIGS. 1 to 3  are performed to form an alloy layer on source/drain regions and gate electrodes as shown in  FIG. 13 . 
         [0050]    In this state, as shown in  FIG. 14 , first SiN films  106  processed as sidewall spacers are removed by wet or dry etching. 
         [0051]    After that, as shown in  FIG. 15 , a second SiN film  108  having tensile stress is deposited to have a film thickness that does not close a narrow spacing between the gate electrodes, and a second SiO 2  film  109  about 20 nm is deposited. Subsequently, as shown in  FIG. 16 , a first resist  110  is deposited and patterned to expose only a pMOS region by lithography. 
         [0052]    As in the first embodiment, after the pMOS region is exposed by lithography, the second SiO 2  film  109  is removed by using the first resist  110  as a mask. 
         [0053]    Furthermore, as shown in  FIG. 17 , after the first resist  110  is removed, the second SiN film  108  in the pMOS region is partially removed and processed into sidewall spacers of the gate electrodes while maintaining the second SiO 2  film  109  in an nMOS region and first SiO 2  films  105  as stoppers in the pMOS region. 
         [0054]    After that, as shown in  FIG. 18 , a third SiN film  111  having compression stress is formed and processed. Finally, a third SiO 2  film  113  is deposited and planarized by CMP, and a semiconductor device is completed by forming contact holes, an interlayer dielectric film  117 , and a metal interconnection  118 . 
         [0055]    In the first to third embodiments described above, partially or entirely removing the sidewall spacers make it possible to avoid the insulating film covering the alloy layer formed on the source/drain regions and gate electrodes from closing the narrow spacing between the gate electrodes while maintaining the film thickness of the insulating film. Also, the insulating film can be readily removed because it is formed so as not to close the narrow spacing between the gate electrodes. This makes the formation of nMOS and pMOS transistors having improved current drivability feasible. Accordingly, the initially deposited insulating film can be removed without causing etching damage to extension portions. This facilitates the formation of different insulating films having different stresses in the nMOS and pMOS transistors. Furthermore, since the insulating film having stress is formed close to the channel portion of the transistor, the stress efficiently acts on the transistor, so the current drivability of the transistor can further improve. Accordingly, the stress can be increased not only by partially or entirely removing the sidewall, spacers, but also by preventing the insulating film from closing the narrow spacing between the gate electrodes. 
         [0056]    The embodiments can provide a semiconductor device capable of applying sufficient stress to the channel portion of a transistor, and a method of fabricating the same. 
         [0057]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Technology Category: h