Patent Document

PRIORITY CLAIM 
       [0001]    This application claims priority from French Application for Patent No. 1556515 filed Jul. 9, 2015, the disclosure of which is incorporated by reference. 
       TECHNICAL FIELD 
       [0002]    Embodiments of the invention relate to integrated circuits, and more particularly to hybrid operation MOS transistors produced on substrates of silicon on insulator type, commonly referred to by those skilled in the art by the acronym “SOI”, in particular a substrate of the fully depleted silicon on insulator type, known by those skilled in the art by the acronym “FDSOI”. 
       BACKGROUND 
       [0003]    Hybrid operation MOS transistors are known and are advantageous notably for electrostatic discharge (ESD) protection applications. Those skilled in the art will be able, for example, to refer to the U.S. Patent Application Publication No. 2013/0141824 (incorporated by reference) which describes this type of transistor. 
         [0004]    These transistors are produced on bulk substrates. Now, electrical simulations have shown (see, Galy, et al. “BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS technology”, EUROSOI-ULIS 2015, 26-28 January 2015, Bologne, Italy (incorporated by reference)) that there would be advantages from an electrical point of view in producing these hybrid operation transistors on a substrate of FDSOI type for an ESD protection application. 
         [0005]    However, the very small thickness of the semiconductor film (typically of the order of 7 nm) does not make it possible to directly produce a contact land on an FDSOI substrate for this type of transistor. 
       SUMMARY 
       [0006]    According to one embodiment, it is proposed to simply produce a transistor on an FDSOI type substrate in which a substrate contact land has been produced. 
         [0007]    Thus, according to one aspect, a method is proposed for producing at least one substrate contact land for an MOS transistor, for example an NMOS transistor, produced in and on an active zone of a substrate of silicon on insulator (SOI) type, in particular of the fully depleted silicon on insulator (FDSOI) type, comprising a production in said active zone of at least one second MOS transistor, for example a PMOS transistor, without any PN junction having at least one contact land on at least one of its source or drain regions, this source and/or drain contact land forming said at least one substrate contact land. 
         [0008]    Thus, a transistor without any junction is used not functionally as transistor but as connection element making it possible to use the source and/or drain region as substrate land. 
         [0009]    In effect, the inventors have observed that, during the biasing of the drain or of the source of the second transistor, and despite the high resistance of the intrinsic silicon, a low current circulates, but one that is sufficient to allow for a substrate biasing of the first transistor. 
         [0010]    And this is easy to produce through a joint production of the two MOS transistors on the same active zone by using a conventional CMOS method, and most particularly advantageous in the FDSOI technology because use is advantageously made of the raised source and drain regions (the raising being inherent to the fabrication method) of the junction-free transistor to easily take a contact on at least one of these source or drain regions so as to produce a substrate contact land without risk of damaging the semiconductor film of the FDSOI substrate. 
         [0011]    The method can further comprise a production in the active zone of at least one third MOS transistor without any PN junction, the first MOS transistor being bracketed by the second and the third MOS transistors, the third MOS transistor comprising at least one contact land on at least one of its source or drain regions, this source or drain contact land forming a second substrate contact land for the NMOS transistor, the insulated gate regions of the three MOS transistors being advantageously produced in the same line of gate material. 
         [0012]    According to another aspect, an integrated electronic device is proposed that comprises
       an intrinsic semiconductor film above a buried insulating layer, itself situated above a bearer substrate, an insulating region delimiting an active zone in the semiconductor film,   a first MOS transistor, situated in and on a first part of the active zone (typically comprising PN junctions between the source/drain regions and the channel region, an insulated gate region above the channel region, a source contact land, a drain contact land, and a gate contact land) and   at least one connection element situated in and on a second part of the active zone, structurally similar to a second MOS transistor without any PN junctions between its source/drain regions and its channel region (typically having an insulated gate region above its channel region), at least one source or drain contact land forming at least one substrate contact land for the first transistor.       
 
         [0016]    Advantageously, the gate regions of the two transistors are linked and incorporated in a same line of gate material. 
         [0017]    The second transistor further comprises a source contact land and a drain contact land that are mutually electrically linked by an electrically conductive link. 
         [0018]    According to one embodiment, the device can comprise a second connection element structurally similar to the first connection element and therefore to a third MOS transistor without any PN junction between its source/drain regions and its channel region, situated in and on a third part of the active zone, the first part of the active zone being situated between the second and third parts, at least one source or drain contact land of the third MOS transistor forming a second substrate contact land for the first MOS transistor. 
         [0019]    Advantageously, the gate regions of the three transistors are linked and incorporated in a same line of gate material. 
         [0020]    The third transistor further comprises a source contact land and a drain contact land that are mutually electrically linked by an electrically conductive link. 
         [0021]    The device also comprises, in the bearer substrate, a single semiconductor well situated under said active zone and a well land intended to bias said well. 
         [0022]    Advantageously, the silicon film is of intrinsic P type, the first transistor is an NMOS transistor, and the other transistor or transistors is/are PMOS transistors. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]    Other advantages and features of the invention will become apparent on studying the detailed description of implementations, that are in no way limiting, and the attached drawings in which: 
           [0024]      FIGS. 1 to 8  schematically represent implementations and embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]      FIG. 1  illustrates a plan view of an integrated device DIS according to one embodiment, for which  FIGS. 2 and 3  are cross-sectional views along the lines II-II and of  FIG. 1 . 
         [0026]    The device DIS comprises a substrate of FDSOI type, which comprises a semiconductor film  1  above a buried insulating layer  2  (“BOX”, standing for Buried Oxide), itself situated above a bearer substrate comprising a semiconductor well  3 . 
         [0027]    The well  3  is here of P type and comprises an upper zone (in contact with the BOX) of P+ type which makes it possible to bias the device via the rear face. 
         [0028]    An insulating region  4  of shallow trench type (“STI”, standing for Shallow Trench Isolation) delimits an active zone  5  in the semiconductor film  1 . 
         [0029]    The semiconductor film  1  comprises a fully depleted semiconductor material which in practice is an intrinsic material, for example intrinsic silicon of P type, that is to say very weakly doped (10 15  atoms/cm 3 ). 
         [0030]    In a first part P 1  of the device, a first MOS transistor TR 1  has been produced, for example an NMOS transistor. 
         [0031]    This first transistor TR 1  comprises source S 1  and drain D 1  semiconductor regions, with N+ type doping, a channel region  80  and an insulated gate region G 1 . 
         [0032]    The reference B 1  denotes the substrate (“bulk”) of the transistor TR 1 . According to a conventional embodiment in the substrates of FDSOI type, the drain D 1  and source S 1  regions are produced in a raised manner by epitaxial growth, but this raising has not been represented in the figures in the interests of simplification. 
         [0033]    The silicidation zones PCG 1 , PCD 1 , and PCS 1 , are, in this example, produced respectively on the gate G 1 , drain D 1  and source S 1  regions, and respectively form gate, drain and source contact lands. 
         [0034]    In a second part P 2  of the semiconductor film  1 , a second MOS transistor TR 2  has been produced, for example a transistor of PMOS type. 
         [0035]    It comprises P +  type doped drain D 2  and source S 2  semiconductor regions, a channel region, and an insulated gate region G 2 . 
         [0036]    The reference B 2  denotes the substrate of the transistor TR 2 . The substrates B 1  and B 2  are therefore electrically linked because they are formed in the same active zone  5 . 
         [0037]    The silicidation zones PCD 2  and PCS 2  are produced respectively on the drain D 2  and source S 2  regions and respectively form the drain and source contact lands. 
         [0038]    The gate regions G 1  and G 2  of the two transistors TR 1  and TR 2  are produced in a same line of gate material. They are therefore here electrically connected and the land PCG 1  is common to the gates G 1  and G 2 . 
         [0039]    Since the semiconductor film  1  is of intrinsic P type, the second transistor TR 2  has no PN junction. Consequently, the biasing of one of its source S 2  or drain D 2  regions makes it possible to bias the substrate B 2  and therefore the substrate B 1  of the first transistor TR 1 . 
         [0040]    In this example, an electrical link  9  formed by vias and a metallization links the source S 2  and drain D 2  regions of the transistor TR 2 . 
         [0041]    The device DIS therefore comprises a transistor TR 1  on a substrate of FDSOI type comprising a substrate land (here PCS 1  and PCD 1 ) produced via the second transistor TR 2 . The second transistor TR 2  is therefore not used as such, but serves simply as connection element for the biasing of the substrate B 1 . 
         [0042]    The device DIS further comprises a contact land BG that makes it possible to bias the wells  3 . Given that the wells  3  of the two transistors TR 1  and TR 2  are common, the contact BG makes it possible to bias both the rear face of the first transistor TR 1  and that of the second transistor TR 2 . 
         [0043]    A schematic representation of the device DIS from an electrical point of view is illustrated in  FIG. 4 . 
         [0044]    The transistor TR 1  is represented therein, comprising its drain D 1 , source S 1  and gate G 1  regions, the contact lands PCG 1 , PCD 1 , PCS 1 , and the second transistor TR 2  with its drain D 2 , source S 2  and gate G 2  regions, and the contact lands PCG 1 , PCD 2 , PCS 2 , the last two forming a substrate contact land BC 1 . 
         [0045]    Two capacitors C 1  and C 2  schematically represent the capacitors formed under each of the transistors TR 1  and TR 2  by the semiconductor film  1 , the insulating layer  2 , and the well  3 . Given that, in this embodiment, the wells of the two transistors TR 1  and TR 2  are linked, the capacitors C 1  and C 2  are represented as connected to the same rear gate contact BG. 
         [0046]    Similarly, given that the gates G 1  and G 2  are produced in the same line of gate material, they are represented as connected to the same gate contact land PCG 1 . 
         [0047]    It would have been possible to produce two independent gates in order, for example, to bias the gate of the second transistor TR 2  independently of that of the first transistor TR 1 . It would thus be possible, by adjusting the bias voltage value of the gate G 2  of the second transistor TR 2 , to modulate the access resistance of the first transistor TR 1  without affecting the operation thereof. 
         [0048]    However, the production of the two gates G 1  and G 2  in a same line of gate material is advantageous from the point of view of the production method. 
         [0049]    The source and drain regions of the second transistor TR 2  are here linked to the same substrate land BC 1  by the metallization  9 . Although this connection is not essential, it makes it possible to bias both the source region S 2  and the drain region D 2  and therefore obtain a higher substrate B 1  bias current. 
         [0050]    Functionally, the device can be considered ( FIG. 5 ) as a single transistor TR, having a front gate contact land PCG 1 , a rear gate contact land BG, a drain contact land PCD 1 , a source contact land PCS 1  and a substrate contact land BC 1 . 
         [0051]    Such a device makes it possible to obtain a very significant current gain (of the order of  10   5 ). 
         [0052]    Depending on the manner in which the transistor TR 1  will be biased, it is possible to obtain different modes of operation, notably operation as MOS transistor, as bipolar transistor, or hybrid operation such as that described in 
         [0053]    U.S. Patent Application Publication No. 2013/0141824. 
         [0054]      FIG. 6  illustrates a device according to an embodiment similar to that described in  FIG. 3  which further comprises a third part P 3  containing a third PMOS transistor TR 3 , having a structure similar to the second transistor TR 2 , and behaving like a second connection element for the biasing of the substrate B 1  of the transistor TR 1 . 
         [0055]    The second and the third transistors TR 2  and TR 3  are each situated on either side of the first transistor TR 1 . 
         [0056]    By adding this third transistor TR 3 , it becomes possible to more effectively bias the substrate B 1  of the transistor TR 1 , and obtain an additional mode of operation of the transistor, which will be described hereinbelow. 
         [0057]    Since the transistor TR 3  has no PN junction between its source/drain regions and its channel region, the biasing of one of its source S 3  or drain D 3  regions makes it possible to bias its substrate and therefore the substrate of the first transistor TR 1 . 
         [0058]    Furthermore, since the wells of the first transistor TR 1  and of the third transistor TR 3  are identical and electrically connected, the contact BG makes it possible to bias both the rear face of the first transistor TR 1 , that of the second transistor TR 2  and also that of the third transistor TR 3 . 
         [0059]    A schematic representation of this embodiment from an electrical point of view is illustrated in  FIG. 7 . A device is represented therein that is similar to that illustrated by 
         [0060]      FIG. 4 , to which is added the third transistor TR 3 , comprising its drain D 3 , source S 3 , substrate B 3  and gate G 3  regions, and the contact lands PCD 2 , PCS 2  forming a second substrate contact land BC 2  for the transistor TR 1 . 
         [0061]    The capacitor C 3  schematically represents the capacitor formed under the transistor TR 3  by the semiconductor film  1 , the insulating layer  2  and the well  3 . In this embodiment, since the three wells of the transistors TR 1 , TR 2  and TR 3  are linked, they are represented as connected to the same contact BG. 
         [0062]    Similarly, since the gate G 3  is produced in the same line of gate material as the gates G 1  and G 2  of the transistors TR 1  and TR 2 , it is represented as connected to the gate contact land PCG 1 . 
         [0063]    The source S 2  and drain D 2  regions of the second transistor are here linked to the same substrate land BC 1  by the metallization  91 , and the source and drain regions of the third transistor are here linked to the same contact land BC 2  by the metallization  90 . 
         [0064]    The resistor R symbolizes the resistance of the substrate B 1  of the first transistor TR 1 . 
         [0065]    Functionally, the device can be considered ( FIG. 8 ) as an MOS transistor T with 4 gates, also known by those skilled in the art by the term “G 4 -FET”, and comprising six contact lands. 
         [0066]    In this mode of operation, the two contact lands BC 1  and BC 2  are used as the electrodes of the transistor T. For example, the contact land BC 1  corresponds to the source and the contact land BC 2  corresponds to the drain. 
         [0067]    The source S 1  and the drain D 1  of the first transistor TR 1  are used as two gates of a JFET transistor with P channel. They can therefore here be biased in order to modulate the current circulating between the source BC 1  and the drain BC 2  of the transistor T. 
         [0068]    The gate G 1  and the rear gate of the transistor TR 1 , linked respectively to the contact lands PCG 1  and BG, can also be biased in order to modulate the current, and also the resistance value R of the substrate B 1 . These two gates form the other two gates of the transistor T with four gates. 
         [0069]    It should be noted that the embodiments represented here are in no way limiting. 
         [0070]    Notably, although, in this example, a same well land BG has been represented, it would have been possible, through an insulation of the underlying wells, to independently bias each of the wells by the rear face. 
         [0071]    Furthermore, although a first NMOS transistor TR 1  has been produced here associated with a second PMOS transistor TR 2  without junction, it would have been possible for the first transistor TR 1  to be a PMOS transistor and for the second transistor TR 2  to be an NMOS transistor without junction. In this case, the semiconductor film  1  would have been of intrinsic N type, obtained from a substrate of intrinsic P type by an appropriate doping.

Technology Category: 5