Patent Document

FIELD OF THE INVENTION  
         [0001]    The present invention relates to a method for fabricating a semiconductor device; and, more particularly, to a method for forming a quantum dot.  
         DESCRIPTION OF RELATED ARTS  
         [0002]    In accordance with a current scale-down trend due to advanced levels of integration in a semiconductor device, the total number of electrons existing in channel regions will be also decreased by a few tens of electrons.  
           [0003]    As the number of electrons necessary for driving the semiconductor device decreases, a percentage of electrons corresponding to a statistic error among those electrons for driving the semiconductor device conversely increase. This increased percentage of the electrons has a severe impact on reliability of the semiconductor device. Therefore, it is evidently required to develop a new structure of the semiconductor device capable of accurately controlling a single electron.  
           [0004]    A single electron transistor, recently proposed for coping with the above limitation, is able to control a single electron and drive the semiconductor device even with an extremely low voltage.  
           [0005]    In other words, when each of a typical metal-oxide silicon field effect transistor (MOSFET) and the single electron transistor performs the same algorithm, the MOSFET needs about 1000 to about 20000 electrons. However, the single electron transistor needs only about 1 to about several electrons, thereby decreasing power consumption by {fraction (1/1000)} and further resulting in power-saving and high integration effects.  
           [0006]    [0006]FIG. 1 is a cross-sectional view showing a single electron transistor in accordance with a prior art.  
           [0007]    Referring to FIG. 1, a first insulating layer  12 A and a second insulating layer  12 B are sequentially deposited on a semiconductor substrate constructed with silicon or Ge—AS. A number of quantum dots are formed on between the first insulating layer  12 A and the second insulating layer  12 B. Herein, the first insulating layer  12 A is a tunneling oxide, and the second insulating layer  12 B is a control oxide.  
           [0008]    Subsequently, a gate electrode  14  is formed on the second insulating layer  12 B. On both ends of the gate electrode  14 , a source area  15  and a drain area  16  are formed within the semiconductor substrate  11 .  
           [0009]    To construct the single electron transistor, it is very important to form uniformly micronized quantum dots of which size is several nanometers on the first insulating layer  12 A corresponding to the gate electrode  14 .  
           [0010]    There suggested several conventional methods for forming quantum dots. A quantum dot can be formed by using the agglomeration phenomenon achieved from serial steps as following: depositing silicon germanium or a thin metal layer on between oxide layers; growing the oxide layers; and treating the grown oxide layers with a thermal process. Lithography can also be used for directly forming a number of quantum dots, or there is another method for forming quantum dots electrically within a gap between energy bands. Yet, there has not been suggested a method for forming a quantum dot satisfying reliability and massproduction simultaneously.  
           [0011]    Also, it is limited to improve properties of the semiconductor device since a quantum dot formed through the conventional method forms mainly multi-crystal silicon.  
         SUMMARY OF THE INVENTION  
         [0012]    It is, therefore, an object of the present invention to provide a method for forming a quantum dot that has a single crystal and satisfy reliability and massproduction simultaneously.  
           [0013]    In accordance with an aspect of the present invention, there is provided a method for forming a quantum dot, including the steps of: forming a first insulating layer on a semiconductor substrate; forming an opening that exposes the semiconductor substrate by etching the first insulating layer; forming a single crystal semiconductor layer in the opening and on the first insulating layer adjacent to the opening; and forming a quantum dot on the first insulating layer adjacent to the opening by removing the single crystal semiconductor layer in the opening and portions of the singly crystal layer on the first insulating layer adjacent to the opening.  
           [0014]    In accordance with another aspect of the present invention, there is also provided a method for forming a quantum dot, comprising the steps of: forming a sub-layer on a substrate; forming an opening that expose the substrate by etching the sub-layer; forming a conductive layer in the opening and on the sub-layer adjacent to the opening; and forming a quantum dot by leaving portions of the conductive layer on the sub-layer adjacent to the opening. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWING(S)  
       [0015]    The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments-given in conjunction with the accompanying drawings, in which:  
         [0016]    [0016]FIG. 1 is a cross-sectional view showing a single electron transistor in accordance with a prior art;  
         [0017]    [0017]FIGS. 2A to  2 F are cross-sectional views illustrating a method for forming a plurality of quantum dots in accordance with a preferred embodiment of the present invention;  
         [0018]    [0018]FIGS. 3A to  3 D are plane views showing a method for forming quantum dots in accordance with the preferred embodiment of the present invention; and  
         [0019]    [0019]FIG. 4 is a cross-sectional view showing a single electron transistor in accordance with the preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0020]    [0020]FIGS. 2A to  2 F are cross-sectional views illustrating a method for forming a quantum dot in accordance with a preferred embodiment of the present invention.  
         [0021]    Referring to FIG. 2A, a first insulating layer  22  is formed on a semiconductor substrate  21  through an oxidation process or a deposition process. At this time, the first insulating layer  22  is a silicon oxide or a silicon nitride, and the semiconductor substrate  21  is a semiconductor layer including silicon in addition to a silicon layer.  
         [0022]    Next, a photosensitive film is coated on the first insulating layer  22  ad patterned through a photo-exposure process and a developing process so as to form a first mask  23 . Thereafter, the first insulating layer  22  is proceeded with a dry etching by using the first mask  23  as an etch mask so to form a first opening  24 A that expose the substrate  21 . Herein, the first opening  24 A is the place where a subsequent single crystal silicon layer is grown. Particularly, the substrate  21  exposed within the first opening  24 A enacts as a seed layer for growing the single crystal silicon layer.  
         [0023]    With reference to FIG. 2B, the first mask  23  is removed. FIG. 3A is a plane view showing the first opening  24 A and the first insulating layer  22  formed on the substrate (not shown) after removing the first mask  23 . The first opening  24 A formed by etching the first insulating layer  22  has a square shape. However, the first opening  24 A can also have a circular or a crisscross shape. A number of the first openings  24 A are neighbored to each other with a consistent distance between them.  
         [0024]    Meanwhile, there remained remnants from the etching (not shown) at lateral and lower sides of the first opening  24 A. Also, there occurs a lattice defect on a surface of the substrate  21  due to the etching process.  
         [0025]    A thermal process is employed to remove the remnants and the lattice defect in an atmosphere of hydrogen or in a vacuum state. This type of thermal process is called a bake process. The bake process also simultaneously removes a native oxide formed on the substrate  21  exposed within the first opening  24 A through the bake process.  
         [0026]    Referring to FIG. 2C, a single crystal silicon layer  25  is formed on the exposed substrate  21  within the first opening  24  with use of a selective epitaxial growth (hereinafter referred as to SEG) technique. At this time, the single crystal silicon layer  25  has a thickness ranging from about 2 nm to about 100 nm. Subsequently, the single crystal silicon layer  25  is gone through the SEG by using the exposed substrate  21  as a seed layer. Simultaneous to the SEG, the single crystal silicon layer  25  is also grown on the first insulating layer  22  adjacent to the first opening  24 A due to lateral over-growth.  
         [0027]    As a result, the single crystal silicon layer  25  fills completely the first opening  24 A, and is overlapped on the first insulating layer  22  adjacent to the first opening  24 A through the lateral over-growth, which is a unique characteristic of the SEG technique. This overlapping results in enlarged patterns, as shown in o FIG. 3B, which is a plane view showing the silicon layer  25  formed on the substrate (not shown) through the SEG. The single crystal silicon layer  25  has a square shape according to the shape of the first opening  24 A. However, the size of the square is bigger than the first opening  24 A because of the simultaneous filling of the first opening  24 A and the lateral over-growth. However, the neighbored single crystal silicon layers  25  are not contacted to each other.  
         [0028]    In the mean time, an ultra high vacuum chemical vapor deposition (UHV CVD) technique is employed to proceed the SEG of the single crystal silicon layer  25 . Such mixture as Si 2 H 2 Cl 2 /H 2 /HCl/PH 3  or SiH 4 /H 2 /HCl/PH 3  can be used as a source gas. Also, controlling a flow quantity of the PH 3  gas controls a doping concentration of the single crystal silicon layer  25 , thereby controlling electric conductivity and tunneling currents. Furthermore, a flow quantity of the source gas is also controlled to have deposition selectivity to the single crystal silicon layer  25  and the first insulating layer  22 .  
         [0029]    With reference to FIG. 2D, a photosensitive film is coated on the first insulating layer  22  including the single crystal silicon layer  25  and patterned through a photo-exposure and a developing processes so as to form a second mask  26 .  
         [0030]    [0030]FIG. 3C is a plane view showing the second mask  26  formed on the substrate (not shown). The second mask  26  has a first open area  26 A and second open areas  26 B. The first open area  26 A exposes the most of the single crystal silicon layer  25  including a central portion that fill the first opening  24 A. The second open areas  26 B expose portions of the single crystal silicon layer  25  on the first insulating layer  22  adjacent to the first opening  24 A.  
         [0031]    Next, the exposed single crystal silicon layer  25  is proceeded with a dry etching or a wet etching by using the second mask  26  as an etch mask so as to form a number of quantum dots  25 A constructed with the single crystal silicon.  
         [0032]    At this time, all portions of the single crystal silicon layer  15  filled within the first opening  24 A and the portions of the single crystal layer on the first insulating layer adjacent to the first opening are removed. That is, portions formed by the lateral over-growth on the first insulating layer  22  adjacent to the first opening and covered the second mask  26  are not removed, thereby forming the quantum dot  25 A.  
         [0033]    Also, a second opening  24 B exposed after etching the single crystal silicon layer  25  is different from the first opening  24 A shown in FIG. 2A. The second opening  24 B is opened as the same area of the single crystal silicon layer excluding the quantum dot  25 A. Thus, the second opening  24 B has a wider opening than the first opening  24 A.  
         [0034]    Referring to FIG. 2E, the second mask  26  is subsequently removed. FIG. 3D is a plane view showing quantum dots  25 A on the first insulating layer  22  after removing the second mask  26 . As shown in FIG. 3D, the quantum dot  25 A is formed on the first insulating layer  22  along edges of the first opening  24 A in the first insulating layer  22 .  
         [0035]    With reference to FIG. 2F, a second insulating layer  27  is formed on the first insulating layer  22  and a number of quantum dots  25 A. At this time, the second insulating layer  27  is formed with a silicon oxide layer.  
         [0036]    Hence, the pluralities of the quantum dots  25 A are positioned between the first insulating layer  22  and the second insulating layer  27 . That is, the pluralities of the quantum dots  25 A are positioned within the insulating layers.  
         [0037]    As described in the above, it is possible to form a uniform quantum dot array by using the lateral over-growth of the SEG technique and the photolithography. Also, it is widely applicable to fabricate a single electron transistor using the method for forming a uniform quantum array and a semiconductor device using the tunneling phenomenon.  
         [0038]    [0038]FIG. 4 is a cross-sectional view showing a single electron transistor in accordance with the preferred embodiment of the present invention.  
         [0039]    Referring to FIG. 4, a tunneling oxide layer  32  is formed on a semiconductor substrate  31  constructed with silicon or Ge—As. Herein, the tunneling oxide  32  is a silicon oxide layer.  
         [0040]    On the tunneling oxide layer  32 , a quantum dot  33  is formed. Herein, the quantum dot  33  is a single crystal silicon pattern with a fine size having a length, a width and a height all in about 50 nm. That is, the quantum dot  33  is formed to have a size that provides the coulomb barrier phenomenon occurring when a single electron or a few electrons are tunneled.  
         [0041]    A control oxide layer  34  is formed to cover the quantum dot  33 . The control oxide layer  34  is a silicon oxide layer or a silicon nitride layer.  
         [0042]    Then, a gate electrode  35  is formed on top of the control oxide layer  34 . A source area  36  and a drain area  37  is formed by implanting n-type or p-type dopants within the substrate  31  on both lateral sides of the gate electrode  35 .  
         [0043]    A main principle of the single electron transistor having the structure described in FIG. 4 is identical as of an electrically erasable programmable read only memory (EEPROM) device. The differences are that the single electron transistor can change a threshold voltage with a single electron or a few electrons in contrast to the EEPROM, and can be operated at a lower voltage than the EEPROM. That is, if a voltage greater than the threshold voltage is supplied to the gate electrode  35 , an inverse layer is formed on a channel area, and electrons of the source area  36  are induced towards the channel area, thereby reducing channel conductance. With the above-described state, electrons provided from the inverse layer of the channel area are tunneled and enter one by one to the quantum dot  33  through a thin tunneling oxide layer at a room temperature. As the electrons enter to the quantum dot  33 , the threshold voltage changes. Therefore, it is preferable to perform programming by tunneling one electron. However, it is difficult to detect a change in the threshold voltage. Hence, the programming is generally carried out by tunneling about 3 to 4 electrons simultaneously to change the threshold voltage in about 1 V.  
         [0044]    On the other hand, during an erase operation, if a consistent negative voltage, i.e., a voltage drawing out electrons within the quantum dot  33 , is supplied to the gate electrode  35 , then, it is possible to draw out the electron from the quantum dot  33 .  
         [0045]    As a result, the threshold voltage is shifted to the original one, resulting in an ease of classifying ‘1’ or ‘0’ state.  
         [0046]    Although, the single crystal silicon layer is grown to form the quantum dot by the SEG technique in the above-preferred embodiment, it is still possible to form a various single crystal layer with materials as Si—Ge, Co—Si and the like, which has an epitaxial relation with silicon substrate.  
         [0047]    The present invention also provides an effect of improving reliability and massproduction simultaneously by forming a number of quantum dots constructed with single crystal silicon through the SEG technique and the known lithography technique.  
         [0048]    While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.

Technology Category: h