Patent Document

BACKGROUND OF THE PRESENT INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to diode packages, and more particularly to a diode chip package no containing outer lead pins and a process for producing the diode package. 
         [0003]    2. Description of Related Art 
         [0004]    As shown in  FIG. 1 , a packaged IC or semiconductor device  80  (hereinafter referred to as a semiconductor package  80 ) contains three important key components, namely, a lead frame  81 , bonding wires  82  and a sealed housing  83 . 
         [0005]    Before packaged, an IC or semiconductor die  84  (hereinafter referred to as a semiconductor chip  84 ) is firstly bound onto a die pad (or chip holder) of the lead frame  81 , and then said bonding wires  82  allow to make interconnections between said semiconductor chip  84  and said lead frame  81  during semiconductor device fabrication, so that the semiconductor chip  84  is electrically connected to the lead frame  81 . Moreover, the sealed housing  83  is to package said lead frame  81  and said semiconductor chip  84  and make them isolated from outside environment as well as to allow some outer lead pins (or contacts)  85  to be extended from the lead frame  81  to relative lateral surfaces (or a lower surface) of the semiconductor package  80  thereof and finally further extendedly exposed to outside environment. 
         [0006]    The semiconductor package  80  can be formed with Pin-Through-Hole (PTH) package or Surface-Mount Technology (SMT) package and used to install in a socket or directly soldered to a printed circuit board to transfer internal functions of the semiconductor package  80  to an external interface of the printed circuit board. 
         [0007]    Accordingly, during semiconductor device fabrication the lead frame  81  plays a role of key component to dominate a preferred quality of the semiconductor package  80 , so that different lead frames are suitably varied for use in package of various semiconductor chips  84 . 
         [0008]    As shown in  FIG. 1 , when a semiconductor diode chip with a p-n junction (hereinafter referred to a diode chip) is chosen to replace said semiconductor chip  84 , there are various kinds of lead frames  81  with different shapes of outer lead pins  85  shown in  FIG. 2  can be chosen to produce a semiconductor diode package  90  (hereinafter referred to as a diode package  90 ) during semiconductor device fabrication. 
         [0009]    Presently, all known diode packages  90  have outer lead pins  85  formed as a basic structure. However, said diode packages  90  due to having outer lead pins  85  is apt to cause problems of dimensional inaccuracy, this shortcoming tends to jeopardize and affect stability of processing a Surface-Mount Technology (SMT) package for the diode packages  90 . 
       SUMMARY OF THE INVENTION 
       [0010]    To improve prior known diode packages more excellent in practical application, the primary objective of the present invention is to provide a chip scale diode package with simpler structural constitution no containing outer lead pins, which basic structure at least comprises a diode chip, a pair of mirrored lead frame electrodes formed as internal electrodes being electrically connected to upper and lower surfaces of the diode chip, a sealed casing to encase the diode chip and the mirrored lead frame electrodes except allowing two ends of the mirrored lead frame electrodes to be exposed to relative lateral surfaces of the sealed casing, and two opposite external electrodes each coated to one of said relative lateral surfaces of the sealed casing to obtain an electrical connection with one corresponding end of the mirrored lead frame electrodes. 
         [0011]    Another objective of the present invention is to provide a process for producing a chip scale diode package, comprising the following steps:
       a) preparing a pre-stamped component having one or more lead frame plates and plural positioning holes formed in symmetrical positions thereof,   b) arranging a mirrored pre-stamped components formed from two identical pre-stamped components of step a) by having one shifted with 180 degrees from and mirrored to the other one, and aligning them through their positioning holes;   c) coating lead-free conductive pastes to any predetermined area of the mirrored pre-stamped components of step b) where is designated to fix one relative diode chip;   d) bonding one or more diode chips precisely soldered to any corresponding predetermined area of step c) to let any diode chip have its own upper and lower surfaces respectively soldered with one relative lead frame plate from the mirrored pre-stamped components;   e) packaging a sealed casing to encase every diode chip and every lead frame plate of step d) except every lead frame plate having one end exposed to one lateral surface of the sealed casing;   f) covering an external electrode to each relative lateral surface of the sealed casing where exposed of corresponding lead frame plate&#39;s end of step e) by coating, dipping, evaporation or sputtering process and to have every external electrode electrically connected with every corresponding end of the mirrored lead frame electrodes encased with the sealed casing; and   g) obtaining a chip scale diode package with simpler structural constitution no containing outer lead pins.       
 
         [0019]    A chip scale diode package produced by the present process can be formed as a SMT diode package with a single diode chip or an array-type SMT diode package with multiple diode chips. 
         [0020]    The disclosed diode package is novel as it no contains outer lead pins, and has the following benefits:
       1. the diode package is miniaturized like a chip scale appearance, no leaves outer lead pins outsides and effectively promotes dimensional accuracy of diode package;       
 
         [0022]    2. due to no containing outer lead pins the diode package produced by the present process may contain one or more diode chips to increase and improve diverse and versatile functions suited for use in various industrial applications; 
         [0023]    3. as compared to prior known semiconductor device, the diode package due to structure simpler is economically suited for automated mass production via automation equipment; and 
         [0024]    4. the diode package due to made of no lead-containing material conforms to requirements for environmental protection. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]      FIG. 1  is a schematic drawing showing a conventional IC or semiconductor package. 
           [0026]      FIG. 2  illustrates prior known semiconductor diode packages have outer lead pins formed in various shapes. 
           [0027]      FIG. 3  is a schematic drawing showing a chip scale diode package of the present invention no containing outer lead pins. 
           [0028]      FIG. 4  is a schematic drawing showing two identical lead frames are used to hold a diode chip during manufacture of diode packages of the present invention. 
           [0029]      FIG. 5  is a partial cross section drawing to show a semi-product of the disclosed diode packages of the present invention not yet having external electrodes formed thereof. 
           [0030]      FIG. 6  is another partial cross section drawing to show a finished product of the disclosed diode packages of the present invention having external electrodes formed thereof. 
           [0031]      FIG. 7  is a schematic drawing showing another embodiment of diode packages of the present invention having multiple external electrodes formed thereof. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0032]    Referred to  FIG. 3 , a chip scale diode package  10  of the present invention is herein defined a diode package miniaturized in whole package size like chip scale has two ends formed with external electrodes  60  thereof and particularly no contains any outer lead pins exposed outside. 
         [0033]    Referred to from  FIG. 4  to  FIG. 6 , the diode package  10  of the present invention at least comprises a diode chip  20 , two lead frame electrodes (or called internal electrodes)  33 , a sealed casing  50  and two external electrodes  60 . 
         [0034]    The technical feature of said diode package  10  of the present invention is that the diode chip  20  and the lead frame electrodes  33  are encased with the sealed casing  50  thereof, and both lead frame electrodes  33  with the same structure are respectively installed and connected to an upper surface and a lower surface of the diode chip  20  by a specific means of allowing both lead frame electrodes  33  to be shifted with 180 degrees from and mirrored to each other. For clarity, said two lead frame electrodes  33  are herein defined as mirrored lead frame electrodes (or internal electrodes)  33 . 
         [0035]    For more detailed description, each of mirrored lead frame electrodes  33  has one end connected onto either the upper surface or the lower surface of the diode chip  20  thereof, and has an opposite end not only extended to one lateral surface of the sealed casing  50  but also obtained an electrical connection with one corresponding external electrode  60  which is already coated on lateral surface of the sealed casing  50  thereof. 
         [0036]    Accordingly, said mirrored lead frame electrodes  33  after encased with the sealed casing  50  are designed as internal electrodes and electrically connected to external electrodes  60  of the diode package  10  thereof, resulted in that the disclosed diode package  10  of the present invention having diode characteristics can be used as a semiconductor diode. 
         [0037]    Referred to  FIG. 7 , another embodiment of the present invention is to disclose an array-type diode package  15 , which structural constitution in addition to having two or more diode chips  20  has the same basic structure as that of the diode package  10  mentioned above, which at least comprises two or more diode chips  20  each having corresponding mirrored lead frame electrodes  33  installed and connected to its upper surface and lower surface thereof, a sealed casing  50  encased all diode chips  20  and all mirrored lead frame electrodes  33  to form as a miniaturized package size like array-type chips scale, and multiple external electrodes for use in making electrical connection with corresponding mirrored lead frame electrodes  33  thereof. 
         [0038]    The diode package  10  or the array-type diode package  15  of the present invention may be any kind of semiconductor diode only if suitably made by a known semiconductor die bonding process, and preferably may be a transient voltage suppression diode (TVS diode), a Schottky diode, a switch diode, a Zener diode or a rectifier diode, but not limited. 
         [0039]    The mirrored lead frame electrodes  33  are formed from one or more lead-free conductive metals or its alloys selected from the group consisting of silver (Ag), tin (Sn), copper (Cu), gold (Au), nickel (Ni), palladium (Pd) and platinum (Pt), but not limited. 
         [0040]    The sealed casing  50  may be formed form a ceramic material or a plastic material, and preferably from an epoxy resin. 
         [0041]    Referred to from  FIG. 4  to  FIG. 6 , a conductive adhesive layer  41  formed from a lead-free conductive paste  40  is used to bond the diode chip  20  and the corresponding mirrored lead frame electrodes  33  together as an integrated structure. 
         [0042]    The lead-free conductive paste  40  contains one or more lead-free conductive metals selected from the group consisting of silver (Ag), tin (Sn), copper (Cu), gold (Au), nickel (Ni), palladium (Pd) and platinum (Pt), but not limited. 
         [0043]    Said external electrodes  60  are made using the known process for coating, dipping, evaporation or sputtering process, and the external electrodes  60  are formed from one or more lead-free conductive metals or its alloys selected from the group consisting of silver (Ag), tin (Sn), copper (Cu), gold (Au), nickel (Ni), palladium (Pd) and platinum (Pt), but not limited. 
         [0044]    As matched for use in various industrial applications, the diode package  10  of  FIG. 3  or  FIG. 6  is designed to have a single diode chip  20  and packaged as a chip scale semiconductor diode with SMT package (abbreviated as a SMT diode package), or the array-type diode package  15  of  FIG. 7  is designed to have multiple diode chips  20  and packaged as an array-type semiconductor diode with SMT package (abbreviated as an array-type SMT diode package). 
         [0045]    As shown in  FIG. 4 , a process for producing the diode package  10  or the array-type diode package  15  of the present invention is to teach a pre-stamped component  30  is prepared in advance, wherein the structural constitution of the pre-stamped component  30  at least includes one or more lead frame plates  31  arranged in parallel and spaced a distance each other, and plural positioning holes  35  formed in symmetrical positions on the pre-stamped component  30  thereof. 
         [0046]    The key technical feature regarding for producing a SMT diode package or an array-type SMT diode package of the present invention is that two identical pre-stamped components  30  are intentionally used and shifted with 180 degrees from each other, and then through their corresponding positioning holes  35  to make them aligned and stacked as two stackable mirrored pieces. For clarity, said two identical pre-stamped components  30  shifted with 180 degrees from and mirrored to each other are herein defined as mirrored pre-stamped components  30 . 
         [0047]    Said novel mirrored pre-stamped components  30  are suited for producing semiconductor diode, and its practical application can be contributive to design specific automatic packing equipment for use in automatically producing said diode package  10  or said array-type diode package  15  of the present invention and get a mass production of the diode package  10  or the array-type diode package  15  thereof. 
         [0048]    The process for producing chip scale diode package  10  or array-type diode package  15  of the present invention is capable of producing above-mentioned SMT diode packages or array-type SMT diode packages. A chip scale diode package  10  is taken as an illustrated example, of which process for producing the same comprises the steps of: 
         [0049]    1. Arranging mirrored pre-stamped components  30 ; 
         [0050]    As shown in  FIG. 4 , two identical pre-stamped components  30  each having one or more lead frame plates  31  are shifted with 180 degrees from and mirrored to each other, and are aligned them in accurate position by using their positioning holes  35  to be stacked. 
         [0051]    2. Coating lead-free conductive pastes  40 ; 
         [0052]    As shown in  FIG. 4 , by means of printing or coating process, a lead-free conductive paste  40  is applied to a predetermined area designated on each lead frame plate  31  of the pre-stamped components  30 , where is planned to make the diode chip  20  precisely fixed thereto. 
         [0053]    3. Bonding and soldering diode chip  20 ; 
         [0054]    As shown in  FIG. 4 , a die bonder is used to allow each diode chip  20  precisely bonded to its corresponding lead frame plate  31  of which is arranged from the pre-stamped components  30  for bonding the diode chip  20 . By die bonding technology, every gap spaced between one diode chip  20  and its two corresponding lead frame plates  31  arranged from one set of mirrored pre-stamped components  30  for bonding the diode chip  20  is evenly filled with lead-free conductive pastes  40 . 
         [0055]    After baked, said lead-free conductive paste  40  is cured into a conductive adhesive layer  41 , resulted in that on upper surface the diode chip  20  is bonded with a first lead frame plate  31  and on lower surface the diode chip  20  is bonded with a second lead frame plate  31  being shifted with 180 degree from and mirrored to the first lead frame plate  31 , all components are tightly bonded as soldered. 
         [0056]    4. Packaging and making mirrored lead frame electrodes (or internal electrodes)  33 ; 
         [0057]    As shown in  FIG. 5 , the diode chip  20  after having both upper and lower surfaces soldered with its corresponding lead frame plate  31  is placed into a packaging mold, and semi-molten resin is injected into the mold. 
         [0058]    After the resin is cured, a sealed casing  50  is formed to encase the diode chip  20  and the two corresponding lead frame plates  31  arranged for bonding the diode chip  20 . After deflashing and trimming, each lead frame plate  31  soldered to the diode chip  20  has one end extended to one lateral surface of the sealed casing  50 , so that the two corresponding lead frame plates  31  soldered to both upper and lower surfaces of the diode chip  20  are formed as mirrored lead frame electrodes (or internal electrodes)  33  of the sealed casing  50 . 
         [0059]    5. Covering external electrodes  60  to obtain a finished diode package  10  no containing outer lead pins; 
         [0060]    As shown in  FIG. 5  and  FIG. 6 , each lateral surface of the sealed casing  50  by means of coating, silver dipping or thin film process is coated with an external electrode  60  to electrically connect with the internal electrodes  33  of the sealed casing  50 , and then a chip scale diode package  10  of the present invention is finished. 
         [0061]    As shown in  FIG. 3  or  FIG. 7 , the finished diode package  10  no containing any outer lead pins after measured of physical properties has diode characteristics, so that the diode package  10  of the present invention is qualified to be used as a semiconductor diode. 
         [0062]    As a result, due to no use of lead-containing tin paste, the process for producing chip scale diode package  10  or array-type diode package  15  of the present invention conforms to various international requirements for environmental protection. Further, due to no containing of outer lead pins, the chip scale diode package  10  or array-type diode package  15  produced by the presented process is free from problems of dimensional inaccuracy, capable of promoting package stability, and particularly suited for automated mass production.

Technology Category: 5