Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
     This patent application claims priority from Indian Provisional Application No. 2904/CHE/2008, filed 24 Nov. 2008, the entirety of which is incorporated herein by reference. 
     TECHNICAL FIELD 
     The invention relates generally to a delay locked loop (DLL), and more particularly, to a DLL that includes watchdog circuit. 
     BACKGROUND 
     Referring to  FIG. 1  of the drawings, the reference numeral  100  generally designates a conventional DLL. DLL  100  generally comprises a phase detector (PD)  102 , a charge pump  104 , a loop filter  106 , and a delay line  108  (which includes a set of buffers  110 - 1  to  110 - n ). In operation, DLL  100  is supposed to lock so that total delay D of the delay line  108  is approximately equal to period of the reference clock signal REF. Lock is achieved with the help of PD  102 ; however, PD  102  is generally limited to operating under the condition that the delay D is between 0 and twice the period of the reference clock signal REF. If delay D is outside of this range, DLL  100  can potentially to lock to other multiples of the period of the reference clock signal REF (harmonic lock) and can cause functional failure. Thus, there is a need for a circuit to generally ensure that the delay remains in a predetermined range. 
     An example of another conventional DLL is U.S. Pat. No. 6,977,605. 
     SUMMARY 
     In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a phase detector (PD) that receives a clock signal; a charge pump that is coupled to the phase detector; a loop filter that is coupled to the charge pump; a delay line having a plurality of taps and a delay, wherein the delay line receives the clock signal, and wherein the delay line is coupled to the loop filter and the PD; a watchdog circuit that is coupled to the delay line so as to receive a first signal from a first tap of the plurality of taps and a second signal from a second tap of the plurality of taps, that receives the clock signal, and that is coupled to at least one of the charge pump and PD, wherein the watchdog circuit compares a rising edge from the first signal to a corresponding rising edge from the second signal, and wherein, when the rising edge from the first signal occurs before the corresponding rising edge from the second signal, the watchdog circuit determines that the delay of the delay line is within a predetermined range, and wherein, when the when the rising edge from the first signal occurs after the corresponding rising edge from the second signal, the watchdog circuit adjusts the charge pump so as to adjust the delay to be within the predetermined range. 
     In accordance with a preferred embodiment of the present invention, the delay line further comprises a plurality of buffers that are coupled in series with one another and that are each coupled to the loop filter. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is an example of a conventional DLL; 
         FIG. 2  is an example of a DLL in accordance with a preferred embodiment of the present invention; and 
         FIGS. 3 through 5  are example timing diagrams for the DLL of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION 
     Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
     Referring to  FIG. 2  of the drawings, the reference numeral  200  generally designates a DLL in accordance with a preferred embodiment of the present invention. DLL  200  generally comprises PD  202 , charge pump  204 , loop filter  106 , delay line  108 , and watchdog circuit  206 . 
     In operation, DLL  200  has a similar operation to DLL  100 , but the watchdog circuit  206  is provided to generally ensure that the delay D of delay line  108  remains within a predetermined range. Typically, watchdog circuit  206  is coupled to several taps (typically two) from delay line or coupled to the outputs from two of the buffers  110 - 1  to  110 - n  and receives the reference clock signal REF. Watchdog circuit  206  generally detects three edges from the delay line  108  (through the taps) to perform “harmonic detection.” The first edge is generally an edge from the clock signal, while the second and third edges (E 1  and E 2 , respectively) are from the taps such that the second edge (E 1 ) occurs before the third edge (E 2 ). Under the circumstances, where the edges occur in order, the delay D is determined to be within a predetermined range, and the watchdog circuit  206  outputs a harmonic detect signal HD to the PD  202  and/or charge pump  204  indicating this (i.e., HD=0). If the third edge occurs before the second edge, the watchdog circuit  206  determines that the delay D of the delay line  108  is outside of the predetermined range (i.e. D∉[0,2T], where T is the period of the reference clock signal REF), and the watchdog circuit  206  outputs a harmonic detect signal HD to the PD  202  and/or charge pump  204  indicating this (i.e., HD=1). 
     Turning now to  FIGS. 3 through 5 , example timing diagrams for the DLL  200  can be seen. In  FIG. 3 , the corresponding rising edges occur in order, so the harmonic detect signal from watchdog circuit  206  would reflect that the delay D of delay line  108  is within the predetermined range (i.e., D∈[0,2T]). Thus, for  FIG. 3 , the watchdog circuit  206  outputs a harmonic detect signal HD to the PD  202  and/or charge pump  204  indicating this (i.e., HD=0). In  FIG. 4 , the delay for each of edges E 1  and E 2  are less than the period T of reference clock signal REF, but the difference between the delay for edge E 2  and period T is less than the delay for edge E 1  (i.e., DE 2 −T&lt;DE 1 ). So, for  FIG. 4 , the watchdog circuit  106  would output a harmonic detect signal HD (i.e., HD=1) to the PD  202  and/or charge pump  204  indicating that the delay D of the delay line  108  is outside of the predetermined range (i.e. D∉[0,2T]). In  FIG. 5 , the edges occur in order, so that the watchdog circuit  106  would output a harmonic detect signal HD (i.e., HD=0) to the PD  202  and/or charge pump  204  indicating that the delay D of the delay line  108  is within of the predetermined range (i.e. D∈[0,2T]). 
     As can be seen from  FIGS. 3 through 5 , the watchdog circuit  206  uses the timings of these edges to calculate a harmonic lock, but the harmonic is related to the choice of the edges E 1  and E 2 . For the lower range of the watchdog circuit  206 , the following equations are used: 
                     DE   ⁢           ⁢   2     &gt;   T           (   1   )                 D   &gt;       N   ⋆   T         E   ⁢           ⁢   2     ⁢                 ,           (   2   )               
where N is the number of taps for delay line  108 . For the upper range of the watchdog circuit  206 , the following equations are used:
 
                     DE   ⁢           ⁢   1     &gt;       T   ⁢           ⁢   or   ⁢           ⁢   DE   ⁢           ⁢   2     -   T     &gt;     DE   ⁢           ⁢   1             (   3   )               D   &lt;     min   ⁢     {         N   ⋆   T         E   ⁢           ⁢   2     ⁢               ,       N   ⋆   T         E   ⁢           ⁢   2     -     E   ⁢           ⁢   1           }               (   4   )               
For example, if N=48, E 1 =15 (15 th  tap), and E 2 =30 (30 th  tap), the watchdog circuit  206  will detect a harmonic when 1.6T&lt;D&lt;3.2T, so that this particular choice can detect the second and third harmonics. Additionally, multiple watchdog circuits  206  can be used in parallel with different taps (i.e., different values of E 1  and E 2 ) to determine whether higher order harmonic locks exist.
 
As an example, assuming the watchdog circuit  206  detects harmonic a harmonic lock condition (i.e., HD=1) from delay D 1  (as per equation (2)) to D 2  (as given by equation (4), watchdog circuit  206  will also detect harmonic from
 
 D 2+ M*D 1 to  (5)
 
 D 2+ M*D 2,  (6)
 
where M is a non-negative integer number. This property can reduce number of watchdog circuits  206  used in parallel to detect higher order harmonics. If an aim of the watchdog circuit  106  is to detect any harmonic less than the sixteenth harmonic for delay line containing 128 cells and if cases for only M=0 are considered, watchdog circuits  106  in parallel would be used. However, if cases for M&gt;0 are considered, all the harmonics less than the seventeenth harmonic will be covered with first 3 watchdogs itself. Table 1 demonstrates these cases.
 
     
       
         
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 N 
                 128 
                   
                   
                   
                   
                   
                   
                   
                   
                   
                   
                   
                   
               
             
          
           
               
                 T 
                 1 
                   
                   
                   
                 NT/(E2- 
                 M = 0 
                 M = 1 
                 M = 2 
                 M = 3 
               
             
          
           
               
                 No 
                 E1 
                 E2 
                 NT/E2 
                 NT/E1 
                 E1) 
                 L 
                 H 
                 L 
                 H 
                 L 
                 H 
                 L 
                 H 
               
               
                   
               
             
          
           
               
                 1 
                 32 
                 64 
                 2.0 
                 4.0 
                 4.0  
                 2.0  
                 4.0 
                 6.0 
                 8.0 
                 10.0 
                 12.0 
                 14.0 
                 16.0 
               
               
                 2 
                 17 
                 34 
                 3.8 
                 7.5 
                 7.5 
                 3.8 
                 7.5 
                 11.3 
                 15.1 
                 18.8 
                 22.6 
                 26.4 
                 30.1 
               
               
                 3 
                 9 
                 18 
                 7.1 
                 14.2 
                 14.2  
                 7.1 
                 14.2 
                 21.3 
                 28.4 
                 35.6 
                 42.7 
                 49.8 
                 56.9 
               
               
                 4 
                 5 
                 10 
                 12.8 
                 25.6 
                 25.6 
                 12.8 
                 25.6 
                 38.4 
                 51.2 
                 64.0 
                 76.8 
                 89.6 
                 102.4 
               
               
                   
               
             
          
         
       
     
     Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.

Technology Category: 5