Patent Document

FIELD OF THE INVENTION  
       [0001]     The invention relates to a method for operating a phase locked loop (PLL). The invention relates equally to a PLL and to components, devices and systems comprising a PLL.  
       BACKGROUND OF THE INVENTION  
       [0002]     PLLs can be used, for example, for realizing frequency synthesizers of cellular phones. In a cellular phone, a frequency synthesizer is an essential part of a radio receiver integrated circuit (IC) and of a radio transmitter IC.  
         [0003]     A typical PLL comprises, connected to each other in a loop in this order, a voltage controlled oscillator (VCO), a programmable frequency divider, a phase detector, a charge pump and a loop filter.  
         [0004]     The VCO transforms a low frequency control voltage, in particular a direct-current (DC) control voltage, into a radio frequency (RF) signal. A change of the control voltage is reflected in a change of frequency of the generated RF signal in accordance with the gain of the VCO. The frequency of the signal output by the VCO is divided by a factor currently set in the programmable frequency divider. The phase comparator then compares the phase of the resulting frequency divided signal with the phase of a reference signal, and outputs a signal representing the detected phase difference. The charge pump generates current impulses, the length of which are controlled by the output signal of the phase detector. The generated current pulses are filtered by the loop filter, which provides a corresponding DC control voltage to the VCO and thus takes care that the VCO generates a signal which is locked to a desired frequency.  
         [0005]     The frequency of the RF signals output by the VCO can be changed by changing the division ratio applied by the programmable divider.  
         [0006]     The loop filter of the PLL may be active or passive and is typically some kind of an RC-filter. It includes at least one capacitor storing the driving DC control voltage for the VCO in order to ensure a stable supply of the DC control voltage to the VCO.  
         [0007]     When the division ratio applied by the frequency divider is changed in order to change the frequency of the VCO output signal, the phase detector detects suddenly a large phase difference between the frequency divided VCO output signal and the reference signal. As a result, the voltage over the capacitor of the loop filter changes rapidly. In the dielectric insulator layer of a capacitor, there exists a physical phenomenon called dielectric absorption. The dielectric absorption is a consequence of a slowness of molecule dipoles in a dielectric material. After a rapid voltage change, the phenomenon tends to partly move the voltage across the capacitor back to the original value.  
         [0008]      FIG. 1  presents a model of the dielectric absorption of a capacitor C 11 . The model includes a resistor-capacitor (RC) circuit, comprising a series connection of a resistor R 11  and of a capacitor C 12 , which is arranged in parallel with the actual capacitor C 11 . The RC circuit causes the parasitic side effect.  
         [0009]     For external, non-integrated loop filters, solid capacitors of the np0 type are available, for which the dielectric absorption is at a level, that PLL settling time specifications can be met. This kind of capacitors can not be integrated, however, so this solution is expensive.  
         [0010]     In highly dielectric capacitors, in contrast, which are used in modern integrated circuits, the effect of the dielectric absorption is significant. In the case of integrated capacitors, the time constant of the parasitic RC circuit depicted in  FIG. 1  can be some milliseconds or even more. This makes a PLL equipped with such a capacitor too slow for some applications, for instance for a usage in a cellular phone.  
         [0011]     In U.S. patent application 2004/0100311 A1, the problem of the dielectric absorption of PLL loop filter capacitors in conjunction with the change in the tuning voltage of a PLL is addressed as well. In this document, it is proposed to compensate for the memory effect of the loop filter capacitors by means of a resonant frequency pre-selection in the VCO. To this end, the VCO has a frequency-determining capacitance controlled through a second tuning input. It is proposed that this capacitance is controlled by the same frequency word as the frequency divider such that a change in the tuning voltage upon a change in the frequency word is as small as possible.  
         [0012]     It is a disadvantage of such an approach that the accuracy may not be satisfactory due to the fact that a PLL includes many variables that cannot be predicted by reading the divider input. This applies in particular to component variations and thermal drifts. The resulting system thus needs a lot of frequency overlapping between each rough step. As a consequence, the design of the most critical components, for example the VCO, becomes very difficult. Further, the window in which the system is able to tune the VCO might be too large to avoid the memory effect.  
       SUMMARY OF THE INVENTION  
       [0013]     It is an object of the invention to provide a different solution for dealing with the dielectric absorption in loop filter capacitors of a PLL. It is an object of the invention to enable the use of integrated loop filters without requiring an adjustment of the resonance frequency of the VCO.  
         [0014]     A method for operating a PLL is proposed. The PLL is assumed to comprises a VCO and a loop filter. The VCO generates an alternating-current (AC) output signal having a frequency which depends on an applied control voltage. The loop filter provides a control voltage to the VCO, which reflects determined phase differences between a, potentially frequency divided, output signal of the VCO and a reference signal. The proposed method comprises detecting frequency deviations between a, potentially frequency divided, output signal of the VCO and a reference signal, wherein a resolution employed for detecting the frequency deviations is lower than a resolution employed for determining the phase differences. The proposed method further comprises adding a DC voltage shift to the control voltage provided by the loop filter, in case a frequency deviation is detected.  
         [0015]     Moreover, a PLL is proposed, which comprises means for generating an alternating-current output signal having a frequency which depends on an applied control voltage. The proposed PLL further comprises means for providing a control voltage to the means for generating an alternating-current output signal, the control voltage reflecting determined phase differences between a, potentially frequency divided, output signal of the means for generating an alternating-current output signal and a reference signal. The proposed PLL further comprises means for detecting frequency deviations between a, potentially frequency divided, output signal of the means for generating an alternating-current output signal and a reference signal, wherein a resolution employed for detecting the frequency deviations is lower than a resolution employed for determining the phase differences. The proposed PLL further comprises means for adding a direct-current voltage shift to a control voltage provided by the loop filter, in case a frequency deviation is detected by the means for detecting frequency deviations.  
         [0016]     Moreover, a PLL is proposed, which comprises a VCO adapted to generate an AC output signal having a frequency which depends on an applied control voltage. The proposed PLL further comprises a loop filter adapted to provide a control voltage to the VCO. The control voltage reflects determined phase differences between a, potentially frequency divided, output signal of the VCO and a reference signal. The proposed PLL further comprises a coarse tuning circuit. The coarse tuning circuit is adapted to detect frequency deviations between a, potentially frequency divided, output signal of the VCO and a reference signal. A resolution employed for detecting the frequency deviations is lower than a resolution employed for determining the phase differences. The coarse tuning circuit is further adapted to add a DC voltage shift to a control voltage provided by the loop filter, in case a frequency deviation is detected.  
         [0017]     Moreover, a frequency synthesizer, an IC, a radio receiver, a radio transmitter and an electronic device are proposed, which comprise the proposed PLL.  
         [0018]     Moreover, a communication system is proposed, which comprises at least one electronic device including the proposed PLL.  
         [0019]     Finally, a software program product is proposed, in which a software code for operating a phase locked loop is stored. The phase locked loop is assumed to comprise a voltage controlled oscillator and a loop filter, wherein the voltage controlled oscillator generates an alternating-current output signal having a frequency which depends on an applied control voltage, and wherein the loop filter provides a control voltage to the voltage controlled oscillator. The control voltage reflects determined phase differences between a, potentially frequency divided, output signal of the voltage controlled oscillator and a reference signal. When being executed, the software code detects frequency deviations between a, potentially frequency divided, output signal of the voltage controlled oscillator and a reference signal, wherein a resolution employed for detecting the frequency deviations is lower than a resolution employed for determining the phase differences. The software code further causes an adding of a direct-current voltage shift to the control voltage provided by the loop filter, in case a frequency deviation is detected.  
         [0020]     The invention proceeds from the idea that the tuning of a PLL could be split up into two parts. While the conventional PLL components may take care of a fine tuning, an additional frequency locked loop may take care of a coarse tuning. If the frequency locked loop operates on a coarser level, that is, with a lower resolution, than the conventional PLL, the frequency locked loop is faster than the conventional PLL. While changing the frequency channel, the VCO frequency is thus first quickly coarse tuned to a new value. The coarse tuning may be performed by components, which measure the frequency roughly and introduce an adequate DC shift into the VCO control circuit. As a result, the remaining frequency variations in the divided VCO output signal are so small that the voltage across the integration capacitor of the loop filter remains nearly constant, which implies that the occurring dielectric absorption is negligible.  
         [0021]     It is an advantage of the invention that it allows integrating a loop filter despite of the strong dielectric absorption occurring in integrated capacitors. The total settling time of the PLL, consisting now of a rough and a fine tuning, is shorter than the settling time of a conventional PLL using an integrated loop filter. The time savings result from the fast and effective coarse tuning. Also the fine tuning is fast, because the frequency step size remaining after the coarse tuning is very small. As the fine tuning of the PLL is performed in a conventional way, there is no disadvantageous effect on the general RF performance of the PLL either.  
         [0022]     With an integrated loop filter, significant cost savings in material can be achieved. The production of a PLL may also be rendered easier and quicker, if the very sensitive parts of the PLL are safely inside an IC.  
         [0023]     While the above cited U.S. patent application 2004/0100311 A1 proposes a pure feed forward system, which may reach only a poor accuracy, the invention makes use of a feedback system. This means that the frequency can be measured accurately every time the frequency is changed. As the influence of all strongly varying components may be reflected in the detected frequency deviations, the accuracy of the rough tuning can be sufficiently fine for ensuring an operation without any memory effect.  
         [0024]     In one embodiment of the invention, the level of the added DC voltage shift depends on an amount of a detected frequency deviation. The accuracy of the DC voltage shift can be selected by choosing the resolution of the detection of the frequency deviation.  
         [0025]     In one embodiment of the invention, the frequency deviations are detected on a digital basis, the resulting digital value representing an amount of a respective frequency deviation. The digital value may then be converted into an analog value, forming a basis for generating the DC voltage shift.  
         [0026]     The coarse tuning circuit of the proposed PLL may comprise to this end a frequency detector adapted to detect the frequency deviations on a digital basis and to output a digital value representing an amount of a respective frequency deviation. In addition, the coarse tuning circuit may comprise a digital-to-analog (D/A) converter adapted to convert a digital value output by the frequency detector into an analog signal. In addition, the coarse tuning circuit may comprise a DC level shifter adapted to add a DC voltage shift to the control voltage provided by the loop filter, using a level for the DC voltage shift which depends on an analog signal provided by the D/A converter.  
         [0027]     The loop filter of the proposed PLL can be realized in various forms. Moreover, it can be active or passive.  
         [0028]     In one embodiment of the invention, the loop filter is an active loop filter comprising an operational amplifier. In this case, the coarse tuning circuit may be adapted to add the DC voltage shift to an output voltage of the operational amplifier of the loop filter.  
         [0029]     In another embodiment of the invention, the loop filter is a passive loop filter. In this case, the coarse tuning circuit may be adapted to add a DC voltage shift by changing a bias voltage of the loop filter.  
         [0030]     The invention can be implemented in any PLL comprising a VCO and a loop filter, and thus as well in any component, device or system comprising such a PLL. It can be used for example, though not exclusively, in fixed or mobile radio communication devices.  
         [0031]     Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not drawn to scale and that they are merely intended to conceptually illustrate the structures and procedures described herein. 
     
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0032]      FIG. 1  is a simple model of a dielectric absorption in a capacitor;  
         [0033]      FIG. 2  is a schematic block diagram of an exemplary system in which the invention can be implemented;  
         [0034]      FIG. 3  is a schematic circuit diagram of a PLL according to a first embodiment of the invention for use in the system of  FIG. 2 ;  
         [0035]      FIG. 4  is a flow chart illustrating an operation in the PLL of  FIG. 3 ; and  
         [0036]      FIG. 5  is a schematic circuit diagram of a PLL according to a second embodiment of the invention for use in the system of  FIG. 2 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0037]      FIG. 2  is a schematic block diagram of an exemplary communication system according to the invention, in which a PLL according to an embodiment of the invention is implemented.  
         [0038]     The communication system is a cellular communication system comprising a network element  20  of a cellular communication network and a cellular phone  21 . The network element can be, for instance, a base station.  
         [0039]     The cellular phone  21  is an exemplary electronic device according to the invention. It comprises a transmitter  22  and a receiver  26 . It is to be understood that the functions of the transmitter  22  and the functions of the receiver  26  could also be combined in a transceiver.  
         [0040]     The transmitter  22  includes an IC  23  with a frequency synthesizer  24 . The frequency synthesizer  24  comprises a PLL  25 .  
         [0041]     The receiver  26  includes an IC  27  with a frequency synthesizer  28 . The frequency synthesizer  28  comprises a PLL  29 .  
         [0042]     The cellular phone  21  can be designed in a conventional manner, except that the PLL  25  of the transmitter  22  and the PLL  29  of the receiver  26  comprise a coarse tuning circuit.  
         [0043]     When data is to be transmitted by the cellular phone  21  to the network element  22 , the data has to be modulated in some way onto RF carrier signals. The frequency synthesizer  24  of the transmitter  22  is responsible for generating the required RF signals. The PLL  25  of the frequency synthesizer  24  multiplies to this end a reference frequency provided by a reference clock of the frequency synthesizer  24  (not shown) with an appropriate factor for obtaining an RF signal having a selected frequency.  
         [0044]     When modulated RF signals transmitted by the network element  20  are received at the cellular phone  21 , the receiver  26  downconverts the received RF signals by mixing them with a locally generated RF signal having a suitable frequency. Suitable RF signals are generated locally by the frequency synthesizer  28 . The PLL  29  of the frequency synthesizer  28  multiplies to this end the frequency of a reference signal provided by a reference clock of the frequency synthesizer  28  (not shown) with an appropriate factor.  
         [0045]      FIG. 3  presents a first embodiment of a PLL  25 ,  29  that may be implemented in the frequency synthesizers  24 ,  28  of the cellular phone  21  of  FIG. 2 .  
         [0046]     The PLL  25 ,  29  comprises a VCO  30 . The output of the VCO  30  is connected via a programmable frequency divider  31  on the one hand to a first input of a phase detector  32  and on the other hand to a first input of a digital frequency detector  36 . It has to be noted that the frequency detector  36  can be realized in hardware and/or in software that is executed by a processing component of the IC  23 ,  27  (not shown).  
         [0047]     Moreover, a reference clock signal REF CLOCK is applied on the one hand to a second input of the phase detector  32  and one the other hand to a second input of the frequency detector  36 . The reference clock signal is generated by the reference clock of the respective frequency synthesizer  24 ,  28  comprising the PLL  25 ,  29 .  
         [0048]     The output of the phase detector  32  is connected via a charge pump  33  to a first input of a loop filter, more specifically to the inverting input of a first operational amplifier  34  of the loop filter. In addition, a reference voltage V ref  is applied to the non-inverting input of the first operational amplifier  34 . The loop filter comprises in addition integrating capacitors. That is, a first capacitor C 31  is arranged between the inverting input of the first operational amplifier  34  and the output of the first operational amplifier  34 . Further, a series connection of a resistor R 31  and a second capacitor C 32  is arranged in parallel to the first capacitor C 31  between the inverting input of the first operational amplifier  34  and the output of the first operational amplifier  34 .  
         [0049]     The output of the first operational amplifier  34  is connected via further resistor R 32  to the inverting input of a second operational amplifier  38 . Moreover, the output of the frequency detector  36  is connected via a D/A converter unit  37  to the non-inverting input of the second operational amplifier  38 .  
         [0050]     A resistor R 33  is arranged between the inverting input of the second operational amplifier  38  and the output of the second operational amplifier  38 . The operational amplifier  38  and the resistors R 32  and R 33  form a DC shifter.  
         [0051]     The output of the second operational amplifier  38 , finally, is connected to a control input of the VCO  30 .  
         [0052]     The arrangement of VCO  30 , frequency divider  31 , phase detector  32 , charge pump  33  and loop filter  34 , C 31 , C 32 , R 31  corresponds to the arrangement in an exemplary conventional PLL using an active loop filter. In such a conventional PLL, the output of the loop filter is connected directly to an input of the VCO, though. The frequency detector  36 , the D/A converter unit  37  and the DC shifter  38 , R 32 , R 33  form an exemplary, digitally controlled coarse tuning circuit  35 , which is added according to the invention to a conventional PLL.  
         [0053]     The operation of the PLL  25 ,  29  depicted in  FIG. 3  will now be described in more detail with reference to the flow chart of  FIG. 4 .  
         [0054]     Apart from the influence by the coarse tuning circuit  25 , the PLL  25 ,  29  operates in a well known manner, as illustrated on the right hand side of  FIG. 4 .  
         [0055]     The VCO  30  thus generates and outputs an RF signal having a frequency, which is determined by a DC control voltage applied to the control input of the VCO  30  (step  401 ). The output signal of the VCO  30  is used as the output signal of the frequency synthesizer  24 ,  28 . In addition, the VCO output signal is frequency divided by the frequency divider  31  with a programmed factor (step  402 ). The resulting frequency divided VCO output signal is forwarded to the phase detector  32 . The phase detector  32  detects the phase difference Δφ between the frequency divided VCO output signal and the reference signal REF CLOCK, and outputs a corresponding error signal. (step  403 )  
         [0056]     The PLL  25 ,  29  is locked, when the phase difference Δφ between the frequency divided VCO output signal and the reference signal REF CLOCK is equal to zero, which implies that also the frequencies of the compared signals are equal. For achieving or maintaining a locked state, the charge pump  33  generates current impulses, the lengths of which are controlled by the error signal provided by the phase detector  32 . As indicated by its name, the charge pump  33  thus pumps charges i.e. a supplied current. The current impulses of the charge pump  33  are fed into the loop-filter. By means of its capacitors C 31 , C 32 , the loop-filter is able to provide a stable DC control voltage to the control input of the VCO  30 , which is adjusted continuously in accordance with the current impulses provided by the charge pump  33  and thus in accordance with the error signal provided by the phase detector  32 . (step  404 )  
         [0057]     This conventional operation is appropriate as long as the division ratio applied by the frequency divider  31  is kept constant. In this case, only a fine tuning is required once a locked state has been achieved.  
         [0058]     The division ratio applied by the frequency divider  31  is set to a new value, however, whenever the frequency synthesizer  24 ,  28  is required to provide an RF signal having a different frequency than before. In these cases, the conventional tuning would take a rather long time due to the dielectric absorption in the dielectric insulator layers of the capacitors C 31 , C 32  of the loop filter.  
         [0059]     In order to accelerate the tuning of the PLL  25 ,  29  to a new frequency, an additional coarse tuning is carried out by the coarse tuning circuit  35 , as illustrated on the left and side of  FIG. 4 .  
         [0060]     For the coarse tuning, the frequency detector  36  determines roughly the difference in frequency Δf between the divided VCO output signal and the reference signal REF CLOCK on a digital basis (step  405 ).  
         [0061]     The further steps  107  and  108  have only an impact, in case the frequency difference Δf is detectable with the selected resolution of the digital detection (step  406 ). Thus, in case the frequency deviation is small, the actual control of the PLL is left entirely to the conventional components.  
         [0062]     The digital value output by the frequency detector  36  is fed to the D/A converter unit  37 . The D/A converter unit  37  includes a D/A converter portion, which converts the digital value representing the current frequency deviation into an analog voltage, and a sequential logic portion, which drives the D/A converter portion. (step  407 )  
         [0063]     The output voltage of the D/A converter unit  37  is then used as a reference for the DC level shifter. The DC level shifter changes the DC level of the DC control voltage provided by the loop filter in accordance with the roughly determined frequency difference Δf. (step  408 )  
         [0064]     Thus, when changing the channel by reprogramming the frequency divider  31 , the frequency of a provided RF signal is first quickly coarse tuned to a new value. The fine tuning components then only have to take care of small phase differences such that the voltage over the integration capacitors C 31 , C 32  is nearly constant. The total loop gain stays stable and immune to the coarse tuning.  
         [0065]     The presented PLL  25 ,  29  can be designed for instance for an accuracy of 1 MHz. With the proposed coarse tuning, the fine tuning has to adjust the voltage in the loop filter only by about 20 mV to reach the precise frequency. Since the rough tuning by the coarse tuning circuit  35  can be realized to operate very fast and since the fine tuning circuit has to take care only of small adjustments, the PLL  25 ,  29  can be adjusted quickly to any new channel.  
         [0066]     The speed and the accuracy achieved with the coarse tuning circuit  35  depend contrariwise on the amount of bits, which are used by the frequency detector  36  for representing a detected frequency difference Δf. If the bit count is four, for example, four measurement cycles are needed by the frequency detector  36  for determining the frequency deviation, and 2 4 =16 possible DC shifting levels are available.  
         [0067]      FIG. 5  presents a second embodiment of a PLL  25 ,  29  that may be implemented in the frequency synthesizers  24 ,  28  of the cellular phone  21  of  FIG. 2 .  
         [0068]     The PLL  25 ,  29  comprises a VCO  50 . The output of the VCO  50  is connected via a programmable frequency divider  51  on the one hand to a first input of a phase detector  52  and on the other hand to a first input of a digital frequency detector  56 . Also the frequency detector  56  can be realized in hardware and/or in software.  
         [0069]     Moreover, a reference clock signal REF CLOCK is applied on the one hand to a second input of the phase detector  52  and one the other hand to a second input of the frequency detector  56 .  
         [0070]     The output of the phase detector  52  is connected via a charge pump  53  and a loop filter to a control input of the VCO  50 .  
         [0071]     The output of the frequency detector  56  is connected via a D/A converter unit  57  to an amplifier  58 .  
         [0072]     In this embodiment, the loop filter is a passive loop filter. It comprises a first capacitor C 51  and a series connection of a resistor R 51  and a second capacitor C 52 , which are arranged in parallel between the output of the charge pump  53  and the output of the amplifier  58 . The amplifier  58  functions as a DC shifter.  
         [0073]     The arrangement of VCO  50 , frequency divider  51 , phase detector  52 , charge pump  53  and loop filter C 51 , C 52 , R 51  correspond to the arrangement of an exemplary conventional PLL using a passive loop filter. In a conventional PLL, the loop filter would be connected between the output of the charge pump  53  and ground, though. The frequency detector  56 , the D/A converter unit  57  and the DC shifter  58  form an exemplary, digitally controlled coarse tuning circuit  55 , which is added according to the invention to a conventional PLL.  
         [0074]     The components corresponding to a conventional PLL operate in a conventional manner for achieving a fine tuning. The coarse tuning circuit  55  operates basically in the same manner as the coarse tuning circuit  35  described with reference to  FIGS. 3 and 4 . Only in this case, the output of the DC shifter  58  is used for changing a bias voltage of the loop filter.  
         [0075]     While there have been shown and described and pointed out fundamental novel features of the invention as applied to preferred embodiments thereof, it will be understood that various omissions and substitutions and changes in the form and details of the devices and methods described may be made by those skilled in the art without departing from the spirit of the invention. For example, it is expressly intended that all combinations of those elements and/or method steps which perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Moreover, it should be recognized that structures and/or elements and/or method steps shown and/or described in connection with any disclosed form or embodiment of the invention may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.

Technology Category: h