Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a frequency compensation configuration for integrated circuit (IC) controllers using closed loop feedback. In particular, this invention relates to a circuit for summing the difference between two voltages with another variable, such as, for example, a current. 
     2. Background of the Related Art 
     In electronic circuit implementations of IC control systems, it is often required to sum a difference between a variable voltage and a reference voltage with another variable such as a current. It is also required to further process the summed result with an integrator that may, in addition to the pole near zero frequency, also have a real zero at a finite frequency, and to output this result as a voltage to be used in other functions. 
     This function would ordinarily be accomplished with a circuit implementation utilizing an operational amplifier as shown in  FIG. 1 . Referring to  FIG. 1 , the circuit includes an amplifier  20  having a gain of A, a voltage source  1 , a current source  2  and a reference voltage  4 . The voltage source  1  is coupled to a negative input of the amplifier  20  through a resistance  3  and the current source  2  is also coupled to the negative input of the amplifier  20 . The reference voltage  4  is coupled to a positive input of the amplifier  20 . The output of the amplifier  20  is coupled to the negative input through a feedback connection comprising a resistance  5  and a capacitance  6 . 
     Assuming the input impedance of the amplifier  20  is large enough and initial conditions are ignored, the transfer function in the frequency domain of the circuit shown in  FIG. 1  is: 
                         -     V   OUT         (           V   1     -     V   REF     +       V   OUT     A         R   ⁢           ⁢   s       -     I   2       )       =         S   ⁢           ⁢     R   F     ⁢     C   F       +   1       S   ⁢           ⁢       C   F     ⁡     (     1   +     1   A       )             ,           (   1   )               
where A is the gain of the amplifier  20 . If A&gt;&gt;1, then the term 1/A becomes negligible. It is noted that this expression can be extended with additional voltage variable and/or current variable inputs (in addition to V 1  and I 2 ).
 
     However, there are difficulties when implementing this circuit in an integrated circuit. For example, the required value C F  of the capacitance  6  may be difficult to realize because of the physical size of the capacitance in the integrated circuit. It is also difficult to initialize a desired value of voltage on the capacitance  6  because neither of its terminals is grounded. 
     Therefore, there is a need for a circuit capable of summing the difference between two voltages with another variable such as a current that overcomes aforementioned difficulties associated with prior art circuit designs. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention relates to a frequency compensation circuit internal to an integrated circuit which overcomes the deficiencies of the prior art designs. In an exemplary embodiment, the internal frequency compensation circuit of the present invention comprises a transconductance amplifier having a first input configured to receive a reference voltage, a second input configured to receive an input voltage and an input current, a first output configured to output a first output current, and a second output configured to output a second output current; and a compensation network connected between the second output of the transconductance amplifier and a reference potential, wherein the first output is connected to the second input. 
     The transconductance amplifier of the internal frequency compensator of the present invention is configured to provide an output current proportional to a sum of the input current and a current proportional to a difference between the reference voltage and the input voltage. Further, the compensation network of the present invention comprises a capacitor having one terminal connected to a reference potential such as ground. 
     Among other advantages as noted below, the internal frequency compensation circuit of the present invention provides means to modify the capacitance value C F  in the compensation circuit without changing the transfer function. In addition the internal frequency compensation circuit of the present invention provides easier control of the initial condition voltage of the capacitor. The circuit of the present invention can also easily provide multiple independent current outputs all of which are proportional to the same inputs without additional amplifiers or amplifier input stages. 
     The invention itself, together with further objects and advantages, can be better understood by reference to the following detailed description and the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a prior art internal frequency compensator. 
         FIG. 2  is an exemplary block diagram of a frequency compensation circuit in accordance with the present invention. 
         FIG. 3  is an exemplary circuit diagram of an input circuit implementation of a frequency compensation circuit in accordance with the present invention. 
         FIG. 4  is an exemplary block diagram of alternative implementations of an input circuit block for use in a frequency compensation circuit in accordance with the present invention. 
         FIG. 5  is an exemplary circuit diagram of some alternative implementations of an output circuit block for use in a frequency compensation circuit in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 2  shows an exemplary embodiment of a frequency compensation circuit  100  in accordance with the present invention. Referring to  FIG. 2 , the frequency compensation circuit  100  comprises a transconductance amplifier  30  which is a voltage controlled current source, a voltage source  1 , a current source  2  and a reference voltage  4 . The voltage source  1  is coupled to a negative input  32  of the transconductance amplifier  30  through a resistance  3  and the current source  2  is also coupled to the negative input  32  of the transconductance amplifier  30 . The reference voltage  4  is coupled to a positive input  31  of the transconductance amplifier  30 . The primary output of the transconductance amplifier  30  is coupled to the negative input  32  through a feedback connection. The first output of the transconductance amplifier  30  is coupled to a first compensation network  10  comprising a resistance  7  and a capacitance  8 . A second output of the transconductance amplifier  30  can be coupled to additional compensation impedance  9  or other circuits. 
     The transconductance amplifier  30  in the given embodiment has a differential voltage input comprising a positive input  31  and a negative input  32 , and a first current source output  33  with a gain G m . Further, the transconductance amplifier  30  in the given embodiment has one or more secondary independent current outputs  34 ,  35  with matched but magnitude scaled gains k 1 ×G m , . . . , k n ×G m , where k n (n=1, 2, . . . ) are predetermined scaling factors that may be less than, equal to or more than 1. 
     The primary current output  33  is connected to the negative input  32  to provide a feedback function. Thus, the negative input  32  is driven to the same potential as the positive input by the large value of G m  and the feedback connection. The negative input  32  is also coupled to the voltage source  1  via the resistance  3  and to the current source  2 , while the positive input  31  is coupled to the reference voltage  4 . 
     The first current output  34  is coupled to a first compensation network  10  comprising a resistance  7  and a capacitance  8 . It is noted that one of the terminals of the capacitance  8  is connected to ground or other suitable reference potential. Alternatively, the compensation network comprising capacitance  8  may be indirectly connected to ground or other reference potential via the series resistance  7 . Since the capacitance  8  is connected to ground or the reference potential, it is easy to control an initial voltage of the capacitance  8  (for example, to initialize or reset the circuit). The transconductance amplifier  30  may have additional independent outputs  35  connected to separate impedances  9  having an impedance value of Z n  to provide different transfer functions or to drive other circuits. 
     Assuming the input impedance of the transconductance amplifier  30  is large enough and initial conditions are ignored, the voltage transfer function for the output of this circuit taken at  34  is: 
                       -     V   OUT           (         V   1     -     V   REF     +       V   OUT         k   1     ⁢       G   m     ⁡     (       R   F     +     1     S   ⁢           ⁢     C   F           )               R   S       )     -     I   2         =         S   ⁢           ⁢     R   F     ⁢     C   F       +   1       S   ⁣       C   F       k   1                   (   2   )               
Similarly, assuming k 1 R F G m &gt;&gt;1, the transfer function for the secondary current output  35  is:
 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           
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     It is noted that with the advantages of multiple independent outputs, the capacitor size C F  (or Z n ) can be easily scaled with the factor k 1 (or k n ). In addition, the secondary current outputs which have scaled but proportional outputs related to the same inputs may have different filter functions, for example proportional and integral outputs, different filter types or bandwidths, comparator or window functions and etc. 
     The transconductance amplifier  30  in the given embodiment has an input circuit block  40  and an output circuit block  50 . 
     Examples of the configuration of the input circuit block  40  are shown in  FIGS. 3 and 4 . The input circuit block  40  further comprises a differential voltage input stage  41  and a level shift and/or additional current gain stage  42 . The input circuit block may output a high side signal X H  or a low side signal X L . Examples of the detailed configuration of the input circuit block  40  are shown in  FIGS. 4   a - 4   d . As shown for example in  FIG. 4   a , the differential voltage input stage  41  may comprise two NMOS transistors  43  and  44  and a bias current sink  45   a . A level shift stage  42  may comprise a PMOS current mirror  46 . In  FIG. 4   b , the differential voltage input stage  41  may comprise two PMOS transistors  47  and  48  and a bias current source  45   b . The level shift stage  42  may comprise a NMOS mirror  49 . In  FIGS. 4   c  and  4   d , the MOS transistors are replaced with bipolar transistors. 
     The input circuit comprises the differential voltage input stage with complementary current outputs X H  and X L , where X H  is a sink current and X L  is a source current. |X H |+|X L |=|bias current| or if additional gain is needed, |X H |+|X L |=k×|bias current|, where k is a factor greater than 1. The current mirror is needed to provide the correct polarity currents to drive the output stages. In function, this circuit converts a differential input voltage into complementary currents for driving on output stage. 
     Examples of the configuration of the output circuit block  50  are shown in  FIGS. 5   a  and  5   b . In the given embodiment, CMOS transistors ( FIG. 5   a ) or bipolar transistors ( FIG. 5   b ) may be employed. The output circuit block  50  may comprise n additional stages (n=1, 2, . . . ), each having a complementary pair of transistors (NMOS and PMOS or NPN and PNP). 
     As shown for example in  FIG. 5   a , in each stage, the sources of the PMOS transistors are coupled to Vcc and the sources of the NMOS transistors are coupled to ground. The complementary signals from the input circuit block  40 , X H  and X L  shown in  FIGS. 5   a  and  5   b , are connected to the gate (or base) terminal of the PMOS (PNP) transistors and the NMOS (NPN) transistors, respectively, in each stage. Here, w/l indicate the relative dimensions of the MOS transistors and A indicate the relative emitter areas (sizes) of the bipolar transistors. Subscripts H and L indicate high side and low side. Complementary driving signals from the input stage are connected to the output stage at X. The output from the first stage  51 , which is taken at the drain terminals of the transistors in the first output stage, may constitute the current output used for feedback to the input and the outputs from n th  stages (n=2, 3, . . . ) may constitute the secondary current outputs, where n=1 is for the primary compensator and n=2, 3, . . . are secondary current outputs for other uses. 
     It is noted that only one input circuit block  40  is required even for multiple outputs. The input referred offsets for ratio scaled and matched (proportional to w/l or A) outputs scale by the same factors (k n ). Also, G m  has to be only sufficiently large for equation (3) to be valid without any requirement for a specific value or temperature dependence. In this point, the present invention differs from classic “G m -C” filters, and large G m  is usually as easy to achieve as large A. 
     In classical “G m -C” filters, the response is a function of the actual value of the parameter G m , so G m  must be a value independent of process variation and temperature and changing only with the value of a prescribed additional (control) signal (e.g. for a tuning frequency control). In general, the G m  of a differential voltage input stage to output current depends on process parameters, transistor sizes, die temperature and etc, as well as the bias current. Here, the circuit output is set by R s  and Z n  and not by actual G m &#39;s but only G m  ratios (factor k&#39;s). 
     One of the advantages associated with the present invention is the use of the transconductance amplifier  30 . With the scaling factors k n , the capacitance value C F  in the compensation network  10  can be easily modified. In addition, since the capacitor  8  in the compensation network  10  is connected to ground (or other reference potential), the circuit of the present invention allows easy initialization or reset of the voltage of the capacitor  8 . 
     Another advantage associated with the present invention is that it can also provide multiple outputs all accurately proportional to each other and having the same input referenced voltage offset and variation with bias current. 
     Although certain specific embodiments of the present invention have been disclosed, it is noted that the present invention may be embodied in other forms without departing from the spirit or essential characteristics thereof. Thus, the present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims, and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Technology Category: 5