Patent Document

CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    This non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 98143664 filed in Taiwan, R.O.C. on 2009/12/18, the entire contents of which are hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of Invention 
         [0003]    The present invention relates to a switched-mode power supply, and in particular to a switched-mode power supply without an external inductor. 
         [0004]    2. Related Art 
         [0005]    A switched-mode power supply (SMPS) is a power supply employing the architecture of an inductor and a field effect transistor (FET) switch, which uses magnetic coils (inductor) as an energy storage device. This type of power supply can provide the highest power conversion efficiency (up to 97%), of all direct current conversion methods, and can improve the battery life of a portable product, thus prolonging the product&#39;s working time. 
         [0006]    Since an SMPS uses an inductor as an energy storage element, an inductance value of the energy storage inductor will directly influence efficiency. A higher inductance value can decrease the ripple and hysteresis loss generated by an SMPS, and thus an inductor of 4.7 μF, 10 μF or above is generally used. 
         [0007]    However, larger inductor occupies larger area of a circuit board, resulting in high cost. Accordingly, as in the current trend of integrating circuits, direct fabrication of an inductor into an integrated circuit (IC) would be an excellent choice. However, a very large circuit area will be occupied if an inductor of higher than 10 nF is fully-integrated in an IC, which is not consistent with a reasonable cost and also has a low quality factor. Therefore, whether in a buck converter, a boost converter, a buck boost converter, or a Cuk converter SMPS, the inductor is implemented off-chip. 
         [0008]    In the SMPS, the switch of an MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) in a power stage is generally controlled by pulse width modulation (PWM) or pulse frequency modulation (PFM). The PWM method is changing the duty cycle of an MOSFET to adjust the output, without changing the cycle T of the MOSFET; and the PFM method is maintaining the duty cycle, but changing the cycle T to adjust the output. A dual-mode chip has also become available, which works in a PFM mode during low load, such as in waiting status, so as to reduce the operating frequency and thus decrease the power consumption; and is switched to operate in PWM mode during high load, so as to provide a high load current. 
         [0009]      FIG. 1  is a schematic view of a conventional buck converter power supply  1 , in which an external element  2  includes an inductor L 1  and a capacitor C 1  as energy storage elements, and circuit elements other than the external element  2  are generally disposed in an IC. A frequency compensation circuit  20  obtains a feedback voltage VFB via a voltage-dividing circuit formed of a resistor R 1  and a resistor R 2 , and an error amplifier detects the change of an output voltage Vout according to a difference between the feedback voltage VFB and a reference voltage Vref, so as to generate an error signal, Vc. A comparator  14  compares the error signal Vc output from the frequency compensation circuit  20  with a triangle wave Vsaw, so as to generate a PWM output VDUTY. A driver embodied by a non-overlap clock generator  12  then generates two non-overlap clock signals according to the PWM output VDUTY, so as to control the upper and lower bridge switches P 1  and N 1  in a power stage  18 , and generate an output current to charge and discharge the inductor L 1  and the capacitor C 1 , thus supplying an output voltage Vout to a load RL. 
         [0010]    In a current PWM modulator or PFM modulator, a comparator-based design is generally employed, in which the PWM modulator is generally a circuit including a comparator and a triangle wave; and the PFM modulator is a circuit including an SR latch circuit and a comparator. The inductance value of an external inductor L 1  is correlated with the operating frequency of a power supply, and when the inductor L 1  has a high inductance value, the power supply can operate at a lower frequency; on the contrary, when the inductor L 1  has a low inductance value, the power supply needs to operate at a higher frequency. 
       SUMMARY OF THE INVENTION 
       [0011]    The present invention provides several embodiments of SMPSes without an external inductor. 
         [0012]    According to an embodiment of the present invention, an SMPS is provided, which supplies an output current to charge an external capacitor to generate an output voltage. The SMPS includes a first bonding wire, a second bonding wire, and a power conversion chip. The power conversion chip includes a first pad, connected to an end of the first bonding wire; a second pad, connected to an end of the second bonding wire; a frequency compensation circuit, electrically coupled to the second pad, for acquiring a feedback voltage, and outputting an error signal according to a reference voltage and the feedback voltage; a current-controlled PWM modulator, electrically coupled to the frequency compensation circuit, for generating a high-frequency PWM output signal according to the error signal and a high-frequency clock signal; a current-controlled PFM modulator, electrically coupled to the frequency compensation circuit, for generating a high-frequency PFM output signal according to the error signal; a power stage, switched under control to output the output current from a switch node connected to the first pad; a selector, electrically coupled to the current-controlled PWM modulator and the current-controlled PFM modulator, for enabling the current-controlled PWM modulator or the current-controlled PFM modulator according to a selection signal; and a driver, electrically coupled to the power stage, the current-controlled PWM modulator and the current-controlled PFM modulator, for controlling the power stage switch according to the PWM output signal or the PFM output signal. The first bonding wire is electrically coupled to the other end of the second bonding wire, and connected directly to an end of the external capacitor. 
         [0013]    According to another embodiment of the present invention, an SMPS is provided, which supplies an output current to charge an external capacitor to generate an output voltage. The SMPS includes a first bonding wire, a second bonding wire, and a power conversion chip. The power conversion chip includes a first pad, connected to an end of the first bonding wire; a second pad, connected to an end of the second bonding wire; a frequency compensation circuit, electrically coupled to the second pad, for acquiring a feedback voltage, and outputting an error signal according to a reference voltage and the feedback voltage; a current-controlled PWM modulator, electrically coupled to the frequency compensation circuit, for generating a high-frequency PWM output signal according to a high-frequency clock signal and the error signal; a power stage, switched under control to output the output current from a switch node connected to the first pad; and a driver, electrically coupled to the power stage and the current-controlled PWM modulator, for controlling the power stage switch according to the PWM output signal. The first bonding wire is electrically coupled to the other end of the second bonding wire, and connected directly to an end of the external capacitor. 
         [0014]    According to another embodiment of the present invention, an SMPS is provided, which supplies an output current to charge an external capacitor to generate an output voltage. The SMPS includes a first bonding wire, a second bonding wire, and a power conversion chip. The power conversion chip includes a first pad, connected to an end of the first bonding wire; a second pad, connected to an end of the second bonding wire; a frequency compensation circuit, electrically coupled to the second pad, for acquiring a feedback voltage, and outputting an error signal according to a reference voltage and the feedback voltage; a current-controlled PFM modulator, electrically coupled to the frequency compensation circuit, for generating a high-frequency PFM output signal according to the error signal; a power stage, switched under control to output the output current from a switch node connected to the first pad; and a driver, electrically coupled to the power stage and the current-controlled PFM modulator, for controlling the power stage switch according to the PFM output signal. The first bonding wire is electrically coupled to the other end of the second bonding wire, and connected to an end of the external capacitor. 
         [0015]    In another embodiment, the current-controlled PWM modulator includes a voltage-to-current converter and an inverter. The voltage-to-current converter converts and generates a corresponding PWM control current according to the error signal, and the PWM control current pulls down the inverter strongly or weakly, to generate a PWM output signal. 
         [0016]    Preferably, the current-controlled PWM modulator further includes a current mirror and a buffer. The current mirror mirrors the PWM control current, so as to pull down the inverter strongly or weakly, and the buffer buffers and outputs the PWM output signal. 
         [0017]    In another embodiment, the current-controlled PFM modulator includes a voltage-to-current converter, a current mirror, and a current-starved voltage-controlled oscillator (VCO). The voltage-to-current converter converts and generates a corresponding PFM control current according to the error signal, the current mirror mirrors the PFM control current, so as to be provided to the current-starved VCO, and the current-starved VCO outputs PFM output signals with different frequencies according to the magnitude of the PFM control current. Preferably, a buffer is further included to buffer and output the PFM output signal. 
         [0018]    The SMPS proposed in each of the embodiments of the present invention is capable of high-frequency switching, and thus can use a parasitic inductor provided by bonding wires and lead frame as energy storage inductors without an external inductor, thereby reducing the cost. 
         [0019]    The detailed features and advantages of the present invention are described below in great detail through the following embodiments, and the content of the detailed description is sufficient for those skilled in the art to understand the technical content of the present invention and to implement the present invention there accordingly. Based upon the content of the specification, the claims, and the drawings, those skilled in the art can easily understand the relevant objectives and advantages of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The present invention will become more fully understood from the detailed description and accompanying drawings given herein below for illustration only, and thus not limitative of the present invention wherein: 
           [0021]      FIG. 1  is a schematic view of a prior art SMPS; 
           [0022]      FIGS. 2A and 2B  show a bonding wire and an equivalent circuit model thereof; 
           [0023]      FIG. 3  is a schematic view of an SMPS according to an embodiment of the present invention; 
           [0024]      FIG. 4A  is a circuit diagram of a current-controlled PWM modulator according to an embodiment of the present invention; 
           [0025]      FIG. 4B  is an oscillogram of a high-frequency clock signal and an output signal in the embodiment as shown in  FIG. 4A ; 
           [0026]      FIG. 5  is a schematic view of an SMPS according to another embodiment of the present invention; 
           [0027]      FIG. 6  is a circuit diagram of a current-controlled PFM modulator according to another embodiment of the present invention; and 
           [0028]      FIG. 7  is a schematic view of an SMPS according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0029]    In the present invention, bonding wires and lead frames are directly used as external inductors, so as to reduce the cost of an external circuit. However, the conventional SMPS cannot directly use bonding wires as external inductors, as the conventional SMPS is embodied with a comparator-based architecture, and can only operate at a switch frequency between 500 kHz to 10 MHz. Since the inductance value provided by the bonding wires including lead frame is only nH order, a power stage must be switched with a frequency far greater than 10 MHz. The conventional power supply with the comparator-based architecture cannot reach such a high frequency. 
         [0030]    Therefore, the embodiment of the present invention provides a current-controlled PWM modulator and a current-controlled PFM modulator, which are digitally switched to provide a frequency far greater than 10 MHz. 
         [0031]    In the first place, the bonding wire may be defined according to a bonding wire shown in  FIG. 2A  and an equivalent model shown in  FIG. 2B . A bonding wire  200  is bonded between pads  202  and  204 , where an inductance value thereof is expressed by L, a wire diameter is expressed by d, a wire length is expressed by 1, and a height is expressed by h (distance between the bonding wire  200  and a substrate  206 ). A calculation formula of the inductance value L is given as follows: 
         [0000]    
       
         
           
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         [0032]    in which, capacitance C is a function of frequency, and δ is a skin depth of a material. 
         [0000]    
       
         
           
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         [0033]    Generally, an inductance value provided by a bonding wire is about 1 nH to 10 nH. Therefore, the operating frequency of the SMPS according to the embodiment of the present invention is approximately within the range of 100 MHz to 400 MHz. Note that, in this invention, not only bonding wires but also lead frames contribute certainly equivalent inductance. 
         [0034]      FIG. 3  is a schematic view of an SMPS according another embodiment of the present invention, in which a current-controlled PWM modulator is employed. A capacitor C 1  and a load RL are connected in parallel, with no external inductor disposed in an output path of a power conversion chip  100 A; and an output current Iout directly charges and discharges the capacitor C 1  via a pad  22  and a bonding wire  32 , so as to generate an output voltage Vout. A bonding wire  36  is connected directly to the output voltage Vout, so as to provide the output voltage Vout to a pad  26 ; and resistors R 1  and R 2  divide the output voltage Vout, so as to provide a feedback voltage VFB for PWM control. In this embodiment, the pads  22  and  26  are both connected directly to the capacitor C 1  via bonding wires  32  and  36 , and the parasitic inductors of the bonding wires  32  and  36  are used as energy storage inductors. A frequency compensation circuit  20  compares the feedback voltage VFB with a reference voltage Vref to output error signal Vc, a current-controlled PWM modulator  42  then outputs a high-frequency PWM output signal to a non-overlap clock generator  12  according to the error signal Vc and a high-frequency clock signal provided by a high frequency generator  30 . Next, the non-overlap clock generator  12  generates two non-overlap control signals to a power stage  18  according to the PWM output signal, so as to switch an upper and lower bridge switches P 1  and N 1  in the power stage  18 . The power stage  18  is switched under control to generate the output current Iout, which charges and discharges the capacitor C 1  through a switch node  19 , the pad  22 , and the bonding wire  32 , so as to generate the output voltage Vout. As described previously, an inductance value provided by the bonding wire  32  and the bonding wire  36  is from 1 nH and to 10 nH, and thus the frequency of the PWM output signal output from the current-controlled PWM modulator  42  is between 100 MHz and 400 MHz. In a practical circuit, the bonding wires  32  and  36  may bond the pad and a lead frame (not shown) together, and then connected to the capacitor C 1  via a pin of the lead frame. Therefore, in other embodiments, parasitic inductance and capacitance caused by the lead frame may also be taken into consideration. 
         [0035]      FIG. 4A  is a circuit diagram of a current-controlled PWM modulator according to another embodiment of the present invention. An inverter  423  is formed by serially connected transistors P 2  and N 2 , and switches under the control of a clock signal CK to generate a signal Vp at an output end thereof; in which the clock signal CK is a high-frequency clock signal provided by a high frequency generator  30 , as shown in  FIG. 3 . A voltage-to-current converter  421  converts and generates a PWM control current I 1  according to an error signal Vc, a first current mirror  422  mirrors the PWM control current I 1  to generate a converted current I 2 , and then a second current mirror  424  mirrors the converted current I 2  to generate a current I 3  to the inverter  423 . When an output voltage Vout is higher than Vref, the error signal Vc increases, the PWM control current I 1  generated by the voltage-to-current converter  421  increase, and thus the current I 3  also increases to pull down the output of the inverter  423  strongly. In this case, the signal Vp decreases rapidly and its pulse width is decreased; here a corresponding waveform output from the inverter  423  is a waveform Vp 1  as shown in  FIG. 4B . When the output voltage Vout is lower than Vref, the PWM control current I 1  decreases, and the current I 3  is also decreased to pull down the output of the inverter weakly. So the signal Vp decreases slowly and its pulse width is increased; here a corresponding waveform output from the inverter  423  is a waveform Vp 2  as shown in  FIG. 4B . A buffer  425  is connected to the inverter  423  for buffering, and outputs the PWM output signal (PWM_CTRL). 
         [0036]      FIG. 5  is a schematic view of an SMPS according to another embodiment of the present invention. Similar to the embodiment shown in  FIG. 3 , a power conversion chip  100 B is connected directly to an external capacitor C 1  via bonding wires  32  and  36 , and uses parasitic inductors of bonding wires  32  and  36  as energy storage inductors; thus, a current-controlled PFM modulator  44  thereof also needs to output a high-frequency PFM control signal. In this embodiment, the current-controlled PFM modulator  44  does not need an additionally provided high-frequency clock signal, so that the high frequency generator does not need to be installed. The current-controlled PFM modulator  44  is electrically coupled between a frequency compensation circuit  20  and a driver embodied by a non-overlap clock generator  12 , and generates a high-frequency PFM output signal according to an error signal Vc. Accordingly, the non-overlap clock generator  12  controls the switch of a power stage  18  to generate an output current Iout. The output current Iout is output from a switch node  19  to charge and discharge the external capacitor C 1 , thereby generating an output voltage Vout. 
         [0037]      FIG. 6  is a circuit diagram of a current-controlled PFM modulator  44  according to another embodiment of the present invention. A voltage-to-current converter  441  generates a corresponding PFM control current I 4  according to an error signal Vc; a current mirror  444  is connected between the voltage-to-current converter  441  and a current-starved VCO  442 , mirrors the PFM control current I 4  and generates a current I 5 . The current-starved VCO  442  includes a ring oscillator with odd stages, and outputs an output signal with a fixed duty cycle and a changeable cycle according to the magnitude of the current I 5 . The buffer  443  is connected to an output end of the current-starved VCO  442 , for buffering and outputting a PFM control signal PFM_CTRL. 
         [0038]    In order to have high efficiency at heavy load (the load current is larger or around 1 A) or a light load (load current &lt;100 mA), the present invention also provides an SMPS with PWM/PFM dual mode. 
         [0039]      FIG. 7  is a schematic view of another embodiment of an SMPS according to the present invention, which has both a current-controlled PWM modulator  42  and a current-controlled PFM modulator. A selector  46  is electrically coupled to the current-controlled PWM modulator  42  and the current-controlled PFM modulator  44 , and enables the current-controlled PWM modulator  42  or the current-controlled PFM modulator  44  according to a selection signal Se 1 . A multiplexer  48  is electrically coupled to the current-controlled PWM modulator  42  and the current-controlled PFM modulator  44 , and also switches according to the selection signal Se 1  to provide a PWM output signal or a PFM output signal to a non-overlap clock generator  12 . The selection signal Se 1  is provided externally, and can be determined by detecting the change at an output end; for example, it is determined to work in a PFM or PWM mode when an output current Tout or an output voltage Vout is risen to or dropped to a threshold value. 
         [0040]    Please refer to  FIG. 2B  for an equivalent circuit model of a bonding wire. In fact the bonding wire also has the property of a resistor, and thus it is preferred that the properties of resistors, inductors and capacitors in the whole path through the pad  22 , the bonding wire  32 , the output end, the bonding wire  36  to the pad  26  are all taken into consideration when determining the operating frequency of the SMPS. 
         [0041]    As described previously, the bonding wire  36  and the bonding wire  32  may be bound between a pad and a lead frame. In an embodiment, the bonding wire  36  and the bonding wire  32  are connected to the capacitor C 1  via a common pin on the lead frame after being connected to the same lead frame. In another embodiment, the bonding wire  36  and the bonding wire  32  are respectively connected to a first pin and a second pin, and then the first pin and the second pin are electrically connected to the capacitor C 1  via an external PCB (Printed Circuit Board). 
         [0042]    Although in the above embodiments, only one single bonding wire is used to embody each of the bonding wires  32  and  36  respectively, multiple bonding wires may also be employed to embody the bonding wire  32 / 36  so that the electrical properties provided by the bonding wires may be precisely controlled. In general description, the independent bonding wires  32  and  36  separate from each other may be defined as a first bonding wire and a second bonding wire according to the aforesaid embodiments of the present invention. 
         [0043]    While the present invention has been described by the way of example and in terms of the preferred embodiments, it is to be understood that the invention need not to be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures.

Technology Category: h