Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. P2004-116418, filed on Dec. 30, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a CMOS image sensor and a method for fabricating the same. 
         [0004]    2. Discussion of the Related Art 
         [0005]      FIG. 1  illustrates a cross sectional view of a CMOS image sensor according to the related art.  FIG. 2  illustrates a cross sectional view of an active region in a CMOS image sensor according to the related art. 
         [0006]    As shown in  FIG. 1  and  FIG. 2 , a p-type well  2  is formed in a p-type substrate  1 . Also, shallow trench isolation STI regions  3  are formed in a surface of the p-type well  2  for electric isolation of pixels. 
         [0007]    Then, an N-type photodiode  5  is formed inside the P-type well  2  in each of cell regions  4 . Also, impurity regions  6  are formed in the surface of the P-type well  2  adjacent to the N-type photodiode  5 , wherein the impurity regions  6  serve as source and drain regions. 
         [0008]    Subsequently, a poly-silicon gate electrode  7  is formed on the surface of the P-type well  2  in correspondence with the impurity regions  6 . In the drawings, a voltage source Vc applies a voltage to the impurity regions  6 , and a gate insulating layer  8  is provided. 
         [0009]    As designs become smaller when forming the poly-silicon gate electrode for a CMOS transistor according to the related art, shallow trench isolation (STI) is often used to isolate the pixels from one another. 
         [0010]    STI, trenches are formed in the surface of the P-type well  2 , and then oxide layers are grown or deposited into the trenches. After that, an etch-back process is performed to the oxide layers, whereby isolation layers are formed in the trenches for isolation of the pixels. 
         [0011]    However, when etching the surface of the flat silicon substrate  1 , crumpled portions may be generated. In this case, mechanical and electrical stresses may be generated in a tilted or crumpled surface between the oxide layer inside the trench and the silicon substrate  1 , thereby causing an increase in defect density. Accordingly, a leakage current occurs in the CMOS image sensor, and a dark defect occurs in images. 
       SUMMARY OF THE INVENTION 
       [0012]    Accordingly, the present invention is directed to a CMOS image sensor and a method for manufacturing the same that substantially obviates one or more problems due to limitations and disadvantages of the related art. 
         [0013]    The present invention provides a CMOS image sensor having an improved signal efficiency in low light circumstances by reducing a dark signal. 
         [0014]    Additional advantages and features of the invention will be set forth in the description which follows and will become apparent to those having ordinary skill in the art upon examination of the following. These and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
         [0015]    To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, there is provided a CMOS image sensor including a substrate having a first conductive type comprising an image area and a circuit area, a STI isolation layer in the substrate for electrical isolation within the circuit area, and a field oxide in the substrate for electrical isolation within the image area. 
         [0016]    A gate electrode comprising a gate oxide and a polysilicon gate can be formed on the circuit area of the substrate. Both side portions of the gate oxide can be formed on the field oxide. 
         [0017]    In another aspect of the present invention, there is provided a method for manufacturing a CMOS image sensor including the steps of forming a STI isolation layer in a substrate of a first conductive type, wherein the substrate comprises an image area and a circuit area and the STI isolation layer is for electrical isolation within the circuit area. The method can further include forming a field oxide in the substrate for electrical isolation within the image area. 
         [0018]    The field oxide formation can comprise the steps of forming a pad oxide on the substrate, forming a nitride on the pad oxide, selectively etching the nitride and pad oxide sequentially so that a portion of the substrate where the field oxide is to be formed is exposed, and forming a thermal oxide on the exposed portion of the substrate by performing thermal oxidation process on the entire substrate. 
         [0019]    The method can further comprise a step of forming a gate electrode on the circuit area of the substrate. The gate electrode formation can comprise the steps of forming a CVD oxide layer on the entire surface of the substrate, including the thermal oxide by performing CVD process; forming a polysilicon layer on the CVD oxide layer; and selectively etching the polysilicon layer and CVD oxide layer sequentially in such a way that at least a portion of remained CVD oxide layer overlaps with the thermal oxide. 
         [0020]    It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    The accompanying drawings, which are included to provide a further understanding of the invention illustrate exemplary embodiments of the invention and together with the description serve to explain the principle of the invention. In the drawings: 
           [0022]      FIG. 1  is a cross sectional view of a CMOS image sensor according to the related art; 
           [0023]      FIG. 2  is a cross sectional view illustrating an active region in a CMOS image sensor according to the related art; 
           [0024]      FIG. 3  is a cross sectional view of a CMOS image sensor according to an exemplary embodiment of the present invention; and 
           [0025]      FIG. 4A to 4F  are cross sectional views of a CMOS image sensor fabricated using a method according to an exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
         [0027]      FIG. 3  illustrates a cross sectional view of a CMOS image sensor according to the present invention. 
         [0028]    As shown in  FIG. 3 , a P-type well (not shown) is formed in a P-type substrate  10 . Also, channel stop regions CS  12  are formed in a surface of the P-type well  11 , wherein the channel stop regions CS function as isolation regions for electrically isolating pixels from one another. The channel stop regions CS  12  are formed by forming field oxide layers (not shown) in field regions of the substrate  10  through a LOCOS (Local Oxidation of Silicon) process and then implanting channel stop ions to the portions of the substrate  10  below the field oxide layers. A N-type photodiode  19  and a source/drain region  20  are respectively formed in the P-type well of each of the pixel areas. A polysilicon gate  16   a  is formed on the source/drain region  20 . A voltage source Vd for applying a voltage to the source/drain region  20  and a gate oxide  15   a  are provided. 
         [0029]      FIG. 4A to 4F  are cross sectional views illustrating processes for making an active region in a CMOS image sensor according to the present invention. 
         [0030]    As shown is  FIG. 4A , a P-type well is formed in a P-type substrate  10  by implanting P-type ions thereto. A pad oxide layer  11  and nitride layer  12  are sequentially formed on the P-type well. A photoresist pattern  13  is then formed on the nitride layer  12  to expose a portion of the nitride layer  12  corresponding to field regions. 
         [0031]    Referring to  FIG. 4B , a pad oxide pattern  11   a  and a nitride pattern  12   a  are formed by selectively etching the pad oxide layer  11  and nitride layer  12  using the photoresist pattern  13  as a mask and then stripping the photoresist pattern  13 . 
         [0032]    Referring to  FIG. 4C , a field oxide  14  is formed on the exposed portion of the substrate  10  by performing a thermal oxidation process. Subsequently, the nitride pattern  12   a  and pad oxide pattern  11   a  are removed. 
         [0033]    Referring to  FIG. 4D , a CVD process is performed on the entire surface of the substrate  10 , including the field oxide  14 , to form a gate oxide layer  15  thereon. Then, a polysilicon layer  16  is deposited on the gate oxide layer  15 . 
         [0034]    As shown in  FIG. 4E , after a photoresist pattern  17  is formed on the polysilicon layer  16  in such a way that a portion of the polysilicon layer  16  corresponding to the field oxide  14  is exposed, channel stop ions of high density are implanted using the photoresist pattern  17  as a mask. The channel stop ions are the same conductive type as the substrate  10 , that is, P-type. Consequently, the implanted channel stop ions constitute a P-type ion area  18  below the field oxide  14 , which constitute a channel stop region together with the field oxide  14 . 
         [0035]    Referring to  FIG. 4F , the polysilicon layer  16  and gate oxide layer  15  are selectively etched using the photoresist pattern  17  as a mask. As a result, a gate oxide  15   a  and a polysilicon gate  16   a  are formed on the circuit area of the substrate  10 . According to an exemplary embodiment of the present invention, the gate oxide  15   a  is formed in such a way that both sides of the gate oxide  15   a  overlap with the field oxide  14 . 
         [0036]    Subsequently, N-type photodiode  19  (see  FIG. 3 ) and source/drain region  20  (see  FIG. 3 ) are sequentially formed using a conventional process. 
         [0037]    In forming the isolation regions for the CMOS image sensor according to the present invention, the oxide layers are formed in the pixels by gate oxide and CVD oxide deposition instead of a shallow trench isolation STI process according to the related art. 
         [0038]    Accordingly, a silicon substrate etching process required for performing a STI process can be avoided, at least in the inner area of the substrate corresponding to each pixel. Thus, it is possible to minimize a stress between the oxide layer and the silicon substrate. 
         [0039]    Using the gate oxide and CVD oxide, a threshold voltage is increased in the field region contrary to an active region for forming a transistor to result in no effect on the operation of a circuit. That is, while the related art STI process is still used in the circuit area, the STI process is replaced with LOCOS process in the imaging area. 
         [0040]    In the CMOS image sensor according to the present invention, it is possible to decrease a parasitic capacitance between the poly-silicon gate electrode and the substrate, thereby decreasing noise caused by coupling. 
         [0041]    Also, it is possible to minimize the surface deformation of the silicon substrate when performing the process for isolation of the pixels, thereby decreasing a dark signal and a dark defect. 
         [0042]    It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Technology Category: 5