Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation of co-pending U.S. patent application Ser. No. 10/913,941, filed Aug. 6, 2004, which claims benefit of U.S. patent application Ser. No. 10/256,563, filed Sep. 27, 2002, and issued as U.S. Pat. No. 6,858,547, which claims benefit of U.S. Provisional Patent Application Ser. No. 60/388,928, filed Jun. 14, 2002. Each of the aforementioned related patent applications is herein incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates generally to forming gate dielectric in field effect transistors, and particularly to forming metal oxide/metal silicate gate dielectric films using chemical vapor deposition.  
         [0004]     2. Description of the Related Art  
         [0005]     The present invention is especially useful in forming complementary metal oxide semiconductor (CMOS) integrated-circuit devices and will be described in that context. Other applications will also be mentioned. CMOS technology has enabled the microelectronic industry to simultaneously meet several technological requirements to fuel market expansion. This has been accomplished largely by a calculated reduction (scaling) of the dimensions of the field-effect transistor (FET).  FIG. 1  illustrates portions of a cross sectional view of a field effect transistor (FET) pair in a typical complimentary metal oxide semiconductor (CMOS) device. Device  100  comprises a silicon wafer  155  doped with a p-type material, a p-type epitaxial silicon layer  165  on wafer  155 , a p-type well region  120  and an n-type well region  150  defined in epitaxial layer  165 , an n-type transistor (NMOS FET)  110  defined in p-well  120  and a p-type transistor (PMOS FET)  140  defined in n-well  150 . Region  180  electrically isolates NMOS  110  and PMOS  140  transistors and region  160  electrically isolates the pair of transistors  110  and  140  from other semiconductor devices on substrate  155 .  
         [0006]     NMOS transistor  110  comprises a gate region  122 , a source region  114  and a drain region  116 . The source and drain regions are n-type regions on opposite sides of gate region  122 . Channel region  118  is interposed between source region  114  and drain region  116 . A gate dielectric layer  112  separates channel region  118  and gate region  122 . Gate dielectric  112  electrically insulates gate region  122  from channel region  118 . The gate region comprises a conductor material, typically doped polycrystalline silicon (polysilicon) or amorphous silicon. The dopant may be an n-type dopant such as a phosphorus or a p-type dopant such as boron. When an appropriate voltage is applied between p-type silicon wafer  155  and gate region  122 , electrons from p-well  120  move into region  118  directly below dielectric  112  thereby creating an n-type channel  118 . A voltage applied between source  114  and drain  116  causes current to flow between source  114  and drain  116 .  
         [0007]     PMOS transistor  140  comprises a gate region  152 , a source region  144  and a drain region  146 . The source and drain regions are p-type regions on opposite sides of gate region  152 . Channel region  148  is interposed between source region  144  and drain region  146 . A gate dielectric  142  separates channel region  148  and gate region  152 . Dielectric  142  electrically insulates gate region  152  from channel region  148 . The gate region comprises a conductor material typically doped polysilicon or amorphous silicon. Again, the dopant may be an n-type or p-type material. When an appropriate voltage is applied between p-type silicon wafer  155  and gate region  152 , holes from n-well  150  move into region  148  directly below dielectric layer  142  thereby creating a p-type channel  148 . A voltage applied between source  144  and drain  146  causes current to flow between source  144  and drain  146 .  
         [0008]     With the rapid shrinking of the transistor feature size, the gate dielectric thickness has also decreased. For several decades, silicon dioxide has been the material of choice for the gate dielectric layer. Silicon dioxide offers a stable high-quality Si—SiO 2  interface and superior electrical isolation properties.  
         [0009]     However, as the dimensions of the transistor continue to decrease, the continued use of silicon dioxide as a dielectric gate material is problematic. The fundamental problem is the need to keep the capacitance of the gate high while the area of the gate is shrinking faster than the thickness of the gate dielectric. The capacitance C of the gate is given by C=kE 0 A/d, wherein A is the area of the gate, d is the thickness of the dielectric layer, k is the dielectric constant, and E 0  is the permittivity of free space. In order to ensure higher gate oxide capacitance, the silicon dioxide layer thickness proportionately has been decreased to less than 2 nanometers as the area of the gate has been decreasing. However, future generations will likely require a further reduction to below 1.0 nanometer. The primary issue is that as thickness decreases, leakage current increases. This leakage in current is due primarily to the ability of the electrons to go through the thinner SiO 2  dielectric layer. In an example, current density for a 1.5 nanometer thick SiO 2  layer at 1 V is 1 A/cm 2 ; however, as the SiO 2  thickness decreases to 1 nanometer, the leakage-current density approaches 100 A/cm 2  at the same operating voltage.  
         [0010]     Consequently, there is a need for an alternative gate dielectric material that can be used in a large enough physical thickness to reduce current leakage density and still provide a high gate capacitance. In order to achieve this, the alternative gate dielectric material must have a dielectric constant that is higher than that of silicon dioxide. Typically, the thickness of such an alternative dielectric material layer is expressed in terms of the equivalent oxide thickness (EOT). Thus, the equivalent oxide thickness (EOT) of an alternative dielectric layer in a particular capacitor is the thickness that the alternative dielectric layer would have if its dielectric constant were that of silicon dioxide.  
         [0011]     Another consideration in selecting an alternative dielectric material is the mobility of charge carries in the transistor channel. The material selected for the dielectric film affects the mobility of the carriers in the transistor channel, thereby affecting overall transistor performance. It is desirable to find an alternative dielectric material for which the mobility of carriers in the transistor channel is equivalent to or higher than that for silicon dioxide gate dielectric films. For future generation transistors, a peak mobility of 400 cm 2 /Vs or greater is desirable.  
       SUMMARY OF THE INVENTION  
       [0012]     The present invention comprises forming a metal oxide, metal silicate, or combination metal oxide-metal silicate dielectric stack on a semiconductor wafer.  
         [0013]     In one embodiment, the method comprises pre-treating the semiconductor wafer, e.g., to remove oxide, with hydrofluoric acid to form an HF-last surface and then pre-treating the HF-last surface with ozonated water for a specified time period. After pre-treating, a dielectric stack is formed on the pre-treated surface using a chemical vapor deposition process. A flow of NH 3  is then provided in a process zone surrounding the semiconductor wafer. In one embodiment, after providing the NH 3  flow, a polycrystalline or amorphous silicon gate is formed over the dielectric stack using a LPCVD process.  
         [0014]     In another embodiment, the method of forming a dielectric stack on a semiconductor wafer comprises pre-treating the semiconductor wafer with hydrofluoric acid to form an HF-last surface, pre-treating the HF-last surface with NH 3 , forming the dielectric stack on the pre-treated surface, and providing a flow of N 2  in a process zone surrounding the semiconductor wafer after forming the dielectric stack.  
         [0015]     In yet another embodiment, the method of forming a dielectric stack on a semiconductor wafer comprises pre-treating the semiconductor wafer with hydrofluoric acid to form an HF-last surface, pre-treating the HF-last surface using an in-situ steam generation process, forming the dielectric stack on the pre-treated surface, and annealing the semiconductor wafer after forming the dielectric stack. The in-situ steam generation process comprises providing an inert gas flow in a process zone surrounding the HF-last surface, reacting hydrogen with an oxidizer in the process zone surrounding the HF-last surface for a very short duration, and providing an inert gas flow in the process zone after the reacting step. Preferably, the dielectric stack comprises layers of hafnium oxide, hafnium silicate layers, or a combination thereof formed using a MOCVD process.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     So that the manner in which the above recited features of the present invention, and other features contemplated and claimed herein, are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.  
         [0017]     Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:  
         [0018]      FIG. 1  illustrates portions of a cross sectional view of field effect transistor (FET) pair in a typical complimentary metal oxide semiconductor (CMOS) device.  
         [0019]      FIG. 2  illustrates a cross-sectional view of a portion of a transistor having a dielectric stack.  
         [0020]      FIG. 3  illustrates the processing steps used to form a hafnium oxide and hafnium silicate gate dielectric stack.  
         [0021]      FIG. 4  illustrates the general chemical structure for the hafnium oxide precursors of the form Hf(NRR′) 4 .  
         [0022]      FIG. 5  illustrates the chemical structure of the TDEAH precursor.  
         [0023]      FIG. 6  illustrates the general chemical structure for precursors of the form SiR 1 R 2 R 3 R 4 .  
         [0024]      FIG. 7  illustrates the chemical structure of the TDMAS precursor.  
         [0025]      FIG. 8  illustrates the processing steps used to form a hafnium oxide and hafnium silicate gate dielectric stack.  
         [0026]      FIG. 9  illustrates the processing steps that may be used for forming the dielectric stack using a flash in-situ steam generation (ISSG) pre-treatment process. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0027]      FIG. 2  illustrates a cross-sectional view of a portion of a field effect (FET)  200  transistor having a dielectric stack in accordance with an embodiment of the invention. FET  200  comprises a source  250 , a drain  240 , a gate  210 , a dielectric stack  260  and a channel  270  interposed between source  250  and drain  240 . Preferably, the transistor is formed on a silicon wafer and the gate is made of polycrystalline or amorphous silicon. In a PMOS FET, source  250  and drain  240  comprise a p-type silicon and in an NMOS FET, source  250  and drain  240  comprise an n-type silicon.  
         [0028]     In one embodiment, dielectric stack  260  comprises at least two layers, where each layer comprises either a metal oxide layer or a metal silicate layer. In the embodiment shown, there is a metal oxide layer  230  and a metal silicate layer  220 . The stack is formed using any metal that is capable of forming a high-k layer, e.g., HfO 2 , ZrO 2 . A high-k layer comprises a dielectric material having a dielectric constant greater than 4. Preferably, metal oxide layer  230  and metal silicate layer  220  comprise any metal that can form amino precursors. More preferably, metal oxide layer  230  comprises hafnium oxide and the metal silicate layer  220  comprises hafnium silicate. In one embodiment, the hafnium oxide layer thickness is about 3 nanometers and the hafnium silicate layer thickness is about 1 nanometer. Such a dielectric stack has an EOT of about 1.12 nanometers. In another embodiment, the hafnium oxide layer thickness is about 4 nanometers and hafnium silicate layer thickness is about 1.5 nanometers. Such a dielectric stack has an EOT of about 1.61 nanometers. An EOT of 1.61 nanometers provides the desired peak mobility of 400 cm 2 /Vs. In yet another embodiment, the dielectric stack thickness is selected to provide both the desired capacitance corresponding to 1.12 nanometers EOT and the desired peak mobility of 400 cm 2 /Vs.  
       Example 1  
       [0029]      FIG. 3  illustrates the processing steps used in accordance with the invention to form a hafnium oxide, hafnium silicate, or combination thereof gate dielectric stack having an EOT of about 1.12 nanometers. At step  310 , an HF-last surface is formed on a semiconductor wafer by introducing a dilute hydrofluoric acid solution onto the wafer surface for a specified time period. In one embodiment, the wafer is immersed in a hydrofluoric acid bath for a time period of about 2 minutes to about 15 minutes. More preferably, the wafer is immersed in a 2% hydrofluoric acid bath for about 2 minutes.  
         [0030]     Next, the wafer is placed in a thermal chamber for pre-treating at 1 to 100 Torr. A step  320 , NH 3  is introduced onto the HF-last surface for a specified time period and at a specified temperature. Step  320  adds a nitride “coating” or “layer” that aids in preventing the dopant of the gate layer ( 210  in  FIG. 2 ) from diffusing into the channel ( 270  in  FIG. 2 ). Preferably, the specified time period is in the range of about 5 seconds to about 120 seconds and the specified temperature is in the range of about 400° C. to about 1,100° C. More preferably, the specified time period is about 30 seconds and the specified temperature is about 600° C. at 30 Torr.  
         [0031]     The wafer is then transported from the thermal chamber to a deposition chamber. A hafnium oxide or hafnium silicate layer is then formed at step  330  using deposition processes such as MOCVD, LPCVD, PECVD, VPE, ALD or PVD. Preferably, the hafnium oxide or hafnium silicate layer is formed using a MOCVD process.  
         [0032]     If a hafnium oxide layer is preferred, O 2 , N 2  and a hafnium oxide precursor are introduced onto the wafer surface. The hafnium oxide precursor is any precursor of the alkylamido or alkylamino ligand group. In one embodiment, the hafnium oxide precursor is selected from a group comprising amino or amido precursors of the form Hf(NRR′) 4  where 
        R=H, CH 3 , C 2 H 5 , C 3 H 7 , alkyl, and aryl and     R′=H, CH 3 , C 2 H 5 , C 3 H 7 , alkyl, and aryl. 
 
  FIG. 4  illustrates the general chemical structure for the hafnium oxide precursors of the form Hf(NRR′) 4 . Preferably, the hafnium oxide precursor is tetrakis(diethylamido)hafnium (TDEAH).  FIG. 5  illustrates the chemical structure of the TDEAH precursor. 
       
 
         [0035]     TDEAH is flowed onto the wafer surface at a rate in the range of about 1 mg/min to about 50 mg/min. Preferably, TDEAH is flowed onto the wafer surface at a rate of about 7 mg/min. O 2  is flowed onto the wafer surface at a rate in the range of about 30 sccm to about 3,000 sccm. Preferably, O 2  is flowed onto the wafer surface at a rate of about 1,000 sccm. N 2  is flowed onto the wafer surface at a rate in the range of about 30 sccm to about 3,000 sccm. Preferably, N 2  is flowed onto the wafer surface at a rate of about 1,500 sccm. O 2 , N 2  and TDEAH are introduced onto the wafer surface either simultaneously or sequentially or a combination thereof.  
         [0036]     The hafnium oxide layer is formed at temperatures in the range of about 225° C. to about 700° C. Preferably, the hafnium oxide layer is formed at about 485° C. The pressure in the deposition chamber is in the range of about 1.5 Torr to about 8 Torr. Preferably, the pressure is about 4 Torr. The hafnium oxide layer formed has a thickness in the range of about 5 Å to about 50 Å. Preferably, the hafnium oxide layer formed has a thickness of about 30 Å.  
         [0037]     In one embodiment, the wafer is transported to a second chamber after forming the hafnium oxide layer in a first chamber. The process conditions of the first chamber are then adjusted for forming the hafnium silicate layer. The wafer is then transported back to the first chamber for forming the second layer. Alternatively, the wafer can remain in the same chamber for sequential deposition of the second layer. The choice of whether to use single- or multiple-chamber deposition depends on a number of factors including the deposition process chosen for each layer (e.g., MOCVD for one layer and ALD for another or MOCVD for both layers), the capabilities or limitations of the system (transfer speed between chambers, temperature ramping capabilities), whether the wafers are being processed in a development or production environment, and/or whether an anneal process is performed between the deposition of the two dielectric layers.  
         [0038]     Alternatively, the hafnium silicate layer may be formed at step  330  using deposition processes such as MOCVD, LPCVD, PECVD, VPE, ALD or PVD. Preferably, the hafnium silicate layer is formed using a MOCVD process, where O 2 , N 2 , and hafnium silicate precursors are introduced onto the wafer surface and the process temperature is about 480° C. to about 600° C. and the pressure is adjusted to about 4 Torr.  
         [0039]     The hafnium silicate precursors are precursors of the alkylamido or alkylamino ligand group. The hafnium silicate precursors are selected from precursors of the form Hf(NRR′) 4  and SiR 1 R 2 R 3 R 4  where  
         [0000]     R=H, CH 3 , C 2 H 5 , C 3 H 7 , alkyl, and aryl;  
         [0000]     R′=H, CH 3 , C 2 H 5 , C 3 H 7 , alkyl, and aryl;  
         [0000]     R 1 =H, NH 2 , N(CH 3 ) 2 , N(C 2 H 5 ) 2 , N(C 3 H 7 ) 2 , NCO, alkoxy, amino, alkyl and aryl;  
         [0000]     R 2 =H, NH 2 , N(CH 3 ) 2 , N(C 2 H 5 ) 2 , N(C 3 H 7 ) 2 , NCO, alkoxy, amino, alkyl and aryl;  
         [0000]     R 3 =H, NH 2 , N(CH 3 ) 2 , N(C 2 H 5 ) 2 , N(C 3 H 7 ) 2 , NCO, alkoxy, amino, alkyl and aryl; and  
         [0000]     R 4 =H, NH 2 , N(CH 3 ) 2 , N(C 2 H 5 ) 2 , N(C 3 H 7 ) 2 , NCO, alkoxy, amino, alkyl and aryl.  
         [0040]     The general chemical structure for the precursors of the form Hf(NRR′) 4  is shown in  FIG. 4 .  FIG. 6  illustrates the general chemical structure for precursors of the form SiR 1 R 2 R 3 R 4 . Preferably, the hafnium silicate precursors are tetrakis(diethylamido)hafnium (TDEAH) and tetrakis(dimethylamido)silicon (TDMAS).  FIG. 7  illustrates the chemical structure of the TDMAS precursor. The chemical structure for the TDEAH precursor is shown in  FIG. 5 .  
         [0041]     TDEAH is flowed onto the wafer surface at a rate in the range of about 1 mg/min to about 50 mg/min. Preferably, TDEAH is flowed onto the wafer surface at a rate of about 6 mg/min. TDMAS is flowed onto the wafer surface at a rate of about 1 mg/min to about 50 mg/min. Preferably, TDMAS is flowed at a rate of 50 mg/min. O 2  is flowed onto the wafer surface at a rate of about 30 sccm to about 1,000 sccm, preferably about 1,000 sccm, and N 2  is flowed onto the wafer surface at a rate of about 30 sccm to about 3,000 sccm, preferably about 1,500 sccm. O 2 , N 2 , TDEAH and TDMAS are introduced onto the wafer surface either simultaneously or sequentially or a combination thereof.  
         [0042]     The hafnium silicate layer is formed at temperatures in the range of about 325° C. to about 700° C. and pressure is in the range of about 1.5 Torr to about 8 Torr. Preferably, the hafnium silicate layer is formed at about 600° C. at a pressure of about 4 Torr. The hafnium silicate layer thickness is about 5-20 Å, preferably 10 Å. The SiO 2  concentration of the hafnium silicate layer is from about 5 mol % to about 80 mol %. More preferably, the SiO 2  concentration is about 10 mol %.  
         [0043]     Thus, either a hafnium oxide or hafnium silicate layer can be formed at steps  330  and  340 . Should, for example, hafnium oxide be used to form both layers, it is preferred that the hafnium oxide layers have differing compositions or stoichiometry, for example, a first layer comprised of HfO 2  and a second layer comprised of Hf 2 O 3 . Similarly, should both layers be comprised of hafnium silicate, it is preferable that the hafnium silicate layers have differing compositions and/or stoichiometry.  
         [0044]     After forming the hafnium silicate layer or hafnium oxide layer at step  340 , the wafer is transported back to the thermal chamber for further processing at 1 to 100 Torr. At step  350 , N 2  is introduced onto the wafer surface for a specified time period and at a specified temperature. Preferably, the specified time period is in the range of about 5 seconds to about 60 seconds at temperatures in the range of about 400° C. to about 1,100° C. More preferably, N 2  is introduced onto the wafer surface for about 60 seconds at a temperature of about 800° C. at 10 Torr.  
         [0045]     In one embodiment, a gate electrode is next formed at step  360  on the hafnium oxide or hafnium silicate layer. The gate electrode layer may be made of polycrystalline or amorphous silicon and is formed using a chemical vapor deposition process such as MOCVD, LPCVD, PECVD, VPE, ALD or PVD. In one embodiment, the gate electrode is formed using an LPCVD process where silane or disilane is flowed onto the wafer at temperatures in the range of about 400° C. to about 900° C. Preferably, the gate electrode is formed at a temperature of about 570° C.  
         [0046]     In some embodiments, a nitride layer may be formed on the hafnium oxide or hafnium silicate layer before formation of the polysilicon gate (i.e., to form a layer between the hafnium silicate layer  220  and the polysilicon gate  210 , see  FIG. 2 ). This embodiment is illustrated at step  850  of  FIG. 8 . Alternatively, for example, a nitride layer may be formed between the channel  270  and the hafnium oxide layer  220 . This embodiment is shown at step  320  of  FIG. 3 . The nitride layer prevents dopant diffusion from the gate electrode into the silicon channel. In such embodiments, the polysilicon gate electrode  210  is implanted with dopants such as boron and phosphorus; and the structure is then annealed at ˜1000° C. for activation and distribution of the dopant in the polysilicon layer. It is undesirable for dopant to diffuse from the gate electrode layer  210  into the silicon channel  270 . In small doses, such diffusion can affect threshold voltages, and in larger doses such diffusion can increase leakage currents. Either case drastically affects transistor performance.  
       Example 2  
       [0047]      FIG. 8  illustrates the processing steps used in accordance with the invention to form a hafnium oxide and hafnium silicate gate dielectric stack having a peak mobility of about 400 cm 2 /Vs. At step  810 , an HF-last surface is formed on a semiconductor wafer by introducing a dilute hydrofluoric acid solution onto the wafer surface for a specified time period. In one embodiment, the wafer is immersed in a hydrofluoric acid bath for a time period of about 1 minute to about 15 minutes. More preferably, the wafer is immersed in a 2% hydrofluoric acid bath for about 2 minutes.  
         [0048]     Next, at step  820 , the HF-last surface is exposed to ozonated water by, for example, immersing the wafer in an ozonated water bath. Preferably, the ozone concentration in the ozonated water is in the range of about 10 ppm to about 30 ppm. Preferably, the ozone concentration in the water is about 20 ppm. Preferably, the HF-last surface is exposed to the ozonated water for about 5 minutes to about 15 minutes. More preferably, the HF-last surface is exposed to the ozonated water for about 10 minutes.  
         [0049]     The wafer is next placed in a deposition chamber. A hafnium oxide layer is then formed at step  830  using deposition processes such as MOCVD, LPCVD, PECVD, VPE, ALD or PVD. Preferably, the hafnium oxide layer is formed using a MOCVD process.  
         [0050]     O 2 , N 2  and a hafnium oxide precursor are introduced onto the wafer surface. The hafnium oxide precursor is any precursor of the alkylamido or alkylamino ligand group. In one embodiment, the hafnium oxide precursor is selected from a group comprising amino or amido precursors of the form Hf(NRR′) 4  where 
        R=H, CH 3 , C 2 H 5 , C 3 H 7 , alkyl, and aryl and     R′=H, CH 3 , C 2 H 5 , C 3 H 7 , alkyl, and aryl. 
 
  FIG. 4  illustrates the general chemical structure for the hafnium oxide precursors of the form Hf(NRR′) 4 . Preferably, the hafnium oxide precursor is tetrakis(diethylamido)hafnium (TDEAH).  FIG. 5  illustrates the chemical structure of the TDEAH precursor. 
       
 
         [0053]     TDEAH is flowed onto the wafer surface at a rate of about 1 mg/min to about 50 mg/min, preferably about 7 mg/min, O 2  is flowed onto the wafer surface from about 30 sccm to about 3,000 sccm, preferably 30 sccm, and N 2  is flowed onto the wafer surface at a rate of about 30 sccm to about 3,000 sccm, preferably about 1500 sccm. O 2 , N 2  and TDEAH are introduced onto the wafer surface either simultaneously or sequentially or a combination thereof.  
         [0054]     The hafnium oxide layer is formed at temperatures in the range of about 225° C. to about 700° C., preferably, at about 485° C. The pressure in the deposition chamber is in the range of about 3 Torr to about 8 Torr, preferably about 4 Torr. Preferably, the hafnium oxide layer formed has a thickness of about 2-5 nanometers, and preferably about 4 nanometers.  
         [0055]     After forming the hafnium oxide layer, the wafer is transported from the deposition chamber another chamber. For example, the chamber may be an anneal chamber, a cool-down chamber or a loadlock chamber. Preferably, an anneal step is performed between deposition of the hafnium oxide layer and the hafnium silicate layer. Once the wafer is transferred, the temperature and pressure in the first deposition chamber are adjusted for forming the hafnium silicate layer. For an MOCVD process, the temperature is adjusted to about 600° C. and the pressure is adjusted to about 4 Torr. The wafer is then transported from the cool-down chamber to the deposition chamber. A hafnium silicate layer is then formed at step  840  using deposition processes such as MOCVD, LPCVD, PECVD, VPE, ALD or PVD. In another embodiment, the wafer is not transported to another chamber after forming the hafnium oxide layer, but the wafer remains in the deposition chamber while the process conditions of the deposition chamber are adjusted for forming the hafnium silicate layer. In this case, ramping the temperature from the processing temperature of the hafnium oxide processing conditions to the temperature of the hafnium silicate processing conditions provides an anneal-like environment and a separate anneal step may be eliminated.  
         [0056]     Preferably, the hafnium silicate layer is formed using a MOCVD process. O 2 , N 2 , and hafnium silicate precursors are introduced onto the wafer surface. The hafnium silicate precursors are precursors of the alkylamido or alkylamino ligand group. The hafnium silicate precursors are selected from precursors of the form Hf(NRR′) 4  and SiR 1 R 2 R 3 R 4  where  
         [0000]     R=H, CH 3 , C 2 H 5 , C 3 H 7 , alkyl, and aryl;  
         [0000]     R′=H, CH 3 , C 2 H 5 , C 3 H 7 , alkyl, and aryl;  
         [0000]     R 1 =H, NH 2 , N(CH 3 ) 2 , N(C 2 H 5 ) 2 , N(C 3 H 7 ) 2 , NCO, alkoxy, amino, alkyl and aryl;  
         [0000]     R 2 =H, NH 2 , N(CH 3 ) 2 , N(C 2 H 5 ) 2 , N(C 3 H 7 ) 2 , NCO, alkoxy, amino, alkyl and aryl;  
         [0000]     R 3 =H, NH 2 , N(CH 3 ) 2 , N(C 2 H 5 ) 2 , N(C 3 H 7 ) 2 , NCO, alkoxy, amino, alkyl and aryl; and  
         [0000]     R 4 =H, NH 2 , N(CH 3 ) 2 , N(C 2 H 5 ) 2 , N(C 3 H 7 ) 2 , NCO, alkoxy, amino, alkyl and aryl.  
         [0057]     The general chemical structure for the precursors of the form Hf(NRR′) 4  is shown in  FIG. 4 .  FIG. 6  illustrates the general chemical structure for precursors of the form SiR 1 R 2 R 3 R 4 . Preferably, the hafnium silicate precursors are tetrakis(diethylamido)hafnium (TDEAH) and tetrakis(dimethylamido)silicon (TDMAS).  FIG. 7  illustrates the chemical structure of the TDMAS precursor. The chemical structure for the TDEAH precursor is shown in  FIG. 5 .  
         [0058]     TDEAH is flowed onto the wafer surface at a rate of about 1 mg/min to about 50 mg/min, preferably about 6 mg/min, TDMAS is flowed onto the wafer surface at a rate of about 1 mg/min to about 50 mg/min, preferably about 10 mg/min, O 2  is flowed onto the wafer surface at a rate of about 30 sccm to about 3,000 sccm, preferably about 1,000 sccm, and N 2  is flowed onto the wafer surface at a rate of about 30 sccm to about 3,000 sccm, preferably about 1,500 sccm. O 2 , N 2 , TDEAH and TDMAS are introduced onto the wafer surface either simultaneously or sequentially or a combination thereof.  
         [0059]     The hafnium silicate layer is formed at temperatures in the range of about 325° C. to about 700° C. and at pressure in the range of about 3 Torr to about 8 Torr. Preferably, the hafnium silicate layer is formed at about 600° C. at a pressure of about 4 Torr. The hafnium silicate layer thickness is from 5 to 20 Å, preferably about 1.5 nanometers. The SiO 2  concentration of the layer is about 5-80 mol %, preferably about 45 mol % to about 50 mol %. More preferably, the SiO 2  concentration is about 50 mol %.  
         [0060]     After forming the hafnium silicate layer, the wafer is transported from the deposition chamber to the thermal chamber for further processing. At step  850  NH 3  is then introduced onto the wafer surface at 1 to 100 Torr for a specified time period and a specified temperature. Preferably, the specified time period is in the range of about 5 seconds to about 60 seconds. More preferably, the specified time period is about 60 seconds. Preferably, the specified temperature is in the range of about 400° C. to about 1,100° C. More preferably, the specified temperature is about 700° C. at 30 Torr.  
         [0061]     In one embodiment, a polycrystalline-Si or amorphous-Si gate electrode is next formed at step  860  on the hafnium silicate layer. The gate electrode layer is formed using a chemical vapor deposition process such as MOCVD, LPCVD, PECVD, VPE, ALD or PVD. In one embodiment, the gate electrode is formed using an LPCVD process where silane or disilane is flowed onto the wafer at temperatures in the range of about 400° C. to about 900° C. Preferably, the gate electrode is formed at a temperature of about 550° C. As described supra, to avoid undesired dopant diffusion from the gate electrode into the silicon channel, the wafer may be treated with NH 3  (step  850  of  FIG. 8 ) after deposition of the dielectric layer  220  and before deposition of the polysilicon gate  210  (layers shown in  FIG. 3 ). Such a treatment forms a nitride coating or layer that prevents dopant diffusion. Alternately, a nitride layer may be formed between the dielectric layer  230  and the silicon channel  270  by treating the wafer with NH 3  ( FIG. 3 , step  330 ) after formation of the HF-last.  
         [0062]     As described previously, as an alternative to forming first a hafnium oxide layer then forming a hafnium silicate layer, two hafnium oxide layers may be used or two hafnium silicate layers may be used, or first a hafnium silicate layer followed by a hafnium oxide layer may be used. Optionally, a third layer may be formed over the second layer as just described. Such a third layer would comprise hafnium silicate.  
         [0000]     Gate Formation Using a Flash In-Situ Steam Generation (ISSG) Process  
         [0063]     In the flash in-situ steam generation (ISSG) process in accordance with the invention, the reactants, hydrogen and an oxidizer, are introduced onto an HF-last wafer surface for a very short duration to form hydroxyl groups and water vapor in the thermal chamber The hydroxyl groups then bond to the HF-last surface, thereby enhancing high-k nucleation. In accordance with the invention, the growth of interfacial SiO 2  between the silicon channel and the hafnium oxide layer is minimized due to a very short flash in-situ steam generation process and by introducing inert gases before and after the flash ISSG process.  
         [0064]      FIG. 9  illustrates the processing steps that may be used in accordance with the invention for forming the dielectric stack using a flash in-situ steam generation (ISSG) pre-treatment process. At step  910 , an HF-last surface is formed on a semiconductor wafer by introducing a dilute hydrofluoric acid solution onto the wafer surface for a specified time period. In one embodiment, the wafer is immersed in a hydrofluoric acid bath for a time period of about 1 minute to about 15 minutes. More preferably, the wafer is immersed in a 2% hydrofluoric acid bath for about 2 minutes.  
         [0065]     After the HF-last processing, the wafer is placed in a thermal chamber. The HF-last surface is then pre-treated using a flash ISSG process. First, at step  920 , an inert gas such as helium or nitrogen is introduced into the chamber for a specified time period. Then, at step  930 , the reactants, hydrogen and an oxidizer such as O 2  or N 2 O, are introduced into the chamber for a very short duration. The flow of reactants is then stopped at step  940  while the inert gas continues to flow onto the wafer surface at step  950 . Table 1 provides some illustrative temperatures, flow rates and reactant flow times for a flash ISSG process.  
                                                                 TABLE 1                                   Temp.       Oxidizer   He   Reactant           (° C.)   H 2  (sccm)   (sccm)   (sccm)   Flow Time(s)                                    Example 1   750   8   2,980 (O 2 )   2,980   6       Example 2   750   15   2,980 (N 2 O)   2,980   6       Example 3   750   15   2,980 (O 2 )   2,980   6       Example 4   800   5   1,000 (O 2 )   0   3       Example 5   800   5   1,000 (N 2 O)   0   3                  
 
         [0066]     After the pre-treating, the wafer is transported to a deposition chamber. A metal oxide and a metal silicate layer are then formed on the pre-treated surface. Preferably, any metal that forms amino precursors, including alkoxides or halides, may be used to form the metal oxide and metal silicate layers. In one embodiment, hafnium oxide and hafnium silicate layers are formed at steps  960  and  970  using the processes described earlier in reference to  FIGS. 3 and 8 . Table 2 provides illustrative parameters for forming the hafnium oxide and hafnium silicate layers.  
                                                                         TABLE 2                                   Hf   Si   O 2     N 2     Temp.   Pressure           (mg/min)   (mg/min)   (sccm)   (sccm)   (° C.)   (Torr)                                    Example 6   7   0   1,000   1,500   485   4       Example 7   6   50   1,750   750   425   3       Example 8   6   50   1,750   750   525   5.5       Example 9   6   50   1,750   750   575   8                  
 
         [0067]     After forming the metal oxide and metal silicate layers, the wafer is transported from the deposition chamber to the thermal chamber for post-deposition processing. In one embodiment, the post-deposition processing comprises the post-treatment processes described earlier in reference to  FIGS. 3 and 8 . In another embodiment, the post-deposition processing comprises annealing the wafer surface at step  980  in a thermal or plasma environment using H 2 , O 2 , N 2 O, NO, NH 3 , O 3 , N 2 , He or a combination thereof.  
         [0068]     In one embodiment, a polycrystalline-Si or amorphous-Si gate electrode is next formed at step  990  after post-deposition processing. The gate electrode layer is formed using a deposition process such as MOCVD, LPCVD, PECVD, VPE, ALD or PVD. In one embodiment, the gate electrode is formed using an LPCVD process where silane or disilane is flowed onto the wafer at temperatures in the range of about 400° C. to about 900° C. Preferably, the gate electrode is formed at a temperature of about 550° C. To avoid undesired dopant diffusion, a nitride layer may be formed between the dielectric layer  220  and the polysilicon gate  210  prior to formation of the polysilicon gate. Alternately, a nitride layer may be formed between the dielectric layer  230  and the silicon channel  260 .  
         [0069]     Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims. For example, although the specific embodiments are described using a hafnium oxide and hafnium silicate dielectric gate stack, those skilled in the art will appreciate that the dielectric stack may be formed using any metal that is capable of forming films with the desired capacitance and mobility. Additionally, although the specific embodiments use metal oxide and metal silicate films, other film compositions that provide the desired capacitance and mobility may also be used to form the dielectric stack.  
         [0070]     While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Technology Category: c