Patent Document

BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a method for correcting symbol timing and the apparatus thereof, especially to a method for correcting the symbol timing of a receiver and the corresponding apparatus. 
   2. Description of the Prior Art 
   In the field of digital communication, the transmitter transmits signals carrying digital data to a receiver with a specific symbol timing T 1 . After receiving the signals, the receiver recovers the digital data by sampling the signals according to a specific symbol timing T 2 . If the symbol timing of the receiver T 2  is the same as the symbol timing of the transmitter T 1 , and no phase delay between the two timings, the receiver will recover the digital data correctly. Oppositely, if the symbol timing T 2  is different from the symbol timing T 1 , or having phase delay between the two timings, the receiver will not recover the digital data correctly. Accordingly, a critical mechanism is required to be set in the receiver for ensuring that the symbol timing T 2  of the transmitter is synchronizing with the symbol timing T 1  or that the timing reference of the receiver has a certain relation to the timing reference of the transmitter by signal processing. 
   Generally speaking, for synchronizing the symbol timing T 2  of the receiver with the symbol timing T 1  of the transmitter, the receiver calculates the sampled data by utilizing a timing recovery algorithm (TR algorithm) to obtain timing metrics, which are related to the difference of the timing references (i.e., the timing error) of the transmitter and the receiver, and are advantageously utilized to correct the symbol timing of the sampling circuit of the receiver. Once the symbol is corrected, the symbol timing T 2  is synchronizing with the symbol timing T 1  or there is a certain relation between these two timings. Please refer to the flowing journals for detailed description: K. H. Mueller and M. Muller, “Timing Recovery in Digital Synchronous Data Receivers,” IEEE Trans. Communications, vol. Com-24, pp. 516-531, May 1976, and F. Gardner, “A BPSK/QPSK Timing-Error Detector for Sampled Receivers, “IEEE Trans. Communications, vol. Com-34, pp. 423-429, May 1986. 
   SUMMARY OF THE INVENTION 
   It is therefore an objective of the claimed invention to provide a method and an apparatus to correct a symbol timing of a receiver. 
   According to an embodiment of the claimed invention, a method for correcting a symbol timing of a receiver is disclosed. The receiver receives a signal transmitted from a transmitter with a symbol period. The method comprises: sampling the signal with a sampling period to generate N sampled data in sequence, wherein the sampling period is the half of the symbol period, and N is a positive integer; selecting M data from a K th  data of the N sampled data to be a first data set according to a timing recovery algorithm (TR algorithm), wherein K and M are positive integers; calculating the first data set to generate a first timing metric according to the TR algorithm; selecting M data from a (K th +1) data of the N sampled data to be a second data set according to the TR algorithm, wherein K+M is less than N; calculating the second data set to generate a second timing metric according to the TR algorithm; and correcting the symbol timing according to the first and the second timing metrics. 
   According to another embodiment of the claimed invention, an apparatus for correcting a symbol timing of a receiver is disclosed. The receiver receives a signal transmitted from a transmitter based on a symbol period. The apparatus comprises a sampling circuit, a timing error detector, and a symbol timing correction circuit. The sampling circuit samples the signal with a sampling period to generate N sampled data in sequence, wherein the sampling period is half of the symbol period, and N is a positive integer. The timing error detector, which is coupled to the sampling circuit, selects M data from a K th  data of the N sampled data to be a first data set according to a timing recovery algorithm (TR algorithm), calculates the first data set to generate a first timing metric according to the TR algorithm, selects M data from a (K th +1) data of the N sampled data to be a second data set according to the TR algorithm, and calculates the second data set to generate a second timing metric according to the TR algorithm. The symbol timing correction circuit, which is coupled to the timing error detector, corrects the symbol timing according to the first and the second timing metrics. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows the graph of the “S-curve”. 
       FIG. 2  shows a functional block diagram of a digital signal receiver according to an embodiment of the present invention. 
       FIG. 3  shows a circuitry of the timing error detector  230  and the timing metric processing circuit  240  according to a first embodiment of the present invention. 
       FIG. 4  shows a circuitry of the timing error detector  230  and the timing metric processing circuit  240  according to a second embodiment of the present invention. 
       FIG. 5  shows a circuitry of the timing error detector  230  and the timing metric processing circuit  240  according to a third embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   Generally, there is a specific relationship between the average of the timing metrics and the timing error. As shown in  FIG. 1 , the specific relationship has a characteristic curve of an “S” shape, so this characteristic curve is often referred to as an “S-curve”. The points P and points N are stable synchronous points. Since the S-curve is like a periodic curve, the sign of the average of the timing metrics is opposite in every T 2 /2, such as the region R 1  and the region R 2  in  FIG. 1 . According to the observation mentioned above, in practical applications more timing metrics can be obtained based on the fact that the S-curve is like a periodic curve. That is, typically a timing metric is obtained every symbol period T 2  (i.e., a T-spaced timing metric); however, actually, a timing metric can be obtained less than a symbol period T 2  by shortening the sampling period, e.g., every T 2 /2 performing a sampling process and calculating the sampled data to generate the timing metric. If a timing metric is obtained every T 2 /2, this timing metric is referred to as a T/2-spaced timing metric. 
   Please refer to  FIG. 2 .  FIG. 2  shows a functional block diagram of a digital signal receiver according to an embodiment of the present invention. In this embodiment, the Mueller and Muller method is taken as an example to illustrate the operational principle of the digital signal receiver  200 . For a detailed description of the Mueller and Muller method please refer to K. H. Mueller and M. Muller, “Timing Recovery in Digital Synchronous Data Receivers,” IEEE Trans. Communications, vol. Com-24, pp. 516-531, May 1976. After being sampled by the sampling circuit  210 , the signal S 1  is turned into a digital data D 1 . The digital data D 1  is afterward transmitted to both the digital signal processing circuit  220  for further process and the timing error detector  230  for generating the timing metric. Assuming that the timing error detector  230  initially gets two data D 1 [(k)T 2 /2] and D 1 [(k+2)T 2 /2] (where k is an integer and T 2  being the symbol period) to generate a timing metric M 1 , then the timing error detector  230  gets the next two data D 1 [(k+1)T 2 /2] and D 1 [(k+3)T 2 /2], which are respectively sampled with a T 2 /2 delay with respect to the former two data, to generate the next timing metric M 2 . According to the S-curve statistically, the signs of the timing metric M 1  and the timing metric M 2  are opposite, and therefore a timing metric processing circuit  240  is required to process the timing metric M 1  and the timing metric M 2  in advance. Afterward, the result M′ generated from the timing metric processing circuit  240  is transmitted to a symbol timing correction circuit  250 , which utilizes the result M′ as a reference information to correct symbol timing. 
   Please refer to  FIG. 3 .  FIG. 3  shows a circuitry of the timing error detector  230  and the timing metric processing circuit  240  according to a first embodiment of the present invention. In this embodiment, a timing error detector  310  includes quantizers  311  and  312 . After timing error detector  310  processes the digital data D 1 , and timing metric M is generated. The timing metric M is transmitted to the timing metric processing circuit  240  and then a result M′ is generated. The result M′ is transmitted to the symbol timing correction circuit  250  for further processing. The timing error detector  310  utilizes the Mueller and Muller method architecture, and use T 2 / 2  delay time for delaying the digital data D 1  to get the correct symbol timing more effectively. On the other hands, based on the characteristic of the S-curve, the timing metric processing circuit  320  is modified to obtain more effective timing metrics compared to the timing metric processing circuit of prior art. The delay time of the delay circuit  322  is modified from T 2  to T 2 / 2  and allocated behind the delay circuit  322  is a multiplier  324 , which receives timing metrics M and multiplies the timing metrics M by 1 and −1 in turn, i.e., the sign in one of two incoming timing metrics will be changed. Originally, only one timing metric M is obtained in one symbol period T 2 ; however, by modifying the timing metric processing circuit  320 , more timing metrics M can be obtained in one symbol period T 2 . Because that one timing metric M is obtained in less than one symbol period T 2 , the symbol timing correction becomes more efficient. 
   Please refer to  FIG. 4 .  FIG. 4  shows a circuitry of the timing error detector  230  and the timing metric processing circuit  240  according to a second embodiment of the present invention. In this embodiment, the timing error detector  310  is the same as the mention above, and the timing metric processing circuit  410  utilizes two delay circuits  412  and  414 , the delay times of which are T 2  and T 2 ′. The periods of the delay times T 2  and T 2 ′ are the same, i.e., the periods of the two delay times can both be set T 2 , but the phase difference between the two delay times is T 2 /2. Allocated behind the delay circuit  414  is a multiplier  416 , which multiplies every timing metric passing through the multiplier  416  by −1. That is, the sign of every timing metric M changes after the timing metric passes through the delay time  414 . The delay times of delay circuits  412  and  414  are both T 2 , and the phase between them is set T 2 /2, i.e., a timing metric is effectively obtained every T 2 /2. Moreover, the sign of one of two successive timing metrics is changed, which corresponds to the characteristic of the S-curve. As a result, more timing metrics can be obtained within a symbol period T 2 , i.e., a timing metric is generated within less than a symbol period T 2 , providing a more effective correction on the symbol timing. 
   Please refer  FIG. 5 .  FIG. 5  shows a circuitry of the timing error detector  230  and the timing metric processing circuit  240  according to a third embodiment of the present invention. In this embodiment, a timing error detector  510  includes quantizers  511  and  512 . The timing error detector  510  also adopts the same Mueller and Muller method to generate timing metrics. The timing error detector  510  changes the sign in one of two successive timing metrics, summing one timing metric and the other sign-changed timing metric to generate a result, and then outputs the result. More specifically, the timing error detector  510  gets the two data D 1 [(k)T 2 / 2 ] and D 1 [(k+2)T 2 / 2 ] to generate a timing metric M 1 , and subsequently gets the two data D 1 [(k+1)T 2 / 2 ] and D 1  [(k+3)T 2 / 2 ] to generate a timing metric M 2 . The timing error detector  510  changes the sign of the timing metric M 2  and then adds the sign-changed M 2  with M 1 , i.e., actually, the timing error detector  510  outputs a data of M 1 -M 2  to the timing metric processing circuit  520 . The timing metric processing circuit  520  adopts a delay circuit  522  of a delay time of T 2 , meaning that the timing metric processing circuit  520  generates a timing metric M′ every timing period T 2 . Each timing metric M′ practically comprises information of two timing metrics (e.g., M 1  and M 2 ). As a result, the symbol timing correction circuit  250  also practically receives one timing metric M′ every symbol period; however, each timing metric M′ comprises more information for correction. Therefore, the symbol timing can be more effectively corrected. 
   According to the embodiments mentioned above, two data processing methods can be summarized referring to the timing error detector  230  and the timing metric processing circuit  240 . By utilizing one of the two methods, all timing metrics can be turned into effective information. 
   1. Changing the sign of odd or even timing metrics (the method adopted by the first and the second embodiments). Since the fact that the S-curve is like a periodic curve implies that the signs of two timing metrics, whose phase difference is half symbol period, are opposite, the signs of all timing metrics are made the same. Therefore, the sign in one of two successive timing metrics is changed. In practical applications, it is optional to change the signs of the odd timing metrics or the even timing metrics. 
   2. Subtracting two successive timing metrics, i.e., subtracting the even timing metrics from the odd timing metrics or subtracting the odd timing metrics from the even timing metrics (the method adopted by the third embodiment). For example, assuming that timing metrics M[1], M[2], M[3], M[4], . . . are generated in sequence, therefore, modified timing metrics such as M[1]-M[2], M[3]-M[4], . . . or M[2]-M[1], M[4]-M[3], . . . are utilized to correct the symbol timing of the receiver. 
   In summary, typically only one timing metric is generated within one symbol period; however based on the method and apparatus disclosed in the present invention, a timing metric is generated within less than one symbol period. In other words, more than one timing metrics (e.g., 2 timing metrics) correspond to one symbol period. Since more timing metrics are therefore obtained, correction of the symbol timing is more effectively achieved. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Category: h