Patent Document

FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to a communications transmitter and specifically to a single communications transmitter that is capable of transmitting data using multiple interface standards. 
       BACKGROUND 
       [0002]    High-Definition Multimedia Interface (HDMI) is currently used in several hundred million digital televisions and other consumer electronics that incorporate digital video and/or audio, such as game consoles, digital-video-disc (DVD) players, Blu-ray-disc players, and digital-set-top boxes. HDMI is a first single cable solution for transmission of uncompressed digital video signals using any suitable television or personal computer (PC) video format, including standard, enhanced, and high-definition video and/or audio signals using any suitable television and/or PC audio format from a source device to a sink device. 
         [0003]    DisplayPort was developed to address computing-world concerns and replace the external, box-to-box, analog-video-graphics-array (VGA) interfaces in PC and LCD monitors, as well as in consumer electronics, but it also targets the external digital-visual-interface (DVI) found mostly in consumer electronics systems. DisplayPort is a second single cable solution for transmission uncompressed of video signals using any suitable television or PC video format and/or audio signals using any suitable television or PC audio format from the source device to the sink device. 
         [0004]    HDMI is mainly used in the high definition consumer electronics market, such as an external interface for high-definition televisions to provide an example. DisplayPort, on the other hand, is a a general-purpose internal and external display interface aimed at the computer industry. Both HDMI and DisplayPort are used for the transmission of video signals and/or audio signals from the source device to the sink device. With the gradual convergence of high definition consumer electronics market and the computer industry, manufacturers will like to design source devices that are capable of transmitting the video signals and/or the audio signals using either HDMI and DisplayPort. However, HDMI and DisplayPort both transmit the video signals and/or the audio signals in differing ways. As a result of these differences, a typical HDMI source device includes a HDMI transmitter that is solely configured according to the HDMI interface standard. Likewise, a typical DisplayPort source device includes a DisplayPort transmitter that is solely configured according to the DisplayPort interface standard. Presently, to design a source device that transmits according to the HDMI interface standard and the DisplayPort interface standard, manufacturers design source devices with separate transmitters, one transmitter configured for HDMI and another separate transmitter configured for DisplayPort. These separate transmitters increase a cost and/or size of the source device. 
         [0005]    Therefore, what is needed is a source device having a single transmitter that is capable of transmitting video signals and/or audio signals using either the HDMI interface standard or the DisplayPort interface standard. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES 
         [0006]    The present invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. The left most digit(s) of a reference number identifies the drawing in which the reference number first appears. 
           [0007]      FIG. 1  illustrates a conventional High-Definition Multimedia Interface (HDMI) system architecture. 
           [0008]      FIG. 2  illustrates a conventional HDMI receiver used in the conventional HDMI system architecture. 
           [0009]      FIG. 3  illustrates a conventional DisplayPort system architecture. 
           [0010]      FIG. 4  illustrates a conventional DisplayPort transmitter and a conventional DisplayPort receiver used in the conventional DisplayPort system architecture. 
           [0011]      FIG. 5  illustrates a Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. 
           [0012]      FIG. 6  illustrates a HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. 
           [0013]      FIG. 7  further illustrates the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. 
           [0014]      FIG. 8  illustrates a HDMI mode of operation of the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. 
           [0015]      FIG. 9  illustrates a DisplayPort mode A of operation of the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. 
           [0016]      FIG. 10  illustrates a DisplayPort mode B of operation of the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. 
           [0017]      FIG. 11  further illustrates the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to a second exemplary embodiment of the present invention. 
           [0018]      FIG. 12  is a flowchart of exemplary operational steps of the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. 
       
    
    
       [0019]    The present invention will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    The following Detailed Description refers to accompanying drawings to illustrate exemplary embodiments consistent with the present invention. References in the Detailed Description to “one exemplary embodiment,” “an exemplary embodiment,” “an example exemplary embodiment,” etc., indicate that the exemplary embodiment described may include a particular feature, structure, or characteristic, but every exemplary embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same exemplary embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an exemplary embodiment, it is within the knowledge of those skilled in the relevant art(s) to effect such feature, structure, or characteristic in connection with other exemplary embodiments whether or not explicitly described. 
         [0021]    The exemplary embodiments described herein are provided for illustrative purposes, and are not limiting. Other exemplary embodiments are possible, and modifications may be made to the exemplary embodiments within the spirit and scope of the present invention. Therefore, the Detailed Description is not meant to limit the present invention. Rather, the scope of the present invention is defined only according to the following claims and their equivalents. 
         [0022]    The following Detailed Description of the exemplary embodiments will so fully reveal the general nature of the present invention that others can, by applying knowledge of those skilled in relevant art(s), readily modify and/or adapt for various applications such exemplary embodiments, without undue experimentation, without departing from the spirit and scope of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and plurality of equivalents of the exemplary embodiments based upon the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein. 
         [0023]    High-Definition Multimedia Interface (HDMI) 
         [0024]      FIG. 1  illustrates a conventional High-Definition Multimedia Interface (HDMI) system architecture. A HDMI system architecture  100  transfers uncompressed digital data representing audio, video, and/or auxiliary data information from a HDMI source  102  to a HDMI sink  104  according to a High-Definition Multimedia Interface Specification (herein “HDMI interface standard”), of which Version 1.3a is the latest, which is incorporated by reference herein in its entirety. The HDMI source  102  may include a set-top box, a Digital Video Disc (DVD) player, a personal computer (PC), a video gaming console, or any other suitable device that includes at least one HDMI output. The HDMI sink  104  may include a digital audio device, a computer monitor, a digital television, or any other suitable device that includes at least one HDMI input. 
         [0025]    Referring to  FIG. 1 , the HDMI source  162  includes a HDMI transmitter  106 . The HDMI transmitter  106  receives and transmits at least one of a video signal  150 , an audio signal  152 , and/or auxiliary data to the HDMI sink  104  via four differential Transition Minimized Differential Signaling (TMDS) output pairs. The auxiliary data may include data describing the video signal  150 , the audio signal  152  and/or the HDMI source  102  itself. 
         [0026]    Three of the four TMDS output pairs, denoted as output data pairs  154 . 1  through  154 . 3  are used for transmission of the video signal  150 , the audio signal  152 , and/or the auxiliary data. One of the four differential TMDS output pairs, denoted as data clock pair  156 , is used for transmission of a data clock to be used by the HDMI sink  104  to recover the video, the audio, and/or the auxiliary data information from the output data pairs  154 . 1  through  154 . 3 . 
         [0027]    The HDMI sink  104  includes a HDMI receiver  108 . The HDMI receiver  108  receives the output data pairs  154 . 1  through  154 . 3  and the data clock pair  156  from the HDMI source  102 . The HDMI receiver  108  may recover a video signal  158 , an audio signal  160 , and/or the auxiliary data from the output data pairs  154 . 1  through  154 . 3  based upon the data clock pair  156 . 
         [0028]    The HDMI system architecture  100 , including the HDMI source  102  and the HDMI sink  104 , is further defined in the HDMI interface standard. 
         [0029]      FIG. 2  illustrates a conventional HDMI receiver used in the conventional HDMI system architecture. TMDS technology uses current drive to develop a low voltage differential signal at a HDMI sink, such as the HDMI sink  104  to provide an example. A HDMI receiver  200  provides a differential HDMI biasing current I HDMI , having a first component I HDMI(+)  and a second component I HDMI(−) , through a transmission line to a HDMI transmitter, such as the HDMI transmitter  106  to provide an example. More specifically, the HDMI receiver  200  provides the differential HDMI biasing current I HDMI  from a HDMI voltage source V HDMI  within the HDMI receiver  200  itself to the HDMI transmitter. The transmission line carries data via output data pairs, such as the output data pairs  154 . 1  through  154 . 3  to provide an example, and a clock via the data clock pair, such the data clock pair  156  to provide an example, from the HDMI source to the HDMI sink. 
         [0030]    Referring to  FIG. 2 , the HDMI receiver  200  includes a differential to single-ended converter  202 . The differential to single-ended converter  202  converts a differential input signal  250 , including a first component  250 (+) and a second component  250 (−), to provide a single-ended output signal  252 . The differential input signal  250  may represent data from the one of the output data pairs  154 . 1  through  154 . 3  or a data clock from the data clock pair  156 . 
         [0031]    DisplayPort 
         [0032]      FIG. 3  illustrates a conventional DisplayPort system architecture. A DisplayPort system architecture  300  transfers uncompressed digital data representing audio and/or video information from a DisplayPort source  302  to a DisplayPort sink  304  according to the Video Electronics Standards Association (VESA) DisplayPort Standard (herein “DisplayPort interface standard”), of which Version 1, Revision 1a, is the latest, which is incorporated by reference herein in its entirety. The DisplayPort source  302  may include a set-top box, a Digital Video Disc (DVD) player, a personal computer (PC), a video gaming console, or any other suitable device that includes at least one DisplayPort output. The DisplayPort sink  304  may include a digital audio device, a computer monitor, a digital television, or any other suitable device that includes at least one DisplayPort input. 
         [0033]    Referring to  FIG. 3 , the DisplayPort source  302  includes a DisplayPort transmitter  306 . The DisplayPort transmitter  306  transmits at least one of a video signal  350  and/or an audio signal  352  to the DisplayPort sink  304  via a Main Link  354 . The Main Link  354  may include one, two, or four AC-coupled, doubly terminated differential pairs often referred to as lanes. Unlike the HDMI Source, the DisplayPort source  302  does not dedicate a lane to provide a data clock. The DisplayPort sink  304  extracts the data clock from the data carried by the Main Link  354 . The DisplayPort system architecture  300  additionally includes a bi-directional auxiliary channel  356  for management of the Main Link  354  and control of the DisplayPort source  302  and/or the DisplayPort sink  304 . 
         [0034]    The DisplayPort system architecture  300  includes a DisplayPort receiver  308 . The DisplayPort receiver  308  receives data from the Main Link  354  and extracts the data clock from the data carried by the Main Link  354 . 
         [0035]    The DisplayPort receiver  308  may recover at least one of a video signal  358 , and/or an audio signal  160  from the Main Link  354 . 
         [0036]    The DisplayPort system architecture  300  including the DisplayPort source  302  and the DisplayPort sink  304  is further defined in the DisplayPort interface standard. 
         [0037]      FIG. 4  illustrates a conventional DisplayPort transmitter and a conventional DisplayPort receiver used in the conventional DisplayPort system architecture. Unlike the HDMI receiver  200 , a DisplayPort receiver  402  is AC-coupled to a DisplayPort transmitter  400 . The DisplayPort transmitter  306 , as described above, may include one or more DisplayPort transmitters  400 . Likewise the DisplayPort receiver  308  may include one or more DisplayPort receivers  402 . More specifically, the DisplayPort transmitter  400  includes a first capacitor C 1  to AC-couple the first component  454 (+) of the differential signal  454  from the DisplayPort transmitter  400  and a second capacitor C 2  to AC-couple the second component  454 (−) of the differential signal  454  from the DisplayPort transmitter  400 . 
         [0038]    The AC-coupling of the DisplayPort transmitter  400  and the DisplayPort receiver  402  prevents the DisplayPort receiver  402  from providing a biasing current through a transmission line to the DisplayPort transmitter. Therefore, the DisplayPort transmitter  400  internally provides the biasing current necessary for operation. The transmission line carries data via the Main Link  354  and/or management and control data via the auxiliary channel  356  from the DisplayPort source to the DisplayPort sink. 
         [0039]    Referring to  FIG. 4 , the DisplayPort transmitter  400  includes a single-ended to differential to converter  404 . The single-ended to differential to converter  404  converts a single-ended signal  450  to provide the differential signal  454  including a first component  454 (+) and a second component  454 (−). 
         [0040]    The differential signal  454  may represent data transmitted to the Main Link  354  and/or management and control data transmitted to the auxiliary channel  356 . Likewise, the DisplayPort receiver  402  includes a differential to single-ended converter  406 . The differential to single-ended converter  402  converts a differential signal  454 , including a first component  454 (+) and a second component  454 (−), to provide a single-ended output signal  452 . The differential input signal  454  may represent data received from the Main Link  354  and/or management and control data received from the auxiliary channel  356 . 
         [0041]    Dual HDMI/DisplayPort 
         [0042]      FIG. 5  illustrates a Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. A DisplayPort system architecture  500  transfers uncompressed digital data representing audio and/or video information from a HMDI/DisplayPort dual source  502  to a HDMI sink, such as the HDMI sink  104 , or a DisplayPort sink, such as the DisplayPort sink  304 , according to the HDMI interface standard or the DisplayPort interface standard. In other words, the HMDI/DisplayPort dual source  502  may communicate with any suitable sink device that is configured to operate according to the DisplayPort interface standard and/or the HDMI interface standard. The dual source  502  may include a set-top box, a Digital Video Disc (DVD) player, a personal computer (PC), a video gaming console, or any other suitable device that includes at least one output that is capable of communicating with the HDMI sink or the DisplayPort sink. 
         [0043]    Referring to  FIG. 5 , the HMDI/DisplayPort dual source  502  includes a HMDI/DisplayPort dual transmitter  506 . The HMDI/DisplayPort dual transmitter  506  represents a single transmission device that may communicate with any suitable sink device that is configured to operate according to the DisplayPort interface standard and/or the HDMI interface standard. For example, the HMDI/DisplayPort dual transmitter  506  transmits at least one of a video signal  550 , and/or an audio signal  552  to the one of the HDMI sink  104  or the DisplayPort sink  304  via N differential output pairs denoted as output data pairs  554 . 1  through  554 .N. For example, the HMDI/DisplayPort dual transmitter  506  may transmit the video signal  550 , and/or the audio signal  552  to the HDMI sink via four output pairs according to the HDMI interface standard. Alternatively, the HMDI/DisplayPort dual transmitter  506  may transmit the video signal  550  and/or the audio signal  552  to the DisplayPort sink via one, two, or four output pairs according to the DisplayPort interface standard. 
         [0044]      FIG. 6  illustrates a HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. An HMDI/DisplayPort dual transmitter, such as the HMDI/DisplayPort dual transmitter  506  to provide an example, may include one HMDI/DisplayPort transmitter  600  for each output data pair. 
         [0045]    For example, the HMDI/DisplayPort dual transmitter may include four HMDI/DisplayPort transmitters  600  to transmit a video signal, such as the video signal  550 , an audio signal, such as the audio signal  552 , and/or a data clock according to the HDMI interface standard. Alternatively, the HMDI/DisplayPort dual transmitter may include one, two, or four HMDI/DisplayPort transmitters  600  to transmit the video signal  550 , and/or the audio signal  552  according to the DisplayPort interface standard. 
         [0046]    The HMDI/DisplayPort transmitter  600  may transmit a differential output signal  652 , having a first component  652 (+) and a second component  652 (-), based upon a differential input signal  650 , having a first component  650 (+) and a second component  650 (−), to a HDMI sink, such as the HDMI sink  104 , or a DisplayPort sink, such as the DisplayPort sink  304 , according to the HDMI interface standard or the DisplayPort interface standard. The differential input signal  650  may represent one or more of the video signal, the audio signal, and/or the data clock according to the HDMI interface standard. Alternatively, the differential input signal  650  may represent one or more of the video signal and/or the audio signal according to the DisplayPort interface standard. 
         [0047]    From the discussion above, a HDMI sink, such as the HDMI sink  104  to provide an example, may provide a biasing current I BIAS , such as the differential HDMI biasing current I HDMI  as described in  FIG. 2  to provide an example, to the HMDI/DisplayPort transmitter  600  in an HDMI mode of operation. Alternatively, the HMDI/DisplayPort transmitter  600  may internally provide the biasing current I BIAS  in the DisplayPort mode of operation. 
         [0048]    The HMDI/DisplayPort transmitter  600  includes a first selectable impedance network  602 , a second selectable impedance network  604 , and a source current generator  606 . The first selectable impedance network  602  and the second selectable impedance network  604  may include any suitable combination of passive elements, such-as resistors, capacitors, and inductors to provide some examples that are selectable by the HMDI/DisplayPort transmitter  600 . For example, the first selectable impedance network  602  and/or the second selectable impedance network  604  may each include one or more selectable impedances. The HMDI/DisplayPort transmitter  600  may select any one of the selectable impedances or any combination of the selectable impedances depending upon a mode of operation. 
         [0049]    For example, in the HDMI mode of operation, the HMDI/DisplayPort transmitter  600  selects a first combination of the selectable impedances in the first selectable impedance network  602  and selects a first combination of the selectable impedances in the second selectable impedance network  604  such that the HMDI/DisplayPort transmitter  600  is configured to be provided with the biasing current I BIAS  via the differential output signal  652 . The DisplayPort mode of operation includes a high output voltage mode referred to as a DisplayPort mode A of operation and a low output voltage mode referred to as a DisplayPort mode B of operation. In the DisplayPort mode A of operation, the HMDI/DisplayPort transmitter  600  selects a second combination of the selectable impedances in the first selectable impedance network  602  and selects a second combination of the selectable impedances in the second selectable impedance network  604  such that the HMDI/DisplayPort transmitter  600  is configured to internally provide the biasing current I BIAS  from an operating voltage V DISPLAYPORT . Likewise, in the DisplayPort mode B of operation, the HMDI/DisplayPort transmitter  600  selects a third combination of the selectable impedances in the first selectable impedance network  602  and selects a third combination of the selectable impedances in the second selectable impedance network  604  such that the HMDI/DisplayPort transmitter  600  is configured to internally provide the biasing current I BIAS  from the operating voltage V DISPLAYPORT . 
         [0050]    The source current generator  606  determines a magnitude of the biasing current I BIAS  that is to be provided by the HMDI/DisplayPort transmitter  600  in the HDMI mode of operation or internally provided by the HMDI/DisplayPort transmitter  600  in the DisplayPort mode of operation. In other words, the source current generator  606  controls the magnitude of the biasing current I BIAS  that is to be provided by the HMDI/DisplayPort transmitter  600  in the HDMI mode of operation or internally provided by the HMDI/DisplayPort transmitter  600  in the DisplayPort mode of operation. 
         [0051]      FIG. 7  further illustrates the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. A HMDI/DisplayPort transmitter  700  may transmit the differential output signal  652  based upon the differential input signal  650  to a HDMI sink, such as the HDMI sink  104 , or a DisplayPort sink, such as the DisplayPort sink  304 , according to the HDMI interface standard or the DisplayPort interface standard. The HMDI/DisplayPort transmitter  700  may represent an exemplary embodiment of the HMDI/DisplayPort transmitter  600 . The HMDI/DisplayPort transmitter  700  includes a first selectable impedance network  702 , a second selectable impedance network  704 , and a source current generator  706 . The first selectable impedance network  702 , the second selectable impedance network  704 , and the source current generator  706  may represent exemplary embodiments of the first selectable impedance network  602 , the second selectable impedance network  604 , and the source current generator  606 , respectively. 
         [0052]    The first selectable impedance network  702  includes resistors R 1  through R 4  coupled to a corresponding switch Q 3  through Q 6 . In an exemplary embodiment, the switches Q 3  through Q 6  are p-type metal oxide silicon (PMOS) transistors. However, this example is not limiting, those skilled in the relevant art(s) may implement the switches Q 3  through Q 6  differently using n-type metal oxide silicon (NMOS) transistors differently in accordance with the teachings herein without departing from the spirit and scope of the present invention. The first selectable impedance network  702  selectively switches among resistors R 1  through R 4 , or selectively switches one or more combinations of the resistors R 1  through R 4  depending upon the mode of operation of the HMDI/DisplayPort transmitter  700 . Each of the resistors R 1  through R 4  is coupled to a corresponding switch Q 3  through Q 6 . The resistors R 1  through R 4  may be switched into or out of the first selectable impedance network  702  by selectively turning on or turning off its corresponding switch Q 3  through Q 6 . A transistor Q 7 , having its gate coupled to its respective drain, limits a flow back current that may be provided by the differential output signal  652  to the operating voltage V DISPLAYPORT  when the operating voltage V DISPLAYPORT  is powered down, namely in the HDMI mode of operation. In an exemplary embodiment, the transistor Q 7  represents a NMOS transistor formed within a deep n-well. In this exemplary embodiment, the transistor Q 7  includes five terminals: a gate, a drain, a source, a body, and a deep n-well. The gate, drain, body, and deep n-well are coupled to the operating voltage V DISPLAYPORT  while the source is coupled to the first selectable impedance network  702 . 
         [0053]    The second selectable impedance network  704  includes resistors R 5  through R 8  coupled to a corresponding switch Q 8  through Q 11 . In an exemplary embodiment, the switches Q 8  through Q 11  are p-type metal oxide silicon (PMOS) transistors. However, this example is not limiting, those skilled in the relevant art(s) may implement the switches Q 8  through Q 11  differently using n-type metal oxide silicon (NMOS) transistors differently in accordance with the teachings herein without departing from the spirit and scope of the present invention. The second selectable impedance network  704  selectively switches among resistors R 5  through R 8 , or selectively switches one or more combinations of the resistors R 5  through R 8  depending upon the mode of operation of the HMDI/DisplayPort transmitter  700 . Each of the resistors R 5  through R 8  is coupled to a corresponding switch Q 8  through Q 11 . The resistors R 5  through R 8  may be switched into or out of the second selectable impedance network  704  by selectively turning on or turning off its corresponding switch Q 8  through Q 11 . 
         [0054]    The source current generator  706  is provided with the biasing current I BIAS  from the HMDI sink in the HDMI mode of operation or is internally provided with the biasing current I BIAS  in the DisplayPort mode of operation. 
         [0055]    The biasing current I BIAS  is used to bias a first transistor Q 1  and a second transistor Q 2 . In an exemplary embodiment, the first transistor, Q 1  and the second transistor Q 2  represent n-type metal oxide silicon (NMOS) transistors. 
         [0056]    However, this example is not limiting, those skilled in the relevant art(s) may implement the switches Q 3  through Q 6  differently using p-type metal oxide silicon (PMOS) transistors differently in accordance with the teachings herein without departing from the spirit and scope of the present invention. The first transistor Q 1  and the second transistor Q 2  may receive the first component  650 (+) of the differential input signal  650  and the second component  650 (−) of the differential input signal  650 , respectively. 
         [0057]    As shown in  FIG. 7 , the source current generator  706  includes a replica current generator  708  and a current mirror module  710 : The replica current generator  708  provides a replica current I REPLICA  to the current mirror module  710 . More specifically, the replica current generator  708  provides the replica current I REPLICA  to the current mirror module  710  based upon a first operating voltage V DISPLAYPORT , typically 2.5VDC, and a second operating voltage V HDMI , typically 3.3VDC, by selectively switching among resistors R 10  through R 12  or a combination of the resistors R 10  through R 12  depending upon the mode of operation of the HMDI/DisplayPort transmitter  700 . Each of the resistors R 10  through R 12  is coupled to a corresponding switch Q 12  through Q 14 . The resistors R 10  through R 12  may be switched into or out of the replica current generator  708  by selectively turning on or turning off its corresponding switch Q 12  through Q 14 . A transistor Q 15 , having its gate coupled to its respective drain, limits a flow back current that may be provided by the replica current I REPLICA  to the operating voltage V DISPLAYPORT  when the operating voltage V DISPLAYPORT  is powered down, namely in the HDMI mode of operation. In an exemplary embodiment, the transistor Q 15  represents a NMOS transistor formed within a deep n-well. In this exemplary embodiment, the transistor Q 15  includes five terminals: a gate, a drain, a source, a body, and a deep n-well. The gate, drain, body, and deep n-well are coupled to the operating voltage V DISPLAYPORT  while the source is coupled to the resistors R 10  and R 11 . 
         [0058]    The current mirror module  710  determines the magnitude of the biasing current I BIAS  by mirroring a reference current I REF , the replica current I REPLICA  and/or the bias current I BIAS . More specifically, the current mirror module  710  ensures that the replica current I REPLICA  and/or the bias current I BIAS  is proportional to or mirrors the reference current I REF . In other words, the current mirror module  710  operates to ensure that a feedback voltage V F , a replica voltage V R , and a bias voltage V B , are substantially equal such that the replica current I REPLICA  and/or the bias current I BIAS  mirrors the reference current I REF . As shown in  FIG. 7 , the current mirror module  710  includes transistors Q 16  through Q 19  and an operational amplifier AMP 1 . 
         [0059]    The operational amplifier AMP 1  controls the reference current I REF  flowing through the transistor Q 16  by comparing the replica voltage V R  with the feedback voltage V F . If the replica voltage V R  is not equal to the feedback voltage V F , the operational amplifier AMP 1  increases and/or decreases the amount of the reference current I REF  flowing through the transistor Q 16  until the replica voltage V R  is substantially equal to the feedback voltage V F . 
         [0060]    The transistor Q 17  receives the reference current I REF  from the transistor Q 16  as determined by the operational amplifier AMP 1 . The transistor Q 18  mirrors the transistor Q 17  such that a current flowing through the transistor Q 18  is proportional to a current flowing through the transistor Q 17 . In other words, the current flowing through the transistor Q 18  mirrors the current flowing through the transistor Q 17  such that the replica voltage V R  is substantially equal to the feedback voltage V F . In an exemplary embodiment, the transistor Q 17  has a width that is twice a width of the transistor Q 18  such that approximately twice as much current flows through the transistor Q 17  when compared with the transistor Q 18 . 
         [0061]    The transistor Q 19  mirrors the current flowing through the transistor Q 17  and/or the transistor Q 18  such that the current flowing through the transistor Q 17  and/or the transistor Q 18  is proportional to a current flowing through the transistor Q 19 . In other words, the current flowing through the transistor Q 19  mirrors the current flowing through the transistor Q 17  and/or the transistor Q 18  such that the replica voltage V R , the feedback voltage V F , and the replica voltage V R  are substantially equal. In an exemplary embodiment, the transistor Q 19  has a programmable width. 
         [0062]      FIG. 8  illustrates a HDMI mode of operation of the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. More specifically,  FIG. 8  illustrates a HMDI/DisplayPort transmitter  800  configured to operate in the HDMI mode of operation. The HMDI/DisplayPort transmitter  800  may represent an exemplary embodiment of the HMDI/DisplayPort transmitter  700  configured to operate in the HDMI mode of operation. 
         [0063]    As shown in  FIG. 8 , in the first selectable impedance network  702 , the switches Q 3  through Q 6  may be turned off via the control lines A and B such that the first selectable impedance network  702  is turned off in its entirety in the HDMI mode of operation. In the second selectable impedance network  704 , the switches Q 8  through Q 11  may be turned on via control lines F and G. R DS,Q8  through R DS,Q11  represent a drain to source resistance of the switches Q 8  through Q 11 , when turned on. This combination of the first selectable impedance network  702  and the second selectable impedance network  704  allows the biasing current I BIAS  to be provided to the source current generator  706  by the HDMI sink. In the replica current generator  708 , the switch Q 14  is turned on via a control line E and switches Q 12  and Q 13  are turned off via control lines C and D. R DS,Q14  represents a drain to source resistance of the switch Q 14 , when turned on. The replica current generator  708  provides the replica current I REPLICA  to the current mirror  710 . The current mirror  710  causes the biasing current I BIAS  and the replica current I REPLICA  to be proportional to the reference current I REF . 
         [0064]      FIG. 9  illustrates a DisplayPort mode A of operation of the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. More specifically,  FIG. 9  illustrates a HMDI/DisplayPort transmitter  900  configured to operate in the DisplayPort mode A of operation according to the DisplayPort interface standard. The HMDI/DisplayPort transmitter  900  may represent an exemplary embodiment of the HMDI/DisplayPort transmitter  700  configured to operate in the DisplayPort mode A of operation. 
         [0065]    As shown in  FIG. 9 , in the first selectable impedance network  702 , the switches Q 3  through Q 6  may be turned on via the control lines A and B in the DisplayPort mode A of operation. R DS,Q3  through R DS,Q6  represent a drain to source resistance of the switches Q 3  through Q 6 , when turned on. In the second selectable impedance network  704 , the switches Q 8  through Q 11  may be turned off via control lines F and G such that the second selectable impedance network  704  is turned off in its entirety. This combination of the first selectable impedance network  702  and the second selectable impedance network  704  allows the biasing current I BIAS  to be internally provided to the source current generator  706 . In the replica current generator  708 , the switch Q 12  is turned on via a control line C and switches Q 13  and Q 14  are turned off via control lines D and E. R DS,Q12  represents a drain to source resistance of the switches Q 12 , when turned on. The current mirror  710  causes the biasing current I BIAS  and the replica current I REPLICA  to be proportional to the reference current I REF . 
         [0066]      FIG. 10  illustrates a DisplayPort mode B of operation of the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. 
         [0067]    More specifically,  FIG. 10  illustrates a HMDI/DisplayPort transmitter  1000  configured to operate in the DisplayPort mode B of operation according to the DisplayPort interface standard. The HMDI/DisplayPort transmitter  1000  may represent an exemplary embodiment of the HMDI/DisplayPort transmitter  700  configured to operate in the DisplayPort mode B of operation. 
         [0068]    As shown in  FIG. 10 , in the first selectable impedance network  702 , the switches Q 3  and Q 6  may be turned on via the control line A and the switches Q 4  and Q 5  may be turned off via the control line B in the DisplayPort mode B of operation. R DS,Q3  and R DS,Q6  represent a drain to source resistance of the switches Q 3  and Q 6 , when turned on. In the second selectable impedance network  704 , the switches Q 8  through Q 9  may be turned on via control line F and the switches Q 10  through Q 11  may be turned off via control line F and G. R DS,Q8  and R DS,Q9  represent a drain to source resistance of the switches Q 8  and Q 9 , when turned on. This combination of the first selectable impedance network  702  and the second selectable impedance network  704  allows the biasing current I BIAS  to be internally provided to the source current generator  706 . In the replica current generator  708 , the switches Q 12  and Q 13  are turned on via a control lines C and D and the switches Q 14  is turned off via control line E. R DS,Q12  and R DS,Q13  represent a drain to source resistance of the switches Q 12  and Q 13 , when turned on. The current mirror  710  causes the biasing current I BIAS  and the replica current I REPLICA  to be proportional to the reference current I REF . 
         [0069]      FIG. 11  further illustrates the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to a second exemplary embodiment of the present invention. A HMDI/DisplayPort transmitter  1100  is substantially similar to the HMDI/DisplayPort transmitter  700  as described above. Therefore, only differences between the HMDI/DisplayPort transmitter  700  and the HMDI/DisplayPort transmitter  1100  are to be described in further detail. 
         [0070]    The HMDI/DisplayPort transmitter  1100  includes thin oxide transistors Q 20  through Q 22  and thick oxide transistors Q 23  through Q 25 , the thick oxide transistors Q 23  through Q 25  being formed with a thicker gate oxide when compared with a gate oxide of the thin oxide transistors Q 20  through Q 22 . This combination of thin oxide and thick oxide transistors provides the HMDI/DisplayPort transmitter  1100  with a greater speed when compared to the HMDI/DisplayPort transmitter  700  that only includes the transistors Q 1  and Q 2 . More specifically, the thinner gate oxide of the thin oxide transistors Q 20  through Q 22  allows the thin oxide transistors Q 20  through Q 22  to turn off and/or on at faster rate when compared to the transistors Q 1  and Q 2  of the HMDI/DisplayPort transmitter  700 . However, the first operating voltage V DISPLAYPORT  and/or the second operating voltage V HDMI  may exceed a breakdown voltage of the thin oxide transistors Q 20  through Q 22 . The thick oxide transistors Q 23  through Q 25  prevent the thin oxide transistors Q 20  through Q 22  from exceeding their respective breakdown voltages. It should be noted that the thin oxide transistor Q 22  and the thick oxide transistor Q 25  allow the HMDI/DisplayPort transmitter  1100  to better mirror the reference current I REF . 
         [0071]    The HMDI/DisplayPort transmitter  1100  includes a source current generator  1102 . The source generator  1102  includes a biasing module  1104  in addition to the replica current generator  708  and the current mirror module  710  as described above. The biasing module  1104  provides a fixed biasing current to the thick oxide transistors Q 23  through Q 25 . The biasing module  1104  includes a resistor R 13 , transistors Q 26  and Q 27 , and an operational amplifier AMP 2 . The operational amplifier AMP 2  provides the fixed biasing current by comparing a fixed reference voltage V REF  with a voltage between a source of the transistor Q 26  and a drain of the transistor Q 27 . A biasing of the transistor Q 26  is controlled by an output of the operational amplifier AMP 2  while a biasing of the transistor Q 27  is controlled by a fixed reference current I REF2 . A current, dependent on the biasing of the transistors Q 26  and Q 27 , flows from the second operating voltage V HDMI  flows through the resistor R 13  and transistors Q 26  and Q 27 . 
         [0072]    The HMDI/DisplayPort transmitter  1100  may be configured to operate in the HDMI mode of operation, the DisplayPort mode A of operation, and the DisplayPort mode B of operation as discussed in  FIG. 8  through  FIG. 10 . 
         [0073]      FIG. 12  is a flowchart of exemplary operational steps of the HMDI/DisplayPort transmitter used in the Dual HDMI/DisplayPort system architecture according to an exemplary embodiment of the present invention. The invention is not limited to this operational description. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings herein that other operational control flows are within the scope and spirit of the present invention. The following discussion describes the steps in  FIG. 12 . 
         [0074]    At step  1202 , an impedance of a first selectable impedance network is selected. The first selectable impedance network, such as the first selectable impedance network  602  to provide an example, includes one or more selectable impedances. Any one of the selectable impedances of the first selectable impedance network or any combination of the selectable impedances may be selected depending upon a mode of operation. For example, step  1202  may select a first impedance from among the selectable impedances in the HDMI mode of operation and a second impedance from among the selectable impedances in the DisplayPort mode of operation. 
         [0075]    At step  1204 , an impedance of a second selectable network is selected. The second selectable network, such as the second selectable impedance network  602  to provide an example, includes one or more selectable impedances. Any one of the selectable impedances of the second selectable network or any combination of the selectable impedances may be selected depending upon the mode of operation. For example, step  1204  may select a first impedance from among the selectable impedances in the HDMI mode of operation and a second impedance from among the selectable impedances in the DisplayPort mode of operation. 
         [0076]    At step  1206 , a replica current, such as the replica current I REPLICA  to provide an example, corresponding to the HDMI mode of operation or the DisplayPort mode of operation is produced. The replica current is configured to replicate a biasing current, such as the biasing current I BIAS , that may be externally provided by a HDMI sink, such as the HDMI sink  104  to provide an example, or internally generated depending upon the mode of operation. A replica current generator, such as the replica current generator  710  to provide an example, may be used to provide the replica current. The replica current is proportional to or mirrors a reference current, such as the reference current l REF  to provide an example. In other words, the replica current mirrors the reference current such that ultimately the biasing current mirrors the reference current as well. 
         [0077]    At step  1208 , data is received by a data transmitter, such as the HMDI/DisplayPort transmitter  600 , the HMDI/DisplayPort transmitter  700 , and or the HMDI/DisplayPort transmitter  1100  to provide some examples. The data transmitter transmits the data to the HDMI sink according to the HDMI interface standard or to a DisplayPort sink, such as the DisplayPort sink  304 , according to the DisplayPort interface standard. 
       CONCLUSION 
       [0078]    It is to be appreciated that the Detailed Description section, and not the Abstract section, is intended to be used to interpret the claims. The Abstract section may set forth one or more, but not all exemplary embodiments, of the present invention, and thus, are not intended to limit the present invention and the appended claims in any way. 
         [0079]    The present invention has been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed. 
         [0080]    It will be apparent to those skilled in the relevant art(s) that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only according to the following claims and their equivalents.

Technology Category: g