Patent Document

BACKGROUND 
       [0001]    A register file is an array of processor registers (memory cells, bit cells) in a central processing unit (CPU). Modern integrated circuit-based register files may be implemented by way of fast static random access memories (SRAMs) with multiple ports having dedicated read and write ports. The memory cells may operate by discharging read and write bitlines to ground level during read and write operations respectively. The read and write bitlines may be precharged to a voltage source (Vcc) level after every operation and may be maintained at Vcc even in IDLE mode. Maintaining bitlines at Vcc level results in the register file suffering high leakage current. Discharging and precharging bitlines in full-swing to perform read/write operations requires high active power for the register file. 
         [0002]      FIG. 1  illustrates an example memory cell  100  (e.g., 8 transistor memory cell). The memory cell  100  includes first and second transistors  110 ,  120  coupled together in series and third and fourth transistors  130 ,  140  coupled in series. Both series stacks are coupled between ground and Vcc and are cross coupled to one another (gate to source/drain connection). The first and third transistors  110 ,  130  may be positive channel transistors (e.g., PMOS) while the second and fourth transistors  120 ,  140  may be negative channel transistors (e.g., NMOS). The memory cell  100  also includes a fifth and sixth transistor  150 ,  160  coupled to the gates of the first series stack  110 / 120  and the second series stack  130 / 140  respectively. The fifth and sixth transistors  150 ,  160  are coupled to write wordline (gates) and write or writebar bitlines respectively. The transistors  150 ,  160  act as pass gates for writing data to the memory cell  100 . When the memory cell is not in write mode (idle or read mode) the bitlines are tied high (Vcc). When the memory cell  100  is in write mode the write wordline is activated (set high) and the appropriate bitline (write or writebar) is discharged (set low) to write the appropriate bit to the memory cell  100 . 
         [0003]    The memory cell  100  further included seventh and eight transistors  170 ,  180  coupled together in series. The transistor  170  is coupled to read wordline and read bitline. When the memory cell  100  is not in read mode (idle or write mode) the read bitline is tied high. When the memory cell  100  is in read mode the read wordline is activated (set high) and the read bitline is discharged (set low) so that the data can be read from the memory cell  100 . 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    The features and advantages of the various embodiments will become apparent from the following detailed description in which: 
           [0005]      FIG. 1  illustrates an example memory cell, according to one embodiment; 
           [0006]      FIG. 2  illustrates an example ground biased memory system, according to one embodiment; 
           [0007]      FIG. 3  illustrates an example ground biased register file, according to one embodiment; 
           [0008]      FIG. 4  illustrates an example read operation for a ground biased register file, according to one embodiment; and 
           [0009]      FIG. 5  illustrates an example write operation for a ground biased register file, according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]      FIG. 2  illustrates an example ground biased memory system  200  (e.g., file register). The system  200  includes a memory cell  210  (e.g.,  100  of  FIG. 1 ), ground biased write control circuitry  220 , ground biased read control circuitry  230 , read bit-line sense control circuitry  240 , skewed output inverter  250 , and write bitline keeper  260   
         [0011]    The ground biased write control circuitry  220  is used to ensure that write and writebar bitlines are biased at GND level when bits are not being written to the memory cell  210  (either in IDLE mode or READ mode). The ground biased write control circuitry  220  may be controlled by a ground biased write enable signal (e.g., inverted write enable signal). The ground biased write control circuitry  220  may include first and second transistors  222 ,  224  coupled in a shunt configuration to the write bitline and the writebar bitline respectively. The first and second transistors  222 ,  224  may be negative channel transistors (e.g., NMOS). The first and second transistors  222 ,  224  may receive the ground biased write enable signal (at their gates) and bias the bitlines to ground when the signal is active (no writing). 
         [0012]    The ground biased read control circuitry  230  is used to ensure that read bitline is biased at GND level when bits are not being read from the memory cell  210  (either in IDLE mode or WRITE mode). The ground biased read control circuitry  230  may be controlled by a ground biased read enable signal (e.g., inverted read enable signal). The ground biased read control circuitry  230  may include a transistor  232  coupled in a shunt configuration to the read bitline. The transistor  232  may be negative channel transistor (e.g., NMOS). The transistor  232  may receive the ground biased read enable signal (at gate) and bias the bitline to ground when the signal is active (no reading). 
         [0013]    The read bitline sense control circuitry  240  is used to sense the read bitline during read operation. The read bitline sense control circuitry  240  may be controlled by the ground biased read enable signal. The read bitline sense control circuitry  240  may include a transistor  242  coupled to the read bitline and a voltage source node (e.g., Vcc). The transistor  242  may be positive channel transistor (e.g., PMOS). The transistor  242  may receive the ground biased read enable signal (at gate) and be activated for sensing the read bitline when the ground biased read enable signal is inactive (reading is occurring). 
         [0014]    The skewed output inverter  250  receives the signal read from memory cell  210  via the read bitline and inverts the data when the data exceeds a defined trip-point voltage. The inverted data may be provided to an output latch  270 . The output latch  270  may output the data based on a latch enable signal. 
         [0015]    The write bitline keeper  260  is used to maintain the write bitline or the writebar bitline that was active in order to write data to the memory cell  210  at a predetermined voltage level (e.g., Vcc) during consecutive write cycles. The write bitline keeper  260  may include inverters  262 ,  264  and transistors  266 ,  268  coupled between the write bitline or writebar bitline and a voltage source node (e.g., Vcc) respectively. 
         [0016]      FIG. 3  illustrates an example ground biased register file  300 . The register file  300  includes data architecture circuitry (right side) and timing architecture circuitry (left side). The data architecture circuitry includes a plurality of memory cells  305  (e.g.,  100 ,  210 ), a data input driver (e.g., positive edge flip-flops)  310 , ground biased write control circuitry  315  (e.g.,  220 ), write bitline keeper  320  (e.g.,  260 ), output latch  325 , output inverter  330  (e.g.,  250 ), ground biased read control circuitry  335  (e.g.,  230 ), and read bit-line sense control circuitry  340  (e.g.,  240 ). The function of each of these devices is the same or similar to the corresponding devices discussed with respect to  FIG. 2  above. 
         [0017]    The timing architecture circuitry includes a write enable flip-flop  350 , a write address row decoder flip-flop  355 , low phase timing logics  360 ,  365 , inverters  370 ,  375 ,  380 , and NAND gates  385 . The timing architecture also includes a read address row decoder flip-flop, a read enable flip-flop, inverters and NAND gates (not illustrated). 
         [0018]    The write enable flip-flop  350  receives a write enable signal when the register file  300  is in write mode and enables writing by activating the enable signal on the positive edge of a clock signal. The row decoder  355  receives write addresses associated with memory cells  305  to have bits written thereto and activates associated write wordlines (rows). The row decoder  350  activates the write wordlines on the positive edge of the enable signal. The low phase timing logics  360 ,  365  receive the enable signal from the write enable flip flop  350  and activates a write driver enable signal and a write wordline enable signal respectively on the low phase of the clock (when the clock signal is in a high phase the enable signals are inactive). It should be noted that the low phase timing logics  360 ,  365  are illustrated as separate devices but may in fact be the same device. 
         [0019]    The write driver enable signal is provided to data input driver  310 . The data input driver  310  receives input data for writing and activates the appropriate bitline (write or writebar) based on the input data when the write driver enable signal is active (the write enable signal clocks the data in). 
         [0020]    The write wordline enable signal is provided to NAND gates  370  associated with each memory cell  305 . The NAND gates also receive the associated write wordline for each memory cell  305 . The result of the NAND gates  370  are run through the inverters  375  and then provided to the memory cell  305 . When both signals are active an active signal is provided to the memory cell  305 . It should be noted that the NAND gates  370  and inverters  375  could be replaced with AND gates or other circuitry (write wordline activation circuitry). 
         [0021]    The write enable signal is inverted (e.g., by the inverter  380 ) to produce the write ground biased enable signal that is provided to the ground biased write control circuitry  315 . The write ground biased enable signal drives the write/writebar bitlines to ground when no writing is occurring. 
         [0022]    While the logic for generating a read enable signal is not illustrated (e.g., read enable flip-flop), the read enable signal would be inverted (e.g., by the inverter  385 ) to produce the read ground biased enable signal that is provided to the ground biased read control circuitry  335  and the read bit-line sense control circuitry  340 . The read ground biased enable signal drives the read bitline to ground when no reading is occurring (by activating the ground biased read control circuitry  335 ) and helps sense the read output (by activating the read bit-line sense control circuitry  340 ) when reading is occurring. 
         [0023]    While the logic for activating the appropriate read wordlines is not illustrated (e.g., read address row decoder), the read wordline signals would be provided, along with the read enable signal, to read wordline activation circuitry (e.g., NAND gates  390  and inverters  395 ) for the associated memory cells  305 . 
         [0024]      FIG. 4  illustrates an example read operation for a ground biased register file (e.g.,  300 ). When discussing the read operation and the various signals associated therewith reference will be made to components of the ground biased register file  300  from  FIG. 3 . During non-reading periods (e.g., write, idol), the read wordline signals provided to the associated bit cells  305  are inactive (e.g., low, logic 0) and the read ground bias enable signal is active (e.g., high, logic 1). The active read ground biased enable signal turns ON the ground biased read control circuitry  335  and turns OFF the read bit-line sense control circuitry  340  so that the read bitline is biased to ground. Since the read bitline is biased to ground the output of the inverter  330  will be high. 
         [0025]    During reading periods, the read wordline signals provided to the associated bit cells  305  are activated to turn ON the bitcell read ports. Then, the read ground biased enable signal is deactivated and the deactivated read ground biased enable signal turns OFF the ground biased read control circuitry  335  and turns ON the read bit-line sense control circuitry  340  to start bitline sensing process. When a ‘0’ is being read, current from the read bit-line sense control circuitry  340  charges up the read bitline capacitance. The read bitline is charged until the inverter  330  trips (the trip value is met). The output of the inverter  330  at that point will be zero. The inverter output is provided to the output latch  335  which outputs the data when a latch enable signal is received. The latch enable signal may be generated by a self-timed control block based on the end of the read cycle (when clock returns to low phase). The latch enable signal may coincide with the timing of the inverter  330  being tripped when reading a ‘0’. 
         [0026]    When a ‘1” is being read, current from the read bit-line sense control circuitry  340  flows into the bitcell  305  and the read bitline stays at a voltage level near to ground. When the enable signal is activated (e.g., by the self-timed control block) the inverter  330  has not tripped so the latch  335  outputs the ‘0’. 
         [0027]    After the output data (either ‘0’or ‘1’) is latched, the read wordline signal is turned OFF and the read ground bias enable signal is turned ON so that the read bitline is again biased at GND level. 
         [0028]      FIG. 5  illustrates an example write operation for a ground biased register file (e.g.,  300 ). When discussing the write operation and the various signals associated therewith reference will be made to components of the ground biased register file  300  from  FIG. 3 . During non-writing periods (e.g., read, idol), the write wordline signals provided to the associated bit cells  305  and the write driver enable signal provided to the data input driver  310  are inactive and the write ground bias enable signal is active. The active write ground biased enable signal turns on the ground biased write control circuitry  315  which biases the write/writebar bitlines to ground. 
         [0029]    During a write period, the row decoder  355  completes a decoding process within a high phase of the clock. During the low phase of the clock, the appropriate write wordline signals and the write driver enable signal are turned ON and the write ground bias signal is turned OFF. The inactive write ground bias signal turns off the ground biased write control circuitry  315  so that the bitlines are not biased to ground and the active write driver enable signal enables the input latch  310  to power the appropriate write/writebar bitline to Vcc. The active write wordline and the active write/writebar bitline turn ON the bitcell passgates (e.g.,  150 ,  160 ) and the appropriate value is written to the bitcell  305 . If the same data is written to the same column during consecutive write cycles, the keeper  320  maintains the appropriate write/writebar bitline at the same voltage level as the previous cycle (no precharge is performed and GND-bias is OFF). Thus, memory consumes less write power as bitlines are not being charged or discharged. 
         [0030]    Although the disclosure has been illustrated by reference to specific embodiments, it will be apparent that the disclosure is not limited thereto as various changes and modifications may be made thereto without departing from the scope. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described therein is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment. 
         [0031]    The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.

Technology Category: 3