Patent Document

CROSS-REFERENCE TO RELATED APPLICATION(S) AND CLAIM OF PRIORITY 
       [0001]    The present application is related to U.S. Provisional Patent Application No. 61/204,023, filed Dec. 31, 2008, entitled “METHOD AND CIRCUIT FOR CANCELLING OUT COMPARATOR-DELAY IN THE RELAXATION OSCILLATOR.” Provisional Patent Application No. 61/204,023 is assigned to the assignee of the present application and is hereby incorporated by reference into the present application as if fully set forth herein. The present application hereby claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 61/204,023. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure is directed, in general, to resistive-capacitive relaxation oscillators, and more specifically, to canceling propagation delay within such an oscillator. 
       BACKGROUND 
       [0003]    Relaxation oscillators capable of generating a very precise and stable oscillation frequency may be implemented using stable resistive and capacitive components together with a threshold device, such that the capacitance charges gradually and discharges rapidly. The resonant frequency of a conventional resistive-capacitive (RC) relaxation oscillator is derived from a time constant based on the resistive and capacitive components. In relaxation oscillator embodiments utilizing a comparator, the comparator contributes to overall non-zero propagation delay and adds to the period of the oscillator output. However, the propagation delay of a comparator may vary with temperature, supply voltage, input slew rate, input bias levels, parasitic capacitance, process corners, and other variables. This limitation complicates generation of a precise and stable oscillation frequency in a comparator-based relaxation oscillator. 
         [0004]    One approach to achieving a very precise output frequency with a comparator-based relaxation oscillator is to make the comparator propagation delay negligibly small relative to the RC time constant. In addition to being difficult to implement, very fast comparators (with a proportionately small propagation delay) consume significant power. In addition, such very fast comparators typically require a very short channel (on the order of 0.18 microns) and high-speed complimentary metal-oxide-semiconductor (CMOS) technology. 
         [0005]    Rather than minimizing the magnitude of the comparator propagation delay to generate a precise relaxation oscillator output frequency, an alternative is to minimize temperature and voltage variation of the comparator&#39;s propagation delay and/or use trimming technology to reduce process variation. However, this approach limits the uppermost oscillation frequency achievable and adds to manufacturing expense. 
         [0006]    There is, therefore, a need in the art for improved implementation of comparator-based relaxation oscillators. 
       SUMMARY 
       [0007]    A relaxation oscillator includes a capacitor connected to a comparator input, current sources switched to supply power to the capacitor based on an output of the comparator, and a duplicate integrator shifting a voltage on the capacitor to offset a propagation delay through the comparator. The duplicate integrator includes current sources and a capacitor matching and switched in tandem with those within the relaxation oscillator, plus an additional current source, and is selectively switched into connection with the comparator input. By canceling the comparator propagation delay, the oscillator output frequency can be stably controlled through selection of resistive and capacitive values, using cheaper technology and tolerating large temperature, voltage and process variations. 
         [0008]    Before undertaking the DETAILED DESCRIPTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
           [0010]      FIG. 1  illustrates an integrated circuit device including a comparator-based relaxation oscillator with comparator propagation delay cancellation in accordance with one embodiment of the present disclosure; 
           [0011]      FIG. 2  is a simplified circuit diagram of a comparator-based relaxation oscillator; 
           [0012]      FIG. 2A  illustrates the voltages as a function of time at the inputs of the comparator within the comparator-based relaxation oscillator of  FIG. 2 ; and 
           [0013]      FIGS. 3A and 3B  illustrate comparator propagation delay cancellation within a comparator-based relaxation oscillator in accordance with one embodiment of the present disclosure; 
           [0014]      FIG. 4  is a circuit for generating a comparator propagation delay cancellation voltage within a comparator-based relaxation oscillator in accordance with one embodiment of the present disclosure; 
           [0015]      FIG. 4A  illustrates the capacitor voltage shift generated by the circuit of  FIG. 4 ; 
           [0016]      FIG. 5  is a simplified circuit diagram of a relaxation oscillator with comparator propagation delay cancellation in accordance with one embodiment of the present disclosure; 
           [0017]      FIGS. 5A and 5B  are comparative illustrations of the capacitor voltage and comparator output as a function of time for the circuit of  FIG. 5 ; and 
           [0018]      FIG. 6  is a set of timing diagrams for simulated operation of the circuit of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0019]      FIGS. 1 through 6 , discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system. 
         [0020]      FIG. 1  illustrates an integrated circuit device including a comparator-based relaxation oscillator with comparator propagation delay cancellation in accordance with one embodiment of the present disclosure. Integrated circuit device  100  includes processing circuitry  101 , such as encoding or decoding circuitry. A comparator-based relaxation oscillator  102  provides a reference frequency to processing circuitry  101 , for use in processing signals such as wireless communication signals or video data signals. A precise and stable reference frequency is provided by relaxation oscillator through comparator delay cancellation as described in further detail below. 
         [0021]    Those skilled in the art will recognize that the complete structure and operation of an integrated circuit device employing a relaxation oscillator is not depicted in  FIG. 1  or described herein. Instead, for simplicity and clarity, only so much of an integrated circuit device as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. In addition, although described in the context of an integrated circuit device, the principles of the present disclosure may be applied in other context, employing discrete components or the like. 
         [0022]      FIG. 2  is a simplified circuit diagram of a comparator-based relaxation oscillator. Current sources I 1  and I 2  each delivering a current I and switches SW 1  and SW 2  (which are switched in tandem) are connected in series between a power supply voltage and ground. A capacitor C 1  having a capacitance C is connected in parallel with current source I 2  and switch SW 2 , between ground and a node V cap . The capacitor C 1  is selectively charged and discharged by current sources I 1  and I 2  as a result of switches SW 1  and SW 2  being opened and closed. One input for a comparator  200  is connected to node V cap , and the other input is selectively connected to a reference voltage V ref  selectively switched between V high  and V low . When the reference voltage V ref  is V high , the capacitor C 1  is charging; when the reference voltage is V low , the capacitor C 1  is discharging. The intrinsic resistance within devices and connections provides the resistive component of the RC time delay. The output of the comparator  200  provides an output signal  201  for the oscillator, and a feedback signal  202  controls switching of the current sources I 1  and I 2  into and out of connection with capacitor C 1 . 
         [0023]      FIG. 2A  illustrates the voltages as a function of time at the inputs of the comparator  200  within the comparator-based relaxation oscillator of  FIG. 2 . The reference voltage V ref  at the negative input is switched at a predetermined period between V high  and V low  separated by a difference ΔV. As a result, the voltage V cap  across capacitor C 1  cycles with effectively the same period. However, the propagation delay T delay  through comparator  200  results in capacitor C 1  charging and discharging more than the voltage difference ΔV. This propagation delay is added into the period of the oscillator output, such that the period of the output signal  201  is: 
         [0000]      Period= CΔV/I+ 4 *T   delay , or  (1) 
         [0000]      Period= RC+ 4 *T   delay ,  (2) 
         [0000]    where RC is the time constant defined by the resistive and capacitive values of the circuit and can be made stable using current technology. However the propagation delay T delay  varies based on the factors described above, and introduces imprecision into the period of output signal  201 . Removing the propagation delay T delay  would allow the oscillator period to be defined solely by the resistive and capacitive values. Accordingly, instead of trying to control or minimize such propagation delay T delay , that delay time is extracted and compensated for using feedback. In that way, even when the comparator delay changes, that delay is always canceled out from the oscillator period. 
         [0024]      FIGS. 3A and 3B  illustrate comparator propagation delay cancellation within a comparator-based relaxation oscillator in accordance with one embodiment of the present disclosure. As illustrated in  FIG. 3A , the propagation delay T delay  causes the capacitor C 1  to excessively charge/discharge by a voltage V err  determined from: 
         [0000]        V   err =( I/C )* T   delay ,  (3) 
         [0000]    where the current I is the output of both current sources I 1  and I 2 . Over a half period, the resulting voltage difference is approximately ΔV+2*V err . To compensate for the propagation delay induced error, the voltage difference ΔV is adjusted to make a voltage swing on the capacitor C 1  be: 
         [0000]      Δ V   new =(Δ V− 2* V   err )  (4) 
         [0000]    As illustrated in  FIG. 3B , shifting the voltage on capacitor C 1  up/down by 2*V err  is equivalent to making ΔV new =(ΔV−2*V err ). 
         [0025]      FIG. 4  is a circuit for generating a comparator propagation delay cancellation voltage within a comparator-based relaxation oscillator in accordance with one embodiment of the present disclosure. Using current sources I 3  and I 4  matched to current sources I 1  and I 2  and a capacitor C 2  matched with capacitor C 1 , and switching switch SW 3  for a pulse duration T delay , a voltage V is generated having the value V err : 
         [0000]        V =( I/C )* T   delay .  (5) 
         [0000]    Since T delay  introduces V err , the exact same propagation delay T delay  is employed to regenerate V err  and compensate the voltage swing on node V cap .  FIG. 4A  illustrates the capacitor voltage shift generated by the circuit of  FIG. 4 . 
         [0026]      FIG. 5  is a simplified circuit diagram of a comparator-based relaxation oscillator with comparator propagation delay cancellation in accordance with one embodiment of the present disclosure. Relaxation oscillator  500  includes a main integrator  501  and a duplicate integrator  502 . Main integrator  501  includes current sources I 1  and I 2  each generating current I and switches SW 1  and SW 2  connected in series between a power supply voltage and ground. Main integrator  501  also includes a capacitor C 1  having capacitance C connected in parallel with current source I 2  and switch SW 2 , between node V cap  and ground. 
         [0027]    Duplicate integrator  502  includes current sources I 4  and I 5  each generating current I and switches SW 4  and SW 5  connected in series between the power supply voltage and ground, in parallel with current sources I 1  and I 2  and switches SW 1  and SW 2  and having a similar node V cap2 . Switches SW 1 , SW 2 , SW 4  and SW 5  are all switched in tandem. Duplicate integrator  502  also includes a capacitor C 2  having capacitance C connected in parallel with current source I 5  and switch SW 5 , between node V cap2  and ground. Duplicate integrator  502  further includes a current source I 3  generating current I and a switch SW 3  selectively connecting current source I 3  to node V cap2 . Another switch SW 6  selectively connects node V cap2  to node V cap . Switches SW 3  and SW 6  are switched in tandem. 
         [0028]    Node V cap  is connected to one input of comparator  503 , with the other comparator input switched between reference voltage V ref  values of V high  and V low , delayed relative to current source switching by switches SW 1 , SW 2 , SW 4  and SW 5  as described in further detail below. Logic  504  connected to the output of comparator  503  generates one signal  505  for controlling switches SW 1 , SW 2 , SW 4  and SW 5  (which is also the output of the relaxation oscillator) and a second signal  506  controlling switches SW 3  and SW 6 . Signal  506  has a pulse duration of T delay  recurring every half-period of the oscillation. 
         [0029]    Similar to the circuit of  FIG. 4  described above, duplicate integrator  502  generates a voltage shift for application to node V cap  to cancel comparator propagation delay and render the oscillator output frequency dependent solely on the resistive and capacitive values. Delay cancellation cannot be applied directly to the main integrator  501  while generating the T delay  pulse, or else the comparator  503  will see different slew rates on the input terminal, hence affecting T delay . Thus, in the exemplary embodiment of  FIG. 5 , a separate charging/discharging current and capacitor integrator  502  is employed to compensate for comparator propagation delay induced error. When the T delay  pulse is active, delay cancellation is enabled on the duplicate integrator  502  but not on the main integrator  501 . At the falling edge of the T delay  pulse, delay cancellation finishes and the charge on the duplicate integrator  502  is transferred to the main integrator  501 . The voltage at node V cap  of the main integrator  501  is then shifted up by an amount proportional to the T delay  pulse duration. Logic  504  delays V ref  switching as described below, and extracts the two T delay  pulses per period. 
         [0030]      FIGS. 5A and 5B  are comparative illustrations of the capacitor voltage and comparator output as a function of time for the circuit of  FIG. 5 . In  FIG. 5A , V ref  switching and current switching using switches SW 1 , SW 2 , SW 4  and SW 5  are synchronous. Transitions in capacitor voltage V cap  and V ref  input occur concurrently. To cancel comparator propagation delay, V ref  switching is delayed relative to transitions in the capacitor voltage by at least 2*T delay . 
         [0031]      FIG. 6  is a set of timing diagrams for simulated operation of the circuit of  FIG. 5 . Plot  610  illustrates the output of comparator  500 , including the 2*T delay  pulses. Plot  612  illustrates both the capacitor voltage V cap  (generally sawtooth waveform) and V ref  switching (square waveform). At the end of the T delay  pulse, the charge accumulated on the duplicate integrator  502  is transferred to the main integrator  501 , with the result that the capacitor voltage V cap  is shifted by an amount proportional to T delay . Plot  614  illustrates voltage V cap2  on capacitor C 2  of the duplicate integrator. Plot  616  illustrates the relaxation oscillator output, with delay-insensitive frequency. 
         [0032]    The precision of the all-silicon based oscillator  500  described above is not limited by the accuracy of the comparator&#39;s propagation delay, which can vary widely with temperature, voltage and process degrading performance. Comparator propagation delay may be as much as 25% of the desired oscillation period without affecting the output frequency of the relaxation oscillator. In addition, with comparator propagation delay cancellation, cheaper and slower CMOS technology is sufficient, translating into overall cost savings. 
         [0033]    “Real-time” delay compensation as described above renders the oscillator output frequency insensitive to comparator propagation delay. The circuit overhead is only the logic  504 , current sources I 3 , I 4  and I 5 , switches SW 5  and SW 6 , and integrating capacitor C 2 . In addition, relaxation oscillators are traditionally used as current-to-frequency converters, such that delay cancellation improves the current-to-frequency conversion accuracy and dynamic range. 
         [0034]    Although the above description is made in connection with specific exemplary embodiments, various changes and modifications will be apparent to and/or suggested by the present disclosure to those skilled in the art. Tt is intended that the present disclosure encompass all such changes and modifications as fall within the scope of the appended claims.

Technology Category: 5