Patent Document

BACKGROUND 
     The present disclosure relates generally to welding power supplies, and more particularly, to systems and methods for controlling current flow through an output load of a power control circuit. 
     Welding power supply circuits typically convert power from a primary source to an output suitable for welding operations. The output power is provided at an appropriate voltage or current level and may be controlled and regulated according to the process requirements. Some welding processes require the output to be AC. For instance, typical high current AC outputs for gas tungsten arc welding (GTAW) or submerged arc welding (SAW) may require circuitry that efficiently generates a square wave output with a magnitude of several hundreds of amperes. Typical circuit topologies designed to meet this need include a buck converter that steps down a supplied DC voltage, a full bridge inverter that converts the stepped down DC voltage to an AC output, and an output clamp circuit that suppresses output energy caused by parasitic output inductance from welding cables during output current reversal. 
     Since welding operations generally require high current levels and low voltage levels at the output, an important design criterion of typical welding and plasma cutting power supply circuits is the limitation of power losses in the circuit. However, it is now recognized that traditional power supply circuits include a combination of components (e.g., buck converter, full bridge inverter, and output clamp circuit) that typically contain multiple transistors and diodes, which greatly contribute to power losses in the circuit, leading to inefficiencies in the circuit design. Indeed, it is now recognized that there exists a need for circuits that reduce the power losses in the circuit and increase the efficiency of the welding power supply. 
     BRIEF DESCRIPTION 
     The present disclosure is directed to systems and methods relating to a power control circuit. One embodiment of the present disclosure efficiently achieves a desired square wave AC output by combining components of a buck converter and a full bridge inverter in a unique manner. In particular, the present disclosure provides methods and systems for creating and controlling an AC output for welding, plasma cutting or heating. For example, one embodiment of the present disclosure provides a power control circuit and current flow paths through the power control circuit that are generated via switching of transistors in the circuit on and off. Specifically, in one embodiment, the power control circuit includes a pulse width modulation leg, which controls the level of current flow through an inductor. Additionally, the power control circuit may include a bidirectional buck converter that converts an unregulated DC flow from a source to a regulated DC flow through the inductor. Further, the power control circuit may include a steering leg, which controls a direction of current flow through the inductor. In some embodiments, an output clamp circuit of the power control circuit may function to suppress the parasitic load inductance during polarity reversal. In other embodiments, if a voltage higher than the input voltage is not required to maintain the arc current during polarity reversal, then the output clamp circuit may be removed and an input leg may be used to suppress the parasitic load inductance during polarity reversal. 
    
    
     
       DRAWINGS 
       These and other features, aspects, and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings, wherein: 
         FIG. 1  illustrates an exemplary welding, cutting or heating power supply in accordance with aspects of the present disclosure; 
         FIG. 2  is a circuit diagram illustrating an exemplary embodiment of the output power control circuit of the welding power supply in accordance with aspects of the present disclosure; 
         FIG. 3  is a circuit diagram illustrating an exemplary embodiment of the output power control circuit with current flow established from left to right through the output load in accordance with aspects of the present disclosure; 
         FIG. 4  is a circuit diagram illustrating an exemplary embodiment of the output power control circuit with current flow freewheeling from left to right through the output load in accordance with aspects of the present disclosure; 
         FIG. 5  is a circuit diagram illustrating an exemplary embodiment of the output power control circuit with current flow established from right to left through the output load in accordance with aspects of the present disclosure; 
         FIG. 6  is a circuit diagram illustrating an exemplary embodiment of the output power control circuit with current flow freewheeling from right to left through the output load in accordance with aspects of the present disclosure; 
         FIG. 7  is a circuit diagram of an exemplary embodiment of the output power control circuit illustrating the first step of current reversal from left to right to right to left through the output load in accordance with aspects of the present disclosure; 
         FIG. 8  is a circuit diagram of an exemplary embodiment of the output power control circuit illustrating the second step of current reversal from left to right to right to left through the output load in accordance with aspects of the present disclosure; 
         FIG. 9  is a circuit diagram of an exemplary embodiment of the output power control circuit illustrating the first step of current reversal from right to left to left to right through the output load in accordance with aspects of the present disclosure; 
         FIG. 10  is a circuit diagram of an exemplary embodiment of the output power control circuit illustrating the second step of current reversal from right to left to left to right through the output load in accordance with aspects of the present disclosure; and 
         FIG. 11  is a graphical representation of exemplary waveforms generated during output power control circuit operation. 
         FIG. 12  is a circuit diagram illustrating an exemplary embodiment of the output power control circuit of the welding power supply in accordance with aspects of the present disclosure; 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates an exemplary welding, cutting or heating power supply  10 , which functions to power and control a welding, cutting or heating operation in accordance with aspects of the present disclosure. The power supply unit  10  in the illustrated embodiment contains a control panel  12  through which a user may control the supply of materials, such as power, gas flow, and so forth, to the welding, cutting or heating operation through knobs  14  or other panel components. The power supply  10  contains ports  16 , which may communicatively couple the power supply  10  to other system components, such as a torch, a work lead, a wall power outlet, and so forth. The portability of the unit  10  depends on a set of wheels  18 , which enable the user to easily move the power supply unit  10  to the location of a workpiece. 
       FIG. 2  is a circuit diagram illustrating one embodiment of an output power control circuit  20  of the welding power supply  10  in accordance with aspects of the present disclosure. The power control circuit  20  converts an unregulated DC input to a regulated AC output as needed for the welding, cutting or heating operation being performed. For instance, typical submerged arc welding (SAW) operations may require a regulated high current square wave output of several hundreds of amperes. However, primary power sources, such as a wall outlet, provide an unregulated AC output that is insufficient for a SAW operation. Therefore, it is now recognized that circuitry must convert the output of the primary power source to an output suitable for the welding, cutting or heating operation being performed. In operation, the power control circuit  20  illustrated in  FIG. 2  efficiently converts unregulated DC inputs to a first capacitor  22  from the primary power supply to regulated AC outputs for the welding, cutting or heating operation. In the following discussion, the power control circuit  20  illustrated in  FIG. 2  may be broken up into legs and sides for explanatory purposes. However, one skilled in the art would understand that the components of the circuit  20  may be arranged and/or grouped differently while retaining the overall function of the circuit  20 . 
     A pulse width modulation (PWM) leg  24  modulates current received from the first capacitor  22  such that the received unregulated DC current is converted to a regulated DC current. The PWM leg  24  includes a first transistor  26  and a first diode  28  coupled in parallel, a second transistor  30  and a second diode  32  coupled in parallel, an inductor  34 , and a first terminal  36  of an output  38 . The first transistor  26  and the first diode  28  may be positioned in between a first node  40  and a second node  42 . As illustrated in  FIG. 2 , the first node  40  may be located such that it is positioned on a first outer edge  41  of the circuit  20 . The second node  42  is located below the first outer edge  41  of the circuit  20  but above a second outer edge  43  of the circuit  20 . The second transistor  30  and the second diode  32  may be positioned in between the second node  42  and a third node  44 , which may be located such that it is positioned on the second outer edge  43  of the circuit  20 . The inductor  34  may be positioned in between the second node  42  and the first terminal  36  of the output  38  and parallel to the first outer edge  41  and the second outer edge  43  of the circuit  20 . 
     The PWM leg  24  alternates switching of the first transistor  26  or the second transistor  30  to increase or decrease current at the output  38  as dictated by the demands of the welding or plasma cutting operation. In some embodiments, the first transistor  26 , the second diode  32 , and the inductor  34  may be configured to function as a buck converter. Similarly, in some embodiments, the second transistor  30 , the first diode  28 , and the inductor  34  may be configured to function as a buck converter, transferring energy from an input to an output by storing and subsequently releasing energy in the inductor  34 . Taken together, the first transistor  26 , the first diode  28 , the second transistor  30 , the second diode  32 , and the inductor  34  may function as a bidirectional buck converter, which converts the DC voltage across the first capacitor  22  to a regulated DC current in the inductor  34 . 
     A steering leg  46 , which includes a third transistor  48  and a third diode  50  coupled in parallel and a fourth transistor  52  and a fourth diode  54  coupled in parallel, forms a half bridge inverter that determines the direction of current flow through the inductor  34 . The steering leg  46  is positioned between the first outer edge  41  and the second outer edge  43  of the circuit  20 . During operation, the steering leg  46  facilitates current flow either from right to left through the inductor  34  or from left to right through the inductor  34  by turning the third transistor  48  and the fourth transistor  52  on and off. The third transistor  48  and the third diode  50  may be positioned in between the first node  40  and a fourth node  56 . The fourth transistor  52  and the fourth diode  54  may be positioned in between the fourth node  56  and the third node  44  such that they exist in series with the first node  40 , which is positioned on the first outer edge  41  of the circuit  20 , and the fourth node  56 , which is positioned in between the first outer edge  41  of the circuit  20  and the second outer edge  43  of the circuit  20 . A second terminal  58  of the output  38  extending from the fourth node  56  in parallel with the first outer edge  41  and the second outer edge  43  of the circuit  20  may be configured to receive current from the steering leg  46 . 
     An output clamp leg  59  includes a second capacitor  60  that is configured to function as an output clamp circuit, which suppresses the energy in a parasitic output inductance of the welding or cutting cables during polarity reversal. The output clamp leg  59  is positioned between and connects the first outer edge  41  and the second outer edge  43  of the circuit  20 . In some embodiments, the capacity of the second capacitor  60  is much less than the capacity of the first capacitor  22 . In some embodiments, the peak current in the second capacitor  60  during polarity reversal may be the current in the inductor  34  and the parasitic output inductance of the welding or cutting cables. 
     An input leg  61  includes the first capacitor  22  and a blocking diode  62  arranged in series. As illustrated in  FIG. 2 , the blocking diode  62  may be positioned on the first outer edge  41  of the circuit  20  and the first capacitor  22  may be positioned in between the first outer edge  41  and the second outer edge  43  of the circuit  20 . The input leg  61  is positioned between the first outer edge  41  and the second outer edge  43  of the circuit  20 . The first capacitor  22  is configured to receive power from a primary power source that may include a line frequency step down transformer and a rectifier. The transformer may be single phase or three phase and may output 50 Hz or 60 Hz. The transformer may have multiple primary taps to accommodate multiple input voltages. The blocking diode  62  allows the second capacitor  60  to resonate with the series combination of the inductor  34  and the parasitic output inductance during polarity reversal as described in more detail below. 
       FIG. 3  is a circuit diagram illustrating an exemplary embodiment of the output power control circuit  20  with a current flow  64  established from left to right through the inductor  34  (i.e. state  1 ). To establish the left to right current flow  64  through the inductor  34 , the fourth transistor  52  is turned on, and the first transistor  26  is pulse width modulated to regulate the magnitude of the current through the inductor  34 . The forward path of current  64  originates from the first capacitor  22  and flows through the blocking diode  62 , the first node  40 , the first transistor  26 , the inductor  34 , the first terminal  36  of the output  38 , the output  38 , the second terminal  58  of the output  38 , the fourth node  56 , the fourth transistor  52 , the third node  44  and back to the first capacitor  22 . When the pulse width modulation of the first transistor  26  dictates that it is off, a freewheel current path  66 , as illustrated in  FIG. 4 , is established to allow the magnitude of the current flowing through the inductor  34  to decrease (i.e. state  2 ). The freewheel current path  66  flows from left to right through the inductor  34  and is through the second diode  32 , the second node  42 , the inductor  34 , the first terminal  36  of the output  38 , the output  38 , the second terminal  58  of the output  38 , the fourth node  56 , the fourth transistor  52 , and the third node  44 . The second transistor  30 , the first diode  28 , the third diode  50 , and the third transistor  48  are not used when DC current is flowing from left to right through the inductor  34 . 
       FIG. 5  is a circuit diagram illustrating an exemplary embodiment of the output power control circuit  20  with a current flow  68  established from right to left through the inductor  34  (i.e. state  5 ). To establish the right to left current flow  68  through the inductor  34 , the third transistor  48  is turned on, and the second transistor  30  is pulse width modulated to regulate the magnitude of the current through the inductor  34 . The forward path of current  68  originates from the first capacitor  22  and flows through the blocking diode  62 , the first node  40 , the third transistor  48 , the second terminal  58  of the output  38 , the output  38 , the first terminal  36  of the output  38 , the inductor  34  the second node  42 , the second transistor  30 , the third node  44  and back to the first capacitor  22 . When the pulse width modulation of the second transistor  30  dictates that it is off, a freewheel current path  70 , as illustrated in  FIG. 6 , is established to allow the magnitude of the current flowing through the inductor  34  to decrease (i.e. state  6 ). The freewheel current path  70  flows from right to left through the inductor  34  and is through the first diode  28 , the first node  40 , the third transistor  48 , the fourth node  56 , the second terminal  58  of the output  38 , the output  38 , the first terminal  36  of the output  38 , the inductor  34 , and the second node  42 . The first transistor  26 , the second diode  32 , the third diode  50 , and the fourth diode  54  are not used when DC current is flowing from right to left through the inductor  34 . 
     In some embodiments, once current flow has been established either in the left to right current path  64  or in the right to left current path  68  through the inductor  34 , the direction of the current flow may be reversed. For instance, if current flow has been established in the left to right current path  64  through the inductor  34 , the direction of the current flow can be reversed by turning all the transistors  26 ,  30 ,  48 ,  52  off. A first intermediate current flow path  72  illustrated in  FIG. 7  is established wherein the current continues to flow from left to right through the inductor  34  (i.e. state  3 ). The first intermediate current flow path  72  flows from the inductor  34  through the first terminal  36  of the output  38 , the output  38 , the second terminal of the output  58 , the fourth node  56 , the third diode  50 , the first node  40 , the second capacitor  60 , the third node  44 , the second diode  30 , and the second node  42 . The inductor  34  releases the energy it stored during the left to right current flow  64 , charging the second capacitor  60  to a voltage greater than the voltage of the first capacitor  22 , at which point the blocking diode  62  begins to block. The second transistor  30  and the third transistor  48  are turned on to allow the second capacitor to unload its energy back into the output load  38  and the inductor  34  after the current in the inductor  34  reaches zero. 
     When the current in the inductor  34  reaches zero, the voltage on the second capacitor  60  is at an upper limit. Subsequently, the energy built up in the second capacitor  60  will begin to discharge, reversing the direction of the current flow and establishing a current flow path  74  from right to left through the inductor  34 , as illustrated in  FIG. 8  (i.e. state  4 ). Since the second transistor  30  and the third transistor  48  have been turned on, current will flow from the second capacitor  60  through the first node  40 , the third transistor  48 , the fourth node  56 , the second terminal of the output  58 , the output  38 , the first terminal of the output  36 , the inductor  34 , the second transistor  30 , and the third node  44 . When the voltage on the second capacitor  60  discharges to the voltage on the first capacitor  22 , current flow will be established through the inductor  34  from right to left at approximately the same magnitude as prior to polarity reversal, slightly reduced by circuit losses. Subsequently, the third transistor  48  remains on and the second transistor  30  is pulse width modulated to regulate the current flow through the inductor  34  and reestablish the current path from right to left as previously shown in  FIG. 5 . 
     Once current flow has been reestablished in the right to left current path  68  through the inductor  34 , the direction of the current flow can be reversed by turning all the transistors  26 ,  30 ,  48 ,  52  off. A first intermediate current flow path  76  illustrated in  FIG. 9  is established wherein the current continues to flow from right to left through the inductor  34  (i.e. state  7 ). The first intermediate current flow path  76  flows from the inductor  34  through the second node  42 , the first diode  28 , the first node  40 , the second capacitor  60 , the third node  44 , the fourth diode  54 , the fourth node  56 , the second terminal  58  of the output  38 , the output  38 , and the first terminal of the output  36 . The inductor  34  releases the energy it stored during the right to left current flow  68 , charging the second capacitor  60  to a voltage greater than the voltage of the first capacitor  22 , at which point the blocking diode  62  begins to block. The first transistor  26  and the fourth transistor  52  are turned on to allow the second capacitor to unload its energy back into the output load  38  and the inductor  34  after the current in the inductor  34  reaches zero. 
     When the current in the inductor  34  reaches zero, the voltage on the second capacitor  60  is at an upper limit. Subsequently, the energy built up in the second capacitor  60  will begin to discharge, reversing the direction of the current flow and establishing a current flow path  78  from left to right through the inductor  34 , as illustrated in  FIG. 10  (i.e. state  8 ). Since the first transistor  26  and the fourth transistor  52  have been turned on, current will flow from the second capacitor  60  through the first node  40 , the first transistor  26 , the second node  42 , the inductor  34 , the first terminal of the output  36 , the output  38 , the second terminal of the output  58 , the fourth node  56 , the fourth transistor  52 , and the third node  44 . When the voltage on the second capacitor  60  discharges to the voltage on the first capacitor  22 , current flow will be established through the inductor  34  from left to right at approximately the same magnitude as prior to polarity reversal, slightly reduced by circuit losses. Subsequently, the fourth transistor  52  remains on and the first transistor  26  is pulse width modulated to regulate the current flow through the inductor  34  and reestablish the current path from left to right as previously shown in  FIG. 3 . 
       FIG. 11  illustrates exemplary current and voltage waveforms generated during control circuit operation. In particular,  FIG. 11  illustrates an inductor current waveform  80 , a second capacitor voltage waveform  82 , a first transistor voltage waveform  84 , a second transistor voltage waveform  86 , a third transistor voltage waveform  88 , and a fourth transistor voltage waveform  90 . From an initial time  92  to a later time  94 , the circuit  20  is switching between state  1  and state  2  to maintain the current at the output  38  at 1000 A flowing from left to right through the inductor  34  as previously described with respect to  FIGS. 3-4 . The fourth transistor  52  is on in both states  1  and  2  while the first transistor  26  is on in state  1  and off in state  2 . A current at the output  38  appears to be a constant 1000 A but is actually increasing a few amps in state  1  and decreasing a few amps in state  2 . From a time  94  to a later time  96 , the circuit  20  remains exclusively in state  2 , the fourth transistor  52  is the only transistor on, and the current at the output  38  is decreasing. 
     At the time  96 , the fourth transistor  52  is turned off, and the circuit  20  is in state  3  as previously described with respect to  FIG. 7 . The second transistor  30  and the third transistor  48  are turned on in state  3  even though the current flow path is through the second diode  32  and the third diode  50 . During state  3 , the current at the output  38  rapidly decreases while the voltage on the second capacitor  60  increases. Subsequently, at a later time  98 , the current at the output  38  reverses, and the voltage on the second capacitor  60  is at an upper limit. At the time  98 , the circuit  20  enters state  4 , as previously described with respect to  FIG. 8 . The current at the output  38  increases rapidly through the second capacitor  60 , the second transistor  30 , and the third transistor  48 . The voltage on the second capacitor  60  begins to decrease. 
     Subsequently, at an approximate later time  100 , the current at the output  38  has reversed and is flowing from right to left through the inductor  34 . The voltage on the second capacitor  60  has reached its initial condition. From the approximate time  100  to an approximate time  102 , the circuit  20  is in state  5 , as previously described with respect to  FIG. 5 . The second transistor  30  and the third transistor  48  are on, and the current at the output  38  increases. At the time  102 , the current at the output  38  has reached 1000 A and is flowing from right to left through the inductor  34 . The circuit  20  is switching between states  5  and  6  to maintain the output current at 1000 A as previously described with respect to  FIGS. 5-6 . The second transistor  30  is on in state  5  while the current at the output is increasing a few amps. 
     From a time  104  to a later time  106 , the circuit  20  is in state  6  as previously described with respect to  FIG. 6 . The third transistor  48  is on, the second transistor  30  is off, and the current at the output is decreasing a few amps. At the time  106 , the third transistor  48  turns off, and the circuit is in state  7  as previously described with respect to  FIG. 9 . The first transistor  26  and the fourth transistor  52  turn on in state  7  even though the current flow is through the first diode  28  and the fourth diode  54 . During state  7 , the current at the output  38  rapidly decreases, while the voltage on the second capacitor  60  increases. At an approximate later time  108 , the current at the output  38  reverses, and the voltage on the second capacitor  60  is at an upper limit. At the time  108 , the circuit  20  enters state  8  as previously described with respect to  FIG. 10 . The current at the output increases rapidly through the second capacitor  60 , the first transistor  26 , and the fourth transistor  52 . The voltage on the second capacitor  60  begins to decrease. 
     At an approximate time  110 , the current at the output  38  has reversed, and current flow is from left to right through the inductor  34  while the voltage on the second capacitor  60  has reached its initial condition. From the approximate time  110  to an approximate time  112 , the circuit  20  returns to state  1 , wherein the first transistor  26  and the fourth transistor  52  are on, and the current at the output  38  increases. At the approximate time  112 , the current at the output  38  has reached 1000 A flowing from left to right through the inductor  34 , and the circuit  20  is switching between states  1  and  2  to maintain the output current at 1000 A. In the illustrated exemplary operation, the above described sequence of states repeats for the next 10 mS cycle (i.e. 100 Hz frequency) of current at the output  38 . 
       FIG. 12  is a circuit diagram illustrating a further embodiment of the output power control circuit  20  of  FIG. 2 . It is well known to those skilled in the art that certain welding processes, such as AC GTAW, require a voltage of approximately 200 volts or more during polarity reversal to maintain current flow and prevent arc rectification. Other process, such as AC SAW, may not require this high voltage during polarity reversal, and the embodiment of the output power control circuit  20  illustrated in  FIG. 12  may be used. In such processes, the output clamp leg  59 , which includes the second capacitor  60  that is configured to function as the output clamp circuit  59  in the embodiment illustrated in  FIG. 2 , may be eliminated from the output power control circuit  20 . Additionally, if the capacitor  60  is eliminated from the output clamp circuit  20 , then the blocking diode  62 , which was part of the input leg  61  in  FIG. 2 , is no longer required. Accordingly, in the illustrated embodiment, the output current flows through the capacitor  22  of the input leg  61  during polarity reversal, and the output voltage is clamped to the voltage on capacitor  22 . 
     While only certain features of the present disclosure have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the present disclosure.

Technology Category: b