Patent Document

[0001]    This is a continuation of application Ser. No. 13/763,624 filed Feb. 9, 2013. application Ser. No. 13/763,624 is hereby incorporated by reference in its entirety. 
     
    
     FIELD OF INVENTION 
       [0002]    This invention relates to switching circuits. More specifically, effectively switching on and off a capacitor or capacitor bank within a closed system in response to measured load imbalance and harmonic distortion that utilizes master slave relationships with a closed electronic system. This invention is applicable to arc welding, magnetizing materials, and switching capacitors no list only three applications via a novel means. 
       BACKGROUND 
       [0003]    In a typical power line capacitor switching system application, electrical parameters of the power drawn is measured using integrated circuits, the parameter also indicating the reactive power by a load and then communicating via a switching device to a capacitor bank which thereby attempts to match the load of a power line at an designated signal value or by calculated measured factor ratio. Traditionally electronic switches attempt to switch high-energy loads at the voltage zero point crossing meaning where the line voltage crosses through the neutral line wherein the voltage equals zero. The state of the art today and for the past several decades has been to use switch circuits that require a certain amount of current to bias their base and this current is typically induce by the line voltage. Consequently, it is impossible to turn the switch on exactly at the zero crossing of the line voltage. 
         [0004]    Currently, there are no effective means or methods for correcting for imbalance or harmonic distortion within industrial and commercial settings. The current state of the art calculates a signal value of reactive power drawn by the load or calculated from a ratio of an active power value and converted to presumed power value. Under these two methods there is a problem to overcome. In the case of a 208, 3 phase AC line, the peak voltage of the line will be approximately 300 volts. The minimum voltage of the line will be approximately 300 volts and any voltage undischarged from the capacitor will be added to the line voltage and consequently the switching voltage will be as much as two times that of the line voltage. Under these applications both switches and capacitors are damaged and frequent replacements are the common practice. Currently there are no high energy power line capacitor switching systems that match the voltage of the capacitor to the line voltage at the time the switch contact is made, how the capacitor can be discharged rapidly so that it can to switched on rapidly, or that guarantees that the capacitor is kept in its discharge mode in the event of a power loss. 
         [0005]    The ever-increasing demand for electrical energy has triggered a search for greater efforts to attain higher efficiency in every aspect of this industry. The costs for generating as well as for electricity have risen as demand has increased. Many efforts to increase efficiency, reduce consumption, and mitigate delivery costs have been developed and implemented to this end. 
         [0006]    Most importantly, the state of the current art is focused on addressing power factor correction or in common parlance, reducing KVAR. Our invention is focused on correcting for load imbalance and harmonic distortion commonly known as KW. 
         [0007]    Thus there is a need in the art for a novel, dynamic capacitor switching system to correct for load imbalance and harmonic distortion. 
         [0008]    The present invention describes a novel and dramatically more efficient point to locate and implement the switching circuit. This current invention teaches that the optimum timing of the switching circuit is in the second quadrant of the Alternate Power line circle. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention provides a novel means for measuring the negative energy within a closed AC electronic system that will correct for load imbalance and harmonic distortion. As part of this novel means the system itself can designate master slave relationships within the closed system to facilitate the safe transfer of energy from a source to a load while overcoming the deficiencies of conventional circuit protection and correction devices. 
         [0010]    The present embodiments provide, among other features and benefits, significant advances in the control of power conversion, obtaining high power factor at low loads. A brief summary of various illustrative example embodiments is presented. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit the scope of the invention. Detailed descriptions of a preferred exemplary embodiment adequate to allow those of ordinary skill in the art to make and use the inventive concepts will follow in later sections. 
         [0011]    Various embodiments relate to methods of controlling power delivered from the main source to a load by an imbalance correcting system which utilizes a novel switch that enables a system previously not achievable to address KW meaning both load imbalance and harmonic distortion. The load imbalance correcting system receives an alternating-current (AC) voltage as an input, wherein the mains AC voltage has an absolute voltage value varying in a cyclic manner from a zero to a zero over a cycle period. The switch unique to this system locates point between 90 degrees and 180 degrees (second quadrant) of the voltage and current AC waveform and syncs the voltage and the current as both cross the zero point. 
         [0012]    Among features and benefits provided by the various embodiments, this ability to synchronize the zero crossing of the voltage and the current in the second quadrant of the AC waveform the current delivery to the load provides substantially improved imbalance correction of AC voltage. 
         [0013]    Thus, the scope of the disclosed invention should be determined by the appended claims and their legal equivalents, rather than the examples given. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The present invention may be more fully understood by one of skill in the art with references being had to the following detailed description of several preferred embodiments, taken in conjunction with the accompanying drawings wherein like elements are designated by identical reference numbers throughout several views and in which: 
           [0015]      FIG. 1  is a graphical representation illustrating a typical phase 3 system; 
           [0016]      FIG. 2  is a graphical representation illustrating a phase 3 system implementing the current invention; 
           [0017]      FIG. 3 a    is a schematic diagram of an exemplary control circuitry in an imbalance factor corrector; 
           [0018]      FIG. 3 b    is a schematic diagram of an exemplary control circuitry in an imbalance factor corrector; 
           [0019]      FIG. 3 c    is a schematic diagram of an exemplary control circuitry in an imbalance factor corrector; 
           [0020]      FIG. 4 a    is a schematic diagram of an exemplary control circuitry in an imbalance factor corrector; 
           [0021]      FIG. 4 b    is a schematic diagram of an exemplary control circuitry in an imbalance factor corrector; 
           [0022]      FIG. 5 a    is a schematic diagram of an exemplary control circuitry in an imbalance factor corrector; and 
           [0023]      FIG. 5 b    is a schematic diagram of an exemplary control circuitry in an imbalance factor corrector. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]      FIG. 1  is a graphical depiction, which shows a phase diagram of the statures of the panel before any correction is made by implementing the current invention. This figure specifically shows the relative phase relationship between all voltages and currents in a typical phase 3 system. The solid red line represents imbalance current in neutral line. It is produced by vector sum of all currents involved. The red dots of capacitor phase lines indicate the maximum and minimum amount of capacitance that is allowed for the panel. These limits will assure the stability of the system so it does not create harmonics and will produce minimum acceptable phase correction. 
         [0025]      FIG. 2  is a graphical depiction, which shows the correction achieved by implementing the current invention. The thick purple lines indicate the amount of capacitance applied to each phase. The red line indicating the neutral current in  FIG. 1  has disappeared indicating there is no more current being wasted in neutral line. The lack of current in the neutral line indicates that the system has been balanced. 
         [0026]      FIG. 3 a    Shows a schematic diagram of the Main Board. A current from VDD  1  passes through resistor R 22 . Some of the current passing through resistor R 22  passes through resistor R 26  and to capacitor C 13 . Capacitor are also referred to as output means and switching power means. Capacitor C 13  and resistor R 26  are connected in parallel to one another. The current passing through resistor  26  passes into capacitor C 16  and capacitor C 17  respectively. Some of the current passing through capacitor C 16  passes onto COM. Some of the current passing through capacitor C 16  and capacitor C 17  passes to processor U 1  via NC 4 . Input from HPF 1  pass through resistor R 38  to processor U 2  via HPF 2 . Processor U 1  send an output current from Dgnd  21  and NC 19  to COM. Processor U 1  sends an output current from NEG-SDO  20  through resistor R 42  to Meter_Data_Out. Processor U 1  receives a current from Meter Clock at OSCI  17 . A current passes from AMP 1  passing through resistor R 48  and is received by the Processor U 1  via G 0   16 . Processor is also referred to a controller in the specification as well as the Claims. A current passes from AMP 2  passing through resistor R 39  and is received by the Processor U 1  via G 1   15 . A current passes from Master_CS_ 1  passing through resistor R 51  and is received by the Processor U 2  via F 0 −/CS  14 . A current passes from Master_SOO passing through resistor R 37  and is received by the Processor U 1  via F 1 -SDI  13 . A current passes from Master_SCO passing through resistor R 31  and is received by the Processor U 1  via F 2 -SCK  12 . A current passes from Meter_Reset passing through resistor R 32  and is received by the Processor U 1  via/MCLR  9 . A current leaves processor U 1  via Agnd  11  and passes through capacitors C 23 , COM, and capacitor C 15  respectively. Some of the current passing through capacitors C 23  and C 15  are received by processor U 1  via Ref_in/out  10 . A current passes from L 1  Main through resistor Z 2 , resistor R 7 , resistor R 16  resistor R 19  and resistor R 25  respectively Current passing through resistor Z 2 , resistor R 7 , resistor R 16  resistor R 19  and resistor R 25  passes into COM. Resistor Z 2 , resistor R 7 , resistor R 16  resistor R 19  and resistor R 25  are connected in series. The current passing through resistor R 16  passes into capacitor C 7 . The current passing through Capacitor C 7  passes into capacitor C 1 , to Com, and to processor U 1  at CH 1   7 , respectively. Some current passing through resistor R 16  and resistor R 19  passes to AC_Line_Sync. A current from Common passes through Bead  21 , resistor R 1 , resistor R 3 , and resistor R 2 , respectively. A current from L 2 _Main passes through Bead Z 3 , resistor R 7 , Resistor R 16 . Some of the current passing through resistor R 16  passes to resistor  19 , to capacitor C 7 , and to AC_Line_Sync, respectively. A current from common passed through bead Z 1 . Some of the current passing through Bead Z 1  passes to resistor R 1 , resistor R 3  and resistor R 2  respectively. The current passing through resistor R 1  passes to capacitor C 1 , COM, and to CH 1   7 . Some current passing through resistor R 20  passes to capacitor C 10  and AC_Line_PH 1 . The current passing through AC_Line_PH 2  passes to processor U 1  via CH 1 +  8 . The current passing through capacitor C 11  passes to COM. Some current passing through capacitor C 1  passes to capacitor C 7 . Some current passing through capacitor C 7  passes to processor U 1  at CH 1 −  7 . Some current passing through capacitor C 7  and the current passing through resistor R 1  from Common pass into capacitor C 1 . Some of the current that passes through capacitor C 1  passes through resistor R 9  and into processor U 1  at CH 0 −  6 , respectively. The current passing through resistor R 9  passes through resistor R 5  and CN 2   4 . A current from CT 1  passes through resistor R 8  and through resistor R 5 , respectively. The current passing through resistor R 8  passes into capacitor C 4  and some current passes to processor U 1  via Cho+  5 . The current passing through capacitor C 4  passes to COM. The current passing from Common passes through resistor R 3  into capacitor C 8 . The current passing through capacitor C 8  passes through resistor R 20 . A current from VDD  2  passes through resistor R 23 . Some of the current passing through resistor R 23  passes through resistor R 28  and to capacitor C 14 . Capacitor C 14  and resistor R 28  are connected in parallel to one another. The current passing through resistor  28  passes into capacitor C 21 , capacitor C 20 , and to processor U 2  via Dvdd  1 , respectively. Some of the current passing through resistor R 28  and capacitor C 20  passes onto COM. Some of the current passing through resistor R 23  and capacitor C 14  passes to processor U 2  via NC  4 . Input from HPF  2  pass through resistor R 41  to processor U 2  via HPF 1 . Processor U 2  send an output current from Dgnd  21  and NC 19  to COM respectively. Processor U 2  sends an output current from NEG-SDO  20  through resistor R 46  to Meter_Data_Out. Processor U 2  receives a current from Meter Clock at OSCI  17 . A current passes from AMP 1  passing through resistor R 50  and is received by the Processor U 2  via G 0   16 . A current passes from AMP 2  passing through resistor R 46  and is received by the Processor U 2  via G 1   15 . A current passes from Master_CS_ 2  passing through resistor R 53  and is received by the Processor U 2  via F 0 −/CS  14 . A current passes from Master_SOO passing through resistor R 40  and is received by the Processor U 2  via F 1 -SDI  13 . A current passes from Master_SCO passing through resistor R 33  and is received by the Processor U 2  via F 2 -SCK  12 . A current passes from Meter_Reset passing through resistor R 34  and is received by the Processor U 2  via/MCLR  9 . A current leaves processor U 2  via Agnd  11  and passes through capacitors C 26 , COM, and capacitor C 19  respectively. Some of the current passing through capacitors C 26  and C 19  are received by processor U 2  via Ref_in/out  10 . A current passes from L 2  Main through resistor Z 4 , resistor R 14 , and resistor R 17 . Some of the current passing through resistor R  17  passes through capacitor C 8  and resistor R 20  respectively. The current passing through capacitor C 8  passes through resistor R 3 . The current passing through resistor R 3  passes to processor U 2  via Ch 1 −  7 . Some of the current passing through resistor R 20  passes to capacitor C 11 , to resistor R 20 , and to processor U 2  via AC_Line_PH 2 , respectively. The current passing through Capacitor C 11  passes to COM. Current from processor U 2  from CHO−  6  passes to capacitor C 3  and to resistor R 13  respectively. The current passing through resistor R 13  passes though resistor R 6 . The current passing through resistor R 6  passes through resistor R 12  then to capacitor C 2  and the processor via CHO−  5 . The current passing through capacitor C 2  passes to COM. Some current passing through resistor R 12  passes to CN 3   1  and  3 . Current passing through resistor R 6  enter CN 3  via pin  4 . A current from VDD  3  passes through resistor R 24 . Some of the current passing through resistor R 24  passes through resistor R 30  and to capacitor C 18 . Capacitor C 18  and resistor R 30  are connected in parallel to one another. The current passing through resistor  30  passes into capacitor C 25 , capacitor C 24 , and to processor U 3  via Dvdd  1 , respectively. Some of the current passing through resistor R 30  and capacitor C 24  passes onto COM. Some of the current passing through resistor R 24  and capacitor C 18  passes to processor U 2  via NC  4 . Input from HPF  2  pass through resistor R 45  to processor U 2  via HPF 1 . Processor U 3  send an output current from Dgnd  21  and NC 19  to COM respectively. Processor U 3  sends an output current from NEG-SDO  20  through resistor R 49  to Meter_Data_Out. Processor U 3  receives a current from Meter Clock at OSCI  17 . A current passes from AMP 1  passing through resistor R 52  and is received by the Processor U 2  via G 0   16 . A current passes from AMP 2  passing through resistor R 47  and is received by the Processor U 3  via G 1   15 . A current passes from Master_CS_ 3  passing through resistor R 54  and is received by the Processor U 3  via F 0 −/CS  14 . A current passes from Master_SOO passing through resistor R 44  and is received by the Processor U 3  via F 1 -SDI  13 . A current passes from Master_SCO passing through resistor R 35  and is received by the Processor U 3  via F 2 -SCK  12 . A current passes from Meter_Reset passing through resistor R 36  and is received by the Processor U 3  via/MCLR  9 . A current leaves processor U 3  via Agnd  11  and passes through capacitors C 22 , COM, and capacitor C 27  respectively. Some of the current passing through capacitors C 22  and C 27  are received by processor U 3  via Ref_in/out  10 . A current passes from L 3  Main through resistor Z 4 , resistor R 15 , and resistor R 18 . Some of the current passing through resistor R  18  passes through capacitor  19  and resistor R 21  respectively. Some of the current passing through resistor R 21  passes to capacitor C 12 , to resistor R 29 , and to processor U 2  via AC_Line_PH 3 , respectively. The current passing through resistor R 29  passes to COM. Some of the current passing through capacitor C 9  passes to resistor R 2 , capacitor C 6  and to processor U 3  via Common_GND, respectively. Current passing through capacitor C 6  passes to COM, resistor R 11  and to processor U 3  respectively. Some current passing through resistor R 11  passes to resistor R 4  and to CN 1  at pins  2  and  4  respectively. Some current passing through resistor R 4  passes to resistor R 19  and to CN 1  at pins  1  and  3 . The current passing through resistor R 10  passes into capacitor C 5  and the processor via CHO+  5 . 
         [0027]      FIG. 3 b    Shows a schematic diagram of the Main Board. A current from 3.3V_Aux and from CN 4  pin  1  passes through resistor R 55  to capacitor C 28  and through resistor R 56 . Some of the current passing through resistor R 56  passes to CN 4  via pin  2  and to processor U 4  via MCLR  18 . The current passing through capacitor C 28  to COM. A current from processor U 4  from AVDD  17 , VDD  40 , VDD  28 , pass through resistor R 57  and capacitor C 31 , capacitor C 32 , capacitor C 35  and capacitor C 36  respectively. A current from processor U 4  via VCAP  7  to capacitor C 30 . The current passing through capacitor C 30 , capacitor C 31 , capacitor C 32 , capacitor C 35 , and capacitor C 36  flow to COM. The current passing through resistor R 57  passes to capacitor C 29 . Some of the current passing through capacitor C 29  passes to CN 4  pin  5  and to COM. CN 4  receives a signal at pin  3  from processor U 4  from pin  21  Meter_PGC. A signal from processor U 4  from pin  22  Meter_PGD is received at CN 4  at pin  4 . Some of the current from AC_LINE_SYNC passed through resistor R 97  and enters processor U 4  via pin  24  AN 5 /Cin+/RP 3 /CN 7 /RB 3  and to capacitor C 51  respectively. A current from COMP_FB passes through resistor R 98  and passes to capacitor C 51  and to processor U 4  at pin  24  AN %/C 1 in+/RP 3 /CN 7 /RB 3 . The current passing through capacitor C 51  passes to COM. A signal from Meter_Clock passes to processor U 4  at SCL 1 /RP 8 /CN 22 /PMD 4 /RB 8  at  44 . A signal from Meter_RESET passes to processor U 4  at DA 1 /RP 9 /CN 21 /PMD 3 /RB 9  at pin  1 . A signal from Master_CS_ 1  passes to processor U 4  at PGED 2 /EMCD 2 /RP 10 /CN 16 /PMD 2 /RB 10  at pin  8 . A signal from Master_CS_ 2  passes to processor U 4  at PGEC 2 /RP 11 /CN 15 /PMD 1 /RB 11  at pin  9 . A signal from Master_CS_ 3  passes to processor U 4  at AN 12 /RP 12 /CN 14 /PMD 0 /RB 12  at pin  10 . A signal from HPF 1  passes to processor U 4  at AN 11 /RP 13 /CN 13 /PMRD/RB 13  at pin  11 . A signal from AMP 1  passes to processor U 4  at AN 10 /RP 14 /CN 12 /PMWR/RB 14  at pin  14 . A signal from AMP 2  passes to processor U 4  at AN 9 /RP 15 /CN 11 /PMCS/RB 15  at pin  15 . A signal from Meter_DATA_OUT passes to processor U 4  at Interface Board. RP 22 /CN 18 /PMA 1 /RC 6  at pin  2 . A signal from Master_SCO passes to processor U 4  at interface board. RP 23 /CN 17 /PMA 0 /RC 7  at pin  3 . A signal from Master_SOO passes to processor U 4  at RP 24 /CN 20 /PMA 50 /RC 8  at pin  4 . A current passes from processor U 4  from AVSS at pin  16 , VSS at pin  6 , VSS at pin  29  and VSS pin  39  to COM. Processor U 4  sends a signal via SOSCO/T 1 CK/CN 0 /RA  4  at pin  34  to interface board. Processor U 4  sends a signal via SOSCI/RP 4 /CN 1 /RB  4  at pin  35  to interface board. Processor U 4  sends a signal via OSC 1 /CLK 1 /CN 30 /RA  2  at pin  30  to capacitor C 34  and CR 1  respectively. The current passing through capacitor C 34  passes to COM. Processor U 4  sends a signal via OSC 2 /CLK 0 /CN 29 /RA  3  at pin  31  to capacitor C 33  and CR 1  respectively. The current passing through capacitor C 34  passes to COM. Processor U 4  sends a signal via TCK/PMA 7 /RA  7  at pin  13  to interface board. Processor U 4  sends a signal via TD 0 /PMA 8 /RA  8  at pin  32  to interface board. Processor U 4  sends a signal via TD 1 /PMA 9 /RA  9  at pin  35  to interface board. Processor U 4  sends a signal via TMS/PMA 10 /RA  10  at pin  12  to interface board. Processor U 4  sends a signal via RP 19 /CN 28 /PMBE/RC 3  at pin  36  to COMP_Fb and to resistor R 60  respectively. The current passing through resistor R 60  passes to optoisolator U 6 . Optoisolator also means opto coupler and in the claims is referred to as sensing means. Current passing through optoisolator U 6  passes to COM and to resistor R 61 . A current passing through 3.3V_Main passes into optoisolator and passing through optoisolator U 6  passes through resistor R 61  and to processor U 4  via PH 1 _SIG. Processor U 4  sends a signal via RP 20 /CN 25 /PMA 4 /RC 4  at pin  37  to resistor R 59 . The current passing through resistor R 59  passes to Inductive coupler U 5  at pin  3 . An induced current from the current passing via pin  3  sends a current to Meter_OUT_Micro. Processor U 4  receives an induced current from Inductive coupler U 5  via RP 21 /CN 26 /PMA 3 /RC 5  at pin  38  as the induced current passes through resistor R 58 . The induced current passes into inductive coupler U 5  from Micro_OUT_Meter. Processor U 4  sends a signal via PGED 3 /ASDA 1 /RP 5 /CN 27 /PMD 7 /RB 5  at pin  41  to interface board. Processor U 4  sends a signal via PGEC 3 /ASCL 1 /RP 6 /CN 24 /PMD 6 /RB 6  at pin  42  to interface board. Processor U 4  sends a signal via INT 0 /RP 7 /CN 23 /PMD 5 /RB 7  at pin  43  to interface board. 
         [0028]      FIG. 3 c    Shows a schematic diagram of the Main Board. A current from 3.3V Main passes through resistor R 76 , resistor R 68 , and Program at pin  1 , respectively. Current passes from processor U 7  from VDD pin  2 , VDD  16 , VDD  37 , VDD  46 , VDD  52  and passes through resistor R 68 , EN VREG  86  and to Program at pin  2 . Some of the current passing through resistor R 68  passes to capacitor C 41  and also to resistor R 72  respectively. Some of the current passing through resistor R 72  passes to Program at pin  2  and to processor U 7  via MCLR at  13 . Some of the current that passes through resistor R 76  passes to capacitor C 44  and to processor  47  via Avdd pin  30 . Processor U 7  receives a current signal via INT 0 /RP 7 /CN 23 /PMD 5 /RB 7  at pin  43  to interface board. A current passes from processor RPI 38 /RC 1  at  6  and passes to interface board. A current passes from processor RPI 39 /RC 2  at  7  and passes to interface board. A current passes from processor RP 40 /RC 3  at  6  and passes to interface board. A current is received by processor U 7  from PH 1 _SIC at RP 141 /RC 4  at  9 . A current passes from +5_AUX through resistor R 62  and. The current passing through resistor R 62  then passes through resistor R 63 , capacitor C 37  and along line 12V_Ref to processor U 7  via C 1 ND/RP 21 /RG 6  at pin  10 . A current from Meter_OUT_Micro_IN passes through R 73  along line RX 2  to processor U 7  at C 2 IND/RP 19 /RG 8  at pin  12 . A current from MORO_OUT_Micro_IN passes through R 71  along line TX 2  to processor U 7  at C 2 INC/RP 27 /RG 9  at pin  14 . A current from 3.3V_Main passes through resistor R 66  and resistor R 67 , respectively. Current passing through resistor R 66  passes to diode D 1  along line METER_LINK_LED to processor U 7  at RP 133 /RE 8   18 . Current passing through resistor  67  passes through diode D 2  along line SUB_LINK_LED to processor U 7  at TCK/RA 1  at pin  38 . A current from 3.3V_MAIN passes through diode D 3  along line INTERFACE_LINK_LED to resistor R 75 . The current passing through resistor R 75  passes to processor U 7  at AN 13 /CTEDG 1 /RB 13  at pin  42 . Processor U 7  receives a current passing through resistor R 69  passing along line/from PGC at PGEC 1 /AN 1 /RP 1 /RB 1  at pin  24 . Processor U 7  receives a current passing through resistor R 74 . Some of the current passing through resistor R 74  passes along line/from PCD at PGED 1 /AN 0 /RP 0 /RB 0  pin  25  and to processor U 7  at pin  11  C 1 NC/RP 26 /RG 7 . Processor U 7  receives a current passing along line from PS_12V_CHECK at AN 2 /RP 13 /RB 2  at pin  23 . Processor U 7  receives a current passing through resistor R 70  passes along line/from EX_AMP_TEMP_DETECT at AN 4 /RB 3  at  22 . Processor U 7  receives a current passes along line/from INT_AMP_TEMP_DETECT at AN 4 /RB 3  at  21 . Processor U 7  receives a current passing along line/from PS_5V_CHECK at AN 5 /RP 18 /Rb 5  at  20 . Processor U 7  receives a current passing along line/from TMS/RA 0  at pin  17 . Processor U 7  receives a current passing along line/from RP 134 /RE 9  at pin  19 . Processor U 7  receives a current passing along line/from Vref−/RA 9  at pin  28 . Processor U 7  receives a current passing along line/from Vref−/RA 10  at pin  29 . Processor U 7  receives a current passing along line/from PGEC 2 /AN 6 /RP 6 /RB 6  at pin  26 . Processor U 7  receives a current passing along line/from PGED 2 /AN 7 /RP 7  at pin  27 . Processor U 7  receives a current passing along line/from AN 8 /RP 8 /RB 8  at pin  32 . Processor U 7  receives a current passing along line/from AN 10 /CVREF/RB 10  at pin  34 . Processor U 7  receives a current passing along line/from AN 9 /RP 9 /RB 9  at pin  33 . Processor U 7  receives a current passing along line/from AN 11 /RB 11  at pin  35 . Processor U 7  receives a current passing along line/from AN 12 /CTEDG 2 /RB 12  at pin  41 . Processor U 7  receives a current passing along line/from AN 14 /CTPLS/RP 14 /RB 14  at pin  43 . Processor U 7  receives a current passing along line/from AN 15 /REF 0 /RP 29 /RB 15  at pin  44 . Processor U 7  receives a current passing along line/SUB_POWER_CTRL from RP 31 /RF 13  at pin  39 . A current passes from RP 132 /RF 12  pin  40  of Processor U 7  through resistor R 95  along line SUB_CLOCK. A current passes from RP 16 USB 10 /RF 3  pin  51  of Processor U 7  through resistor R 77  along line SUB_CLOCK. Processor U 7  receives a current passing along line/from VBUS/RF 7  at pin  54 . Processor U 7  receives a current passing along line/from VUSB at pin  55 . Processor U 7  receives a current passing along line/from D−/RG 3  at pin  56 . Processor U 7  receives a current passing along line/from D+/RG 2  at pin  57 . A current passes from U 7  via SOS/RC 13  pin  73  to capacitor C 42  and crystal CR 3 . A current passes from U 7  via SOSCO/RP 137 /RC 14  pin  74  to capacitor C 43  and crystal CR 3 , respectively. A current passes from U 7  via OSC 1 /CLKIN/RC 12  pin  63  to capacitor C 39  and crystal CR 2 , respectively. A current passes from U 7  via OSC 2 /CLK 0 /RC 15  pin  64  to capacitor C 39  and crystal CR 2 , respectively. A current passes from Processor U 7  at AVSS pin  31 , VSS pin  15 , VSS pin  36 , VSS pin  45 , VSS pin  65 , VSS pin  75  and VCAP at pin  85 , respectively. Some of the current passes from VCAP pin  85  passes to capacitor C 46  and to capacitor C 45  respectively. A current from +5V passes into CN 6  at pin  10 . Current passes from CN 1  pin  9  to processor U 7  via SDA 3 /RE 7  at pin 5 . Current passes from CN 1  pin  8  to processor U 7  via SCL 3 /RE 6  at pin  4 . Current passes from CN 1  pin  7  to processor U 7  via RE 6  at pin  3 . Current passes from CN 6  pin  6  to processor U 7  via RE 4  at pin  100 . Current passes from CN 6  pin  5  to processor U 7  via RE 3  at pin  99 . Current passes from CN 6  pin  4  to processor U 7  via RE 2  at pin  98 . Current passes from CN 6  pin  3  to processor U 7  via RE 1  at pin  94 . Current passes from CN 6  pin  2  to processor U 7  via RE 0  at pin  93 . A current passes from U 7  via RG 15  pin  1  to interface board. A current passes from U 7  via RG 14  pin  95  to interface board. A current passes from U 7  via RG 12  pin  96  to interface board. A current passes from U 7  via AN 22 /RA 7  pin  92  to interface board. A current passes from U 7  via AN 23 /RA 6  pin  91  to interface board. A current passes from U 7  via RG 1  pin  89  to interface board. A current passes from U 7  via RG 0  pin  90  to interface board. A current passes from U 7  via VCMPST 2 /SESSVLD/RF 1  pin  88  to interface board. A current passes from U 7  via VBUSSTVBUSVLD/RF 1  pin  87  to interface board. A current passes from U 7  via C 3 INA/RD 7  pin  84  to MAC IC U 8  CE pin  1 . A current passes from U 7  via C 3 INB/RD 6  pin  83  to MAC IC U 8  WP pin  3 . A current passes from U 7  via RP 20 /RD 5  pin  82  to MAC IC U 8  SO pin  2 . A current passes from U 7  via RP 25 /RD 4  pin  81  to MAC IC U 8  SI pin  5 . A current passes from U 7  via RP 22 /RD 3  pin  78  to MAC IC U 8  SCK pin  6 . A current passes from U 7  via DPH/RP 23 /RD 2  pin  77  to MAC IC U 8  HOLD pin  7 . Some current passing from MAC IC U 8  VDD pin  8  to capacitor C 48  and through resistor R 89 , respectively. Some current from 3.3V_Main passes to capacitor C 48  and resistor R 89 , respectively. Some current passes through resistor R 89  to NPN transistor Q 2 . Some of the current passing through NPN transistor Q 2  passes through resistor R 85  and to CN 10  pin  3 . CN 10  links to interface board. The current passing through resistor R 85  communicates with processor U 7  via line MAIN_REO_TO_INTF to RD 13  pin  80 . Processor U 7  pin  79  communicates to CN 10  U 8  via line MAIN_REO_FROM_INTF at pin  3 . A current from CN 10  pin  4  passes through resistor R 81  along line MAIN_SCK. The current passing from CN 10  pin  4  passes through resistor R 81  passes to processor U 7  via RP 12 /RD 11  at pin  71 . The current passing from CN 10  via pin  5  passes through resistor R 86  via line MAIN_SD 1  and passes to processor U 7  via RP 3 /RD 10  at pin  70 . CN 10  from pin  5  communicates to processor U 7  via line MAIN_SD 0 . Current from CN 10  passes through resistor R 82  to U 7  DPLN/RP 4 /RD 9  pin  69 . A current passes from U 7  via DLMN/RTCC/RP 2 /RD 8  pin  50  to interface board. A current passes from U 7  via RP 17 /RF 5  pin  50  to interface board. A current passes from U 7  via RP 10 /RF 4  pin  49  to interface board. Current from a +12V power source passes to relay safety switch K 1 . When relay safety switch is closed the current passes to connector CN 9  via pin  9  and connector CN 11  via pin  9 , respectively. A current from line SUB_POWER_CTRL passes through resistor R 93  to NPN transistor Q 3 . Some current passing through NPN transistor Q 3  passes to capacitor C 50  and to relay safety switch K 1 . The current passing from capacitor C 50  passes to relay safety switch K 1 . Current from capacitor C 50  passes to connector CN 9  via pin  9  and connector CN 11  via pin  9 , respectively. The current from connector relay safety switch K 1  passes through CN 11  via pin  1  and passes from pin  1  to connector CN 9  at pin  1  and then to connector CN 8  pin  1 . Connector CN 11 , connector CN 9  and connector CN 8  are connected in series. A current received at pin  1  of connector CN 8  passes to pin  9  of connector CN 8 . The current from relay safety switch K 1  passes through connector CN 11  pin  2  to connector CN 9  pin  2  and then to connector CN 8  pin  2 . Some of the current passing through pin  2  of connector CN 8  passes through resistor R 83  and to NPN transistor Q 1 . The current passing from NPN transistor Q 1  passes to resistor R 78  and then to processor U 7  along line ROST_OUT_SUB_Boards to RP 5 /RD 15  pin  48 . The current passing through resistor R 83  passes to processor U 7  along line ROST_in_SUB_Boards to RP 143 /RD 14  pin  47 . The current from relay safety switch K 1  passes through connector CN 11  pin  3  to connector CN 9  pin  3  and then to connector CN 8  pin  3 . The current passing through pin  3  of connector CN 8  passes through resistor R 79  along line TX_SUB_Boards to RP 15 /RF 8  of processor U 7  via pin  53 . The current from relay safety switch K 1  passes through connector CN 11  pin  4  to connector CN 9  pin  4  and then to connector CN 8  pin  4 . The current passing through pin  7  of connector CN 8  passes through resistor R 80  along line RX_SUB_Boards to RP 30 /RF 2  of processor U 7  via pin  52 . The current from relay safety switch K 1  passes through connector CN 11  pin  5  to connector CN 9  pin  5  and then to connector CN 8  pin  5 . The current passing through pin  5  of connector CN 8  passes along line PH 1 _SIC to interface board. The current from relay safety switch K 1  passes through connector CN 11  pin  6  to connector CN 9  pin  6  and then to connector CN 8  pin  6 . The current passing through pin  6  of connector CN 8  passes along line SUB_CLOCK to interface board. The current from relay safety switch K 1  passes through connector CN 11  pin  7  to connector CN 9  pin  7  and then to connector CN 8  pin  7 . The current passing through pin  7  of connector CN 8  passes along line SUB_RESET to interface board. The current from relay safety switch K 1  passes through connector CN 11  pin  8  to connector CN 9  pin  8  and then to connector CN 8  pin  8 . The current passing through connector CN 11  at pin  8  passes to pin  10  of connector CN 11 . The current passing through connector CN 9  at pin  8  passes to pin  10  of connector CN 9 . Some of the current passing through connector CN 8  at pin  8  passes to pin  10  of connector CN 8  and to ground. 
         [0029]    The Main Board. Connector CN 19  and connector C 21  communicate to daughter boards  1  and  2  (not shown) via line L 3 _main. Connector CN 14  and connector CN 18  communicate to daughter boards  3  and  4  (not shown) via line L 2 _main. Connector CN 13 , and connector CN 17  communicate to daughter boards  3  and  4  (not shown) via line L 1 _main. A 12V power source passes some current to capacitor C 52 , resistor R 94 , MOV 1  and to connector CN 20  at pin  2 , respectively. Some of the current passing through MOV 1  passes to connector CN 20  at pin  1  and to ground. The current passing through resistor R 94  passes to capacitor C 53  and to voltage regulator U 11 . The voltage passing through voltage regulator U 11  passes to ground and to capacitor C 56  respectively. A 5V power source provide a current hat passes to capacitor C 56  and to voltage regulator U 13 . The current passing through voltage regulator U 13  passes to capacitor C 58 . The current passing thorough capacitor C 56  and capacitor C 58  pass to connector CN  20  at pin 1 . A 3.3V power source provides a current that passes to capacitor C 58 . Current for 3.3V_Main passes to capacitor C 60 , capacitor C 61 , capacitor C 62 , capacitor C 63 , capacitor C 64 , and capacitor C 65 , respectively. Capacitor C 60 , capacitor C 61 , capacitor C 62 , capacitor C 63 , capacitor C 64 , and capacitor C 65  and connected in parallel and provide current to the system. 
         [0030]      FIGS. 4 a  and 4 b    are schematic diagrams of the interface board. The interface processing chip U 4  receives and process all the information received from the main board and the daughter board. Processor U 8  receives a charge of 3.3 volts to power its LED display readout at pin  8 . Processor U 8  possesses a read-only memory that retains its data when the power is turned off and that can be electronically erased and reprogrammed. Processor U 8  receives a signal from Flash-hid at pin  7 . Processor U 8  receives a signal from flash_clk at pin  6 . Processor Flash_CE receives a signal from pin  1 . Processor U 8  receives a signal from Flash_MSDI at pin  2 . Processor U 8  receives a signal from MSD 0  at pin  5 . Processor U 8  receives a signal from Flash_WP at pin  3 . Processor U 8  releases a charge (VSS) at pin  4 . Interface board contains two opto couplers, U 2  and U 3  respectively. An power source sends a 5 volt charge to opto coupler U 3 , opto coupler U 2  and to capacitor C 1 , respectively. Capacitor C 1  has a storage capacity able to draw off a portion of the charge provided by the 5 volt power source. Both opto couplers U 3  and U 2  redirect the incoming charge to capacitors C 2  and C 1  respectively. Capacitors C 2  an C 3  are designed to draw of a portion of the line charge to achieve a reduction of charge resulting in to auxiliary powers source each possessing 3.3 volt. In each redirection the resultant 3.3 volts passes to a power source provide an auxiliary power source. The voltage difference is redistributed throughout the dual opto coupler circuit. Opto coupler U 3  is electrically connected to opto coupler U 2  hence work in conjunction to achieve a reduction line charge. A 5 volt power source provides a bi-directional charge to Interface Board link at pin and to diode D 8 . The charge exiting D 8  proceeds to resistor R 16 . The exiting charge from diode D 8  proceeds bi-directionally to diode D 11  and to capacitor C 26  Diode D 14 , and to power source B 1 , respectively. The charge at D 11  proceeds to pin  2  of interface board link CN 1 . Interface board link CN 1  sends a signal from pin  3  bi-directionally to transistor Q 4  and resistor R 12  respectively. The charge exiting transistor Q 4  proceeds to resistor R 11 . The charge exiting resister R 11  proceeds to RJ 5  of the interface processor U 4 . The charge exiting resistor R 12  proceeds to RB 0  of the interface processor U 4 . Interface board link sends a signal from pin  4  to resistor R 13 . The charge exiting resistor R 13  proceeds to RC 3  of the interface processor. Interface processor sends a signal from RC 5  to resister R 10 . The exiting signal proceeds to pin  5  of the interface board link. Interface board link CN 1  sends a signal from pin  6  to resistor R 9 . The exiting charge proceeds to RC 4  of the interface processor U 4 . A 5 v powers source provides a VCC charge to processor U 5 . Processor U 5  receives a signal from RS232-TX at RI in Processor U 5  sends a signal to interface processor U 4  from RS232_RX. A 5 v power source provides a charge that proceeds bi-directionally to capacitor C 24  and capacitor C 23  respectively. The charge exiting capacitor C 24  proceeds bi-directionally to resistor  24  and to capacitor C 20  respectively. The charge exiting resistor R 24  proceeds to RS232 COM  1 . The charge exiting capacitor C 20  proceeds to Processor U 5 . A 3.3 v power source proceeds a charge that proceeds bi-directionally to resistor R % and pin  1  of program respectively. The charge exiting resistor R 5  proceeds bi-directionally to resistor R 8  and capacitor C 5 , respectively. The charge exiting resistor R 8  proceeds bi-directionally to pin  2  of program and MCLR of interface processor U 5 . Program sends and receives signal from the interface processor U 5  via pin  3  of Program and RB 7  of interface processor U 5  respectively. Program sends and receives signal from the interface processor U 5  via pin  4  of Program and RB 8  of interface processor U 4  respectively. A positive power sources at VDD  62 , VDD  17 , VDD  37 , VDD  37 , VDD 59 , VDD  86 , AVDD  30 , and Envreg  39  provide a charge that proceeds to capacitors C 10 , C 9 , C 7 , and C 6  respectively. A charge from program exits program at pin  5  and proceeds to capacitors C 6 , C 7 , C 9 , and C 10  respectively. Interface processor U 4  sends a positive power charge from VDDPLL  81 , VDDTX  76 , and VDDRX to capacitors C 11  and C 12  respectively. Display RS sends a signal to resistor R 27 . The exiting signal proceeds to the Interface processor U 4  and said signal is received at RH 3 . Display RW sends a signal to resistor R 28 . The exiting signal proceeds to the Interface processor U 4  and said signal is received at RE 1 . Display Enable sends a signal to resistor R 29 . The exiting signal proceeds to the Interface processor U 4  and said signal is received at Reo. Interface Processor U 4  sends a signal to Display  1  contrast from RC 2  the signal exiting RC 2  proceeds to resistor R 30 . The signal exiting R 30  bi-directionally proceeds to capacitor C 25  and Display 1 , respectively. Display 1   07  sends a signal to resistor R 32 . The exiting signal proceeds to interface processor U 4  and said signal is received at RF 7 . Display 1   06  sends a signal to resistor R 33 . The exiting signal proceeds to interface processor U 4  and said signal is received at RF 6 . Display  05  sends a signal to resistor R 34 . The exiting signal proceeds to interface processor U 4  and said signal is received at RF 5 . Display 1   04  sends a signal to resistor R 35 . The exiting signal proceeds to interface processor U 4  and said signal is received at RF 4 . Display 1   03  sends a signal to resistor R 36 . The exiting signal proceeds to interface processor U 4  and said signal is received at RF 3 . Display 1   02  sends a signal to resistor R 37 . The exiting signal proceeds to interface processor U 4  and said signal is received at RF 2 . Display 1   01  sends a signal to resistor R 38 . The exiting signal proceeds to interface processor U 4  and said signal is received at Display 1   0   o  sends a signal to resistor R 39 . The exiting signal proceeds to interface processor U 4  and said signal is received at RF 0 . Interface processor U 4  receives a signal from SC Unit LED_x 1  at RH 1 . Interface processor U 4  receives a signal from Sc Unit LED_x 0  at RH 0 . Interface processor U 4  receives a signal from SC Unit LED_x 6  at RE 2 . Interface processor U 4  receives a signal from SC Unit LED_x 7  at RE 3 . Interface processor U 4  receives a signal from SC Unit LED_x 8  at RE 4 . Interface processor U 4  receives a signal from SC Unit LED_x 9  at RE 5 . Interface processor U 4  receives a signal from SC Unit LED_x 10  at RE 6 . Interface processor U 4  receives a signal from SC Unit LED_x 11  at RE 7 . Interface processor U 4  receives a signal from SC Unit LED_x 2  at RD 0 . Interface processor U 4  receives a signal from SC Unit LED_x 3  at RD 1 . Interface processor U 4  receives a signal from SC Unit LED_x 4  at RD 2 . Interface processor U 4  receives a signal from SC Unit LED_x 5  at RD 3 . Interface processor U 4  receives a signal from MSDO at RD 4 . Interface processor U 4  receives a signal from Flash MSD 1  at RD 5 . Interface processor U 4  receives a signal from Flash_CLK at RD 6 . Interface processor U 4  receives a signal from Flash-Hold at RD 7 . Interface processor U 4  receives a signal from SC Unit LED_y 3  at RJ 4 . Interface processor U 4  receives a signal from SC Unit LED_y 2  at RJ 3 . Interface processor U 4  receives a signal from SC Unit LED_y 1  at RJ 2 . Interface processor U 4  receives a signal from Flash_WP at RB 5 . Interface processor U 4  receives a signal from Flash_CE at RB 4 . Interface processor U 4  sends a signal that proceeds directly to resistor R 14  RC 6 . The signal exiting resistor R 14  proceeds to RS232 TX. RS232 sends a signal to resistor R 15 . The signal exiting resistor R 15  proceeds to RC 7  of the interface processor U 4 . 
         [0031]      FIGS. 5 a  and 5 b    show a schematic representation of daughter board  1  wherein L 1   2 , L 2   3 , and L 3   4  convey a signal to said daughter board  1  from interfacing board  6  via connector  5 . Display  7  shows a readout of time, date, current, voltage, power factor, power harmonics, imbalance, capacitance device to list several functions for illustration purposes only. Said display  7  is shows information from a menu (not shown) that is selected via manual selection using press buttons  12 ,  13 ,  14 , and  15 . Display  7  receives signals from said press buttons  12 ,  13 ,  14 , and  15  respectively via  4  capacitor/resistors  8 ,  9 ,  10 , and  11  respectively. Said capacitor/resistors  8 ,  9 ,  10 , and  11  and connected to and receive signal from 4 press buttons  12 ,  13 ,  14 , and  15  respectively. LED array  16  is configured to indicate 8 individual indicators  17 ,  18 ,  19 ,  20 ,  21 ,  22 ,  23 ,  24 , and  25  respectively. Said indicators  17 ,  18 ,  19 ,  20 ,  21 ,  22 ,  23 ,  24 , and  25  are connected so that when capacitance is applied on any particular daughter board a corresponding pair of indicators will emit a light. An IP LED detector  26  is connected to the daughter board  1  and emits a light when capacitance is applied. Sender link Led  27  is connected to daughter board  1  and said Sender link Led emits a light when a signal is being sent from said daughter board  1  in the event capacitance is being applied. Status Led  28  is connected to daughter board  1  and flashes in the event a signal is being received. Link LED  29  is connected to said daughter board  1  and emits a flashing light when a link to an outside data collection unit has been established. Interface processor  9  receives signals from and sends signals to main board  30  via the interface board  31 . 232 port  32  is connected to the daughter board  1  and allows communication to the system for calibration, upgrades to illustrate two of many functions only. CatV  34  is connected to daughter board  1  and allows communication with the facility as well as to other units. Said communication may include but is not limited to relationship designation, energy demands to list two options for illustration purposes only. Battery  35  is an internal energy source that protects the integrity of the unit in the event of a power outage and maintains date and time to list two functions for the purpose of illustration only.

Technology Category: 5