Patent Document

BACKGROUND  
         [0001]    This invention relates generally to semiconductor memories and, particularly, to flash memories.  
           [0002]    Flash memories typically use a one transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Commonly flash memory is provided in densities that come in standard multiples of a given density. For example, flash memory may be provided in multiples of 32 megabits. Some users may prefer to have an interim density or a density between two successive multiples, such as 48 megabits.  
           [0003]    Flash memories generally come in either top boot or bottom boot configurations. The parameters utilized for the booting process in a bottom boot configuration are allocated to the lowest addressable addresses of the flash array. In the top boot configuration, those parameters are allocated to the highest addressable addresses.  
           [0004]    To enable an interim density, normally bottom boot flash is utilized. In such case, the interim density may be easily implemented by disabling or locking a memory block (or blocks) associated with the highest (or higher) addressable addresses. In this way, the locked block(s) do not in any way interfere with access to the booting parameters that are stored in the lowest addressable addresses.  
           [0005]    A problem arises in providing interim densities with top boot flash memories since the boot parameters are located in precisely the same blocks that would be disabled, normally, to produce the interim density.  
           [0006]    Thus, there is a need for a way to enable interim densities in top boot flash memories. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1 is a block depiction of one embodiment of the present invention;  
         [0008]    [0008]FIG. 2 illustrates the operation of the selectably inverting buffer shown in FIG. 1 in accordance with one embodiment of the present invention; and  
         [0009]    [0009]FIG. 3 is a block diagram of a system according to one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0010]    Referring to FIG. 1, a flash memory  10  may receive an external address  12  and an enable  14  that may be a chip enable or chip enable bar signal. Those signals are provided to a selectably inverting buffer  16 . The buffer  16  may selectably invert one or more signals to generate an internal address  18  from the external address  12 .  
         [0011]    Generally, the flash memory  10  may be designed to a default configuration of either a top or bottom boot configuration. Then, as desired by the end user, the buffer  16  may be programmed to convert external addresses to internal addresses to generate either a top boot or a bottom boot architecture as desired. For example, the buffer  16  may include selectively openable fuses that either insert or remove an inverter gate in one embodiment. In one embodiment, if the default configuration is a top boot architecture, and if a bottom boot architecture is desired, the external address may be inverted. If a top boot architecture is the default configuration and a top boot architecture is the desired configuration, no inversion may occur.  
         [0012]    The inversion of the external address to form the internal address changes the order of decoding the block addresses to implement the desired architecture. In other words, in one architecture, the boot parameters may be located at the highest addressable addresses and, in another architecture, they may be located in the lowest addressable addresses. The same external address signals may be utilized, but through the operation of the buffer  16 , those external signals may be translated for the desired configuration.  
         [0013]    The internal address  18  is then provided to a block selector  20 . The block selector may use the most significant bit (MSB) of the internal address to access the appropriate blocks within a memory array  22  in one embodiment. Generally, a block may be one of a series of equally sized portions or sectors of flash memory array  22 .  
         [0014]    The operation of the buffer  16  is illustrated in FIG. 2. In the embodiment illustrated, the upper most block  24   a , having the most significant bits [ 11 ], is locked. By locked, it is intended to refer to the situation where both writing to and reading from the block is prevented.  
         [0015]    In such case, the boot parameters  26  (indicated as a shaded region within the block  24   b  having the most significant bits [ 10 ]) are located at the highest addressable address. This is consistent with the conventional top boot block architecture. However, those addresses may be converted to internal addresses consistent with a default bottom boot architecture.  
         [0016]    In such case, an external address  12  directed to the locked block  24   a  is converted by buffer  16  to an internal address  18  having most significant bits [ 01 ], as indicated as block  24   g . Similarly, the block  24   b  is converted to become the block  24   h  and the boot parameters  26  are provided in the internal address  18  as the lowest addressable addresses, as indicated at  26 . Likewise, the block  24   c  addresses are converted by buffer  16  to address the block  24   e , which has the highest addressable internal address and the block  24   d  becomes the block  24   f , which has the second highest addressable addresses.  
         [0017]    Thus, instead of the top block from the memory space being locked, buffer  16 -may convert addresses and lock a different memory block. In addition, the address inversion is removed with respect to the second most significant bit (MSB-1) and replaced with a system in which the locked block is situated above the lowest addressable block and the parameters are provided in the next lowest internal addressable block. For example, as shown in FIG. 2, the most significant external address bit (e.g., one for blocks  24   a  and  24   b  and zero for blocks  24   c  and  24   d ) is inverted but the second most significant bit (one for blocks  24   a  and  24   c  and zero for blocks  24   b  and  24   d ) is not inverted.  
         [0018]    Thus, an interim density may be achieved in a top boot flash memory without jeopardizing any performance aspects or introducing greater complexity into the design process, in some embodiments. Particularly, without inserting extra circuitry in the critical signal path, performance may be substantially unchanged or even improved in some cases. With a simple logic functionality, design changes may be reduced in terms of complexity, incremental die size and validation effort.  
         [0019]    While the embodiment is illustrated in which the interim density is a quarter of the increment between successive densities, any lockable amount of density is possible in accordance with some embodiments of the present invention. Moreover, while an architecture is illustrated in which the default configuration is a bottom boot architecture, flash memories that have a default top boot architecture may be implemented in some embodiments of the present invention.  
         [0020]    Referring to FIG. 3, a processor-based system  30 , in one embodiment, may be a wireless processor-based system. In other words, the system  30  may communicate with other devices through a wireless interface  48  over an appropriate wireless protocol, such as a short range wireless protocol or a cellular telephone protocol, to mention two examples. The system  30  may include a processor  32  coupled by an interface  34  to a bus  38  and a system memory  36 .  
         [0021]    The bus  38 , in turn, may be coupled to one or more bus devices  40  and another interface  42 . In one embodiment, the interface  42  may be coupled to still another bus  44 . The bus  44  may couple the flash memory  10 , which in one embodiment may store the system boot parameters that are part of the basic input/output system (BIOS). The bus  44  may also couple to a serial input/output (SIO) interface  46  that, in turn, is connected to a wireless interface  48 .  
         [0022]    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Technology Category: 3