Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to field emission display (FED) devices. More particularly, this invention relates to methods and apparatuses for improving beamlet uniformity in FED devices. 
     2. Description of the Related Art 
     Field emission display (FED) devices are an alternative to cathode ray tube (CRT) and liquid crystal display (LCD) devices for computer displays. CRT devices tend to be bulky with high power consumption. While LCD devices may be lighter in weight with lower power consumption relative to CRT devices, they tend to provide poor contrast with a limited angular display range. FED devices provide good contrast and wide angular display range and are lightweight with low power consumption. An FED device typically includes an array of pixels, wherein each pixel includes one or more cathode/anode pairs. Thus, it is convenient to use the terms “column” and “row” when referring to individual pixels or columns or rows within the array. 
     FIG. 1 illustrates a portion of an FED device  10  produced in accordance with conventional micro-tipped cathode structure. The FED device  10  includes a faceplate  12  and a baseplate  20 , separated by spacers  32 . The spacers  32  support the FED device  10  structurally when the region  34  in between the faceplate  12  and the baseplate  20  is evacuated. The faceplate  12  includes a glass substrate  14 , a transparent conductive anode layer  16  and a cathodoluminescent layer or phosphor layer  18 . The phosphor layer  18  may include any known phosphor material capable of emitting photons in response to bombardment by electrons. 
     The baseplate  20  includes a substrate  22  with a row electrode  24 , a plurality of micro-tipped cathodes  26 , a dielectric layer  28  and a column-gate electrode  30 . The baseplate  20  is formed by depositing the row electrode  24  on the substrate  22 . The row electrode  24  is electrically connected to a row of micro-tipped cathodes  26 . The dielectric layer  28  is deposited upon the row electrode  24 . A column-gate electrode  30  is deposited upon the dielectric layer  28  and acts as a gate electrode for the operation of the FED device  10 . 
     The substrate  22  may be comprised of glass. The micro-tipped cathodes  26  may be formed of a metal such as molybdenum, or a semiconductor material such as silicon, or a combination of molybdenum and silicon. Micro-tipped cathodes  26  may also be formed with a conductive metal layer (not shown) formed thereon. The conductive metal layer may be comprised of any well-known low work function material. 
     The FED device  10  operates by the application of an electrical potential between the column electrode  30  or gate electrode  30  and the row electrode  24  causing field emission of electrons  36  from the micro-tipped cathode  26  to the phosphor layer  18 . The electrical potential is typically a DC voltage of between about 30 and 110 volts. The transparent conductive anode layer  16  may also be biased (1-2 kV) to strengthen the electron field emission and to gather the emitted electrons toward the phosphor layer  18 . The electrons  36  bombarding the phosphor layer  18  excite individual phosphors  38 , resulting in visible light seen through the glass substrate  14 . 
     The micro-tipped cathodes  26  of FED device  10  are 3-dimensional structures which may be formed as evaporated metal cones or etched silicon tips. Micro-tipped cathodes  26  provide enhanced electric field strength by about a factor of four or five over the 2-dimensional structure of the 2-dimensional alternative FED device  40  (see FIG.  2 ). However, the 2-dimensional structure of the alternative FED device  40  can be formed with planar films and photolithography. 
     Referring to FIG. 2, a portion of an alternative FED device  40  is shown in accordance with conventional flat cathode structure. FED device  40  includes a faceplate  42  and a baseplate  50  separated by spacers (not shown for clarity). The faceplate  42  may include a glass substrate  44 , a transparent conductive anode layer  46  disposed over the glass substrate  44 , and a phosphor layer  48  disposed over transparent conductive anode layer  46 . An electrical potential of between about one kilovolts to about two kilovolts may be applied to the transparent conductive anode layer  46  to enhance field emission of electrons and to gather emitted electrons at the phosphor layer  48 . 
     The baseplate  50  may include a substrate  52 , a conductive layer  54 , a flat cathode emitter  56 , a dielectric layer  58  and a grid electrode  60 . The conductive layer  54  may be a row electrode  54  and is deposited on the substrate  52 . The flat cathode emitter  56  and dielectric layer  58  are deposited on the conductive layer  54 . The grid electrode  60  may also be referred to as the column electrode  60 . The grid electrode  60  is deposited over, and supported by, the dielectric layer  58 . The flat cathode emitter  56  may comprise a low effective work function material such as amorphic diamond. 
     Several techniques have been proposed to control the brightness and gray scale range of FED devices. For example, U.S. Pat. No. 5,103,144 to Dunham, U.S. Pat. No. 5,656,892 to Zimlich et al. and U.S. Pat. 5,856,812 to Hush et al., incorporated herein by reference, teach methods for controlling the brightness and luminance of flat panel displays. However, even using these brightness control techniques, it is still very difficult to obtain a uniform electron beam from an FED emitter. Thus, there remains a need for methods and apparatuses for controlling FED beam uniformity. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention includes a field emitter circuit including a row electrode, at least one cathode structure on the row electrode, a grid electrode proximate to the at least one cathode structure and an electron beam uniformity circuit coupled to the grid electrode for providing a grid voltage sufficient to induce electron emission from the at least one cathode structure and with a periodically varying signal to provide electron beam uniformity. 
     A field emission display (FED) embodiment of the invention includes a faceplate, a baseplate and a circuit for controlling electron beam uniformity. The faceplate of this embodiment may include a transparent screen, a cathodoluminescent layer and a transparent conductive anode layer disposed between the transparent screen and the cathodoluminescent layer. The baseplate of this embodiment may include an insulating substrate, a row electrode disposed on the insulating substrate, a cathode structure disposed on the row electrode, an insulating layer disposed around the cathode structure and on the row electrode, and a column electrode disposed upon the insulating layer and proximate to the cathode structure. The cathode structure of this embodiment may be micro-tipped. In another embodiment, the cathode structure may be flat. The circuit for controlling electron beam uniformity provides a grid voltage including a periodic signal superimposed on a DC offset voltage. The DC offset voltage is sufficient to induce field emission of electrons from the cathode structure. The superimposed periodic signal provides electron beam uniformity. 
     An alternative embodiment of the present invention is a field emission display monitor including a video driver circuitry, a video monitor chassis for housing, and coupling to, the video driver circuitry and a field emission display coupled to the video driver circuitry and housed essentially within the monitor chassis. The field emission display may also include user controls coupled to the monitor chassis and in communication with the video driver circuitry. The field emission display includes an electron beam uniformity circuit. 
     A computer system embodiment of this invention includes an input device, an output device, a processor device coupled to the input device and the output device, and an FED coupled to the processor device. 
     The method according to this invention includes providing an FED device as described herein and varying the grid voltage with a periodic signal superimposed upon a DC offset voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings, which illustrate what is currently regarded as the best mode for carrying out the invention and in which like reference numerals refer to like parts in different views or embodiments: 
     FIG. 1 illustrates a portion of a structural cross-section of an array of micro-tipped cathode emitters in a conventional field emission display (FED) device; 
     FIG. 2 illustrates a portion of a structural cross-section of an array of flat cathode emitters in an alternative conventional FED device; 
     FIG. 3 is a schematic of a single emitter and FED in accordance with this invention; 
     FIG. 4 illustrates a portion of a structural cross-section of an array of micro-tipped cathode emitters in accordance with this invention; 
     FIG. 5 illustrates a portion of a structural cross-section of an array of flat cathode emitters in accordance with this invention; 
     FIG. 6 is a block diagram of a video monitor including an FED in accordance with this invention; and 
     FIG. 7 is a block diagram of a computer system including an FED in accordance with this invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 3, an emitter circuit  102 , in accordance with this invention, is shown schematically as part of an FED  100 . The emitter circuit  102  includes a cathode  104  with a row electrode  106  coupled to a switching element  108 . The switching element  108  is driven by row driver circuitry  110 . The emitter circuit  102  further includes a grid electrode  112  coupled to an electron beam uniformity circuit  114 . The terms “grid electrode” and “column electrode” may be used interchangeably. The grid electrode  112  is shown in proximity to the cathode  104 . Cathode  104  may be a micro-tipped cathode  26  as illustrated in FIG.  1 . Alternatively, cathode  104  may be a flat cathode  56  as illustrated in FIG.  2 . The emitter circuit  102  may further include a switching element in series between the cathode  104  and the row electrode  106 . The emitter circuit  102  additionally may further include a resistive element, R, in series between the switching element  108  and a ground potential, GND. The row driver circuitry  110  may include current and brightness control circuitry as described in U.S. Pat. No. 5,856,812 to Hush et al., U.S. Pat. No. 5,103,144 to Dunham and U.S. Pat. No. 5,656,892 to Zimlich et al. 
     The electron beam uniformity circuit  114  provides a grid voltage, V Grid . The grid voltage, V Grid , in conventional FED devices is typically a DC voltage of between about 30 volts and 110 volts relative to ground potential, GND. The grid voltage, V Grid , of the present invention provides a periodic signal superimposed on a DC offset of between about 30 and 110 volts. The periodic signal is chosen with an operating frequency faster than detectable by the human eye. In what is currently considered to be the best mode of the invention, a frequency of about 50 Hertz or greater is sufficient to be undetectable by the human eye. The periodic signal may be sinusoidal, with peak-to-peak voltage excursions of between about 5 volts and 50 volts. Alternatively, the periodic signal may be a rectangular wave also with peak-to-peak variations of between about 5 volts and 50 volts. The duty cycle of the rectangular wave may be between about 10 percent and 90 percent. The circuitry comprising the electron beam uniformity circuit  114  for generating the grid voltage as described above is within the knowledge of one skilled in the art and thus, will not be further detailed. 
     FIG. 3 also schematically illustrates an FED  100  embodiment of the invention. FED  100  includes an emitter circuit  102  as described above and a faceplate  118 . The faceplate  118  may include a transparent screen or glass substrate layer (not shown for clarity), a transparent conductive anode layer  122  (hereinafter “anode  122 ”) and a cathodoluminescent layer or phosphor layer  124 . An electrical potential of between about 500 volts to about 5000 volts may be applied to the transparent conductive anode layer  122  to enhance the field emission of electrons and gather the emitted electrons at the phosphor layer  124 . 
     In operation, with switching devices  108  and  116  both on, the row electrode  106  is pulled to ground potential, GND, through resistor, R. The electrical potential, V Grid , between the cathode  104  (row electrode  106 ) and the grid electrode  112  is sufficient to cause electron emission from the cathode  104 . The emitted electrons may then be swept to the phosphor layer  124  causing illumination at the faceplate  118 . 
     Referring to FIG. 4, a portion of an FED device  410  produced in accordance with this invention including micro-tipped cathode structures. The FED device  410  includes a faceplate  12  and a baseplate  20 , separated by spacers  32 . The spacers  32  support the FED device  410  structurally when the region  34  in between the faceplate  12  and the baseplate  20  is evacuated. The faceplate  12  includes a glass substrate  14 , a transparent conductive anode layer  16  and a cathodoluminescent layer or phosphor layer  18 . The phosphor layer  18  may include any known phosphor material capable of emitting photons in response to bombardment by electrons. 
     The baseplate  20  includes a substrate  22  with a row electrode  24 , a plurality of micro-tipped cathodes  26 , a dielectric layer  28  and a column electrode  30 , also referred to as a gate electrode  30 . The baseplate  20  is formed by depositing the row electrode  24  on the substrate  22 . The row electrode  24  is electrically connected to a row of micro-tipped cathodes  26 . The dielectric layer  28  is deposited upon the row electrode  24 . A column electrode  30  is deposited upon the dielectric layer  28  and acts as a gate electrode for the operation of the FED device  410 . 
     The substrate  22  may be comprised of glass. The micro-tipped cathodes  26  may be formed of a metal such as molybdenum, or a semiconductor material such as silicon, or a combination of molybdenum and silicon. Micro-tipped cathodes  26  may also be formed with a conductive metal layer (not shown) formed thereon. The conductive metal layer may be comprised of any well-known low work function material. 
     The FED device  410  operates by the application of an electrical potential between the column electrode  30  and the row electrode  24  causing field emission of electrons  36  from the micro-tipped cathode  26  to the phosphor layer  18 . Electron beam uniformity circuit  114  provides a grid voltage, V Grid , sufficient to emit electrons from the micro-tipped cathodes  26  with improved electron beam uniformity over prior art devices. The output of the electron beam uniformity circuit  114 , V Grid , of the present invention provides a periodic signal superimposed on a DC voltage offset of between about 30 and 110 volts. The periodic signal is chosen with an operating frequency faster than detectable by the human eye. In what is currently considered to be the best mode of the invention, a frequency of about 50 Hertz or greater is sufficient to be undetectable by the human eye. The periodic signal may be sinusoidal, with peak-to-peak voltage excursions of between about 5 volts and 50 volts. Alternatively, the periodic signal may be a rectangular wave also with peak-to-peak variations of between about 5 volts and 50 volts. The duty cycle of the rectangular wave may be between about 10 percent and 90 percent. The circuitry comprising the electron beam uniformity circuit  114  for generating the grid voltage as described above is within the knowledge of one skilled in the art and thus, will not be further detailed. 
     Transparent conductive anode layer  16  may also be biased to between about 500 volts to about 5000 volts to strengthen the electron field emission. The electrons  36  bombarding the phosphor layer  18 , illuminate individual phosphors  38 , resulting in visible light seen through the glass substrate  14 . The micro-tipped cathodes  26  of FED device  410  are 3-dimensional structures which may be formed as evaporated metal cones or etched silicon tips. 
     Referring to FIG. 5. a portion of an alternative FED device  540  is shown in accordance with this invention including flat cathode structures. FED device  540  includes a faceplate  42  and a baseplate  50  separated by spacers (not shown for clarity). The faceplate  42  may include a glass substrate  44 , a transparent conductive anode layer  46  disposed over the glass substrate  44 , and a phosphor layer  48  disposed over transparent conductive anode layer  46 . An electrical potential of between about 500 volts to about 5000 volts may be applied to the transparent conductive anode layer  46  to enhance the field emission of electrons and gather the emitted electrons at the phosphor layer  48 . 
     The baseplate  50  may include a substrate  52 , a conductive layer  54 , a flat cathode emitter  56 , a dielectric layer  58  and a grid electrode  60 . The conductive layer  54  may be a row electrode  54  and is deposited on the substrate  52 . The flat cathode emitter  56  and dielectric layer  58  are deposited on the conductive layer  54 . The grid electrode  60  may also be referred to as the column electrode  60 . The grid electrode  60  is deposited over, and supported by, the dielectric layer  58 . The flat cathode emitter  56  may comprise a low effective work function material such as amorphic diamond. 
     FIG. 6 is a block diagram of a video monitor  600  in accordance with this invention. The video monitor includes an FED  610  coupled  615  to video driver circuitry  620  which is coupled  625  to user controls  630 . The FED  610  includes an electron beam uniformity circuit  114  as described herein. The video driver circuitry  620  interfaces  640  with a video controller (not shown). The components of the video monitor  600  are housed in a video monitor chassis  650 . Details of how to make and use video driver circuitry  620 , user controls  630  and video monitor chassis  650  are within the knowledge of one skilled in the art and thus, will not be further detailed herein. 
     FIG. 7 illustrates a block diagram of a computer system  90  including an FED  80  in accordance with this invention. The computer system  90  includes an input device  70 , an output device  72 , an FED  80  and a processor device  74  coupled to the input device  70 , the output device  72  and the FED  80 . The FED  80  includes an electron beam uniformity circuit  114  as described herein. 
     Although this invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, it should be understood that the embodiments described herein are merely exemplary and that a person skilled in the art may make many variations and modifications without departing from the spirit and scope of the invention. All such variations and modifications are intended to be included within the scope of the invention as defined in the appended claims.

Technology Category: 5