Patent Document

TECHNICAL FIELD 
     The invention relates generally to low voltage differential signal (LVDS) drivers and, more particularly, to LVDS drivers that operate with supply rages between about 3.3V and about 1.8V. 
     BACKGROUND 
     LVDS drivers are commonly used with many different types of circuits, such as clocking circuitry. Looking specifically to clock products, especially those with multiple output channels, signal integrity from the LVDS drivers themselves as well as isolation of each LVDS driver from the other drivers are important. Lowering the supply voltage (1.8V, for example) would be desirable to help isolate the drivers, but drivers that operate in these voltage ranges encounter signal degradation issues (especially at high frequencies). 
     Turning  FIG. 1 , an example conventional circuit  100  employing an LVDS  102  can be seen. The driver  102  generally comprises current source  106  and complementary metal oxide semiconductor (CMOS) transistors M 1  through M 4 . In operation, driver  102  receives complementary differential signals D and  D  (which are rail-to-rail signals) at the gates of transistors M 1  through M 4  and supplies a signal over transmission line  106  (which is terminated by resistor R 1  to generally prevent line reflections) to receiver  104 . Because of the use of these CMOS transistors or switches, though, amplitude degradation and noise increase with frequency, and there are significant switching transients. Another conventional alternative is to use a driver that employs bipolar transistors; however, these types of drivers generally require high voltages (typically 3.3V or greater). 
     Some other examples of conventional circuits are: U.S. Pat. No. 6,617,888; U.S. Pat. No. 6,791,377; and U.S. Patent Pre-Grant Publ. No. 2003/0227303. 
     SUMMARY 
     A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a first supply rail having a voltage between about 1.8V and about 3.3V; a second supply rail; an input stage coupled between that first and second supply rails that receives a differential input signal, wherein the input stage includes at least one differential input pair of complementary metal oxide semiconductor (CMOS) transistors; and a first output stage that is coupled to the input stage and to at least one of the first and second supply rails, wherein the first output stage includes a plurality of diode-connected transistors; a second output stage that is coupled between the first and second supply rails and to the first output stage, wherein the second output stage includes a first plurality of transistors; a third output stage that is coupled between the first and second supply rails and to the first and second output stages, wherein the third output stage includes a second plurality of transistors; and a pair of differential output terminals that are coupled to each of the second and third stages, wherein the pair of differential output terminals carry a differential current, and wherein the differential current travels in a first direction and is supplied through the second output stage when the differential input signal is in a first state, and wherein the differential current travels in a second direction and is supplied through the third output stage when the differential input signal is in a second state. 
     In accordance with a preferred embodiment of the present invention, the input stage further comprises a first NMOS transistor that is coupled to the first supply rail at its drain and that receives at least a portion of the differential input signal at its gate; a second NMOS transistor that is coupled to the first supply rail at its drain and the source of the first NMOS transistor at its source and that receives at least a portion of the differential input signal at its gate; and a current source that is coupled between the sources of the first and second NMOS transistors and the second supply rail. 
     In accordance with a preferred embodiment of the present invention, the input stage further comprises a third NMOS transistor that is coupled to at least one of the plurality of diode-connected transistors at its drain and to the drain of the first NMOS transistor at its gate; a fourth NMOS transistor that is coupled to at least one of the plurality of diode-connected transistors at its drain and to the drain of the second NMOS transistor at its gate; and a second current source that is coupled between the sources of the third and fourth NMOS transistors and the second supply rail. 
     In accordance with a preferred embodiment of the present invention, the first output stage further comprises a first diode-connected PNP transistor that is coupled to the first supply rail at its emitter and the first input stage at its base and collector; a second diode-connected PNP transistor that is coupled to the second supply rail at its emitter and the first input stage at its base and collector; a first current source that is coupled to the emitter and base of the first PNP transistor and the second supply rail; and a second current source that is coupled to the emitter and base of the second PNP transistor and the second supply rail. 
     In accordance with a preferred embodiment of the present invention, the second output stage further comprises a first PNP transistor that is coupled to the first supply rail at its emitter and the base of at least one of the plurality of diode-connected transistors at its base; and a second PNP transistor that is coupled to the first supply rail at its emitter, the base of the first PNP transistor at its base, and one of the differential output terminals at its collector; and a current mirror that is coupled to the collector of the first PNP transistor and one of the differential output terminals. 
     In accordance with a preferred embodiment of the present invention, the third output stage further comprises a first PNP transistor that is coupled to the first supply rail at its emitter and the base of at least one of the plurality of diode-connected transistors at its base; and a second PNP transistor that is coupled to the first supply rail at its emitter, the base of the first PNP transistor at its base, and one of the differential output terminals at its collector; and a current mirror that is coupled to the collector of the first PNP transistor and one of the differential output terminals. 
     In accordance with a preferred embodiment of the present invention, the differential output terminals further comprises a positive output terminal and a negative output terminal. 
     In accordance with a preferred embodiment of the present invention, the first direction of the differential current is a first current traveling into the apparatus through the positive output terminal and a second current traveling out of the apparatus through the negative output terminal. 
     In accordance with a preferred embodiment of the present invention, the second direction of the differential current is a first current traveling out of the apparatus through the positive output terminal and a second current traveling into the apparatus through the negative output terminal. 
     In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises an input stage having: a first differential pair of CMOS transistors that receive a differential input signal; a second differential pair of CMOS transistors that are coupled to the first differential pair; a first output stage having a first diode-connected bipolar transistor and a second diode-connected bipolar transistor, wherein each of the first and second diode-connected bipolar transistors is coupled to one of CMOS transistors from the second differential pair; a second output stage having: a first set of bipolar transistors, wherein each bipolar transistor from the first set is coupled to the first diode-connected transistor at its base; and a first current mirror coupled that is coupled the collector of at least one of the bipolar transistors from the first set; and a third output stage having: a second set of bipolar transistors, wherein each bipolar transistor from the first set is coupled to the first diode-connected transistor at its base, wherein the collector of at least one bipolar transistor from the second set is coupled to the first current mirror; and a second current mirror coupled that is coupled the collector of at least one bipolar transistors from the first set and at least one bipolar transistor from the second set. 
     In accordance with a preferred embodiment of the present invention, the first output stage further comprises a first diode-connected PNP transistor that is coupled to at least one of the CMOS transistors at its base and collector; a second diode-connected PNP transistor that is coupled to at least one of the CMOS transistors at its base and collector; a first current source that is coupled to the emitter and base of the first PNP transistor; and a second current source that is coupled to the emitter and base of the second PNP transistor. 
     In accordance with a preferred embodiment of the present invention, the first set of bipolar transistors further comprises a first PNP transistor that is coupled to the base of at least one of the plurality of diode-connected bipolar transistors at its base and the first current mirror at its collector; and a second PNP transistor that is coupled to the base of the first PNP transistor at its base and the second current mirror at its collector. 
     In accordance with a preferred embodiment of the present invention, the second set of bipolar transistors further comprises a first PNP transistor that is coupled to the base of at least one of the plurality of diode-connected bipolar transistors at its base and the second current mirror at its collector; and a second PNP transistor that is coupled to the base of the first PNP transistor at its base and the first current mirror at its collector. 
     In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises signal generating circuitry; and a plurality of low voltage differential signal (LVDS) drivers that are each coupled to the signal generating circuitry, wherein each LVDS driver includes: a positive input terminal that is coupled to the signal generating circuitry; a negative input terminal that is coupled the signal generating circuitry; a first supply rail having a voltage between about 1.8V and about 3.3V; a second supply rail; a positive output terminal; a negative output terminal; a first NMOS transistor that is coupled to the positive input terminal at its gate and the first supply rail at its drain; a second NMOS transistor that is coupled to the negative input terminal at its gate and the first supply rail at its drain; a first current source that is coupled between the sources of the first and second NMOS transistors and the second supply rail; a third NMOS transistor that is coupled to the drain of the first NMOS transistor at its gate; a fourth NMOS transistor that is coupled to the drain of the second NMOS transistor at its gate; a second current source that is coupled to the sources of the third and fourth NMOS transistors; a first PNP transistor that is coupled to the drain of the third NMOS transistor at its base and collector and the first supply rail at its emitter; a second PNP transistor that is coupled to the drain of the fourth NMOS transistor at its base and collector and the first supply rail at its emitter; a third current source that is coupled to the emitter and base of the first PNP transistor; a fourth current source that is coupled to the emitter and base of the second PNP transistor; a third PNP transistor that is coupled to the first supply rail at its emitter and the base of the first PNP transistor at its base; a fourth PNP transistor that is coupled to the first supply rail at its emitter, the base of the first PNP transistor at its base, and the negative output terminal at its collector; a first current mirror that is coupled to the second supply rail and the collector of the third PNP transistor and the positive output terminal; a fifth PNP transistor that is coupled to the first supply rail at its emitter and the base of the second PNP transistor at its base; a sixth PNP transistor that is coupled to the first supply rail at its emitter, the base of the second PNP transistor at its base, and the positive output terminal at its collector; and a second current mirror that is coupled to the second supply rail, the collector of the fifth PNP transistor, and the negative output terminal. 
     In accordance with a preferred embodiment of the present invention, the signal generating circuitry further comprises: a phase locked loop (PLL); and intermediate circuitry coupled between the PLL and each of the LVDS drivers. 
     In accordance with a preferred embodiment of the present invention, a method is provided. The method comprises receiving a differential signal by a differential input pair of CMOS transistor, wherein the differential input signal has a state; mirroring one of a first current and a second current, generated in a first output stage from a supply voltage between about 1.8V and about 3.3V, in a corresponding one of a second output stage and a third output stage based at least in part on the state of differential signal; and generating a differential current at a first output terminal and a second output terminal, wherein direction of the differential current is based at least in part on the state of the differential signal, and wherein the second and third output stages are coupled to each of first and second output terminals. 
     In accordance with a preferred embodiment of the present invention, the state of the differential signal further comprises a first state and a second state, and wherein the step of mirroring further comprises generating the first current in a first diode-connected bipolar transistor for the first state; mirroring the first current in the second output stage for the first state; generating the second current in a second diode-connected bipolar transistor in the second state; and mirroring the second current in the third output stage for the second state. 
     In accordance with a preferred embodiment of the present invention, the step of generating further comprises: generating the differential current in a first direction for the first state; and generating the differential current in a second direction for the second state. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram of a conventional circuit using an LVDS driver with CMOS transistors; 
         FIG. 2  is an example of a block diagram of a system in accordance with a preferred embodiment of the present invention; and 
         FIG. 3  is an example of a circuit diagram of the LVDS drivers of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION 
     Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
     Referring to  FIG. 2  of the drawings, the reference numeral  200  generally designates a system in accordance with a preferred embodiment of the present invention. The system  200  generally comprises a phased locked loop (PLL)  202 , intermediate circuitry  204 , and drivers  300 - 1  to  300 -N. PLL  202  can generally operate to provide one or more clock signals to intermediate circuit  204  (which can be comprised of a variety of different types of circuit). The intermediate circuitry  204  can then distribute signals to divers  300 - 1  to  300 -N for transmission across differential transmission lines  206 - 1  to  206 -N (respectively). 
     Turning to  FIG. 3 , an example of the drivers  300  (which is generally the same as each of drivers  300 - 1  to  300 -N) can be seen. Driver  300  is generally divided into an input stage  302  and three output stage  304 ,  306 , and  308 . This driver  300  takes advantage of the characteristics of bipolar and CMOS transistors so that the supply voltage can be between about 1.8V and about 3.3V (which is provided on supply rail VDD). The input stage is generally comprised of differential input pairs of CMOS transistors M 5 /M 6  and M 7 /M 8 , resistors R 1  and R 1 , and current sources  310  and  312 . The first input stage  304  is generally comprised of resistors R 4  and R 5 , diode-connected PNP transistors Q 1  and Q 2 , and current sources  314  and  316 . The second input stage  306  is generally comprised of PNP transistors Q 3  and Q 4 , resistors R 5  and R 6  and current mirror Q 7 , Q 8 , R 10 , and R 11 , and the third output stage  308  generally comprises resistors R 8 , R 9 , R 14 , and R 15 , transistors Q 5  and Q 6 , and current mirror Q 9 , Q 10 , R 12 , and R 13 . Alternatively, transistors M 5  and M 6  can be replaced with bipolar transistors. 
     In operation, differential input signals are received by input terminals INM and INP so that an output signal having a differential current can be provided by or carried by output terminals OUTP and OUTM. The state of the differential signal (which does not need to be fully rail-to-rail for switching), as applied to terminals INM and INP, influences the direction of the differential current carried by terminals OUTP and OUTM. The relative currents carried by the terminals OUTP and OUTM generally comprise the differential current with the direction of the differential current being related to the relative directions carried by terminals OUTP and OUTM. 
     For a state of the differential input signal where a high signal is applied to input terminal INP and a low signal is applied to input terminal INM, a first current would travel out through terminal OUTP, and a second current would travel in through terminal OUTM. To accomplish this, the high and low signals are applied to the gates of NMOS transistors M 5  and M 6 , respectively. As a result, high and low signals are respectively applied to the gates of transistors M 7  and M 8  (which are coupled to the drains of transistors M 6  and M 5 , respectively). Current, then, flows through resistor R 4  and diode-connected PNP transistor Q 1 , which is mirrored by PNP transistors Q 5  and Q 6 . Because the collector of PNP transistor Q 5  is coupled to terminal OUTP, the first current is carried out of the driver  300  by terminal OUTP. Additionally, because the collector of PNP transistor Q 6  is coupled to the diode-connected NPN transistor Q 10 , the current mirrored by PNP transistor Q 6  is provided to diode-connected NPN transistor Q 10  and mirrored by NPN transistor Q 9  (which is coupled to terminal OUTM at its collector), allowing the second current to be carried into the driver  300  by terminal OUTM. 
     Alternatively, for a state of the differential input signal where a low signal is applied to input terminal INP and a high signal is applied to input terminal INM, the first current would travel in through terminal OUTP, and the second current would travel out through terminal OUTM. To accomplish this, the high and low signals are applied to the gates of NMOS transistors M 6  and M 5 , respectively. As a result, high and low signals are respectively applied to the gate of transistors M 8  and M 7 . Current, then, flows through resistor R 5  and diode-connected PNP transistor Q 2 , which is mirrored by PNP transistors Q 3  and Q 4 . Because the collector of PNP transistor Q 4  is coupled to terminal OUTM, the second current is carried out of the driver  300  by terminal OUTM. Additionally, because the collector of PNP transistor Q 3  is coupled to the diode-connected NPN transistor Q 7 , the current mirrored by PNP transistor Q 3  is provided to diode-connected NPN transistor Q 7  and mirrored by NPN transistor Q 8  (which is coupled to terminal OUTP at its collector), allowing the first current to be carried into the driver  300  by terminal OUTP. 
     As shown, driver  300  also includes several other features that enhance its operation. For example, current sources  314  and  316  are coupled to the gates and collectors of diode-connected PNP transistors Q 1  and Q 2 , respectively. These current sources  316  and  314  (which are coupled to supply rail VSS that is typically at ground) are provided to allow a standing current to remain in transistors Q 1  and Q 2  (partially saturated), which, in turn, causes a quiescent current to remain in transistors Q 3  to Q 10 . By providing current sources  314  and  316 , small swing differential signals may be applied to transistors M 7  and M 8 , and much more rapid switching can take place because of the partial saturation of transistors Q 1  through Q 10 . Additionally, resistors R 14  and R 15  are coupled between terminals OUTP and OUTM so as to provide a common mode voltage to common mode terminal VCM. 
     As a result of the configuration of the driver  300 , several advantages over conventional LVDS drivers can be realized. For example, in systems (such as system  200 ), there is better channel-to-channel isolation or reduced electromagnetic interference because of small-differential swings (which are generally not rail-to-rail) that generate minimal aggressor noise and because the fully-differential signaling is more immune to noise from adjacent channels. Additionally, there is lower additive jitter and less phase noise at a 1 MHz offset by avoiding the use of short-channel CMOS devices in a critical path. Moreover, driver  300  maintains a generally constant amplitude at high frequencies (i.e., up to 100 MHz). Additionally, the supply voltage is scalable (generally down to about 1.8V), and the phase noise remains generally constant across the supply. 
     Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.

Technology Category: h