Patent Document

RELATED APPLICATION 
   This application is based upon and claims the benefit of priority from the prior Korean Patent Application No. 10-2005-0127736, filed Dec. 22, 2005, the entire contents of which are incorporated herein by reference. 
   TECHNICAL FIELD 
   The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a semiconductor device with a bulb shaped recess gate pattern. 
   DESCRIPTION OF RELATED ARTS 
   As semiconductor devices became more highly integrated, a conventional planar type gate interconnection line including a gate pattern formed over a flat active region results in a short gate channel length and high ion-implantation concentration. Accordingly, junction leakage is generated due to an increased electric field and thus, the semiconductor device has a poor refresh property. 
   To alleviate the above problem associated with a conventional planar type gate interconnection line, a process has been implemented to form a recess gate pattern in an etched active region of a substrate. The recess gate pattern process increases a channel length and reduces an ion-implantation concentration, thereby improving a refresh property of the semiconductor device. 
   Furthermore, because a length of the recess gate pattern cannot decrease infinitely to satisfy the continuous demand for higher integration of semiconductor devices, a bulb shaped recess gate pattern with a wide and rounded lower portion thereof has been suggested to further improve a refresh property. 
     FIGS. 1 and 2  are micrographic images of transmission electron microscopy (TEM) illustrating a conventional semiconductor device with a bulb shaped recess gate pattern. 
   In  FIG. 1 , an abnormal phenomenon in the bulb shaped recess gate pattern formed on a substrate is illustrated. 
   An isotropic etching process is performed using a plasma obtained by mixing CF x , and CHF x , with oxygen gas to form the bulb shaped recess gate pattern. During the etching process, because of a low etch selectivity ratio between silicon and an oxide layer, the substrate becomes very sensitive to a chamber condition and a surface thereof may be damaged. As a result, the bulb shaped recess gate pattern may be unstable. 
     FIG. 2  illustrates a damaged top  100  and a damaged side  200  of the bulb shaped recess gate pattern, and an abnormal bulb formation  300 . 
   Similar to  FIG. 1 , an isotropic etching process is performed using a plasma obtained by mixing CF x  and CHF x  with oxygen gas to form the bulb shaped recess gate pattern. The damages and abnormality of the bulb shaped recess gate pattern illustrated in  FIG. 2  are due to a low etch selectivity ratio between silicon and an oxide layer. 
   SUMMARY 
   Consistent with embodiments of the present invention, there is provided a method for fabricating a semiconductor device with a bulb shaped recess gate pattern with reduced damages to a top and a side thereof and with reduced abnormality by increasing an etch selectivity between an oxide layer and silicon. 
   Consistent with embodiments of the present invention, there is provided a method for fabricating a semiconductor device, including selectively etching a first portion of a substrate to form a first recess; forming a spacer on sidewalls of the first recess; performing an isotropic etching process on a second portion of the substrate beneath the first recess to form a second recess, the second recess being wider and more rounded than the first recess; removing the spacer; and forming a gate pattern having a first portion buried into the first and second recesses and a second portion projecting over the substrate. 
   Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be apparent from that description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. 
   It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other features will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
       FIGS. 1 and 2  are micrographic images of transmission electron microscopy (TEM) illustrating a conventional semiconductor device with a bulb shaped recess gate pattern; 
       FIGS. 3A to 3E  are cross-sectional views illustrating a method for fabricating a semiconductor device with a bulb shaped recess gate pattern consistent with the present invention; and 
       FIG. 4  is a micrographic image of TEM illustrating a semiconductor device with a bulb shaped recess gate pattern consistent with the present invention. 
   

   DETAILED DESCRIPTION 
   Herein after, detailed descriptions of certain embodiments consistent with the present invention will be provided with reference to the accompanying drawings. 
     FIGS. 3A to 3E  are cross-sectional views illustrating a method for fabricating a bulb shaped recess gate pattern consistent with embodiments of the present invention. 
   As shown in  FIG. 3A , a plurality of device isolation layers  32  are formed in a substrate  31  through a shallow trench isolation (STI) process. Herein, the device isolation layers  32  are formed to define an active region and thus, the device isolation layers  32  have a greater depth than a recess gate pattern subsequently formed. 
   To form the device isolation layers  32 , predetermined portions of the substrate  31  are etched, thereby forming trenches. Insulation layers are buried into the trenches and polished through a chemical mechanical polishing (CMP) process to form the device isolation layers  32 . 
   Subsequently, a plurality of mask patterns  33  are formed over the substrate  31  including the device isolation layers  32 . Herein, each of the mask patterns  33  is formed by sequentially stacking a patterned sacrificial oxide layer  33 A, a patterned hard mask  33 B, a patterned anti-reflective coating layer  33 C, and a patterned photoresist layer  33 D. Although not shown, processes of forming the patterned sacrificial oxide layer  33 A, the patterned hard mask  33 B, the patterned anti-reflective coating layer  33 C, and the patterned photoresist layer  33 D are explained. First, a sacrificial oxide layer is formed over the substrate  31  including the device isolation layers  32 . The sacrificial oxide layer can be a pad oxide layer used during the device isolation layer formation process. Then, a hard mask is formed over the sacrificial oxide layer. The hard mask comprises silicon and serves to secure a margin of a photoresist layer during a subsequent etching process. Next, an anti-reflective coating layer and a photoresist layer are sequentially formed over the hard mask. Afterwards, the photoresist layer is patterned through a photo-exposure process and a developing process. Next, the anti-reflective layer, the hard mask, and the sacrificial oxide layer are patterned using the patterned photoresist layers  33 D as an etch mask. As a result, the mask patterns  33  including the patterned sacrificial oxide layer  33 A, the patterned hard mask  33 B, the patterned anti-reflective coating layers  33 C, and the patterned photoresist layers  33 D are formed. 
   As shown in  FIG. 3B , predetermined portions of the substrate  31  are etched using the mask patterns  33  as an etch mask, thereby forming a plurality of first recesses  34  with a vertical profile. When the first recesses  34  are formed, most portions of the mask patterns  33  except the patterned sacrificial oxide layers  33 A are removed. 
   As shown in  FIG. 3C , a plurality of spacers  35  are formed on sidewalls of the first recesses  34  to a thickness ranging from approximately 50 Å to approximately 100 Å. The spacers  35 , along with the patterned sacrificial oxide layers  33 A, prevent damages to the substrate  31  during a subsequent etching process for forming a second recess. The spacers  35  comprise an oxide formed at a medium temperature ranging from approximately 500° C. to approximately 700° C. 
   As shown in  FIG. 3D , the substrate  31  beneath the first recesses  34  is etched to form a plurality of second recesses  36 . The second recesses  36  are formed through an isotropic etching process in the same chamber where the first recesses  34  are formed. That is, the first recesses  34  and the second recesses  36  are formed in-situ. Also as  FIG. 3D  shows, the second recesses  36  are wider and more rounded than the first recesses  34 . 
   The second recesses  36  may be formed by etching the substrate  31  in one apparatus selected from the group consisting of an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, a microwave down stream (MDS) plasma reactor, an electron cyclotron resonance (ECR) plasma reactor, and a helical type plasma reactor, with a pressure ranging from approximately 20 mTorr to approximately 100 mTorr, a top power ranging from approximately 500 W to approximately 1,500 W, and without a bottom power. 
   The etching of the substrate  31  for forming the second recesses  36  may use a plasma including tetrafluoromethane (CF 4 ) gas, helium (He) gas and oxygen (O 2 ) gas as a main gas and, in addition, chlorine (Cl 2 ) gas or hydrogen bromide (HBr) gas. The addition of chlorine (Cl 2 ) gas or hydrogen bromide (HBr) results in a high etch selectivity between the substrate  31  which comprises silicon and the spacers  35  which comprise oxide. A flow rate of the CF 4  gas is approximately 30 sccm to approximately 80 sccm, a flow rate of the He gas is approximately 50 sccm to approximately 300 sccm, and a flow rate of the O 2  gas is approximately 10 sccm to approximately 50 sccm. A flow rate of the additional gas such as Cl 2  or HBr is approximately one fifth to approximately one third of the flow rate of the CF 4  gas. For example, the flow rate of the additional gas is approximately 6 sccm to approximately 27 sccm. 
   With the additional gas such as Cl 2  or HBr, a high etch selectivity between oxide layer and silicon is achieved during the etching of the substrate  31  for forming the second recesses  36 . Thus, it becomes possible to secure uniformity in a bulb formation without damage to either internal or external sides of a recess pattern. It is also possible to extend a channel length by forming the second recesses  36  which are wider and more rounded than the first recesses  34 . 
   Subsequently, although not shown, a plasma oxidation process is performed using a chemical dry etching (CDE) method. To perform the plasma oxidation process, an ICP type apparatus with a faraday field is used with supply of a power ranging from approximately 300 W to approximately 3,000 W. Also, the plasma oxidation process is performed using a plasma including CF 4  gas, He gas and O 2  gas. The CF 4  gas, the He gas and the O 2  gas are mixed in a ratio of approximately 12 to 100 to 30. Particularly, the plasma oxidation process is performed to oxidize the substrate  31  to a thickness of approximately 50 Å. 
   Hereinafter, recesses including the first recesses  34  and the second recesses  36  are referred to as recesses R. 
   As shown in  FIG. 3E , a wet cleaning process is performed. Herein, the wet cleaning process is performed by using a solution of hydrogen fluoride (HF) or buffered oxide etchant (BOE) to remove the patterned sacrificial oxide layer  33 A, the spacers  35  which comprises an oxide, and an etch residue. 
   Next, a gate insulation layer  37  is formed over the substrate  31  including the recesses R. Next, a plurality of gate patterns  38  are formed with first portions thereof buried in the recesses R and second portions thereof projecting over the substrate  31 . Herein, each of the gate patterns  38  is formed by sequentially stacking a polysilicon layer  38 A, a gate electrode  38 B, and a gate hard mask  38 C. 
     FIG. 4  is a micrographic image of transmission electron microscopy (TEM) illustrating semiconductor devices with bulb shaped recess gate patterns consistent with embodiments of the present invention. 
     FIG. 4  illustrates bulb shaped recess gate patterns formed by etching a silicon substrate with a plasma including Cl 2  gas or HBr gas, which results in a high etch selectivity between an oxide layer and silicon. First bulb shaped recess gate patterns  400  are formed by etching the silicon substrate with a plasma including Cl 2  gas with a flow rate of approximately 10 sccm, and second bulb shaped recess gate patterns  500  are formed by etching the silicon substrate with a plasma including HBr gas with a flow rate of approximately 10 sccm. First bulb shaped recess gate patterns  400  and second bulb shaped recess gate patterns  500  have a uniform profile. 
   Consistent with the present invention, it is possible to increase etch selectivity between silicon and an oxide layer by using a plasma including Cl 2  gas or HBr gas. Consequently, problems of damage to the top and side of a recess gate pattern and possible abnormality of the recess gate pattern are alleviated or avoided. 
   As described above, the method for fabricating a semiconductor device with the bulb shaped recess gate pattern consistent with the present invention achieves a high etch selectivity between silicon and an oxide layer during an etching for forming the recess gate pattern and makes it possible to secure uniformity in a bulb formation without causing any damages to internal and external sides of the recess gate pattern. Thus, a channel length of the recess gate pattern can be increased and an ion-implantation concentration can be decreased. Accordingly, a refresh property of the device can be greatly improved, thereby improving a design rule and maximizing a process margin. The method for fabricating the semiconductor device with the bulb shaped recess gate pattern consistent with embodiments of the present invention also allows for an increased scale of integration of semiconductor devices, improved yields of production, and decreased production costs. 
   It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed process without departing from the scope or spirit of the invention. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Technology Category: 5