Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS 
     The present disclosure is a continuation of U.S. patent application Ser. No. 13/336,785 (now U.S. Pat. No. 8,680,924), filed Dec. 23, 2011. This application claims the benefit of U.S. Provisional Patent App. No. 61/426,991, filed Dec. 23, 2010. The entire disclosures of the applications referenced above are incorporated herein by reference. 
    
    
     BACKGROUND 
     Particular embodiments of the present invention generally relate to power amplifiers. More specifically, particular embodiments of the present invention relate to a power amplifier configured to cancel even harmonic signals. 
     Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section. 
     Power amplifiers are configured to amplify the power of a received AC signal, such as an RF signal. Traditional power amplifiers often include a single nMOS transistor or a cascode both with tank loading.  FIG. 1  is a simplified schematic of a traditional power amplifier  100  that includes an nMOS transistor  105  coupled between an inductor  110  and ground. Inductor  110  may be coupled to a voltage source Vdd. Inductor  110  may be coupled to a capacitor  115  in a tank configuration for tuning the resonance of power amplifier  100 . The nMOS transistor  105  may be in a common source configuration with the gate of the nMOS transistor  105  configured to operate as an input to receive an AC signal and the drain coupled to the output Vout of power amplifier  100 .  FIG. 2  is a simplified schematic of another traditional power amplifier  200  that may include first and second nMOS transistors  205  and  210  in series between an inductor  215  and ground. Inductor  215  may be coupled to a voltage source Vdd. Inductor  215  may also be coupled to a capacitor  220  in a tank configuration for tuning the resonance of power amplifier  200 . The nMOS transistors  205  and  210  may be in a common source, common gate configuration with the gate of nMOS transistor  205  configured to operate as an input to receive an AC signal and a drain of transistor  210  coupled to the output of power amplifier  200 . 
     In traditional power amplifiers, such as power amplifier  100  and  200  described above, there are typically a number of nonlinear components at the drain of the transistor adjacent to the inductor. For example, the even harmonics, and especially the 2 nd  harmonic, of a received AC signal tend to be fairly large at the drain of the transistor adjacent to the inductor. The averaging DC current from the even harmonics tends to be relatively large and flows in the inductor generating a relatively large amount of heat. As a result of the heat in the inductor, the inductance may change and in a worst case scenario the inductor may catastrophically fail. 
     Therefore, it would be desirable to provide new power amplifiers that are configured to reduce the nonlinear components and reduce the adverse effects of the nonlinear components in power amplifiers. 
     SUMMARY 
     Particular embodiments of the present invention generally relate to power amplifiers. More specifically, particular embodiments of the present invention relate to a power amplifier configured to cancel even harmonic signals. 
     According to one specific embodiment, a power amplifier includes a push-pull pair of transistors including a first transistor inductively coupled to a voltage source and coupled to a ground. A second transistor is inductively coupled to the ground and is coupled to the voltage source. Gates of the first and the second transistors are AC inputs configured to receive an AC signal having a fundamental frequency. Drain regions of the first and the second transistors are, respectively, first and second output nodes. The power amplifier further includes a capacitor coupled between the first output node and the second output node where the capacitor is configured as a pathway for cancellation of even harmonic signals of the fundamental frequency of the AC signal. 
     According to another specific embodiment, the power amplifier further includes a first inductor disposed between the first transistor and the voltage source. The first output node is between the first transistor and the first inductor. The power amplifier further includes a second inductordisposed between second transistor and the ground. The second output node is between the second transistor and the second inductor. 
     According to another specific embodiment, the first output node is between the drain of the first transistor and the first inductor, and the second output node is between the drain of the second transistor and the second inductor. 
     According to another specific embodiment, a source of the first transistor is coupled to the ground, and a source of the second transistor is coupled to the voltage source. 
     According to another specific embodiment, the first transistor and the second transistor are in a common source configuration. 
     According to another specific embodiment, the power amplifier further includes a first tank capacitor coupled in parallel with the first inductor and configured to tune the resonant frequency of a first inductor. The power amplifier further includes a second tank capacitor coupled in parallel with the second inductor and configured to tune the resonant frequency of a second inductor. 
     According to another specific embodiment, the capacitor is substantially not a pathway for cancellation of fundamental frequency of the AC signal. 
     According to another specific embodiment, the first output node and the second output node are the same output of the power amplifier and are configured to be combined by a combiner. 
     According to another embodiment, a power amplifier includes a first transistor, and a first inductor coupled in series with the first transistor between a voltage source and a ground. A first node between the first transistor and the first inductor is a first output. The power amplifier further includes a second transistor and a second inductor coupled in series with the second transistor between the voltage source and the ground. A second node between the second transistor and the second inductor is a second output. Gates of the first and the second transistors are AC inputs configured to receive an AC signal having a fundamental frequency. The power amplifier further includes a capacitor coupled between the first node and the second node and is configured as a pathway for cancellation of even harmonic signals of the fundamental frequency of the AC signal. 
     According to another embodiment, a fully-differential power amplifier includes first, second, third, and fourth transistor-inductor pairs each coupled in series between a voltage source and a ground. The fully-differential power amplifier further includes a first capacitor coupled between a first node, which is between the first transistor-inductor pair, and a second node, which is between the second transistor-inductor pair. The fully-differential power amplifier further includes a second capacitor coupled between a third node, which is between the third transistor-inductor pair, and a fourth node, which is between the fourth transistor-inductor pair. A first transistor of the first transistor-inductor pair is coupled to ground, and a first inductor of the first transistor-inductor pair is coupled to a voltage source. A second transistor of the second transistor-inductor pair is coupled to the voltage source, and a second inductor of the second transistor-inductor pair is coupled to the ground. A third transistor of the third transistor-inductor pair is coupled to ground, and a third inductor of the third transistor-inductor pair is coupled to a voltage source. A fourth transistor of the fourth transistor-inductor pair is coupled to the voltage source, and a fourth inductor of the fourth transistor-inductor pair is coupled to the ground. Gates of the first and the second transistors are plus input configured to receive an AC signal having a fundamental frequency, and gates of the third and the fourth transistors are minus input configured to receive the AC signal having the fundamental frequency. The first and second capacitors are configured to cancel even harmonics of the fundamental frequency of the AC signal. 
     According to one specific embodiment of the fully-differential power amplifier, the first and the third transistor are a first differential pair, and the second and fourth transistors are a second differential pair. Further, the first, second, third, and fourth transistors may be in a common source configuration. 
     According to another specific embodiment of the fully-differential power amplifier, the fully-differential power amplifier further includes a combiner having first, second, third, and fourth combiner inductors respectively in series. The first inductor and the first combiner inductor are inductively coupled. The third inductor and the second combiner inductor are inductively coupled. The fourth inductor and the third combiner inductor are inductively coupled. The second inductor and the fourth combiner inductor are inductively coupled. 
     According to another specific embodiment of the fully-differential power amplifier, the fully-differential power amplifier further includes a combiner having first and second combiner inductors in series. The first inductor, the second inductor, and the first combiner inductor are inductively coupled. The third inductor, the fourth inductor, and the second combiner inductor are inductively coupled. 
     The following detailed description and accompanying drawings provide a more detailed understanding of the nature and advantages of the present invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified schematic of a traditional power amplifier that includes an nMOS transistor coupled in series with an inductor between a voltage source and ground; 
         FIG. 2  is a simplified schematic of another traditional power amplifier that may include first and second nMOS transistors coupled in series with an inductor between a voltage source and ground; 
         FIG. 3  is a simplified schematic of a power amplifier according to one embodiment of the present invention; 
         FIG. 4A  is a simplified schematic of a fully-differential power amplifier according to one embodiment of the present invention; 
         FIG. 4B  is an alternative simplified schematic of the fully-differential power amplifier shown in  FIG. 4A ; and 
         FIG. 5  is a simplified schematic of a fully-differential power amplifier according to an alternative embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Described herein are embodiments of a power amplifier and a method of operation for the power amplifier where the power amplifier is configured to cancel even harmonic signals present in the power amplifier. 
     In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. 
     Power amplifiers are configured to amplify the power of a received AC signal, such as an RF signal, for subsequent transmission of the amplified AC signal. Power amplifiers may be included in a variety of mobile devices, such as mobile telephones. A power-amplified AC signal may be directed through an antenna of a mobile device for transmission. 
       FIG. 3  is a simplified schematic of a power amplifier  300  according to one embodiment of the present invention. Power amplifier  300  includes a push-pull pair of transistors  305  and  310 , (referred to as transistors  305  and  310 ). Power amplifier  300  further includes first and second inductors  315  and  320  and a capacitor  325 . Power amplifier  300  may also include first and second tank capacitors  330  and  335 . Transistors  305  and  310  may be metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar-junction transistors (BJTs), or other transistor types. For convenience, power amplifier embodiments are described herein as including MOSFETs. While power amplifier embodiments are described herein as including MOSFETs, it will be understood by those of skill in the art that BJTs or other types of transistors may be appropriately substituted for the MOSFETs, and these power amplifier embodiments that include BJTs or the like are considered to be within the scope and purview of the power amplifier embodiments of the present invention. 
     According to one embodiment, transistor  305  is an nMOS transistor with a drain  305   a  (sometimes referred to a drain region) coupled to a first end of inductor  315  where a second end of inductor  315  is coupled to a voltage source Vdd. A source  305   b  of transistor  305  may be coupled to ground. Specific configurations of the sources and the drains of transistors  305  and  310  are described herein for convenience of explanation of specific embodiments. Alternative embodiments of the power amplifiers may include alternative configurations of the sources and the drains of transistors  305  and  310  as will be understood by those of skill in the art. A gate  305   c  of transistor  305  may be a first AC input  340   a  configured to receive an AC signal. 
     Capacitor  330  is coupled to inductor  315  in parallel in a tank configuration. Capacitor  330  is configured to tune the resonant frequency of inductor  315 . 
     According to one embodiment, transistor  310  is a pMOS transistor with a drain  310   a  coupled to a first end of inductor  320  where a second end of inductor  320  is coupled to ground. A source  310   b  of transistor  310  is coupled to the voltage source Vdd. A gate  310   c  of transistor  310  may be a second AC input  340   b  configured to receive the AC signal supplied to the first AC input  340   a . Capacitor  335  may be coupled to inductor  320  in parallel in a tank configuration. Capacitor  335  is configured to tune the resonant frequency of inductor  320 . Inductors  315  and  320  may be considered the respective loads of the push-pull pair of transistors  305  and  310 . 
     Power amplifier  300  includes a first output node  345   a  disposed between inductor  315  and the drain  305  a of transistor  305 . Power amplifier  300  further includes a second output node  345   b  disposed between inductor  320  and the drain  310   a  of transistor  310 . According to one embodiment capacitor  325  is coupled between the first output node  345   a  and the second output node  345   b.    
     The even harmonics (e.g., 2 nd  harmonic, 4 th  harmonic, etc.) of the AC signal that are at the drain of transistor  305  are generally 180 degrees out of phase with the even harmonics of the AC signal that are at the drain of transistor  310 . The capacitance of capacitor  325  is determined such that the circuit path between the two output nodes is substantially a short circuit for the even harmonics, but is not a short circuit for the fundamental frequency of the AC signal. According to one specific embodiment, the capacitance of capacitor  325  is approximately 20 picofarads for an approximately 2 gigahertz AC signal. As the even harmonics on either side of capacitor  325  are out of 180 degrees phase and as capacitor  325  is substantially a short for the even harmonics on either side of capacitor  325 , the even harmonics on either side of capacitor  325  tend to cancel each other. Because the even harmonics on either side of capacitor  325  tend to cancel each other, capacitor  325  ensures that the even harmonics do not substantially pass into the inductors  315  and  320 . As a result, unnecessary heating of the inductors  315  and  320  via the even harmonics is inhibited. Capacitor  325  may be replaced with alternative circuits that provide capacitance, such as a diode or the like according to one alternative embodiment. 
     The voltage at the first output node  345   a  (i.e., the voltage at the drain of transistor  305 ) may be expressed as: Vdn=ao n +o.i n v(/o)+a2 n v(2/ 0 )+ou n v(3/o)+ . . . , and the voltage at the second output node  345   b  (i.e., the voltage at the drain of transistor  310 ) may be expressed as: V dp =ao p +ai p v(/o)+a2 p v(2/ 0 )+ou n v(3/o)+ . . . . The even coefficients of the voltage expressions for nMOS transistors and pMOS transistors have different polarities, providing for the substantial cancellation of the even harmonics across capacitor  325 . 
     Power amplifier  300  is a single stage power amplifier that is not fully differential. Two power amplifiers  300  may be inductively coupled to form a fully-differential power amplifier according to one embodiment of the present invention. 
       FIG. 4A  is a simplified schematic of a fully-differential power amplifier  400  according to one embodiment of the present invention. Fully-differential power amplifier  400  includes a first power amplifier  400   a  and a second power amplifier  400   b . Power amplifiers  400   a  and  400   b  have substantially the same configuration as power amplifier  300  described above. Power amplifiers  400   a  and  400   b  are both configured to cancel the even harmonics of the fundamental frequency of a received AC signal. The numbering scheme of the power amplifiers used with respect to fully-differential power amplifier  400  is changed for convenience as fully-differential power  400  includes first and second stages where each stage includes a power amplifier  300 . 
     Power amplifier  400   a  includes a push-pull pair of transistors  405   a  and  410   a , which are referred to herein as transistors  405   a  and  410   a . Power amplifier  400   a  further includes first and second inductors  415   a  and  420   a  and a capacitor  425   a . Power amplifier  400  may also include first and second tank capacitors  430   a  and  435   a . Transistors  405   a  and  410   a  are MOSFETs, BJTs, or other transistors types. According to one embodiment, transistor  405   a  is an nMOS transistor, and transistor  410   a  is a pMOS transistor. The electronic components of power amplifier  400   a  are configured substantially the same as the corresponding electronic components of power amplifier  300 . For example, transistor  405   a  may be in a common source configuration and coupled in series with inductor  415   a . The series pair of transistor  405   a  and inductor  415   a  are coupled between the voltage source Vdd and the ground where transistor  405   a  is coupled to the ground and inductor  415   a  is coupled to the voltage source Vdd. Transistor  410   a  is similarly in a common source configuration and is coupled in series with inductor  420   a . The series pair of transistor  410   a  and inductor  420   a  are coupled between the voltage source Vdd and the ground with transistor  410   a  coupled to the voltage source Vdd and inductor  420   a  coupled to the ground. 
     Power amplifier  400   b  includes a push-pull pair of transistors  405   b  and  410   b , which are referred to herein as transistors  405   b  and  410   b . Power amplifier  400   b  further includes first and second inductors  415   b  and  420   b  and a capacitor  425   b . Power amplifier  400  may also include first and second tank capacitors  430   b  and  435   b . Transistors  405   b  and  410   b  may be MOSFETs, BJTs, or other transistor types. According to one embodiment, transistor  405   b  is an nMOS transistor, and transistor  410   b  is a pMOS transistor. The electronic components of power amplifier  400   a  are configured substantially the same as the corresponding electronic components of power amplifier  300 . For example, transistor  405   b  may be in a common source configuration and coupled in series with inductor  415   b . The series pair of transistor  405   b  and inductor  415   b  are coupled between the voltage source Vdd and the ground where transistor  405   b  is coupled to the ground and inductor  415   b  is coupled to the voltage source Vdd. Transistor  410   b  is similarly in a common source configuration and is coupled in series with inductor  420   b . The series pair of transistor  410   b  and inductor  420   b  are between the voltage source Vdd and the ground with transistor  410   b  coupled to the voltage source Vdd and inductor  420   b  coupled to the ground. 
     The first and second output nodes of power amplifier  400   a  are coupled by capacitor  425   a . The first and second output nodes of power amplifier  400   b  are coupled by capacitor  425   b . Capacitor  425   a  is configured to provide a circuit path for the cancellation of even harmonics on opposite sides of capacitor  425   a . Similarly, capacitor  425   b  is configured to provide a circuit path for the cancellation of even harmonics on opposite sides of capacitor  425   b.    
     The gates of transistors  405   a  and  410   a  are the AC inputs for power amplifier  400   a  and are the “plus” inputs of fully-differential power amplifier  400 . The gates of transistors  405   b  and  410   b  are the AC inputs for power amplifier  400   b  and are the “minus” inputs of fully-differential power amplifier  400 . The plus inputs of the fully-differential power amplifier are designated with “+” symbols in  FIG. 4A , and the minus inputs are designated with symbols in  FIG. 4A . The nMOS transistors  405   a  and  405   b  are a fully differential n-pair and the pMOS transistors  410   a  and  410   b  are a fully differential p-pair. 
     According to one embodiment of the present invention, a combiner  460  is configured to combine the outputs of fully-differential power amplifier  400  to deliver an amplified AC signal to an antenna  465  or the like. Combiner  460  includes a first, second, third, and fourth inductors  470   a ,  470   b ,  470   c , and  470   d  coupled together in series and coupled to antenna  465 . Inductors  470   a ,  470   b ,  470   c , and  470   d  are inductively coupled, respectively, to inductors  415   a ,  420   a ,  415   b , and  420   b  where each pair of inductively coupled inductors is a transformer. 
       FIG. 4B  is an alternative simplified schematic of the fully-differential power amplifier  400  shown in  FIG. 4A . Transistors  405   a  and  405   b  are shown as a driver  405  with positive and negative differential outputs, and transistors  410   a  and  410   b  are shown as a driver  410  also with positive and negative differential outputs. The fully-differential power amplifier  400  as shown in  FIG. 4B  clearly shows the serial nature of the first, the second, the third, and the fourth inductors  470   a ,  470   b ,  470   c , and  470   d . As shown in  FIG. 4B , the laterally adjacent inductors  415   a  and  470   a  are inductively coupled, the laterally adjacent inductors  415   b  and  470   b  are inductively coupled, the laterally adjacent inductors  420   a  and  470   d  are inductively coupled, and the laterally adjacent inductors  420   b  and  470   c  are inductively coupled. The node between inductors  415   a  and  415   b  may be coupled to a reference voltage, such as Vdd. The node between inductors  420   a  and  420   b  may be coupled to ground. 
       FIG. 5  is a simplified schematic of a fully-differential power amplifier  500  according to an alternative embodiment. The same reference numeral schema used for the foregoing described figures is used in  FIG. 5  to identify the same elements or substantially similar elements. Fully-differential power amplifier  500  is substantially similar to fully-differential power amplifier  400  but differs in that a combiner  480  of fully-differential power amplifier  500  differs from combiner  460  of fully-differential power amplifier  400 . Combiner  480  includes the first inductor  470   a  inductively coupled to both inductors  415   a  and  420   a , and the second inductor  470   b  inductively coupled to both inductors  415   b  and  420   b . Inductors  470   a  and  470   b  are disposed in series. Inductors  470   a ,  415   a , and  420   a  are substantially parallel, and inductors  470   b ,  415   b , and  420   b  are also substantially parallel. Combiner  480  then applies the outputs onto antenna  465 . 
     The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations, and equivalents may be employed without departing from the scope of the invention as defined by the claims.

Technology Category: h