Patent Document

RELATED APPLICATIONS  
       [0001]    The present application is related to concurrently filed, co-pending, and commonly assigned U.S. patent application Ser. No. ______, Attorney Docket No. 10020790-1, entitled “SYSTEMS AND METHODS FOR CORRECTING GAIN ERROR DUE TO TRANSITION DENSITY VARIATION IN CLOCK RECOVERY SYSTEMS;” U.S. patent application Ser. No. ______, Attorney Docket No. 10021026-1, entitled “SYSTEM AND METHOD FOR DESIGNING AND USING ANALOG CIRCUITS OPERATING IN THE MODULATION DOMAIN;” and U.S. patent application Ser. No. ______, Attorney Docket No. 10021027-1, entitled “SYSTEMS AND METHODS FOR CORRECTING PHASE LOCKED LOOP TRACKING ERROR USING FEED-FORWARD PHASE MODULATION;” the disclosures of which are hereby incorporated herein by reference. 
     
    
     
       TECHNICAL FIELD  
         [0002]    The present invention is generally related to phase lock loop (PLL) demodulators and more particularly to systems and methods for utilizing feed-forward tracking error compensation to address tracking error in a PLL demodulator.  
         BACKGROUND OF THE INVENTION  
         [0003]    Phase locked loops (PLLS) are devices that generate a signal and that lock their phase to the phase of an input reference signal. According to the prior art, as shown in FIG. 1, PLL  100  typically has three main components: voltage-controlled oscillator (VCO)  101 , phase detector  102 , and loop filter  103 . VCO  101  generates a signal that has a frequency proportional to the tuning voltage input. This proportionality is typically expressed as a VCO gain parameter (K v ) denoted in units of radians/second per volt. Reference signal  104  may be provided at a reference frequency and phase. Phase detector  102  generates an output voltage proportional to the phase difference between the reference signal and the VCO signal. This proportionality is typically expressed as a phase detection gain parameter (K d ) denoted in units of volts/radian. Thus, phase detector  102  generates a phase error signal (i.e., the phase tracking error). Loop filter  103  amplifies and filters this error signal, which is then fed back to VCO  101 . This feedback adjusts the phase of VCO  101  and causes VCO  101  to approximate the phase of the reference signal thereby minimizing the error.  
           [0004]    PLL  100  as shown in FIG. 1 is difficult to analyze on a mathematical basis, because the input and ouput of the loop filter are different types of variables (i.e., voltage proportional to phase and voltage proportional to frequency, respectively). By definition, phase is the time integral of frequency. Therefore, an ideal VCO  200  may be modeled as two mathematical blocks: ideal integrator  201  and ideal voltage to phase transducer  202  as shown in FIG. 2 according to the prior art. Ideal VCO  200  may be incorporated in a PLL system to provide useable PLL model  300  as shown in FIG. 3 according to the prior art. PLL model  300  may then be analyzed according to mathematical model  400  shown in FIG. 4 according to the prior art. In mathematical model  400 , K d  represents the phase detection gain parameter of phase detector  102 , F(s) represents the transfer function of loop filter  103  (expressed in Laplace transform notation), 1/s represents the transfer function of ideal integrator  201  (also expressed in Laplace transform notation), and K v  represents the VCO gain parameter of VCO  101 . The loop gain is represented by the parameter G which equals K d K v F(s)/s. Moreover, θ vco  represents the phase of the signal produced by VCO  101  and θ ref  represents the phase of the reference signal. The relationship between θ vco  and θ ref  may be represented by the following equation: θ vco /θ ref =G/(1+G). Thus, when the loop gain is relatively large (G&gt;&gt;1), θ vco  approximates θ ref  with a significant degree of accuracy.  
           [0005]    Integrator  201  acts as a low pass filter and causes the loop gain to decrease with increasing frequency. Thus, tracking error increases with increasing frequency. At some frequency, the loop gain falls below unity. Above this frequency (which defines the loop bandwidth), the loop has relatively little response to the reference stimulus and, hence, limits the capacity of PLL  100  to continue accurately tracking the reference signal. Accordingly, this places a constraint upon the bandwidth of modulation that may be applied to the reference signal. Theoretically, the loop bandwidth can be increased by increasing the loop gain. However, in practice, implementations of VCO  101  have finite modulation bandwidth. The limited bandwidth of VCO  101  may be modeled in VCO  500  as a parasitic low pass filter  501  defined by transfer function P(s) as shown in FIG. 5 according to the prior art. This has the effect of modifying the mathematical model by adding another low pass function to loop model  600  as shown in FIG. 6 according to the prior art. As shown in FIG. 6, the loop gain (G) equals K d K v F(s)P(s)/s. This has the practical effect of limiting the loop bandwidth to a relatively small fraction of the VCO bandwidth. Because of numerous design constraints associated with implementations of VCO  101 , the VCO bandwidth cannot be made arbitrarily high. Accordingly, the VCO bandwidth often becomes a limiting factor on loop bandwidth. In addition to the VCO bandwidth, the loop filter may have its own bandwidth limitations, especially if it utilizes active circuitry. The effect of finite loop filter bandwidth is the same as VCO bandwidth in terms of limiting loop bandwidth.  
           [0006]    PLLs are commonly utilized to build frequency or phase demodulators. A demodulator is a system driven by a modulated signal that produces an output voltage that is proportional to the modulation. FIG. 7 depicts PLL frequency demodulator  700  according to the prior art. VCO  101  tracks the phase of the reference signal. Because of the close mathematical relationship between phase and frequency, VCO  101  also tracks the frequency of the reference. Since the tuning voltage applied to VCO  101  is proportional to the VCO frequency (and, hence, to the reference frequency), the tuning voltage is used directly as demodulated output  701 .  
           [0007]    [0007]FIG. 8 depicts phase demodulator  800  according to the prior art. Phase demodulator  800  is substantially the same as frequency demodulator  700  except that leaky integrator  801  has been added to convert the tuning voltage (proportional to frequency) into a voltage (demodulated output  802 ) proportional to phase. Since an ideal integrator is not physically realizable, a so-called “leaky” integrator  801  is shown. Specifically, leaky integrator  801  approximately acts as an ideal integrator above a specified minimum frequency (ω 1 ). Below that frequency, leaky integrator  801  changes to a flat gain versus frequency characteristic. This imparts a low frequency cutoff to the frequency response of the demodulation output port.  
         BRIEF SUMMARY OF THE INVENTION  
         [0008]    In an embodiment, the present invention is directed to a PLL phase demodulator that utilizes feed-forward error correction. The feed-forward error correction may occur by calibrating an equalizer to possess a transfer function that emulates the modulation response curve of the VCO of the PLL phase demodulator. In operation, the equalizer may receive the filtered and integrated version of the error signal produced by the phase detector of the PLL. The equalizer filters the received signal according to the calibrated transfer function. The output of the equalizer is provided to a adder to combine the equalized signal with the error signal produced by the phase detector. The combined signal represents the demodulated output signal. In other embodiments, a similarly calibrated equalizer may be utilized to address tracking error in a frequency demodulator. By utilizing a suitable calibrated equalizer, embodiments in accordance with the invention enable demodulators to operate at arbitrarily high modulation frequencies (for small modulation index) that are not limited by the loop bandwidth or VCO bandwidth.  
           [0009]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:  
         [0011]    [0011]FIG. 1 depicts a PLL according to the prior art;  
         [0012]    [0012]FIG. 2 depicts a conceptual model of a VCO according to the prior art;  
         [0013]    [0013]FIG. 3 depicts PLL including the conceptual model of a VCO according to the prior art;  
         [0014]    [0014]FIG. 4 depicts a mathematical model of a PLL according to the prior art;  
         [0015]    [0015]FIG. 5 depicts a practical VCO model according to the prior art;  
         [0016]    [0016]FIG. 6 depicts a mathematical model of a PLL that includes a practical VCO model according to the prior art;  
         [0017]    [0017]FIG. 7 depicts a conventional PLL frequency demodulator according to the prior art;  
         [0018]    [0018]FIG. 8 depicts a conventional PLL phase demodulator according to the prior art;  
         [0019]    [0019]FIG. 9 depicts a PLL phase demodulator according to embodiments in accordance with the invention;  
         [0020]    [0020]FIG. 10 depicts a mathematical model of the PLL phase demodulator shown in FIG. 9 according to embodiments in accordance with the invention;  
         [0021]    [0021]FIG. 11 depicts a flowchart for calibrating the PLL phase demodulator shown in FIG. 9 according to embodiments in accordance with the invention;  
         [0022]    [0022]FIG. 12 depicts a mathematical analysis of calibration according to embodiments in accordance with the invention;  
         [0023]    [0023]FIG. 13 depicts a clock data recovery phase demodulator according to embodiments in accordance with the invention; and  
         [0024]    [0024]FIG. 14 depicts a frequency demodulator according to embodiments in accordance with the invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0025]    One of the principal sources of inaccuracy in PLL demodulators is the phase tracking error. Phase tracking error may be minimized by increasing the loop bandwidth as much as possible. As previously noted, in practice, the loop components (namely, VCO  101 ) have parasitic frequency response impairments that place an upper bound on the achievable bandwidth. The usable bandwidth is, in turn, limited to a small fraction of the loop bandwidth if high accuracy (i.e., low phase tracking error) is desired. In any event, the demodulation bandwidth cannot exceed the loop bandwidth even for low accuracy applications. Accordingly, embodiments in accordance with the invention address these difficulties by providing an accurate, wideband response PLL demodulator that does not require an excessively high VCO modulation bandwidth.  
         [0026]    [0026]FIG. 9 depicts PLL phase demodulator  900  according to embodiments in accordance with the invention. PLL phase demodulator  900  comprises the typical main components of a phase demodulator: VCO  101 , phase detector  102 , loop filter  103 , and leaky integrator  801 . PLL phase demodulator  900  differs from conventional PLL phase demodulators by utilizing adder  903  in conjunction with equalizer  901 . Equalizer  901  is operable to equalize the low frequency modulation signal received from leaky integrator  801  according to a transfer function that emulates the modulation response curve of VCO  101 . The calibration filter constants associated with equalizer  901  may be adjusted according to the determined modulation responsive curve of VCO  101 . PLL phase demodulator  900  further comprises adder  903  that produces output signal  909  (which is a voltage proportion to phase (VPTP)). Specifically, adder  903  adds the phase detector output to the equalized signal from equalizer  901  thereby canceling out demodulation error due to mistracking error. Moreover, summing these two signals enables PLL phase demodulator  900  to operate at arbitrarily high modulation frequencies (for small modulation index) that are not limited by the loop bandwidth or VCO bandwidth.  
         [0027]    The operation of PLL phase demodulator  900  depends upon the frequency of the modulation originally applied to reference input signal  910  (i.e., the signal being demodulated). In essence, there are three regimes of operation. For low modulation frequencies (i.e., well within the loop bandwidth), the operation is substantially identical to operation of conventional PLL phase demodulators. In this regime, the loop tracking error is negligible and, hence, there is negligible output from phase detector  102 . At these frequencies, the effect of equalizer  901  is to apply a scaling factor to signal  910 . Specifically, signal  910  passes through equalizer  901  without appreciable modification except for scaling. For high modulation frequencies (i.e., well beyond the loop bandwidth), the loop has negligible response, and the phase of VCO  101  is approximately constant. This occurs, because the combination of loop filter  103 , the modulation bandwidth of VCO  101 , and the built-in integrator of VCO  101  causes severe high frequency attenuation. In this case, signal  910  is negligible and the tracking error is approximately 100%. In other words, the tracking error is equal and opposite to the modulation carried on reference input  910 . Thus, phase detector  102  operates as a phase demodulator in its own right. In this case, the phase detector signal  911  passes through to output signal  909  without appreciable modification and equalizer  901  has little appreciable effect in the high frequency regime. For medium modulation frequencies, the operation is a combination of the two previously described modes. In the medium modulation frequency regime, equalizer  901  applies a scaling factor and a frequency response effect to cancel error due to phase mistracking.  
         [0028]    [0028]FIG. 10 depicts mathematical model  1000  of PLL phase demodulator  900  according to embodiments in accordance with the invention. Mathematical model  1000  demonstrates the accuracy of PLL phase demodulator  900  at all frequencies above the cutoff frequency of leaky integrator  801 . In mathematical model  1000 , θ vco  represents the phase of the signal produced by VCO  101  and θ in  represents the phase of the reference signal. Also, K d  represents the phase detection gain parameter of phase detector  102 , F(s) represents the transfer function of loop filter  103 , P(s) represents the transfer function of the parasitic low pass filter characteristic of VCO  101 , 1/s represents the transfer function of ideal integrator  201 , K v  represents the VCO gain parameter of VCO  101 , E(s) represents the transfer function of equalizer  901 , and 1/(s+ω 1 ) represents the transfer function of leaky integrator  801 . According to embodiments in accordance with the invention, it may be advantageous to set the transfer function of E(s) to equal K d K v P(s). The input to equalizer  901  (signal  910  of FIG. 9) is characterized by θ VCO /K v P(s)/s. Thus, by setting E(s) in this manner, output signal  909  (V demod ) equals K d {θ VCO [s/(s+ω 1 )−1]+θ IN }. If the frequency (ω) of the modulation applied to reference input signal  910  is substantially greater than the specified minimum frequency of leaky integrator  801  (i.e., ω&gt;&gt;ω 1 ), then V demod  very closely approximates K d θ IN .  
         [0029]    Returning now to FIG. 9, PLL phase demodulator  900  further comprises structure to facilitate calibration of equalizer  901 . Specifically, PLL phase demodulator  900  comprises switch  904  to switch modes of operation between a demodulation mode and a calibration mode. When switch  904  places PLL phase demodulator  900  into the calibration mode, the output from loop filter  903  is diverted and sent to calibration loop filter  905  (which will be discussed in greater detail below). After calibration loop filter  905 , the filtered signal is processed and provided to adder  907  where the filtered signal is added to the signal generated by calibration source  906 . The combined signal then proceeds through the remaining circuit path through leaky integrator  801 , equalizer  901 , and adder  903 . Calibration voltmeter  902  may be used to measure the voltage of output signal  909  during calibration. Also, calibration frequency meter  908  may be used to measure to frequency of VCO  101 .  
         [0030]    In embodiments in accordance with the invention, calibration may occur to determine the scale factor (K d ) of phase detector  102 . Additionally, calibration may occur to set equalizer  901  to the appropriate DC gain and frequency response characteristics. In embodiments in accordance with the invention, a quasi open-loop calibration algorithm is utilized. To implement the quasi open-loop algorithm, calibration source  906  may advantageously generate DC signals and AC signals of frequencies included in the loop bandwidth. Likewise, an unmodulated frequency reference source (not shown) may be utilized to drive reference input signal  910 . Preferably, the unmodulated frequency reference source may generate AC signals of frequencies over a small range centered on the frequency of the signal to be measured after calibration is complete.  
         [0031]    In embodiments in accordance with the invention, the quasi open-loop calibration algorithm takes advantage of the fact that the accuracy of PLL phase demodulator  900  is independent of loop filter  103 . Calibration is facilitated by the use of calibration loop filter  905  which acts as a low pass filter with a relatively low cutoff frequency. Adapting calibration loop filter  905  in this manner results in a narrow loop bandwidth. The loop can be considered open during the calibration mode due to the narrowed loop bandwidth. However, the loop is kept in lock for proper operation during the demodulation mode by utilizing switch  904  to bypass calibration loop filter  905 .  
         [0032]    [0032]FIG. 11 depicts flowchart  1100  for calibrating PLL phase demodulator  900  according to embodiments in accordance with the invention. In step  1101 , the reference input of phase detector  102  is excited with an unmodulated frequency signal. In step  1102 , using calibration source  906  in AC mode, the system is excited with a frequency well within the loop bandwidth and above the cutoff frequency of leaky integrator  801 . In step  1103 , the DC gain of equalizer  901  is adjusted for a null at the V demod  output (output signal  909  of FIG. 9). In step  1104 , the system is excited with one or more frequencies in the vicinity of the cutoff frequency of P(s) associated with VCO  101 . In practice, P(s) is typically a single pole function and, hence, only one frequency is generally required in step  1104 . In step  1105 , the frequency response characteristics of equalizer  901  are adjusted to achieve the best null for the frequencies applied to the system in step  1104 . In step  1106 , using calibration source  906  in DC mode, the tuning voltage applied to VCO  101  is swept across a range of values. The function of step  1107  is to determine the voltage that tunes VCO frequency to the frequency of the signal to be measured after calibration is complete. In step  1108 , the tuning voltage is incremented from the determined voltage by a small amount. In step  1109 , the change in the VCO frequency is measured. In step  1110 , the VCO gain parameter (K v ) is calculated. In step  1111 , the calculated value of K v  is used to calculate the gain of phase detector  102  (K d ) and to, thereby, determine the calibration factor for output signal  909 .  
         [0033]    [0033]FIG. 12 depicts mathematical model  1200  that may be used to analyze the calibration algorithm described in connection with FIG. 11. It shall be appreciated that the effect of calibration loop filter  905  may be neglected from the mathematical analysis. As shown in FIG. 12, K v  equals Δf/ΔC(0) where Δf is the change in frequency of VCO frequency in response to the change in the DC value of the calibration source. Then, K v  equals E(0)/K v , because P(0)=1. By utilizing the relationship that if V demod =0, then E(s)=K v K v P(s), the frequency response requirements for E(s) may be determined by observing the nulls produced during the testing methodology discussed with respect to FIG. 11 (see output signal  909  of FIG. 9).  
         [0034]    Phase detectors generally have a limited phase range (typically between 180 to 360 degrees). The amplitude of the modulation outside the loop bandwidth should be confined within this range. Modulation at frequencies within the loop bandwidth is not subject to this constraint. It shall be appreciated that many signals of interest have the characteristic that the phase modulation is large at low frequencies and tapers off at high frequencies. Thus, there are a relatively large number of applications that may utilize PLL demodulators according to embodiments in accordance with the invention.  
         [0035]    For example, FIG. 13 depicts measurement system  1300  that may be used to measure jitter on data signal  1302  according to embodiments in accordance with the invention. Measurement system  1300  is substantially similar to PLL demodulator  900  of FIG. 9 except PLL demodulator  1300  comprises clock/data recovery (CDR) phase detector  1301  which is known in the art for recovering a clock from a data stream. Accordingly, CDR phase detector  1301  may be used to facilitate the measurement of jitter associated with the data. Adder  1301  of PLL demodulator  1300  combines high frequency jitter signal  1304  with the output of equalizer  901  to produce composite jitter signal  1303 . Also, as known in the art, most data transmission systems are associated with jitter specifications that require allowable jitter above a specified frequency to be limited to a moderate value which is typically well within the range of phase detector  1301 . By adapting PLL demodulator  1300  according to embodiments in accordance with the invention, the measurement of jitter by measurement system  1300  is assured of being accurate for high frequency jitter outside the PLL bandwidth.  
         [0036]    As previously noted, phase demodulators may be converted to frequency demodulators by employing a differentiator circuit element. However, it is preferred to avoid cascading leaky integrator  801  with the differentiator circuit element. Therefore, it is advantageous to place the differentiator  1401  before adder  903  and to omit leaky integrator  801  as shown in frequency demodulator  1400  in FIG. 14 according to embodiments in accordance with the invention. By implementing frequency demodulator  1400  in this manner, frequency demodulator  1400  demodulates frequency-modulated reference signal  1402  as demodulated signal  1403 . Moreover, frequency demodulator  1400  shares the advantageous characteristics previously described with respect to phase demodulators implemented according to embodiments in accordance with the invention.  
         [0037]    Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Technology Category: h