Patent Document

FIELD OF THE INVENTION 
     The present invention relates to a charge pump, and more particularly to a charge pump having high charge conversion efficiency. 
     BACKGROUND OF THE INVENTION 
     Currently, a charge pump is often used as a voltage booster or a voltage multiplier to raise an input voltage supplied from a low voltage source to a working voltage having a relatively higher level, so as to supply the high-level working voltage to various driving circuits that require a higher voltage. 
     Please refer to  FIG. 1  that illustrates a prior art Dickson charge pump. As shown, the Dickson charge pump includes four charging capacitors C 1 ˜C 4 , an output capacitor Cout, and five source/drain coupled n-type metal-oxide-semiconductor field-effect (MOS) transistors T 1 ˜T 5 . The Dickson charge pump has an input end and an output end, the voltage levels thereat are represented by Vin and Vout, respectively. The charging capacitors C 1 ˜C 4  are separately used to receive clock signals CK and XCK, so as to increase the voltage level Vin at the input end to the voltage level Vout at the output end. The output voltage level Vout can be represented by: 
     
       
         
           
             Vout 
             = 
             
               
                 ∑ 
                 
                   i 
                   - 
                   1 
                 
                 5 
               
               ⁢ 
               
                 ( 
                 
                   Vin 
                   - 
                   
                     Vt 
                     ⁡ 
                     
                       ( 
                       Mi 
                       ) 
                     
                   
                 
                 ) 
               
             
           
         
       
     
     Where, Vt(Mi) is a threshold voltage of the source/drain coupled n-type MOS transistors T 1 ˜T 5 . However, when multiple stages of transistors are connected in series in the Dickson charge pump, the threshold voltage would increase to thereby reduce the voltage conversion efficiency as being influenced by the so-called body effect. 
       FIG. 2  illustrates another prior art charge pump. As shown, this prior art charge pump includes two charge transfer branches, namely, a first branch A and a second branch B. The first charge transfer branch A includes eight (8) transistors MN 1 ˜MN 4  and MP 1 ˜MP 4 , and four charging capacitors C 1 -C 4 . The second charge transfer branch B includes eight (8) transistors MN 5 ˜MN 8  and MP 5 ˜MP 8 , four charging capacitors C 5 ˜C 8 , and an output capacitor Cout. The charging capacitors C 1 , C 3 , C 6  and C 8  receive clock signals CK and XCK that have a polarity reverse to that of the clock signals CK and XCK received by the charging capacitors C 2 , C 4 , C 5  and C 7 . Therefore, the two charge transfer branches A and B can be considered as two independent and reverse-phase charge pump circuits. In the charge pump shown in  FIG. 2 , the capacitors C 1 -C 8  are off-chip capacitors and therefore the charge pump could not be integrated on a chip. In the case source/drain coupling transistors are used to substitute for the off-chip transistors, the source/drain coupling transistors are subject to breakdown caused by an overly large gate voltage. 
     SUMMARY OF THE INVENTION 
     A primary object of the present invention is to provide a charge pump that is able to solve the problem of failing to integrate the charge pump on a chip as found in the prior art. 
     To achieve the above and other objects, a charge pump capable of amplifying an input voltage received at an input end and outputting the amplified voltage at an output end as an output voltage is provided according to the present invention. The charge pump according to the present invention includes a first clock input, a second clock input, a first cascode section, a second cascode section, a third cascode section, a fourth cascode section, a first source/drain coupling transistor, a second source/drain coupling transistor, a third source/drain coupling transistor, a fourth source/drain coupling transistor, a first diode-connected transistor, a second diode-connected transistor, a first output transistor, and a second output transistor. 
     The first clock input and the second clock input provide a first clock signal and a second clock signal, respectively. The first cascode section includes a first transistor and a second transistor cascode-connected to between the input end and a first point, and a gate of the first transistor and a gate of the second transistor are connected to each other at a first node. The second cascode section includes a third transistor and a fourth transistor cascode-connected to between the input end and a second point, and a gate of the third transistor and a gate of the fourth transistor are connected to each other at a second node. The third cascode section includes a fifth transistor and a sixth transistor cascode-connected to between the first point and the output end, and a gate of the fifth transistor and a gate of the sixth transistor are connected to each other at a third node. The fourth cascode section includes a seventh transistor and an eighth transistor cascode-connected to between the second point and the output end, and a gate of the seventh transistor and a gate of the eighth transistor are connected to each other at a fourth node. The first source/drain coupling transistor has a source and a drain separately coupled to the first clock input, and a gate coupled to the second node. The second source/drain coupling transistor has a source and a drain separately coupled to the second clock input, and a gate coupled to the first node. The third source/drain coupling transistor has a source and a drain separately coupled to the first node, and a gate coupled to the fourth node. The fourth source/drain coupling transistor has a source and a drain separately coupled to the second node, and a gate coupled to the third node. The first diode-connected transistor is connected to between the second node and the third node. The second diode-connected transistor is connected to between the first node and the fourth node. The first output transistor is connected to between the fourth node and the output end by way of diode; and the second output transistor being connected to between the third node and the output end by way of diode. 
     The first clock signal has a polarity reverse to that of the second clock signal. 
     The first node is a connecting point of the cascode-connected first transistor and second transistor; the second node is a connecting point of the cascode-connected third transistor and fourth transistor; the third node is a connecting point of the cascode-connected fifth transistor and sixth transistor; and the fourth node is a connecting point of the cascode-connected seventh transistor and eighth transistor. 
     With the above arrangements, the charge pump of the present invention has one or more of the following advantages: 
     (1) The charge pump substitutes the source/drain coupling transistors for the charging capacitors to thereby enable the integration of the charge pump on a chip. 
     (2) The charge pump is provided with diode-connected transistors to thereby solve the problem of breakdown of transistors. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The structure and the technical means adopted by the present invention to achieve the above and other objects can be best understood by referring to the following detailed description of the preferred embodiments and the accompanying drawings, wherein 
         FIG. 1  illustrates a prior art Dickson charge pump; 
         FIG. 2  illustrates another prior art charge pump; 
         FIG. 3  is a schematic view of a charge pump according to a first embodiment of the present invention; 
         FIG. 4  shows a first clock signal and a second clock signal according to the present invention; 
         FIG. 5  is a schematic view of a charge pump according to a second embodiment of the present invention; 
         FIG. 6  shows the output voltage transient responses of the charge pump according to the second embodiment of the present invention and a prior art charge pump; 
         FIG. 7A  is a graph illustrating the output voltage-output current relationship of the charge pump according to the second embodiment of the present invention and of different prior art charge pumps; and 
         FIG. 7B  is a graph illustrating the conversion efficiency of the charge pump according to the second embodiment of the present invention and of different prior art charge pumps. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention will now be described with some preferred embodiments thereof. For the purpose of easy to understand, elements that are the same in the preferred embodiments are denoted by the same reference numerals. Please refer to  FIG. 3  that illustrates a charge pump according to a first embodiment of the present invention. As shown, the charge pump includes a first clock output CLK, a second clock output CLKB, a first cascode section  31 , a second cascode section  32 , a third cascode section  33 , a fourth cascode section  34 , a first source/drain coupling transistor Mc 1 , a second source/drain coupling transistor Mc 2 , a third source/drain coupling transistor Mc 3 , a fourth source/drain coupling transistor Mc 4 , a first diode-connected transistor Md 1 , a second diode-connected transistor Md 2 , a first output transistor Mo 1 , a second output transistor Mo 2 , and a load capacitor CL. 
     The first clock output CLK provides a first clock signal φ 1 , and the second clock output CLKB provides a second clock signal φ 2 . The first clock signal φ 1  and the second clock signal φ 2  have reversed polarities, as shown in  FIG. 4 . And, the voltage values of the first clock signal φ 1  and the second clock signal φ 2  are switched between zero and Vdd. 
     The first cascode section  31  includes cascode-connected first transistor M 1  and second transistor M 2 , and is connected to between an input end and a first point S 1  while the gates of the first and the second transistor M 1 , M 2  are connected to each other at a first node N 1 . The second cascode section  32  includes cascode-connected third transistor M 3  and fourth transistor M 4 , and is connected to between the input end and a second point S 2  while the gates of the third and the fourth transistor M 3 , M 4  are connected to each other at a second node N 2 . The third cascode section  33  includes cascode-connected fifth transistor M 5  and sixth transistor M 6 , and is connected to between the first point S 1  and an output end while the gates of the fifth and the sixth transistor M 5 , M 6  are connected to each other at a third node N 3 . The fourth cascode section  34  includes cascode-connected seventh transistor M 7  and eighth transistor M 8 , and is connected to between the second point S 2  and the output end while the gates of the seventh and the eighth transistor M 7 , M 8  are connected to each other at a fourth node N 4 . Further, as can be seen from the connection shown in  FIG. 3 , the first node N 1  is the connecting point of the cascode-connected first transistor M 1  and second transistor M 2 , the second node N 2  is the connecting point of the cascode-connected third transistor M 3  and fourth transistor M 4 , the third node N 3  is the connecting point of the cascode-connected fifth transistor M 5  and sixth transistor M 6 , and the fourth node N 4  is the connecting point of the seventh transistor M 7  and eighth transistor M 8 . 
     Preferably, the first transistor M 1 , the third transistor M 3 , the fifth transistor M 5  and the seventh transistor M 7  are n-type Metal-oxide-semiconductor field-effect (MOS) transistors, while the second transistor M 2 , the fourth transistor M 4 , the sixth transistor M 6  and the eighth transistor M 8  are p-type MOS transistors. 
     The first source/drain coupling transistor Mc 1 , the second source/drain coupling transistor Mc 2 , the third source/drain coupling transistor Mc 3 , and the fourth source/drain coupling transistor Mc 4  respectively utilize the parasitic capacitance between source/drain and gate to replace the charging capacitors shown in  FIG. 2  to thereby enable the integration of the charge pump of the present invention on a chip via a standard MOS process. The connection of the source/drain coupling transistors Mc 1 ˜Mc 4  to one another has been shown in  FIG. 3  and is therefore not further described. 
     In  FIG. 4 , there are defined three phases I, II and III. In the first phase I and the third phase III, the first clock signal φ 1  and the second clock signal φ 2  provide a voltage value of zero and Vdd, respectively. Therefore, the first transistor M 1 , the fourth transistor M 4 , the sixth transistor M 6  and the seventh transistor M 7  are ON while the second transistor M 2 , the third transistor M 3 , the fifth transistor M 5  and the eighth transistor M 8  are OFF. In the second phase II, the transistors M 1 ˜M 8  respectively have an ON/OFF state reverse to that in the first phase I or the third phase III. 
     In the first phase I or the third phase III, in which first clock signal φ 1  is low (0V), the voltage values of the first node N 1  and the second node N 2  are increased to 2Vdd and Vdd, respectively; and the voltage values of the third node N 3  and the fourth node N 4  are increased to 3Vdd and 2Vdd, respectively. In the second phase II, in which the first clock signal φ 1  is high (Vdd), the voltage values of the first node N 1  and the second node N 2  are Vdd and 2Vdd, respectively; and the voltage values of the third node N 3  and the fourth node N 4  are 2Vdd and 3Vdd, respectively. Thus, the third source/drain coupling transistor Mc 3  and the fourth source/drain coupling transistor Mc 4  would break down because a voltage difference between the gate and the source/drain exceeds 2Vdd. 
     For the purpose of integrating the charge pump of the present invention on a chip without causing breakdown of the source/drain coupling transistors, the first diode-connected transistor Md 1  is additionally provided between the second node N 2  and the third node N 3 , the second diode-connected transistor Md 2  is additionally provided between the first node N 1  and the fourth node N 4 , the first output transistor Mo 1  is provided between the fourth node N 4  and the output end by way of diode, and the second output transistor Mo 2  is provided between the third node N 3  and the output end by way of diode. 
     After the above-mentioned transistors are provided, in the phases with the first clock signal φ 1  being low (0V), the charge transfer operation is executed along a path from the first transistor M 1  via the first diode-connected transistor Md 1  and the first output transistor Mo 1  to the load capacitor CL at the output end; and in the phase with the first clock signal φ 1  being high (Vdd), the charge transfer path is from the fourth transistor M 4  via the seventh transistor M 7  and the sixth transistor M 6  to the load capacitor CL at the output end. During the course of charge transfer by controlling the charge pump via the clock signals φ 1  and φ 2 , it is able to avoid the source/drain coupling transistors from breakdown due to an exceeded voltage difference of 2Vdd between the gate and the source/drain of the coupling transistors. In addition, it is also able to speed up the charge transfer process to obtain upgraded transfer efficiency. 
     Please refer to  FIG. 5  that is a schematic view of a charge pump according to a second embodiment of the present invention. The second embodiment is different from the first embodiment in that a fifth cascode section  35 , a sixth cascode section  36 , a fifth source/drain coupling transistor Mc 5 , a sixth source/drain coupling transistor Mc 6 , a third diode-connected transistor Md 3 , and a fourth diode-connected transistor Md 4  are further provided in the charge pump. Since all other electronic elements in the second embodiment are connected in manners similar to those in the first embodiment and are illustrated in  FIG. 5 , they are not further described herein. After the above-mentioned additional transistors are added, it is able to generate at the output end an output voltage having a voltage value of 5Vdd. Please refer to  FIG. 6 , which shows the output voltage transient responses of the charge pump according to the second embodiment of the present invention and a prior art charge pump. As shown, after the above-mentioned additional transistors are added, the charge pump of the present invention has a response time from 0V to 5V faster than that of the prior art charge pump. 
       FIG. 7A  illustrates the output voltage-output current relationship of the charge pump according to the second embodiment of the present invention and of different prior art charge pumps, and  7 B illustrates the conversion efficiency of the charge pump according to the second embodiment of the present invention and of different prior art charge pumps. Please refer to  FIGS. 7A and 7B  the same time. As shown, under the same operating conditions, the charge pump of the present invention can generate an output voltage at the output end and provide conversion efficiency higher than those of the prior art charge pumps. 
     In the following Table 1, a comparison of the charge pump of the present invention with other prior art charge pumps is shown. As can be seen from Table 1, under the same operating conditions, the charge pump of the present invention provides higher output voltage and conversion efficiency than the prior art charge pumps. 
     
       
         
               
               
               
               
             
               
               
               
               
               
               
               
             
               
               
               
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
               
               
             
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Dickson 
                 Prior Art 
                 Present 
               
               
                   
                 Charge Pump 
                 Charge Pump 
                 Invention 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 Process 
                 90 
                 nanometer 
                 90 
                 nanometer 
                 90 
                 nanometer 
               
               
                 technology 
               
               
                 Input voltage 
                 1 
                 V 
                 1 
                 V 
                 1 
                 V 
               
               
                 Clock rate 
                 200 
                 MHz 
                 200 
                 MHz 
                 200 
                 MHz 
               
             
          
           
               
                 Off-chip 
                 2 
                 pF 
                 1 
                 pF 
                 None 
               
               
                 capacitor 
               
             
          
           
               
                 MOS capacitor 
                 none 
                 none 
                 1 
                 pF 
               
             
          
           
               
                 Output voltage 
                 1.26 
                 V 
                 3.14 
                 V 
                 3.88 
                 V 
               
               
                 (load 150 μA) 
               
             
          
           
               
                 Conversion 
                 23.9% 
                 57.56% 
                 65.46% 
               
               
                 efficiency 
               
               
                 (load 150 μA) 
               
               
                   
               
             
          
         
       
     
     The present invention has been described with some preferred embodiments thereof and it is understood that many changes and modifications in the described embodiments can be carried out without departing from the scope and the spirit of the invention that is intended to be limited only by the appended claims.

Technology Category: h