Patent Document

BACKGROUND OF THE INVENTION 
     The present invention relates to a starting circuit, and, more particularly, to a starting circuit which produces a starting signal for initializing an internal circuit in a semiconductor integrated circuit device. 
     FIG. 1 shows a conventional starting circuit  51  in a semiconductor integrated circuit device  100 . The starting circuit  51  receives power from a high potential power supply Vcc 1  and a low potential power supply Vss. 
     The starting circuit  51  comprises a voltage-dividing circuit  52 , a first stage section  53  and a waveform shaping circuit  54 . The voltage-dividing circuit  52  includes resistors R 1  and R 2  connected in series between the high potential power supply Vcc 1  and the low potential power supply Vss (0 V). The voltage-dividing circuit  52  supplies the first stage section  53  with a voltage Vn 11  generated by dividing the high potential power supply voltage Vcc 1  in accordance with the ratio of the resistance values of the resistors R 1  and R 2 . 
     The first stage section  53  includes a resistor R 3  and an N-channel MOS transistor (hereinafter simply referred to as an NMOS transistor) TN 1  connected in series between the high potential power supply Vcc 1  and the low potential power supply Vss. The divided voltage Vn 11  is supplied to the gate of the NMOS transistor TN 1  and the NMOS transistor TN 1  goes on or off according to the level of the divided voltage Vn 11 . When the NMOS transistor TN 1  goes off, the first stage section  53  supplies the waveform shaping circuit  54  with an H level (high potential power supply level) signal S 11 . When the NMOS transistor TN 1  goes on, the first stage section  53  supplies the waveform shaping circuit  54  with an L level (low potential power supply level) signal S 11 . 
     The waveform shaping circuit  54  includes a plurality (for example, two) of inverter circuits  55  and  56  connected in series. The first-stage inverter circuit  55  receives the signal S 11  from the first stage section  53 . The waveform shaping circuit  54  waveform-shapes the signal S 11  to produce a starting signal STTZ and supplies it to an internal circuit  57 . 
     When the level of the external power supply (high potential power supply Vcc 1 ) supplied to the semiconductor integrated circuit device  100  starts rising from the off state, a current starts flowing in the resistor R 3  which forms a constant current source. At this time, the divided voltage Vn 11  from the voltage-dividing circuit  52 , as shown in FIG. 2, rises in proportion to the rise of the external power supply voltage Vcc 1 . Because the divided voltage Vn 11  does not exceed a threshold voltage Vthn 1  of the NMOS transistor TN 1  until time t 1 , the NMOS transistor TN 1  is maintained in the off state. Accordingly, the first stage section  53  supplies the H level signal S 11  to the waveform shaping circuit  54  and the starting signal STTZ is set at the H level. In response to a high starting signal STTZ, the internal circuit (including a flip-flop circuit and a latch circuit)  57  is initialized. 
     Further, when the high potential power supply Vcc 1  rises and the divided voltage Vn 11  exceeds the threshold voltage Vthn 1  of the NMOS transistor TN 1  after time t 1 , the NMOS transistor TN 1  is turned on. Consequently, the waveform shaping circuit  54  outputs a low starting signal STTZ. The initialization of the internal circuit  57  is completed in response to the trailing edge of the starting signal STTZ. Subsequently, when the high potential power supply Vcc 1  becomes stable at a normal operating voltage (at which the internal circuit  57  operates normally), the starting circuit  51  holds the starting signal STTZ at the L level. Accordingly, unless the high potential power supply Vcc 1  falls below a predetermined value again, the internal circuit  57  is not reinitialized. Thus, in the semiconductor integrated circuit device  100 , the internal circuit  57  is initialized with the starting signal STTZ of the starting circuit  51  at power-on and malfunctioning of the internal circuit  57  is prevented. 
     If the time t 1  at which the NMOS transistor TN 1  goes on is earlier than the time at which the initialization of the internal circuit  57  is normally completed, the internal circuit  57  (i.e., the semiconductor integrated circuit device  100 ) malfunctions. Accordingly, the ratio of resistance values of the resistors R 1  and R 2  is set so that the divided voltage Vn 11  may exceed the threshold voltage Vthn 1  along with the rise of the high potential power supply voltage Vcc 1  and the time t 1  may be later than the time at which the initialization of the internal circuit  57  is normally completed. 
     Moreover, the threshold voltage Vthn 1  of the NMOS transistor TN 1  varies widely in a range from the maximum threshold voltage Vthn 1 max to the minimum threshold voltage Vthn 1 min due to unevenness in the chip manufacturing process. Therefore, the ratio of resistance values of the resistors R 1  and R 2  is set so that the divided voltage Vn 11  may exceed the maximum threshold voltage Vthn 1 max of the NMOS transistor TN 1 . The time at which the divided voltage Vn 11  exceeds the minimum threshold voltage Vthn 1 min of the NMOS transistor TN 1  is defined as t 2 . The ratio of values of resistance of the resistors R 1  and R 2  is set so that the time t 2  may be later than the time at which the initialization of the internal circuit  57  is normally completed. 
     In recent years, lower voltage power supplies have been replacing high voltage power supplies, and, as shown in FIG. 2, a high potential power supply Vcc 2  having a lower voltage level than the high potential power supply Vcc 1  is used as an operating power supply. However, in using the power supply Vcc 2 , the resistors R 1  and R 2  having the resistance values set for the high potential power supply Vcc 1  are not suitable. Specifically, because a divided voltage Vn 12  at which the high potential power supply voltage Vcc 2  is divided does not exceed the maximum threshold voltage Vthn 1 max, the NMOS transistor TN 1  does not go on. Accordingly, the starting signal STTZ does not fall to the L level and the initialization of the internal circuit  57  is not completed. 
     Therefore, the ratio of resistance values of the resistors R 1  and R 2  is changed so that a divided voltage Vn 13  of the power supply Vcc 2  may exceed the maximum threshold voltage Vthn 1 max. Accordingly, the starting circuit  11  can output the L level starting signal STTZ. 
     However, due to the variation in the ratio of resistance of the resistors R 1  and R 2 , the time t 3  at which the divided voltage Vn 13  exceeds the minimum threshold voltage Vthn 1 min is reached more quickly. Accordingly, before the initialization of the internal circuit  57  is normally completed, the starting signal STTZ may fall. In other words, if the time t 3  at which the starting signal STTZ falls to the L level is too quick and the initialization of the internal circuit  57  is not completed normally, a malfunction may occur in the semiconductor integrated circuit device  100 . Consequently, irrespective of how the ratio of resistance of the resistors R 1  and R 2  is set, the starting circuit  51  cannot produce the starting signal STTZ which falls at the time at which an arbitrary semiconductor integrated circuit device  100  is normally initialized. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a starting circuit which produces a starting signal will surely initialize an internal circuit of a semiconductor integrated circuit device. 
     In one aspect of the present invention, a starting circuit is provided that operates by receiving power from high potential and low potential power supplies. The starting circuit includes a first transistor having a threshold voltage within a predetermined range. The first transistor receives a control voltage generated from the high potential and low potential power supplies and produces a signal from the time when the high potential power supply voltage starts rising to the time when the control voltage rises to the first transistor threshold voltage. A correction circuit is connected to the first transistor and adjusts the control voltage in accordance with the threshold voltage of the first transistor. 
     In another aspect of the present invention, a starting circuit is provided which operates by receiving power from high potential and low potential power supplies. The starting circuit includes a first transistor having a threshold voltage within a predetermined range. The first transistor receives a control voltage generated from the high potential and low potential power supplies and produces a signal from the time when the high potential power supply voltage starts rising to the time when the control voltage rises to the first transistor threshold voltage. A correction circuit is connected to the first transistor adjusts the control voltage in accordance with the threshold voltage of the first transistor. A voltage-dividing circuit divides the voltage of the high and low potential power supplies and generates the control voltage. The voltage-dividing circuit includes a first plurality of resistors connected in series between the high and low potential power supplies. The control voltage is determined by the ratio of the resistance values of the first plurality of resistors. The correction circuit includes a correction voltage-dividing circuit having a second plurality of resistors connected in series between high potential and low potential power supplies. The ratio of resistance values of the second plurality of resistors differs from the ratio of resistance values of the first plurality of resistors. The correction circuit includes a plurality of switching elements for selecting one of a divided voltage generated by the second plurality of resistors and the divided voltage of the voltage-dividing circuit and supplying the selected divided voltage to the first transistor as the control voltage. 
     In yet another aspect of the present invention, a semiconductor integrated circuit device is provide that includes a starting circuit which operates by receiving power from high potential and low potential power supplies. The starting circuit includes a first transistor having a threshold voltage within a predetermined range. The first transistor receives a control voltage generated by the high potential and low potential power supplies and generates a signal from the time when the high potential power supply voltage starts rising to and the time when the control voltage rises to the first transistor threshold voltage. A correction circuit is connected to the first transistor and adjusts the control voltage in accordance with the threshold voltage of the first transistor. A Waveform shaping circuit waveform-shapes the signal from the first transistor and generates a starting signal. An internal circuit is connected to the waveform shaping circuit and performs the initialization operation in response to the signal. 
     Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
     FIG. 1 is a circuit diagram of a conventional starting circuit; 
     FIG. 2 is a timing chart of each voltage of the starting circuit of FIG. 1; 
     FIG. 3 is a circuit diagram of a starting circuit according to a first embodiment of the present invention; 
     FIG. 4 is a timing chart of each voltage of the starting circuit of FIG. 3; 
     FIG. 5 is a circuit diagram of a starting circuit according to a second embodiment of the present invention; 
     FIG. 6 is a circuit diagram of a switching circuit of the starting circuit of FIG. 5; 
     FIG. 7 is a timing chart of each voltage of the starting circuit of FIG. 5; and 
     FIG. 8 is a circuit diagram of a starting circuit according to a third embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
     With reference to FIGS. 3 and 4, a starting circuit  11  of a semiconductor integrated circuit device  110  according to a first embodiment of the present invention is described centered around its differences from the previously discussed conventional starting circuit  51 . In the drawings, the same numerals are used for the same elements throughout. 
     As shown in FIG. 3, the starting circuit  11  comprises a voltage-dividing circuit  12 , a first stage section  53  and a waveform shaping circuit  54 . The first stage section  53  includes a resistor R 3  and an N-channel MOS transistor (hereinafter referred to as a first transistor) TN 1  connected in series between a high potential power supply Vcc 2  and a low potential power supply Vss (0 V). 
     The voltage-dividing circuit  12  includes resistors R 4  and R 5  and a correction circuit  13  connected in series between the high potential power supply Vcc 2  and the low potential power supply Vss (0 V). The correction circuit  13  preferably includes an N-channel MOS transistor (hereinafter a second transistor) TN 2 . The gate and drain of the second transistor TN 2  are connected to each other. A node N 1  between the resistors R 4  and R 5  is connected to the gate of the first transistor TN 1 . 
     The second transistor TN 2  is turned off until its gate voltage (drain voltage) exceeds a threshold voltage Vthn 2 . The voltage-dividing circuit  12  supplies a divided voltage Vn to the first stage section  53  until the voltage provided by the high potential power supply Vcc 2  exceeds the threshold voltage Vthn 2  of the second transistor TN 2 . The voltage-dividing circuit  12  supplies the voltage at the node N 1  (the divided voltage Vn) to the first stage section  53  when the high potential power supply voltage Vcc 2  exceeds the threshold voltage Vthn 2  of the second transistor TN 2 . The divided voltage Vn is a voltage (Vthn 2 +{(Vcc 2 −Vthn 2 )×R 5 /(R 4 +R 5 )}) generated by adding the threshold voltage Vthn 2  of the second transistor TN 2  and a voltage into which the voltage (Vcc 2 −Vthn 2 ) between the high potential power supply Vcc 2  and the drain of the second transistor TN 2  is divided according to the ratio of the resistance values of the resistors R 4  and R 5 . 
     The divided voltage Vn rises quickly to a high value, as the threshold voltage Vthn 2  of the second transistor TN 2  is relatively large. 
     The threshold voltage Vthn 2  of the second transistor TN 2  is set at a lower value than the threshold value Vthn 1  of the first transistor TN 1 . In other words, the gate length of the second transistor TN 2  is made shorter than the gate length of the first transistor TN 1 . Moreover, because the first and second transistors TN 1  and TN 2  are manufactured using the same process, they have the same electrical characteristics. Accordingly, the threshold voltage Vthn 2  of the second transistor TN 2  and the threshold voltage Vthn 1  of the first transistor TN 1  vary in the same manner. Consequently, the correction circuit  13  corrects the divided voltage Vn so that is rises quickly to a high value as the threshold voltage Vthn 1  of the first transistor TN 1  is relatively large. 
     Hence, the correction circuit  13  increases the divided voltage Vn by the threshold voltage Vthn 2  of the second transistor TN 2 , which varies in accordance with unevenness in the threshold voltage Vthn 1  of the first transistor TN 1 . That is, the correction circuit  13  adjusts the divided voltage Vn in accordance with the threshold voltage Vthn 1  of the first transistor TN 1 . 
     The divided voltage Vn is applied to the gate of the first transistor TN 1  of the first stage section  53  and the first transistor TN 1  turns on or off depending on the divided voltage Vn. The first stage section  53  supplies an H level (high potential power supply level) signal S 11  to the waveform shaping circuit  54  when the first transistor TN 1  is turned off. Conversely, the first stage section  53  supplies an L level (low potential power supply level) signal S 11  to the waveform shaping circuit  54  when the first transistor TN 1  is turned on. 
     The drain of the first transistor TN 1  is connected to an inverter circuit  55  of the waveform shaping circuit  54  and the signal S 11  from the first stage section  53  is supplied to the inverter circuit  55 . The waveform shaping circuit  54  waveform-shapes the signal S 11  and supplies a waveform-shaped signal to an internal circuit (including a flip-flop circuit and a latch circuit)  57  as a starting signal STTZ. 
     Next, with reference to the timing chart of FIG. 4, the operation of the starting circuit  11  is described. 
     Now, assume the threshold voltage of the first transistor TN 1  is the maximum value (maximum threshold voltage) Vthn 1 max. In this case, the second transistor TN 2  also has substantially the maximum threshold voltage (maximum threshold voltage Vthn 2 max) since they are made using the same process at the same time. 
     When the external power supply (high potential power supply Vcc 2 ) supplied to the semiconductor integrated circuit device  110  starts rising, a current starts flowing in the resistor R 3 . Until the high potential power supply voltage Vcc 2  exceeds the maximum threshold voltage Vthn 2 max of the second transistor TN 2 , the divided voltage Vn 1  rises substantially at the same rate as the high potential power supply voltage Vcc 2 . Subsequently, the divided voltage Vn 1  (Vthn 2 max+{(Vcc 2 −Vthn 2 max)×R 5 /(R 4 +R 5 )}) rises at a smaller rate of increase than the high potential power supply Vcc 2  in proportion to the rise of the external power supply voltage (high potential power supply voltage Vcc 2 ). Because the divided voltage Vn 1  does not exceed the maximum threshold voltage Vthn 1 max of the first transistor TN 1  up to time t 11 , the first transistor TN 1  is turned off. Accordingly, the first stage section  53  supplies the H level signal S 11  to the waveform shaping circuit  54  and the starting signal STTZ is maintained at the H level. The internal circuit  57  is initialized in response to the high starting signal STTZ. Besides, the divided voltage Vn 1  is set to a higher potential than the divided voltage Vn due to the resistors R 4  and R 5  by the maximum threshold voltage Vthn 2 max of the second transistor TN 2 . Accordingly, the divided voltage Vn 1  is adjusted to exceed the maximum threshold voltage Vthn 1 max of the first transistor TN 1 . 
     When the high potential power supply Vcc 2  rises and the divided voltage Vn 1  exceeds the maximum threshold voltage Vthn 1 max of the first transistor TN 1 , the first transistor TN 1  goes on and the starting signal STTZ falls to the L level. The time t 11  at which the first transistor TN 1  turns on is set later than the time at which the initialization of the internal circuit  57  is completed. The initialization of the internal circuit  57  is completed in response to the trailing edge of the starting signal STTZ. Subsequently, when the high potential power supply Vcc 2  becomes stable at a normal operating voltage (at which the internal circuit  57  operates normally), the starting circuit  51  maintains the starting signal STTZ at the L level. Accordingly, unless the high potential power supply Vcc 2  falls below a predetermined value, the internal circuit  57  is not initialized again. 
     Next, regarding the case where the threshold voltage of the first transistor TN 1  has the minimum value (minimum threshold voltage) Vthn 1 min due to the manufacturing process, a change in each voltage is described. In this case, the second transistor TN 2  also has the minimum threshold voltage Vthn 2 min. 
     When the external power supply (high potential power supply Vcc 2 ) starts rising, the divided voltage Vn 2  rises substantially at the same rate as the high potential power supply voltage Vcc 2  until the high potential power supply voltage Vcc 2  exceeds the minimum threshold voltage Vthn 2 min of the second transistor TN 2 . Subsequently, the divided voltage Vn 2  (Vthn 2 min+{(Vcc 2 −Vthn 2 min)×R 5 /(R 4 +R 5 )}) rises at a lower rate of increase than the high potential power supply Vcc 2  in proportion to the rise of the high potential power supply voltage Vcc 2 . Because the divided voltage Vn 2  does not exceed the minimum threshold voltage Vthn 1 min of the first transistor TN 1  up to time t 12 , the first transistor TN 1  is turned off. Accordingly, the first stage section  53  supplies the H level signal S 11  to the waveform shaping circuit  54  and the starting signal STTZ is maintained at the H level. The internal circuit  57  is initialized in response to a starting signal STTZ High. The divided voltage Vn 2  is adjusted by the the correction circuit  13  so as to rise to a higher potential than the divided voltage Vn according to the resistors R 4  and R 5  by the minimum threshold voltage Vthn 2 min of the second transistor TN 2 . 
     When the high potential power supply voltage Vcc 2  rises and the divided voltage Vn 2  exceeds the minimum threshold voltage Vthn 1 min of the first transistor TN 1 , the first transistor TN 1  goes on and the starting signal STTZ is set at the L level. The time t 12  at which the first transistor TN 1  is turned on is set later than the time the initialization of the internal circuit  57  is completed in the same manner as the time t 11 . The initialization of the internal circuit  57  is completed in response to the trailing edge of the starting signal STTZ. Subsequently, when the high potential power supply Vcc 2  becomes stable at a normal operating voltage (at which the internal circuit  57  operates normally), the starting circuit  51  maintains the starting signal STTZ at the L level. Accordingly, the internal circuit  57  is not initialized again unless the high potential power supply Vcc 2  falls below a predetermined value. Thus, the internal circuit  57  is initialized by the starting circuit  51  when the power of the semiconductor integrated circuit device  110  is turned on and malfunctioning of the internal circuit  57  (i.e., semiconductor integrated circuit device  110 ) is prevented. 
     The divided voltages Vn 1  and Vn 2  and times t 11  and t 12  are set according to the ratio of resistance values of the resistors R 4  and R 5 . The ratio of resistance values of the resistors R 4  and R 5  is set so that the time t 11  at which the divided voltage Vn 1  exceeds the maximum voltage Vthn 1 max and the time t 12  at which the divided voltage Vn 2  exceeds the minimum threshold voltage Vthn 1 min are later than the time at which the initialization of the internal circuit  57  is normally completed. 
     As described above, according to the starting circuit  11  of the first embodiment, the threshold voltage Vthn 2  of the second transistor TN 2  is set lower than the threshold voltage Vthn 1  of the first transistor TN 1 . The threshold voltages Vthn 1  and Vthn 2  of the first and second transistors TN 1  and TN 2  have substantially the same electrical characteristics. Accordingly, the divided voltage Vn is automatically adjusted to a high voltage by the threshold voltage Vthn 2  of the second transistor TN 2 . Consequently, even if unevenness occurs in the threshold voltages Vthn 1  and Vthn 2 , the times t 11  and t 12  at which the divided voltage Vn exceeds the threshold voltages Vthn 1  to Vthn 1 min are set later than the time at which the initialization of the internal circuit  57  is normally completed. Accordingly, even if the external power supply is a relatively low high potential power supply Vcc 2 , the starting circuit  11  produces the starting signal STTZ in accordance with unevenness of the threshold voltage Vthn 1  of the first transistor TN 1 . As a result, the internal circuit  57  is surely initialized. 
     Second Embodiment 
     With reference to FIGS. 5 to  7 , a starting circuit  21  according to a second embodiment of the present invention is described below. As shown in FIG. 5, the starting circuit  21  includes a voltage-dividing circuit  22 , a correction voltage-dividing circuit  23 , a switching circuit  24 , a first stage section  53  and a waveform shaping circuit  54 . 
     The voltage-dividing circuit  22  includes resistors R 6  and R 7  connected in series between a high potential power supply Vcc 2  and a low potential power supply Vss (0 V). A node N 2  between the resistors R 6  and R 7  is connected to the gate of a first transistor TN 1  of the first stage section  53  via a fuse F 1  which functions as a switching element. The voltage-dividing circuit  22  supplies the first stage section  53  with a divided voltage Vn 3  at which the high potential power supply voltage Vcc 2  is divided according to the ratio of resistance values of the resistors R 6  and R 7  when the fuse F 1  is not broken. When the fuse F 1  is broken, the voltage-dividing circuit  22  is not connected with the first stage section  53 . 
     The correction voltage-dividing circuit  23  includes three resistors R 8  to R 10  connected in series between the high potential power supply Vcc 2  and the low potential power supply Vss (0 V). Fuses F 2  and F 3  which function as switching elements are connected to a node N 3  between the resistors R 8  and R 9  and to a node N 4  between the resistors R 9  and R 10 , respectively. The correction voltage-dividing circuit  23  sets the potential of a node N 5  between the fuses F 2  and F 3  to a divided voltage Vn 4  (Vcc 2 ×(R 9 +R 10 )/(R 8 +R 9 +R 10 )) at which the high potential power supply voltage Vcc 2  is divided according to the ratio of resistance values between the resistors R 8 , R 9  and R 10  when the fuse F 3  is broken. When the fuse F 2  is broken, the correction voltage-dividing circuit  23  sets the potential of the node N 5  to a divided voltage Vn 5  (Vcc 2 ×R 10 /(R 8 +R 9 +R 10 )) at which the high potential power supply voltage Vcc 2  is divided in accordance with the ratio of resistance values between the resistors R 8  or R 9  and R 10 . The fuses F 1  to F 3 , the switching circuit  24  and the correction voltage-dividing circuit  23  form a correction circuit  25 . 
     As shown in FIG. 6, the switching circuit  24  includes an NMOS transistor TN 3 , and a resistor R 11  and a fuse F 4  connected in series between the high potential power supply Vcc 2  and the low potential power supply Vss (0 V). The gate of the NMOS transistor TN 3  is connected to a node N 6  between the resistor R 11  and the fuse F 4 . 
     The NMOS transistor TN 3  is connected between the node N 5  and the gate of the first transistor TN 1 . The switching circuit  24  sets the potential of the node N 6  at the L level (low potential power supply level) when the fuse F 4  is not broken. At this time, the NMOS transistor TN 3  is turned off and the nonconductive state is set between the node N 5  and the gate of the first transistor TN 1 . Moreover, the switching circuit  24  sets the potential of the node N 6  at the H level (high potential power supply level) when the fuse F 4  is broken. At this time, the NMOS transistor TN 3  is turned on and the nonconductive state is set between the node N 5  and the gate of the first transistor TN 1 . Consequently, the correction voltage-dividing circuit  23  supplies the divided voltage Vn 4  to the first stage section  53  when the fuses F 1 , F 3  and F 4  are broken. Moreover, the correction voltage-dividing circuit  23  supplies a divided voltage Vn 5  to the first stage section  53  when the fuses F 1 , F 2  and F 4  are broken. The resistance values of the resistors R 6  to R 10  are set so that the sizes of the respective divided voltages Vn 3 , Vn 4  and Vn 5  are Vn 4 &gt;Vn 3 &gt;Vn 5 . 
     The first stage section  53  comprises the resistor R 3  and the first transistor TN 1  connected in series between the high potential power supply Vcc 2  and the low potential power supply Vss. Any one of the divided voltages Vn 3 , Vn 4  and Vn 5  is supplied to the gate of the first transistor TN 1  and the first transistor TN 1  goes on or off in response to the divided voltages Vn 3 , Vn 4  and Vn 5 . 
     As shown in FIG. 7, time t 21  at which the first transistor TN 1  goes on is set later than the time at which the initialization of an internal circuit  57  is normally completed. The ratio of resistance values of the resistors R 6  and R 7  is set so that the divided voltage Vn 3  rises to the vicinity of the maximum threshold voltage Vthn 1 max. Moreover, the ratio of resistance values of the resistors R 6  and R 7  is set so that the time t 21  at which the divided voltage Vn 3  exceeds the mean threshold voltage Vthn 1  is later than the normal completion timing of the initialization of the internal circuit  57 . 
     The ratio of resistance values between the resistors R 8 , R 9  and R 10  is set so that the divided voltage Vn 4  will exceed the maximum threshold voltage Vthn 1 max. The ratio of resistance values between the resistors R 8 , R 9  and R 10  is set so that the time t 21  at which the divided voltage Vn 4  exceeds the maximum threshold voltage Vthn 1 max is later than the normal completion timing of the initialization of the internal circuit  57 . 
     The ratio of resistance values between the resistors R 8 , R 9  and R 10  is set so that the divided voltage Vn 5  rise to the vicinity of the mean threshold voltage Vthn 1 . Moreover, the ratio of resistance values between the resistors R 8 , R 9  and R 10  is set so that the time t 21  at which the divided voltage Vn 5  exceeds the vicinity of the minimum threshold voltage Vthn 1 max is later than the normal completion timing of the initialization of the internal circuit  57 . 
     Next, with reference to FIG. 7, the change of the divided voltage Vn 3  is described for the case where the first transistor TN 1  has the mean threshold voltage Vthn 1 . In this case, the respective fuses F 1  to F 4  are not broken and the first stage section  53  receives the divided voltage Vn 3  from the voltage-dividing circuit  22 . 
     As shown in FIG. 7, when the high potential power supply voltage Vcc 2  starts rising, the divided voltage Vn 3  rises in proportion to the rise of the high potential power supply voltage Vcc 2 . Because the divided voltage Vn 3  does not exceed the mean threshold voltage Vthn 1  of the first transistor TN 1  up to the time t 21 , the first transistor TN 1  is turned off. Accordingly, the first stage section  53  supplies an H level signal S 11  to the waveform shaping circuit  54  and a starting signal STTZ is set at the H level. The internal circuit  57  is initialized in response to a starting signal STTZ High. 
     When the high potential power supply Vcc 2  rises and the divided voltage Vn 3  exceeds the mean threshold voltage Vthn 1  of the first transistor TN 1 , the first transistor TN 1  goes on and the starting signal STTZ is set at the L level. The time at which the first transistor TN 1  is turned on is substantially the same as the time t 21  and is later than the time at which the initialization of the internal circuit  57  is completed. The initialization of the internal circuit  57  is completed in response to the trailing edge of the starting signal STTZ. Subsequently, when the high potential power supply voltage Vcc 2  becomes stable at a normal operating voltage (at which the internal circuit  57  operates normally), the starting circuit  21  maintains the starting signal STTZ at the L level. 
     Next, the change of the divided voltage Vn 4  is described for the case where the first transistor TN 1  has the maximum threshold voltage Vthn 1 max. In this case, the fuses F 1 , F 3  and F 4  corresponding to the maximum threshold voltage Vthn 1 max are broken. Accordingly, the divided voltage Vn 4  is supplied from the correction voltage-dividing circuit  23  to the first stage section  53 . 
     When the high potential power supply Vcc 2  begins to rise, the divided voltage Vn 4  rises in proportion to the rise of the high potential power supply voltage Vcc 2 . Because the divided voltage Vn 4  does not exceed the maximum threshold voltage Vthn 1 max of the first transistor TN 1  up to the time t 21 , the first transistor TN 1  is turned off. Accordingly, the first stage section  53  supplies the H level signal S 11  to the waveform shaping circuit  54  and the starting signal STTZ is set at the H level. The internal circuit  57  is initialized in response to the starting signal STTZ High. 
     When the high potential power supply Vcc 2  rises further and the divided voltage Vn 4  exceeds the maximum threshold voltage Vthn 1 max of the first transistor TN 1 , the first transistor TN 1  goes on and the starting signal STTZ is set at the L level. The time at which the first transistor TN 1  goes on is substantially the same as the time t 21  and is later than the time at which the initialization of the internal circuit  57  is completed. The initialization of the internal circuit  57  is completed in response to the trailing edge of the starting signal STTZ. Subsequently, when the high potential power supply voltage Vcc 2  becomes stable at a normal operating voltage (at which the internal circuit  57  operates normally), the starting circuit  21  holds the starting signal STTZ at the L level. 
     Next, the change of the divided voltage Vn 5  is described for the case where the first transistor TN 1  has the minimum threshold voltage Vthn 1 min. In this case, the fuses F 1 , F 2  and F 4  corresponding to the minimum threshold voltage Vthn 1 min are broken. Accordingly, the divided voltage Vn 5  is supplied from the correction voltage-dividing circuit  23  to the first stage section  53 . 
     When the high potential power supply Vcc 2  begins to rise, the divided voltage Vn 5  rises in proportion to the rise of the high potential power supply voltage Vcc 2 . Because the divided voltage Vn 5  does not exceed the minimum threshold voltage Vthn 1 min of the first transistor TN 1 , the first transistor TN 1  is turned off. Accordingly, the first stage section  53  supplies the H level signal S 11  to the waveform shaping circuit  54  and the starting signal STTZ is set at the H level. The initial circuit  57  is initialized in response to the starting signal STTZ. 
     When the high potential power supply Vcc 2  rises further and the divided voltage Vn 4  exceeds the minimum threshold voltage Vthn 1 min of the first transistor TN 1 , the transistor TN 1  goes on and the starting signal STTZ is set at the L level. The initialization of the internal circuit  57  is completed in response to the trailing edge of the starting signal STTZ. 
     As discussed above, according to the starting circuit  21  of the second embodiment, when the fuses F 1  to F 4  corresponding to the threshold voltage Vthn 1  of the first transistor TN 1  are broken, the ratio of the resistance value of the correction voltage-dividing circuit  23  is easily changed corresponding to the threshold voltage Vthn 1 . Accordingly, the gate voltage of the first transistor TN 1  is surely set higher than the threshold voltage of the first transistor TN 1 . As a result, the starting circuit  21  produces the starting signal STTZ in accordance with unevenness in the threshold voltage of the first transistor TN 1  even for a low high potential power supply Vcc 2 . 
     Third Embodiment 
     With reference to FIG. 8, a starting circuit  31  of a third embodiment of the present invention is described below. The starting circuit  31  of the second embodiment differs from the conventional starting circuit  51  in the configuration of a voltage-dividing circuit  32 . 
     The voltage-dividing circuit  32  includes resistors R 11 , R 12 , R 13  and R 14  connected in series between a high potential power supply Vcc 2  and a low potential power supply Vss (0 V). Fuses F 11 , F 12  and F 13  which function as switching elements are connected to nodes N 11 , N 12  and N 13  of the respective resistors R 11  to R 14 , respectively, and a node N 14  of fuses F 11 , F 12  and F 13  is connected to the gate of a first transistor TN 1 . Resistance values of the resistors R 11  to R 14  are set to the same values as the resistors R 6  and R 7  of the second embodiment. The resistance values of the resistors R 12  and R 13  are set to the same values as the resistor R 9  of the second embodiment. The resistance values of the respective resistors R 11  to R 14  may be changed appropriately. 
     The respective fuses F 11  to F 13  are selectively blown or broken in accordance with the threshold voltage of the first transistor TN 1 . The voltage-dividing circuit  32  supplies the gate of the first transistor TN 1  with a voltage Vn 11  generated by dividing the high potential power supply voltage Vcc 2  in accordance with the resistors R 11  to R 14  selected according to the states of the fuses F 11  to F 13 . The voltage-dividing circuit  32  and the fuses F 11  to F 13  form a correction circuit  33 . 
     Immediately after the starting circuit  31  is fabricated, the respective fuses F 11  to F 13  are not broken, but are in the closed-circuit state. At this time, the voltage-dividing circuit  32  supplies the divided voltage Vn 11  at which the high potential power supply voltage Vcc 2  is divided according to the ratio of resistance values of the resistors R 11  to R 14 . The divided voltage Vn 11  rises to equal to or greater than the mean threshold voltage Vthn 1  of the first transistor TN 1  in proportion to the rise of the high potential power supply voltage Vcc 2 . Accordingly, regarding the first transistor TN 1  having the threshold voltage Vthn 1 , the starting circuit  31  outputs a starting signal STTZ which falls from the H level to the L level along with lapse of time (rise of the high potential power supply voltage Vcc 2 ). 
     On one hand, if the transistor TN 1  has the maximum threshold voltage Vthn 1 max, the fuses F 12  and F 13  are broken. Hereupon, the voltage-dividing circuit  31  supplies the gate of the first transistor TN 1  with a divided voltage Vn 12  (Vcc 2 ×(R 12 +R 13 +R 14 )/(R 11 +R 12 +R 13 +R 14 )) generated by dividing the high potential power supply voltage Vcc 2  in accordance with the ratio between the resistance value of the resistor R 11  and the combined resistance values of the resistors R 12  to  14 . This divided voltage Vn 12  is higher than the divided voltage Vn 11  and rises to the maximum threshold voltage Vthn 1 max. 
     Thus, the correction circuit  33  adjusts the divided voltage Vn 12  in accordance with the maximum threshold voltage Vthn 1 max of the first transistor TN 1 . Accordingly, in the first transistor TN 1  having the maximum threshold voltage Vthn 1 max, the starting circuit  31  outputs the starting signal STTZ which changes from the H level to the L level in accordance with the lapse of time (rise of the high potential power supply voltage Vcc 2 ). 
     If the threshold voltage of the first transistor TN 1  varies in value between the maximum threshold voltage Vthn 1 max and the mean threshold voltage Vthn 1 , the fuse F 13  is broken. Thus, the correction circuit  33  corrects the divided voltage Vn 11  in accordance with the threshold voltage of the first transistor TN 1 . 
     On the other hand, if the first transistor TN 1  has the minimum threshold voltage Vthn 1 min, the fuses F 11  and F 12  are broken. Hereupon, the voltage-dividing circuit  32  supplies the gate of the first transistor TN 1  with a divided voltage Vn 13  (Vcc 2 ×(R 14 )/(R 11 +R 12 +R 13 +R 14 )) generated by dividing the high potential power supply voltage Vcc 2  in accordance with the ratio between the combined resistance values of the resistors R 11  to R 13  and the value of resistance of the resistor R 14 . The divided voltage Vn 13  is lower than the divided voltage Vn 11  and rises to the minimum threshold voltage Vthn 1 min. Further, the divided voltage Vn 13  slowly rises at a lower rate than the divided voltage Vn 11 . Accordingly, regarding the first transistor TN 1  having the minimum threshold voltage Vthn 1 min, the starting circuit  31  outputs the starting signal STTZ which falls from the H level to the L level substantially at the same time (time t 21  (see FIG.  7 )) as when the divided voltage Vn 11  is selected. 
     If the threshold voltage of the first transistor Tn 1  varies in value between the maximum threshold voltage Vthn 1 max and the mean threshold voltage Vthn 1 , the fuse F 11  is broken. Thus, the correction circuit  33  corrects the divided voltage Vn 11  in accordance with the threshold voltage of the first transistor TN 1 . 
     As described above, according to the starting circuit  31 , the fuses F 11  to F 13  are broken in accordance with the threshold voltage of the first transistor TN 1 . Accordingly, the divided voltage Vn 11  is optimally corrected, and the time at which the first transistor TN 1  goes on is set to be later than the time at which the normal initialization of the internal circuit  57  is completed. As a result, even if a low high potential power supply Vcc 2  is used, the internal circuit  57  is surely initialized. 
     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the invention may be embodied in the following forms. 
     In the aforementioned embodiments, the first transistor TN 1  may be a P-channel MOS transistor. In this case, between the high potential power supply Vcc 2  and the low potential power supply Vss, the arrangement between a resistor R 3  and the first transistor TN 1  can be replaced. Further, in the first embodiment, a second transistor TN 2  is changed to a P-channel MOS transistor and the P-channel MOS transistor is connected between the high potential power supply Vcc 2  and a resistor R 4 . 
     In the first embodiment, a plurality of the second transistors TN 2  may be connected between a resistor R 5  and the low potential power supply Vss. In this case, the value of the sum of the threshold voltages of a plurality of the second transistors TN 2  is set to be lower than the threshold voltage of the first transistor TN 1 . 
     In the second embodiment, four or more resistors connected in series may also be used instead of three resistors R 8  to R 10 . Nodes between the respective resisters are connected to a node N 5  of FIG. 5 via a fuse. Accordingly, the number of divided voltages supplied to a first stage section  53  is changed to three or more. 
     In the second embodiment, a circuit may also be used instead of the fuses F 1  to F 4  if the divided voltages Vn 3 , Vn 4  and Vn 5  generated in a voltage-dividing circuit  22  and a correction voltage-dividing circuit  23  can be selected. For example, a MOS type transistor may also be used as a switching element. 
     The present examples and embodiments are to be considered as illustrative and not restrictive and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.

Technology Category: 5