Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a PLL (Phase-Locked Loop) circuit. More particularly, the present invention relates to the PLL circuit for reducing a phase offset without an increase in an operation voltage. 
     2. Description of the Related Art 
     Conventionally, a PLL circuit has been known as one of basic techniques used in various fields, for example, such as information processing, communication and the like. This conventional PLL circuit, whose example is shown in FIG. 1, is provided with a phase frequency comparator  50 , a charge pump  51 , a loop filter  52 , a voltage current converter  53 , a current control oscillator  54  and a feedback frequency divider  55 . 
     The phase frequency comparator  50  compares a phase and a frequency of an input signal f REF  with those of a feedback signal f FB  outputted from the feedback frequency divider  55 , respectively, to generate one of an increase signal UP and a decrease signal DOWN which indicate errors between both the signals. For example, a clock signal from an oscillator (not shown) is used as the input signal f REF  The increase signal UP generated by the phase frequency comparator  50  has a pulse width corresponding to a phase delay and a frequency drop of the feedback signal f FB  with respect to the input signal f  REF . Also, the decrease signal DOWN has a pulse width corresponding to a phase advance or leading and a frequency rise or increase of the feedback signal f FB  with respect to the input signal f REF . The increase signal UP and the decrease signal DOWN which are generated by the phase frequency comparator  50  are sent to the charge pump  51 . 
     The charge pump  51  is a charge pump of a single output. The charge pump  51  generates the current pulses corresponding to the respective pulse widths of the increase signal UP and the decrease signal DOWN to send to the loop filter  52 . The loop filter  52  has a resistor R 2  and capacitors C 4 , C 5 . The loop filter  52  accumulates charges in the capacitors C 4 , C 5 , in response to the current pulses sent by the charge pump  51 , and discharges the charges accumulated in the capacitors C 4  ,C 5 , and then generates the voltages corresponding to the current pulses. The voltages generated by the loop filter  52  are sent to the voltage current converter  53 . 
     The voltage current converter  53  converts the voltage outputted from the loop filter  52  into a current to send to the current control oscillator  54 . The current control oscillator  54  generates a signal oscillating at a frequency corresponding to a value of the current sent by the voltage current converter  53 . The current control oscillator  54  oscillates at a frequency equal to N times the frequency of the input signal f REF  at a lock state. The signal generated by the current control oscillator  54  is outputted to external portion as an output signal f OUT  of the PLL circuit, and sent to the feedback frequency divider  55 . The feedback frequency divider  55  performs a frequency division into 1/N on the output signal f OUT  to generate the feedback signal f FB  and send the feedback signal f FB  to the phase frequency comparator  50 . 
     The operations of the conventional PLL circuit having the above-mentioned configuration will be described below. Let us suppose that a phase of the feedback signal f FB  fed back to the phase frequency comparator  50  from the feedback frequency divider  55  is more delayed than a phase of the input signal f REF . 
     In this case, the phase frequency comparator  50  generates the increase signal UP having the pulse width corresponding to the frequency drop and the phase delay to send to the charge pump  51 . The charge pump  51  sends out a current corresponding to the increase signal UP, and charges the capacitors C 4 , C 5  of the loop filter  52 . Thus, the voltage generated by the loop filter  52  is made higher, which thereby increases the current outputted by the voltage current converter  53 . This results in a rise of an oscillation frequency of the output signal f OUT  outputted by the current control oscillator  54 . Also, a phase of the output signal f OUT  is advanced to thereby approach a phase of the input signal f REF  . 
     On the other hand, the case in which the phase of the feedback signal F FB  is more advanced than a phase of the input signal f REF  will be described below. 
     In this case, the phase frequency comparator  50  generates the decrease signal DOWN having the pulse width corresponding to the frequency rise and the phase advance to send to the charge pump  51 . So, the charge pump  51  pulls the current corresponding to the decrease signal DOWN, and discharges the capacitors C 4 , C 5  of the loop filter  52 . Thus, the voltage outputted by the loop filter  52  is made lower, which thereby decreases the current outputted by the voltage current converter  53 . This results in the drop in the oscillation frequency of the output signal f OUT  outputted by the current control oscillator  54 . Also, the phase of the output signal f OUT  is delayed to thereby approach the phase of the input signal f REF  . 
     As mentioned above, the PLL circuit always compares the phase and the frequency of the output signal f OUT  with those of the input signal f REF  , respectively. If there is the phase delay or the phase advance in the output signal f OUT  with respect to the input signal f REF , the feedback control is carried out so as to correct it. If the phase delay or the phase advance is converged within a predetermined range, the phase frequency comparator  50  generates the increase signal UP and the decrease signal DOWN having the same short pulse width. Thus, the amounts of the charges which are charged and discharged in the capacitors C 4 , C 5  of the loop filter  52  are equal to each other and balanced so that the PLL circuit becomes at the lock state. 
     At this lock state, the phase and the frequency of the output signal f OUT  coincide with those of the input signal f REF , respectively. By the way, the charge pump  51  typically has a dead band, in which the charges are never charged and discharged unless there is a phase difference greater than a certain value, with regard to the relation between the phase difference, namely, the phase delay or the phase advance and the amount of the charge to be charged or discharged. Thus, it is designed such that the increase signal and the decrease signal having the same pulse width are generated even at the lock state. 
     The configuration example of another conventional PLL circuit will be described below with reference to FIG.  2 . 
     A charge pump  61  used in this PLL circuit is a differential output pump. That is, the charge pump  61  generates a current pulse OUT 1  corresponding to a pulse width of an increase signal UP and a current pulse OUT 2  corresponding to a pulse width of a decrease signal DOWN, and sends to a first loop filter  62 A and a second loop filter  62 B, respectively. The configurations and the operations of the first loop filter  62 A and the second loop filter  62 B are equal to those of the above-mentioned loop filter  52 . Then, a voltage current converter  53  converts a potential difference between a signal outputted from the first loop filter  62 A and a signal outputted from the second loop filter  62 B into a current signal. 
     According to this PLL circuit, the noise components of a power supply noise, a coupling noise to circuits except the loop filters and the like included in each of the first loop filter  62 A and the second loop filter  62 B are equal with each other, and the noise as a whole is cancelled out by the voltage current converter  53 . That is, the above-mentioned noise has no influence on the potential difference between the first loop filter  62 A and the second loop filter  62 B, which leads to the merit of generating the PLL circuit strong in the noise. 
     By the way, in FIGS. 1 and 2, the capacitors C 5 , C 5 , are mounted so as to weaken a sharp change in a signal waveform caused by a pulse noise or a jitter. Values of capacitances of the capacitors C 5 , C 5 , are further smaller than those of the capacitors C 4 , C 4 , respectively. 
     The above-mentioned explanations are the examples of the typical PLL circuits. A PLL circuit in which the several defects in those conventional PLL circuits are removed is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 8-84073) as a differential current control oscillator having a variable load. FIG. 3 shows the configuration of the main portion of this PLL circuit. 
     This PLL circuit receives an input signal f REF  serving as a reference clock and a feedback signal f FB  from a feedback frequency divider  55  to output a pair of an increase signal UP and a decrease signal DOWN. Also, differential output signals OUTI, OUT 2  outputted from a first charge pump  71 A are sent to capacitors C A  C B  of a loop filter  72 , respectively, and sent through a voltage current converter  53  to a current control oscillator  54 . 
     On the other hand, a current outputted by a second charge pump  71 B is directly outputted to the current control oscillator  54 . An oscillation frequency of the current control oscillator  54  is determined by the current from the voltage current converter  53  and the current from the second charge pump  71 B. An output signal of the current control oscillator  54  is outputted to external portion as an output signal f OUT  and also sent through the feedback frequency divider  55  to the phase frequency comparator  50  as a feedback signal f FB . 
     This PLL circuit has two charge pumps, differently from the PLL circuits shown in FIGS. 1,  2 . 
     When an output current of the charge pump  51  in FIG. 1 is assumed to be I P , a signal processing in the loop filter  52  can be represented as [I p ·(R 2 +1/(s·C 4 ))=I P ·R 2 +I P /(s·C 4 )] as an equation after a Laplace transform in an alternating current theory. A second term on a right side in this equation is an integration term for changing a frequency, and a first term on the right side is a linear term for instantly changing a phase. 
     On the contrary, in the PLL circuit of FIG. 3, the first charge pump  71 A controls the frequency (integration term), and the second charge pump  71 B controls the phase (linear term). By the way, as for the linear term, the second charge pump  71 B may be designed such that when a gain of the voltage current converter  53  is assumed to be [g vi  ], a current value of [I P ·R 2 ·g vi ] is directly inputted to the current control oscillator  54 . 
     As mentioned above, since the charge pump is divided into two sections, the resistor elements R 2 , R 2 ′ are unnecessary which constitute the loop filter  52 ,  62 A or  62 B as shown in FIGS. 1,  2 . As a result, since an area of a chip for forming a resistor is not required, this provides a merit of largely contributing to an improvement of an integration degree. Usually, a value of the resistor R 2  is in a range between 100 KΩ and 10 MΩ. The resistor occupies a region between 100 μm angle and 1 mm angle in the area of the chip. Thus, the fact that this resistor is not required can largely contribute to the improvement of the integration degree. 
     By the way, the charge pump  51  of the PLL circuit shown in FIG. 1 is constituted, for example, as shown in FIG.  4 . In this charge pump  51 , a P-channel MOS transistor Q 10  is turned on in response to the increase signal UP. Thus, the charges are charged into the capacitance elements (capacitors C 4 , C 5 ) of the loop filter  52  from a power supply V DD . Also, an N-channel MOS transistor Q 11  is turned on in response to the decrease signal DOWN. Hence, the charges accumulated in the capacitance elements of the loop filter  52  are discharged. 
     However, this conventional charge pump  51  has the following problem. 
     At the lock state, the pulse width of the increase signal UP is equal to that of the decrease signal DOWN. Thus, the amount of the charges charged into the capacitance elements of the loop filter  52  should be equal to the amount of the charges discharged from the capacitance elements. However, the problem lies in a fact that the amounts are different from each other because of the following two reasons. 
     The first reason is as follows. 
     That is, when the P-channel MOS transistor Q 10  acting as a switch is turned on, a voltage applied between a source and a drain of a P-channel MOS transistor Q 9  acting as a constant current source is changed depending on the voltage of the loop filter  52 . Similarly, when the N-channel MOS transistor Q 11  acting as a switch is turned on, a voltage applied between a source and a drain of an N-channel MOS transistor Q 12  acting as a constant current source is changed depending on the voltage of the loop filter  52 . In any case, the amount of the charges flowing into the loop filter  52  in a unit time, or the amount of the charges flowing out from the loop filter  52  in the unit time is changed depending on the voltage of the loop filter  52 . Here, as for the amounts changed depending on the voltage of the loop filter  52  with regard to the amounts of the charges, the changed amount on the side of the P-channel MOS transistor Q 9  connected to the power supply V DD  is directionally opposite to the charged amount on the side of the N-channel MOS transistor Q 12  connected to a ground. As a result, even if the increase signal UP and the decrease signal DOWN are the pulses having the same length, the amounts of the charges which are charged into and discharged from the capacitance elements of the loop filter  52  are different from each other. 
     The second reason is as follows. 
     That is, a factor on a manufacturing process and the like cause respective parasitic capacitances generated in the P-channel MOS transistor and the N-channel MOS transistor to be different from each other. As a result, the amounts of the charges when the charges are charged into or discharged from the parasitic capacitances are changed depending on the output voltage of the loop filter  52 , namely, the oscillation frequency. Moreover, they are never cancelled out. 
     This results in a situation that the capacitance elements of the loop filter  52  is charged, for example, at a substantially excessive state. The occurrence of this situation causes the oscillation frequency to be higher, and also makes the phase of the output signal f OUT  more advanced than that of the input signal f REF . So, the adjustment is done such that the pulse width of the decrease signal DOWN is made longer, and the amount of the charges discharged from the capacitance elements of the loop filter  52  becomes zero. And, it is balanced at this state. Thus, although the frequency of the input signal f REF  is synchronous with that of the output signal F OUT , a so-called phase offset is induced in which the phase of the output signal F OUT  is still advanced with respect to that of the input signal f REF  and it becomes at the lock state. 
     A problem corresponding to the first reason can be solved by using a circuit technique of a cascade connection used in a PLL circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 8-84073). However, the usage of the cascade connection brings about a problem that a high operation voltage must be supplied. So, a PLL circuit is desirable which does not use the cascade connection. 
     Also, another problem corresponding to the second reason can be solved by configuring a switching circuit with a differential circuit, such as the PLL circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 8-84073). However, the configuration achieves a certain measure of the solution and it is insufficient. 
     The following technique is disclosed in a paper by Ilya I. Novof, John Austin, Ram Kelkar, Don Strayer, and Steve Wyatt with a title of “Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ± ps Jitter” in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, No. 11, NOVEMBER 1995, pp 1259˜1266. That is to say, a fully integrated phase-locked loop (PLL) in a digital 0.5 μm CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than ±100 ps with a peak-to-peak jitter of ±50 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator. 
     The following technique is disclosed in U.S. Pat. No. 5,619,161 (US005619161A) by Novof et al. That is to say, a phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no “dead zone”. A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition. 
     SUMMARY OF THE INVENTION 
     The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a PLL circuit that can protect a phase offset from occurring. Another object of the present invention is to provide a PLL circuit that can reduce an operation voltage to a low voltage. 
     In order to achieve an aspect of the present invention, a PLL circuit, includes: a comparator comparing a phase of an input signal with a phase of a feedback signal to generate a comparison result; an integrator generating a first current to control an oscillation frequency of an output signal based on the comparison result; a phase controller controlling a phase of the output signal based on the comparison result such that a phase difference between the phase of the input signal and the phase of the output signal at a lock state is reduced to generate a second current; a current control oscillator generating the output signal, the output signal oscillating at a frequency corresponding to a third current, wherein the first current and the second current add up to the third current; and a feedback frequency divider performing a frequency division on the output signal to generate the feedback signal to send to the comparator. 
     In this case, the phase controller protects a phase offset. 
     Also in this case, the comparator compares a frequency of the input signal with a frequency of the feedback signal in addition to the comparing the phase of the input signal with the phase of the feedback signal, to generate the comparison result. 
     Further in this case, the integrator includes a first charge pump, a first loop filter and a first voltage current converter, and wherein the first charge pump has a single output section, the single output section outputting a single current corresponding to the comparison result, and wherein the first loop filter has a first capacitor connected to the single output section and wherein the first voltage current converter converts a voltage generated by the first loop filter into the first current. 
     In this case, the integrator includes a specific first charge pump, a specific first loop filter and a specific first voltage current converter, and wherein the specific first charge pump has specific first and second output sections, the s specific first and second output sections outputting specific currents corresponding to the comparison result, respectively, and wherein the specific first loop filter has a specific first capacitor connected to the specific first output section and a specific second capacitor connected to the specific second output section and wherein the specific first voltage current converter converts a specific voltage generated by the specific first loop filter into the first current. 
     Also in this case, the integrator further includes a specific first common-mode voltage controller maintaining a specific first potential inputted to the specific first voltage current converter within a specific first predetermined range. 
     Further in this case, a PLL circuit further includes: a clock tree synthesis buffer section inputting the output signal from the current control oscillator to output to the feedback frequency divider. 
     In this case, the phase controller includes a differential charge pump having first and second output sections, the first and second output sections outputting currents corresponding to the comparison result, respectively and being connected to each other through a resistor. 
     Also in this case, a value of the resistor is 1 KΩ. 
     Further in this case, the phase controller includes a voltage current converter converting a potential difference across the resistor into the second current. 
     In this case, the phase controller includes a loop filter having the resistor and a first capacitor connected to the first output section and a second capacitor connected to the second output section. 
     Also in this case, the first and second capacitors protect a sharp voltage variation caused by a pulse noise, respectively. 
     Further in this case, the phase controller includes a common-mode voltage controller maintains a potential inputted to the voltage current converter within a predetermined range. 
     In this case, a voltage of a predetermined value is supplied to a middle point of the resistor such that a potential inputted to the voltage current converter is maintained within a predetermined range. 
     Also in this case, the phase controller includes a specific loop filter having the resistor and a third capacitor connected with the first and second output sections. 
     Further in this case, a voltage of a predetermined value is supplied to a middle point of the resistor. 
     In this case, the differential charge pump includes first and second circuits, and wherein the first circuit includes a first constant current source and a first P channel MOS transistor and a first N channel MOS transistor in series, a first connecting point between the first P channel MOS transistor and the first N channel MOS transistor corresponding to the first output section, and wherein the second circuit includes a second constant current source and a second P channel MOS transistor and a second N channel MOS transistor in series, a second connecting point between the second P channel MOS transistor and the second N channel MOS transistor corresponding to the second output section. 
     Also in this case, the differential charge pump is constituted without using a circuit technique of a cascade connection. 
     Further in this case, the first and second output sections are connected to each other through a wiring instead of the resistor. 
     In this case, the differential charge pump has a dead band in which a charge is never charged or discharged unless there is a specific phase difference greater than a set value between the phase of the input signal with the phase of the feedback signal. 
     According to a PLL circuit of the present invention, a phase controller generates a current pulse only for a short time in accordance with a comparison result from a phase frequency comparator to control a phase of an output signal. Accordingly, a phase offset, which is a phase difference between an input signal and an output signal that is induced at a lock state, can be reduced to thereby protect the phase offset from occurring. 
     According to this configuration, the circuit technique of the cascade connection described in the column of the conventional technique becomes unnecessary to thereby provide a merit that the PLL circuit can be operated at a low voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing a configuration example of a conventional PLL circuit; 
     FIG. 2 is a block diagram showing a configuration example of a conventional another PLL circuit; 
     FIG. 3 is a block diagram showing a configuration example of a conventional still another PLL circuit; 
     FIG. 4 is a circuit diagram showing a detailed configuration of a charge pump and a loop filter in the conventional PLL circuit; 
     FIG. 5 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention; 
     FIG. 6 is a circuit diagram showing a configuration of first and second charge pumps in FIG. 5; and 
     FIG. 7 is a circuit diagram showing a variation of the second loop filter in FIG.  5 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the present invention will be described below with reference to the attached drawings. 
     FIG. 5 is a block diagram showing the configuration of a PLL circuit according to the embodiment of the present invention. This PLL circuit is provided with a phase frequency comparator  10 , an integrator  20 , a phase controller  21 , a current control oscillator  14 , a CTS buffer  15  and a feedback frequency divider  16 . 
     The phase frequency comparator  10  compares a phase and a frequency of an input signal f REF  with those of a feedback signal f FB  from the feedback frequency divider  16 , respectively, to generate an increase signal UP and a decrease signal DOWN which indicate errors of both the signals. For example, a clock signal from an oscillator (not shown) is used as the input signal f REF . The increase signal UP generated by the phase frequency comparator  10  has a pulse width corresponding to a phase delay of the feedback signal f FB  with respect to the input signal f REF . Also, the decrease signal DOWN has a pulse width corresponding to a phase advance of the feedback signal f FB  with respect to the input signal f REF . The increase signal UP and the decrease signal DOWN which are generated by the phase frequency comparator  10  are sent to the integrator  20  and the phase controller  21 . 
     The integrator  20  is composed of a first charge pump  11 A, a first loop filter  12 A, a first voltage current converter  13 A and a first common-mode voltage controller  17 A. The first charge pump  11 A is a charge pump of a differential output. For example, as shown in FIG. 6, the first charge pump  11 A is composed of a drive signal generator  110 , a first circuit  111  and a second circuit  112 . 
     As shown in FIG. 6, the drive signal generator  110  generates signals ┐U (hereafter, “┐” implies an inversion), D to drive the first circuit  111  and, signals ┐D , U to drive the second circuit  112 . This drive signal generator  110  is composed of inverters INV 1  to INV 4  and delay circuits DLY 1  and DLY 2 . The respective inverters INV 1  to INV 4  have the same electric characteristics, and the delay circuits DLY 1  and DLY 2  have the same delay characteristics as the inverters INV 1  to INV 4 . 
     The increase signal UP from the phase frequency comparator  10  is inverted by the inverter INV 1 , and sent to the inverter INV 2  and the delay circuit DLY 1 . The inverter INV 2  inverts the signal from the inverter INV 1 , and sends as the signal U to the second circuit  112 . The delay circuit DLY 1  delays the signal from the inverter INV 1 , and sends as the signal ┐U to the first circuit  111 . Thus, a change timing of the signal ┐U coincides with a change timing of the signal U. 
     Similarly, the decrease signal DOWN from the phase frequency comparator  10  is inverted by the inverter INV 3 , and sent to the inverter INV 4  and the delay circuit DLY 2 . The inverter INV 4  inverts the signal from the inverter INV 3 , and sends as the signal D to the first circuit  111 . The delay circuit DLY 2  delays the signal from the inverter INV 3 , and sends as the signal ┐D to the second circuit  112 . Thus, a change timing of the signal ┐D coincides with a change timing of the signal D. 
     The first circuit  111  is constituted by transistors Q 1  to Q 4  connected in series. The transistors Q 1 , Q 2  are composed of P-channel MOS transistors, and the transistors Q 3 , Q 4  are composed of N-channel MOS transistors. A drain of the transistor Q 1  is connected to a power supply V DD , and a source thereof is connected to a drain of the transistor Q 2 . A second bias  2  from a voltage source (not shown) is sent to a gate of the transistor Q 1 . So, the transistor Q 1  acts as a constant current source. A source of the transistor Q 2  is connected to a drain of the transistor Q 3 . The signal ┐U is sent to a gate of the transistor Q 2  from the drive signal generator  110 . This transistor Q 2  acts as a switch which is turned on or off in response to the signal ┐U. 
     A source of the transistor Q 3  is connected to a drain of the transistor Q 4 . The signal D is sent to a gate of the transistor Q 3  from the drive signal generator  110 . This transistor Q 3  acts as a switch which is turned on or off in response to the signal D. A source of the transistor Q 4  is grounded. A first bias  1  is sent to a gate of the transistor Q 4  from a voltage source (not shown). So, the transistor Q 4  acts as a constant current source. A first output terminal OUT 11  is pulled out from a connection point between the transistors Q 2 , Q 3 . 
     Similarly, the second circuit  112  is constituted by transistors Q 5  to Q 8  connected in series. The transistors Q 5 , Q 6  are composed of P-channel MOS transistors, and the transistors Q 7 , Q 8  are composed of N-channel MOS transistors. A drain of the transistor Q 5  is connected to the power supply V DD , and a source thereof is connected to a drain of the transistor Q 6 . The second bias  2  from the voltage source (not shown) is sent to a gate of the transistor Q 5 . So, the transistor Q 5  acts as a constant current source. A source of the transistor Q 6  is connected to a drain of the transistor Q 7 . The signal ┐D is sent to a gate of the transistor Q 6  from the drive signal generator  110 . This transistor Q 6  acts as a switch which is turned on or off in response to the signal ┐D. 
     A source of the transistor Q 7  is connected to a drain of the transistor Q 8 . The signal U is sent to a gate of the transistor Q 7  from the drive signal generator  110 . This transistor Q 7  acts as a switch which is turned on or off in response to the signal U. A source of the transistor Q 8  is grounded. The first bias  1  is sent to a gate of the transistor Q 8  from the voltage source (not shown). So, the transistor Q 8  acts as a constant current source. A second output terminal OUT 12  is pulled out from a connection point between the transistors Q 6 , Q 7 . By the way, all values of currents flowing through the transistors Q 1 , Q 4 , Q 5  and Q 8  acting as the constant current sources are equal to each other. 
     The first output terminal OUT 11  of the first charge pump  11 A is connected through the first loop filter  12 A to an input terminal of each of the first voltage current converter  13 A and the first common-mode voltage controller  17 A. Also, the second output terminal OUT 12  is connected through the first loop filter  12 A to the other input terminal of each of the first voltage current converter  13 A and the first common-mode voltage controller  17 A. 
     The first loop filter  12 A is composed of capacitors C A , C B . One terminal of the capacitor C A  is connected to the first output terminal OUT 11  of the first charge pump  11 A, and the other terminal is grounded. Also, one terminal of the capacitor C B  is connected to the second output terminal OUT 12 , and the other terminal is grounded. Outputs of the first loop filter  12 A (a potential of the first output terminal OUT 11  and a potential of the second output terminal OUT 12 ) are sent to the first voltage current converter  13 A and the first common-mode voltage controller  17 A. By the way, the first loop filter  12 A may be configured such that a capacitor is mounted between the first output terminal OUT 11  and the second output terminal OUT 12  of the first charge pump  11 A. 
     The first voltage current converter  13 A is the well known circuit for converting the difference between the potential of the first output terminal OUT 11  and the potential of the second output terminal OUT 12  outputted by the first loop filter  12 A, into an electrical signal, and then sending to the current control oscillator  14 . The first common-mode voltage controller  17 A is used in order to maintain the potentials inputted to the first voltage current converter  13 A, within a predetermined range. This first common-mode voltage controller  17 A is the well known circuit used to determine an average voltage of outputs. A current signal outputted by the first voltage current converter  13 A is sent to the current control oscillator  14 . 
     The phase controller  21  is composed of a second charge pump  11 B, a second loop filter  12 B, a second voltage current Converter  13 B and a second common-mode voltage controller  17 B. The configuration of the second charge pump  11 B is equal to that of the first charge pump  11 A. 
     A first output terminal OUT 21  of the second charge pump  11 B is connected through a second loop filter  12 B to one input terminal of each of the second voltage current converter  13 B and the second common-mode voltage controller  17 B. Also, a second output terminal OUT 22  is connected through the second loop filter  12 B to the other input terminal of each of the second voltage current converter  13 B and the second common-mode voltage controller  17 B. 
     The second loop filter  12 B is composed of capacitors C 1 , C 2 , and a resistor R 1 . One terminal of the capacitor C 1  is connected to the first output terminal OUT 21  of the second charge pump  11 B, and the ther terminal is grounded. Also, one terminal of the capacitor C 2  is connected to the second output terminal OUT 22 , and the other terminal is grounded. Moreover, the resistor R 1  is connected between the first output terminal OUT 21  and the second output terminal OUT 22 . A value of the resistor R 1  may be set at, for example, about 1 KΩ. The resistor of the above-mentioned value only occupies a region of about 10 μm angle in an area of a chip. Thus, the drop of the integration degree does not bring about a severe problem. 
     Outputs of the second loop filter  12 B (a potential of the first output terminal OUT 21  and a potential of the second output terminal OUT 22 ) is sent to the second voltage current converter  13 B and the second common-mode voltage controller  17 B. 
     By the way, a loop filter  12 C having the configuration shown in FIG. 7 may be used instead of the second loop filter  12 B. This loop filter  12 C is composed of a resistor R 1  and a capacitor C 3  which are respectively connected between the first output terminal OUT 21  and the second output terminal OUT 22  of the second charge pump  11 B. Even the usage of the loop filter  12 C can provide the effect and the action similar to those of the second loop filter  12 B. 
     The capacitors C 1 , C 2  in the second loop filter  12 B of FIG. 5 are provided to protect a sharp voltage variation caused by a pulse noise. If the pulse noise is sufficiently small, those capacitors C 1 , C 2  can be omitted. 
     The configuration of the second voltage current converter  13 B is equal to that of the first voltage current converter  13 A, and the configuration of the second common-mode voltage controller  17 B is equal to that of the first common-mode voltage controller  17 A. An output line of the second voltage current converter  13 B is coupled to an output line of the first voltage current converter  13 A. Accordingly, a current outputted by the second voltage current converter  13 B and a current outputted by the first voltage current converter  13 A are added to each other, to be sent as a synthesis current to the current control oscillator  14 . 
     The second common-mode voltage controller  17 B in the phase controller  21  may be substituted by the configuration that a predetermined voltage source is sent to, for example, a middle point of the resistor R 1 . In this case, the voltage source can be configured such that a resistor division is performed on the power supply voltage V DD  to accordingly generate a voltage of V DD /2. This configuration does not require the second common-mode voltage controller  17 B. Thus, this has a merit that the circuit becomes simple. 
     The current control oscillator  14  generates a signal oscillating at a frequency corresponding to a current value of the synthesis current. The current control oscillator  14  oscillates at a frequency equal to N times the frequency of the input signal f REF  at a lock state. The signal generated by the current control oscillator  14  is outputted to external portion as an output signal f OUT  of the PLL circuit, and also sent to the CTS buffer  15 . 
     The CTS (Clock Tree Synthesis) buffer  15  is composed of a plurality of buffer circuits for receiving the output signal f OUT  from the current control oscillator  14 . An output of each of the buffer circuits is sent as a clock signal to each section of an electric circuit includes the PLL circuit. Thus, a skew between a plurality of clock signals is corrected. 
     A clock signal from one of the buffer circuits in the CTS buffer  15  is sent to the feedback frequency divider  16 . The feedback frequency divider  16  divides the output signal f OUT  into 1/N, and sends to the phase frequency comparator  10 . 
     The operations of the PLL circuit having the above-mentioned configuration according to the embodiment of the present invention will be described below. At first, let us consider a case in which a phase of a feedback signal f FB  fed from the feedback frequency divider  16  back to the phase frequency comparator  10  is more delayed than that of the input signal f REF . 
     In this case, the phase frequency comparator  10  generates the increase signal UP having the pulse width corresponding to the phase delay, and sends to the first charge pump  11 A of the integrator  20  and the second charge pump  11 B of the phase controller  21 . 
     At first, the operation of the integrator  20  is as follows. That is, the drive signal generator  110  of the first charge pump  11 A generates the signal ┐U and the signal U in response to the increase signal UP. When the generated signal ┐U is sent to the transistor Q 2 , the transistor Q 2  is turned on, which causes a current to flow out from the first output terminal OUT 11 . Then, the charges of the current are charged into the capacitor C A . As a result, a potential corresponding to a pulse width of the signal ┐U appears at the first output terminal OUT 11 . 
     At the same time, when the signal U generated by the drive signal generator  110  is sent to the transistor Q 7 , the transistor Q 7  is turned on, which causes a current to pull from the second output terminal OUT 12 . Then, the charges accumulated in the capacitor C B  are discharged. As a result, a potential corresponding to a pulse width of the signal U appears at the second output terminal OUT 12 . The potential at the first output terminal OUT 11  and the potential at the second output terminal OUT 12  are sent to the first voltage current converter  13 A and the first common-mode voltage controller  17 A. 
     The first voltage current converter  13 A converts the potential difference of the potentials from the first loop filter  12 A into a current signal, and sends to the current control oscillator  14 . In this case, the potential difference is positive (which hereafter implies that the potential at the first output terminal OUT 11  is higher than the potential at the second output terminal OUT 12 ). Thus, the current outputted by the first voltage current converter  13 A is increased, which increases an oscillation frequency of the output signal f OUT  outputted by the current control oscillator  14 . 
     The operation of the phase controller  21  is as follows. That is, the second charge pump  11 B, when the increase signal UP is sent by the phase frequency comparator  10 , acts similarly to the first charge pump  11 A. Then, the second charge pump  11 B makes a current flow out from the first output terminal OUT 21 , and also makes a current pull from the second output terminal OUT 22 . Accordingly, the charges are charged into the capacitor C 1 . So, a potential corresponding to a pulse width of the signal ┐U appears at the first output terminal OUT 21 . At the same time, the charges accumulated in the capacitor C 2  are discharged. Then, a potential corresponding to a pulse width of the signal U appears at the second output terminal OUT 22 . 
     Here, the potentials appearing at the first output terminal OUT 21  and the second output terminal OUT 22  become equal to each other after an elapse of a period defined by a time constant determined by the capacitors C 1 , C 2  and the resistor R 1 , since the first output terminal OUT 21  and the second output terminal OUT 22  are connected to each other through the resistor R 1 . The potential at the first output terminal OUT 21  and the potential at the second output terminal OUT 22  are sent to the second voltage current converter  13 B and the second common-mode voltage controller  17 B. 
     The second voltage current converter  13 B converts the difference between the potential at the first output terminal OUT 21  and the potential at the second output terminal OUT 22  outputted by the second loop filter  12 B, into a current signal, and sends to the current control oscillator  14 . In this case, the potential difference between the potentials is positive to thereby increase the current outputted by the second voltage current converter  13 B only for a short time. Thus, the oscillation frequency of the output signal f OUT  outputted by the current control oscillator  14  is made higher only for the short time. Hence, the phase of the output signal f OUT  is advanced to accordingly approach the phase of the input signal f REF . The output signal f OUT  from the current control oscillator  14  is sent through the CTS buffer  15  to the feedback frequency divider  16 . Then, after divided by the feedback frequency divider  16 , it is fed back to the phase frequency comparator  10  as the feedback signal f FB . Next, let us consider a case in which the phase of the feedback signal f FB  fed from the feedback frequency divider  16  back to the phase frequency comparator  10  is more advanced than that of the input signal f REF . 
     In this case, the phase frequency comparator  10  generates a decrease signal DOWN having a pulse width corresponding to a phase advance, and sends to the first charge pump  11 A of the integrator  20  and the second charge pump  11 B of the phase controller  21 . 
     At first, the operation of the integrator  20  is as follows. That is, the drive signal generator  110  of the first charge pump  11 A generates the signal D and the signal ┐U in response to the decrease signal DOWN. When the generated signal D is sent to the transistor Q 3 , the transistor Q 3  is turned on, which causes a current to pull from the first output terminal OUT 11 . Then, the charges accumulated in the capacitor C A  are discharged. As a result, a potential corresponding to a pulse width of the signal D appears at the first output terminal OUT 11 . 
     At the same time, when the signal ┐D generated by the drive signal generator  110  is sent to the transistor Q 6 , the transistor Q 6  is turned on, which causes a current to flow out from the second output terminal OUT 12 . Then, the charges of the current are charged into the capacitor C B . As a result, a potential corresponding to a pulse width of the signal D appears at the second output terminal OUT 12 . The potential at the first output terminal OUT 11  and the potential at the second output terminal OUT 12  are sent to the first voltage current converter  13 A and the first common-mode voltage controller  17 A. 
     The first voltage current converter  13 A converts the potential difference between the potential at the first output terminal OUT 11  and the potential at the second output terminal OUT 12  outputted by the first loop filter  12 A, into a current signal, and sends to the current control oscillator  14 . In this case, the potential difference is negative (which hereafter implies that the potential at the first output terminal OUT 11  is lower than the potential at the second output terminal OUT 12 ). Thus, the current outputted by the first voltage current converter  13 A is decreased, which decreases the oscillation frequency of the output signal f OUT  outputted by the current control oscillator  14 . 
     The operation of the phase controller  21  is as follows. That is, the second charge pump  11 B, when the decrease signal DOWN is sent by the phase frequency comparator  10 , acts similarly to the first charge pump  11 A. Then, the second charge pump  11 B makes a current pull from the first output terminal OUT 21 , and also makes a current flow out from the second output terminal OUT 22 . Accordingly, the charges accumulated in the capacitor C 1  are discharged. So, a potential corresponding to the pulse width of the signal D appears at the first output terminal OUT 21 . At the same time, the charges are charged into the capacitor C 2 . Then, a potential corresponding the pulse width of the signal ┐D appears at the second output terminal OUT 22 . 
     Here, the potentials appearing at the first output terminal OUT 21  and the second output terminal OUT 22  become equal to each other after the elapse of the period defined by the time constant determined by the capacitors C 1 , C 2  and the resistor R 1 , since the first output terminal OUT 21  and the second output terminal OUT 22  are connected to each other through the resistor R 1 . The potential at the first output terminal OUT 21  and the potential at the second output terminal OUT 22  are sent to the second voltage current converter  13 B and the second common-mode voltage controller  17 B. 
     The second voltage current converter  13 B converts the potential difference between the potential at the first output terminal OUT 21  and the potential at the second output terminal OUT 22  outputted by the second loop filter  12 B, into a current signal, and sends to the current control oscillator  14 . In this case, the potential difference between the potentials is negative to thereby decrease the current outputted by the second voltage current converter  13 B only for a short time. Thus, the oscillation frequency of the output signal f OUT  outputted by the current control oscillator  14  is made lower only for the short time. And, the phase of the output signal f OUT  is delayed to accordingly approach the phase of the input signal f REF  . The output signal f OUT  from the current control oscillator  14  is sent through the CTS buffer  15  to the feedback frequency divider  16 , similarly to the above-mentioned case. Then, after divided by the feedback frequency divider  16 , it is fed back to the phase frequency comparator  10  as the feedback signal f FB  . 
     As mentioned above, according to the PLL circuit of the embodiment of the present invention, in the phase controller  21 , the small current pulse is always outputted to thereby adjust the phase. Thus, it is possible to obtain the output signal f OUT  having no phase offset. Also, the charge pump in this PLL circuit does not use the circuit technique referred to as the cascade connection, for example, as shown in FIG.  7 . Hence, it can be operated at a low voltage. 
     By the way, in the above-mentioned embodiment, the charge pump of the differential output is used as the integrator  20 . However, the charge pump of the single output may be used as shown in FIG.  1 . Even this case can provide the effect and the action similar to those of the case in which the charge pump of the differential output is used. 
     Also, in the above-mentioned embodiment, the PLL circuit is described which has the phase frequency comparator for comparing the phase and the frequency. However, the above-mentioned phase controller can be applied in its original state to even a PLL circuit having a phase comparator for comparing only the phase. Even this case can provide the effect and the action similar to those of the above-mentioned embodiment. 
     As mentioned above, according to the present invention, it is possible to provide the PLL circuit, which can protect the phase offset from occurring and also reduce the operation voltage to the low voltage.

Technology Category: 5