Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This Application is a continuation of pending U.S. application Ser. No. 14/297,965, filed on Jun. 6, 2014, which claims priority of U.S. Provisional Application No. 61/900,624, filed on Nov. 6, 2013, the entireties of which are incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
       [0002]    The invention relates to an integrated circuit, and more particularly to a standard cell of an integrated circuit. 
       Description of the Related Art 
       [0003]    In semiconductor design, standard cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. A standard cell is formed by a plurality of transistor and interconnect structures that provide a Boolean logic function (e.g. AND, OR, XOR, XNOR, inverters) or a storage function (e.g. flip-flop or latch). The standard cells are realized as fixed-height, variable-width full-custom cells. The standard cells are arranged in rows in a semiconductor substrate. In between the rows are routing areas for interconnecting the standard cells. Furthermore, power leafs may also be arranged through the routing areas or may have designed areas overlying the standard cells. 
         [0004]    In order to simplify the ASIC design process, various vendors have developed various standard cell libraries. Use of the standard cells is advantageous to save time and cost for designing various ASICs. Furthermore, the standard cells are typically optimized full-custom layouts, which minimize delays and area. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    Integrated circuits are provided. An embodiment of an integrated circuit is provided. In one embodiment, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor disposed in a first row in a semiconductor substrate and at least one first NMOS transistor disposed in a first area of a second row in the semiconductor substrate, and a second standard cell, comprising a plurality of second PMOS transistors disposed in the first row and a third row in the semiconductor substrate and a plurality of second NMOS transistors disposed in a second area of the second row in the semiconductor substrate, wherein the second row is adjacent to the first and third rows and arranged between the first and third rows. 
         [0006]    Furthermore, in another embodiment, the integrated circuit comprises; a first standard cell, comprising at least one first NMOS transistor disposed in a first row in a semiconductor substrate and at least one first PMOS transistor disposed in a first area of a second row in the semiconductor substrate; and a second standard cell, comprising a plurality of second PMOS transistors disposed in a third row and a second area of the second row in the semiconductor substrate and a plurality of second NMOS transistors disposed in a fourth row in the semiconductor substrate. The second row is adjacent to the first and fourth rows and arranged between the first and fourth rows, and the fourth row is adjacent to the second and third rows and arranged between the second and third rows. 
         [0007]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0008]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0009]      FIG. 1  shows an integrated circuit according to an embodiment of the invention; 
           [0010]      FIG. 2  shows an example illustrating a layout diagram of the standard cells S 6  and D 1  of  FIG. 1  according to an embodiment of the invention; 
           [0011]      FIG. 3  shows a schematic illustrating a relationship between the track number and the packing density of the double height cell and the single height cell according to an embodiment of the invention; and 
           [0012]      FIG. 4  shows an example illustrating a layout diagram of the standard cells D 1 , D 3  and S 8  of  FIG. 1  according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0013]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0014]      FIG. 1  shows an integrated circuit  100  according to an embodiment of the invention. The integrated circuit  100  comprises a plurality of standard cells disposed in a plurality of rows in a semiconductor substrate  110 . In  FIG. 1 , the standard cells S 1 -S 11  and the standard cells D 1 -D 3  form a standard cell array  120 , and the standard cells S 1 -S 11  and D 1 -D 3  are arranged in the rows R n -R n+4 , wherein a N-well  130  is formed in the row R n , a N-well  140  is formed in the row R n+2 , and a N-well  150  is formed in the row R n+4 . In one embodiment, the P-wells can be formed in the rows R n+1  and R n+3 . Specifically, the rows with N-wells (e.g. R n , R n+2  or R n+4 ) and the rows without N-wells (e.g. R n+1  or R n+3 ) are alternately arranged in the semiconductor substrate  110 . Furthermore, each of the standard cells S 1 -S 11  is a single height cell having a height SH, and each of the standard cells D 1 -D 3  is a double height cell having a height DH. The height DH is substantially twice the height SH, and the double height cell is capable to provide a high speed operation with high density. Furthermore, the double height cell will benefit area and power reduction under low speed application. The layout differences between the single height cell and the double height cell will be described below. 
         [0015]      FIG. 2  shows an example illustrating a layout diagram of the standard cells S 6  and D 1  of  FIG. 1  according to an embodiment of the invention. The standard cell S 6  comprises three PMOS transistors MP 61 -MP 63  and three NMOS transistors MN 61 -MN 63 . A gate G 61  and a P+ doping region PD 6  adjacent to the gate G 61  form the PMOS transistor MP 61 , a gate G 62  and the P+ doping region PD 6  adjacent to the gate G 62  form the PMOS transistor MP 62 , and a gate G 63  and the P+ doping region PD 6  adjacent to the gate G 63  form the PMOS transistor MP 63 . Furthermore, the gate G 61  and an N+ doping region ND 6  adjacent to the gate G 61  form the NMOS transistor MN 61 , the gate G 62  and the N+ doping region ND 6  adjacent to the gate G 62  form the NMOS transistor MN 62 , and the gate G 63  and the N+ doping region ND 6  adjacent to the gate G 63  form the NMOS transistor MN 63 . The standard cell D 1  comprises four PMOS transistors MP 11 -MP 14  and two NMOS transistors MN 11 -MN 12 . A gate G 11  and a P+ doping region PD 1   a  adjacent to the gate G 11  form the PMOS transistor MP 11 , a gate G 12  and the P+ doping region PD 1   a  adjacent to the gate G 12  form the PMOS transistor MP 12 . The gate G 11  and a P+ doping region PD 1   b  adjacent to the gate G 11  form the PMOS transistor MP 13 , and the gate G 12  and the P+ doping region PD 1   b  adjacent to the gate G 12  form the PMOS transistor MP 14 . It is to be noted that a quantity of the PMOS transistors in the P+ doping region PD 1   b  of the row R n  is equal to a quantity of the PMOS transistors in the P+ doping region PD 1   a  of the row R n+2 . Furthermore, the gate G 11  and an N+ doping region ND 1  adjacent to the gate G 11  form the NMOS transistor MN 11 , and the gate G 12  and the N+ doping region ND 1  adjacent to the gate G 12  form the NMOS transistor MN 12 . In the rows R n  and R n+2 , the P+ doping regions PD 6 , PD 1   a  and PD 1   b  have the same height (e.g. W1), thus each gate of the PMOS transistors in the standard cell S 6  and each gate of the PMOS transistors in the standard cell D 1  have the same width W1. In the row R n+1 , a height (e.g. W3) of the N+ doping region ND 1  is at least twice a height (e.g. W2) of the N+ doping region ND 6 , thereby each gate of the NMOS transistors in the standard cell D 1  has at least twice width of each gate of the NMOS transistors in the standard cell S 6 , i.e. W3≧2×W2. 
         [0016]      FIG. 3  shows a schematic illustrating a relationship between the track number and the packing density of the double height cell and the single height cell according to an embodiment of the invention, wherein the track number is used to represent a height of a standard cell. In  FIG. 3 , curve  310  represents a property of the single height cell, and curve  320  represents a property of the double height cell. If comparison is made with the same packing density (e.g. Pden), the double height cell has a larger track number than that of the single height cell, i.e. n2&gt;n1. Thus, the double height cell is good for power, area and timing optimization. 
         [0017]      FIG. 4  shows an example illustrating a layout diagram of the standard cells D 1 , D 3  and S 8  of  FIG. 1  according to an embodiment of the invention. The standard cell D 1  has be described in  FIG. 2 . In the standard cell S 8 , a gate G 81  and a P+ doping region PD 8  adjacent to the gate G 81  form a PMOS transistor in the row R n+2 , and the gate G 81  and an N+ doping region ND 8  adjacent to the gate G 81  form an NMOS transistor in the row R n+3 . In the row R n+2 , the P+ doping regions PD 1   a  and PD 8  have the same height (e.g. W1), thus each gate of the PMOS transistors in the standard cell D 1  and the gate of the PMOS transistor in the standard cell S 8  have the same width W1. The height (e.g. W3) of the N+ doping region ND 1  in the row R n+1  is at least twice the height (e.g. W2) of the N+ doping region ND 8  in the row R n+3 , thereby each gate of the NMOS transistors in the standard cell D 1  has at least twice width of the gate of the NMOS transistor in the standard cell S 8 , i.e. W3≧2×W2. Furthermore, in the standard cell D 3 , the gates G 31 -G 34  and the P+ doping region PD 3  adjacent to each gate form a plurality of PMOS transistor in the row R n+2.  Furthermore, the gates G 31 -G 34  and the N+ doping region ND 3   a  adjacent to each gate form a plurality of NMOS transistors in the row R n+3 , and the gates G 31 -G 34  and the N+ doping region ND 3   b  adjacent to each gate form a plurality of NMOS transistors in the row R n+1 . It is to be noted that a quantity of the NMOS transistors in the N+ doping region ND 3   b  of the row R n+1  is equal to a quantity of the NMOS transistors in the N+ doping region ND 3   a  of the row R n+3 . In the row R n+2 , the height (e.g. W4) of the P+ doping region PD 3  is at least twice the height (e.g. W1) of the P+ doping region PD 8 , thereby each gate of the PMOS transistors in the standard cell D 3  has at least twice width of each gate of the PMOS transistors in the standard cell D 1 , i.e. W4≧2×W1. In the row R n+1 , the height (e. g. W3) of the N+ doping region ND 1  is at least twice the height (e.g. W2) of the N+ doping region ND 3   b , thereby each gate of the NMOS transistors in the standard cell D 1  has at least twice width of the gate of the NMOS transistor in the standard cell D 3 , i.e. W3≧2×W2. 
         [0018]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Category: h