Patent Document

FIELD OF INVENTION 
   The present invention relates to a technique for reducing bus transitions, i.e., reducing switching activity (SA) on a bus. The present invention has been developed with application to the transmission of signals in the Bayer format. 
   BACKGROUND OF THE INVENTION 
   Digital signals in the Bayer format, such as those provided by an image sensor in a camera for example, have the format shown in  FIG. 1 . Basically, a matrix format is being dealt with in which each row is alternately coded with two colors: odd rows are alternately coded with the red and green colors, while even rows are alternately coded with the green and blue colors. In the layout shown in  FIG. 1 , the respective letters R, G and B stand for red, green and blue. 
   When an image sensor, such as the one schematically indicated as reference  1  in  FIG. 2 , is to be connected to a processor  2  for processing the pixel data to reconstruct the image, a problem arises due to the fact that data items in the Bayer format are highly uncorrelated with each other. During transmission on the bus B to the processor  2  ( FIG. 2 ), the data in question gives rise to a high switching activity. 
   The problem can be addressed, at least in principle, by applying data encoding techniques on the bus B for reducing switching activity. For example, on small-size buses, such as those up to 8 bits, the technique known as bus inverter (BI) is a good encoding technique for the majority of cases. The results deriving from the application of this technique can vary, and in quite a significant manner, depending on the type of data being transmitted. 
   SUMMARY OF THE INVENTION 
   In view of the foregoing background, an object of the present invention is to provide a process for converting digital video signals between a Bayer format and an encoded format. 
   This and other objects, advantages and features in accordance with the present invention are provided by a process for converting digital video signals between a Bayer format and an encoded format, with pixels in each line of the Bayer format being alternately coded with two colors, and the digital video signals in the encoded format having a reduced switching activity when transmitted over a bus as compared to the digital video signals in the Bayer format being transmitted over the bus. The process comprises ordering the pixels in sets of adjacent pixels in the encoded format, with the sets respectively grouping pixels that code a same color. 
   Another aspect of the present invention is directed to system for converting digital video signals between a Bayer format and an encoded format, with pixels in each line of the Bayer format being alternately coded with two colors, and the digital video signals in the encoded format having a reduced switching activity when transmitted over a bus as compared to the digital video signals in the Bayer format being transmitted over the bus. The system comprises at least one converter element connected to the bus for converting between the Bayer format and the encoded format so that, in the encoded format, the pixels are ordered in sets of adjacent pixels, with the sets respectively grouping pixels that code a same color. 
   The present invention is thus based on performing an ordered encoding of the sequence of Bayer format data provided as input to the transmission bus. This reduces the transitions during transmission on the bus. The data is then reordered into the Bayer format at the output of the transmission bus. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will now be described by way of a nonlimiting example, with reference to the enclosed drawings, in which: 
       FIGS. 1 and 2  generically illustrate application of the present invention; 
       FIG. 3  illustrates, in general terms, an architecture for the transmission of Bayer data over a bus operating in accordance with the present invention; 
       FIG. 4  illustrates an extension of the architecture as shown in  FIG. 3 ; and 
       FIG. 5  illustrates a block diagram of an encoder operating in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following is not to be interpreted as a limitation with regards to the scope of the present invention. It will be presumed that in an application context such as that represented in  FIG. 2  (transmission of video data acquired by a sensor  1  in a Bayer format to a processor  2  via a bus B), 640*480 pixels for example, transmit on the connection bus. The transmission is between the sensor  1  and the processor or controller  2  for each image in a VGA format. 
   This communication absorbs a large quantity of power due to the effect of induced transitions on the connection bus B. To better understand the motives of this situation (which are likely to arise for any number of bits representing the pixels and for any size of bus), it is presumed that the pixels have a color represented by k bits and that the connection bus B between the sensor  1  and the processor  2  is a k/2 bit bus. 
   For this system, it is presumed that the sensor has n pixels per column (five pixels in the illustrated example), and there are a total of m rows (in this case totaling five in number). Each color is first transmitted with k/2 bits of the upper part (from bit k- 1  to bit k/2), and then the k/2 bits of the lower part (from bit [k/2-1] to bit 0). 
   The output data can thus be represented in the following manner:
 
P 1,1 (R)H,P 1,1 (R)L,P 1,2 (G)H,P 1,2 (G)L, . . . , P 1,n−1 (G)H,P 1,n−1 (G)L,P 1,n (R)H,P 1,n (R)L, P 2,1 (G)H,P 2,1 (G)L,P 2,2 (B)H,P 2,2 (B)L, . . . , P 2,n−1 (B)H,P 2,n−1 (B)L,P 2,n (G)H,P 2,n (G)L, . . . , P m,1 (R)H,P m,1 (R)L,P m,2 (G)H,P m,2 (G)L, . . . , P m,n−1 (G)H,P m,n−1 (G)L,P m,n (R)H,P m,n (R)L
 
where:
         P 1,1 (R)H=Pixel row 1, position 1 (Red) upper bits   P 1,1 (R)L=Pixel row 1, position 1 (Red) lower bits   P 1,2 (G)H=Pixel row 1, position 2 (Green) upper bits   P 1,2 (G)L=Pixel row 1, position (Green) lower bits   . . .   P m,n (R)H=Pixel row m, position n (Red) upper bits   P m,n (R)L=Pixel row m, position n (Red) lower bits
 
Values in the output data from the sensor  1  are found to be highly uncorrelated with each other, and this reflects in the high switching activity on the bus B.
       

   The idea at the base of the present invention is therefore that of reorganizing the data, with regards to both the position of upper and lower bits and the color represented by the pixels, and consequently, transferring the data (with reference to the above example) on the basis of the sequence specified below:
 
P 1,1 (R)H,P 1,3 (R)H, . . . , P 1,n (R)H,P 1,1 (R)L, P 1,3 (R)L, . . . P 1,n (R)L, P 1,2  (G)H,P 1,4 (G)H, . . . , P 1,n−1 (G)H,P 1,2 (G)L,P 1,4 (G)L, . . . P 1,n (G)L, P 2,1 (G)H,P 2,3 (G)H, . . . , P 2,n (G)H,P 2,1 (G)L,P 2,3 (G)L, . . . P 2,n−1 (G)L, P 2,2 (B)H,P 2,4 (B)H, . . . , P 2,n−1 (B)H,P 2,2 (B)L,P 2,4 (B)L, . . . P 2,n−1 (B) L, . . . , P m,1 (R)H,P m,3 (R)H, . . . , P m,n (R)H,P m,1 (R)L,P m,3 (R)L, . . . P m,n (R)L, P m,2 (G)H,P m,4 (G)H, . . . , P m,n−1 (G)H,P m,2 (G)L,P m,4 (G)L, . . . P m,n−1 (G)L.
 
   To implement the encoding from the previously seen classical format to the encoded format shown above, it is sufficient to associate the output of the sensor  2  with an encoder  3  that receives the data in the classical format and transforms it into the encoded format ready for transmission on the bus B. 
   Symmetrically, a decoder  4  is at the input to the processor  2 , which receives the data in the encoded format and transforms it back to the classical format for input to the processor  2 . In effect, the encoder  3  reorders the pixels that are ordered in the Bayer format so that pixels of the same color are grouped together as much as possible. 
   In fact, by comparing the previously illustrated classical data format and the encoded format, it is immediately obvious that the first (classical format) has a high recurrence of situations in which the relative colors of adjacent pixels are different. On the contrary, data in the second form (encoded format) is grouped into a first group or set of pixels relative to a first color (red in the illustrated example), followed by a second group or set of pixels of a second color (green in the illustrated example) and, lastly, a group or set of pixels relative to the third color (blue in the illustrated example). In addition, grouping the upper and lower parts of the data items reduces data variance. 
   In a possible embodiment of the encoder circuit  3 , the operation of which is timed by a clock signal CLK, are provided by a series of k-bit registers (typically flip-flops) that contain the pixels of an entire row. In particular, the registers in question are grouped into four blocks for the purposes of containing: 
   in the first block, the upper part (H) of the set of pixels in odd positions and which belong to the row being dealt with each time; in the case of the sensor shown in  FIGS. 1 to 4 , for example, the upper part of the red pixels for the first row could be handled; 
   in the second block, the lower part of the set of pixels in odd positions and which belong to the row being processed each time; in the case of the sensor shown in  FIGS. 1 to 4 , for example, the lower part of the red pixels for the first row could be handled; 
   in the third block, the upper part of the set of pixels in even positions and which belong to the row being processed each time; in the case of the sensor shown in  FIGS. 1 to 4 , for example, the upper part of the green pixels for the first row could be handled; and 
   in the fourth block, the lower part of the set of pixels in even positions and which belong to the row being processed each time; in the case of the sensor shown in  FIGS. 1 to 4 , for example, the lower part of the green pixels could be handled. 
   The above indicated blocks or registers are dimensioned to contain all the data items of a row minus  4 . In addition, the registers in question are preferably duplicated over two lines. The first line includes four first registers  1 A,  2 A,  3 A and  4 A (line A), and the second line includes four second registers  1 B,  2 B,  3 B and  4 B (line B). This permits a maximum speed of operation to be maintained. While data is loaded into one line (line A instead of line B for example), the data grouped in the other line (line B instead of line A for example) can be sent. 
   Multiplexers  5 A,  5 B,  6 A,  6 B,  7 A and  7 B are provided at the input to the above described registers (except for the blocks  4 A and  4 B). They are to pass to the input of their respective block, which is either the input signal present on a line  8  and known as Data in (generically n-bit) or alternatively, the output signal of the block immediately upstream. 
   Reference  9  indicates a control unit for blocks  1 A,  2 A,  3 A and  4 A, as well as for the multiplexers  5 A,  6 A and  7 A. In a symmetrical manner, the control unit  9  is also for the blocks  1 B,  2 B,  3 B and  4 B, as well as for the multiplexers  5 B,  6 B and  7 B, via corresponding enabling EN_A and EN_B signals and selection SEL_A and SEL_B signals. The suffixes A and B indicate the lines and the blocks to which the control signals are intended. 
   Reference  10  indicates a multiplexer for the outputs, that is, an overall output for the circuit. The output data is indicated as Data out, and is from either the data available on block  1 A or the data available on block  1 B as a function of a selection signal SEL_OUT produced by the control unit  9 . 
   The control unit  9  operates according to the following criteria: 
   1) acquire a first data item at an input, shift block  1 A by one position and write it in the register that has just been freed. 
   2) acquire a second data item at an input, shift block  2 A by one position and write it in the register that has just been freed. 
   3) acquire the next data item at an input, shift block  3 A by one position and write it in the register that has just been freed. 
   4) acquire the next data item at an input, shift block  4 A by one position and write it in the register that has just been freed. 
   5) acquire the first data item at an input, shift block  1 A by one position and write it in the register that has just been freed. 
   6) acquire the next data item at an input, shift block  2 A by one position and write it in the register that has just been freed. 
   7) return to step  3  until all the data items of a row minus  4  have been loaded, when a block  4 A has just been written. 
   8) shift block  1 A by one position, thereby sending the first encoded data item in output and write the fourth from last data item acquired in input on block  1 A in the register that has just been freed. 
   9) select multiplexer  5 A as an input to block  1 A and shift blocks  2 A and  1 A by one position, thereby outputting a data item from  2 A which is passed as an input to  1 A and write the third from last data item acquired in input on block  2 A in the register that has just been freed. 
   10) select multiplexer  6 A as an input to block  2 A and shift blocks  3 A,  2 A and  1 A by one position, thereby outputting a data item from  3 A which is passed as an input to  2 A and a data item from  2 A which is passed as an input to  1 A, and write the next to last data item acquired as an input on block  3 A in the register that has just been freed. 
   11) the same procedure is performed for writing the last data item on the block  4 A and shifting all of the data items in the individual blocks up to the output. 
   12) the same technique (described in steps  1  to  11 ) is then applied for writing the next row in line B and simultaneously sending out the encoded data of line A. 
   13) the same technique is repeated for all of the rows, alternating the two lines A and B so that data is loaded into one line while data is sent out from the other line. 
   By adopting the above-described technique, it is possible to generate a flow of data for output Data out with the same frequency at input and with only an initial delay equal to a line minus four data items. The data in question is thus suitable for being transmitted over the bus B with reduced switching activity. 
   As illustrated in  FIG. 4 , it is possible to reduce switching activity even further by providing two additional modules, one on one side between the encoder  3  and the bus B and the other between the bus B and the decoder  4  on the other side. The two additional modules are respectively an encoder  3 ′ and a decoder  4 ′, which implement any type of known approach for reducing switching activity (the bus inverter technique for example). In this way, it is possible to further improve overall system performance. 
   The structure of the decoder  4  can be based on the same circuit layout represented in  FIG. 5 . By passing the encoded data to the input line  8  in  FIG. 5  it is possible to acquire signals output from a circuit having the layout represented in  FIG. 5  that corresponds to Bayer signals in the classical format. The processor  2  receives the data with the same frequency as the output from the sensor  1  with an initial delay equal to 2 lines minus four data items. This delay is given by the sum of the delays that arise at the encoder  3  level and at the decoder  4  level. 
   The approach according to the invention permits a considerable reduction to be achieved in the switching activity (SA) that is prone to arise on the connection bus B between the Bayer sensor  1  and the processor  2  that is to process the relative data. For example, by creating a line of 8 pixels (to reduce the size of the encoder as a whole and therefore without operating on the entire row), it is possible to achieve a reduction in switching activity of approximately 30%. 
   It will be appreciated that the present invention that has just been described allows the output of data to commence even before memorization of the row is completed. This permits savings on circuit components equivalent to 4 n-bit buffer memories, thus reducing the initial wait delay by 4 CLK pulses. 
   It will also be appreciated that the described technique is in no way restricted by the number of pixels utilized. The described approach is in fact applicable both in the described case in which the buffer contains the entire row and in the case in which the size of the buffer is different from the size of the row, or rather, for example, 4 pixels, half a row, one and half rows, two rows, etc. 
   With the principle of the invention being understood, the details disclosed herein could be extensively changed with respect to that described and illustrated above without leaving the scope of this invention, as defined by the enclosed claims.

Technology Category: 5