Patent Document

BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a CR oscillation circuit, and particularly to a CR oscillation circuit for controlling an oscillation frequency by an outside resistor. 
   This application is a counterpart of Japanese Patent Application, Serial Number 086155/2002, filed on Mar. 26, 2002, the subject matter of which is incorporated herein by reference. 
   2. Description of the Related Art 
   FIGS.  2 (A) and  2 (B) are respectively diagrams for describing a conventional outside resistor type CR oscillation circuit. FIG.  2 (A) is a diagram showing a circuit configuration of the conventional CR oscillation circuit, and FIG.  2 (B) is a diagram illustrating operation waveforms. 
   As shown in FIG.  2 (A), the CR oscillation circuit has inverters  201 ,  202  and  203  connected in series between a node N 1  and a node N 3 . A capacitor  204  is electrically connected both the node N 1  and a node N 2 . The node N 2  is electrically connected both the inverter  202  and the inverter  203 . The node N 1  is electrically connected to a terminal  205  for connecting one end of an outside resistor R 1 . The node N 3  on the output side of the inverter  203  is electrically connected to a terminal  206  for connecting the other end of the outside resistor R 1 . An oscillation signal OUT is outputted from the node N 3 . Owing to the electrical connection of the outside resistor R between the terminals  205  and  206  in such a circuit, a feedback circuit is made up of the outside resistor R and the internal capacitor  204 . Thus, an oscillation output OUT having a frequency corresponding to the time constant T of these elements is obtained. 
   The operation of the CR oscillation circuit will next be described. 
   Now assume that a source voltage is represented as VDD, threshold voltages of respective inverters are respectively represented as 0.5VDD, and “H” and “L” of input and output levels are respectively represented as VDD and 0 (=GND) for simplification of description. Further, the input impedance of each inverter is assumed to be infinite. 
   When power is turned on at a time t 0  in FIG.  2 (B), the capacitor  204  is discharged and a voltage V 21  at the node N 1  is assumed to be 0. Since the voltage level of the node N 1  is outputted to the node N 2  via the inverters  201  and  202 , a voltage V 22  at the node N 2  results in 0. Further, since the voltage V 22  at the node N 2  is inverted by the inverter  203 , a voltage V 23  at the node N 3  becomes VDD. 
   With power-on at the time t 0 , the capacitor  204  starts to charge via the outside resistor R. Thus, the voltage V 21  at the node N 1  exponentially rises from 0 to VDD according to the time constant T of the capacitor  204  and the outside resistor R. 
   When the voltage V 21  reaches 0.5VDD at a time t 1 , the voltage inputted to the inverter  201  exceeds the threshold voltage thereof. Thus, the voltage outputted from the inverter  201  reaches 0 and the voltage V 2  on the output side of the inverter  202  changes from 0 to VDD. Since, at this time, the voltage charged in the capacitor  204  is 0.5VDD, the voltage V 21  at the node N 1  reaches 1.5VDD. On the other hand, the voltage V 23  at the node N 3  on the output side of the inverter  203  results in 0. Correspondingly, the voltage V 21  at the node N 1  exponentially decreases from 1.5VDD to 0 according to the time constant T. 
   When the voltage V 21  decreases to 0.5VDD at a time t 2 , the input voltage of the inverter  201  reaches less than or equal to its threshold voltage. Consequently, the output voltage of the inverter  201  becomes VDD and the voltage V 22  on the output side of the inverter  202  changes from VDD to 0. Since, at this time, the voltage charged in the capacitor  204  is 0.5VDD, the voltage V 21  at the node N 1  results in −0.5VDD. On the other hand, the voltage V 23  at the node N 3  on the output side of the inverter  203  reaches VDD. Correspondingly, the voltage V 21  at the node N 1  exponentially rises from −0.5VDD to VDD according to the time constant T. 
   When the voltage V 21  increases to 0.5VDD at a time t 3 , the input voltage of the inverter  201  exceeds its threshold voltage. Consequently, the output voltage of the inverter  201  becomes 0 and the voltage V 22  on the output side of the inverter  202  changes from 0 to VDD. Since, at this time, the voltage charged in the capacitor  204  is 0.5VDD, the voltage V 21  at the node N 1  results in 1.5VDD. On the other hand, the voltage V 23  at the node N 3  on the output side of the inverter  203  reaches 0. Correspondingly, the voltage V 21  at the node N 1  exponentially decreases from 1.5VDD to 0 according to the time constant T. 
   With similar repetitive operations, the respective inverters are subsequently periodically inverted according to the time constant T set by the values of the capacitor  204  and the resistor R, and an oscillation signal OUT having a desired frequency is outputted from the node N 3 . 
   However, the conventional CR oscillation circuit involves the following problems. 
   Although the outside resistor R having a value corresponding to an intended oscillation frequency is electrically connected to the terminals  205  and  206 , such parasitic capacitance Cp as indicated by each dotted line in FIG.  2 (A) is contained in an actually-connected outside resistor R. The parasitic capacitance Cp greatly varies according to the state of packaging thereof. Also a problem arises in that since the value of the built-in capacitor  204  is relatively small, the influence of each parasitic capacitance Cp increases, thus causing errors in a value at a single test on the outside resistor and an oscillation frequency at its packaging. 
   SUMMARY OF THE INVENTION 
   A CR oscillation circuit according to the present invention includes an oscillation unit having first through third invertion circuits series-connected between a first node and a second node, a capacitance element provided between the first node and an output terminal of the second inverting circuit, and a switch part for electrically connecting the first and second nodes according to a level of a control voltage; a constant current unit for allowing a constant current to flow according to a resistance value of an externally-provided resistive element to thereby supply a constant voltage; and a level conversion unit for converting a level of the constant voltage to produce the control voltage. 
   The present invention provides a CR oscillation circuit which reduces an error produced in an oscillation frequency according to the state of packaging of an outside resistor. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which: 
       FIG. 1  is a circuit diagram showing a CR oscillation circuit according to an embodiment of the present invention; and 
       FIGS. 2A , B is a circuit diagram showing a conventional CR oscillation circuit and a timing chart thereof. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1  is a circuit diagram showing a CR oscillation circuit according to an embodiment of the present invention. The CR oscillation circuit according to the embodiment of the present invention comprises an oscillation unit  100 , a constant current unit  110 , and a level conversion unit  120 . 
   The oscillation unit  100  comprises nodes N 1 , N 2  and N 3 , inverters  201 ,  202  and  203 , a capacitor  204 , and a switch part  101 . In the oscillation unit  100 , the switch part  101  has four nodes and electrically connects the third and fourth nodes according to voltage levels applied to the first and second nodes. The node N 1  is electrically connected to a fourth node of the switch part  101 , an input terminal of the inverter  201 , and one end of the capacitor  204 . An output terminal of the inverter  201  is electrically connected to an input terminal of the inverter  202 , and an output terminal of the inverter  202  is electrically connected to the node N 2 . The node N 2  is electrically connected to an input terminal of the inverter  203  and the other end of the capacitor  204 . An output terminal of the inverter  203  is electrically connected to the node N 3 . The node N 3  is electrically connected to the third node of the switch part  101 . The oscillation unit  100  outputs an oscillation signal OUT from the node N 3 . 
   Now, the switch part  101  is a transfer gate, which comprises a P channel MOS transistor (PMOS transistor)  102 , and an N channel MOS transistor(NMOS transistor)  103 . The PMOS transistor  102  has a gate electrode electrically connected to the first node of the switch part  101 , a source electrode electrically connected to the third node, and a drain electrode electrically connected to the fourth node. The NMOS transistor  103  includes a gate electrode electrically connected to the second node of the switch part  101 , a source electrode electrically connected to the third node, and a drain electrode electrically connected to the fourth node. 
   The constant current unit  110  comprises PMOS transistors  111  and  112  which constitute a current mirror, NMOS transistors  113  and  114  which constitute a current mirror, a terminal  115 , an outside resistive element R 1 , and nodes N 4  and N 5 . The constant current unit  110  is capable of controlling a current by the outside resistive element R 1 . The PMOS transistor  111  has a gate electrode electrically connected to a gate electrode of the PMOS transistor  112 , a source electrode to which a source voltage VDD is applied, and a drain electrode electrically connected to the node N 5 . The PMOS transistor  112  has a gate electrode and a drain electrode electrically connected to the node N 4 , and a source electrode to which the source voltage VDD is applied. The NMOS transistor  113  has a gate electrode and a drain electrode electrically connected to the node N 5 , and a source electrode to which a ground voltage GND is applied. The NMOS transistor  114  has a gate electrode electrically connected to the gate electrode of the NMOS transistor  113 , a source electrode electrically connected to the terminal  115 , and a drain electrode electrically connected to the node N 4 . One end of the resistive element R 1  is electrically connected to the terminal  115 , whereas the other end thereof is electrically connected to the ground voltage GND. 
   Owing to the connection of the outside resistive element R 1  between the terminal  115  and the ground voltage GND in such a constant current unit  110 , a current that flows through the PMOS transistors  111  and  112  and NMOS transistors  113  and  114 , is controlled to a constant value corresponding to the resistance value of the external resistive element R 1 . The constant current unit  110  outputs a constant voltage V 1  corresponding to the constant current from the node N 4 . 
   The level conversion unit  120  comprises a node N 6 , a PMOS transistor  121 , and an NMOS transistor  122 . The PMOS transistor  121  has a gate electrode electrically connected to the node N 4 , a source electrode to which the source voltage VDD is applied, and a drain electrode electrically connected to the node N 6 . The NMOS transistor  122  has a gate electrode and a drain electrode electrically connected to the node N 6 , and a source electrode to which the ground voltage GND is applied. The level conversion unit  120  level-converts the voltage V 1  at the node N 4  and outputs a control voltage V 2  from the node N 6 . The control voltage V 2  is supplied to the gate electrode of the NMOS transistor  103  (or the second node of the switch part  101 ). 
   The operation of the CR oscillation circuit will be described. 
   When power is applied to the CR oscillation circuit, a constant current corresponding to the resistance value of the outside resistor R 1  flows in the constant current unit  110 . Thus, a constant voltage V 1  corresponding to the constant current is outputted to the node N 4  of the constant current unit  110 . 
   The constant voltage V 1  is supplied to the level conversion unit  120 , where it is level-converted. The converted control voltage V 2  is outputted from the node N 6 . The constant voltage V 1  and the control voltage V 2  are respectively supplied to the gates of the PMOS transistor  102  and NMOS transistor  103 . Thus, each of the parallel-connected PMOS transistor  102  and NMOS transistor  103  assumes a constant conducting resistor corresponding to the outside resistor R 1  and operate a feedback resistor with respect to the node N 3  to the node N 1 . 
   On the other hand, oscillating operations carried out by the inverters  201  through  203 , the capacitor  204 , and the PMOS transistor  102  and NMOS transistor  103  are represented as shown in FIG.  2 (B). 
   Thus, the CR oscillation circuit according to the present embodiment has the PMOS transistor  102  and NMOS transistor  103  operated as the feedback resistor, the constant current unit  110  for controlling each of the conducting resistors for these PMOS transistor  102  and NMOS transistor  103  by means of the outside resistor R 1 , and the level conversion unit  120 . A current that flows in the constant current unit  110 , is not affected by the parasitic capacitance of the outside resistor R 1 . Accordingly, an advantageous effect is brought about in that a CR oscillation circuit free of the occurrence of an error in oscillation frequency according to the state of packaging of the outside resistor R 1  is obtained. Also an advantageous effect is brought about in that since the PMOS transistor  102  and the NMOS transistor  103  are utilized in combination as a transfer gate type, currents charged into and discharged from the capacitor  204  can be set so as to flow freely in either direction, thereby making it possible to control the oscillation frequency accurately and reliably. 
   Incidentally, the present invention is not limited to the embodiment referred to above. Various modifications can be made thereto. For example, the following are mentioned as such modifications.
         (a) The circuit configuration of the constant current unit  110  is not limited to the illustrated one. As an alternative to it, one may be used which causes a constant current to flow according to the value of the outside resistor R 1  and outputs a constant voltage V 1  corresponding to the constant current.   (b) The circuit configuration of the level conversion unit  120  is not limited to the illustrated one. As an alternative to it, one may be used which converts a constant voltage V 1  outputted from the constant current unit  110  to a control voltage V 2  for the NMOS transistor  103  and outputs it.   (c) A circuit configuration may be adopted in which the circuits for the constant current unit  110  and the level conversion unit  120  are changed so as to supply the constant voltage V 1  of the constant current unit  110  to the NMOS transistor  103  and supply the control voltage V 2  of the level conversion unit  120  to the PMOS transistor  102 .       

   According to the present invention as described above in detail, a CR oscillation circuit has a feedback resistor using a conducting resistor for each transistor, a constant current circuit for controlling the conducting resistor according to the value of en outside resistor, and a level converting circuit. Consequently, an advantageous effect is obtained in that the CR oscillation circuit is not affected by parasitic capacitance of the outside resistor and produces no error in oscillation frequency according to the state of packaging. 
   According to the present invention, a first conductive type MOS transistor in which the value of a conducting resistor is controlled by a constant voltage, and a second conductive type MOS transistor in which the value of a conducting resistor is controlled by a control voltage, are connected in parallel as transistors according to the present invention. Consequently, an advantageous effect is obtained in that a more reliable operation can be performed. 
   While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Technology Category: h