Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of U.S. application Ser. No. 10/833,917 filed on Apr. 28, 2004, allowed on Feb. 12, 2008. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The invention relates generally to the field of image sensors and, more particularly, to producing at least 30 frames per second (video) by sampling the entire array of the image sensor and summing all pixel values in a predetermined manner. 
       BACKGROUND OF THE INVENTION 
       [0003]    Referring to  FIG. 1 , an interline charge coupled device (CCD) image sensor  10  is comprised of an array of photodiodes  20 . The photodiodes  20  are covered by color filters to allow only a narrow band of light wavelengths to generate charge in the photodiodes. Referring to  FIG. 2 , typically image sensors having a pattern of three or more different color filters arranged over the photodiodes in a 2×2 sub array as shown in  FIG. 2 . For the purpose of a generalized discussion, the 2×2 array is assumed to have four colors, A, B, C, and D. The most common color filter pattern used in digital cameras, often referred to as the Bayer pattern, color A is red, color B and C are green, and color D is blue. 
         [0004]    Referring back to  FIG. 1 , image readout of the photo-generated charge begins with the transfer of some or all of the photodiode charge to the vertical CCD (VCCD)  30 . In the case of a progressive scan CCD, every photodiode simultaneously transfers charge to the VCCD  30 . In the case of a two field interlaced CCD, first the even numbered photodiode rows transfer charge to the VCCD  30  for first field image readout, then the odd numbered photodiode rows transfer charge to the VCCD  30  for second field image readout. 
         [0005]    Charge in the VCCD  30  is read out by transferring all columns in parallel one row at a time into the horizontal CCD (HCCD)  40 . The HCCD  40  then serially transfers charge to an output amplifier  50 . 
         [0006]      FIG. 1  shows an array of only 24 pixels. Many digital cameras for still photography employ image sensors having millions of pixels. A 10-megapixel image sensor would require at least ⅓ second to read out at a 40 MHz data rate. This is not suitable if the same camera is to be used for recording video. A video recorder requires an image read out in 1/30 second. The shortcoming to be addressed by the present invention is how to use an image sensor with more than 1 million pixels as both a high quality digital still camera and 30 frames/second video camera. 
         [0007]    The prior art addresses this problem by providing a video image at a reduced resolution (typically 640×480 pixels). For example, an image sensor with 3200×2400 pixels would have only every fifth pixel read out as described in U.S. Pat. No. 6,342,921. This is often referred to as sub-sampling, or sometimes as thinned out mode or skipping mode. The disadvantage of sub-sampling the image by a factor of 5 is only 4% of the photodiodes are used. A sub-sampled image suffers from reduced photosensitivity and alias artifacts. If a sharp line focused on the image sensor is only on the un-sampled pixels, the line will not be reproduced in the video image. Other sub-sampling schemes are described in U.S. Pat. Nos. 5,668,597 and 5,828,406. 
         [0008]    Prior art including U.S. Pat. No. 6,661,451 or US patent application publication 2002/0135689 A1 attempt to resolve the problems of sub-sampling by summing pixels together. However, this prior art still leaves some pixels un-sampled. 
         [0009]    US patent application publication 2001/0010554 A1 increases the frame rate by summing pixels together without sub-sampling. However, it requires a two field interlaced read out. It is more desirable to obtain a video image with progressive scan read out. Interlaced video acquires the two fields at different times. A moving object in the image will appear in different locations when each interlaced field is acquired. 
         [0010]    Another disadvantage of the prior art is it only reduces the image resolution in the vertical direction. In the horizontal direction, the HCCD must still read out every pixel. Only reducing the image resolution through sub-sampling or other methods in the vertical direction does not increase the frame rate to 30 frames/second for very large (greater than 8 million pixels) image sensors. 
         [0011]    US patent application publication 2003/0067550 A1 reduces the image resolution vertically and horizontally for even faster image readout. However, this prior art requires a striped color filter pattern (a 3×1 color filter array), which is generally acknowledged to be inferior to the Bayer or 2×2 color filter array patterns. 
         [0012]    If view of the deficiencies of the prior art, an invention is desired which is able to produce 30 frames/second video from a megapixel image sensor with a 2×2 color filter pattern while sampling 100% of the pixel array and reading out the video image progressive scan (non-interlaced). 
       SUMMARY OF THE INVENTION 
       [0013]    The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the invention resides in a method for reading out charge from an interlined CCD having a plurality of photo-sensing regions and a plurality of vertical shift registers, and each photosensitive region is mated respectively to a CCD of a vertical shift register and a color filter having a repeating pattern of two rows in which each row includes at least two colors spanning the photo-sensing regions, the method comprising (a) reading out one row from each of the two-row pattern; (b) summing the same color from each row in the vertical shift register to reduce the resolution by one half; (c) without transferring charge out of the vertical shift register, repeating step (a) and (b) for the remaining row; and (d) reading out the charge in the vertical shift registers in a manner in which different colors are not summed together. 
       ADVANTAGEOUS EFFECT OF THE INVENTION 
       [0014]    The present invention includes the advantage of producing 30 frames per second for video while sampling the entire pixel array. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a prior art image sensor; 
           [0016]      FIG. 2  is a typical prior art color filter array for image sensors; 
           [0017]      FIGS. 3   a  and  3   b  are diagrams illustrating flow of charge in image sensors of the present invention; 
           [0018]      FIG. 4  is a detailed view of a pixel including the VCCC; 
           [0019]      FIGS. 5   a - 5   c  are diagrams of an alternative embodiment of the flow of charge in image sensors of the present invention; 
           [0020]      FIGS. 6   a - 6   d  are an alternative embodiment of the flow of charge in the image sensors of the present invention; 
           [0021]      FIG. 7  is a side view of  FIGS. 6   a - 6   d  including the associated diagrams of clocking of the charge in the channels; 
           [0022]      FIG. 8  is a timing diagram of  FIG. 7 ; 
           [0023]      FIGS. 9   a - 9   f  is still further an alternative embodiment of the present invention; 
           [0024]      FIG. 10  is a side view of  FIGS. 9   a - 9   f  including the clocking of charge in the channel; 
           [0025]      FIG. 11  is a timing diagram of  FIG. 10 ; 
           [0026]      FIGS. 12   a - 12   f  are another alternative embodiment of the present invention; 
           [0027]      FIG. 13  is a side view of  FIGS. 12   a - 12   f  including the clocking of charge in the channel; 
           [0028]      FIG. 14  is a side view of a prior art image sensor including the flow of charge in the channel; 
           [0029]      FIG. 15  is a prior art timing diagram for  FIG. 14 ; 
           [0030]      FIG. 16  is a side view of a prior art image sensor including the flow of charge in the channel; 
           [0031]      FIG. 17  is a prior art timing diagram of  FIG. 16 ; 
           [0032]      FIG. 18  is the image sensor of the present invention including the VCCDs and HCCDs; 
           [0033]      FIGS. 19   a - 19   d  are diagrams of the image sensor of the present invention illustrating the clocking of charge in the VCCDs and HCCDs; 
           [0034]      FIGS. 20   a - 20   b  are diagrams of the image sensor of the present invention illustrating the clocking of charge in the HCCDs; 
           [0035]      FIG. 21  is a detailed view of the HCCDs; 
           [0036]      FIG. 22  is a timing diagram of  FIG. 21 ; 
           [0037]      FIGS. 23   a  and  23   b  are side views of the image sensor of  FIG. 22  illustrating the clocking of charge in the HCCDs in full resolution mode; 
           [0038]      FIG. 24  is a timing diagram of  FIGS. 23   a  and  23   b;    
           [0039]      FIGS. 25   a  and  25   b  are side views of the image sensor of the present invention illustrating the clocking of charge; 
           [0040]      FIG. 26  is a timing diagram for  FIGS. 25   a  and  25   b ; and 
           [0041]      FIG. 27  is a camera illustrating a typical commercial embodiment for the image sensor of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0042]    Referring to  FIGS. 3   a  and  3   b , there is shown the image sensor  100  of the present invention. For clarity, only a small portion of the pixel array of the image sensor  100  is shown. It consists of an array of photodiodes  120  with VCCDs  130  positioned in between columns of photodiodes  120 . There are color filters repeated in a 2×2 array spanning across the entire photodiode array. The 4 color filters A, B, C, and D are of 3 or 4 unique colors. The colors typically are, but not limited to, A=red, B=C=green, D=blue. Other common color schemes utilize cyan, magenta, and yellow or even white filters. 
         [0043]    Referring briefly to  FIG. 4 , one pixel is shown. The VCCD  130  is of the interlaced 4-phase type with two control gate electrodes  132  and  134  per photodiode  120 . 
         [0044]    Referring back to  FIG. 3   a , the full resolution read out of an image stored in the photodiodes  120  proceeds in the below-described manner for an interlaced image sensor  100 . First the charge in field  1 , consisting of all lines labeled as line  1 , is transferred from the photodiodes  120  to the adjacent VCCD  130 . The VCCD  130  will only receive charge from lines containing colors A and C. Once charge is in the VCCD  130 , it is transferred in parallel towards a serial HCCD (not shown) and then towards and output amplifier (not shown), as is well known in the art. Next in  FIG. 3   b , after all signal from colors A and C have been transferred out of the VCCD  130 , the remaining charge in the photodiodes  120  in line  2  is transferred into the VCCD  130 . This is field  2  containing only colors B and D. Since the image is read out in two fields, an external shutter is used to block light and prevent further accumulation of signal in the second field while the first field is being read out. 
         [0045]    When the sensor is installed in a digital camera and is to be used in video mode, the external shutter is held open and the image sensor  100  is operated continuously. Most applications define video as a frame rate of at least 10 frames/sec with 30 frames/sec being the most desired rate. Currently, image sensors are typically of such high resolution that full resolution image readout at 30 frames/sec is not possible at data rates less than 50 MHz and one or two output amplifiers. The solution of the present invention is to sum together pixels inside the image sensor to reduce the number of pixels down to a resolution allowing video rate imaging. 
         [0046]    First, the case where frame rate is increased by reducing the vertical resolution by half is discussed. Referring now to  FIG. 5   a , this is the same image sensor  100  that was shown in  FIGS. 3   a  and  3   b  with a different read out sequence. First, charge from the photodiodes  120  in line  1  and line  3  are transferred into the VCCD  130  and the VCCD  130  is clocked such that the two charge packets from lines  1  and  3  are summed together in the VCCD  130 . Now the image sensor  100  will be in the state shown in  FIG. 5   b . Two rows of colors A and C have been summed together and are held in the VCCD  130 . Next the remaining lines  2  and  4  are transferred from the photodiodes  120  to the VCCD  130 . Those two lines are then summed together without mixing together with the summed charge packets of lines  1  and  3 . Now the image sensor  100  will be in the state shown in  FIG. 5   c . All photodiodes  120  have been read out with two rows summed together. The charge packets corresponding to the colors A, B, C, and D are in the VCCD  130  with the original 2×2 color filter pattern arrangement maintained at half the vertical resolution. Now only one field needs to be transferred out of the VCCD thus increasing the frame rate. The sequence of  FIGS. 5   a - 5   c  are preferably under conditions where the exposure time is long relative to the time required to sum the pixels together in the VCCD  130 . If the camera is used outside in bright sunlight, the summing of pixels will enhance the sensitivity such that a very short exposure time will be required. The exposure time might be as short as 100 to 200 μs. The photodiodes  120  from color A are transferred to the VCCD  130  before photodiodes  120  from color B. This time difference is a significant time, about 40 μs. The color B photodiodes  120  will receive a longer exposure time than the photodiodes  120  from color A. Thus, video recording with very short exposure times will show an undesirable color hue shift. 
         [0047]    The short exposure color hue shift can be avoided by always transferring charge from photodiodes  120  of all colors simultaneously to the VCCD  130 . This is shown in  FIG. 6   a . Photodiodes  120  in lines  3  and  4  are transferred simultaneously to the VCCD  130 . Since all colors are transferred at the same time, there will be no hue shift for very short exposure. Charge remains in the photodiodes of lines  1  and  2 . 
         [0048]    Referring to  FIG. 6   b , the charge packets in the VCCD  130  are shifted down two lines to bring them into proper alignment to receive charge from the same colors in lines  1  and  2 . In  FIG. 6   c , charge from photodiodes  120  of lines  1  and  2  are transferred and summed with the same colors already present in the VCCD  130 . Now in  FIG. 6   d , the final state of the VCCD  130  after charge summing contains the 2×2 color filter pattern of the original photodiode array with the vertical resolution decreased by half. The charge packets in the VCCD  130  are transferred out of the imager as a single field progressive scan image. The progressive scan image eliminates problems with interlaced field separation. This read out method also samples every pixel in the image for maximum photo-sensitivity and minimal moiré artifacts and minimal color alias. 
         [0049]    Referring to  FIG. 7 , the details of the clocking of charge packets are shown.  FIG. 7  is a cross section down the center of the VCCD  130  of the column containing pixels of colors A and B. The labels A or B and a numerical subscript identify the charge packets. The Letter identifies which color photodiode the charge packet originated from. The subscript identifies which photodiode line the charge packet originated from. The labels T 0  through T 5  mark the time steps of the charge transfer clocking sequence in  FIG. 8 . The gates in  FIG. 7  are wired to 8 control voltages V 1  through V 8 . The voltages applied to each of the gates at each time step is shown in  FIG. 8 . The voltage on a gate is one of three levels: VL is the lowest level creating a barrier in the VCCD channel potential (the off state), VM is the middle level creating a well in the VCCD channel potential (the on state), VH is the high level which turns on the transfer channel between the photodiodes and VCCD. 
         [0050]    The clocking sequence begins in  FIG. 8  by turning on the photodiode transfer channel under gates V 5  and V 8  of  FIG. 7 . This puts charge packets A 3  and B 4  into the VCCD. This is indicated at time step T 0  of  FIG. 7 . The gate voltages are changed according to  FIG. 8  from time steps T 1  through T 4  to advance the charge packets by 4 gates (two lines). Then the photodiode transfer channel under gates V 1  and V 4  are turned on to add charge packets A 1  and B 2  to charge packets A 3  and B 4 . After time step T 5  the VCCD is clocked with the well-known standard 4-phase CCD timing sequence. Since the number of lines is reduced by half, the frame rate for the image sensor doubles.  FIG. 8  does not represent the only possible timing diagram, those skilled in the art can produce many small variations to produce the same charge summing result. 
         [0051]    Sometimes a factor of two-speed increase is not sufficient. Also, a video image is desired to be 480 lines. An image sensor with 1440 lines must be reduced by a factor of three. 
         [0052]    Next, the VCCD clocking sequence for reducing the number of lines by a factor of three is discussed. Referring to  FIG. 9   a , charge in the photodiodes  120  of lines  2  and  5  only are transferred to the VCCD  130 . Then in  FIG. 9   b , the VCCD  130  transfers charge by two lines to align the charge packets from lines  2  and  5  with lines  3  and  6 . In  FIG. 9   c , the charge from the photodiodes  120  in lines  3  and  6  is transferred and added on top of the charge packets already in the VCCD  130 . In  FIG. 9   d , the summed charge packets are transferred another two lines to align them with lines  1  and  4 . Now in  FIG. 9   e , the last remaining photodiode charge in lines  1  and  4  are transferred and added on top of the charge packets already in the VCCD  130 . After the final photodiode transfer in  FIG. 9   f , there is the 2×2 color filter pattern in the VCCD  130  with one-third the number of lines as the original full resolution image. 
         [0053]    Note that in the sequence of  FIGS. 9   a - 9   f , every time there is a photodiode to VCCD transfer, all four colors of the 2×2 color filter pattern were transferred to the VCCD  130  simultaneously. 
         [0054]      FIG. 10  details the clocking of charge packets for reducing the number of lines by a factor of three.  FIG. 10  is a cross section down the center of the VCCD of the column containing pixels of colors A and B. The labels A or B and a numerical subscript identify the charge packets. The Letter identifies witch color photodiode the charge packet originated from. The subscript identifies witch photodiode line the charge packet originated from. The labels T 0  through T 8  mark the time steps of the charge transfer clocking sequence in  FIG. 11 . The gates in  FIG. 10  are wired to 12 control voltages V 1  through V 12 . The voltages applied to the gates at each time step are shown in  FIG. 11 . The VCCD will be clocked as a 6-phase CCD with four gates normally on and two gates normally off. 
         [0055]    The clocking sequence begins in  FIG. 11  by turning on the photodiode transfer channel under gates V 4  and V 10  of  FIG. 10 . This puts charge packets A 2  and B 5  into the VCCD. This is indicated at time step T 0  of  FIG. 10 . The gate voltages are changed according to  FIG. 11  with 6-phase CCD timing from time steps T 1  through T 4  to advance the charge packets by 4 gates (two lines). Then the photodiode transfer channel under gates V 6  and V 12  are turned on to add charge packets A 6  and B 3  to charge packets A 2  and B 5 . From time step T 4  to T 8  the VCCD is clocked to advance the charge packets another 4 gates. This aligns the charge packets with the photodiodes in lines  1  and  4 . The photodiode transfer channel under gates V 2  and V 8  are turned on to add charge packets B 1  and A 4  to the charge packets already in the VCCD. After time step T 8  all of the photodiodes have be read out and the image is in the VCCD with one third the number of lines. It is read out of the VCCD by using 6-phase CCD clocking.  FIG. 11  does not represent the only possible timing diagram, those skilled in the art can produce many small variations to produce the same charge summing result. 
         [0056]      FIGS. 12   a - 12   f  show alternative charge transfer sequences for summing together three lines. Referring to  FIG. 12   a , charge in the photodiodes  120  of lines  5  and  6  only are transferred to the VCCD  130 . Then in  FIG. 12   b , the VCCD  130  transfers charge by two lines to align the charge packets from lines  5  and  6  with lines  3  and  4 . In  FIG. 12   c , the charge from the photodiodes  120  in lines  3  and  4  are transferred and added on top of the charge packets already in the VCCD  130 . In  FIG. 12   d , the summed charge packets are transferred another two lines to align them with lines  1  and  2 . Now in  FIG. 12   e , the last remaining photodiode charge in lines  1  and  2  are transferred and added on top of the charge packets already in the VCCD  130 . After the final photodiode transfer in  FIG. 12   f , there is the 2×2 color filter pattern in the VCCD  130  with one-third the number of lines as the original full resolution image. 
         [0057]    Note that in the sequence of  FIGS. 12   a - 12   f , every time there is a photodiode to VCCD transfer, all four colors of the 2×2 color filter pattern were transferred to the VCCD  130  simultaneously. 
         [0058]    Referring to  FIG. 13 , the detail for the charge transfer sequence of  FIGS. 12   a - 12   f  is shown. At time step T 0  in  FIG. 13 , the photodiode to VCCD transfer channel under gates V 9  and V 12  is turned on to transfer charge packets from color B line  5  (B 5 ) and color A line  6  (A 6 ). The A 6  and B 5  charge packets are transferred two lines using 6-phase CCD clocking. Next the color B line  3  (B 3 ) is transferred from the photodiode to VCCD under gate V 5  and color A line  4  (A 4 ) is transferred from the photodiode to VCCD under gate V 8 . The summed charge packets A 4 +A 6  and B 3 +B 5  are transferred two lines in the VCCD with 6-phase clocking. The final two rows of charge are transferred from the photodiodes to the VCCD under gates V 1  and V 4 . The A 2  and B 1  charge packets are added to the A 4 +A 6  and B 3 +B 5  charge packets already in the VCCD. 
         [0059]    Thus far the present invention discloses how to sum together two lines or three lines of charge packets to increase the frame rate by a factor of two or three. Even if an image sensor with 1440 lines is reduced in resolution to 480 lines by summing three line pairs it will still take longer than 1/30 sec to read out an image. The solution to faster image read out is to also sum together charge packets in the HCCD. 
         [0060]    Referring to  FIG. 14 , there is shown a well-known prior art HCCD. It is a pseudo-two phase CCD employing four control gates per column. Each pair of two gates H 1 , H 2  and H 3  are wired together with a channel potential implant adjustment  380  under one of the two gates. The channel potential implant adjustment  380  controls the direction of charge transfer in the HCCD. Charge is transferred from the VCCD one line at a time under the H 2  gates of the HCCD.  FIG. 14  shows the presence of charge packets from the line containing colors A and C from  FIG. 1 . The charge packets are advanced serially one row through the HCCD at time steps T 0 , T 1 , and T 2 , by applying the clock signals of  FIG. 15 . 
         [0061]    U.S. Pat. No. 6,462,779 provides a method of summing two pixels in the HCCD to reduced the total number of HCCD clock cycles in half. This is shown in  FIG. 16 . This method is designed for linear image sensors where all pixels are of one color. In a two dimensional array employing the 2×2 color pattern of  FIG. 2 , each line has more than one color. Thus, in  FIG. 16  when a line containing colors A and C is transferred into the HCCD and clocked with the timing of  FIG. 17  the colors A and C are added together. That destroys the color information and the image. 
         [0062]    The present invention shown in  FIG. 18  provides a method to prevent the mixing of colors when summing pixels in the HCCD. The invention consists of an array of photodiodes  430  covered by a 2×2 color filter pattern of four colors A, B, C, and D. Charge packets from the photodiodes  430  are transferred and summed vertically in the VCCD  420  using the two or three line summing described earlier. The two line summing is depicted in  FIG. 18 . There is a first HCCD  400  and a second HCCD  410  located at the bottom of the pixel array. There is a transfer channel  460  every other column for the purpose of transferring half of the charge packets from the first HCCD  400  to the second HCCD  410 . There is an output amplifier  440  and  450  at the end of each HCCD for converting the charge packets to a voltage for further processing. 
         [0063]      FIGS. 19   a - 19   d  shows the charge transfer sequence for reading out one line through the HCCD. First in  FIG. 19   a , one line containing colors A and C is transferred into the first HCCD  400  as shown in  FIG. 19   b . Charge packets are labeled with a letter corresponding to the color and a subscript corresponding to the column from which the charge packet originated. In  FIG. 19   c , the charge packets from the even numbered columns only pass through the transfer gate  460  and into the second HCCD  410 . In  FIG. 19   d , the charge packets in the second HCCD  410  are advanced by one column to align them with the charge packets in the first HCCD  400 . The number of clock cycles needed to read out each HCCD is equal to one half the number of columns in the HCCD. The addition of a second HCCD  410  reduces the read out time by half. Most importantly, each HCCD now contains only one color type. 
         [0064]    Two charge packets may be summed together horizontally in each HCCD  400  and  410  as shown in  FIGS. 20   a  and  20   b . The summing is done without mixing charge packets of different colors. The two pixel summing reduces the number of charge packets to read out of each HCCD  400  and  410  by another factor of two. This HCCD design provides a total speed improvement of a factor of four. Combined with the two line or three line summing described earlier allows an eight or twelve fold increase in frame rate for a video mode. That is enough to allow sampling of all pixels in an 11 million-pixel image sensor at a frame rate of 30 frames/second. 
         [0065]      FIG. 21  shows the HCCD structure in greater detail. There is the first HCCD  400  and second HCCD  410  fabricated on top of an n-type buried channel CCD  520  in a p-type well or substrate  540 . The buried channel CCD  520  has channel potential implant adjustments  530  for pseudo-2-phase clocking. The top portion of  FIG. 21  shows the side view cross section K-M through the first HCCD  400 . There are seven wires, which supply the control voltages to the HCCD gates H 1  through H 7 . An additional wire TG controls the transfer gate between the two HCCDs  400  and  410 . The gate electrodes are typically, but not required to be, poly-silicon material of at least two levels. A third level of poly-silicon may be used for the transfer gate if the manufacturing process used does not allow the first or second levels of poly-silicon to be used. With careful use of implants in the buried channel of the transfer gate region and slightly modified gate voltages the transfer gate can be omitted entirely. The exact structure of the transfer gate is not important to the function of the invention. 
         [0066]    The clock voltages applied to the HCCD of  FIG. 21  are shown in  FIG. 22  for transfer of charge from the first HCCD to the second HCCD. At time T 0  of  FIG. 22 , the H 1 , H 6  and H 7  gates are switched high to receive charge from the first VCCD  400 . The H 2 , H 3 , and H 4  barrier gates are held low to prevent the mixing of charge packets in the first HCCD  400 . At time T 1  the transfer gate TG is turned on and H 1  is clocked low to transfer only the charge packets under the H 1  gate from the first HCCD  400  to the second HCCD  410 . TG is turned off at time T 2 . Finally at time T 3 , the second HCCD clocks are switched to advance the charge packets in the second HCCD  410  so the charge packets are held under the same gate as the first HCCD  400  charge packets. 
         [0067]    The following discusses the readout of the HCCD in full resolution mode for still photography.  FIG. 23   a  shows the charge transfer sequence for the first HCCD and  FIG. 23   b  shows the charge transfer sequence for the second HCCD. A letter corresponding to the color of the charge packet, A, B, C, or D, identifies the charge packets. The subscript on the charge packet label corresponds to the column number of the charge packet. The clock voltages for each time step are shown in  FIG. 24 . The HCCD is clocked as a pseudo 2-phase CCD between two voltages H and L. The transfer gate TG is held in the off state (L) to prevent mixing of charge between the two HCCDs. 
         [0068]    In video mode, two charge packets are summed together as shown in  FIG. 25   a  for the first HCCD and  FIG. 25   b  for the second HCCD. Notice that the first HCCD only contains charge packets from pixels of color A and the second HCCD only contains charge packets from pixels of color C.  FIG. 26  shows the gate voltage clocking sequence. Gates H 1 , H 2 , and H 5  are held constant at a voltage approximately halfway between H and L. The voltages H and L in video mode do not have to be equal to the voltages used for fill resolution still photography. Only gates H 3 , H 4 , H 6  and H 7  are clocked in a complimentary manner. As can be seen in  FIGS. 25   a  and  25   b  one clock cycle advances the charge packets by four columns in the HCCD. This is what provides the factor of four-speed increase in video mode. 
         [0069]    Due to the large number of photodiode charges being summed together there is the possibility of too much charge in the VCCD or HCCD causing blooming. The VCCD and HCCD can easily be overfilled. It is widely known that the amount of charge in a vertical overflow drain type photodiode is regulated by a voltage applied to the image sensor substrate. This voltage is simply adjusted to reduce the photodiode charge capacity to a level to prevent overfilling the VCCD or HCCD. This is the exact same procedure normally used even without summing together pixels. 
         [0070]      FIG. 27  shows an electronic camera  610  containing the image sensor  600  capable of video and high-resolution still photography as described earlier. In video mode 100 percent of all pixels are sampled. 
         [0071]    The VCCD charge capacity is controlled by the amplitude of the VCCD gate clock voltages. Since the invention sums charges in the HCCD the VCCD does not have to contain full charge packets in order to produce a full signal at the output amplifiers. If the HCCD will sum together two charge packets then VCCD charge capacity can be reduced by a factor of two by lowering the amplitude of the VCCD clock voltages. The advantage of lowing the VCCD clock voltages is reduced power consumption in video mode. The power consumption varies as the voltage squared. Thus a camera would increase the VCCD clock voltages if the camera is operating in still photography mode, or decrease the VCCD clock voltages if the camera is operating in video mode. 
         [0072]    The invention has been described with reference to a preferred embodiment. However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention. 
       PARTS LIST 
       [0000]    
       
           10  Image Sensor (CCD) 
           20  Photodiodes 
           30  Vertical CCD (VCCD) 
           40  Horizontal CCD (HCCD) 
           50  Output Amplifier 
           100  Image Sensor 
           120  Photodiodes 
           130  Vertical CCD (VCCD) 
           132  Control Gate Electrodes 
           134  Control Gate Electrodes 
           380  Channel Potential Implant Adjustment 
           400  First Horizontal CCD (HCCD) 
           410  Second Horizontal CCD (HCCD) 
           420  Vertical CCD (VCCD) 
           430  Photodiodes 
           440  Output Amplifier 
           450  Output Amplifier 
           460  Transfer Channel 
           520  n-type Buried Channel CCD 
           530  Channel Potential Implant Adjustment 
           540  p-type Well or Substrate 
           600  Image Sensor 
           610  Electronic Camera

Technology Category: 5