Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to network interconnecting devices in general and, in particular, to LAN switches in which the ports are configured to enable communications between the port and attached devices. 
     2. Prior Art 
     The interconnection of devices with LAN switches is well known in the prior art. Two types of communications protocols are used to effectuate communications in the network. The Token Ring and ethernet or CSMA/CD (Collision Detect) are the major types of protocol that are well known. The present invention (described below) relates to the Token Ring protocol and further discussion of ethernet or CSMA/CD will not be given. 
     The details of the Token Ring protocol are set forth in the IEEE 802.5 standard for Local Area Network (LAN) and are incorporated herein by reference. As a consequence, only the portions of the standard that are required to understand the present invention will be given. Historically, Token Ring has a 4 Mbps (Mega bit per second) or 16 Mbps data transmission rate. The protocol for Token ring is usually implemented in a Medium Access Control (MAC) chip which is embedded in a device termed “adapter” which interfaces a device or switch port to the transmission mechanism that interconnects the switch port and the device. 
     In order to simplify system setup and make the switch more user friendly, circuit arrangements, termed “configuror”, are provided in the ports to reconfigure them so that the communication between ports and attached devices is made possible. Examples of prior art configurors and methods are set forth in U.S. Pat. Nos. 5,625,621 and 5,680,397. Both patents are assigned to the assignee of the present invention and are incorporated herein by reference. 
     In order to increase the speed and throughput of Token Ring networks, the IEEE 802.5 Amendment 1 has promulgated a 100 Mbps standard. Among the things or requirements set forth in the standard are signal shape and other signal characteristics that are sensitive to impedance changes. To be compatible with the standard, the 100 Mbps must be met with different types of cable, such as Shielded Twisted Pair (STP), Unshielded Twisted Pair (UTP), with different types of resistance (i.e., 150 Ohms or 100 Ohms). 
     In view of the IEEE 802.5 Amendment 1, there is a need for device to reconfigure high speed port of a Token Ring Switch. 
     SUMMARY OF THE INVENTION 
     The present invention provides a circuit arrangement (configuror) that configures high speed ports so that signals on the transmit and receive conductors meet the IEEE 802.5 Amendment 1 standard (incorporated herein by reference) without causing signal degradation on both UTP and STP wiring. The circuit arrangement, also, compensates for variations in transmission impedance. A software protocol is then executed as a dialogue between partners (port and attached device) so that both can appropriately auto detect and configure. 
     The circuit arrangement includes two impedance matching transformers with first and second sets of windings connected to different pins in different connectors located at the high speed port of the switch. A third and fourth Sets of windings are switchable coupled to a switching relay. A controller drives the switching relay so that a capacitor coupled to the primary side of one of the transformer connects the transmit pair to ground potential whether the configuration is in a straight feed through mode or a crossover mode. In the straight feed through mode, signals are received through selected windings of one of the transformers and signals are transmitted through selected windings of the other transformer. 
     In crossover mode, signals are transmitted via selected windings of said one of the transformer; whereas signals are received via selected ones of the other transformers. The above, as well as additional features and advantages of the present invention, will become apparent. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a switch with a high speed port according to the teachings of the present invention. 
     FIG. 2 shows the Port Configuror arranged in the Straight Feed Through mode. 
     FIG. 3 shows a Port Configuror in the Cross-Over mode. 
     FIG. 4 shows the flowchart of a program used by the port controller to configure the port. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows a schematic of a Switch  10  embodying the teachings of the present invention. Switch  10  includes Housing  10 ′ to which a plurality of ports, port  1  through port N, are fabricated. In the figure, port  1  is the high speed (100 Mbps) port which is designed and managed pursuant to IEEE 802.5 and IEEE 802.5 Amendment 1, which are incorporated herein by reference. In the preferred embodiment of this invention, port  1  is fitted with two connectors identified as Con  1  and Con  1 ′. The dual connectors and other port structures, including the “configuror”, are not part of the standard. As will be explained hereinafter, Connector  1  could be connected to one type of media with a first type of impedance; whereas, Connector  1 ′ is connected to another type of media with a different impedance. In the preferred embodiment of the invention, one of the connectors is connected to a 100 Ohms transmission line, while the other is connected to a 150 Ohms transmission line. The transmission lines are twisted pair, shielded or unshielded. The other ports,  2  through N in the switch, are provided with connectors labeled Con  2  through Con N. In the preferred embodiment of this invention, each of these ports can operate as specified in the IEEE 802.5 standard. Essentially, these ports can operate at {fraction (4/16)} Mbps. The configuration of these ports are in accordance with the teachings set forth in the above referenced IBM patents which are incorporated herein by reference. 
     Each of the ports is connected by a port (PT) module (MOD) to a Switch Fabric  14 . Each of the port modules,  2  through port module N, are provided with a Port  18  Configuror  2  through Port Configuror N. The port configuror configures the port in accordance with the teachings set forth in the above referenced IBM patents. In addition, each of the port modules  2  through port module N are provided with circuitry in accordance with the teachings of IEEE 802.5 standard for Token Ring. Since this standard and mode of configuration are well known in the art, further description or discussion of these modules will not be given. The remaining portion of this document relates to the High Speed Port  1  which is the subject matter of the present invention. 
     Still referring to FIG. 1, the Port Module  1  includes Medium Access Control (MAC) functions in accordance with the IEEE 802.5 standard for Token Ring. These standards are well known In the prior art and, therefore, a detailed description will not be given. Suffice it to say that the functions enable the transmission and reception of frames. The Port Configuror  1  provides configuration for the high speed port. The IEEE 802.5 Amendment 1 describes the details; such as, signal characteristics which are required to operate the port at high speed are incorporated herein by reference. 
     Still referring to FIG. 1, the Switch Fabric  14  exchanges information between ports of the switch, thereby enabling the device not shown connected to any one of the ports to communicate with the device connected on the other port. The Switch Fabric  14  can be as simple as a high speed bus or as complicated as a cross-point switch. These switching sub-assemblies are well known in the prior art and further description will not be given. A Controller  12  through a Control Interface  12 ′ and a Control Bus  12 ″ provide connection to the switch fabric and each of the port modules. The Controller  12  and its attachment provide the switch level functions such as: 
     Timing signals for the switch fabric 
     Port-to-Port routing based on the source and destination address of the data 
     Broadcasting of data among multiple ports 
     Frame data address resolution (determine the exit port based on the destination address in the data) 
     In the the preferred embodiment of the invention, Controller  12  is a programmed microprocessor. 
     FIGS. 2 and 3 show circuit diagrams for the circuit arrangement termed “Port Configuror” provided in the high speed switch port. The function of the Port Configuror is to configure the port so that data terminal equipment such as a PC, server, word processing station, etc., connected to the port can exchange information between the port and the device. As stated previously, the configuration is both physical and logical. For the physical configuration, the transmit pair and receiver pair of conductors are determined; whereas, for the logical configuration, the port is marked primary or secondary in accordance with the terminology used in IEEE 802.5 standard for Token Ring. Similarly, the station that is connected to the port is characterized as a primary or secondary. 
     Still referring to FIGS. 2 and 3, the primary difference between these two figures is that in FIG. 2, the port is configured in a straight feed through mode; whereas, in FIG. 3, the port is configured in a cross-over mode. The distinction between the straight feed through and cross-over mode will be given as soon as the basic circuit arrangement is described. Because both figures are substantially identical except for the setting in switch relay  3 , FIG. 3 will be used to describe the port configuror. It should be noted that common elements in both figures are identified with similar characters. 
     Referring now to FIG. 3, two connectors labeled  6  and  7  are positioned in the high speed Port  8  of the switch. In the preferred embodiment of this invention, Connector  6  is a DB-9 Connector with its output connected to a 150 Ohms transmission line. This transmission line connects the Connector  6  to a data terminal equipment at the other end (the data terminal is omitted for simplification and clarity). The DB-9 Connector includes four terminals labeled  6 ,  1 ,  9  and  5 . Terminals  5  and  9  are the “read” terminal (RD+, RD−) and are connected to Windings A and B of Transformer  4 . Terminals  1  and  6  of Connector  6  are the “transmit” terminals (TD+, TD−) and are connected to Windings E and F of Transformer  5 . 
     Still referring to FIG. 3, Connector  7  is an RJ-45 connector and its output is connected to 100 Ohms transmission line which connects the connector to a device not shown. Connector  7  includes pins  5 ,  4 ,  6  and  3 . Pins  3  and  6  are the pins for the read signal and are connected through Coil  4 ′ to Windings C and D of Transformer  4 . Similarly, Pins  4  and  5  of Connector  7  are the transmit pins and are connected through Coil  5 ′ to Coils G and H of Transformer  5 . A Capacitor C 4  connectors the center tap between Windings C and D to a ground potential. Likewise, Capacitor C 5  connects the center tap of Windings G and H to a ground potential. 
     Still referring to FIG. 3, the primary side of Transformer  4  has two windings labeled J, K and port connection labeled RD+, CT-RD (a center tap) and RD−. These port connections are coupled through Switching Relay  3  to terminals labeled Rx+, CT and Rx− on the Media Access Control Circuit  1 . As will be explained subsequently, the connection of these terminals can be changed depending on the signal which Media Access Control Circuit  1  outputs on Switch Control  2 . 
     Still referring to FIG. 3, Transformer  5  has a primary side with Windings L, M and port connections labeled TD+, CT TD (center tap), and TD−. The Media Access Control Circuit  1  has terminal Tx+, Tx−. A Capacitor C 3  couples the Switch Relay  3  to a ground potential. 
     FIG. 3 shows a system configured in a cross-over mode configuration. In the cross-over mode configuration, the transmit terminals (Tx+, Tx−) of the assembly is connected through Switch Relay  3  to the read positive (RD+) and read negative (RD−) terminal of the Transformer  4 . In addition, C 3  is coupled through the switching relay to the center tap (CT-RD) of Transformer  4 . Likewise, the Rx+, Rx− and CT terminals of the Media Access Control Circuit  1  are connected through Switch Relay  3  to TD+, CT-TD, and TD− of Transformer  5 . In this cross-over mode, the center tap terminal of Transformer  4  Is connected through C 3  to a ground potential. The control signal for changing the contacts of Switch Relay  3  is provided on Switch Control  2  and is generated by the Media Access Control Circuit  1  (details to be given hereinafter). 
     With reference to FIG. 2, for the moment, the showing in FIG. 2 represents the circuit arrangement in the straight feed through configuration. In the feed through configuration, Rx+ is connected to RD+, CT is connected to CT RD, and Rx− is connected to the RD− terminal of Transformer  4 . Similarly, Tx+ is connected to TD+ and CT TD is connected through Capacitor C 3  to ground potential. Finally, Tx− is connected to TD− of Transformer  5 . In essence, in the feed through configuration there is no cross-over. The receiver terminal, negative and positive, of the Media Access Control Circuit  1  is tied to the read terminals and center tap terminal of Transformer  4 . In a similar manner, the transmit (Tx+ and Tx−) are tied to TD+, TD− of Transformer  5  and C 3  is tied to CT TD of Transformer  5 . As stated above, the switching of the Switch Relay  3  to make the proper connection is determined by the circuit in the media access control of the port. It is this control circuit that will now be described. 
     In the preferred embodiment of this Invention, the controller is a microprocessor located within the Media Access Control Circuit  1  executing the program shown in FIG.  4 . The program on the left side of an imaginary broken line (not shown) is used to configure the port physically. Stated another way, the program is used to determined the pair of conductors that are the transmit pair and the pair of conductors that are the receive pair. The circuit on the right side of the imaginary dotted line (not shown) configures the circuit logically. In other words, the flowchart on the right side of the broken line (not shown) identifies the port which is termed “primal” or “secondary”. The primary and secondary designations are in accordance with the IEEE 802.5 standard. Likewise, the station or device which is connected to the port can be termed either “primary” or “secondary”. As stated previously, the device or station which is connected to the port is provided with an adapter practicing the 802.5 protocol. Likewise, an adapter or functions of adapters practicing the same IEEE standard for Token Ring is provided at the port of the switch. With reference to FIGS. 2,  3  and  4 , when the machines are first powered on, the main processor (Controller  12 —FIG. 1) executes diagnostics to verify the operation of the Token Ring design. 
     Once a link active signal has been detected by ( 24 ) or ( 29 ), the physical connection has been established. Each end must now make the logical connection using a similar process. This process is started by ( 32 ) in which the Media Access Control Circuit  1  assumes it is the primary end and sends a primary command ( 32 ) to logically establish a connection with the secondary. The Media Access Control Circuit  1  then tests for a secondary response in ( 33 ) and ( 34 ) for a period of three seconds. If a response is received, the Media Access Control Circuit  1  informs the system processor that it is ready for transferring data ( 43 ). If no response is received, a random wait time is generated with ( 35 ) and ( 36 ) as described previously. However, in this scenario, the Media Access Control Circuit  1  changes to secondary ( 37 ) and waits up to three seconds for a primary command to be received ( 38  and  39 ). If a primary command is received, the Media Access Control Circuit  1  sends a secondary response ( 42 ) to the primary command and it is ready for data transfer ( 43 ). If no response is received, a random wait time is generated with ( 40 ) and ( 41 ) and the process is repeated until both the primary and secondary ends have established a logical connection. When a logical connection is established, the system processor CTRL  12  is notified that the Media Access Control Circuit  1  is ready for data transfer ( 43 ). 
     In summary, the teachings of the present invention configures the high speed port of the switch. The configuration is done both physically and logically. The high speed station is a full duplex station which is able to transmit and receive data simultaneously; thus, meeting the requirement set forth in IEEE 802.5 Amendment 1 for 100 megabits per second station. 
     While the invention has been particularly shown and described with reference for preferred embodiment, it will be understood by those skilled in the art that various changes in both form and detail may be made therein without departing from the scope and spirit of the invention.

Technology Category: 5