Patent Document

CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of priority to Chinese Patent Application No. 201410226541.6, filed with the Chinese Patent Office on May 27, 2014 and entitled “SHIFT REGISTER AND METHOD OF DRIVING THE SAME, AND GROUP OF SHIFT REGISTERS AND METHOD OF DRIVING THE SAME”, the content of which is incorporated herein by reference in its entirety. 
       TECHNICAL FIELD 
       [0002]    The present invention relates to the field of driving devices and particularly to a shift register and method of driving the same, and a group of shift registers and method of driving the same in a display drive circuit. 
       BACKGROUND OF THE INVENTION 
       [0003]    In recent years, an active matrix display device has been popularized, for example, widely applied in a mobile phone, a tablet computer, an MP3, an MP4 and other mobile devices. In the prior art, the display device comprises a plurality of scan lines (gate lines), a plurality of signal lines (data lines), a scan line (gate line) drive circuit and a signal line (data line) drive circuit. The respective drive circuits are embodied as scan circuits constituted of a plurality of transistors. 
         [0004]    A Complementary Metal Oxide Semiconductor (CMOS) circuit composed of some n-channel transistors (NMOS) and some p-channel transistors (PMOS) is generally used in a shift register constituting such a scan circuit. However the concurrent fabrication of both the n-channel transistors and the p-channel transistors may result in the problems of a large number of process steps in and a high production cost of fabricating the Complementary Metal Oxide Semiconductor (CMOS) circuit. 
         [0005]    Moreover capacitor devices are also present in the shift register of the scan circuit, and the combination of the capacitors and the transistors may have the circuit complicated and the number of devices further increased, thus resulting in an increase in area of the frame edge of a display. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    One inventive aspect is a shift register. The shift register includes first through sixth transistors. A gate of the first transistor is connected to a first clock signal terminal, a source of the first transistor is connected to a first input signal terminal, and a drain of the first transistor is connected to a source of the second transistor and a gate of the sixth transistor. A gate of the second transistor is connected to a first level signal terminal, the source of the second transistor is connected to the drain of the first transistor and the gate of the sixth transistor, and a drain of the second transistor is connected to a gate of the third transistor. The gate of the third transistor is connected to the drain of the second transistor, a source of the third transistor is connected to a second clock signal terminal, and a drain of the third transistor is connected to an output terminal and a drain of the fifth transistor. A gate of the fourth transistor is connected to a source of the fourth transistor, the gate and the source of the fourth transistor are connected to a second input signal terminal, and a drain of the fourth transistor is connected to a gate of the fifth transistor and a drain of the sixth transistor. The gate of the fifth transistor is connected to the drain of the fourth transistor and the drain of the sixth transistor, a source of the fifth transistor is connected to a second level signal terminal and a source of the sixth transistor, and the drain of the fifth transistor is connected to the output terminal and the drain of the third transistor. The gate of the sixth transistor is connected to the drain of the first transistor and the source of the second transistor, the source of the sixth transistor is connected to the second level signal terminal and the source of the fifth transistor, and the drain of the sixth transistor is connected to the drain of the fourth transistor and the gate of the fifth transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a circuit diagram of a shift register according to an embodiment of the invention; 
           [0008]      FIG. 2  is a timing diagram of the shift register in  FIG. 1  in operation; 
           [0009]      FIG. 3  is a schematic structural diagram of a group of shift registers according to an embodiment of the invention; and 
           [0010]      FIG. 4  is a timing diagram of the group of shift registers in  FIG. 3  in operation. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0011]    Particular embodiments of the invention will be described below in details with reference to the drawings in order to make the foregoing objects, features and advantages of the invention more apparent and readily understood. 
         [0012]    Numerous details will be set forth in the following description so as to facilitate understanding of the invention, but the invention can alternatively be practiced in other embodiments than those described here, so the invention will not be limited to the particular embodiments to be disclosed below. 
         [0013]    An embodiment of the invention provides a shift register, and  FIG. 1  illustrates a schematic circuit scheme of the shift register comprising: a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , a fifth transistor M 5  and a sixth transistor M 6 . 
         [0014]    A gate of the first transistor M 1  is connected to a first clock signal terminal CK 1 , a source of the first transistor M 1  is connected to a first input signal terminal IN 1 , and a drain of the first transistor M 1  is connected to a source of the second transistor M 2  and a gate of the sixth transistor M 6  to a node N 1 ; 
         [0015]    A gate of the second transistor M 2  is connected to a first level signal terminal VGL, the source of the second transistor M 2  is connected to the drain of the first transistor M 1  and the gate of the sixth transistor M 6  to the node N 1 , and a drain of the second transistor M 2  is connected to a gate of the third transistor M 3  to a node N 3 ; 
         [0016]    The gate of the third transistor M 3  is connected to the drain of the second transistor M 2 , a source of the third transistor M 3  is connected to a second clock signal terminal CK 2 , and a drain of the third transistor M 3  is connected to an output terminal OUT and a drain of the fifth transistor M 5 ; 
         [0017]    A gate of the fourth transistor M 4  is connected to a source thereof and a second input signal terminal IN 2 , and a drain of the fourth transistor M 4  is connected to a gate of the fifth transistor M 5  and a drain of the sixth transistor M 6  to a node N 2 ; 
         [0018]    The gate of the fifth transistor M 5  is connected to the drain of the fourth transistor M 4  and the drain of the sixth transistor M 6  to the node N 2 , a source of the fifth transistor M 5  is connected to a second level signal terminal VGH and a source of the sixth transistor M 6 , and the drain of the fifth transistor M 5  is connected to the output terminal OUT and the drain of the third transistor M 3 ; and 
         [0019]    The gate of the sixth transistor M 6  is connected to the drain of the first transistor M 1  and the source of the second transistor M 2 , the source of the sixth transistor M 6  is connected to the second level signal terminal VGH and the source of the fifth transistor M 5 , and the drain of the sixth transistor M 6  is connected to the drain of the fourth transistor M 4  and the gate of the fifth transistor M 5  to the node N 2 . 
         [0020]    Furthermore all of the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5  and the sixth transistor M 6  are PMOS transistors. 
         [0021]    In this embodiment, an input signal at the first level signal terminal VGL is a low-level signal, an input signal at the second level signal terminal VGH is a high-level signal, a first input signal is input to the first input signal terminal IN 1 , a second input signal is input to the second input signal terminal IN 2 , a first clock signal is input to the first clock signal terminal CK 1 , and a second clock signal is input to the second clock signal terminal CK 2 , where the second clock signal is opposite in phase to the first clock signal.  FIG. 2  illustrates a timing diagram thereof in operation, and a method of driving the shift register according to this embedment will be described with reference to  FIG. 1  and  FIG. 2 . 
         [0022]    As illustrated in  FIG. 1  and  FIG. 2 , a drive process comprises three phases including a reset phase a, a shift phase b and a turn-off phase c respectively. 
         [0023]    In the reset phase a: 
         [0024]    The first clock signal which is a low-level pulse signal in the reset phase a is input to the first clock signal terminal CK 1  to turn on the first transistor M 1 ; 
         [0025]    The low-level signal is input to the first input signal terminal IN 1  and is transmitted by the first transistor M 1  to the gate of the sixth transistor M 6  and the source of the second transistor M 2 , and the potential at the node N 1  is at a low level, thus turning on the sixth transistor M 6 ; 
         [0026]    Since the source of the sixth transistor M 6  is connected to the second level signal terminal VGH to which the second level signal which is a high-level signal is input, that is, the level of the signal is constant and higher than the level of the subsequent first level signal, the high-level signal is transmitted by the sixth transistor M 6  to the gate of the fifth transistor M 5 , and the potential at the node N 2  is at a high level, thus turning off the fifth transistor M 5  so that the fifth transistor M 5  will not contribute to any change in output; 
         [0027]    The first level signal which is a low-level signal is input to the first level signal terminal VGL, that is, the level of the signal is constant and lower than the second level signal described above, thus turning on the second transistor M 2 ; and 
         [0028]    The low-level signal transmitted by the first transistor M 1  is transmitted by the second transistor M 2  to the gate of the third transistor M 3 , and the potential at the node N 3  is at a low level, thus turning on the third transistor M 3 ; and since the fifth transistor M 5  will not contribute to any change in output, an output at the output terminal OUT is only the second clock signal, transmitted by the third transistor M 3 , connected to the second clock signal terminal, where the second clock signal opposite in phase to the first clock signal is at a high level at this time, that is, the output at the output terminal OUT is also at a high level thus resetting the entire shift. 
         [0029]    In the shift phase b: 
         [0030]    The first clock signal connected at the first clock signal terminal CK 1  is changed to a high level, thus turning off the first transistor M 1 , and at this time the potential at the node N 1  is kept at a low level in the reset phase a, and the sixth transistor M 6  is kept turned on, and since the signal at the gate of the second transistor M 2  is constantly at a low level, the second transistor M 2  and also the third transistor M 3  are kept turned on; and 
         [0031]    At this time the second clock signal is input to the second clock signal terminal CK 2  is changed to a low level, and the potential at the node N 3  will be pulled lower due to coupling by the circuit, and at this time the second transistor M 2  can suppress excessive leaked current of a parasitic capacitor to thereby achieve an effect of stabilizing the circuit. 
         [0032]    Also the high-level signal is still input to the second input signal terminal IN 2 , thus further turning off the fourth transistor M 4 , and the high-level signal, transmitted by the sixth transistor M 6 , input to the second level signal terminal is still input to the gate of the fifth transistor M 5 , thus turning off the fifth transistor M 5  so that the fifth transistor M 5  will not contribute to any output at the output terminal, but only the low-level signal which is input to the second clock signal terminal will be transmitted by the third transistor M 3  to the output terminal, and the shift function of the shift register has been embodied so far, that is, the low-level pulse signal at the input terminal is shift by one stage for output. 
         [0033]    Since the shift register according to this embodiment is typically used in a gate driver, it will be further provided with a hold function for a period of time in which the shift register needs to well hold a output at a high level in the turn-off phase c: 
         [0034]    The first clock signal is input to the first clock signal terminal CK 1  and is changed to a low level, thus turning on the first transistor M 1 ; 
         [0035]    The high-level signal is input to the first input signal terminal IN 1  and is transmitted by the first transistor M 1  to the gate of the sixth transistor M 6  and the source of the second transistor M 2 , and the potential at the node N 1  is at a high level, thus turning off the sixth transistor M 6 ; 
         [0036]    Since the signal at the gate of the second transistor M 2  is constantly at a low level, the second transistor M 2  is kept turned on to transmit the high-level signal, transmitted by the first transistor M 1 , to the gate of the third transistor M 3 , and the potential at the node N 3  is at a high level, thus turning off the third transistor M 3  so that the third transistor M 3  will not contribute to any output of the circuit; 
         [0037]    The second input signal is input to the second input signal terminal IN 2  and is changed to a low level, thus turning on the fourth transistor M 4 ; 
         [0038]    The low-level signal is transmitted by the fourth transistor M 4  to the gate of the fifth transistor M 5 , and since the sixth transistor M 6  is turned off, the potential at the node N 2  is at a low level, thus turning on the fifth transistor M 5 ; and 
         [0039]    The high-level signal is input to the second level signal terminal and is transmitted by the fifth transistor M 5  to the output terminal. 
         [0040]    As can be apparent, the shift register according to this embodiment of the invention can enable a correct operation of the circuit, and the second transistor M 2  can suppress excessive leaked current of a parasitic capacitor in the shift phase b to thereby have the gate thereof driven correctly; and furthermore the shift register according to this embodiment of the invention can dispense with a capacitor to thereby significantly lower the width of a drive area for a display device, i.e., a non-display area, which is a edge frame area. 
         [0041]    Moreover the shift register according to this embodiment of the invention comprises only six PMOS transistors, and since a p-channel transistor (PMOS) circuit alone can be fabricated in a process using two fewer masks than in a process of fabricating an n-channel transistor circuit (NMOS), the shift register according to this embodiment of the invention can be fabricated in a lower number of process steps and at a lower cost than a shift register comprising an NMOS transistor circuit. 
         [0042]    An embodiment of the invention further provides a group of shift registers comprising a number n of shift registers (n&gt;1 and n is an integer) connected to each other to have n stages. As illustrated in  FIG. 3 , the group of shift registers comprises a first-stage shift register P 1 , a second-stage shift register P 2 , a third-stage shift register P 3 , . . . , and an n-th shift register Pn connected to each other to have n stages. An output terminal OUT 1  of the first-stage shift register P 1  is connected to a first input signal terminal P 2 -IN 1  of the second-stage shift register P 2 , an output terminal OUT 2  of the second-stage shift register P 2  is connected to a second input signal terminal P 1 -IN 2  of the first-stage shift register P 1  and a first input signal terminal P 3 -IN 1  of the third-stage shift register P 3 , an output terminal OUT 3  of the third-stage shift register P 3  is connected to a second input signal terminal P 2 -IN 2  of the second-stage shift register P 2  and a first input signal terminal P 4 -IN 1  of the stage 4 shift register P 4  (not illustrated), . . . , a first input signal terminal Pn-IN 1  of the n-th shift register Pn is connected to an output terminal OUTn−1 of the (n−1)-th shift register (not illustrated), and a second input signal terminal Pn−1−IN 2  of the (n−1)-th shift register (not illustrated) is connected to an output terminal OUTn of the n-th shift register. 
         [0043]    First level signal terminals VGL of the respective stages of shift registers P 1 , P 2 , P 3 , . . . , Pn are connected in parallel, and second level signal terminals VGH of the respective stages of shift registers P 1 , P 2 , P 3 , . . . , Pn are connected in parallel. 
         [0044]    First clock signal terminals CK 1  of the odd-stage shift registers P 1 , P 3 , . . . , P 2   k− 1 (k is a positive integer) are connected to each other, second clock signal terminals CK 2  of the even-stage shift registers P 2 , P 4 , . . . , P 2   k  are connected to each other, and the first clock signal terminals CK 1  of the odd-stage shift registers P 1 , P 3 , . . . , P 2   k− 1 are connected to the second clock signal terminals CK 2  of the even-stage shift registers P 2 , P 4 , . . . , P 2   k.    
         [0045]    Second clock signal terminals CK 2  of the odd-stage shift registers P 1 , P 3 , . . . , P 2   k− 1 are connected to each other, first clock signal terminals CK 1  of the even-stage shift registers P 2 , P 4 , . . . , P 2   k  are connected to each other, and the clock signal terminals CK 2  of the odd-stage shift registers P 1 , P 3 , . . . , P 2   k− 1 are connected to the first clock signal terminals CK 1  of the even-stage shift registers P 2 , P 4 , . . . , P 2   k.    
         [0046]    Furthermore all of the first transistor M 1 , the second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 , the fifth transistor M 5  and the sixth transistor M 6  are PMOS transistors. 
         [0047]    Furthermore a first input signal terminal P 1 -IN 1  of the first-stage shift register P 1  is connected to an initial signal terminal STV, and a second input signal terminal Pn-IN 2  of the n-th shift register Pn is connected to a turn-off signal terminal END. 
         [0048]    An embodiment of the invention further provides a method of driving a group of shift registers, which can drive gates in a plurality of rows, and  FIG. 4  illustrates a timing diagram of its circuit in operation, which will be described below with reference to  FIG. 3  and  FIG. 4 . 
         [0049]    A first clock signal CK 1  is input to first clock signal terminals CK 1  of the odd-stage shift registers P 1 , P 3 , . . . , P 2   k− 1 (k is a positive integer) and second clock signal terminals CK 2  of the even-stage shift registers P 2 , P 4 , . . . , P 2   k,  a second clock signal CK 2  is input to second clock signal terminals CK 2  of the odd-stage shift registers P 1 , P 3 , . . . , P 2   k− 1 and first clock signal terminals CK 1  of the even-stage shift registers P 2 , P 4 , . . . , P 2   k,  a first level signal is input to first level signal terminals VGL, and a second level signal is input to second level signal terminals VGH. 
         [0050]    A signal at a first input signal terminal P 2 -IN 1  of the second-stage shift register P 2  is input to an output terminal OUT 1  of the first-stage shift register P 1  is connected to, signals at a second input signal terminal P 1 -IN 2  of the first-stage shift register P 1  and a first input signal terminal P 3 -IN 1  of the third-stage shift register P 3  are input to an output terminal OUT 2  of the second-stage shift register P 2 , signals at a second input signal terminal P 2 -IN 2  of the second-stage shift register P 2  and a first input signal terminal P 4 -IN 1  of the stage 4 shift register P 4  (not illustrated) are input to an output terminal OUT 3  of the third-stage shift register P 3 , . . . , a signal at an output terminal OUTn−1 of the (n−1)-th shift register is input to a first input signal terminal Pn-IN 1  of the n-th shift register Pn, and a signal at an output terminal of the n-th shift register is input to a second input signal terminal of the (n−1)-th shift register. 
         [0051]    Furthermore an initial signal is input to a first input signal terminal P 1 -IN 1  of the first-stage shift register P 1 , and a turn-off signal is input to a second input signal terminal Pn-IN 2  of the n-th shift register Pn is connected. 
         [0052]    Referring to  FIG. 4 , in a first half of a first cycle, a low-level signal at an initial signal terminal STV is input to the first input signal terminal P 1 -IN 1  of the first-stage shift register P 1 , and the first clock signal, the second clock signal, the first level signal and the second level signal are input respectively to the first clock signal terminal CK 1 , the second clock signal terminal CK 2 , the first signal level terminal VGL and the second level signal terminal VGH of the first-stage shift register P 1  at the same timing as the first clock signal, the second clock signal, the first level signal and the second level signal in the shift register described above. As can be apparent from the timing of the shift register described above in operation, the first-stage shift register P 1  is in the reset phase of its timing in operation, and the second clock signal at a high level is output at the output terminal OUT 1  thereof in the first half of the cycle for initialization. 
         [0053]    In a second half of the cycle, the initial level signal is changed to a high level, and the first-stage shift register P 1  is in the shift phase of its timing in operation, and as can be apparent from the timing of the shift register described above in operation, the second clock signal at a low level is output at the output terminal OUT 1  thereof in the second half of the cycle, thus shifting the initial signal at a low level backward by a half of the cycle. 
         [0054]    At this time the low-level signal at the output terminal OUT 1  of the first-stage shift register P 1  is input to the first input signal terminal P 2 -IN 1  of the second-stage shift register P 2 , the second clock signal at a low level is input to the first clock signal terminal CK 1  thereof, the second-stage shift register P 2  is in its reset phase, and a high-level signal is output at the output terminal P 2 -OUT. The high-level signal output at the output terminal P 2 -OUT of the second-stage shift register P 2  is transmitted to the second input signal terminal P 1 -IN 2  of the first-stage shift register P 1  to make the first-stage shift register P 1  enter the turn-off phase of a next cycle for to be further turned off. In a next cycle of the cycle, the second-stage shift register P 2  repeats its operation similar to that of the first-stage shift register P 1  so that a low level is output, thus turning on the third-stage shift register P 3 , and the second-stage shift register P 2  is turned off by the output terminal P 3 -OUT of the third-stage shift register P 3  after a delay of a half of the cycle. This process will be repeated so that the low-level signal output by the preceding stage of shift register is output by the next stage of shift register after being delayed by a half of the cycle to turn off the preceding stage of shift register. 
         [0055]    At the end of the operation by the last stage of shift register, e.g., the n-th shift register Pn, it will not be turned off by any next stage of shift register, so a turn-off signal is provided to delay the output of the n-th shift register Pn by a half of the cycle as denoted by END in the timing diagram. 
         [0056]    In the group of shift registers and method of driving the same according to the embodiments of the invention, the first clock signal is input to the first clock signal terminals of the odd-stage shift registers and the second clock signal terminals of the even-stage shift registers, and the second clock signal is input to the second clock signal terminals of the odd-stage shift registers and the first clock signal terminals of the even-stage shift registers, so that the function of driving row by row can be performed only using the two clock signals to thereby ensure a correct output of the circuit. 
         [0057]    The group of shift registers according to the embodiment of the invention can be embodied in the capacitor-free structure while ensuring a correct output to thereby further lower the area of the scan circuit and make the frame edge further narrowed; and moreover each shift register in the group of shift registers comprises only six PMOS transistors for which there are two less masks than the scan circuit comprising NMOS transistors to thereby simplify process steps thereof. 
         [0058]    It shall be noted that the foregoing embodiments can be referred to for and combined with each other. Although the invention has been disclosed as above in connection with the preferred embodiments thereof, they are not intended to limit the scope of the invention, and any those skilled in the art can make possible variations and modifications to the technical solution of the invention in light of the method and the disclosure above without departing from the spirit and scope of the invention, so any apparent modifications, equivalent changes and adaptations that can be made to the embodiments above in view of the technical essence of the invention without departing from the disclosure of the invention shall come into the scope of the technical solution of the invention.

Technology Category: g