Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention concerns a method and a system for compensating the non-linearity of a sigma-delta analog-to-digital converter. 
     2. Description of the Related Art 
     Equipment in all fields, electronic or otherwise, consumer or professional, increasingly employs digital rather than analog processing. This choice is often justified by technical advantages that are now well known, such as very stable parameters, excellent reproducibility of results, and increased functionality. 
     The external world being inherently analog, in most cases analog-to-digital converters (ADC) and digital-to-analog converters (DAC) provide at some level the interface between the external world and the digital core of the equipment. 
     The development of powerful digital processors has created a need for a high-resolution analog-to-digital converter compatible with CMOS VLSI (Very Large Scale Integration) technologies. The sigma-delta modulation converter in particular has exploited technological developments. 
     As shown in FIG. 1, a sigma-delta analog-to-digital converter primarily includes an adder  1 , a noise-shaping filter  4 , a quantizer  5 , a digital filter  6  and a feedback loop  8  connecting the output of the quantizer  5  to the negative input  3  of the adder  1 . The feedback loop  8  includes an analog-to-digital converter  7 . A sample-and-hold device (not shown), usually on the input side of the adder  1 , oversamples the signal at a given frequency and then maintains the level at the output  2  constant to enable the sigma-delta analog-to-digital converter to process the data. The noise-shaping filter  4  shapes the noise spectrum to attenuate the noise power in the frequency range of the wanted signal. The quantizer  5  employs a set of discrete levels and associates the closest discrete level with the analog value at its input. This introduces an error known as “quantizing noise”. The performance of a converter is conditioned by the quantizing noise power. To this end, the oversampling performed in the sample-and-hold device (not shown) and the feedback loop  8  “pushes” the maximum quantizing noise power out of the pass-band of the signal (the band of frequencies at which the system operates). The digital filter  6  at the output of the sigma-delta analog-to-digital converter, also known as a decimation filter, eliminates the shaped quantizing noise and undersamples the output signal. The digital-to-analog converter  7  has a transfer function that links the input (quantizing) digital levels delivered by the quantizer  5  to output analog values that are then fed to the negative input  3  of the adder  1 . The analog-to-digital converter  7  associates a corresponding analog output value with each quantizing input level. 
     The fundamental principle of the sigma-delta analog-to-digital converter consists firstly of oversampling the signal using the analog sample-and-hold device, pushing the quantizing noise power maximum outside the pass-band of the signal, by integrating the quantizer into a feedback loop, and then filtering the signal obtained by means of a digital filter  6 . These conjugate actions initially “dilute” the quantizing noise in a wide band thanks to the oversampling, shape the noise spectrum, and then filter the quantizing noise to retain only the wanted band of the signal. 
     Using a multibit quantizer associated with a multibit digital-to-analog converter in the feedback loop of a sigma-delta analog-to-digital converter is beneficial because it improves the signal/noise ratio and dynamic range of the sigma-delta analog-to-digital converter. 
     However, the performance of the sigma-delta analog-to-digital converter is highly dependent on the linearity of the sigma-delta analog-to-digital converter  7  used in the feedback loop  8 . 
     One prior art solution that has been proposed for calibrating the multibit digital-to-analog converter regardless of the number of levels is described by SARHANG-NEJAD and G. C. TEMES, “A High Resolution Multibit Sigma Delta ADC with Digital Correction and Relaxed Amplifier Requirements”, IEEE Journal of solid state circuits, vol. 28, N 6, June 1993, pages 648-660. It proposes to improve the performance of the sigma-delta analog-to-digital converter by measuring the non-linearities of the digital-to-analog converter  7  during a calibration phase. During the calibration phase, the multibit sigma-delta analog-to-digital converter is converted into a one-bit sigma-delta analog-to-digital converter (only the most significant bit at the output of the quantizer is considered). The calibration phase essentially employs the components shown in FIG. 2, which shows the adder  1 , the noise-shaping filter  4 , the quantizer  5  and the decimation filter  6 . The digital-to-analog converter  7  is replaced by switching means Ea for imposing at the negative input  3  of the adder  1  either a positive voltage Vref or a negative voltage −Vref, depending on the value of the output of the one-bit quantizer  5 . The digital-to-analog converter  7  is then placed at the positive input  2  of the adder  1 . A counter Eb controls the digital-to-analog converter  7  by feeding it a digital signal (corresponding to one of the levels available to the quantizer  5 ) so that it generates an analog signal at the input of the one-bit sigma-delta analog-to-digital converter. An adder Ec receiving the output signal of the counter Eb and the output signal of the decimation filter  6  calculates a correction value that is stored in a memory module Ed. The counter Eb also controls addressing of the memory module Ed. 
     Each correction value represents a digital error caused by the digital-to-analog converter  7  in converting between a digital value and its analog conversion. During the phase of normal use, the sigma-delta analog-to-digital converter is equivalent to that shown in FIG. 1 with a digital correction module (not shown) containing the correction values added in front of the decimation filter  6 . All digital values leaving the quantizer  5  are corrected by the digital correction module before reaching the decimation filter  6 . Thus the corrected digital value entering the decimation filter  6  is substantially equal to the analog value at the negative input  3  of the adder  1 . 
     The above technique has a number of drawbacks, associated with the manner in which the correction values are measured. In the calibration phase (FIG.  2 ), the output of the digital-to-analog converter  7  is fed to the positive input  2  of the adder  1 , whereas under normal operating conditions (FIG. 1 plus correction module) the digital-to-analog converter  7  is in the feedback loop  8  and its output is fed to the negative input  3  of the adder  1 . The behavior of the digital-to-analog converter  7  differs between the calibration phase and normal operating conditions because the two inputs of the adder  1  are different. The two inputs of the adder  1  do not have exactly the same capacitance, because it generally uses switched capacitors. 
     FIG. 3 shows an adder using switched capacitors. The switches  9 ,  10  and  12 ,  13  respectively switch a capacitor C 1  and a capacitor C 2  which are connected to a ground  14 . The adder has two inputs E 1  and E 2  respectively connected to the capacitors C 1  and C 2 . An operational amplifier  11  performs the addition operation by means of a feedback capacitor C. The capacitors C 1  and C 2  theoretically have the same capacitance. However, in practice, because of manufacturing tolerances, their capacitances are different and the gain between the two inputs is therefore different. 
     During the calibration phase, the digital-to-analog converter is therefore connected to the input E 1  and the values injected are measured accurately. During the normal operation phase, the digital-to-analog converter included in the feedback loop is connected to the input E 2  of the adder. Because the capacitors C 1  and C 2  are in practice different, the values measured during the calibration phase are therefore not in fact the values injected during the normal operation phase. Also, the accuracy of the measurement may be influenced by offset voltages inherent to the sigma-delta analog-to-digital converter. The offset voltages may not be a problem during the normal operation phase, but can become a problem during the calibration phase because it entails measuring DC voltages. 
     SUMMARY OF THE INVENTION 
     The invention aims to solve the above problem by retaining the structure of the sigma-delta analog-to-digital converter during the calibration phase and using only digital signals. 
     The invention proposes a method of compensating the non-linearity of a sigma-delta analog-to-digital converter with N quantizing levels and including a digital-to-analog converter in a feedback loop. N is an integer greater than two. The method includes a normal operation phase in which a plurality of digital values corresponding to a plurality of quantizing levels are modified by correction values Ci, where i is a positive integer from 1 to N, calculated during a calibration phase. According to a general feature of the invention, the correction values Ci are calculated from values of the output of the sigma-delta analog-to-digital converter processed digitally with the digital-to-analog converter retained in the feedback loop of the sigma-delta analog-to-digital converter and after converting the multibit sigma-delta analog-to-digital converter into a sigma-delta analog-to-digital converter with three quantizing levels, for example modifiable levels. The number N is a positive integer greater than 2. 
     The correction values C i  are used to correct errors caused by the digital-to-analog converter. The corrections are preferably made instantaneously during the normal operation phase. 
     The method in accordance with the invention of compensating non-linearity includes a calibration phase during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with three quantizing levels X m , X M  and X i , where i is from 1 to N−2; during a period P 1   i , a predetermined value is delivered to the input of the sigma-delta analog-to-digital converter and the values from the output of the sigma-delta analog-to-digital converter are processed digitally; this calibration phase is executed N−2 times, retaining the levels X m  and X M , and taking successively for the level X i  the N−2 levels other than the levels X m  and X M . The correction values Ci of the N−2 levels other than X m  and X M  are advantageously calculated using the processed values, the N−2 correction values C i  being adapted to modify the N−2 levels other than X m  and X M  during the normal operation phase. 
     The levels X m , X M  and X i  are digital values that are converted into analog values in accordance with a transfer function of the digital-to-analog converter. 
     The method can further include, during the calibration phase and before calculating the correction values Ci, at least one step F during which the multibit sigma-delta analog-to-digital converter is converted into a sigma-delta analog-to-digital converter with two quantizing levels X m  and X M . During a period P 2 , said predetermined value is delivered to the input of the sigma-delta analog-to-digital converter, and the successive values of the output of the sigma-delta analog-to-digital converter are processed digitally. In other words, step F advantageously eliminates any offset voltages in the sigma-delta analog-to-digital converter. 
     For example, if step F is performed only once, the periods P 1   i  can all be equal to one another and equal to the period P 2 . 
     The calibration phase presupposes that X i  is different from X m  and X M . 
     In accordance with the invention the sigma-delta analog-to-digital converter with N quantizing levels is converted into a sigma-delta analog-to-digital converter with a number of quantizing levels less than N by modifying quantizing threshold values and by digital processing using internal comparators. In the general case the sigma-delta analog-to-digital converter with N quantizing levels is converted into a sigma-delta analog-to-digital converter with three quantizing levels, and if the optional step F (offset voltage correction) is implemented, it is also converted into a sigma-delta analog-to-digital converter with two quantizing levels. 
     According to one advantageous feature of the invention, the levels X m  and X M  are respectively the minimum value and the maximum value of the N quantizing levels. 
     In one embodiment of the invention, during the normal operation phase, its correction value C i  is added to each level X i  present at the output of the quantizer. Thus the digital value after correction is substantially equal to the analog value at the output of the digital-to-analog converter. 
     In one advantageous variant of the invention, said predetermined value is equal to zero and, during the calibration phase, and during the period P 1   i  for each level X i , the number N i  of values equal to X I  and the total number NT i  of all the output values are counted at the output of the sigma-delta analog-to-digital converter and a sum S 1   i  of the NT i  values is calculated. The periods P 1   i , which are not all equal a priori, can depend on each intermediate level X i . In this case, step F of the calibration phase is executed N−2 times, each time taking a period P 2   i  equal to each period P 1   i , and a sum S 2   i  is calculated of all the values leaving the sigma-delta analog-to-digital converter during each execution, after which a correction value C i  corresponding to the value X i  is calculated from the equation (for i from 1 to N−2):          C   i     =         S2   i     -     S1   i         N   i                              
     The period P 1   i  for each level X i  is preferably equal to the period needed to count the number N i  of values equal to X i  at the output of the sigma-delta analog-to-digital converter (A 2 ) until the number N i  is equal to a given number N 0 . 
     If step F is executed only once (in which case all the periods P 1   i  are equal to each other and to P 2 ), there is only one sum S 2  and Ci can be calculated from the following equation (for i from 1 to N−2):          C   i     =       S2   -     S1   i         N   i                              
     There are various ways to calculate the correction values Ci. 
     The invention also proposes a system for compensating the non-linearity of a sigma-delta analog-to-digital converter with N quantizing levels including a digital-to-analog converter and a digital filter. According to a general feature of the invention, the system includes means for implementing the various phases previously described. 
     In a preferred embodiment, the calculating and modifying means include: 
     counter means for counting the values leaving the sigma-delta analog-to-digital converter, 
     at least one accumulator for summing the values leaving the sigma-delta analog-to-digital converter, 
     storage means for memorizing numbers delivered by the counting means and the accumulator, 
     processor means for performing calculations on the memorized numbers and generating control signals in the system for controlling the various phases, 
     a correction module between the quantizer and the digital filter and communicating with the processor means, and 
     comparators and a digital processor module internal to the N-level quantizer and capable of converting the quantizer into a quantizer with fewer than N quantizing levels. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other advantages and features of the invention will become apparent on examining the detailed description of one non-limiting embodiment and the accompanying drawings in which: 
     FIG. 1 depicts a prior art sigma-delta analog-to-digital converter. 
     FIG. 2 is a prior art depiction of components employed in a calibration phase of a sigma-delta analog-to-digital converter. 
     FIG. 3 depicts a prior art adder using switched capacitors. 
     FIG. 4 depicts a diagram of the general structure of a sigma-delta analog-to-digital converter implementing the invention. 
     FIG. 5 depicts a diagrammatic view of a three-level quantizer implementing the invention. 
     FIGS. 6 a  and  6   b  depict the results of converting a five-level quantizer into a three-level quantizer. 
    
    
     Although the invention is not limited to it, one example of the method and the system according to the invention for compensating the non-linearity of a sigma-delta analog-to-digital converter with three quantizing levels will now be described. 
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The FIG. 4 diagram is in three parts. A first part A 1  relates to the input signals, a second part A 2  relates to the sigma-delta analog-to-digital converter itself, and a third part A 3  relates to a control system. 
     The first part A 1  has a zero value input  15  used during a calibration phase and an input  16  receiving the analog signal to be digitized by the sigma-delta analog-to-digital converter. A switch  17  connects either to the input  15  or to the input  16 . 
     In the second part A 2 , a signal from the input  15  or  16  reaches the positive input  18   a  of an adder  19 . A noise-shaping filter  20  recovers the output signal of the adder  19 . The signal  21  leaving the noise-shaping filter  20  is fed to the input of a quantizer  22  with three quantizing levels: −1, 0 and 1. The quantizer  22  generates a digital signal  23  which, during a normal operation phase, is fed to the input of a corrector module  27  via a switch  26 . The output signal of the corrector module  27  is then passed through a digital filter  28  in order to undersample it. Undersampling reverts to a frequency in the vicinity of the Nyquist frequency. The digital signal  23  also passes through a feedback loop  25  including a digital-to-analog converter  24  whose output signal is fed to the negative input  18   b  of the adder  19 . 
     The third part A 3  is a control device including an accumulator  29 , a counter  30  and a second counter  31 , all three of which are connected to a random access memory module  32  connected to a digital processor module  33 . The digital processor module  33  performs calculations and generates data signals  35  that are sent to the corrector module  27  of the sigma-delta analog-to-digital converter and control signals  34  that are sent to the quantizer  22  and the switches  17  and  26 . 
     In normal operation, the digital-to-analog converter  24  receives three different digital values (for example in the form of pairs of bits  01 ,  00  and  10  coding the values −1, 0 and 1), and converts them into three analog values, which should ideally be −1, 0 and 1. 
     The three analog points do not usually correspond ideally to the values −1, 0 and 1. For example, the analog point leaving the digital-to-analog converter whose ideal value is 0 can be corrected. The correction of the 0 point is independent of the zero value at the input  15 . It is possible to correct the +1 and −1 points with the zero value still present at the input  15 . 
     During the first calibration phase the switch  17  is switched to the zero value input  15  and the switch  26  is switched to an input  36  common to the accumulator  29 , the counter  30  and the second counter  31 . The quantizer  22  operates in a three-level quantizing mode. The counter  31  then counts the number N 0  of 0 points (points to be corrected) contained in the digital signal  23  passing from the input  36  to the counter  31 . The count continues until the number N 0  reaches a predetermined value. To facilitate subsequent calculations the predetermined value is a power of two. It is equal to 2 18 , for example, i.e. to 262 144. 
     The accumulator  29  calculates the sum S 1  of the values of the output signal of the quantizer  22 . The sum S 1  is stored in the random access memory  32 , together with the number N 1  of points generated by the quantizer  22  and counted by the second counter  30 . The value 2 18  is chosen so that it is sufficiently large for the values stored in memory to be accurate. 
     The second calibration phase consists of converting the sigma-delta analog-to-digital converter with three quantizing levels into a sigma-delta analog-to-digital converter with two quantizing levels. For this it suffices to convert the three-level quantizer  22  into a two-level quantizer. The two levels are the −1 and +1 points. The switch  17  is still switched to the input  15  and the switch  26  is still switched to the input  36 . During this phase the sigma-delta analog-to-digital converter is operated with zero at the input during N 1  samples. The accumulator  29  also calculates the sum S 2  of the N 1  output samples. A zero point correction value is finally calculated from the equation: 
     
       
           C =( S   2 − S   1 )/ N   0   
       
     
     The division is simple to effect in the digital processor module  33  because a power of two has been chosen for the value of N 0 . The value C is then saved in the memory  32 , which has three compartments in which it saves the number N 1 , the sum S 1  and the value C. 
     Once these two calibration phases have been completed, the phase of normal operation of the sigma-delta analog-to-digital converter with three quantizing levels begins. The switch  17  is switched to the input  16 , the switch  26  is switched to the corrector module  27 , and the quantizer  22  operates with three quantizing levels −1, 0 and +1. The analog signal to be digitized is fed to the input  16  and leaves the quantizer  22  in the form of a digital signal  23  which is modified by the corrector module  27  and then digitally filtered by the module  28 . The corrector module  27  executes an algorithm that can be summarized as in the table below: 
     
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 input 
                 output 
               
               
                   
                   
               
             
             
               
                   
                  1 
                  1 
               
               
                   
                  0 
                 0 + C 
               
               
                   
                 −1 
                 −1 
               
               
                   
                   
               
             
          
         
       
     
     Thus if the digital value 0 is present at the output of the quantizer  22 , it is replaced by its correction value C at the output of the corrector module  27 . 
     FIG. 5 shows the three-level quantizer  22  made up of two comparators  37  and  38  and a digital processor module  39 . The comparator  37  has two inputs, a first of which receives the signal  21  from the noise-shaping filter  20  and the second of which is maintained at a fixed voltage V equal to a positive quantizing threshold voltage. The comparator  38  also has two inputs, the first of which also receives the signal  21 , and the second input of the comparator  32  is maintained at a voltage equal to −V. The output of the comparator  37  and that of the comparator  38  enter the digital processor module  39  generating the digital output signal  23 . If the value of the input signal  21  is greater than V, the digital signal  23  takes the value +1. If the value of the input signal  21  is less than −V, the signal  23  takes the value −1. If the value of the input signal  21  is between −V and V, the signal  23  is equivalent to 0. The digital processor module  39  is governed by the following algorithm, in which S 37  is the output of the comparator  37 , and S 38  is the output of the comparator  38 :          +   1     =     S   37             0   =           S   37     _     -     S   38          
     -   1     =       S   38     _                              
     To convert the three-level quantizer  22  into a two-level quantizer the values V and −V at the second inputs of the comparators  37  and  38  are replaced by a null value and the algorithm of the digital processor module  39  is modified so that, when the value of the input signal  21  is positive, the signal  23  is equivalent to +1 and, when the value of the input signal  21  is negative, the signal  23  is equivalent to −1. To this end, the algorithm of the digital processor module  39  is as follows:          +   1     =         S   37          
     -   1     =       S   37     _                              
     In fact, only the comparator  37  is used, the comparator  38  being rendered “invisible”. 
     The non-linearity of the sigma-delta analog-to-digital converter described above can be compensated by carrying out a calibration phase without modifying the structure of the sigma-delta analog-to-digital converter. 
     FIGS. 6 a  and  6   b  show the conversion of the five-level quantizer into a three-level quantizer. The E axis represents the input signal  7  and the S axis represents the output signal  9 . FIG. 6 a  shows the transfer function of a five-level quantizer (−1; −0.5; 0; 0.5; 1). For example, any input signal having a value between two positive values v 1  and v 2  delimiting a range of values on the E axis is converted into a digital signal of value equal to 0.5 on the S axis. To correct the zero level by converting the quantizer to three levels, the intermediate levels (−0.5 and 0.5) are eliminated, as shown in FIG. 5 b . The remaining three levels are therefore (−1; 0; 1). 
     For example, in a simulation for a signal to be converted of maximum amplitude and no correction in accordance with the invention, a sigma-delta analog-to-digital converter with three quantizing levels sampled at a frequency of 2 048 kHz had a signal/noise ratio of 46 dB. The results obtained after applying the first calibration phase with N 0 =262 144 were as follows: N 1 =372 522 and S 1 =−6 408. 
     Executing the second calibration phase yielded a sum S 2 =−3 116 and a 0 point correction value C such that: 
     
       
           C =( S   2 − S   1 )/ N   0 =3 292/262 144 
       
     
     A signal/noise ratio of 105 dB was then obtained in normal operation for a signal to be converted of maximum amplitude and with correction in accordance with the invention. 
     The method described above performs a calibration phase using a three-level quantizer and then a two-level quantizer but retains the general structure of the sigma-delta analog-to-digital converter. The calibration phase is effected simply by controlling the various switches.

Technology Category: h