Patent Document

CROSS REFERENCES TO RERATED APPLICATIONS  
       [0001]     The present invention contains subject matter related to Japanese Patent Application JP 2004-148078 filed in the Japanese Patent Office on May 18, 2004, the entire contents of which being incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to an image processing device used for a color image display used with fixed pixels and an image processing method used for the same.  
         [0004]     2. Description of the Related Art  
         [0005]     A color image display device used with fixed pixels such as a liquid crystal display or plasma display panel (PDP) has a plurality of unit areas which are provided in a matrix in a two-dimensional display region and in which pixels of red (R), green (G) and blue (B) (fixed pixels) are arranged continuously or with adjoining respectively.  
         [0006]     For example, each of the pixels of R, G and B is formed with a pixel region of a stripe or mosaic shape in the unit area.  
         [0007]     The color image display device makes the R pixel emit light on the basis of an R signal, the G pixel emit light on the basis of a G signal, and the B pixel emit light on the basis of a G signal. An emission of Light of the pixels of R, G and B placed in the unit area is visible as a color mixed them, so a designated color is displayed in the unit area.  
         [0008]     Note that, the R, G and B signals are generated so as to respectively make a center of the unit area as a reference.  
       SUMMARY OF THE INVENTION  
       [0009]     However, in the color image display device in related art, an arrangement position which the pixels of R, G and B are arranged in actual is not matched with the center of the unit area used for reference by the R, G and B signals, so that a gap corresponding to an interval of a stripe or mosaic occurs.  
         [0010]     The gap is visible as a color shift at a contour portion of the image and causes a deterioration of an image quality.  
         [0011]     The present invention is to provide an image processing device able to display an image in high quality by a color image display used with fixed pixels and an image processing method for the same.  
         [0012]     According to an embodiment of the present invention, there is provided a image processing device which makes pixels of R, G and B arranged inside each of a plurality of the unit areas on a screen emit light to display a designated color in unit areas, the image processing device including: a signal generation circuit determining a pixel of which an arrangement position is not matched with a reference position of the unit area used for a reference by a first pixel signal of the pixel as a target to be interpolated among pixels of the R, G and B, and generating a second pixel signal which uses the arrangement position of the pixel to be interpolated as a reference on the basis of the first pixel signal.  
         [0013]     According to an embodiment of the present invention, there is provided an image processing method driving a display device which makes pixels of R, G and B arranged inside each of a plurality of the unit areas on a screen emit light to display a designated color in unit areas, the image processing method including: a first step of determining a pixel of which an arrangement position is not matched with a reference position of the unit area used for reference by a first pixel signal of the pixel as a target to be interpolated among the pixels of R, G and B, and generating a second pixel signal which uses the arrangement position of the pixel to be interpolated as a reference on the basis of the first pixel signal; and a second step of driving an emission of light of the pixel corresponding to the second pixel signal on the basis of the second pixel signal generated in the first step.  
         [0014]     An embodiment of the present invention is able to be provided an image processing device able to display an image in high quality by a color image display using fixed pixels and an image processing method used for the same. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]     These features of embodiments of the present invention will be described in more detail with reference to the accompanying drawings, in which:  
         [0016]      FIG. 1  is a view of a whole configuration of a color image display device according to a first embodiment of the present invention;  
         [0017]      FIG. 2  is a view for illustrating the respective signals shown in  FIG. 1 ;  
         [0018]      FIG. 3  is a view for illustrating the respective signals shown in  FIG. 1 ;  
         [0019]      FIG. 4  is a view for illustrating the display device shown in  FIG. 1 ;  
         [0020]      FIG. 5  is a view of a configuration of an interpolation circuit shown in  FIG. 1 ;  
         [0021]      FIG. 6  is a view of a configuration of an interpolation module circuit shown in  FIG. 5 ;  
         [0022]      FIG. 7  is a view for illustrating an interpolation method by an R interpolation circuit shown in  FIG. 6 ;  
         [0023]      FIG. 8  is a view for illustrating a correction used by the R interpolation circuit shown in  FIG. 7 ;  
         [0024]      FIG. 9  is a view of a configuration of the R interpolation circuit shown in  FIG. 6 ;  
         [0025]      FIG. 10  is a view for illustrating an interpolation method by an R interpolation circuit shown in  FIG. 6 ;  
         [0026]      FIG. 11  is a view of a configuration of the B interpolation circuit shown in  FIG. 6 ;  
         [0027]      FIG. 12  is a view for illustrating a modification of the first embodiment of the present invention; and  
         [0028]      FIG. 13  is a view for illustrating a second embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0029]     Hereinafter, preferred embodiments of a color image display according to the present invention will be explained with reference to the drawings.  
       First Embodiment  
       [0030]      FIG. 1  is a view of a whole configuration of a color image display device  1  of the present embodiment.  
         [0031]     As shown in  FIG. 1 , the color image display device  1  has a display  10 , a video signal processing circuit  12 , an interpolation circuit  14  and a drive circuit  16 , for example.  
         [0032]     The color image display device  1  is set to a device used with fixed pixels, such as a liquid crystal display and PDP.  
         [0033]     (Display  10 )  
         [0034]     The display  10  is provided with, for example, rectangle unit areas in a matrix in a two-dimensional display region and arranged with R, G and B pixel regions inside each of the unit areas continuously or with adjoining respectively.  
         [0035]     For example, the R, G and B pixel regions are formed with a stripe or mosaic shape in the unit area.  
         [0036]     In the present embodiment, the R, G and B pixel regions in the unit area are arranged from the left in order of the R pixel, the G pixel and the B pixel toward the right in a horizontal direction of a screen as shown in  FIG. 1  and  FIG. 2C .  
         [0037]     (Video Signal Processing Circuit  12 )  
         [0038]     The video signal processing circuit  12  generates an R signal S_R, a G signal S_G and a B signal S_B on the basis of an video signal VIDEO which is input, and outputs them to the interpolation circuit  14 .  
         [0039]      FIGS. 2 and 3  are schematic views of the unit area and phases of the respective signals.  
         [0040]     In the present embodiment, the video signal VIDEO has a phase shown in  FIG. 2B   
         [0041]     The R signal S_R, the G signal S_G and the B signal S_B generated by the video signal processing circuit  12  have phases shown in  FIGS. 2E, 2D  and  2 F respectively.  
         [0042]      FIG. 4  is a schematic view of an example of the unit areas.  
         [0043]     The R signal S_R, the G signal S_G and the B signal S_B are generated by using a center O_UA of the unit area UA as a reference, not using centers O_R, O_G and O_B of each of the R, G and B pixel regions.  
         [0044]     Therefore, if the R signal S_R, the G signal S_G and the B signal S_B having the phases shown in  FIGS. 2E, 2D  and  2 F are output to the display  10  such as a color image display device in related art, the R, G and B pixel regions in the unit area UA may emit light on the basis of the R signal S_R, the G signal S_G and the B signal S_B and a so-called “phase shift” may occur.  
         [0045]     In the present embodiment, the video signal processing circuit  12  outputs the R signal S_R, the G signal S_G and the B signal S_B shown in  FIGS. 2E, 2D  and  2 F to the interpolation circuit  14 . Then the interpolation circuit  14  generates an R signal S_R 1 , a G signal S_G 1  and a B signal S_B 1  shown in  FIGS. 3C, 3B  and  3 D in accordance with an actual arrangement position of the R, G and B pixels in explanations blow.  
         [0046]     (Interpolation Circuit  14 )  
         [0047]      FIG. 5  is a view of a configuration of the interpolation circuit  14  shown in  FIG. 1 .  
         [0048]     As shown in  FIG. 5 , the interpolation circuit  14  has a memory  32  and an interpolation module circuit  34 .  
         [0049]     The memory  32  stores pixel data of the R signal S_R, the G signal S_G and the B signal S_B which are input from the video signal processing circuit  12 .  
         [0050]     The interpolation module circuit  34  performs an interpolation processing by using the R signal S_R and the B signal S_B generated by using the center O_UA of the unit area UA shown in  FIG. 4  as a reference to generate the R signal S_R 1  and the B signal S_B 1  which uses each of the center O_R of the R pixel region and the center O_B of the B pixel region as references respectively.  
         [0051]     In this time, the interpolation module circuit  34  receives a position determination of a horizontal direction and vertical direction in accordance with the centers O_UA, O_R and O_B, then performs the above interpolation processing on the basis of the position determination.  
         [0052]      FIG. 6  is a view of a configuration of the interpolation module circuit  34  shown in  FIG. 5 .  
         [0053]     As shown in  FIG. 6 , the interpolation module circuit  34  has an R interpolation circuit  42 , a G delay circuit  44  and a B interpolation circuit  46 , for example.  
         [0054]     The R interpolation circuit  42  generates the R signal S_R 1  which uses the center O_R of the R pixel region as a reference as shown in  FIG. 3C  on the basis of the R signal S_R which uses the center O_UA of the unit area as a reference.  
         [0055]     The G delay circuit  44  dose not perform the interpolation processing because the center O_UA of the unit area UA matches the center O_G, and is a FIFO (First-In First-Out) circuit delaying the G signal S_G for a processing time of the R interpolation circuit  42  and the B interpolation circuit  46  and then outputting it as the G signal S_G 1  shown in  FIG. 3B .  
         [0056]     The B interpolation circuit  46  generates the B signal S_B 1  which uses the center O_B of the B pixel region as a reference as shown in  FIG. 3D  on the basis of the B signal S_B which uses the center O_UA of the unit area UA as a reference.  
         [0057]      FIG. 7  is a view for illustrating an interpolation method by the R interpolation circuit  42 .  FIG. 8  is a view of an example of a correction of the pixel region.  
         [0058]     An example shown in  FIG. 7  shows a case generating an R pixel data of the R signal S_R 1  in the unit area UA 3 .  
         [0059]     Note that, in the present embodiment, an interval of the adjoining pixel regions in the horizontal direction is indicated by a “c” as shown in  FIG. 8 .  
         [0060]     Therefore, the right direction in the horizontal direction shown in  FIG. 8  is assumed as a plus, so the correction of the pixel data of the R signal S_R may be indicated by a “−c” and the correction of the pixel data of the B signal S_B may be indicated a “c”.  
         [0061]      FIG. 9  is a view of a configuration of the R interpolation circuit  42  shown in  FIGS. 6 and 7 .  
         [0062]     As shown in  FIG. 9 , the R interpolation circuit  42  has a correction operation circuit  62 , an interpolation coefficient calculation unit  64  and a matrix operation circuit  66 , for example.  
         [0063]     The correction operation circuit  62  calculates horizontal positions x 1 , x 2 , x 3  and x 4  of a reference pixel data shown in  FIG. 7  on the basis of a horizontal position x of the R pixel data to be interpolated and the correction “−c” by using the following formula (1), then outputs the calculated data to the interpolation coefficient calculation unit  64 .  
         [0064]     In this example, each of the horizontal positions x 1 , x 2 , x 3  and x 4  indicates a horizontal position of the center of the pixel in the respective unit areas UA 1 , UA 2 , UA 3  and UA 4  shown in  FIG. 7 .  
         [0065]     In the present embodiment, the R pixel data of the horizontal position x in the unit area UA 3  is generated by performing the interpolation processing on the basis of the R pixel data of the horizontal positions x 1 , x 2 , x 3  and x 4  in the unit areas UA 1 , UA 2 , UA 3  and UA 4  which are placed in the horizontal direction with respect to the unit area UA 3  shown in  FIG. 7 .  
                     x   1     =     1   +     (     x   -     [   x   ]       )                     x   2     =     (     x   -     [   x   ]       )                   x   3     =     1   -     (     x   -     [   x   ]       )                     x   4     =     2   -     (     x   -     [   x   ]       )                     (   1   )             
 
         [0066]     The interpolation coefficient calculation unit  64  operates the following formula (2) with respect to each of the horizontal positions x 1 , x 2 , x 3  and x 4  on the basis of data which is input from the correction operation circuit  62  to generate f(x 1 ), f(x 2 ), f(x 3 ) and f(x 4 ), then outputs the generated data to the matrix operation circuit  66 . Note that, in the following formula (2), a “x-c” is used as the “x”.  
               f   ⁢           ⁢     (   t   )       =         sin   ⁢           ⁢     (     π   ⁢           ⁢   t     )         π   ⁢           ⁢   t       ≅     {           1   -     2   ⁢          t        2       +          t        3             …   ⁢           ⁢     (     0   ≤        t        &lt;   1     )                 4   -     8   ⁢        t          +     5   ⁢          t        2       -          t        3             …   ⁢           ⁢     (     1   ≤        t        &lt;   2     )               0         …   ⁢           ⁢     (     2   ≤        t          )                         (   2   )             
 
         [0067]     The matrix operation circuit  66  performs a matrix operation shown in the following formula (3) on the basis of: f(x 1 ), f(x 2 ), f(x 3 ) and f(x 4 ) indicated by data which is input from the interpolation coefficient calculation unit  64 ; and the pixel data r 1 , r 2 , r 3  and r 4  of the R signal S_R in the horizontal positions x 1 , x 2 , x 3  and x 4 , which data is read out from the memory  32  to calculate a pixel data r to be interpolated of the horizontal position x. The pixel data is output to the drive circuit shown in  FIG. 1  as the pixel data of the R signal S_R 1 .  
             r   =       (       r   1     ⁢           ⁢     r   2     ⁢           ⁢     r   3     ⁢           ⁢     r   4       )     ⁢           ⁢     (           f   ⁢           ⁢     (     x   1     )                 f   ⁢           ⁢     (     x   2     )                 f   ⁢           ⁢     (     x   3     )                 f   ⁢           ⁢     (     x   4     )             )               (   3   )             
 
         [0068]      FIG. 10  is a view for illustrating an interpolation method by the B interpolation circuit  46 .  
         [0069]     An example shown in  FIG. 10  shows a case generating the B pixel data in the unit area UA 3  of the B signal S_B 1 .  
         [0070]      FIG. 11  is a view of a configuration of the B interpolation circuit  46  shown in  FIGS. 6 and 10 .  
         [0071]     As shown in  FIG. 11 , the B interpolation circuit  46  has a correction operation circuit  82 , an interpolation coefficient calculation unit  84  and a matrix operation circuit  86 , for example.  
         [0072]     The correction operation circuit  82  calculates horizontal positions x 1 , x 2 , x 3  and x 4  of a reference pixel data shown in  FIG. 10  by using the above formula (1) on the basis of a horizontal position x to be interpolated of the B pixel data shown in  FIG. 10  and the correction “c”, then outputs the calculated data to the interpolation coefficient calculation unit  84 .  
         [0073]     In this example, each of the horizontal positions x 1 , x 2 , x 3  and x 4  indicates a horizontal position of the B pixel data in each of the unit areas UA 2 , UA 3 , UA 4  and UA 5  shown in  FIG. 10 .  
         [0074]     In the present embodiment, the B pixel data of the horizontal position x in the unit area UA 3  is generated by performing the interpolation processing on the basis of the B pixel data of the horizontal position x 1 , x 2 , x 3  and x 4  in the unit areas UA 2 , UA 3 , UA 4  and UA 5  which are placed in the horizontal direction with respect to the unit area UA 3  shown in  FIG. 10 .  
         [0075]     The interpolation coefficient calculation unit  84  operates the above formula ( 2 ) with respect to each of the horizontal positions x 1 , x 2 , x 3  and x 4  on the basis of data which is input from the correction operation circuit  82  to generates f(x 1 ), f(x 2 ), f(x 3 ) and f(x 4 ), then outputs the generated data to the matrix operation circuit  86 . Note that, in the above formula (2), an “x+c” is used as the “x”.  
         [0076]     The matrix operation circuit  86  performs a matrix operation shown in the following formula (4) on the basis of f(x 1 ), f(x 2 ), f(x 3 ) and f(x 4 ) indicated by data which is input from the interpolation coefficient calculation unit  84  and the pixel data b 1 , b 2 , b 3  and b 4  of the B signal S_B in the horizontal positions x 1 , x 2 , x 3  and x 4  which data is read out from the memory  32  to calculate a pixel data b to be interpolated of the horizontal position x.  
         [0077]     The pixel data b is output as a pixel data of the B signal S_B 1  to the drive circuit  16 .  
             b   =       (       b   1     ⁢           ⁢     b   2     ⁢           ⁢     b   3     ⁢           ⁢     b   4       )     ⁢           ⁢     (           f   ⁢           ⁢     (     x   1     )                 f   ⁢           ⁢     (     x   2     )                 f   ⁢           ⁢     (     x   3     )                 f   ⁢           ⁢     (     x   4     )             )               (   4   )             
 
         [0078]     (Drive Circuit  16 )  
         [0079]     The drive circuit  16  makes each of the R, G, and B pixel regions in the display  10  emit light on the basis of the R signal S_R 1 , the G signal S_G 1  and the B signal S_B 1  shown in  FIGS. 3C, 3B  and  3 D which are input from the interpolation circuit  14 .  
         [0080]     Due to this, light emitting of the pixels of R, B and B in the unit area of the display  10  is visible as a color mixed them, so that a designated color can be displayed in the unit area.  
         [0081]     Next, an example of an operation of the color image display device  1  shown in  FIG. 1  will be described.  
         [0082]     First, the video signal processing circuit  12  generates the R signal S_R, the G signal S_G and the B signal S_B having the phases shown in  FIGS. 2D, 2E ,  2 F on the basis of the input video signal VIDEO having the phase shown in  FIG. 2B , then outputs them to the interpolation circuit  14 .  
         [0083]     Then, the interpolation circuit  14  generates the R signal S_R 1 , the G signal S_G 1  and the B signal S_B 1  shown in  FIGS. 3C, 3B  and  3 D in accordance with the actual arrangement position of the R, G and B pixels on the basis of the R signal S_R, the G signal S_G and the B signal S_B.  
         [0084]     Concretely, the interpolation circuit  14  generates the R signal S_R 1  and the B signal S_B 1  which use the center O_R of the R pixel region and the center O_B of the B pixel region as a reference respectively by the interpolation processing by using the R signal S_R and the B signal S_B generated by using the center O_UA of the unit area UA shown in  FIG. 4  as a reference.  
         [0085]     Further, the interpolation circuit  14  delays the G signal S_G which uses the center O_UA of the unit area UA as a reference by the above interpolation processing, and outputs them as the R signal S_G 1 .  
         [0086]     Then, the drive circuit  16  makes the R pixel region, the G pixel region and the B pixel region in the display  10  emit light on the basis of the R signal S_R 1 , the G signal S_G 1  and the B signal S_B 1  shown in  FIGS. 3C, 3B  and  3 D which are input from the interpolation circuit  14 .  
         [0087]     As mentioned above, the color image display device  1  generates the R signal S_R 1  which uses the center O_R of the R pixel region as a reference as shown in  FIG. 2E  and the B signal S_B 1  which uses the center O_B of the B pixel region as a reference as shown in  FIG. 3D  on the basis of the R signal S_R and the B signal S_B which use the center O_UA in the unit area UA shown in  FIG. 4  as a reference.  
         [0088]     Therefore, the positions which are indicated by the pixel data in the R signal S_R 1  and the B signal S_B 1  can be matched with the actual positions of the R pixel region and the B pixel region in the display  10 , a color shift corresponding to the interval of the pixel regions which occurred in related art can be suppressed, and the display  10  can display an image in high quality.  
         [0089]     Note that, the embodiment mentioned above is illustrated with the case that the R, G and B pixel regions are successively arranged in horizontal direction in the unit area UA. Furthermore, the present invention can be similarly applied with a case that the R, G and B pixel regions are successively arranged in the vertical direction in the unit area UA as shown in  FIG. 12 , for example.  
         [0090]     In this case, the vertical positions y 1 , y 2 , y 3  and y 4  (corresponding to the horizontal positions x 1 , x 2 , x 3  and x 4  in the first embodiment) of the reference pixel data are calculated by using a vertical position y instead of the horizontal position x of the R and B pixel data to be interpolated.  
       Second Embodiment  
       [0091]     The present embodiment is same as the first embodiment with the color image display device  1  except a part of the configuration of the interpolation circuit  14  shown in  FIG. 1  when the R pixel region, the G pixel region and the B pixel region are adjoining in the unit area UA in the display  10  as shown in  FIG. 13 , for example.  
         [0092]     Next, the interpolation circuit  14 a of the present embodiment will be described.  
         [0093]     In an example shown in  FIG. 13 , the entire centers O_R, O_B and O_B of the R, G and B pixel regions do not match the center O_UA of the unit area UA.  
         [0094]     The interpolation circuit  14   a  performs the interpolation processing on the basis of each of the R, G and B pixel data in 16 unit areas UA which are the sum of 4×4 (horizontal×vertical) including the unit area UA to generate each of the R, G and B pixel data in the unit area UA.  
         [0095]     Here, an interpolation of the R pixel data will be described.  
         [0096]     Note that, the interpolations of the G pixel data and the B pixel data are performed similarly to the R pixel data other than using another G pixel data and R pixel data respectively.  
         [0097]     The interpolation circuit  14   a  calculates the horizontal positions x 1 , x 2 , x 3  and x 4  of the reference pixel data by using the following formula (5) on the basis of the horizontal position x of the R pixel data to be interpolated.  
                     x   1     =     1   +     (     x   -     [   x   ]       )                     x   2     =     (     x   -     [   x   ]       )                   x   3     =     1   -     (     x   -     [   x   ]       )                     x   4     =     2   -     (     x   -     [   x   ]       )                     (   5   )             
 
         [0098]     Further, the interpolation circuit  14   a  calculates the vertical positions y 1 , y 2 , y 3  and y 4  of the reference pixel data by using the following formula (6) on the basis of the vertical position y of the R pixel data to be interpolated.  
                     y   1     =     1   +     (     y   -     [   y   ]       )                     y   2     =     (     y   -     [   y   ]       )                   y   3     =     1   -     (     y   -     [   y   ]       )                     y   4     =     2   -     (     y   -     [   y   ]       )                     (   6   )             
 
         [0099]     Then, the interpolation circuit  14   a  operates the following formula (7) with respect to each of the horizontal positions x 1 , x 2 , x 3  and x 4  and the vertical positions y 1 , y 2 , y 3  and y 4  to generate f(x 1 ), f(x 2 ), f(x 3 ), f(x 4 ), f(y 1 ), f(y 2 ), f(y 3 ) and f(y 4 ).  
               f   ⁢           ⁢     (   t   )       =         sin   ⁢           ⁢     (     π   ⁢           ⁢   t     )         π   ⁢           ⁢   t       ≅     {           1   -     2   ⁢          t        2       +          t        3             …   ⁢           ⁢     (     0   ≤        t        &lt;   1     )                 4   -     8   ⁢        t          +     5   ⁢          t        2       -          t        3             …   ⁢           ⁢     (     1   ≤        t        &lt;   2     )               0         …   ⁢           ⁢     (     2   ≤        t          )                         (   7   )             
 
         [0100]     Then, the interpolation circuit  14   a  performs a matrix operation shown in the following formula (8) on the basis of the generated f(x 1 ), f(x 2 ), f(x 3 ), f(x 4 ), f(y 1 ), f(y 2 ), f(y 3 ) and f(y 4 ) and R pixels data r 11 , r 12 , r 13 , r 14 , r 41 , r 42 , r 43 , r 44 , r 21 , r 22 , r 23 , r 24 , r 31 , r 32 , r 33  and r 34  in  16  unit areas UA which are the sum of 4×4 (horizontal×vertical) and read out from the memory to calculate pixel data r to be interpolated of the horizontal position x and the vertical position y.  
         [0101]     The pixel data r is output as a pixel data of the R signal S_R 1  to the drive circuit  16  shown in  FIG. 1 .  
             r   =       (     f   ⁢           ⁢     (     y   1     )     ⁢           ⁢   f   ⁢           ⁢     (     y   2     )     ⁢           ⁢   f   ⁢           ⁢     (     y   3     )     ⁢           ⁢   f   ⁢           ⁢     (     y   4     )       )     ⁢           ⁢     (           r   11           r   21           r   31           r   41               r   12           r   22           r   32           r   42               r   13           r   23           r   33           r   43               r   14           r   24           r   34           r   44           )     ⁢           ⁢     (           f   ⁢           ⁢     (     x   1     )                 f   ⁢           ⁢     (     x   2     )                 f   ⁢           ⁢     (     x   3     )                 f   ⁢           ⁢     (     x   4     )             )               (   8   )             
 
         [0102]     As mentioned above, according to the present embodiment, a color shift corresponding to the interval of the pixel regions can be suppressed even if the interpolation may be needed in the both horizontal direction and vertical direction in the entire R signal S_R, the G signal S_G and the B signal S_B, so that the display  10  can display an image in high quality.  
         [0103]     The present invention may not limit to the embodiments mentioned above.  
         [0104]     The present invention can be applied to the entire display device in which the pixel regions of R, G and B are arranged in the unit area.  
         [0105]     Further, the interpolation methods by the interpolation circuits  14  and  14   a  are not limited and various interpolation methods such as a linear interpolation, a high-order interpolation, that is, no less than two-order interpolation, a bicubic interpolation or a spline interpolation can be used.  
         [0106]     Furthermore, the interpolation circuits  14  and  14   a  may perform an interpolation on the basis of pixel data of the pixel in the unit areas other than around of the unit area which is belong to a pixel to be interpolated.  
         [0107]     The present invention is applied to an image processing device used to a color image display using fixed pixels.  
         [0108]     It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors in so far as they are within scope of the appeared claims or the equivalents thereof.

Technology Category: g