Patent Document

FIELD OF INVENTION  
       [0001]     The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device capable of reducing a write recovery time and increasing a self refresh period, and a driving method thereof.  
       DESCRIPTION OF PRIOR ART  
       [0002]     As a modern semiconductor memory device requires a low operational voltage for reducing power consumption, various techniques have been developed to improve an operation of a sense amplifier, of which one is to apply an overdriving scheme of the sense amplifier to the semiconductor memory device.  
         [0003]     Conventionally, a row address activates a predetermined word line connected to a plurality of memory cells arranged in a same row and then, a data stored in the memory cells are transferred to a bit line. A bit line sense amplifier senses a potential difference of a bit line pair and amplifies the data transferred to the bit line.  
         [0004]     During the above operation, since thousands of bit line sense amplifiers start operating simultaneously, an operational time of the bit line sense amplifier is determined according as current can be sufficiently supplied to drive the bit line sense amplifier. However, it is difficult to supply sufficient current at once because the modern semiconductor memory device requires a low operation voltage. To overcome the above problem, a high voltage is instantaneously supplied to a bit line sense amplifier (BLSA) power line RTO at an initial operation stage so that a voltage level of a normal voltage, i.e., an internal core voltage, is increased. This is so called the overdriving scheme of the bit line sense amplifier. Herein, the initial operation stage is referred to a moment soon after charges are shared with the memory cell and the bit line.  
         [0005]      FIG. 1  is a block diagram setting forth a conventional semiconductor memory device.  
         [0006]     Referring to  FIG. 1 , the conventional semiconductor memory device includes an internal signal generator  10 , a BLSA driving control signal generator  20 , a BLSA power line driver  30 , a BLSA array  40  and a memory cell array  50 . Herein, the BLSA array  40  provided with a plurality of bit line sense amplifiers that sense a potential difference of a bit line pair BL and BLB and amplifies the data transferred to the bit line. The BLSA power line driver  30  applies an operation voltage to BLSA power lines RTO and SZ. The internal signal generator  10  generates a predetermined enable signal SAEN by receiving external commands such as an active command ACT and a precharge command PCG. The BLSA driving control signal generator  20  is controlled by the internal signal generator  10  and generates control signals SP 1 B, SP 2 B and SN to control the BLSA power line driver  30 .  
         [0007]      FIG. 2  is a timing diagram setting forth an operational sequence of the conventional semiconductor memory device.  
         [0008]     To begin with, in case that the active command ACT is activated, data stored in the memory cell is applied to the bit line pair BL and BLB. The internal signal generator  10  activates the predetermined enable signal SAEN in response to the external commands ACT and PCG. The BLSA driving control signal generator  20  activates an overdriving control signal SP 1 B for a predetermined time in response to the predetermined enable signal SAEN so that an external voltage VEXT is applied to the BLSA power line RTO. Therefore, the data of the memory cell applied to the bit line pair BL and BLB is more rapidly sensed and amplified at the bit line sense amplifier.  
         [0009]     Thereafter, in case that a voltage level of the bit line pair BL and BLB becomes beyond a specific voltage level, the BLSA driving control signal generator  20  deactivates the overdriving control signal SP 1 B and simultaneously activates a normal driving control signal SP 2 B. Thus, a core voltage VCORE is applied to the BLSA power line RTO. Afterwards, though it is not shown in  FIG. 2 , a read or a write operation is performed sequentially. Then, when a precharge command PCG is activated, the internal signal generator  10  deactivates the predetermined enable signal SAEN and the BLSA driving control signal generator  20  deactivates the normal driving control signal SP 2 B in response to the deactivated predetermined enable signal SAEN.  
         [0010]     For reference, the BLSA driving control signal generator  20  activates a normal voltage driving signal SN for applying a ground voltage VSS to the BLSA power line SZ, in response to the predetermined enable signal SAEN.  
         [0011]     Meanwhile, according to the conventional semiconductor memory device, when the external voltage VEXT is unstable, the write recovery time in the memory cell becomes longer and further, it is required frequent refreshes due to degradation of a data-voltage level. For example, as the voltage level of the external voltage VEXT is lower and lower, the voltage level of the core voltage VCORE generated on the basis of the external voltage VEXT also becomes lower. Therefore, the voltage level of the BLSA power line RTO is reduced so that the data of the memory cell cannot help but be stored as a low voltage level. Accordingly, it is necessary to perform the frequent refresh operation for retention of the data.  
         [0012]     In addition, if a write command is applied, a data that will be written to the memory cell is over-written to the bit line that existing data of the memory cell has been applied thereto. Thus, as the external voltage VEXT becomes low, a write recovery time is elongated so that there is a limitation for device operation. Herein, the write recovery time refers to the time period that the writing data is over-written to the bit line pair and then, the voltage level of the bit line pair is inverted and amplified.  
         [0013]     The above problem, as aforementioned, is caused by the unstable voltage level of the external voltage VEXT or by a manufacturing process for a highly-integrated memory device. That is, as the semiconductor memory device is highly integrated nowadays, a size of a cell access transistor is reduced. Therefore, it is difficult to carry out a process for forming a plurality of contacts in the device. As a result, provided that the contacts are formed agley in the highly-integrated device, an operational range of the core voltage VCORE becomes low.  
         [0014]     As described above, the conventional semiconductor memory device has a disadvantage that if the operational range of the core voltage VCORE becomes low due to the low external voltage VEXT or the problem of the manufacturing process, the write recovery time is elongated to cause the limitation for the device operation. Furthermore, it is necessary to perform the frequent refresh operation after all in the conventional semiconductor memory device.  
       SUMMARY OF INVENTION  
       [0015]     It is, therefore, an object of the present invention to provide a semiconductor memory device capable of reducing a write recovery time and increasing a refresh period.  
         [0016]     It is, therefore, another object of the present invention to provide a driving method of a semiconductor memory device capable of reducing a write recovery time and increasing a refresh period.  
         [0017]     In accordance with an aspect of the present invention, there is provided a semiconductor memory device incorporating a plurality of memory cells therein, including: a bit line sense amplifier (BLSA) array provided with a plurality of bit line sense amplifiers for sensing and amplifying data of the memory cells applied to bit lines; and a BLSA driving control means for overdriving a bit line connected to the bit line sense amplifier in response to an active command, and for overdriving the bit line in response to a precharge command.  
         [0018]     In accordance with another aspect of the present invention, there is provided a driving method of a semiconductor memory device, including the steps of: a) driving a bit line for a first predetermined time with an overdriving voltage in response to an active command; b) driving the bit line with a normal voltage after the step a); and c) driving the bit line for a second predetermined time with the overdriving voltage in response to a precharge command. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0020]      FIG. 1  is a block diagram setting forth a conventional semiconductor memory device;  
         [0021]      FIG. 2  is a timing diagram explaining an operational sequence of the conventional semiconductor memory device;  
         [0022]      FIG. 3  is a block diagram illustrating a semiconductor memory device in accordance with a preferred embodiment of the present invention; and  
         [0023]      FIG. 4  is a circuit diagram representing a bit line sense amplifier (BLSA) driving control signal generator of the semiconductor memory device in accordance with the present invention;  
         [0024]      FIG. 5  is a circuit diagram depicting a BLSA power line driver of the semiconductor memory device in accordance with the present invention; and  
         [0025]      FIG. 6  is a timing diagram showing an operational sequence of the semiconductor memory device in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF INVENTION  
       [0026]     Hereinafter, a semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawing.  
         [0027]      FIG. 3  is a block diagram setting forth a semiconductor memory device in accordance with a preferred embodiment of the present invention.  
         [0028]     Referring to  FIG. 3 , the semiconductor memory device of the present invention includes a bit line sense amplifier (BLSA) driving controller  600 , a BLSA array  400  and a memory cell array  500 . Furthermore, the BLSA driving controller  600  is provided with an internal signal generator  100 , a BLSA driving control signal generator  200  and a BLSA power line driver  300 .  
         [0029]     Herein, the BLSA driving controller  600  is employed for overdriving a bit line connected to the bit line sense amplifier in response to an active command ACT, and for overdriving the bit line in response to a precharge command PCG. In detail, the BLSA array  400  incorporating therein a plurality of bit line sense amplifiers that sense a potential difference of a bit line pair BL, BLB and amplifies the data transferred to the bit line. The internal signal generator  100  generates a first enable signal SAEN and a second enable signal SAEN_PCG in response to an active command ACT and a precharge command PCG, wherein the first enable signal SAEN has an activation period corresponding to a row active time tRAS and the second enable signal SAEN_PCG has an activation period which is slightly shorter than the row active time tRAS by a predetermined time in comparison with the activation time of the first enable signal SAEN. The BLSA power line driver  300  is used for normally driving or overdriving the BLSA power line RTO. The BLSA driving control signal generator  200  generates a plurality of control signals SP 1 , SP 2 , SN to control the BLSA power line driver  300  in response to the first enable signal SAEN and the second enable signal SAEN_PCG.  
         [0030]      FIG. 4  is a circuit diagram setting forth the BLSA driving control signal generator  200  of the BLSA driving controller  600  in accordance with the preferred embodiment of the present invention.  
         [0031]     Referring to  FIG. 4 , the BLSA driving control signal generator  200  includes an overdriving control signal generator  220  and a normal driving control signal generator  240 . The overdriving control signal generator  220  activates an overdriving control signal SP 1  during a first predetermined time td 1  when the first enable signal SAEN is activated, and also activates the overdriving control signal SP 1  during a second predetermined time td 2  when the second enable signal SAEN_PCG is deactivated. The normal driving control signal generator  240  activates a normal driving control signal SP 2  when the first enable signal SAEN is activated and the overdriving control signal SP 1  is deactivated.  
         [0032]     Meanwhile, the overdriving control signal generator  220  is provided with an initial overdriving unit  222 , a terminal overdriving unit  224  and a NOR gate NR 1  for performing a logic NOR operation to the output signals of the initial overdriving unit  222  and the terminal overdriving unit  224 , in order to output the overdriving control signal SP 1 . Herein, the initial overdriving unit  222  has a first delay unit  222 A for delaying the second enable signal SAEN_PCG by the first predetermined time td 1 , a first inverter I 1  for inverting the output signal of the first delay unit  222 A, a first NAND gate ND 1  for performing a logic NAND operation to the second enable signal SAEN_PCG and the output signal of the first inverter I 1 , a second inverter I 2  for inverting the output signal of the first NAND gate ND 1 . Therefore, the initial overdriving unit  222  activates the overdriving control signal SP 1  for the first predetermined time td 1  when the second enable signal SAEN_PCG is activated.  
         [0033]     In addition, the terminal overdriving unit  224  has a third inverter I 3  for inverting the second enable signal SAEN_PCG, a second NAND gate ND 2  for performing a logic NAND operation to the output signal of the third inverter I 3  and the first enable signal SAEN, a fourth inverter I 4  for inverting the output signal of the second NAND gate ND 2 , a second delay unit  222 B for delaying the output signal of the fourth inverter I 4  by the second predetermined time td 2 , a third NAND gate ND 3  for performing a logic NAND operation to the output signals of the third and the fourth inverters I 3  and I 4 , and a sixth inverter I 6  for inverting the output signal of the third NAND gate ND 3 . Thus, the terminal overdriving unit  224  activates the overdriving control signal SP 1  for the second predetermined time td 2  when the second enable signal SAEN_PCG is deactivated and the first enable signal SAEN is activated.  
         [0034]     The normal driving control signal generator  240  is provided with a seventh and eighth inverters I 7  and I 8  for delaying the second enable signal SAEN_PCG, a ninth inverter I 9  for inverting the overdriving control signal SP 1 , a fourth NAND gate for performing a logic NAND operation to the output signals of the eighth and ninth inverters I 8  and I 9 , and a tenth inverter I 10  for outputting the normal driving control signal SP 2  by inverting the output signal of the fourth NAND gate ND 4 .  
         [0035]      FIG. 5  is a circuit diagram setting forth the BLSA power line driver  300  of the BLSA driving controller  600  in accordance with the preferred embodiment of the present invention.  
         [0036]     Referring to  FIG. 5 , the BLSA power line driver  300  includes a first PMOS transistor PM 1  for applying the core voltage VCORE to the BLSA power line RTO in response to the normal driving control signal SP 2 , a second PMOS transistor PM 2  for applying the external voltage VEXT to the BLSA power line RTO in response to the overdriving control signal SP 1 , a first NMOS transistor NM 1  for applying the ground voltage VSS to the BLSA power line SZ in response to the normal voltage driving signal SN, and a second NMOS transistor for rendering the BLSA power lines RTO and SZ be a same voltage level in response to an equalizing signal bleq. In general, the external voltage VEXT has a higher voltage level than the core voltage VCORE.  
         [0037]      FIG. 6  is a timing diagram setting forth an operational sequence of the semiconductor memory device in accordance with the preferred embodiment of the present invention.  
         [0038]     To begin with, when the active command ACT is activated, data stored in the memory cells are applied to the bit line pair BL, BLB. Then, the internal signal generator  100  activates the first enable signal SAEN and the second enable signal SAEN_PCG in response to the active command ACT. The BLSA driving control signal generator  200  activates the overdriving control signal SP 1  for the first predetermined time td 1  when the second enable signal SAEN_PCG is activated so that the external voltage VEXT is applied to the BLSA power line RTO. Therefore, the data applied to the bit line is rapidly sensed and amplified at the bit line sense amplifier.  
         [0039]     Afterwards, in case that a voltage level of the bit line pair BL and BLB becomes beyond a specific voltage level, the BLSA driving control signal generator  200  deactivates the overdriving control signal SP 1  and activates the normal driving control signal SP 2 . Thereafter, when the precharge command is activated, the internal signal generator  100  deactivates the second enable signal SAEN_PCG. In response to the activated second enable signal SAEN_PCG, the BLSA driving control signal generator  200  deactivates the normal driving control signal SP 2  and activates the overdriving control signal SP 1  for the second predetermined time td 2 . Accordingly, since the external voltage VEXT is applied to the bit line pair BL, BLB just before the word line is deactivated due to the precharge command PCG, the voltage level is rapidly increased to thereby store the data in the memory cell with high speed.  
         [0040]     Thereafter, the BLSA driving control signal generator  200  deactivates the first enable signal SAEN and deactivates the word line so that the data of the bit line pair is stored in the memory cell.  
         [0041]     As described above, the present invention provides an advantageous merit for reducing the write recovery time. In other words, the external voltage VEXT of which voltage level is higher than the core voltage VCORE is applied to the BLSA power line RTO just before performing a precharge operation even though the operational range of the core voltage VCORE becomes lowered because of the low external voltage level. Accordingly, it is possible to reduce the write recovery time. Furthermore, in comparison with the conventional semiconductor memory device, since the voltage level of the memory cell is relatively higher than the prior art, the self refresh period can be increased.  
         [0042]     The present application contains subject matter related to the Korean patent application No. KR 2004-31880, filled in the Korean Patent Office on May 6, 2004, the entire contents of which being incorporated herein by reference.  
         [0043]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Technology Category: 3