Patent Document

FIELD OF THE INVENTION 
     The present invention relates to the generation of periodic waveforms and, more particularly, to a clock phase generator which can generate a plurality of sub-clock phases in between the standard clock phases. 
     BACKGROUND OF THE INVENTION 
     For many analog and digital applications, it is necessary to generate clock signals which have well defined, known clock phases. Such applications include data and clock recovery circuits, data acquisition systems, pulse wave modulation generators and clock multipliers. 
     FIG. 1 illustrates a typical clock signal C 1  having a period P. A phase delay D can be introduced by delaying the clock by a time period of D (e.g., two nanoseconds) and outputting the delayed clock signal as a second clock output C 2 . 
     Thus, for example, if clock signal C 1  has a period P of 8 nanoseconds, then by introducing a two nanosecond delay D to each successive clock signal, four clock signals, C 1  through C 4 , can be utilized for control purposes, all generated based on the first clock signal C 1 . 
     Using prior art techniques, evenly spaced clock signals are generated with multi-phase clock generators and delay-locked loops (DLLs). U.S. Pat. No. 5,436,939 to Co et al., incorporated herein by reference, teaches one such multi-phase clock generator. Both multi-phase clock generators and DLLs use a series of delay elements to generate a plurality of output clock signals from “taps”; the phase delay D associated with a particular tap is referred to as a “tap delay.” Using these prior art schemes, the size of the tap delay is limited by the speed of the intrinsic delay of the delay cell plus the delay from the load the delay cell drives. For example, it is common to utilize a series of inverters in a voltage controlled oscillator (VCO) to implement the phase delay D; however, the smallest possible delay using state-of-the-art inverters is ∝200 pS. Thus, for example, across an 8 nanosecond (8000 pS) period, the maximum number of taps that could be available would be 40 (8000 pS÷200 pS=40). Therefore, conventional multi-phase clock generators and DLLs are not suitable for applications requiring tap delays that are smaller than the intrinsic delay of the delay cell. Further, conventional multi-phase clock generators and DLLs are unsuitable for applications requiring variable phase shifting clock signals, since they cannot output clock signals that have a variable phase delay. 
     Accordingly, there exists a need for a multi-phase clock generator which can produce a variable phase shifting clock signal with tap delays that are less than the intrinsic delay of conventional delay cells. 
     SUMMARY OF THE INVENTION 
     According to the present invention, the minimum and maximum delay values achievable by a standard multi-phase clock generator or DLL are determined to establish a range of potential delays of the clock generator, and then sub-taps or “virtual taps” are embedded within the delay range to enable smaller delays to be selected and added to the output clock signal from each tap. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a clock signal generated by a prior art clock generator; 
     FIG. 2 is a block diagram of a variable phase delay circuit in accordance with the present invention; 
     FIG. 3 illustrates an exemplary embodiment of a reference DAC in accordance with the present invention; 
     FIG. 4 illustrates an exemplary embodiment of a control DAC in accordance with the present invention; and 
     FIG. 5 illustrates the super position of sub-clock pulses on regular clock pulses in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 2 illustrates a variable phase delay circuit in accordance with the present invention. A standard PLL  10  generates a plurality of phase-shifted clock signals C 1 , C 2 , C 3 , and C 4  (in this example, four) out of taps T 1 , T 2 , T 3 , and T 4 , respectively, in a known manner. The PLL  10  generates these equally-spaced, fixed clock signals, each of which have a predetermined phase alignment with respect to the first clock signal output from tap T 1 . Two adjacent taps (T 1  and T 2  in this case) are output to a reference feedback loop  20  and some or all taps (T 1  through T 4  in this case) are output to phase control block  30 . 
     Reference loop  20  comprises a pair of conventional delay cells  22  and  24  (e.g., current-starved delay cells) coupled to receive clock outputs from taps T 1  and T 2 , respectively; a conventional phase comparator/filter  26 ; and a reference Digital-to-Analog Convertor (DAC)  28 . The purpose of reference loop  20  is to add an extra delay to the output of delay cell  22  so that the output of delay cell  22  is phase aligned to the output of delay cell  24 . The outputs of delay cell  22  and delay cell  24  are input to phase comparator  26 . In a known manner phase comparator  26  outputs a voltage V BIAS  corresponding to the difference in phase between the outputs of delay cells  22  and  24 . If this comparison indicates that the phase output from delay cell  24  leads the phase output from delay cell  22 , then V BIAS  is adjusted until the phases of each delay cell overlap (i.e., are phase aligned). If the output from delay cell  24  lags the output from delay cell  22 , the V BIAS  is adjusted in the opposite direction until the outputs of the two delay cells  22  and  24  are phase aligned. Thus, in the reference loop  20 , the phase differences between the output from delay cell  22  and the output from delay cell  24  are integrated with a negative feedback loop to keep their outputs phase aligned. 
     FIG. 3 illustrates one exemplary embodiment of reference DAC  28 . As shown in FIG. 3, reference DAC  28  comprises two similar DACs  28 A and  28 B. DAC  28 A comprises a series of nine diode-connected N-channel Field Effect Transistors (NFETs) MN 1  through MN 9  and eight control NFETs MN 10  through MN 17 . NFET MN 1  acts as a base diode or pedestal diode that is always “on” (i.e., always acting as a diode) and NFETs MN 2  through MN 9  are controlled by NFETS MN 10  through MN 17  to have their gates connected to V DD  so that they also remain “on” at all times. A P-channel field effect transistor (PFET) MP 1  produces a head current that can be increased or decreased to move the phase of the input from tap T 1 . Thus, the voltage V BIAS  coming into DAC  28 A is acted upon by all nine diode connected NFETs MN 1  through MN 9  and outputs a minimum voltage Vmin to delay cell  22 . Accordingly, in delay cell  22 , the maximum amount of delay is added to the output from T 1  and sent to phase comparator  26 , and therefore the output of delay cell  22  defines the slowest operation of the delay cells. 
     DAC  28 B operates similarly, but with less gain, to develop a maximum voltage, and therefore a minimum delay, with respect to the output from tap T 2 . Specifically, NFETs MN 18  through MN 34  are connected together identically to the connections of MN 1  through MN 17 ; however, the gates of control NFETs MN 27  through MN 34  are grounded and, therefore, NFETs M 27  through M 34  are always “off” (i.e., they operate to “remove” the diode-connected NFETs from the circuit). The DACs  28 A and  28 B are therefore different in that DAC  28 B creates a voltage bias based only on the effect of the pedestal diode MN 18  while DAC  28 A creates a bias voltage based on the combined effects of pedestal diode MN 1  and diodes MN 2  through MN 9 . Accordingly, DAC  28 B operates to provide the maximum amount of voltage to delay cell  24 . Thus, the minimum amount of delay (i.e., the intrinsic delay of delay cell  24 ) is added to the output of T 2  at delay cell  24 , and therefore the output of delay cell  24  defines the fastest operation of the delay cells. 
     Although FIGS. 2 and 3 illustrate reference DAC  28  as being formed as part of the integrated circuit, the reference voltages (or currents) supplied by reference DAC  28  can instead be supplied from an off-chip source. 
     The output voltage V BIAS  from phase comparator  26  is also output to a control loop  30  formed by a control DAC  31  and secondary delay cells  32 ,  34 ,  36 , and  38 . Control DAC  31  also receives user input in the form of control signals as described in more detail below with respect to FIG.  4 . Thus, control DAC  31  receives the same bias voltage V BIAS  from phase comparator  26  as that received by DAC  28 , as well as the user control inputs, and generates a control voltage V CONTROL  to each of the delay cells  32  through  38 . Delay cells  32  through  38  also receive the outputs from taps T 1  through T 4 , respectively, from PLL  20 . The control voltage V CONTROL  introduces an additional delay to the outputs from taps T 1  through T 4 , and those delayed clocks are output at subtaps ST 1  through ST 4  (corresponding to delay elements  32  through  38 , respectively) based on the delay needs of the user as identified by control voltage V CONTROL . 
     An exemplary embodiment of control DAC  31  is shown in detail in FIG.  4 . Control DAC  31  is identical to control DAC  28 A of control DAC  28 , with one exception. Instead of having the gates of control transistors MN 44  through MN 51  connected to V DD , control inputs CI 1  through CI 8  are provided which give the user of the system the ability to selectively turn on or off each of the control transistors MN 44  through MN 51  and therefore, control the operation of diode-connected transistors MN 36  through MN 43 . This allows the user to selectively control the voltage output from control DAC  31 . Thus, the user has up to eight (in this example) “sub-delays” SD 1  through SD 8  within the range defined by the outputs of taps T 1  and T 2 , each of which can be added to the outputs of tap T 1  through T 4  by outputting the desired control voltage V CONTROL  to delay cells  32 ,  34 ,  36  and  38 . Thus, the maximum delay available from the delay elements of the system can be increased to an even longer delay, in increments selected by the user. 
     FIG. 5 illustrates clock pulses C 1  and C 2  of FIG. 1, with eight sub-clocks SC 1  through SC 8  shown interposed between the clock pulses. Thus, for example, if a user supplied a digital  0  to any two of the control inputs of FIG. 4 (e.g., CI 1  and CI 2 ) and supplied digital  1 &#39;s to the remaining control inputs (e.g., CI 3  through CI 8 ), then six of the diode-connected transistors (MN 38  through MN 43 ) would be active and the remaining diode-connected transistors (MN  36  and MN 37 ) would be inactive, and the equivalent of two sub-delays would be added to each clock signal C 1  through C 4  (only C 1  and C 2  shown in FIG. 5) so that the outputs ST 1  and ST 2  of delay cells  32  and  34 , respectively would correspond to sub-clock signals SC 1-2  and SC 2-2 , respectively, of FIG.  5 . The outputs of delay cells  36  and  38  would also be delayed accordingly. 
     In this example, eight selectable sub-delays are illustrated; however, any number of sub-delays could be utilized depending upon the needs of the user. 
     By introducing this additional delay via the subtaps, a user can specify any desired clock phase, limited only by the number of subtaps utilized, and the change can be implemental at any time, i.e., the phase is variable. 
     While there has been described herein the principles of the invention, it is to be understood by those skilled in the art that this description is made only by way of example and not as a limitation to the scope of the invention. For example, while the disclosure makes specific reference to utilization of a maximum voltage V MAX  and a minimum voltage V MIN , one of ordinary skill in the art would recognize that simple conversions will allow the use of a maximum current C MAX  and a minimum current C MIN  to accomplish the same result. Accordingly, it is intended by the appending claims, to cover all modifications of the invention which fall within the true spirit and scope of the invention.

Technology Category: h