Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is related to co-pending application docket numbers YOR920090398US1, YOR920090399US1, YOR920090411US1, YOR920090414US1, YOR920090506US1, all of which are incorporated by reference herein. 
       FIELD OF INVENTION 
       [0002]    The present invention relates to semiconductor nanowire field effect transistors. 
       DESCRIPTION OF RELATED ART 
       [0003]    A nanowire field effect transistor (FET) includes doped portions of nanowire that contact the channel region and serve as source and drain regions of the device. Previous fabrication methods that used ion-implantation to dope the small diameter nanowire may result in undesirable amorphization of the nanowire or an undesirable junction doping profile. 
       BRIEF SUMMARY 
       [0004]    In one aspect of the present invention, a method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, forming a conductive material on the source and drain regions, and forming an isolation region around the device. 
         [0005]    In another aspect of the present invention, a method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure, forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, doping the exposed portions of the nanowire to form source and drain regions, forming a silicide material in the source and drain regions of the exposed portions of the nanowire, forming a conductive material on the source and drain regions, and forming an isolation region around the device. 
         [0006]    In yet another aspect of the present invention, a nanowire field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate structure disposed circumferentially around the silicon portion, a polysilicon capping layer having a silicide portion disposed on the gate structure, a source region having a silicide portion, the source region including a first doped epi-silicon nanowire extension contacting the first distal end of the silicon portion, a drain region having a silicide portion, the drain region including a second doped epi-silicon nanowire extension contacting the second distal end of the silicon portion, a first conductive member contacting the silicide portion of the polysilicon capping layer, a second conductive member contacting the silicide portion of the source region, and a third conductive member contacting the silicide portion of the drain region. 
         [0007]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0008]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0009]      FIGS. 1-7D  are cross-sectional views illustrating exemplary methods for forming contacts for field effect transistor (FET) devices. 
           [0010]      FIG. 8  is a top-down view of the devices of  FIG. 7A . 
       
    
    
     DETAILED DESCRIPTION 
       [0011]      FIG. 1  illustrates a cross-sectional view of a plurality of FET devices. A silicon on insulator (SOI) pad region  106 , pad region  108 , and nanowire portion  109  are defined on a buried oxide (BOX) layer  104  that is disposed on a silicon substrate  100 . The pad region  106 , pad region  108 , and nanowire portion  109  may be patterned by the use of lithography followed by an etching process such as, for example, reactive ion etching (RIE). Once the pad region  106 , pad region  108 , and nanowire portion  109  are patterned, an isotropic etching process suspends the nanowires  109  above the BOX layer  104 . Following the isotropic etching, the nanowire portions  109  may be smoothed to form elliptical shaped (and in some cases, cylindrical shaped) nanowires  109  that are suspended above the BOX layer  104  by the pad region  106  and the pad region  108 . An oxidation process may be performed to reduce the diameter of the nanowires  109  to desired dimensions. 
         [0012]    Once the nanowires  109  are formed, gates  103  are formed around the nanowires  109 , as described in further detail below, and capped with a polysilicon layer  102 . A hardmask layer  107 , such as, for example silicon nitride (Si 3 N 4 ) is deposited over the polysilicon layer  102 . The polysilicon layer  102  and the hardmask layer  107  may be formed by depositing polysilicon material over the BOX layer  104  and the SOI portions, depositing the hardmask material over the polysilicon material, and etching by reactive ion etching (RIE) to form the polysilicon layer (capping layer)  102  and the hardmask layer  107  illustrated in  FIG. 1 . The etching of the gates  103  may be performed by directional etching that results in straight sidewalls of the gates  103 . Following the directional etching, polysilicon  102  remains under the nanowires  109  and in regions not masked by the hardmask  107 . Isotropic etching may be performed to remove polysilicon  102  from under the nanowires  109 . 
         [0013]    The fabrication of the arrangement shown in  FIG. 1  may be performed using similar methods as described above for the fabrication of a single row of gates. The methods described herein may be used to form any number of devices on a nanowire between pad regions  106  and  108 . 
         [0014]    The gate  103  is formed by depositing a first gate dielectric layer  120 , such as silicon dioxide (SiO 2 ) around the nanowire  109 . A second gate dielectric layer  122  such as, for example, hafnium oxide (HfO 2 ) is formed around the first gate dielectric layer  120 . A metal layer  124  such as, for example, tantalum nitride (TaN) is formed around the second gate dielectric layer  122 . The metal layer  124  is surrounded by polysilicon layer  102 . Doping the polysilicon layer  102  with impurities such as boron (p-type), or phosphorus (n-type) makes the polysilicon layer  102  conductive. 
         [0015]    A first set of spacers  110  are formed along opposing sides of the polysilicon layer  102 . The spacers  110  are formed by depositing a blanket dielectric film such as silicon nitride and etching the dielectric film from all horizontal surfaces by RIE. The spacers  110  are formed around portions of the nanowire  109  that extend from the polysilicon layer  102  and surround portions of the nanowires  109 . 
         [0016]      FIG. 2A  illustrates the resultant structure after a selective RIE process is performed to remove exposed portions of the nanowires  109  and the pad regions  106  and  108  (shown in  FIG. 1 ). An example of a selective RIE process includes an RIE based on HBr chemistry that etches silicon while being selective to reduce the etching of dielectrics such as silicon oxide and silicon nitride. The portions of the nanowire  108  that are surrounded by the spacers  110  are not etched, and have exposed cross sections defined by the spacers  110 . 
         [0017]      FIG. 2B  illustrates a second set of spacers  210  that may be formed adjacent to the first set of spacers  110 . The second set of spacers may include, for example, a nitride or an oxide material. Once the spacers  210  are formed, a selective RIE process is performed similar to the RIE process described above in  FIG. 2A . 
         [0018]      FIGS. 3A and 3B  illustrates cross-sectional views of the resultant structures following a selective epi-silicon growth that may be performed to form nanowire extensions  302 . The nanowire extensions  302  are epitaxially grown from the exposed cross-sectional portions of the nanowire  109  that are surrounded by the spacer walls  110  (in  FIG. 3A) and 210  (in  FIG. 3B ). The nanowire extensions  302  are formed by epitaxially growing, for example, in-situ doped silicon (Si) or a silicon germanium (SiGe) that may be either n-type or p-type doped. The in-situ doped epi process forms the source region and the drain region of the nanowire FET. As an example, a chemical vapor deposition (CVD) reactor may be used to perform the epitaxial growth. Precursors for silicon epitaxy include SiCl 4 , SiH 4  combined with HCl. The use of chlorine allows selective deposition of silicon only on exposed silicon surfaces. A precursor for SiGe may be GeH 4 , which may obtain deposition selectivity without HCl. Precursors for dopants may include PH 3  or AsH 3  for n-type doping and B 2 H 6  for p-type doping. Deposition temperatures may range from 550° C. to 1000° C. for pure silicon deposition, and as low as 300° C. for pure Ge deposition. 
         [0019]      FIGS. 4A and 4B  illustrate an exemplary resultant structure following silicidation where a silicide  402  is formed on the nanowire extensions  302  (of  FIGS. 3A and 3B ). Examples of silicide forming metals include Ni, Pt, Co, and alloys such as NiPt. When Ni is used the NiSi phase is formed due to its low resistivity. For example, formation temperatures include 400-600° C. 
         [0020]      FIGS. 4C and 4D  illustrate alternate examples of resultant structures that do not include the nanowire extensions  302 . In  FIGS. 4C and 4D , the exposed cross-sectional portions of the nanowire  109  may be doped with ions to form source and drain regions by, for example, a low energy plasma doping or low energy ion implantation followed by an annealing process. A silicide  404  is formed on the exposed cross-sectional portions of the nanowire  109  that are surrounded by the spacer walls  110  (in  FIG. 3A) and 210  (in  FIG. 3B ). 
         [0021]      FIG. 5  illustrates an example of the resultant structure following the removal of the hardmask  107  and the deposition of contact material  502  such as, for example, W, Cu, Ag, or Al on the BOX layer  104 . A silicide  504  is formed on the polysilicon  102 . The resultant structure may be formed by, for example, depositing a layer of the contact material  502  on the BOX layer  104  and the hardmasks  107 . A portion of the contact material  502  and the hardmasks  107  may be removed by, for example, a chemical mechanical polishing (CMP) process. Once the polysilicon  102  is exposed by the CMP process, the silicide  504  may be formed on the polysilicon  102 . Alternatively, the hardmasks  107  may be removed by, for example, a CMP or etching process, and the silicide  504  may be formed on the exposed polysilicon  102 . A layer of the contact material  502  may be formed on the BOX layer  104 , the spacers  110 , and the silicide  504 . Once the layer of contact material  502  is formed, a CMP process may be performed so as to result in the illustrated structure. 
         [0022]      FIG. 6  illustrates a second layer of contact material  601  that is formed on the contact material  502 , and a mask layer  602  that may be disposed by a lithographic process on the contact material  601 . The mask layer  602  defines the contacts for the source (S), drain (D), and gate (G) regions of the devices. 
         [0023]      FIG. 7A  illustrates the resultant FET structure following etching portions of the contact material  601 , and the removal of the mask layer  602  (of  FIG. 6 ). 
         [0024]      FIGS. 7B-7D  illustrate the resultant FET structures of the embodiments described in  FIGS. 4B-4D  respectively above following the formation of silicide  504  in the polysilicon  102  and deposition and etching to form resultant structure of the contact material  601  using similar methods as described above in  FIGS. 5-6 . 
         [0025]      FIG. 8  illustrates a top view of the resultant structure of the illustrated embodiment of  FIG. 7A  following the isolation of the devices with a material  802  such as, for example, an oxide or nitride dielectric material. Following the formation of the contact material  601 , a mask layer is patterned on the devices to define a trench area around the devices. An etching process is used to remove contact material  601  and  502  from the trench area. The trench area is filled with the material  802  as illustrated in  FIG. 8  to form an isolation region. A similar method may be performed to form the material  802  around the devices in the illustrated embodiments of  FIGS. 7B-7D . 
         [0026]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0027]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 
         [0028]    The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0029]    While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Technology Category: 5