Patent Document

BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    Embodiments of the invention relate generally to circuitry and methods for determining the voltage and/or current of transmitters of a device under test through channel de-embedding. 
         [0003]    2. Background Art 
         [0004]    A common communication model consists of a transmitter, channel and receiver. In many cases a received signal is measured in a time domain and voltage of the transmitter signal is estimated. For example the PCI Express® Base Specification Revision 2.0 (PCI-E Gen2), Dec. 20, 2006, chapter 4.3.3.6, page 250, discusses transmitter measurements as follows: 
         [0005]    “When measuring a Transmitter, it is not usually feasible to place the probes directly at the Transmitter&#39;s pins, so it is typical to have PCB traces and other structures between the Tx package and the probe location. If direct measurement cannot be made at the Tx pins, then it will be necessary to deconvolve the effects compliance test board from the measurement.” 
         [0006]    A common practice today is measuring the signal from a transmitter at a printed circuit board (PCB) trace. An oscilloscope has been used in connection with a device under test (DUT) tester to measure the time domain signal at the PCB trace. The trace may distort the signal and give an incorrect view of the DUT transmitter output voltage and/or current. The problem will increase with introduction of 5 GHz and 10 GHz interconnects such as PCI-E Gen2 and IEEE 802.3 10 GBASE-KR. A network analyzer has been used to characterize the PCB trace. The trace may be characterized in units referred to as s-parameters, which are frequency parameters of an electro-magnetic wave. De-embedding techniques have been used to correct for the time domain signal distortion and have involved converting s-parameters to ABCD parameters. Heretofore, the de-embedding techniques have occurred in frequency domain. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The invention will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the invention which, however, should not be taken to limit the invention to the specific embodiments described, but are for explanation and understanding only. 
           [0008]      FIG. 1  is a block diagram representation of a system including a DUT on a circuit board coupled to a tester according to some embodiments of the invention. 
           [0009]      FIG. 2  is a block diagram representation of some implementations of the tester of  FIG. 1 . 
           [0010]      FIG. 3  is a block diagram representation of differential channels between the transmitter and tester of  FIG. 1  according to some embodiments of the invention. 
           [0011]      FIG. 4  is a block diagram representation of a signal ended channel between a transmitter and tester similar to or the same as those used in  FIG. 1  according to some embodiments. 
           [0012]      FIG. 5  shows an equation including prior art two port ABCD parameters for use in some embodiments of the invention. 
           [0013]      FIG. 6  shows an equation including prior art four port ABCD parameters for use in some embodiments of the invention. 
           [0014]      FIG. 7  illustrates representations of a two port circuit for a signal ended channel for S-parameter and ABCD parameters that may be used in connection with some embodiments of the invention. 
           [0015]      FIG. 8  illustrates representations of a four port circuit for a differential channel for S-parameter and ABCD parameters that may be used in connection with some embodiments of the invention. 
           [0016]      FIG. 9  shows an equation that may be used in calculating a DUT voltage according to some embodiments of the invention. 
           [0017]      FIG. 10  is a representation of a source matrix that may be used in connection with some embodiments of the invention. 
           [0018]      FIG. 11  is a representation of a load matrix that may be used in connection with some embodiments of the invention. 
           [0019]      FIG. 12  is a system similar to that of  FIG. 1  that shows additional channels according to some embodiments of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Referring to  FIG. 1 , a system includes a DUT  10  supported by a circuit board  16 , which may be a PCB. DUT  10  includes a transmitter (TX)  12  that provides a differential signal with D+ and D− signal components to channels  18  and  20 . The transmitter can also be called the source. The differential signal may be referred to as either the transmitter output signal or the channel input signal. The D+ signal component has voltage V 1  and current I 1 , and the D− signal component has voltage V 2  and current I 2 . In  FIG. 1 , channels  18  and  20  include traces in circuit board  16  coupled to connectors  34  and  36 , such as, for example, prior art SMA (SubMiniature version A) connectors. The traces in circuit board  16  include conductors  22  and  24  of channel  18  and conductors  26  and  28  of channel  20 . Some embodiments include coupling capacitors C 1  and C 2 . 
         [0021]    Conductors  38  and  40  couple connectors  34  and  36  to tester  46 . As examples, tester  46  may include an oscilloscope and/or logic analyzer. Conductor  38  carries a signal having a voltage V 3  and a current I 3 , and conductor  40  carries a signal having a voltage V 4  and a current I 4 . The magnitudes of currents I 3  and I 4  may be the same as the magnitudes of I 1  and I 2 . In some embodiments, tester  46  includes a receiver (RX)  50  that receives the signals on conductors  38  and  40  and provides received versions of them to de-embedding logic  52 . In some embodiments, RX  50  is an oscilloscope. In other embodiments, RX  50  is something else or is not included at all. The signals provided by RX  50  have voltages V 3 * and V 4 *, and current I 3 * and I 4 *, which are ideally the same as voltages V 3  and V 4 , and currents I 3  and I 4 . In some embodiments, RX  50  is designed such that voltages V 3 * and V 4 * are the same V 3  and V 4 , but currents I 3 * and I 4 * are not necessarily the same as currents I 3  and I 4 . The signals received by either RX  50  or de-embedding logic  52  may be considered tester input signals. 
         [0022]    In some embodiments, de-embedding logic  52  is hardware circuitry, and in other embodiments, it includes a processor, such as a digital signal processor (DPS), microprocessor, or embedded processor, or a combination of hardware and a processor. In some embodiments, de-embedding logic  52  provides differential signals having de-embedded voltages V 1 * and V 2 * which are ideally the same as originally transmitted voltages V 1  and V 2 . Analysis logic  54  receives the signals having voltages V 1 * and V 2 * and draws conclusions about DUT  10 , such as whether it is operating properly. In some embodiments or modes, the signals provided by de-embedding logic  52  have currents I 1 * and I 2 *. In some embodiments or modes, I 1 * and I 2 * are ideally the same as currents I 1  and I 2 , but in other embodiments or modes, that is not the case. 
         [0023]      FIG. 2  illustrates portions of some embodiments of tester  46 , but other embodiments of tester  46  do not include some of these details. Referring to  FIG. 2 , interface circuitry  62  receives signals on conductors  38  and  40  that having voltages V 3  and V 4  and provides signals representative thereof to processor  66 . For example, interface circuitry  62  may include analog-to-digital converters to provide digital signals to processor  66 . Processor  66  performs instructions that are stored on memory  68 . Memory  68  may be flash memory, dynamic random access memory (DRAM), a hard-drive, or some other sort of memory. In some embodiments, memory  68  is also used to store data. In some embodiments, processor  66  performs some or all the functions of both de-embedding logic  52  and analysis logic  54 . A display and/or other output circuitry may be used to provide conclusions of the analysis. 
         [0024]      FIG. 3  illustrates a more schematic version of the structure of  FIG. 1 . In the case of  FIG. 3 , V 1  and V 2  are the transmitter output signals to be estimated, and V 3  and V 4  are the channel output signals measured by the tester. 
         [0025]      FIG. 4  is similar to  FIGS. 1 and 3 , but includes a single ended TX  80 , channel  82 , and tester  86 . Some testers have both single ended and differential capability. In the case of  FIG. 4 , V 1  is the transmitter output signal to be estimated and V 2  is the channel output signal measured by the tester. 
         [0026]    In some embodiments, there are capacitors between the channel and the tester, but that is not the case in other embodiments. 
         [0027]    In the illustrated example, the channel input is the output of TX  12  or TX  80  and the channel output is the input of tester  46  (ignoring connectors  34  and  46 ). In some embodiments, an inventive algorithm described below uses measurements performed after the PCB traces to derive signals at the transmitter outputs. More generally speaking, in some embodiments, the algorithm uses time domain measurements at the channel output to derive the time domain signal at the channel input. The algorithm may significantly reduce the number of incorrect component failures. 
         [0028]    S-parameters and ABCD parameters are well known and described in the prior art literature. Two port ABCD parameters are represented in matrices as shown in  FIG. 5 . Four port ABCD parameters are represented in matrices as shown in  FIG. 6 . The four port ABCD matrix is called T in this disclosure. 
         [0029]      FIG. 7  is a generalized representation of s-parameters  88  of a two port (single ended) channel between signal conductor ends  92  and  96  with incident waves a 1  and a 2  and reflected waves b 1  and b 2 . Ground is represented with reference numbers  94  and  98 . Ground is included in the system of  FIG. 4 , but is not shown in  FIG. 4 .  FIG. 7  also includes a corresponding generalized representation of ABCD parameters  90  with currents I 1  and I 2  and voltages V 1  and V 2 . 
         [0030]      FIG. 8  is a generalized representation of s-parameters  108  of a four port (differential) channel between signal conductor ends  112 ,  116  and  122 ,  126  with incident waves a 1 , a 2 , a 3 , and a 4 , and reflected waves b 1 , b 2 , b 3 , and b 4 . Ground is represented with reference numbers  114 ,  118 ,  124 , and  128 . Ground is included in the system of  FIGS. 1 and 3 , but is not shown in them.  FIG. 8  also includes a corresponding generalized representation of ABCD parameters  110  with currents I 1 , I 2 , I 3 , and I 4 , and voltages V 1 , V 2 , V 3 , and V 4 . 
         [0031]    The following algorithm is used in some embodiments. In other embodiments, the algorithm is different. A network analyzer or other instrument in tester  46  (or tester  86 ) may measure the channel s-parameters in the frequency domain. Tester  46  (or tester  86 ) transforms S-parameters into ABCD parameters. Tester  46  samples voltages V 3  and V 4  in the case of differential channels as in  FIG. 3 , and tester  86  samples voltage V 2  in the case of single ended channels as in  FIG. 4 . Tester  46  (or tester  86 ) transfers the measured signal to the frequency domain using a Fourier transform. A filtering algorithm (discussed below) may be used to filter background noise. 
         [0032]    An input signal calculation may be performed as follows. The equation of  FIG. 9  relates the single ended circuit of  FIG. 4  described by equation in  FIG. 5 . V 1  and V 2  are input and output voltages, where A, B, C, and D are ABCD parameters, Zo 1  is the transmitter output impedance load and Zo 2  is the tester input impedance load. The measurement of Zo 1  may be made for one board or a few boards to get an accurate value and then reused in connection with other DUTs on the same or very similar boards. The value of Zo 2  may be provided by the tester manufacturer or measured using network analyzer. The calculated input signal V 1  is transferred to the time domain using an inverse Fourier transform. 
         [0033]    For use in the differential case related to the circuit described in the picture in  FIG. 3  and in the equation in  FIG. 6 , the equations of  FIGS. 10 and 11  show T load  and T source  matrices, where T source  is an impedance of the transmitter output and T load  is an impedance of tester  46  as reviewed from the channels. A product matrix N is defined in equation (1) as follows: 
         [0000]        N=T   source   *T*T   load   (1) 
         [0000]    wherein matrix T is shown in  FIG. 6 , matrix T source  is shown in  FIG. 10 , and matrix T load  is shown in  FIG. 11 . N is called the product matrix because it is the product of multiplication. The matrix T includes characteristics of the path from TX  12  to tester  46  including channels  18  and  20 . The values of T can be obtained from measurement. The matrix T source  includes impedance characteristics of transmitter  12  and the matrix T load  includes impedance characteristics of the input of tester  46 . 
         [0034]    The channel input voltage signals V 1  and V 2  can be calculated by tester  46  by using the following equations (2) and (3). 
         [0000]        V 1 =N 11× V 3 +N 13 ×V 4  (2) 
         [0000]        V 2 =N 31 ×V 3 +N 33 ×V 4  (3) 
         [0000]    wherein V 1 , V 2 , V 3 , and V 4  are the voltages of  FIG. 1 , N 11  is row 1, column 1 of the matrix N of equation (1); N 13  is row 1, column 3 the matrix N of equation (1), N 31  is row 3, column 1 of the matrix N of equation (1); N 33  is row 3, column 3 the matrix N of equation (1). 
         [0035]    Note that equations (2) and (3) are just for the V terms. In some embodiments, the I terms I 1  and I 2  can be obtained by replacing V 3  and V 4  with I 3  and I 4  and replacing N 11 , N 13 , N 31 , and N 33  with N 22 , N 24 , N 42 , and N 44 . 
         [0036]    The calculated input signals V 1  and V 2  for the differential case can be transferred to the time domain using an inverse Fourier transform. 
         [0037]    Signals measured by an oscilloscope or other tester contains instrument internal noise. This noise may be increased by a de-embedding algorithm and may mask signals. Accordingly, in some embodiments, the noise may be filtered before de-embedding the algorithm is applied. There are various ways in which the filtering algorithm may be implemented removing background noise from the whole measured spectrum or from the part of the measured spectrum. In some embodiments, the filtering algorithm includes the following details, while in other embodiments it includes somewhat different details—and in still other embodiments, the filtering algorithm is not used. In some embodiments, a noise power mean level is found. For each bin in a frequency domain, bin power is compared with the noise power mean level. The following is some pseudo code. 
         [0038]    If bin power−noise power &gt;10 dB, leave the bin as is, 
         [0039]    Else new_bin_magnitude=previous_bin_magnitude/10000 
         [0040]    End 
         [0000]    As an example, the algorithm is tested by measuring a 3.125 GHz signal with the oscilloscope at the channel input and at the channel output. Then, the channel input is estimated from the channel output measurement using the algorithm and compared to the channel input measurement. 
         [0041]    As a result of the de-embedding process described herein, fewer components may be failed during the DUT test process. 
       ADDITIONAL INFORMATION AND EMBODIMENTS 
       [0042]    The “logic” referred to herein can be implemented in circuits, software, microcode, or a combination of them. 
         [0043]    An embodiment is an implementation or example of the invention. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. 
         [0044]    When it is said the element “A” is coupled to element “B,” element A may be directly coupled to element B or be indirectly coupled through, for example, element C. 
         [0045]    When the specification or claims state that a component, feature, structure, process, or characteristic A “causes” a component, feature, structure, process, or characteristic B, it means that “A” is at least a partial cause of “B” but that there may also be at least one other component, feature, structure, process, or characteristic that assists in causing “B.” Likewise, that A is responsive to B, does not mean it is not also responsive to C. 
         [0046]    If the specification states a component, feature, structure, process, or characteristic “may”, “might”, or “could” be included, that particular component, feature, structure, process, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. 
         [0047]    The invention are not restricted to the particular details described herein. Indeed, many other variations of the foregoing description and drawings may be made within the scope of the present invention. Accordingly, it is the following claims including any amendments thereto that define the scope of the invention.

Technology Category: 3