Patent Document

FIELD OF THE INVENTION 
   The disclosure relates to an arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, and a semiconductor device comprising at least one such arrangement of resistors. 
   BACKGROUND SECTION 
   Semiconductor devices, e.g. appropriate, integrated (analog or digital) computing circuits, semiconductor memory devices such as functional memory devices (PLAs, PALs, etc.) and table memory devices, e.g. ROMs or RAMS, in particular SRAMs and DRAMs) comprise a plurality of output pads for outputting data generated in the respective semiconductor device. 
   The output pads are connected with a device driving the corresponding output signals, i.e. a driver device. 
   Each driver device may, for instance, comprise a pull-up and a pull-down circuit which are connected in series, wherein the pull-up circuit may e.g. be connected to the supply voltage, and the pull-down circuit may e.g. be connected to the ground, and wherein—for the driving of a “logically high” output signal—the pull-up circuit may be switched on and the pull-down circuit may be switched off, and—for the driving of a “logically low” output signal—the pull-up circuit may be switched off and the pull-down circuit may be switched on. 
   For linearization of the driver behavior, a correspondingly large resistor, in particular an n-diffusion resistor, may be connected between a corresponding driver device and the respective output pad. 
   For generating an n-diffusion resistor, the corresponding region on the semiconductor device or the chip, respectively, is—relatively strongly—n-doped. 
   The resistance value of the respective n-diffusion resistor may, for instance, by set to the respectively desired amount by correspondingly selecting the length (or the breadth or the width, respectively) of the n-diffusion resistor—the longer (or broader) the n-diffusion resistor is, the higher (or lower) is the resulting resistance value. 
   For technological reasons, the—relatively strongly n-doped—diffusion regions of the n-diffusion resistors are embedded in a weaker n-doped region, i.e. a so-called wn-well. 
   In order to save chip space, several (in particular all) n-diffusion resistors are, as a rule, arranged—side by side—in one single wn-well. 
   Consequently, the n-diffusion resistors are—via the parasitic resistor formed by the wn-well—connected with one another, so that adjacent n-diffusion resistors mutually influence each other in their respective—effectively—resulting resistance value. 
   This influence is the higher, the greater the difference between the resistance values of respectively adjacent n-diffusion resistors is. 
   For this reason, the distance between respectively adjacent n-diffusion resistors must be chosen relatively large in prior art (in particular in the case of a relatively great difference between the resistance values). 
   This—relatively large—distance between the n-diffusion resistors leads to a relatively large chip space needed altogether for the arrangement of the n-diffusion resistors. 
   SUMMARY OF THE INVENTION 
   An arrangement of several resistors jointly positioned in one and the same well of a semiconductor device, and a semiconductor device comprising at least one such arrangement of resistors. 
   An arrangement of several resistors jointly positioned in one and the same well, in particular a wn-well, of a semiconductor device is provided, wherein the resistors—viewed in the longitudinal direction of the resistors—are displaced in relation to each other. 
   In a preferred development of the invention, the resistors—viewed in the longitudinal direction of the resistors—are alternately displaced to the front and to the rear (wherein, advantageously, each of the resistors displaced to the front is displaced by the same length to the front, and each of the resistors displaced to the rear is displaced by the same length to the rear). 
   It is of particular advantage when a particular resistor is displaced—vis-à-vis its directly adjacent resistor—by approximately the length l (or somewhat less than the length l) of the directly adjacent resistor—viewed in longitudinal direction of the resistors. 
   Preferably, all resistors have a substantially identical structure and feature substantially the same individual resistance value. 
   This—and the relatively large distances between two adjacent resistors positioned in the same plane, said distances resulting from the above-described displaced arrangement of the resistors,—has as a consequence that the resistors—which are connected with one another via the parasitic resistor formed by the wn-well—influence each other only relatively weakly in their respective—effectively—resulting resistance value. 
   The distance between directly succeeding or adjacent resistors—positioned in displaced planes—can therefore be chosen relatively small. 
   This leads altogether to a relatively small chip space needed for the resistor arrangement. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the following, the invention will be explained in detail by means of embodiments and the enclosed drawing. The drawing shows: 
       FIG. 1  a sectional view of a portion of a semiconductor device with an arrangement of adjacent n-diffusion resistors positioned in a wn-well, and of metal pads contacting same, in accordance with prior art; 
       FIG. 2  a sectional view of a portion of a semiconductor device with an arrangement of adjacent n-diffusion resistors positioned in a wn-well, and of metal pads contacting same, in accordance with an embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 1  illustrates a sectional view of a portion  1  of a semiconductor device with an arrangement of adjacent n-diffusion resistors  3   a ,  3   b  positioned in a wn-well  2 , and of metal pads  4   a ,  4   b ,  5   a ,  5   b  contacting same, in accordance with prior art. 
   The semiconductor device may, e.g. be an integrated (analog or digital) computing circuit, or a semiconductor memory device such as functional memory device (PLA, PAL, etc.), or a table memory device (e.g. ROM or RAM), in particular a DRAM, e.g. a DDR DRAM (Double Data Rate DRAM). 
   The metal pads  4   a ,  5   a  positioned “at the front” on the semiconductor device illustrated in  FIG. 1  may e.g. be connected to corresponding (not illustrated) output pads of the semiconductor device, and the metal pads  4   b ,  5   b  positioned “at the rear” may e.g. be connected to corresponding (not illustrated, either) signal driver devices. 
   As is further illustrated in  FIG. 1 , the front metal pads  4   a ,  5   a  contact the respective n-diffusion resistor  3   a ,  3   b —via a corresponding diffusion metal contact  6   a ,  7   a —at a region positioned at the front end of the n-diffusion resistor  3   a ,  3   b , and the rear metal pads  4   b ,  5   b  contact the respective n-diffusion resistor  3   a ,  3   b —via a corresponding diffusion metal contact  6   b ,  7   b —at a region positioned at the rear end of the n-diffusion resistor  3   a ,  3   b.    
   By the fact that the resistance value of the respective n-diffusion resistor  3   a ,  3   b  connected between the corresponding signal driver device and the corresponding output pad is chosen correspondingly high, a linearization of the driver behavior may be achieved with the semiconductor device. 
   For generating the n-diffusion resistors  3   a ,  3   b , the corresponding region on the semiconductor device or the chip, respectively, is—relatively strongly—n-doped. 
   The resistance value of the n-diffusion resistors  3   a ,  3   b  may, for instance, be set to the respectively desired amount by selecting (e.g. with respectively identical length l of the n-diffusion resistors  3   a ,  3   b ) their width or breadth b correspondingly—differently—large (in the development shown in  FIG. 1 , for instance, the (first) n-diffusion resistor  3   a  is designed with a—relatively large—breadth b′, and the (second) n-diffusion resistor  3   a  with a—relatively small—breadth b″, so that a relatively low resistance value results for the first n-diffusion resistor  3   a , and a relatively high resistance value results for the second n-diffusion resistor  3   b ). 
   For technological reasons, the—relatively strongly n-doped—diffusion regions of the n-diffusion resistors  3   a ,  3   b  are embedded in a—relatively weakly n-doped—region (namely the above-mentioned wn-well  2 ). 
   In order to save chip space, several (in particular all) n-diffusion resistors  3   a ,  3   b  are arranged—side by side—in one single wn-well  2  (i.e. in addition to the first and second n-diffusion resistors  3   a ,  3   b  illustrated in  FIG. 1 , several further, not illustrated n-diffusion resistors). 
   Consequently, the n-diffusion resistors  3   a ,  3   b  (and the further, not illustrated n-diffusion resistors) are—via the parasitic resistor formed by the wn-well  2 —connected with one another, so that adjacent n-diffusion resistors  3   a ,  3   b  mutually influence each other in their respective—effectively—resulting resistance value. 
   This influence is the higher, the greater the difference between the resistance values of respectively adjacent n-diffusion resistors  3   a ,  3   b  is. 
   For this reason—in the arrangement of the n-diffusion resistors  3   a ,  3   b  according to prior art as illustrated in FIG.  1 —, the distance a between respectively adjacent n-diffusion resistors  3   a ,  3   b  must be chosen relatively large (in particular in the case of a relatively great difference between the resistance values of the n-diffusion resistors  3   a ,  3   b ). 
   This—relatively large—distance a between the n-diffusion resistors  3   a ,  3   b  leads to a relatively large chip space needed altogether for the arrangement of the n-diffusion resistors  3   a ,  3   b.    
     FIG. 2  shows a sectional view of a portion  11  of a semiconductor device with an arrangement of adjacent n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  positioned in a wn-well  12 , and of metal pads  14   a ,  14   b ,  14   c ,  14   d ,  14   e ,  14   f ,  15   a ,  15   b ,  15   c ,  15   d  contacting same, in accordance with an embodiment of the invention. 
   The semiconductor device may e.g. be an integrated (analog or digital) computing circuit, or a semiconductor memory device such as functional memory device (PLA, PAL, etc.), or a table memory device (e.g. ROM or RAM), in particular a DRAM, e.g. a DDR DRAM (Double Data Rate DRAM). 
   As is illustrated in  FIG. 2 , the metal pads  14   a ,  14   c ,  14   e ,  15   a ,  15   c —positioned further “at the front” on the semiconductor device vis-à-vis the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e —contact the respective n-diffusion resistor  13   a ,  13   b ,  13   c ,  13   d ,  13   e  —via a corresponding diffusion metal contact  16   a ,  17   a —at a region positioned at the front end of the n-diffusion resistor  13   a ,  13   b ,  13   c ,  13   d ,  13   e.    
   In analogy, the metal pads  14   b ,  14   d ,  14   f ,  15   b ,  15   d —positioned further “at the rear” on the semiconductor device vis-à-vis the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e —contact the respective n-diffusion resistor  13   a ,  13   b ,  13   c ,  13   d ,  13   e —via a corresponding diffusion metal contact  16   b ,  17   b —at a region positioned at the rear end of the n-diffusion resistor  13   a ,  13   b ,  13   c ,  13   d ,  13   e.    
   As will be explained in detail further below, the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  are—via the metal pads  14   a ,  14   c ,  14   e ,  15   a ,  15   c  and the metal pads  14   b ,  14   d ,  14   f ,  15   b ,  15   d —connected between (not illustrated) output pads of the semiconductor device and corresponding (not illustrated, either) signal driver devices of the semiconductor device. 
   For generating the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e , the corresponding region on the semiconductor device or the chip, respectively, is—in a way known as such—relatively strongly n-doped. 
   As is further illustrated in  FIG. 2 , the—relatively strongly n-doped—diffusion regions of the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  are embedded in a—relatively weakly n-doped—region (namely the wn-well  12  already mentioned above). 
   In order to save chip space, several (e.g. more than two, three, or four, in particular all) n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  of the semiconductor device are positioned in one single wn-well  12  (i.e. in addition to the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  illustrated in  FIG. 2 , a plurality of further, not illustrated n-diffusion resistors). 
   The above-mentioned n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  positioned in one and the same wn-well  12  all have a substantially identical structure. In particular, the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  all have substantially the same length 1, and the same width or breadth b, and the same depth t. 
   For this reason, a—substantially—identical individual resistance value R results for all of the above-mentioned n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e.    
   As is further shown in  FIG. 2 , the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e —being positioned side by side—are, viewed in longitudinal direction of the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e , alternately displaced “to the front” or “to the rear” (namely such that every second n-diffusion resistor (e.g. the first, third, and fifth n-diffusion resistors  13   a ,  13   c ,  13   e ) is displaced to the “rear” e.g. by a respectively identical, for instance by substantially half a resistor length ½, and the remaining n-diffusion resistors positioned therebetween (here e.g. the second and fourth n-diffusion resistors  13   b ,  13   d ) are displaced by a corresponding length (e.g. half a resistor length ½) to the “front”. 
   The central axes (in particular the central transverse axes) of every second of the adjacent n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  (i.e. the central axes of the first, third, and fifth n-diffusion resistors  13   a ,  13   c ,  13   e , and the central axes of the second and fourth n-diffusion resistors  13   b ,  13   d ) each lie in one and the same plane (extending transversely from the top to the bottom through the semiconductor device). 
   Furthermore—also with every second n-diffusion resistor  13   a ,  13   b ,  13   c ,  13   d ,  13   e  (i.e. with the first, third, and fifth n-diffusion resistors  13   a ,  13   c ,  13   e , and with the second and fourth n-diffusion resistors  13   b ,  13   d )—the respective front ends of the corresponding n-diffusion resistors  13   a ,  13   c ,  13   e  or  13   b ,  13   d , respectively (and thus the corresponding—front—diffusion metal contacts  16   a  or  17   a , respectively, of the corresponding n-diffusion resistors  13   a ,  13   c ,  13   e  or  13   b ,  13   d , respectively) lie in one and the same plane (extending in parallel to the above-mentioned central planes). 
   An analogy—also with every second n-diffusion resistor  13   a ,  13   b ,  13   c ,  13   d ,  13   e  (i.e. with the first, third, and fifth n-diffusion resistors  13   a ,  13   c ,  13   e , and with the second and fourth n-diffusion resistors  13   b ,  13   d )— the respective rear ends of the n-diffusion resistors  13   a ,  13   c ,  13   e  or  13   b ,  13   d , respectively (and thus the corresponding—rear—diffusion metal contacts  16   b  or  17   b , respectively, of the corresponding n-diffusion resistors  13   a ,  13   c ,  13   e  or  13   b ,  13   d , respectively) lie in one and the same plane. 
   As is further illustrated in  FIG. 2 , the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  are—alternately—displaced to the “front” or to the “rear”, respectively, to such an extent that the respective front ends of the first, third and fifth n-diffusion resistors  13   a ,  13   c ,  13   e  displaced to the “rear” (and thus their front diffusion metal contacts  16   a ) each lie substantially in the same plane as the respective rear ends of the second and fourth n-diffusion resistors  13   b ,  13   d  displaced to the “front” (and thus their rear diffusion metal contacts  17   b ). 
   Every second of the respectively adjacent metal pads  14   a ,  14   b ,  14   c ,  14   d ,  14   e ,  14   f ,  15   a ,  15   b ,  15   c ,  15   d  has an identical length k′ or k″, respectively (in particular has every second of the respective front metal pads  14   a ,  14   c ,  14   e , and every second of the respective rear metal pads  15   b ,  15   d  a—relatively great, first—length k′, and the metal pads  14   b ,  14   d ,  14   f ,  15   a ,  15   c  therebetween have a—relatively small, second—length k″, so that—despite the above-mentioned displaced arrangement of the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e —the respective front ends of all respective front metal pads  14   a ,  14   c ,  14   e ,  15   a ,  15   c , and the respective rear ends of all respective rear metal pads  14   b ,  14   d ,  14   f ,  15   b ,  15   d  each are substantially positioned in one and the same plane). 
   As already explained above, each of the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  has a—substantially—identical individual resistance value R. 
   Depending on the respectively desired resistance value R desired  of an intermediate resistor—which is to be formed by the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  and is to be connected between a particular signal driver device and the pertinent output pad—, a particular number of n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  is connected in parallel and is connected with the corresponding output pad and the pertinent signal driver device (so that—for e.g. two n-diffusion resistors  13   a ,  13   b  connected in parallel—e.g. a total resistance value R total  of R/2 results for the resulting intermediate resistor, for three n-diffusion resistors  13   a ,  13   b ,  13   c  connected in parallel, e.g. a total resistance value R total  of R/3, etc.). 
   For connecting the corresponding n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  in parallel between a particular output pad and a pertinent driver device, the corresponding front metal pads  14   a ,  14   c ,  14   e ,  15   a ,  15   c  of the respective n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  to be connected in parallel are—jointly—connected to the corresponding output pad, and the corresponding rear metal pads  14   b ,  14   d ,  14   f ,  15   b ,  15   d  of the respective n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  to be connected in parallel are—jointly—connected to the corresponding signal driver device. 
   By the fact that the resistance value R total  of the respective intermediate resistor that is connected between the corresponding signal driver device and the corresponding output pad—and that is formed by the corresponding number of n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  connected in parallel—is chosen appropriately (in particular such that the following applies: R total ≅R desired ), a linearization of the driver behavior may be achieved with the semiconductor device. 
   Since all n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  have the same individual resistance value R, and due to the relatively large distance c between two respectively adjacent n-diffusion resistors lying in the same plane, which results from the displaced arrangement of the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  (e.g. the distance c between the second n-diffusion resistor  13   b  and the fourth n-diffusion resistor  13   d ), the influence of the parasitic resistor—formed by the wn-well  12  and connecting the individual n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  with one another—on the effectively resulting individual resistance R′ of the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e —taking into account the parasitic resistor—(or on the total resistance value R total ′ effectively resulting by the above-mentioned parallel connection—taking into account the parasitic resistor—) is relatively minor. 
   For this reason, in the arrangement of the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  illustrated in  FIG. 2 , the distance a between directly succeeding n-diffusion resistors lying in displaced planes (e.g. the distance a between the first n-diffusion resistor  13  and the second n-diffusion resistor  13   b , the distance a between the second n-diffusion resistor  13   b  and the third n-diffusion resistor  13   c , etc.) may be chosen relatively small. 
   This—relatively small—distance a between the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  leads to a relatively small chip space needed altogether for the arrangement of the n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e.    
   Since the structure of each n-diffusion resistor  13   a ,  13   b ,  13   c ,  13   d ,  13   e  is identical to the structure of the remaining n-diffusion resistors  13   a ,  13   b ,  13   c ,  13   d ,  13   e  (and since each n-diffusion resistor is arranged appropriately vis-à-vis the remaining ones), a standard environment is provided which—once—modelled and verified, enables an exact predictability of the respective—effectively—resulting resistance values.

Technology Category: 5