Patent Document

TECHNICAL FIELD 
     The present invention relates to a method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions, and using a small number of masks. 
     BACKGROUND OF THE INVENTION 
     In advanced processes (gate lengths of 0.35 μm or less), the need has recently arisen to integrate EEPROM-type non-volatile memories in high-speed devices that use the technique of saliciding the diffusions. As known, this technique is based on the use of a layer of self-aligned silicide (“salicide” from “Self-Aligned Silicide”), which reduces the resistivity of the junctions. The layer of salicide (which typically comprises titanium, but can also be cobalt or another transition metal) is formed by depositing a titanium layer on the entire surface of the device, and performing a heat treatment that makes the titanium react with the silicon, which is left bare on the junctions and the gate regions, such as to form titanium silicide. Subsequently, the nonreacted titanium (for example that deposited on oxide regions), is removed by etching with an appropriate solution, which leaves the titanium silicide intact. Thereby, both the gate regions and the junctions have in parallel a silicide layer with low resistivity (approximately 3-4 Ω/square), which reduces the series resistance at the transistors. The salicide technique is described for example in the article “Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxide-semiconductor and complementary metal-oxide-semiconductor technologies” by R.A. Haken, in  J. Vac. Sci. Technol. B , vol 3, No. 6, Nov/Dec 1985. 
     The high voltages necessary for programming non-volatile memories (higher than 16 V) are however incompatible with saliciding the memory cells diffusions, since the breakdown voltage of the salicided junctions is lower than 13 V. 
     Process flows are thus being designed which permit integration of non-volatile memory cells and high-speed transistors with saliciding; however this integration is made difficult by the fact that these components have different characteristics, and require different process steps. 
     SUMMARY OF THE INVENTION 
     The invention provides a method for manufacturing non-volatile cells and high-speed transistors with a small number of masks, which is simple, and has the lowest possible costs. 
     According to the present invention, a method is provided for manufacturing of electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions, and to the resulting electronic device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     To assist understanding of the present invention, an embodiment is now described, purely by way of non-limiting example, with reference to the attached drawings, in which: 
     FIG. 1 shows a cross-section through a silicon wafer, in a first step of the manufacturing method according to the invention; 
     FIG. 2 shows a top view of the wafer of FIG. 1; 
     FIGS. 3-6 show cross-sections similar to FIG. 1, in successive manufacturing steps; 
     FIG. 7 shows a top view of the wafer of FIG. 6; 
     FIGS. 8-9 show cross-sections similar to FIG. 6, in successive manufacturing steps; 
     FIG. 10 shows a top view of the wafer of FIG. 9; 
     FIGS. 11-16 show cross-sections similar to FIG. 9, in successive manufacturing steps; 
     FIG. 17 shows a top view of the wafer of FIG. 16; 
     FIGS. 18-21 show cross-sections similar to FIG. 16, in successive manufacturing steps; 
     FIG. 22 shows a top view of the wafer of FIG. 21; and 
     FIGS. 23-24 show cross-sections similar to FIG. 21, in successive manufacturing steps. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description relates to the manufacturing of LV (low voltage and high speed) and HV (high voltage) NMOS transistors, LV and HV PMOS transistors, and EEPROM memory cells, having a selection transistor and a memory transistor. In particular, in view of the duality in manufacturing NMOS and PMOS transistors, the drawings show only the steps relative to NMOS transistors, and the steps relative to PMOS transistors are described in words alone. The EEPROM memory cells form a memory matrix and are formed in a part of the wafer referred to hereinafter as a matrix zone  15 . 
     In FIG. 1, a wafer  1 , formed from a monocrystalline silicon substrate  2 , here of P-type, has been subjected to the steps of defining the active areas. In detail, with the surface  3  of the substrate  2  covered by an active area mask  4  made of non-oxidisable material (typically including a double layer of silicon oxide and silicon nitride, defined using resist), the wafer  1  has been subjected to thermal oxidation; consequently, on the parts of the substrate  2  which are not covered by the active area mask  4 , thick oxide (field oxide) layers  5  have been grown, delimiting between one another substrate active areas designed to accommodate various components of the device to be formed. In particular, FIG. 1 shows three active areas, an active LV area  6 , designed to accommodate an LV NMOS transistor, an active HV area  7 , designed to accommodate an HV NMOS transistor, and an active matrix area  8 , designed to accommodate EEPROM memory cells. 
     In detail, and in known manner, the active matrix area  8  defines a grid, of which FIG. 2 shows in full only the part relative to a cell, indicated at  9 , which has substantially the shape of a “T” rotated by 90°, and comprises a leg  9   a  (far from active HV area  7 ) and a cross-piece  9   b . Leg  9   a  is adjacent and electrically connected to respective legs  9   a  of other cells arranged above and below the cell shown, and of which only parts are shown; in addition, the leg  9   a  is connected to a leg of an adjacent cell to the right (not shown), which has a structure which is symmetrical relative to that shown. The legs  9   a  are designed to accommodate source regions of the memory transistors; the end of cross-pieces  9   b  are designed to accommodate drain regions of the selection transistors and gate regions of the cells must be formed on the cross-pieces  9   b . Further active areas are generally formed to accommodate LV or HV PMOS transistors, not shown in the drawings. 
     Subsequently active area mask  4  is removed, the free surface  3  of the substrate is oxidized to form a sacrificial oxide layer  10 , and masked implanting of doping ion species of N-type is carried out, to form N-HV regions (not shown) for HV PMOS transistors; then, using an HV P-well resist mask  11 , which covers the entire surface of the wafer  1 , except HV active area  7  and matrix area  8 , implanting of doping ionic species of P-type is carried out, as shown schematically in FIG. 3 by arrows  12 . Then P-HV regions  13  of P-type for high-voltage transistors, and a P-matrix region  14 , also of P-type, for cells, is formed in the substrate  2 , as shown in FIG.  3 . P-HV region  13  and P-matrix region  14  reproduce exactly the shape of the respective HV active area  7  and matrix area  8 , and thus, each cell comprises legs  14   a  (corresponding to legs  9   a  of the active areas of cell  9 , see FIG.  7 ), and cross-pieces  14   b  (FIG. 7, corresponding to the cross-pieces  9   b ). 
     After HV P-well mask  11  has been removed, masked implanting of doping ionic species of N-type is carried out, to form N-LV regions (not shown) for LV PMOS transistors; then, using an LV P-well resist mask  17  that covers the entire surface of the wafer  1 , except LV active areas  6 , doping ionic species of P-type are implanted, as shown schematically in FIG. 4 by arrows  18 . P-LV regions  19  of P-type for LV NMOS transistors are then formed in substrate  2 , as shown in FIG.  4 . Thereby, P-HV regions  13  and P-LV regions  19  are separated from one another, and their electrical characteristics can be optimized to the required electrical characteristics. 
     After LV P-well mask  17  has been removed, a capacitor mask  20  is formed, which covers the entire surface of the wafer  1 , except strips perpendicular to the cross-pieces  14   b . Doping species of N-type (for example phosphorous) are then implanted, as shown schematically in FIG. 5 by arrows  21 . In the cross-pieces  14   b , continuity regions  22  of N-type are thus formed, as necessary for electrical continuity between each selection transistor and the respective memory transistor of each cell. The structure of FIG. 5 is thus obtained. 
     After capacitor mask  20  has been removed, wafer  1  is subjected to annealing, sacrificial layer  10  is removed, and matrix oxidation is carried out, leading to a matrix oxide layer  25  forming on the surface of all the regions  13 ,  14  and  19 . Then, using a matrix oxide mask  24 , shown in cross-section in FIG. 6, and from above in FIG. 7, the matrix oxide layer is removed everywhere except from below the matrix oxide mask  24 , forming a region  25   b  (FIG. 8) arranged partially above the continuity region  22  and partially covering the leg  9   a ; after matrix oxide mask  24  has been removed, wafer  1  is oxidized again, forming a tunnel oxide region  26  on the entire surface of the active areas. The structure in FIG. 8 is thus obtained. 
     A first polycrystalline silicon layer (polyl layer)  27  is then deposited and suitably doped; an interpoly dielectric layer  31  is then formed, for example comprising a triple layer of ONO (silicon oxide-silicon nitride-silicon oxide), as shown in FIG.  9 . 
     A floating gate mask  30 , shown in FIG. 10, is formed; then dielectric layer  31 , polyl layer  27 , and tunnel oxide layer  26  are removed from everywhere except where floating gate regions of the memory transistors are to be formed, as indicated at  27   b  in FIG.  11 . Consequently, of tunnel oxide layer  26 , only a tunnel region  26   b  is left, which is adjacent to an edge of floating gate region  27   b  of the memory transistor. 
     After floating gate mask  30  has been removed, an HV oxidation step is carried out, forming an HV gate oxide layer  34  on the entire free surface of substrate  2 , and in particular on regions P-LV  19  and P-HV  13  (FIG.  12 ). Oxide portions  34   b  are also formed laterally to the floating gate region  27   b  of the memory transistor, as shown in FIG.  12 . Subsequently, using an HV resist oxide mask  35 , which covers regions P-HV  13  and matrix zone  15 , HV gate oxide layer  34  is removed from above regions P-LV  19  (FIG.  13 ). 
     After HV oxide mask  35  has been removed, an LV oxidation step is carried out, forming an LV gate oxide layer  36  on regions P-LV  19 ; in addition, the thickness of HV gate oxide layer  34  on P-HV regions  13  increases, providing the intermediate structure of FIG.  14 . 
     A second polycrystalline layer (poly 2  layer  43 ) then is deposited and doped, as shown in FIG.  15 . An LV gate mask  44  is then formed, which covers regions N-HV (not shown), regions P-HV  13 , and matrix zone  15 , except where cell source regions and cell drain regions are to be formed, such as to define both sides of the control gate regions of the memory transistors, and one side (facing the respective memory transistor) of gate regions of selection transistors. In addition, LV gate mask  44  covers poly 2  layer on regions P-LV  19 , where gate regions of LV NMOS and PMOS transistors are to be defined, as shown in FIGS. 16 and 17, and N-LV regions (not shown), where gate regions of LV PMOS transistors are to be defined. The exposed portions of poly 2  layer  43  are then removed, providing the intermediate structure of FIG. 16, wherein the remaining portions of poly 2  on regions P-LV  19  form gate regions  43   a  of LV NMOS transistors, and the remaining portions of poly 2  on P-matrix regions  14  form control gate regions  43   b  of the memory transistors. As is known, while defining the gate regions of LV transistors, the layers on regions P-HV  13  are protected, as are the layers on regions N-HV (not shown); consequently, the method described provides separate definition of the gate regions of the LV transistors and the HV transistors. 
     After LV gate mask  44  has been removed, wafer  1  is subjected to oxidation, such that an oxide layer  46  grows on the exposed portions of the poly 2  layer. Using a resist mask, not shown, which covers regions N-LV and N-HV, doping ionic species of N-type (LDDN implanting) are implanted, as schematized by arrows  47  in FIG.  18 . At the sides of gate regions  43   a  (inside regions P-LV  19 ), LDD regions  48  of N-type are then formed; and at the sides of gate region  27   b  (inside P-matrix region  14 ), first cell source regions  49  of N-type, and drain regions  50  of N-type, also defining source regions of selection transistors, are formed; in addition, poly 2  layer  43  is suitably doped. The structure of FIG. 18 is thus obtained. 
     After the resist mask (not shown) has been removed, masked implanting of doping ionic species of P-type is carried out; in particular, during this step, regions P-HV  13  and P-LV  19 , as well as matrix zone  15  are covered, whereas in regions N-LV, LDD regions of P-type (not shown) are formed. A dielectric layer (for example TEOS-TetraEthylOrthoSilicate) is then deposited on the entire surface of wafer  1 ; then, in known manner, the TEOS layer is subjected to anisotropic etching and is removed completely from the horizontal portions, remaining only at the sides of the gate regions  43   a  (where it forms spacers  52 , FIG.  19 ), on the side of the floating gate region  27   b  and control gate region  43 b of the memory transistors which does not face the respective selection transistor (on the source region  49 , where it forms spacers  53   b ), on the side of the floating gate region  27   b  and the control gate region  43   b  of the memory transistors which faces the respective selection transistor (on the drain region  50 , where it forms spacers  53   a ), as well as on the side already defined of the poly 2  layer  43 , which is designed to form the gate region of the selection transistors (where it forms spacers  53   c ). In particular, the spacers  53   b  and  53   c  on each drain region  50  are connected to one another, forming a single region which protects the drain region  50  beneath. On the other hand, spacers are not formed above field oxide regions  5 , since the edges of the latter are birds beak-shaped (formed in known manner, not shown for simplicity); in addition, no spacers are formed above regions P-HV  13 , and corresponding regions N-HV, since the gate regions of the HV transistors are not yet defined. The oxide layer  46  is also removed in this step. 
     Subsequently, using a resist mask, not shown, which covers regions N-LV and N-HV, doping ionic species of N-type are implanted, as schematically shown in FIG. 19 by arrows  54 . LV-NMOS source and drain regions  55  of N+-type are then formed in regions P-LV  19 , self-aligned with spacers  52 , and second cell source regions  56  of N+-type are formed self-aligned with spacers  53   a  in P-matrix region  14 . LV-NMOS source and drain regions  55  are more highly doped than LDD regions  48 , and second source regions  56  are more highly doped than first cell source regions  49 . In addition, poly 2  layer  43  and gate regions  43   a  are N-doped, while covering the zones where HV and LV PMOS transistors are to be formed. Thus the structure of FIG. 19 is obtained. 
     After resist mask (not shown) has been removed, analogously doping ionic species of P-type are masked implanted, to form respective source and drain regions in regions of N-LV type (not shown), and for P-type doping of poly 2  layer  43  above N-LV and N-HV regions. In this step, P-LV, P-HV and P-matrix regions are fully covered. 
     Subsequently, if zener diodes, low-doping precision resistors, and/or transistors of N- and P-type with non-salicided junctions are to be provided, a dielectric layer is deposited and defined through a respective mask, in a manner not shown. 
     The exposed poly 2  layer is then salicized. Saliciding, carried out in known manner, as already described, causes the formation of titanium silicide regions above the source and drain regions of the LV NMOS and PMOS transistors (silicide regions  57   a   1  above LV-NMOS source and drain regions  55 , and similar regions for LV PMOS transistors), above the gate regions of LV NMOS and PMOS transistors (silicide regions  57   a   2  above gate regions  43   a  for LV NMOS transistors, and similar regions for LV PMOS transistors), above second cell source regions  56  (silicide regions  57   b   1 ), above control gate regions  43   b  of memory transistors (salicide regions  57   b   2 ) and the regions where gate regions of selection transistors and of HV NMOS and similar HV PMOS transistors are to be formed, as shown in FIG.  20 . 
     Subsequently, an HV gate mask  60  is formed, which covers the entire surface of wafer  1 , except the active areas where high voltage transistors are to be formed (P-HV regions  13 , for HV NMOS), and a portion of P-matrix region  14  designed to form the source of the selection transistor; in particular, mask  60  covers the zones where to form the gate regions of high voltage transistors and the side of the gate regions of selection transistors not facing the respective memory transistor (in this respect see also FIG. 22, which shows HV gate mask  60  from above). The portions of silicide layer  57  and poly 2  layer  43   b  not covered by the HV gate mask  60  are then etched. Thus, the structure of FIG. 21 is obtained, wherein the gate region of the memory transistor is indicated at  43   c , and the gate region of HV NMOS transistor is indicated at  43   d ; the respective portions of salicide are indicated at  57   c  and  57   d . In practice, definition of regions  43   c  and  43   d  takes place after saliciding, and causes removal of the salicide (together with poly 2  layer  43 ), on the high voltage junctions on which silicide must not be present. 
     After HV gate mask  60  has been removed, an N-HV mask  62  is formed, which covers N-LV and N-HV regions (not shown), and P-LV regions  19 . Using NHV mask  62 , doping ionic species of N-type are implanted, as shown schematically in FIG. 23 by arrows  63 . In P-HV regions  13 , at both sides of HV gate regions  43   d , HV-NMOS source and drain regions  64  of N-type are thus formed, which are less doped than LV-NMOS source and drain regions  55 ; simultaneously, in P-matrix region  14 , selection transistor source regions  65   a  are formed, on one side, self-aligned with gate region  43   c  of selection transistors. Selection transistor source regions  65   a  (as well as HV-NMOS source and drain regions  64 ) have a doping level lower than LV-NMOS source and drain regions  55 , and than second cell source regions  56 , and thus they have a higher breakdown voltage, as well as greater resistivity. 
     After NHV mask  62  has been removed, similar masked implanting is carried out for source and drain regions of HV PMOS transistors (which are not shown); a protective dielectric layer  66  is then deposited, providing the structure of FIG. 24, showing an LV NMOS transistor  70 , an HV NMOS transistor  71 , and an EEPROM cell  72 , including a selection transistor  73  and a memory transistor  74 . The final steps then follow, including forming the contacts and the electrical interconnection lines, depositing a passivation layer, etc. 
     Thus, in the final device, EEPROM cells  72  have selection transistor source regions  65   a  which are not salicided, thus have high breakdown voltages, and are obtained independently of the respective drain regions (regions  50 ); second source regions  56  of the memory transistors  74  (forming source lines), which are salicided, and have a different doping from selection source regions  65   a ; control gate lines  43   b  for the memory transistors  74 , and gate regions  43   c  for the selection transistors  73  with low resistivity; in addition gate regions of selection transistors  73  are obtained entirely from the second polycrystalline silicon layer  43 . Furthermore, the cell as a whole is fully non-self-aligned. 
     LV (NMOS and PMOS) transistors have a high-speed LDD structure with a dual gate (gate region  43   a  doped with doping ionic species of the same type as source and drain regions  48 ,  55 ); with salicided source and drain regions  55  and gate region  43   a.    
     HV (NMOS and PMOS) transistors have a dual gate and drain extension structure, with salicided gate region  43   d  alone. 
     The described method thus simultaneously form LV, HV and memory components that have very different characteristics, optimising the necessary number of steps, and using altogether a low number of masks. 
     Finally, it is apparent that many modifications and variants can be made to the method and the device described and illustrated here, all within the scope of the invention, as defined in the attached claims. In particular, the steps described of forming zener diodes and low-doping precision resistors, and N- and P-type transistors with non-salicided junctions, can be omitted if these components are not needed.

Technology Category: h