Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 08/921,237, filed Aug. 29, 1997 now U.S. Pat. No. 5,926,047. 
     This application is related to U.S. patent application Ser. No. 08/921,236 filed on the same day as the instant application by the same assignee as the present invention and entitled Synchronous Clock Generator Including A False Lock Detector. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is directed generally to the field of integrated circuits and, more particularly, to the generation of clock signals for controlling the operation of such circuits. 
     2. Description of the Background 
     Many high-speed integrated circuit devices, such as synchronous dynamic random access memories (SDRAM), microprocessors, etc. rely upon clock signals to control the flow of commands, data, addresses, etc., into, through, and out of the devices. Additionally, new types of circuit architectures such as RAMBUS and SLD RAM require individual parts to work in unison even though such parts may individually operate at different speeds. As a result, the ability to control the operation of a part through the generation of local clock signals has become increasingly more important. 
     Typically, operations are initiated at the edges of the clock signals (i.e., transitions from high to low or low to high). To more precisely control the timing of operations within the device, each period of a clock signal is sometimes divided into subperiods so that certain operations do not begin until shortly after the clock edge. 
     One method for controlling the timing of operations within a period of a clock signal generates phase-delayed versions of the clock signal. For example, to divide the clock period into four subperiods, phase delayed versions are produced that lag the clock signal by 90°, 180° and 270°, respectively. Edges of the phase-delayed clock signals provide signal transitions at the beginning or end of each subperiod that can be used to initiate operations. 
     An example of such an approach is shown in FIG. 1 where the timing of operations in a memory device  10  is defined by an externally provided reference control clock signal CCLKREF and an externally provided reference data clock signal DCLKREF. The reference clock signals CCLKREF, DCLKREF are generated in a memory controller  11  and transmitted to the memory device  10  over a control clock bus  13  and a data clock bus  14 , respectively. The reference clock signals CCLKREF, DCLKREF have identical frequencies, although the reference control clock signal CCLKREF is a continuous signal and the reference data clock signal DCLKREF is a discontinuous signal, i.e., the reference data clock signal DCLKREF does not include a pulse for every clock period. Although the reference clock signals CCLKREF, DCLKREF have equal frequencies, they may be phase shifted by a lag time upon arrival at the memory device  10  due to differences in propagation times, such as may be produced by routing differences between the control clock bus  13  and the data clock bus  14 . 
     Control data CD 1 -CDN arrive at respective input terminals  16  substantially simultaneously with pulses of the reference control clock signal CCLKREF and are latched in respective control data latches  18 . However, if the device attempts to latch the control data CD 1 -CDN immediately upon the edge of the reference clock signal CCLKREF, the control data may not have sufficient time to develop at the input terminals  16 . For example, a voltage corresponding to a first logic state (e.g., a “0”) at one of the input terminals  16  may not change to a voltage corresponding to an opposite logic state (e.g., a “1”) by the time the data are latched. To allow time for the control data CD 1 -CDN to fully develop at the input terminals  16 , the control data are latched at a delayed time relative to the reference control clock signal CCLKREF. To provide a clock edge to trigger latching of the control data CD 1 -CDN at the delayed time, a delay circuit  20  delays the reference clock signal CCLKREF by a delay time to produce a first delayed clock signal CCLKD. Edges of the first delayed clock signal CCLKD activate the control data latches  18  to latch the control data CD 1 -CDN. 
     Data DA 1 -DAM arrive at data terminals  22  substantially simultaneously with the reference data clock signal DCLKREF. Respective data latches  24  latch the data DA 1 -DAM. As with the control data CD 1 -CDN, it is desirable that the data DA 1 -DAM be latched with a slight delay relative to transitions of the reference data clock DCKLREF to allow time for signal development at the data terminals  22 . To provide a delayed clock edge, a delay circuit  26  delays the reference data clock signal DCLKREF to produce a phase-delayed data clock DCLKD that is delayed relative to the reference data clock signal DCLKREF. 
     For latching both control data CD 1 -CDN and data DA 1 -DAM, it is often desirable to allow some adjustment of the phase delay. For example, if the clock frequencies change, the duration of the subperiods will change correspondingly. Consequently, the delayed clocks CCLKD, DCLKD may not allow sufficient signal development time before latching the control data or data, respectively. Also, variations in transmission times of control data, data, or clock signals may cause shifts in arrival times of control data CD 1 -CDN or data DA 1 -DAM relative to the clock signals CCLKREF, DCLKREF of the memory device  10 . 
     One possible approach to producing a variable delay is for the control clock generator to employ a delay-locked loop  28  driven by the external reference clock CLKREF, as shown in FIG.  2 . The reference clock signal CLKREF is input to a conventional, multiple output, variable delay line  30  such as that described in Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,”  IEEE Journal of Solid - State Circuits  31(11):1723-1732, November 1996. The delay line  30  is a known circuit that outputs multiple delayed signals CLK 1 -CLKN with increasing lags relative to the reference signal CLKREF. The delays of the signals CLK 1 -CLKN are variably responsive to a control signal Vcon received at a control port  32 . 
     A feedback path, formed by a comparator  34  and an integrator  36 , produces the control signal Vcon. The feedback path receives the reference clock signal CLKREF at one input of the comparator  34  and receives one of the output signals CLKN from the delay line  30  as a feedback signal at the other input of the comparator  34 . The comparator  34  outputs a compare signal Vcomp that is integrated by the integrator  36  to produce the control signal Vcon. 
     As is known, the control signal Vcon will depend upon the relative phases of the reference clock signal CLKREF and the feedback signal CLKN. If the feedback signal CLKN leads the reference clock signal CLKREF, the control signal Vcon increases the delay of the delay line  30 , thereby reducing the magnitude of the control signal Vcon until the feedback signal CLKN is in phase with the reference signal CLKREF. Similarly, if the feedback signal CLK lags the reference signal CLKREF, the control signal Vcon causes the delay line  30  to decrease the delay until the feedback signal CLKN is in phase with the reference signal CLKREF. 
     In the process of acquiring lock, or if the delay-locked loop  28  is disturbed by an unwanted transient on the power supply, temporary interruption of clock signal, etc., the control voltage Vcon may drive the delay line  30  to the point where the delay line  30  no longer passes a signal. That may occur because voltage-controlled delay lines are generally low-pass devices. More delay causes the cutoff frequency to drop. If that occurs, the phase detector may hang in a state that forces the control voltage to remain at a level which prevents signal transmission through the voltage-controlled delay line  30 . The loop  28  will be hung up, with no output clock signals being produced. Should that occur, it is imperative that the condition be rectified as soon as possible. Thus, there is a need for a loss of signal detector which may detect hang up of the loop  28  and take, or initiate, corrective action. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a loss of signal detector for use with a delay-locked loop of the type which produces a plurality of output signals in response to a clock signal. The detector is comprised of a first monitor for receiving a first one of the plurality of output signals from the delay-locked loop. The second monitor receives a second one of the plurality of output signals from the delay-locked loop. The “second” output signal could be a time delayed version of the first output signal. The first and second signals are preferably, but not necessarily, in quadrature with respect to one another. Each of the monitors is clocked with a clock signal and the inverse of the clock signal. A plurality of logic gates is responsive to the first and second monitors for producing an output signal. 
     The loss of signal detector of the present invention may be incorporated into a synchronous clock generator which comprises a receiver for receiving an external clock signal. A delay line produces a plurality of signals in response to the external clock signal. Each of the plurality of signals is delayed a predetermined period of time with respect to the external clock signal. A plurality of multiplexers is responsive to the delay line for producing at least one clock signal in response to control signals. A first feedback path is responsive to certain of the plurality of signals for producing a feedback signal input to the delay line. A first monitor receives a first one of the plurality of output signals from the delay line while a second monitor receives a second one of the plurality of output signals from the delay line. The first and second signals are substantially in quadrature with respect to each other. Each of the monitors is clocked with the external clock signal and the inverse of the external clock signal. A plurality of logic gates is responsive to the first and second monitors for producing an output signal. 
     The signal loss detector of the present invention provides an early indication that the delay-locked loop has ceased production of local clock signals. The output of the signal loss detector can be used to take corrective action or to initiate corrective action. By promptly recognizing and correcting the loss of signal condition, more adverse consequences resulting from the loss of local clock pulses may be avoided. Those advantages and benefits of the present invention, and others, will become apparent from the Description of the Preferred Embodiments hereinbelow. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For the present invention to be clearly understood and readily practiced, the present invention will be described in conjunction with the following figures wherein: 
     FIG. 1 is a block diagram of a prior art memory system including a memory device and a memory controller linked by control data and data buses; 
     FIG. 2 is a block diagram of a prior art delay-locked loop driven by an external control reference clock signal; 
     FIG. 3 is a block diagram of a synchronous clock generator including a loss of signal detector according to the teachings of the present invention; 
     FIG. 4 illustrates one embodiment of a loss of signal detector that may be used in the synchronous clock generator shown in FIG. 3; 
     FIGS. 5A-5D are a timing diagram helpful in understanding the operation of the loss of signal detector shown in FIG. 4; and 
     FIG. 6 is a more detailed view of the phase detector and charge pump of FIG. 3; 
     FIG. 7 illustrates a block diagram of a system in which the invention shown in FIG. 3 may be used. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 is a block diagram of a synchronous clock generator circuit  38 . The circuit  38  illustrated in FIG. 3 is designed for use by a dynamic random access memory (DRAM) which is used in a SLD RAM architecture. Although the present invention is described with respect to a particular circuit used in a particular architecture, the reader will understand that the concepts of the present invention may be used in other circuits as well as other circuit architectures. The present invention may be employed wherever it is desirable to precisely control the production of local clock signals. 
     A major component of the circuit  38  is a delay line  40 . The delay line  40  may be constructed according to the teachings of the prior art as set forth in the article entitled “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques.” As is known in the art, the delay line  40  has a number of taps associated therewith. As shown in FIG. 3, the delay line  40  has taps labeled T 0 -T 15 , with the last tap labeled 180°. Alternatively, the delay line  40  may be a vernier voltage-controlled delay line  40  of the type disclosed in U.S. patent application Ser. No. 08/879,847 filed Jun. 20, 1997 and entitled Method And Apparatus For Generating A Sequence Of Clock Signals, which is assigned to the same assignee as the present invention. 
     The delay line  40  receives clock signals that are received at a differential receiver  42 . The differential receiver  42  receives the signals CCLKREF, {overscore (CCLKREF)}. The present invention will work with a variety of receivers other than the differential receiver  42  illustrated in FIG.  3 . The clock signal CCLK is input to the delay line  40  through a voltage controlled delay circuit  44 . 
     The output of the delay line  40  is input to a plurality of multiplexers  46  which produce clock signals input to clock drivers  48 . One of the clock drivers  48 ′ produces a clock signal which is input to a latch  50 . The latch  50  receives control data through a receiver  52  and latches that data in response to the clock signal output by the clock driver  48 ′. The latched control data is available at the output of the latch  50 . 
     A first feedback path  53  is comprised of a phase detector  54  and a charge pump  56 . The phase detector  54  receives two signals from the delay line  40  such as the signal available at the T 0  tap and the signal available at the 180° tap. From those signals, a control signal is generated which is input to the charge pump  56 . Charge pump  56  produces a delay control voltage input to the delay line  40 . The first feedback path  53  and the delay line  40  comprise a delay-locked loop. 
     The delay line  40  may be provided with a second, or compound, feedback path  61 . The second feedback path  61  is comprised of a delay matching circuit  62 , a phase detector  66 , and a charge pump  67 . The phase detector  66  receives the clock reference CCLKREF through a receiver  68  and a signal from the delay matching circuit  62 . The phase detector  66  and charge pump  67  work in the same manner as the phase detector  54  and charge pump  56 . Based on the signals input to the phase detector  66 , the charge pump  67  produces a reference delay control voltage which is input to the voltage controlled delayed circuit  44 . As a result, the delay-locked loop can be tuned by the second feedback path  61  to add or subtract delay to the loop by controlling the voltage control delay circuit  44 . Additional information about the feedback path  61  is found in U.S. patent application Ser. No. 08/915,185, filed herewith and entitled Synchronous Clock Generator Including A Compound Delay-Locked Loop, which is assigned to the same assignee as the present invention. 
     Completing the description of FIG. 3, a loss of signal detector  70  constructed according to the teachings of the present invention is provided. The loss of signal detector  70  receives the clock signal CCLK which is available at an output terminal of the voltage control delay circuit  44 . The loss of signal detector  70  also receives two signals from the delay line  40  such as the quad signal (90° signal) and the 180° signal. As discussed below, however, other signals may be used. The loss of signal detector  70  produces an output signal, which is input to the phase detector  54  and the phase detector  66  whenever a loss of signal is detected by the detector  70 . The output signal causes the phase detectors  54 , 66  to control the charge pumps  56 ,  67 , respectively, to force the delay-locked loop to begin producing signal again. 
     FIG. 4 illustrates one embodiment of a loss of signal detector  70  that may be used in conjunction with the synchronous clock generator  38  shown in FIG. 3 while FIGS. 5A-5D illustrate exemplary signals that may be input to the detector  70 . In FIG. 4, the detector  70  is comprised of first, second, third, and fourth logic circuits  72 - 75 , respectively, which may be D-type flip-flops. The first and second logic circuits  72 ,  73 , respectively, operate together to form a first monitor  82 ; the second and third logic circuits  74 ,  75 , respectively, operate together to form a second monitor  84 . A first logic gate  77  is responsive to the first monitor  82  while a second logic gate  79  is responsive to the second monitor  84 . A third logic gate  80  is responsive to the first logic gate  77  and the second logic gate  79 . 
     If the delay-locked loop of the synchronous clock generator circuit  38  is locked, and the delay line  40  is passing signal, a signal at the input of the delay line  40  (the CCLK signal shown in FIG. 5A) will have the same frequency as a signal at the output of the delay line  40  (the 180° signal shown in FIG.  5 D). Sampling the 180° signal of FIG. 5D by clocking the flip-flop  72  with both edges of the input clock signal CCLK and clocking the flip-flop  73  with both edges of the inverse of the input clock signal CCLK will produce opposite logic levels at the Q output terminals of the flip-flops  72 ,  73 . Gating the signal available at the Q output terminal of the flip-flop  72  and the signal available at the {overscore (Q)} output terminal of flip-flop  73  with the logic gate  77  yields an output signal having a low logic level whenever the correct predetermined phase relationship exists between the signals CCLK and 180°. If the signals available at the Q output terminals of the flip-flops  72 ,  73  ever have the same value, the signal at the D inputs is not changing state indicating that the delay line  40  is not passing a signal. When the signals at the Q output terminals have the same value, the output signal will change to a high logic state and propagate through gate  80 . 
     The clock signal CCLK of FIG. 5A is shown as having an arbitrary phase relationship with the signal shown in FIG. 5B due to internal propagation delays, clock driver delays, etc. Race conditions may give a false indication. The present invention addresses that problem by adding the D-type flip-flops  74 ,  75 . The flip-flops  74 ,  75  operate in a way which is identical to the manner in which flip-flops  72 ,  73  operate, except that a signal in quadrature (see FIG. 5C) with the one sampled by the flip-flops  72 ,  73  is sampled. Under locked conditions, one or both of the gates  77 ,  79  will indicate signal present. Only if signal actually ceases to transition at the clock frequencies will no signal be indicated. The signals may then be gated as shown through the logic gate  80  to produce the output signal. 
     Those of ordinary skill in the art will recognize that signals other than those shown in FIGS. 5C and 5D may be used. The signal that is sampled by the first pair of flip-flops need not be the 180° signal. The signal chosen should have a predetermined relationship with the clock signal CCLK such that the signals output by the flip-flops are as set forth above, or some other known relationship dependent upon the logic circuits and logic gates chosen. Although a quadrature relationship is desirable, it is not necessary as long as the signals have a known phase relationship that prevents a race condition from developing at both flip-flops at the same time. Furthermore, the “second signal” could be a time delayed version of the first signal. 
     FIG. 6 illustrates the use of the output signal FQH* to ultimately control the charge pump  67 . In FIG. 6, under normal operation conditions, a phase detector component  60  produces a signal at either the up terminal or the down terminal. The signal available at the up terminal propagates through an AND gate  81  to operate a switch  82  which connects an output terminal  83  to a constant current source  84  of current I. The down signal propagates through an AND gate  85  and an OR gate  86  to operate a switch  87  which connects the output terminal  83  to a constant current signal  88  of the same current I. During normal operation, the signal FQH* is low. AND gates  81  and  85  are enabled by virtue of an inverter  89 , thereby allowing the up and down signals to propagate therethrough. However, upon assertion of the FQH* signal, the inverter  89  causes the signal input to the AND gates  81  and  85  to be low thereby preventing the up and down signals from propagating therethrough. The FQH* signal also propagates through the OR gate  86  to operate the switch  87 . In that manner, the FQH* signal can override the normal up/down signals produced by the phase detector component  60  to connect the output terminal  83  to the constant current sink  88 . 
     FIG. 7 is a block diagram of a computer system  90 . The computer system  90  utilizes a memory controller  92  in communication with SDRAMs  94  through a bus  95 . The memory controller  92  is also in communication with a processor  96  through a bus  97 . The processor  96  can perform a plurality of functions based on information and data stored in the SDRAMs  94 . One or more input devices  98 , such as a keypad or a mouse, are connected to the processor  96  to allow an operator to manually input data, instructions, etc. One or more output devices  99  are provided to display or otherwise output data generated by the processor  96 . Examples of output devices include printers and video display units. One or more data storage devices  100  may be coupled to the processor  96  to store data on, or retrieve information from, external storage media. Examples of storage devices  100  and storage media include drives that accept hard and floppy disks, tape cassettes, and CD read only memories. 
     The present invention is also directed to a method of monitoring a delay-locked loop to determine loss of signal. The method is comprised of the steps of sampling a first signal output from the delay-locked loop with a clock signal. The first signal is also sampled with the inverse of the clock signal. A second signal, either output from the delay-locked loop or a delayed version of the first signal, is sampled with the clock signal. The second signal is also sampled with the inverse of the clock signal. An output signal is produced when the samples of the first signal do not satisfy a predetermined relationship and when the samples of the second signal do not satisfy a predetermined relationship. In a preferred embodiment, the samples of the first signal should have opposite values and the samples of the second signal should have opposite values. Should samples of the first signal have the same value and should samples of the second signal have the same value, then the output signal is produced. 
     While the present invention has been described in conjunction with preferred embodiments thereof, many modifications and variations will be apparent to those of ordinary skill in the art. The foregoing description and the following claims are intended to cover all such modifications and variations.

Technology Category: 5