Patent Document

CROSS-REFERENCE 
     The present invention is a continuation-in-part of U.S. patent application Ser. No. 11/744,908, entitled “Thin Active Layer Fishbone Photodiode and Method of Manufacturing the Same”, filed on May 7, 2007. The present invention also relies on each of the following provisional applications for priority: 61/096,877 filed on Sep. 15, 2008, 61/099,768 filed on Sep. 24, 2008, and 61/159,732 filed on Mar. 12, 2009. All of the aforementioned applications are hereby incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a photodiode array having improved device characteristics. Specifically, the present invention relates to a photodiode device having a fishbone structure that can be fabricated on a thin active layer, such as epi or a thin direct-bonded layer. More specifically, the present invention relates to a photodiode array that has reduced junction capacitance, reduced dark current, and an improved signal-to-noise ratio. 
     BACKGROUND OF THE INVENTION 
     Conventional computed tomography (CT) scanners and digital radiography systems use large numbers of X-ray detectors, on the order of several hundred to several thousand, in which each X-ray detector includes a scintillator to convert X-rays into light and a photocell, or photodiode array, to convert light into an electrical signal. 
     Certain photodiodes have two-electrode radiation-sensitive junctions formed in semiconductor material. Light, which illuminates the junction, creates charge carriers (via mobile or “free” electrons and holes). Doping a semiconductor with a small amount of impurity greatly increases the number of charge carriers within the semiconductor. When a doped semiconductor has excess (majority) holes, it is called p-type and when it contains excess (majority) free electrons, it is known as n-type. The holes in a p-dopes semiconductor are majority carriers while the electrons are minority carriers. In the case of n-type doping, the electrons are the majority carriers and the holes are the minority carriers. The junctions which form where n-type and p-type semiconductors join together are called P-N junctions. At the P-N junction, there forms a region called the depletion zone, which blocks current conduction from the n-type region to the p-type region, but allows current to conduct from the p-type region to the n-type region. The depletion region is void of all majority carriers and is a non-conducting layer. In other words, the recombination of holes and electrons at the P-N junction causes the region to become depleted of mobile charge. 
     The depletion region forms across the P-N junction when the junction is in thermal equilibrium, i.e. things are in a steady state. Electrons and holes will diffuse into regions with lower concentrations of electrons and holes. N-type semiconductors have an excess of free electrons while P-type semiconductors have an excess of holes. Therefore, when a P-N junction is formed, electrons will diffuse into the P side and holes will diffuse into the N side. When a hole and an electron come into contact, however, they eliminate each other through recombination. This bares the donor atoms adjacent to the depletion region, which are now charged ions. The ions are positive on the N side and negative on the P side, creating an electric field that counteracts the continued diffusion of charge carriers. When the electric field is sufficient to repel incoming holes and electrons, the depletion region reaches its equilibrium width. 
     Under reverse bias (P negative with respect to N) this potential is increased, further widening the depletion zone. Forward bias (P positive with respect to N) narrows the zone and eventually reduces it to nothing, making the junction conductive and allowing free flow of charge carriers. Thus, it is possible to manipulate the non-conductive layer to allow a flow of electricity in one direction but not the other (opposite) direction. When the P-N junction is forward-biased, electric charge flows freely due to reduced resistance of the P-N junction. When the P-N junction is reverse biased, however, the junction barrier (and therefore resistance) becomes greater and charge flow is minimal. 
     Essentially active solid-state semiconductor devices, and in particular, silicon photodiodes, are among the most popular photodetectors having a sufficiently high performance over a large wavelength range with ease of use. Silicon photodiodes are sensitive to light in the wide spectral range, extending from deep ultraviolet through visible to near infrared, which is approximately 200 nm to 1100 nm. Silicon photodiodes, by using their ability to detect the presence or absence of minute light intensities, facilitate the extremely precise measurement of these minute light intensities upon appropriate calibration. For example, appropriately calibrated silicon photodiodes detect and measure light intensities varying over a wide range, from very minute light intensities of below 10 −13  watts/cm 2  to high intensities above 10 −3  watts/cm 2 . 
     Silicon photodiodes can be employed in an assortment of applications including, but not limited to, spectroscopy, distance and speed measurement, laser ranging, laser guided missiles, laser alignment and control systems, optical free air communication, optical radar, radiation detection, optical position encoding, film processing, flame monitoring, scintillator read out, environmental applications such as spectral monitoring of earth ozone layer and pollution monitoring, low light-level imaging, such as night photography, nuclear medical imaging, photon medical imaging, and multi-slice computer tomography (CT) imaging, security screening and threat detection, thin photochip applications, and a wide range of computing applications. 
     Typically, photodiode arrays employ a scintillator material for absorbing high energy (ionizing) electromagnetic or charged particle radiation, which, in response, fluoresces photons at a characteristic wavelength. Scintillators are defined by their light output (number of emitted photons per unit absorbed energy) short fluorescence decay times, and optical transparency at wavelengths of their own specific emission energy. The lower the decay time of a scintillator, that is, the shorter the duration of its flashes of fluorescence are, the less so-called “dead time” the detector will have and the more ionizing events per unit of time it will be able to detect. Scintillators are used to detect electromagnetic waves or particles in many security and detection systems, including CT, X-ray, and gamma ray. There, a scintillator converts the energy to light of a wavelength which can be detected by photomultiplier tubes (PMTs) or P-N junction photodiodes. 
     Photodiodes are typically characterized by certain parameters, such as, among others, electrical characteristics, optical characteristics, current characteristics, voltage characteristics, and noise. Electrical characteristics predominantly comprise shunt resistance, series resistance, junction capacitance, rise or fall time and/or frequency response. Optical characteristics comprise responsivity, quantum efficiency, non-uniformity, and/or non-linearity. Photodiode noise may comprise, among others, thermal noise, quantum, photon or shot noise, and/or flicker noise. 
     In an effort to increase the signal to noise ratio and enhance the contrast of the signal, it is desirable to increase the light-induced current of photodiodes. Thus, photodiode sensitivity is enhanced while the overall quality of the photodiode is improved. Photodiode sensitivity is crucial in low-level light applications and is typically quantified by a parameter referred to as noise equivalent power (NEP), which is defined as the optical power that produces a signal-to-noise ratio of one at the detector output. NEP is usually specified at a given wavelength over a frequency bandwidth. 
     Photodiodes absorb photons or charged particles, facilitating detection of incident light or optical power and generating current proportional to the incident light, thus converting the incident light to electrical power. Light-induced current of the photodiode corresponds to the signal while “dark” or “leakage” current represents noise. “Dark” current is that current that is not induced by light, or that is present in the absence of light. Photodiodes process signals by using the magnitude of the signal-to-noise ratio. 
     Leakage current is a major source of signal offset and noise in current photodiode array applications. Leakage current flows through the photodiode when it is in a “dark” state, or in the absence of light at a given reverse bias voltage applied across the junction. Leakage current is specified at a particular value of reverse applied voltage. Leakage current is temperature dependent; thus, an increase in temperature and reverse bias results in an increase in leakage or dark current. A general rule is that the dark current will approximately double for every 10° C. increase in ambient temperature. It should be noted, however, that specific diode types can vary considerably from this relationship. For example, it is possible that leakage or dark current will approximately double for every 6° C. increase in temperature. 
     Various approaches have been used in the prior art to reduce, eliminate or control leakage current. For example, U.S. Pat. No. 4,904,861, assigned to Agilent Technologies, Inc., discloses “[an] optical encoder comprising: a plurality of active photodiodes in an array on a semiconductor chip; a code member having alternating areas for alternately illuminating and not illuminating the active photodiodes in response to movement of the code member; means connected to the active photodiodes for measuring current from the active photodiodes; and sufficient inactive photodiode area on the semiconductor chip at each end of the array of active photodiodes to make the leakage current to each end active photodiode of the array substantially equal to the leakage current to an active photodiode remote from an end of the array”. Similarly, U.S. Pat. No. 4,998,013, also assigned to Agilent Technologies, Inc. discloses “means for shielding a photodiode from leakage current comprising: at least one active photodiode on a semiconductor chip; means for measuring current from the active photodiode; a shielding area having a photodiode junction substantially surrounding the active photodiode; and means for biasing the shielding area photodiode junction with either zero bias or reverse bias.” 
     U.S. Pat. No. 6,670,258, assigned to Digirad Corporation, discloses “[a] method of fabricating a low-leakage current photodiode array comprising: defining frontside structures for a photodiode on a front side of a substrate; forming a heavily-doped gettering layer on a back surface of the substrate; carrying out a gettering process on the substrate to transport undesired components from the substrate to said gettering layer, and to form another layer in addition to said gettering layer, which is a heavily-doped, conductive, crystalline layer within the substrate; after said gettering process, removing the entire gettering layer; and after said removing, thinning the heavily-doped, conductive, crystalline layer within the substrate to create a native optically transparent, conductive bias electrode layer”. Similarly, U.S. Pat. No. 6,734,416, also assigned to Digirad Corporation, discloses “[a] low-leakage current photodiode array comprising: a substrate having a front side and a back side; a plurality of gate regions formed near the front side of the substrate; a backside layer formed within the substrate, near the back side of the substrate, the backside layer having a thickness of approximately 0.25 to 1.0 micrometers and having a sheet resistivity of approximately 50 to 1000 Ohm per square.” 
     U.S. Pat. No. 6,569,700, assigned to United Microelectronics Corporation in Taiwan, discloses “[a] method of reducing leakage current of a photodiode on a semiconductor wafer, the surface of the semiconductor wafer comprising a p-type substrate, a photosensing area for forming a photosensor of the photodiode, and a shallow trench positioned in the substrate surrounding the photosensing area, the method comprising: forming a doped polysilicon layer containing p-type dopants in the shallow trench; using a thermal process to cause the p-type dopants in the doped polysilicon layer to diffuse into portions of the p-type substrate that surround a bottom of the shallow trench and walls of the shallow trench; removing the doped polysilicon layer; filling an insulator into the shallow trench to form a shallow trench isolation (STI) structure; performing a first ion implantation process to form a first n-type doped region in the photosensing area; and performing a second ion implantation process to form a second n-type doped region in the photosensing area.” 
     Also, U.S. Pat. No. 6,504,158, assigned to General Electric Company, discloses “a method of reducing leakage current in an imaging apparatus, including: providing a substrate with at least one radiation-sensitive imaging region therein; forming a guard region in the substrate at or immediately adjacent a cut edge of the substrate to reduce leakage current reaching the at least one radiation-sensitive imaging region from the cut edge when the imaging apparatus is in use; and electrically reverse biasing the at least one radiation-sensitive imaging region and the guard region relative to the substrate.” 
     In certain applications, it is desirable to produce optical detectors having small lateral dimensions and spaced closely together. For example in certain medical applications, it is desirable to increase the optical resolution of a detector array in order to permit for improved image scans, such as computed tomography (CT) scans. However, at conventional doping levels utilized for diode arrays of this type, the diffusion length of minority carriers generated by photon interaction in the semiconductor is in the range of at least many tens of microns, and such minority carriers have the potential to affect signals at diodes away from the region at which the minority carriers were generated. 
     Thus, an additional disadvantage with conventional photodiode arrays is the amount and extent of crosstalk that occurs between adjacent detector structures, primarily as a result of minority carrier leakage current between diodes. The problem of crosstalk between diodes becomes even more acute as the size of the detector arrays, the size of individual detectors, the spatial resolution, and spacing of the diodes is reduced. 
     Various approaches have been used to minimize such crosstalk including, but not limited to, providing inactive photodiodes to balance the leakage current, as described in U.S. Pat. Nos. 4,904,861 and 4,998,013 to Epstein et al., the utilization of suction diodes for the removal of the slow diffusion currents to reduce the settling time of detectors to acceptable levels, as described in U.S. Pat. No. 5,408,122, and providing a gradient in doping density in the epitaxial layer, as described in U.S. Pat. No. 5,430,321 to Effelsberg. 
     In addition to leakage current and effects of crosstalk, noise is often a limiting factor for the performance of any device or system. In almost every area of measurement, the limit to the detectability of signals is set by noise, or unwanted signals that obscure the desired signal. As described above, the NEP is used to quantify detector noise. Noise issues generally have an important effect on device or system cost. Conventional photodiodes are particularly sensitive to noise issues. Like other types of light sensors, the lower limits of light detection for photodiodes are determined by the noise characteristics of the device. 
     As described above, the typical noise components in photodiodes include thermal noise; quantum or shot noise; and flicker noise. These noise components collectively contribute to the total noise in the photodiode. Thermal noise, or Johnson noise, is inversely related to the value of the shunt resistance of photodiode and tends to be the dominant noise component when the diode is operated under zero applied reverse bias conditions. Shot noise is dependent upon the leakage or dark current of photodiode and is generated by random fluctuations of current flowing through the device, which may be either dark current or photocurrent. Shot noise tends to dominate when the photodiode is used in photoconductive mode where an external reverse bias is applied across the device. As an example, detector noise generated by a planar diffused photodiode operating in the reverse bias mode is a combination of both shot noise and thermal noise. Flicker noise, unlike thermal or shot noise, bears an inverse relationship to spectral density. Flicker noise may dominate when the bandwidth of interest contains frequencies less than 1 kHz. 
     Secondary issues also contribute to dark noise and other noise sources that impact photodiode sensitivity. These include primarily determination and/or selection of apt active area specifications (geometry and dimensions), response speed, quantum efficiency at the wavelength of interest, response linearity, and spatial uniformity of response, among others. 
     In CT applications, such as those employed for baggage screening, it is desirable to have high density photodiode arrays with low dark current, low capacitance, high signal-to-noise ratio, high speed and low crosstalk. 
     As mentioned above, however, there are numerous problems with conventional photodiodes that attempt to achieve these competing and often conflicting characteristics. For example, in order to achieve low capacitance the photodiode can be fabricated on a high resistivity (on the order of 4000-6000 Ωcm) silicon material. Using a high resistivity material, however, causes the device to have high dark current. 
       FIG. 1  is a cross-sectional view of a conventional, prior art fishbone photodiode device  100 . The photodiode array  100  comprises substrate wafer  105 , which is a thick bulk wafer having an active area thickness on the order of 275-400 μm. As shown in  FIG. 1  on the conventional fishbone photodiode device some photogenerated holes  110  move randomly in various directions, such as paths  115 , in the thick active volume  106  of the bulk starting material wafer. Since minority carrier lifetime is limited, many of these photogenerated holes are lost due to recombination of holes and electrons in the bulk material, which causes a reduction in charge collection efficiency or responsivity of the photodiode. 
     In order to improve charge collection efficiency in this prior art fishbone photodiode device, the p+ diffused bones need to be placed relatively close to each other. This is disadvantageous, however, because a relatively large number of p+ fishbones is needed when placing the p+ diffused bones closer together, resulting in high junction capacitance. Typically, charge carriers that are photo-generated further from the P-N junction can diffuse toward the p+ diffused “bones” and be collected by the depletion region. 
     In addition, the fishbone photodiode device in the prior art as shown in  FIG. 1  is disadvantageous because the high volume, thick active layer  105  that is used to fabricate the photodiode results in high dark current, since dark current is proportional to the overall volume of the active layer of the device. 
     In addition, the conventional photodiode array described above with respect to  FIG. 1  is disadvantageous in that the photodiode tends to degrade in shunt resistance since the P-N junction is passivated by relatively thin antireflective layers, such as silicon oxide on the order of 150 Å and silicon nitride on the order of 425 Å. 
     The result is a fishbone photodiode having high noise characteristics, and thus, a poor signal to noise ratio. 
     What is needed is a photodiode array that can be fabricated on a thin active layer. In particular, what is needed is a photodiode array that can be fabricated on a thin active layer such as thin epi or thin direct-bonded layer, for fast rise time and better charge collection efficiency. 
     What is also needed is a photodiode array having reduced junction capacitance and reduced dark current, thus improving the signal to noise ratio of the photodiode array. 
     What is also needed is a photodiode array having reduced junction capacitance and reduced dark current, thus improving the signal to noise ratio of the photodiode array without sacrificing performance characteristics, such as quantum efficiency. 
     In addition, what is needed is economically, technically, and operationally feasible methods, apparatuses, and systems for manufacturing photodiode arrays on a thin active layer with reduced junction capacitance and reduced dark current effects. 
     In addition, what is needed is economically, technically, and operationally feasible methods, apparatuses, and systems for manufacturing photodiode arrays that can be used in computed tomography (CT) scanner applications that improve upon overall performance characteristics of the photodiode array and individual diode elements. 
     SUMMARY OF THE INVENTION 
     In one embodiment, the present invention is a photodiode device having a fishbone structure that can be fabricated on a thin active layer, such as epi or a thin direct-bonded layer and having improved device characteristics, including reduced junction capacitance, reduced dark current, and an improved signal-to-noise ratio. 
     In one embodiment, the present invention is a photodiode array comprising: a thin active layer substrate having at least a front side and a back side; a plurality of photodiodes integrally formed in the thin active layer substrate forming said array; a plurality of metal contacts provided on said front side and said back side, wherein the fabrication of said array comprises: coating said front side of said substrate with oxide via mask oxidation; masking said front side of said substrate with an n+ lithography mask; selectively etching the oxide coating on said front side of said thin active layer substrate using the n+ lithography mask and completely etching the oxide coating on the back side of the substrate; diffusing a n+ layer on said front side and said back side of said substrate forming a n+ region; performing a drive-in oxidation on said front side and said back side of said substrate; masking said front side of said substrate with a p+ lithography mask; selectively etching the oxide coating on said front side of said substrate wafer using the p+ lithography mask; diffusing a p+ layer on said front side of said substrate; applying a drive-in oxidation layer on said front side and said back side of said substrate; masking said front side of said substrate to form at least one active area etch pattern; selectively etching the oxide coating on said front side of said substrate using said active area etch pattern and etching the oxide coating on said back side of said substrate completely; applying at least one antireflective layer on said front side and said back side of said substrate; masking said front side of said substrate wafer using a contact window mask; selectively etching the front side of the substrate using said contact window mask to form at least one contact window and completely etching the at least one antireflective layer from the back side of the substrate; metallizing said front side and said back side of said substrate; and masking and selectively etching said front side of said substrate to form metal contacts. 
     In one embodiment, the thin active layer has a thickness of 15 μm. In one embodiment, an oxide layer is retained on at least a portion of the front side of the thin active layer to increase the structural rigidity of the device. Optionally, the photodiode of the present invention further comprises a mechanical support bonded to said back side of said thin active area layer substrate. In one embodiment, the mechanical support comprises n+ silicon substrate. 
     In one embodiment, the p+ mask pattern is a fishbone pattern. In one embodiment, the fishbone pattern p+ mask comprises a plurality of p+ bones further defined by a p+ periphery frame bone. In one embodiment, the distance between adjacent p+ bones in said fishbone pattern is 700 μm. 
     In one embodiment, the antireflective coating layer is a thin film material, wherein the thin film material is one of an oxide, a sulfide, a fluoride, a nitride, a selenide, or a metal. In one embodiment, the antireflective coating is a silicon dioxide antireflective having a thickness of 150 Å. In another embodiment, the antireflective coating is a silicon nitride antireflective having a thickness of 425 Å. 
     In another embodiment, the present invention is a photodiode array comprising: a thin active layer substrate having at least a front side and a back side; a mechanical support bonded to said back side of said thin active area substrate; a plurality of photodiodes integrally formed in the thin active layer substrate forming said array; a plurality of metal contacts provided on said front side and said back side, wherein the fabrication of said array comprises: coating said front side of said substrate with oxide via mask oxidation; masking said front side of said substrate with an n+ lithography mask; selectively etching the oxide coating on said front side of said thin active layer substrate using the n+ lithography mask and completely etching the oxide coating on the back side of the substrate; diffusing a n+ layer on said front side and said back side of said substrate forming a n+ region; performing a drive-in oxidation on said front side and said back side of said substrate; masking said front side of said substrate with a p+ lithography mask; selectively etching the oxide coating on said front side of said substrate wafer using the p+ lithography mask; diffusing a p+ layer on said front side of said substrate; applying a drive-in oxidation layer on said front side and said back side of said substrate; masking said front side of said substrate to form at least one active area etch pattern; selectively etching the oxide coating on said front side of said substrate using said active area etch pattern and etching the oxide coating on said back side of said substrate completely; applying at least one antireflective layer on said front side and said back side of said substrate; masking said front side of said substrate wafer using a contact window mask; selectively etching the front side of the substrate using said contact window mask to form at least one contact window and completely etching the at least one antireflective layer from the back side of the substrate; metallizing said front side and said back side of said substrate; and masking and selectively etching said front side of said substrate to form metal contacts. 
     In yet another embodiment, the present invention is a photodiode array comprising: a thin active area substrate having at least a front side and a back side; a plurality of diode elements integrally formed in the substrate forming said array, wherein each diode element has a p+ fishbone pattern on said front side, further comprising at least one p+ bone and a p+ bone frame periphery, and wherein each p+ bone is protected by a thick oxide layer, and a plurality of front surface cathode and anode contacts, wherein said protected p+ fishbone pattern substantially increases the structural integrity and reduces junction and leakage current between adjacent photodiodes. 
     In yet another embodiment, the present invention is a photodiode array comprising: a thin active area substrate having at least a front side and a back side; a mechanical support bonded to said back side of said thin active area substrate; a plurality of diode elements integrally formed in the substrate forming said array, wherein each diode element has a p+ fishbone pattern on said front side, further comprising at least one p+ bone and a p+ bone frame periphery, and wherein each p+ bone is protected by a thick oxide layer, and a plurality of front surface cathode and anode contacts, wherein said protected p+ fishbone pattern substantially increases the structural integrity and reduces junction and leakage current between adjacent photodiodes. 
     In another embodiment, the present invention is a photodiode element and photodiode array comprising a shallow n+ layer between adjacent p+ bones. 
     In still another embodiment, the present invention is a photodiode element and photodiode array comprising a three p+ bones layout design for each photodiode element. 
     In another embodiment, the present invention is a photodiode element and photodiode array comprising a four p+ bones layout design for each photodiode element. 
     In still another embodiment, the present invention is a photodiode element and photodiode array comprising a five p+ bones layout design for each photodiode element. 
     In still another embodiment, the present invention is a photodiode element and photodiode array comprising a six p+ bones layout design for each photodiode element. 
     In still another embodiment, the present invention is a photodiode element and photodiode array comprising a seven p+ bones layout design for each photodiode element. 
     In still another embodiment, the present invention is a photodiode element and photodiode array comprising an eight p+ bones layout design for each photodiode element. 
     In another embodiment, the present invention is a photodiode element and photodiode array comprising a plurality of p+ bones wherein only the last vertical fishbone of each photodiode element has metal contact bars and that are connected to wire bonding pads. 
     In another embodiment, the present invention is a photodiode element and photodiode array comprising a plurality of p+ bones wherein all fishbones of each photodiode element comprise metal contact bars and that are connected to wire bonding pads. 
     In one embodiment, the present invention is directed toward a photodiode array comprising: a) a thin active layer substrate having at least a front side and a back side; b) a plurality of photodiodes integrally formed in the thin active layer substrate forming said array; c) a plurality of metal contacts provided on said front side, wherein the fabrication of said array comprises: coating said front side and said back side of said substrate with an oxide layer via mask oxidation; coating said front side of said substrate with a photoresist layer; masking said front side of said substrate with a p+ lithography mask; selectively etching the oxide layer on said front side said substrate wafer, wherein the p+ lithography mask is used to reveal p+ diffusion regions on said front side and etching the oxide coating on said back side of said substrate completely; diffusing a p+ layer on said front side of said substrate forming p+ diffusion regions; applying a drive-in oxidation layer on said front side of said substrate; coating said front side of said substrate with a photoresist layer; masking said front side of said substrate with a n+ lithography mask to form at least one active area etch pattern; selectively etching the photoresist layer on said front side of said substrate using said active area etch pattern to reveal n+ diffusion regions on said front side; diffusing a n+ layer on said front side of said substrate forming shallow n+ regions between adjacent p+ regions; performing a drive-in oxidation on said front side of said substrate; coating at least one exposed surface on said front side of said substrate with an oxide layer; coating said front side of said substrate with a silicon nitride layer; coating said front side of said substrate with a photoresist layer; masking said front side of said substrate wafer using a contact window mask; selectively etching the front side of the substrate using said contact window mask to form at least one contact window; metallizing said front side and said back side of said substrate; coating said front side of said substrate with a photoresist layer; and masking and selectively etching said front side of said substrate to form metal contacts. 
     Optionally, the thin active layer has a thickness of 15 μm. The p+ mask pattern is a fishbone pattern. The fishbone pattern p+ mask comprises a plurality of p+ bones further defined by a p+ periphery frame bone. The distance between adjacent p+ bones in said fishbone pattern is 700 μm. The shallow n+ layer has a depth of 0.3 μm. The antireflective coating layer is a thin film material. The thin film material is one of an oxide, a sulfide, a fluoride, a nitride, a selenide, or a metal. The antireflective coating is a silicon dioxide antireflective having a thickness of 150 Å. The antireflective coating is a silicon nitride antireflective having a thickness of 425 Å. The oxide layer is retained on at least a portion of the front side of the thin active layer to increase the structural rigidity of the device. The array further comprising a mechanical support bonded to said back side of said thin active area layer substrate. The mechanical support comprises n+ silicon substrate. 
     In another embodiment, the photodiode array comprises a) a thin active area substrate having at least a front side and a back side; b) a plurality of diode elements integrally formed in the substrate forming said array, wherein each diode element has a p+ fishbone pattern on said front side, further comprising at least two p+ bones, a p+ bone frame periphery, and at least one shallow n+ region between adjacent p+ regions and wherein each p+ bone is protected by a thick oxide layer, and c) a plurality of front surface cathode and anode contacts, wherein said at least one shallow n+ region increases the stability of the diode element relative to a diode element without said shallow n+ region. 
     It should be appreciated that, with respect to the p+ fishbone pattern, in conventional photodiodes a p+ bone is passivated by a relatively thin oxide layer, in the range of about 2700 A. In the present invention, the p+ bone is passivated by about 1 um thick oxide layer plus a 450 A thick silicon nitride layer, thereby providing a better passivation of the p+n junction. This results in a device with a low dark current, such as 4 pA to 6 pA @−10 mV for a 25 mm 2  active area and remains more stable than conventional photodiodes after assembly, as noted by the data herein. 
     Additionally, it should be appreciated that in the surface areas between the two adjacent p+ bones, there is an anti-reflective layer made of a 300 A oxide layer plus a 450 A nitride layer. Positive charges in the oxide layer will increase the minority carrier (holes) recombination velocity at the Si—SiO2 interface, thereby resulting in a reduction in charge collection efficiency. The benefit of having a shallow n+ layer between the two p+ bones is that the high-low N+-N junction will reflect the minority carriers, thereby preventing them from reaching the Si—SiO2 interface. Thus, the charges in the SiO2 have no influence on the photo generated minority carriers, and the presence of the shallow N+ layer will make the device more rugged and stable relative to a device without the shallow n+ layer. 
     Optionally, the thin active layer has a thickness of 15 μm. The p+ mask pattern is a fishbone pattern. The array further comprises a mechanical support bonded to said back side of said thin active area layer substrate. 
     In another embodiment, the photodiode array comprises a thin active area substrate having at least a front side and a back side; a mechanical support bonded to said back side of said thin active area substrate; a plurality of diode elements integrally formed in the substrate forming said array, wherein each diode element has a p+ fishbone pattern on said front side, further comprising at least two p+ bones, a p+ bone frame periphery, and at least one shallow n+ region between adjacent p+ regions and wherein each p+ bone is protected by a thick oxide layer, and a plurality of front surface cathode and anode contacts, wherein said at least one shallow n+ region increases the stability of the diode element relative to a diode element without said shallow n+ region. The thin active layer has a thickness of 15 μm. The p+ mask pattern is a fishbone pattern. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features and advantages of the present invention will be appreciated, as they become better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
         FIG. 1  is a cross-sectional view of a conventional fishbone photodiode device; 
         FIG. 2  is a top view of one embodiment of a photodiode fabricated in accordance with the present invention; 
         FIG. 3A  represents a cross-sectional view of an embodiment of the fishbone photodiode fabricated in accordance with the present invention; 
         FIG. 3B  represents a cross-sectional view of an embodiment of the fishbone photodiode fabricated in accordance with the present invention; 
         FIG. 3C  represents a cross-sectional view of an embodiment of the fishbone photodiode fabricated in accordance with the present invention; 
         FIG. 4A  depicts a cross-sectional, planar view of a manufacturing step for fabricating the fishbone photodiode of the present invention, shown in  FIG. 3A ; 
         FIG. 4B  depicts a cross-sectional, planar view of a manufacturing step for fabricating the fishbone photodiode of the present invention, shown in  FIG. 3A ; 
         FIG. 4C  depicts a cross-sectional, planar view of a manufacturing step for fabricating the fishbone photodiode of the present invention, shown in  FIG. 3A ; 
         FIG. 4D  depicts a cross-sectional, planar view of a manufacturing step for fabricating the fishbone photodiode of the present invention, shown in  FIG. 3A ; 
         FIG. 4E  depicts a cross-sectional, planar view of a manufacturing step for fabricating the fishbone photodiode of the present invention, shown in  FIG. 3A ; 
         FIG. 4F  depicts a cross-sectional, planar view of a manufacturing step for fabricating the fishbone photodiode of the present invention, shown in  FIG. 3A ; 
         FIG. 4G  depicts a cross-sectional, planar view of a manufacturing step for fabricating the fishbone photodiode of the present invention, shown in  FIG. 3A ; 
         FIG. 4H  depicts a cross-sectional, planar view of a manufacturing step for fabricating the fishbone photodiode of the present invention, shown in  FIG. 3A ; 
         FIG. 4I  depicts a cross-sectional, planar view of a manufacturing step for fabricating the fishbone photodiode of the present invention, shown in  FIG. 3A ; 
         FIG. 5A  depicts an exemplary embodiment of an n+ mask used during manufacturing the fishbone photodiode of the present invention; 
         FIG. 5B  depicts an exemplary embodiment of a p+ mask used during manufacturing the fishbone photodiode of the present invention; 
         FIG. 5C  depicts an exemplary embodiment of an active area mask used during manufacturing the fishbone photodiode of the present invention; 
         FIG. 5D  depicts an exemplary embodiment of a contact mask used during manufacturing the fishbone photodiode of the present invention; 
         FIG. 5E  depicts an exemplary embodiment of a metal mask used during manufacturing the fishbone photodiode of the present invention; 
         FIG. 6A  represents a front-side view of one embodiment of the fishbone photodiode array of the present invention, wherein each photodiode element comprises a three p+ bone layout; 
         FIG. 6B  represents a front-side view of one embodiment of the fishbone photodiode array of the present invention, wherein each photodiode element comprises a four p+ bone layout; 
         FIG. 6C  represents a front-side view of one embodiment of the fishbone photodiode array of the present invention, wherein each photodiode element comprises a five p+ bone layout; 
         FIG. 6D  represents a front-side view of one embodiment of the fishbone photodiode array of the present invention, wherein each photodiode element comprises a six p+ bone layout; 
         FIG. 6E  represents a front-side view of one embodiment of the fishbone photodiode array of the present invention, wherein each photodiode element comprises an eight p+ bone layout; 
         FIG. 7  is a table depicting example performance characteristics for each of the three, four, five, six and eight bone layout design arrays of  FIGS. 6A through 6E  at a particular bias voltage; 
         FIG. 8  is another table depicting example performance characteristics for each of the three, four, five, six and eight bones layout design arrays of  FIGS. 6A through 6E  at three different bias voltages; 
         FIG. 9A  is a cross-sectional view of an embodiment of the fishbone photodiode fabricated in accordance with the present invention and that additionally uses a shallow n+ layer between adjacent p+ bones; 
         FIG. 9B  represent a front-side view of an embodiment of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10A  is an illustration of the starting material used in fabricating the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10B  is a depiction of  FIG. 10A , after a mask oxidation step, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10C  is an illustration of  FIG. 10B , after a p+ lithography step, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10D  is an illustration of  FIG. 10C , after a p+ masking step, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones 
         FIG. 10E  is a depiction of  FIG. 10D , after a p+ diffusion and drive-in oxidation step, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10F  is an illustration of  FIG. 10E , after a photoresist layer is applied, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10G  is an illustration of  FIG. 10F , after a n+ masking step, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10H  is an illustration of  FIG. 10G , after a doping and drive-in oxidation step, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10I  is an illustration of  FIG. 10H , after coating with silicon nitride and photoresist, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10J  is a depiction of  FIG. 10I , after a contact lithography step, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10K  is an illustration of  FIG. 10J , after a metal deposition step, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 10L  is an illustration of  FIG. 10K , after a metal mask lithography and selective etching, in one embodiment of the manufacture of the fishbone photodiode array of the present invention, where shallow n+ layers are formed between adjacent p+ bones; 
         FIG. 11  represents a front-side view of one embodiment of the fishbone photodiode array of the present invention, wherein metal contact bars are placed only in the last vertical fishbone of each of the photodiode elements; and 
         FIG. 12  represents a front-side view of one embodiment of the fishbone photodiode array of the present invention, wherein metal contact bars are placed at each of the fishbone of each of the photodiode elements. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is directed towards a photodiode array having a fishbone design that can be fabricated on a material having intermediate resistivity, such as, but not limited to 1000 Ωcm. Such devices are commonly used in CT and X-ray applications. In particular, the present invention is directed towards a fishbone structure photodiode, comprising p+ diffused areas that are small and narrow, resembling fingers or fishbones. Since the p+ diffused areas are reduced, the capacitance of the resultant photodiode is less than the capacitance of a standard diffused photodiode where the full active area is diffused. 
     The photodiode array of the present invention thus overcomes the disadvantages of the conventional photodiodes described above by placing the p+ fishbones at a greater distance from each other, thus necessitating the use of fewer p+ fishbones, reducing the overall junction capacitance. In addition, a thin active layer is employed, reducing leakage or “dark” current, since dark current is proportional to the overall volume of the active layer. In addition, the present invention uses a photomask that serves to provide a thick oxide region or layer on top of the P-N junction prior to the growth/deposition of the relatively thin AR layers. Since the junctions are passivated with a thick oxide layer, the device has more structural rigidity and integrity and is less prone to junction degradation. In another embodiment of the present invention, the thin active layer is placed on a mechanical support for added strength and durability. 
     Thus, the present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. In particular, the present invention is directed toward a fishbone photodiode device that can be fabricated on a thin wafer active area, thus reducing leakage or “dark” current. The present invention is also directed toward a fishbone photodiode device that has reduced junction capacitance owing to the distance between adjacent p+ fishbones, and the relative number of p+ fishbones used to fabricate the device. Because of the reduced dark current and reduced junction capacitance, the overall signal-to-noise ratio of the photodiode array is improved. In addition, the photodiode of the present invention has faster rise times and better charge collection efficiency. 
     The present invention is also directed towards a photodiode array having reduced junction capacitance and reduced dark current, thus improving the signal to noise ratio of the photodiode array without sacrificing performance characteristics, such as quantum efficiency. 
     In one embodiment, the present invention is directed toward a fishbone photodiode device that can be fabricated on a thin active layer and that additionally has a thick oxide region on top of the P-N junction prior to the growth/deposition of the relatively thin AR layers, further lending structural integrity to the photodiode device. 
     The present invention is also directed toward a photodiode array that can be used in computed tomography (CT) scanner applications that improve upon overall performance characteristics of the photodiode array and individual diode elements. 
     While reference may be made to specific embodiments, such as the use of the photodiode array in CT scanning applications, it should be understood to those of ordinary skill in the art that a photodiode array as described herein may be used in any type of imaging application, including, but not limited to mobile and/or cargo screening systems, people screening systems, and the like. 
     Reference will now be made to specific embodiments of the present invention. The embodiment described herein is not a general disavowal of any one specific embodiment or used to limit the claims beyond the meaning of the terms used therein. In addition, various modifications to the described embodiment(s) will be readily apparent to those of ordinary skill in the art and the disclosure set forth herein may be applicable to other embodiments and applications without departing from the spirit and scope of the present invention. 
       FIG. 2  is a top surface view of one embodiment of a photodiode  200  fabricated in accordance with the present invention. As shown in  FIG. 2 , a p+ mask is employed to create and form a p+ fishbone pattern, comprising p+ bones  205  further defined by a periphery frame bone  210 . 
     Unlike conventional fishbone devices, the present invention employs a wider gap between adjacent p+ diffusion bones. In one embodiment, the gap or distance between adjacent p+ bones  205  is 700 μm. The distance from the center of one p+ diffusion bone to the center of an adjacent p+ diffusion bone is referred to as the “pitch”. In one embodiment, the pitch is 714 μm. 
     Fishbone photodiode  200  further comprises active area  215 , contact windows  218 , and metallized areas  220 , which are described in further detail below with respect to the fabrication steps. In one embodiment, the overall starting material active area  215  is 5 mm×5 mm. 
     It should be noted herein that typically, the active area in a detector is either of a round or square shape. There is no restriction on the shape of these active areas, however. Many applications may require triangular, radial, or trapezoidal shapes. Conventional photodiodes are manufactured via standard wafer fabrication techniques involving methods of masking and photoetching; thus, it is relatively simple to create a unique geometry. The geometric size and shape of the active area can be held to tolerances of 2 microns. As described herein, the term “region” is used interchangeably with the term “area” and refers to discrete portions within the photodiode chip. 
     The fabrication of the photodiode described with respect to  FIG. 2  will be described in greater detail with respect to the manufacturing steps shown  FIGS. 4A-4I  and the individual mask elements, as shown in  FIGS. 5A-5E . 
       FIGS. 3A ,  3 B, and  3 C represent cross-sectional views of various embodiments of the fishbone photodiode fabricated in accordance with the present invention. Now referring to  FIG. 3A , in one embodiment, the photodiode array  300  of the present invention is fabricated on thin active layer  305 . In one embodiment, thin active layer  305  has a thickness of 15 μm. The thin active layer results in a decrease in the leakage or dark current of the device, because the dark current is proportional to the volume of the active layer of the device. As shown in FIG.  3 A, quantum efficiency is retained because photo-generated holes  320  need move only a short distance or path  325  before getting collected by depletion region  330 . In one embodiment, depletion region  330  has a surface width of 5 μm. 
     In one embodiment, the photodiode array of the present invention comprises a p+ fishbone pattern, wherein adjacent p+ fishbones  310  are placed at a wide distance from each other, necessitating the use of fewer fishbones than the conventional fishbone photodiode array described above. In one embodiment, the distance between adjacent fishbones  310  is 700 μm. In one embodiment, the distance between the centers of two adjacent fishbones  310 , or pitch, is 714 μm. 
     In another embodiment, the fishbone photodiode of the present invention is fabricated with a thick oxide region  315  on top of each of the P-N junctions prior to the growth/deposition of the relatively thin anti-reflective (AR) layers  341 ,  342 . In one embodiment, thick oxide regions  315  comprise approximately 8000 Å of silicon oxide and approximately 425 A of silicon nitride. In one embodiment, the thick oxide regions or layer  315  comprises three sections  315   a ,  315   b , and  315   c . Sections  315   a  and  315   b  comprise the end sections of thick oxide regions or layer  315  and have a width of 20 μm. Section  315   c  is the middle section of thick oxide regions  315 , directly on top of the p+ fishbone, and, in one embodiment, is thinner than end sections  315   a  and  315   b . Since the P-N junctions are passivated with the thick oxide regions  315 , the device has more structural rigidity and integrity and is less prone to junction degradation. 
     In one embodiment of the photodiode array of the present invention, AR layer  341  comprises silicon oxide and has a thickness of 150 Å. In one embodiment, AR layer  342  comprises silicon nitride and has a thickness of 425 Å. 
     Now referring to  FIG. 3B , in one embodiment, the present invention is a fishbone photodiode device that can be fabricated on a thin active layer  305 , wherein the thin active layer  305  is placed on a mechanical support  335  for added strength and durability. In one embodiment, mechanical support  335  comprises CZ silicon, FZ silicon, quartz, or any other similar mechanical support material that does not affect device performance characteristics. In one embodiment, the mechanical support  335  has a thickness of 250 μm. In one embodiment, and now referring to  FIG. 3C , the mechanical support  335  is n+ silicon substrate. 
       FIGS. 4A through 4I  depict side planar views of manufacturing steps for fabricating the fishbone photodiode  400  of the present invention, as shown in  FIG. 3C , where a n+ silicon substrate mechanical support is employed. It should be understood to those of ordinary skill in the art that while the method of manufacturing the fishbone photodiode of the present invention is described with respect to the use of the mechanical support, the mechanical support is optional and the manufacturing steps can be employed without the support. 
     Modifications or alterations to the manufacturing steps, their corresponding details, and any order presented may be readily apparent to those of ordinary skill in the art. Thus, the present invention contemplates many possibilities for manufacturing the photodiode array of the present invention and is not limited to the examples provided herein. 
     Referring now to  FIG. 4A , the starting material for fabricating photodiode  400  is, in one embodiment, thin active layer  405  on n+ silicon substrate wafer  410 . Thin active layer  405  is preferably silicon, n-type, and has a resistivity of approximately 1,000 Ωcm. In one embodiment, the thin active layer is thin epi or a thin direct-bonded active layer. In one embodiment, thin active layer  405  has a thickness of 15 μm. In one embodiment, the n+ silicon substrate wafer  410  has a thickness of 250 μm. In one embodiment, the overall thickness of the starting material is 265 μm. While it is preferred that the substrate wafer be comprised of silicon, one of ordinary skill in the art would appreciate that any suitable mechanical support, which can be processed in accordance with the processing steps of the present invention, may be used. 
     In addition, both thin active layer  405  and substrate wafer  410  can optionally be polished on both sides to allow for greater conformity to parameters, surface flatness, and specification thickness. It should be understood by those of ordinary skill in the art, however, that the above specifications are not binding and that the type of material and resistivity can easily be changed to suit the design, fabrication, and functional requirements of the present invention. 
     Referring back to  FIG. 4A , in step  450 , both thin active layer  405  and n+ silicon substrate  410  are subjected to a standard mask oxidation process that grows an oxide layer  415  on the front side of thin active layer  405  and the back side of n+ silicon substrate  410 . In one embodiment, the oxide layer  415  comprises silicon oxide (SiO 2 ) having a thickness of approximately 8000 Å. The thick oxide layer  415  will serve to protect the P-N junction, as described with respect to  FIGS. 2 and 3   a . In one embodiment, thermal oxidation is employed to achieve mask oxidation. Standard mask oxidation is well known to those of ordinary skill in the art and will not be described in further detail herein. 
     Now referring to  FIG. 4B , after the standard mask oxidation is complete, in step  455 , the device is subjected to n+ photolithography on the front side of thin active layer  405 . In one embodiment, photolithography comprises employing a photoresist layer to create a specific pattern on the surface of thin active layer  405 . 
     Generally, the photoresist layer is a photosensitive polymeric material for photolithography and photoengraving that can form a patterned coating on a surface. After selecting a suitable material and creating a suitable photoresist pattern, a thin photoresist layer is applied to the front side of thin active layer  405 . In one embodiment, the photoresist layer is applied via a spin coating technique. Spin coating is well known to those of ordinary skill in the art and will not be described in detail herein. 
     In one embodiment, n+ masking is used to form a suitable photoresist layer pattern. An exemplary n+ mask is shown in  FIG. 5A . As shown in  FIG. 5A , the n+ masking results in a specific pattern on thin active layer  405 . Generally, photographic masks are high precision plates containing microscopic images of preferred pattern or electronic circuits. They are typically fabricated from flat pieces of quartz or glass with a layer of chrome on one side. The mask geometry is etched in the chrome layer. In one embodiment, the n+ mask shown in  FIG. 5A  comprises a plurality of diffusion windows with appropriate geometrical and dimensional specifications. 
     Referring back to  FIG. 4B , the photoresist coated thin active layer  405  is aligned with the n+ mask and appropriately treated to reveal n+ diffusion regions. An intense light, such as UV light, is projected through the mask, exposing the photoresist layer in the pattern of the n+ mask. The n+ mask allows selective irradiation of the photoresist on the thin active layer. Regions that are exposed to radiation are hardened while those that are reserved for diffusion remain shielded by the n+ mask and easily removed by etching. 
     The exposed and remaining photoresist is then subjected to a suitable chemical or plasma etching process to reveal the pattern transfer from the mask to the photoresist layer. The etching process is employed to remove the silicon oxide layer from the front side of the thin active layer and the back side of the n+ substrate. In one embodiment, the pattern of the photoresist layer and/or n+ mask defines a plurality of regions  420 , on the front side of the thin active layer, devoid of the oxide layer deposited in step  450  and ready for n+ diffusion. 
     Now referring to  FIG. 4C , in step  460 , the front side of thin active layer  405  and the back side of n+ silicon substrate  410  are subjected to n+ diffusion followed by drive-in oxidation. Generally, diffusion facilitates propagation of a diffusing material through a host material. In step  460 , an appropriate amount of dopant atoms, such as phosphorous, is deposited onto at least a portion of the front side of thin active layer  405  and the entire back side of the n+ silicon substrate  410 . The substrate is then subjected to a drive-in oxidation process that is used to redistribute the dopant atoms and deposit them deeper into the front side of thin active layer  405  and back side of silicon substrate  410 . In one embodiment, this process fills the plurality of regions  420  devoid of the oxide layer via deep diffusion with n+ dopant. In addition, exposed surfaces, such as the front side of thin active layer  405  and back side of silicon substrate  410 , are covered with oxide layer  425 . In one embodiment, oxide layer  425  has a thickness of approximately 3000 Å. 
     Referring now to  FIG. 4D , in step  465 , the front side of thin active layer  405  is subjected to a p+ lithography process, creating a plurality of regions  430 , which are exposed silicon surfaces devoid of any layers. As with any conventional lithography process, p+ lithography comprises at least the following tasks, but not limited to such tasks: substrate preparation; photoresist application; soft baking; mask alignment; exposure; development; hard backing; and etching. In addition, various other chemical treatments may be performed. 
     In one embodiment, the p+ mask shown in  FIG. 5   b  is employed. In one embodiment, the p+ mask pattern is a fishbone pattern that comprises p+ bones  505 , further defined by a periphery frame bone  510 . In one embodiment, bones  505  have a width of 0.014 mm. In one embodiment, the distance between adjacent p+ bones is 700 μm. In one embodiment, the pitch is 714 μm. The p+ masking process is similar to that delineated with respect to the n+ masking process described earlier and will not be repeated in detail herein. 
     The p+ masking process further comprises deposition and drive-in oxidation, as shown in  FIG. 4   e , allowing for predefined and/or predetermined thermal budget in accordance with the principles of the present invention. Now referring to  FIG. 4E , in step  470 , an appropriate amount of dopant atoms, such as boron, is deposited onto at least a portion of the front side of thin active layer  405 . The thin active layer  405  is then subjected to a drive-in oxidation process that is used to redistribute the dopant atoms and deposit them deeper into the front side of thin active layer  405 . In one embodiment, this process fills the plurality of regions  430  devoid of the oxide layer via deep diffusion with p+ dopant. In one embodiment, the p+ regions have a width of 0.014 mm. In one embodiment, the distance between adjacent p+ bones is 700 μm. In one embodiment, the pitch, or distance between the centers of any two adjacent p+ bones, is 714 μm. 
     In addition, exposed surfaces, such as the front side of thin active layer  405  and back side of silicon substrate  410 , are covered with an oxide layer  431 . In one embodiment, oxide layer  431  has a thickness of approximately 2700 Å. 
     In step  475 , as shown in  FIG. 4F , the device wafer undergoes active area photolithography and subsequent selective oxide etching to expose a plurality of active area regions  435  on the front side of thin active layer  405 . In one embodiment, an active area mask, such as that shown in  FIG. 5C  is employed. The active area specifications, among other parameters, form the significant performance characteristics of the photodiode of the present invention. 
     Referring back to  FIG. 4F , a plurality of thick oxide covered regions  440  are retained on top of the P-N junction. In one embodiment, thick oxide regions  440  comprise approximately 8000 Å of silicon oxide and approximately 425 Å of silicon nitride. In one embodiment, the thick oxide regions or layer  440  comprises three sections  440   a ,  440   b , and  440   c . Sections  440   a  and  440   b  comprise the end sections of thick oxide regions or layer  440  and have a width of 20 mm. Section  440   c  is the middle section of thick oxide regions  440 , directly on top of the p+ fishbone, and, in one embodiment, is thinner than end sections  440   a  and  440   b . Since the P-N junctions are passivated with the thick oxide regions  440 , the device has more structural rigidity and integrity and is less prone to junction degradation. 
     In one embodiment, the back side of the n+ silicon substrate  410  is etched completely so that it is devoid of any oxide layer. 
     In step  480 , as shown in  FIG. 4G , dual anti-reflective (AR) layers  441  and  442  are grown on the front side of thin active layer  405  and silicon substrate  410 . Persons of ordinary skill in the art would appreciate that various anti-reflective coating designs, such as 1 layer, 2 layer, 3 layer, and 4+ layer may be employed. By way of example, and by no means limiting, the dual layer anti-reflective coating design adopted herein utilizes a combination of thin film materials, such as oxides, sulfides, fluorides, nitrides, selenides, and metals, among others. In one embodiment of the photodiode array of the present invention, AR layer  441  comprises silicon oxide and has a thickness of 150 Å. In one embodiment, AR layer  442  comprises silicon nitride and has a thickness of 425 Å. 
     Although the thickness of the AR layers of the present invention are optimized for use with LSO/LYSO scintillator crystals, it should be appreciated by those of ordinary skill in the art that the thickness of the AR layer employed in the present invention can be tailored to obtain minimum reflection loss at different wavelengths for different applications and can thus be used with any scintillator material. 
     For example, but not limited to such example, certain photodiode arrays employ a scintillator material such as Cadmium Tungstate. Cadmium Tungstate (CdWO4 or CWO) is a dense, chemically inert solid which is used as a scintillation crystal to detect gamma rays. The crystal is transparent and emits light when it is hit by gamma rays and X-rays, making it useful as a detector of ionizing radiation. Its peak scintillation wavelength is 520 nm (with emission range between 330-540 nm), and efficiency of 13000 photons/MeV. 
     Now referring to  FIG. 4H , in step  485 , a contact etch mask is used to etch a plurality of contact windows  445  into the front side of the thin active layer  405 . Contact lithography, well known to those of ordinary skill in the art, involves printing an image or pattern via illumination of a photomask in direct contact with a substrate coated with an imaging photoresist layer. Typically, a contact window is an aperture defined in a surface passivation layer through which device metallization develops contact with circuit elements. The contact windows  445  formed on the front side of the thin active layer  405  by using standard semiconductor technology photolithography techniques. The contact window oxide can then be removed by either standard wet or standard dry etching techniques as are well known to those of ordinary skill in the art. 
     More specifically, and not limited to such example, in one embodiment of the photodiode array of the present invention, a contact window mask such as that shown in  FIG. 5D  is first applied. In one embodiment, the contact window mask is a dark field mask, which is used to remove the silicon oxide layer in regions requiring contacts. Using the contact mask, at least one of contact windows  445  is opened through the protective and passivation layers deposited on the surface of the thin active layer by etching the oxide from regions  445  that remain exposed by the mask. In one embodiment, contact window etching is achieved via a chemical etching process, wherein the wafer is immersed in buffered oxide etch (BOE), a HF acid-based solution for intervals sufficient to remove the layers exposed by the contact window mask. 
     Referring now to  FIG. 4I , in step  490 , thin active layer  405  and n+ silicon substrate  410  are subjected to a metal deposition process to provide metal contacts  446  on the front side of thin active layer  405  and a metal layer  447  on the back side of the n+ silicon substrate wafer for creating electrical connections. In the metal deposition process, also called metallization, metal layers are deposited on the wafer to create conductive pathways. The most common metals include aluminium, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, and tantalum. Selected metal alloys may also be used. Metallization is often accomplished with a vacuum deposition technique. The most common deposition process include filament evaporation, electron-beam evaporation, flash evaporation, induction evaporation, and sputtering, followed by metal masking and selective etching. 
     In one embodiment, the metal mask shown in  FIG. 5E  is employed. In one embodiment, metal contacts  446  are selectively etched on the front side of the photodiode  400  using the metal mask shown in  FIG. 5E . Metal etching can be performed in a variety of methods, including, but not limited to abrasive etching, dry etching, electroetching, laser etching, photo etching, reactive ion etching (RIE), sputter etching, and vapor phase etching. 
       FIGS. 6A ,  6 B,  6 C,  6 D, and  6 E illustrate various alternative embodiments of a fishbone photodiode array, wherein each photodiode element comprises at least one p+ fishbone, and preferably, at least three p+ fishbones. It should be noted that while the embodiments described herein depict various p+ bone layout designs for an exemplary photodiode array  600  comprising four anode pads  615  on the front side and common cathode metallization (not shown) on the back side, any number of photodiode elements may be used to form a photodiode array. 
     In the examples described below, the photodiode array  600  shown in  FIGS. 6A through 6E  are, in one embodiment, fabricated on silicon chips having a thickness of 0.250 mm and have overall dimensions of 22.254 mm×6.594 mm and a tolerance of +−0.025 mm. 
       FIG. 6A  represents a front-side view of one embodiment of the fishbone photodiode array  600  of the present invention, wherein each photodiode element comprises a three p+ bone layout. A p+ mask is employed to create and form the three p+ fishbone pattern, comprising p+ bones  605  further defined by periphery frame bones  610 . Thus, each of the four photodiode elements  630  comprises three fishbones. In this embodiment, the distance  635  from the center of one p+ diffusion bone  605  to the center of the adjacent periphery frame bone  610 , defining the bones pitch, is 2.493 mm. The distance  640  between the centers of any two adjacent elements or anode pads  615  is 5.600 mm. The photodiode array  600  further comprises active areas  620  which in this example are 5 mm×5 mm each. Also, the distance  645  between anode pads  615  and edge, such as edge  625 , of the corresponding photodiode is 2.727 mm. 
       FIG. 6B  represents a front-side view of one embodiment of the fishbone photodiode array  600  of the present invention, wherein each photodiode element comprises a four p+ bone layout. A p+ mask is employed to create and form the four p+ fishbone pattern, comprising p+ bones  605  further defined by periphery frame bones  610 . Thus, each of the four photodiode elements  630  comprises four fishbones. In this embodiment, the distance  635  from the center of one p+ diffusion bone  605  to the center of the adjacent bone  605  or  610 , defining the bones pitch, is 1.662 mm. The distance  640  between the centers of any two adjacent elements  630  or anode pads  615  is 5.600 mm. The photodiode array  600  further comprises active areas  620  which in this example are 5 mm×5 mm each. Also, the distance  645  between anode pads  615  and edge, such as edge  625 , of the corresponding photodiode is 2.727 mm. 
       FIG. 6C  represents a front-side view of one embodiment of the fishbone photodiode array  600  of the present invention, wherein each photodiode element comprises a five p+ bone layout. A p+ mask is employed to create and form the five p+ fishbone pattern, comprising p+ bones  605  further defined by periphery frame bones  610 . Thus, each of the four photodiode elements  630  comprises five fishbones. In this embodiment, the distance  635  from the center of one p+ diffusion bone  605  to the center of the adjacent bone  605  or  610 , defining the bones pitch, is 1.247 mm. The distance  640  between the centers of any two adjacent elements  630  or anode pads  615  is 5.600 mm. The photodiode array  600  further comprises active areas  620  which in this example are 5 mm×5 mm each. Also, the distance  645  between anode pads  615  and edge, such as edge  625 , of the corresponding photodiode is 2.727 mm. 
       FIG. 6D  represents a front-side view of one embodiment of the fishbone photodiode array  600  of the present invention, wherein each photodiode element comprises a six p+ bone layout. A p+ mask is employed to create and form the six p+ fishbone pattern, comprising p+ bones  605  further defined by periphery frame bones  610 . Thus, each of the four photodiode elements  630  comprises six fishbones. In this embodiment, the distance  635  from the center of one p+ diffusion bone  605  to the center of the adjacent bone  605  or  610 , defining the bones pitch, is 0.997 mm. The distance  640  between the centers of any two adjacent elements  630  or anode pads  615  is 5.600 mm. The photodiode array  600  further comprises active areas  620  which in this example are 5 mm×5 mm each. Also, the distance  645  between anode pads  615  and edge, such as edge  625 , of the corresponding photodiode is 2.727 mm. 
       FIG. 6E  represents a front-side view of one embodiment of the fishbone photodiode array  600  of the present invention, wherein each photodiode element comprises an eight p+ bone layout. A p+ mask is employed to create and form the eight p+ fishbone pattern, comprising p+ bones  605  further defined by periphery frame bones  610 . Thus, each of the four photodiode elements  630  comprises eight fishbones. In this embodiment, the distance  635  from the center of one p+ diffusion bone  605  to the center of the adjacent bone  605  or  610 , defining the bones pitch, is 0.712 mm. The distance  640  between the centers of any two adjacent elements  630  or anode pads  615  is 5.600 mm. The photodiode array  600  further comprises active areas  620  which in this example are 5 mm×5 mm each. Also, the distance  645  between anode pads  615  and edge, such as edge  625 , of the corresponding photodiode is 2.727 mm. 
       FIG. 7  is a table depicting example performance characteristics for each of the three, four, five, six and eight bone layout design arrays of  FIGS. 6A through 6E  at a particular bias voltage. This table provides performance characteristics for the various layouts at 10 mV bias voltage and 540 nm flooded. For example, the four bones design array of  FIG. 6B  can achieve characteristics of Rsh typ 2 Gohm, capacitance typ 34.8 pF @ 0 volt, responsivity typ 0.385 A/W @ 540 nm, response time typ 179 uS. 
       FIG. 8  is another table depicting example performance characteristics for each of the three, four, five, six and eight bones layout design arrays of  FIGS. 6A through 6E  at three different bias voltages. Thus, this table provides performance characteristics for each of the bone design layouts (of  FIGS. 6A through 6E ) at three bias voltages of 0.01V, 1.5V and 3V respectively for 632 nm flooded. 
       FIG. 11  represents a front-side view of another embodiment of the fishbone photodiode array  1100  of the present invention. In this example, but not limited to such example, photodiode array  1100  comprises at least one photodiode element  1130  which in turn, comprises an eight p+ bone layout. In one embodiment, the photodiode array  1100  comprises two elements  1130 . As described earlier, it should be noted that the present invention is not limited to the use of eight p+ bones and a larger or smaller number of p+ bones may be employed depending upon the performance requirements of the photodiode array. A p+ mask is employed to create and form the eight p+ fishbone pattern, comprising p+ bones  1105  further defined by periphery frame bones  1110 . Thus, each of the two photodiode elements  1130  comprises eight fishbones. 
     In this embodiment, the anode metal bars are placed only in the last vertical fishbone  1111  of each of the photodiode elements  1130 . The last vertical fishbone  1111  is part of the periphery frame bones  1110 . Section  1140  shows a magnified view of the last vertical fishbones showing the p+ bone  1111 , the metal contact bars  1112  and the contact window  1113 . The metal contact bars  1112  are connected to the wire bonding pads  1125 . Sections  1150  show magnified views of how the metal bars  1112  at the last vertical fishbones  1111  of the elements  1130  are connected to form the bonding pads  1125  at the end of the second photodiode element. Persons of ordinary skill in the art should appreciate that with anode pads  1125  on the front side and common cathode metallization (not shown) on the back side, any number of such photodiode elements  1130  may be used to form a photodiode array  1100 . 
       FIG. 12  represents a front-side view of still another embodiment of the fishbone photodiode array  1200  of the present invention. In this example, but not limited to such example, photodiode array  1200  comprises at least one photodiode element  1230  which in turn, comprises a five p+ bone layout. In one embodiment, the photodiode array  1200  comprises two elements  1230 . As described earlier, it should be noted that the present invention is not limited to the use of five p+ bones and a larger or smaller number of p+ bones may be employed depending upon the performance requirements of the photodiode array. A p+ mask is employed to create and form the five p+ fishbone pattern, comprising p+ bones  1205  further defined by periphery frame bones  1210 . Thus, each of the two photodiode elements  1230  comprises five fishbones. 
     In this embodiment, the anode metal bars are placed on each of the fishbones (that are five in number in this example)—that is the p+ bones  1205  as well as the periphery bones  1210 . Sections  1240  show magnified views of the fishbones comprising the p+ diffusion  1211 , the metal contact bars  1212  and the contact window  1213 . The metal contact bars  1212 , at each of the fishbones, are connected to the wire bonding pads  1225 . Sections  1250  show magnified views of how the metal bars  1212  at each of the fishbones  1205 ,  1210  of the elements  1230  are connected to form the bonding pads  1225  at the end of the second photodiode element. Persons of ordinary skill in the art should appreciate that with anode pads  1225  on the front side and common cathode metallization (not shown) on the back side, any number of such photodiode elements  1230  may be used to form a photodiode array  1200 . The photodiode array  1200  with metal bars at each of the fishbones for each of the photodiode elements provides high linear current with low series resistance. 
       FIG. 9A  is a cross-sectional view of yet another embodiment of the fishbone photodiode  900  fabricated on an n-type thin active layer  905 . In one embodiment, thin active layer  905  has a thickness of 15 μm. The thin active layer  905  is placed on a mechanical support  935  comprised of n+ silicon substrate. 
     The photodiode array  900  comprises a p+ fishbone pattern, wherein adjacent p+ fishbones  910  are placed at a wide distance from each other, necessitating the use of fewer fishbones. The present embodiment, however, also comprises a shallow n+ layer  950  between p+ bones  910 . In one embodiment, shallow n+ layer  950  has a depth of 0.3 μm. Since there is no electric field in the wide gap between the p+ bones  910 , the photo-generated minority carriers  920 , or the holes in n-type silicon, tend to move randomly and thus, in all directions. Holes  920  moving upward are reflected by the n+n high-low junction and finally get collected by the electric field of the PN junction  930  as depicted by path  925 . Holes  920  moving downward are reflected by the low-high n-n+ junction at the n-type thin layer/n+ substrate interface and finally also get collected by the PN junction  930  as depicted by path  926 . Without the presence of shallow n+ layer  950 , a portion of photo-generated minority carriers  920  would otherwise recombine at the silicon/silicon dioxide interface and reduce the charge collection efficiency of device  900 . Thus, the shallow n+ layer between p+ bones is advantageous in that it increases the efficiency of the photodiode device. 
     The fishbone photodiode  900  of  FIG. 9A  is fabricated with a thick oxide region  915  on top of each of the PN junctions  930  prior to the growth/deposition of the relatively thin anti-reflective (AR) layers  941 ,  942 . In one embodiment, thick oxide regions  915  comprise approximately 8000 Å of silicon oxide and approximately 425 Å of silicon nitride. Since the P-N junctions are passivated with the thick oxide regions  915 , the device has more structural rigidity and integrity and is less prone to junction degradation. 
     In one embodiment AR layer  941  comprises silicon oxide and has a thickness of 150 Å. In one embodiment, AR layer  942  comprises silicon nitride and has a thickness of 425 Å. 
       FIG. 9B  shows a front-side view of fishbone photodiode array  900 , shown as a cross-sectional view in  FIG. 9A . In this example, but not limited to such example, photodiode array  900  comprises at least one photodiode element  901  which in turn, comprises an eight p+ bone layout. As described earlier, it should be noted that the present invention is not limited to the use of eight p+ bones and a larger or smaller number of p+ bones may be employed depending upon the performance requirements of the photodiode array. 
     A p+ mask is employed to create and form the eight p+ fishbone pattern, comprising p+ bones  905 . In addition, an n+ mask is employed to create and form shallow n+ layers  910  between adjacent p+ bones  905 . Persons of ordinary skill in the art should appreciate that with anode pads  915  on the front side and common cathode metallization (not shown) on the back side, any number of such photodiode elements  901  may be used to form a photodiode array  900 . 
       FIGS. 10A-10L  represent exemplary manufacturing steps of the photodiode of the present invention shown in  FIGS. 9A and 9B . 
     Referring now to  FIG. 10A , the starting material for fabricating photodiode  900  of  FIGS. 9   a  and  9   b  is, in one embodiment, thin active layer  1005  on n+ silicon substrate wafer  1010 . Thin active layer  1005  is preferably silicon, n-type, and has a resistivity of approximately 1,000 Ωcm. In one embodiment, the thin active layer  1005  is thin epi or a thin direct-bonded active layer. In one embodiment, thin active layer  1005  has a thickness of 15 μm. In one embodiment, the n+ silicon substrate wafer  1010  has a thickness of 250 μm. In one embodiment, the overall thickness of the starting material is 265 μm. While it is preferred that the substrate wafer be comprised of silicon, one of ordinary skill in the art would appreciate that any suitable mechanical support, which can be processed in accordance with the processing steps of the present invention, may be used. 
     In addition, both thin active layer  1005  and substrate wafer  1010  can optionally be polished on both sides to allow for greater conformity to parameters, surface flatness, and specification thickness. It should be understood by those of ordinary skill in the art, however, that the above specifications are not binding and that the type of material and resistivity can easily be changed to suit the design, fabrication, and functional requirements of the present invention. 
     Referring to  FIG. 10B , in step  1050 , both thin active layer  1005  and n+ silicon substrate  1010  are subjected to a standard mask oxidation process that grows an oxide layer  1015  on the front side of thin active layer  1005  and the back side of n+ silicon substrate  1010 . In one embodiment, the oxide layer  1015  comprises silicon oxide (SiO2). The oxide layer  1015  serves to protect the PN junction (that is formed later and described below). In one embodiment, thermal oxidation is employed to achieve mask oxidation. Standard mask oxidation is well known to those of ordinary skill in the art and will not be described in further detail herein. 
     Now referring to  FIG. 10C , after the standard mask oxidation is complete, in step  1055 , the photodiode device is prepared for p+ photolithography on the front side of thin active layer  1005  by employing a photoresist layer  1011  on the surface of thin active layer  1005 . Generally, the photoresist layer is a photosensitive polymeric material for photolithography and photoengraving that can form a patterned coating on a surface. After selecting a suitable material and creating a suitable photoresist pattern, a thin photoresist layer is applied to the front side of thin active layer  1005 . In one embodiment, the photoresist layer  1011  is applied via a spin coating technique. Spin coating is well known to those of ordinary skill in the art and will not be described in detail herein. 
     Referring to  FIG. 10D , in step  1060 , the photoresist coated thin active layer  1005  is aligned with a suitable p+ mask and appropriately treated to reveal p+ diffusion regions. An intense light, such as UV light, is projected through the mask, exposing the photoresist layer  1011  in the pattern of the p+ mask. The p+ mask allows selective irradiation of the photoresist on the thin active layer. Regions that are exposed to radiation are hardened while those that are reserved for diffusion remain shielded by the p+ mask and easily removed by etching. 
     The exposed and remaining photoresist is then subjected to a suitable chemical or plasma etching process to reveal the pattern transfer from the mask to the photoresist layer  1011 . The etching process is employed to remove the silicon oxide layer from the front side of the thin active layer  1005  and the back side of the n+ substrate  1010 . In one embodiment, the pattern of the photoresist layer  1011  and/or p+ mask defines a plurality of regions  1020 , on the front side of the thin active layer  1005 , ready for p+ diffusion. 
     Now referring to  FIG. 10E , in step  1065 , the front side of thin active layer  1005  is subjected to p+ diffusion followed by drive-in oxidation. Generally, diffusion facilitates propagation of a diffusing material through a host material. In step  1065 , an appropriate amount of dopant atoms, such as boron, is deposited onto at least a portion of the front side of thin active layer  1005 . The substrate is then subjected to a drive-in oxidation process that is used to redistribute the dopant atoms and deposit them deeper into the front side of thin active layer  1005 . In one embodiment, this process fills the plurality of regions  1020 , devoid of the oxide layer, via deep diffusion with p+ dopant. In one embodiment, the depth of p+ diffusion is of the order of 1 μm. In addition, exposed surfaces of the front side of thin active layer  1005 , are covered with oxide layer  1025 . 
     In step  1070  of  FIG. 10F  the front side of the thin active layer  1005  is re-coated with photoresist layer  1012  and prepared for n+ photolithography. Referring now to  FIG. 10G , in step  1075 , the front side of thin active layer  1005  is aligned with a suitable n+ mask and appropriately treated to reveal n+ diffusion regions  1030 . An intense light, such as UV light, is projected through the mask, exposing the photoresist layer  1012  in the pattern of the n+ mask. The n+ mask allows selective irradiation of the photoresist on the thin active layer  1005 . Regions that are exposed to radiation are hardened while those that are reserved for diffusion remain shielded by the n+ mask and easily removed by etching. 
     The exposed and remaining photoresist is then subjected to a suitable chemical or plasma etching process to reveal the pattern transfer from the mask to the photoresist layer  1012 . The etching process is employed to remove the silicon oxide layer from the front side of the thin active layer  1005  and the back side of the n+ substrate  1010 . In one embodiment, the pattern of the photoresist layer  1012  and/or n+ mask defines a plurality of regions  1030 , on the front side of the thin active layer  1005 , and ready for n+ diffusion. 
     The n+ masking process further comprises deposition and drive-in oxidation, allowing for predefined and/or predetermined thermal budget in accordance with the principles of the present invention. Now referring to  FIG. 10H , in step  1080 , an appropriate amount of dopant atoms, such as phosphorous, is deposited onto at least a portion of the front side of thin active layer  1005 . The thin active layer  1005  is then subjected to a drive-in oxidation process that is used to redistribute the dopant atoms and deposit them into the front side of thin active layer  1005 . In one embodiment, this process fills the plurality of regions  1030  via shallow diffusion with n+ dopant. In one embodiment, the shallow n+ regions  1032  have a depth of 0.3 μm. In addition, exposed surfaces are covered with an oxide layer  1031 . In one embodiment, oxide layer  1031  has a thickness of approximately 150 Å. 
     At step  1085  of  FIG. 10I  the front side of the thin active layer  1005  is coated with a thick layer  1033  of silicon nitride and thereafter with a layer of photoresist material  1013 . In one embodiment, the thickness of the silicon nitride layer  1033  is 425 Å. 
     Now referring to  FIG. 10J , in step  1090 , a contact etch mask is used to etch a plurality of contact windows  1045  into the front side of the thin active layer  1005 . Contact lithography, well known to those of ordinary skill in the art, involves printing an image or pattern via illumination of a photomask in direct contact with a substrate coated with an imaging photoresist layer. Typically, a contact window is an aperture defined in a surface passivation layer through which device metallization develops contact with circuit elements. The contact windows  1045  are formed on the front side of the thin active layer  1005  by using standard semiconductor technology photolithography techniques. The contact window oxide can then be removed by either standard wet or standard dry etching techniques as are well known to those of ordinary skill in the art. 
     In one embodiment, the contact window/etch mask is a dark field mask, which is used to remove the passivation layers in regions requiring contacts. Using the contact mask, at least one contact window  1045  is opened through the protective and passivation layers deposited on the surface of the thin active layer  1005  by etching the passivation layers from regions  1045  that remain exposed by the mask. In one embodiment, contact window etching is achieved via a chemical etching process, wherein the wafer is immersed in buffered oxide etch (BOE), a HF acid-based solution for intervals sufficient to remove the layers exposed by the contact window mask. 
     Referring now to  FIG. 10K , in step  1095 , thin active layer  1005  and n+ silicon substrate  1010  are subjected to a metal deposition process to thereafter provide metal contacts on the front side of thin active layer  1005  and a metal layer  1047  on the back side of the n+ silicon substrate wafer  1010  for creating electrical connections. In the metal deposition process, also called metallization, metal layers  1047  are deposited on the wafer to create conductive pathways. The most common metals include aluminium, nickel, chromium, gold, germanium, copper, silver, titanium, tungsten, platinum, and tantalum. Selected metal alloys may also be used. Metallization is often accomplished with a vacuum deposition technique. The most common deposition process includes filament evaporation, electron-beam evaporation, flash evaporation, induction evaporation, and sputtering. After metallization a photoresist layer  1014  is also deposited on the front side of this active layer  1005 . 
     This is followed by metal mask lithography and selective etching in step  1097  of  FIG. 10L  to reveal n+ metal contacts  1048  on the front side of the thin active layer  1005  and on the backside of the n+ silicon substrate  1010 . In one embodiment, metal contacts  1048  are selectively etched using a metal mask and the photoresist layer  1014  (of  FIG. 10K ) is also stripped. Metal etching can be performed in a variety of methods, including, but not limited to abrasive etching, dry etching, electroetching, laser etching, photo etching, reactive ion etching (RIE), sputter etching, and vapor phase etching. 
     The above examples are merely illustrative of the structure and manufacturing steps of the photodiode array of the present invention. Although only a few embodiments of the present invention have been described herein, it should be understood that the present invention might be embodied in many other specific forms without departing from the spirit or scope of the invention. Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive, and the invention may be modified within the scope of the appended claims.

Technology Category: 5