Patent Document

BACKGROUND 
   The present disclosure relates in general to devices and methods for DRAM initialization. In particular, the present disclosure relates to devices and methods for DRAM initialization according to initialization parameters stored when DRAM are not removed. 
   Computers generally comprise a CPU, chipsets, a memory controller and buses. CPU processes most operations of the computer. Chipsets support the operation of the CPU. Generally, the chipset comprises controllers for transmission of data between the CPU and other devices. The memory controller is a part of the chipset, establishing data transmission between memory and the CPU. Buses are connected between the CPU, memory, and other I/O devices. The bus determines the operating speed of a main board. In response to different data transmission requirements, different kinds of buses are provided. A memory bus is connected between the memory controller and the memory module. 
   During boot, memory initialization is performed, comprising setting memory operating frequency and a column address strobe latency (CL). 
   Conventional technology obtains memory initialization parameters by reading serial presence detect (SPD) codes stored in EEPROM of the memory. Thereby, information required for memory initialization is obtained. 
   Using double data rate-synchronous DRAM (DDR) as an example, the operating frequency of the DDR can be 400 MHz, 333 MHz and 266 MHz, and column address strobe latency (CL) of the DDR can be 3 clocks, 2.5 clocks and 2 clocks. BIOS can initialize the DDR operating at 400 MHz and 2.5 CL according to SPD. 
   Boot is delayed by determination of the information required for initialization of memory, performed at each boot. However, when memory is not removed between consecutive boots, determination of the information for memory initialization at subsequent boot is unnecessary since determination is the same. 
   SUMMARY 
   Methods and devices for DRAM initialization are provided. An embodiment of a method for DRAM initialization of a computer system comprises: storing initialization parameters of at least one memory, detecting conditions of the memory, reading the conditions of the memory to initialize memory during boot, when conditions of the memory have not changed. 
   Another embodiment of a device for DRAM initialization of a computer system comprises at least one memory, a detection circuit detecting conditions of the memory, and outputting a fast initialization signal, a buffer storing initialization parameters of at least one memory, a memory controller setting the initialization parameters according to memory information, and reading the conditions of the memory to initialize the memory when boot the computer system and receiving the fast initialization signal. 

   
     DESCRIPTION OF THE DRAWINGS 
     The invention will be more fully understood from the detailed description, given hereinbelow, and the accompanying drawings. The drawings and description are provided for purposes of illustration only and, thus, are not intended to limit the invention. 
       FIG. 1  is a schematic diagram of an embodiment of a computer. 
       FIG. 2A  is a circuit diagram of an embodiment of detection circuit. 
       FIG. 2B  is a true table of the voltage levels against specific terminals of detection circuit shown in  FIG. 2A . 
       FIG. 3  is a flowchart showing an embodiment of a method for DRAM initialization. 
   

   DETAILED DESCRIPTION 
     FIG. 1  is a schematic diagram of an embodiment of a computer  10  comprising CPU  12 , cache memory  14 , memory controller  16 , I/O chipset  17  and I/O interface ( 18 A˜ 18 D). Computer  10  further comprises buses  19  connected between the devices thereof. Memory  20 A˜ 20 D may be respectively installed in four dual in-line memory modules (DIMM). In addition, detection circuit  22  detects whether at least one memory  20 A˜ 20 D is changed. In some embodiments, the detection circuit  22  detects removal of memory from the DIMM. In addition, buffer  21  stores initialization parameters of the memory. In some embodiments, buffer  21  can be located in the Southbridge chipset. 
     FIG. 2A  is a circuit diagram of an embodiment of detection circuit  22 .  FIG. 2B  is a true table of the voltage levels against specific terminals of detection circuit  22  shown in  FIG. 2A . 
   Detection circuit  22  comprises comparator  24  and D-type flip-flops  26 A and  26 B. In some embodiments, comparator  24  can be a XOR logic gate, with terminal A 0  representing status of memory  20 A. The logic level of terminal A 0  is “0” when memory  20 A is plugged in the memory module, “1” when memory  20 A is removed from the memory module. In addition, as shown in  FIG. 1 , four terminals A 0 ˜A 3  respectively represent terminals of memory  20 A˜ 20 D.  FIG. 2A  only shows the detection circuit of memory  20 A. 
   In  FIG. 2A , the initial values of output terminals Q 0  and Q 1 , respectively, of D-type flip-flops  26 A and  26 B are “1” because a predetermined voltage 3.3V SUS  is applied thereto. As memory  20 A does not exist, the logic level of terminal A 0  and nodes B 0  and C 0  are high “1”, terminal E 0  thus outputs low logic level “0”. 
   As memory  20 A is installed, the logic level of terminal A 0  is at low “0”, inverted by inverter  27  and input to D-type flip-flops  26 A. Thus, the logic level of terminal B 0  is at low “0”, and that of terminal C 0  is still at high “1”. Thus, terminal E 0  outputs high logic level “1” because the logic levels of terminals A 0  and C 0  are different. 
   In addition, the high logic level “1” of terminal E 0  enables D-type flip-flops  26 B. Thus, output terminal Q 1  is at low logic level “0”, and the logic level of terminal C 0  becomes low “0”. As the logic levels of terminal A 0  and node C 0  received by comparator  24  are the same, thus the logic level of terminal E 0  is at low “0”. 
   As memory  20 A is removed, the logic levels of terminal A 0  and nodes B 0  return to high “1”, while that of terminal C 0  remains at low “0”. Thus, the logic levels of terminal A 0  and node C 0  received by comparator  24  are different, and the logic level of terminal E 0  is at high “1”. In some embodiments, the logic level of terminal E 0  at high “1” represents output of a fast initialization signal. 
   In addition, the high logic level “1” of terminal E 0  enables D-type flip-flops  26 B. Thus, output terminal Q 1  is at low logic level “0”, and the logic level of terminal C 0  becomes high “1”. As the logic levels of terminal A 0  and node C 0  received by comparator  24  are the same, the logic level of terminal E 0  is at low “0”. 
   Thus, removal of memory  20 A is identified by detecting the logic level of terminal E 0  of comparator  24 . In addition, removed memories  20 B˜ 20 D shown in  FIG. 1  are also detected by the detection circuit corresponding to each memory. 
     FIG. 3  is a flowchart showing an embodiment of a method for DRAM initialization. The DRAMs can be DDR, SDRAM, EDO DRAM, RDRAM or combination thereof. Note that the elements in  FIG. 3  corresponding to those in  FIG. 1  share the same reference numerals. 
   During boot, memory initialization parameters are obtained by detecting serial presence detect (SPD) codes of each memory (S 1 ). Using DDR as an example, the operating frequency of the DDR can be 400 MHz, 333 MHz and 266 MHz, and column address strobe latency (CL) of the DDR can be 3 clocks, 2.5 clocks and 2 clocks. BIOS can initialize the DDR operating at 400 MHz and 2.5 CL according to SPD. As there are a plurality of memories, BIOS must select the initialization parameters for initialization of all memories. 
   Memories are initialized according to memory initialization parameters (S 2 ). The initialization of memory comprises at least setting the operating frequency and CL of the memories. 
   The initialization parameters are stored in a buffer  21  (S 3 ). Initialization of other devices is performed (S 4 ), and the operation system is initialized to complete boot operation (S 5 ), allowing normal operation. 
   When the computer is shut down, power source (3.3V SUS ) is still provided to detection circuit  22  and terminals A 0 ˜A 3  to continue detection of memory condition. Thus, the power supply remains connected, or a battery is provided to sustain the operation of detection circuit  22 . 
   When the computer reboots (S 6 ), memory conditions are detected according to the result of detection circuit  22  (S 7 ). If no memory has been changed, the initialization parameters stored in buffer  21  are read (S 8 ), and memory is initialized accordingly (S 9 ). If any memory has been changed, the initialization parameters of the new memory are obtained by detection of SPD code (S 10 ). Next, memory is initialized according to memory initialization parameters (S 11 ). Initialization of other devices is performed (S 12 ), and the operation system is initialized to complete boot operation (S 13 ). In some embodiments, unchanged memory conditions may indicate no memory removal. 
   Accordingly, memory initialization read from buffer is faster than that determined from SPD codes, especially when all memories are not changed. 
   While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Category: 3