Patent Document

BACKGROUND 
     The subject matter described herein relates to the assembly of thin die coreless packages. 
     Electronic components, including integrated circuits, may be assembled into component packages by physically and electrically coupling them to a substrate. Thin dies exhibit performance advantages in some circumstances. Hence, techniques for the assembly of thin die packages find utility. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The detailed description is described with reference to the accompanying figures. 
         FIG. 1  is a flowchart illustrating operations in an embodiment of a method for assembly of thin die coreless IC packages. 
         FIG. 2A  is a schematic illustration of an embodiment of a thin die coreless IC package. 
         FIGS. 2B-2D  are schematic illustrations of an embodiment of a thin die coreless IC package during an assembly process. 
         FIG. 3  is a flowchart illustrating operations in an embodiment of a method for assembly of thin die coreless IC packages. 
         FIGS. 4A-4E  are schematic illustrations of an embodiment of a thin die coreless IC package during an assembly process. 
     
    
    
     DETAILED DESCRIPTION 
     Described herein are techniques for assembly of thin die coreless packages for integrated circuits. In the following description, numerous specific details are set forth to provide a thorough understanding of various embodiments. However, it will be understood by those skilled in the art that the various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been illustrated or described in detail so as not to obscure the particular embodiments. 
     One embodiment of techniques for assembly of thin die coreless packages for integrated circuits will be described with reference to  FIG. 1  and  FIGS. 2A-2D .  FIG. 1  is a flowchart illustrating operations in an embodiment of a method for assembly of thin die coreless integrated circuit (IC packages).  FIG. 2A  is a schematic illustration of an embodiment of a thin die coreless IC package.  FIGS. 2B-2D  are schematic illustrations of an embodiment of a thin die coreless IC package during an assembly process. 
     Referring first to  FIG. 2A , in some embodiments a thin die coreless (TDCL) package architecture may comprise a thin die  210 , a coreless substrate  215 , a heat spreader, and a thermal interface material (TIM). In some embodiments, a coreless substrate may be obtained in panel form. Extra space may be provided between adjacent substrates. A substrate carrier  230  is provided. In some embodiments the substrate carrier  230  may be designed and fabricated. In the embodiment depicted in  FIG. 2B , the substrate carrier  230  has a flat base and a pressure cover plate  240 . The cover plate  240  includes a grid which will be pressed against the space between adjacent substrates to flatten the coreless substrates. 
     Referring to  FIG. 1 , at operation  105  a coreless substrate  215  is coupled to a pressure cover plate  240  of a substrate carrier  230 . In some embodiments, the coreless substrate  215  may be in panel form. In some embodiments, the coreless substrate  215  provides a space between two or more adjacent substrates. In some embodiments, the carrier  230  comprises a flat base and a pressure cover plate, and the pressure cover plate  240  comprises a fine grid, which is pressed against space between adjacent substrates. 
     At operation  110  flux is applied to the coreless substrate panel  215 . At operation  115  at least one die ( 210 ) is placed on the coreless substrate panel  215  ( FIG. 2C ). At operation  120  solder is reflowed onto the coreless substrate panel  215  ( FIG. 2C ). At operation  125  the coreless substrate panel  215  is defluxed ( FIG. 2C ). At operation  130  the coreless substrate panel  215  is underfilled. 
     At operation  135  at least one heat spreader  250  is attached to the coreless substrate panel ( FIG. 2D ). In some embodiments, attaching at least one heat spreader  250  to the coreless substrate panel  215  may include attaching one or more pressure clips  255  to apply bonding pressure to the heat spreader  250 . The assembled chip packages may then be separated. 
     Another embodiment of techniques for assembly of thin die coreless packages for integrated circuits will be described with reference to  FIG. 3  and  FIGS. 4A-4E .  FIG. 3  is a flowchart illustrating operations in an embodiment of a method for assembly of thin die coreless IC packages.  FIG. 4A  is a schematic illustration of an embodiment of a template for use in a thin die coreless IC package.  FIGS. 4B-4E  are schematic illustrations of an embodiment of a thin die coreless IC package during an assembly process. 
     Referring to  FIG. 3 , at operation  310  a template is formed. In some embodiments a template  405  may be fabricated with one or more shallow cavities for holding the dies  410 . The dimensions and location of the cavities may be controlled with high precision. The template may comprise silicon. At operation  315  a die is positioned in at least one cavity of the template  405 . In some embodiments all dies are positioned in the cavities of the template  405 . 
     At operation  320  the die(s) are transferred to a die carrier  420 . In some embodiments transferring the die(s) to a die carrier comprises coating the die carrier with a layer of a high temperature silicone-based tacky material and contacting the die carrier to the template ( FIG. 4B ). At operation  325  the die carrier  420  is positioned adjacent a substrate panel having printed flux thereon ( FIG. 4B ). The substrate panel may be positioned with a carrier  430  ( FIG. 4C ). In some embodiments carrier  430  comprises a flat base and a pressure cover plate, which may comprise a grid which is pressed against space between adjacent substrates. 
     At operation  330  solder is reflowed onto the coreless substrate panel  215  ( FIG. 4D ). At operation  335  the coreless substrate panel is defluxed ( FIG. 4D ). At operation  340  the coreless substrate panel is underfilled ( FIG. 4D ). 
     At operation  345  at least one heat spreader  450  is attached to the coreless substrate panel ( FIG. 4E ). In some embodiments, attaching at least one heat spreader  450  to the coreless substrate panel  415  may include attaching one or more pressure clips  455  to apply bonding pressure to the heat spreader  450 . The assembled chip packages may then be separated. 
     In the description and claims, the terms coupled and connected, along with their derivatives, may be used. In particular embodiments, connected may be used to indicate that two or more elements are in direct physical or electrical contact with each other. Coupled may mean that two or more elements are in direct physical or electrical contact. However, coupled may also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate or interact with each other. 
     Reference in the specification to “one embodiment” “some embodiments” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment. 
     Although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.

Technology Category: 5