Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to frequency synthesizers for digital communication systems, and in particular, to frequency synthesizers using digital frequency lock loops and allowing direct modulation of the oscillator signal source. 
     2. Description of the Related Art 
     Time division multiple access (TDMA) wireless communication systems use discreet time slots for transmitting data at various defined frequencies. These data transmission time slots are separated by guard time slots to prevent signal collisions and allow the various signal sources within the system to settle at the defined transmission frequencies. Examples of such systems include wireless local area network (LAN) systems and cordless telephone systems, such as that defined according to the DECT standard. By way of example, the DECT time slot is approximately 400 microseconds, with a guard time slot of approximately 20-30 microseconds. Therefore, to achieve zero blindslot operation with a single signal source, a lock time of 20 microseconds is required. 
     One technique which has been used to implement a frequency synthesizer with a fast lock time is to replace a traditional phase lock loop (PLL) within the frequency synthesizer by a frequency counter, a digital-to-analog converter (DAC) and a signal processor (e.g., a microprocessor). The oscillator output is counted by the frequency counter to produce frequency count data. This frequency count data is processed by the signal processor to produce frequency control data which is converted to the appropriate analog signal by the DAC which drives the oscillator. One could also use a digital band select stage within the signal source (e.g., voltage-controlled oscillator) along with a lower resolution tuning DAC. One example of such an implementation can be found in U.S. Pat. No. 5,182,528, the disclosure of which is incorporated herein by reference. As noted, the DAC drives the oscillator and the frequency counter verifies the resulting frequency by counting the number of oscillator signal cycles within a predefined time period. From this count, the frequency can be derived. Accordingly, the locking time is defined by the settling time of the DAC. Some form of data storage circuit is used to store the DAC input data needed for the oscillator (e.g., a voltage-controlled oscillator) to generate the desired frequencies used for the system. 
     With the frequency counter connected directly to the output of the oscillator to count the cycles of the output signal, the counter will be driven by a continuous, or CW, signal during the receive mode of operation, but will be driven by a modulated signal during the transmit mode of operation. As noted, the frequency counter counts the number of oscillator signal periods that occur within a predefined time period which is derived from a system timing unit such as a crystal-referenced oscillator circuit. If the frequency is not within the desired frequency limits, the data presented to the DAC will be modified accordingly (via the data storage circuit) to compensate for any frequency differences until the next time the frequency is to be used. In the receive mode, with the signal having a constant frequency, this frequency compensation is easily done. However, in the transmit mode, with the output signal being modulated in frequency, the derived frequency count information provided by the counter will not accurately reflect the nominal, or center, frequency required to be generated by the oscillator circuit. 
     Accordingly, it would be desirable to have a way to monitor and maintain frequency lock for a frequency modulated signal while still providing for a fast frequency lock time by using a counter circuit in the feedback loop and a DAC to drive the oscillator circuit directly. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram of a frequency synthesizer with a digital FLL in accordance with one embodiment with the present invention. 
     FIG. 2 is a timing diagram illustrating the data transmission and guard time slots for a typical TDMA system for which a frequency synthesizer in accordance with the present invention is particularly advantageous. 
    
    
     SUMMARY OF THE INVENTION 
     A frequency synthesizer with a digital FLL in accordance with the present invention uses a frequency counter circuit in the feedback loop to count the output signal frequency and uses a DAC to provide the frequency control signal for the oscillator circuit. (Alternatively, a lower resolution DAC can be used to provide fine tuning control in combination with an oscillator having a band select section which provides coarse tuning control.) A modulation control circuit provides modulation data for generating a modulation control signal for the oscillator circuit. The modulation data from the modulation control circuit and the frequency count data from the feedback loop are processed together to determine the appropriate compensation data to be provided to the DAC which controls the center frequency of the oscillator signal. By processing these data together, thereby accounting for the amount of modulation applied to the FLL signal source, the center frequency can be maintained more accurately notwithstanding the presence of modulation within the feedback loop signal. 
     In accordance with one embodiment of the present invention, a frequency synthesizer with a digital frequency lock loop (FLL) includes a frequency measurement circuit, a modulation control circuit and a data processing and control circuit. The frequency measurement circuit is configured to couple to a controllable signal generator circuit, receive from the controllable signal generator circuit a controlled signal having a controlled signal frequency and measure the controlled signal frequency and in accordance therewith provide measured frequency data. The controlled signal frequency has associated therewith a center frequency value, an instantaneous frequency value and a frequency deviation value equal to a difference between the center and instantaneous frequency values, and the measured frequency data represent the instantaneous frequency value. The modulation control circuit is configured to couple to the controllable signal generator circuit, provide modulation data and provide to the controllable signal generator circuit a modulation control signal that controls the instantaneous signal frequency value, wherein the modulation data represent the frequency deviation value. The data processing and control circuit, coupled between the frequency measurement circuit and the modulation control circuit, is configured to couple to the controllable signal generator circuit and receive and process the measured frequency data and the modulation data and in accordance therewith provide to the controllable signal generator circuit at least one frequency control signal that controls the center signal frequency value. 
     In accordance with another embodiment of the present invention, a frequency synthesizer with a digital frequency lock loop (FLL) includes a frequency measurement circuit, a modulation control circuit and a data processing and control circuit. The frequency measurement circuit is configured to couple to a controllable signal generator circuit, receive from the controllable signal generator circuit a controlled signal having a controlled signal frequency and measure the controlled signal frequency and in accordance therewith provide measured frequency data. The controlled signal frequency has associated therewith a center frequency value, an instantaneous frequency value and a frequency deviation value equal to a difference between the center and instantaneous frequency values, and the measured frequency data represent the instantaneous frequency value. The modulation control circuit is configured to couple to the controllable signal generator circuit, provide modulation data and provide to the controllable signal generator circuit corresponding modulation control data that control the instantaneous signal frequency value, wherein the modulation data represent the frequency deviation value. The data processing and control circuit, coupled between the frequency measurement circuit and the modulation control circuit, is configured to couple to the controllable signal generator circuit and receive and process the measured frequency data and the modulation data and in accordance therewith provide to the controllable signal generator circuit frequency control data that control the center signal frequency value. 
     In accordance with still another embodiment of the present invention, a method of frequency synthesis includes the steps of: 
     receiving a controlled signal with a controlled signal frequency having associated therewith a center frequency value, an instantaneous frequency value and a frequency deviation value equal to a difference between the center and instantaneous frequency values; 
     measuring the controlled signal frequency and in accordance therewith generating measured frequency data representing the instantaneous frequency value; 
     generating modulation data representing the frequency deviation value; 
     generating a modulation control signal for controlling the instantaneous signal frequency value; and 
     processing the measured frequency data and the modulation data and in accordance therewith generating at least one frequency control signal for controlling the center signal frequency value. 
     In accordance with yet another embodiment of the present invention, a method of frequency synthesis includes the steps of: 
     receiving a controlled signal with a controlled signal frequency having associated therewith a center frequency value, an instantaneous frequency value and a frequency deviation value equal to a difference between the center and instantaneous frequency values; 
     measuring the controlled signal frequency and in accordance therewith generating measured frequency data representing the instantaneous frequency value; 
     generating modulation data representing the frequency deviation value; 
     generating corresponding modulation control data for controlling the instantaneous signal frequency value; and 
     processing the measured frequency data and the modulation data and in accordance therewith generating frequency control data for controlling the center signal frequency value. 
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, a frequency synthesizer with a digital FLL  100  in accordance with one embodiment of the present invention includes frequency counters,  102 ,  104 , a crystal reference oscillator circuit  106 , a data processing circuit  108  (e.g., a microprocessor), a modulator circuit  110 , a data bank circuit  112  (e.g., memory or other data storage circuitry), DAC circuits  114 ,  116 , a sample-and-hold circuit in the form of a switch  124  and a shunt capacitor  118 , a controllable signal generator circuit  120  (e.g., a voltage controlled oscillator (VCO)), and a frequency multiplier circuit  122  (e.g., a frequency doubler), interconnected substantially as shown. 
     The DACs  114 ,  116  are depicted as being single DAC circuits. However, it will be readily understood that one or both of these DAC circuits  114 ,  116  can be implemented in the form of a dual DAC circuit, thereby providing one DAC circuit for coarse frequency tuning and another DAC circuit for fine frequency tuning. Alternatively, e.g., in the case of the center frequency control DAC  116 , the frequency control data  113   a  presented to the DAC  116  can be used to provide the fine frequency control, while additional frequency control data  113   b  can be presented to a storage element (e.g., register) within the VCO  120  for controlling a band select network (e.g., an array of switched capacitors for controlling the center frequency of a resonant network). 
     Also, while the feedback counter  102  used to count the periods of the output signal  123  is represented as a single counter circuit, it will be readily understood that this counter  102  can be implemented with a fixed or variable prescaler and a fixed or programmable counter in accordance with well-known FLL design techniques. (For example, if the prescaler is used, an appropriate count value can be added to the output data  103  provided by the counter  102  prior to processing within the data processor  108 .) Lastly, the frequency multiplier circuit  122  is not necessary for purposes of the present invention. By using a frequency multiplier circuit  122 , however, frequency pulling of the output of the oscillator  120  is prevented and the frequency accuracy required from the oscillator  120  may be reduced. Accordingly, the output  121  of the oscillator  120  may be used to drive the counter  102  directly. 
     As noted, the output signal  123  (or  121 ) is counted by the feedback counter  102  during a predetermined time interval defined by the occurrences of the assertions of the start  104   a  and stop  104   b  control signals from the time interval counter  104 . Accuracy of this time interval is established by the reference signal  107  from the crystal reference oscillator circuit  106 . (As will be readily appreciated, these start and stop signals  104   a ,  104   b  can be a single signal with each transition between the binary states defining the starting and stopping times for the count sequence in the feedback counter  102 .) The resulting frequency count data  103  is presented to the data processor  108 . 
     During the data transmission time slot, the modulator circuit  110 , in accordance with a modulator control signal  200 , provides modulation control data  111   a  to the modulator DAC  114  which converts this data into the appropriate analog modulation control signal  115  for the oscillator  120 . Modulation data  111   b  is provided to the data processor  108 . This modulation data  111   b  informs the data processor  108  how much the output signal  121  of the oscillator  120  is going to be modulated in frequency. In other words, this modulation data  111   b  represents the amount of frequency deviation of the oscillator output signal  121 . 
     It will be readily appreciated that the modulation control data  111   a  and modulation data  111   b  can be identical or different, depending upon the particular implementation. For example, the modulation control data  111   a  can be established to take into account any known non-linearities or other characteristics of the oscillator  120 , while the modulation data  111   b  can be defined to represent the frequency deviation directly without accounting for any specific characteristics of the particular oscillator  120 . Alternatively, these data  111   a ,  111   b  can be identical with the data processor  108  making any necessary adjustments to account for the characteristics of the oscillator  120 . Further alternatively, these data  111   a ,  111   b  can be identical, with the modulation DAC  114  being designed to introduce any compensation necessary to account for the characteristics of the oscillator  120 . 
     The frequency count data  103  from the feedback counter  102  and the modulation data  111   b  from the modulator  110  are processed together within the data processor  108  to produce measured frequency data  109 . This measured frequency data  109  is used to select the appropriate frequency control data within the data bank  112 . The selected frequency control data  113   a  is used to drive the frequency control DAC  116  which generates the appropriate analog frequency control signal  117  for the oscillator  120 . This analog control signal  117  is sampled by being applied to the capacitor  118  via the switch  124  during the guard time slots. During the data transmission time slots, the switch  124  is open, thereby allowing the modulation control signal  115  to drive the oscillator  120  in an open loop configuration. 
     As should be readily appreciated, by processing the frequency count data  103  from the feedback counter  102  in conjunction with the modulation data  111   b  from the modulator  110 , the data processor  108  can account for, e.g., subtract out, effects of the modulation applied to the oscillator  120 . This allows the current data addressing data  109  to be generated for selecting the appropriate frequency control data within the data bank  112 , thereby, in turn, providing the correct frequency control data  113   a  to the frequency control DAC  116 . 
     Following initial application of power to the frequency synthesizer  100 , the data processor  108  generates a sequence of data  109  to select a sequence of frequency control data  113   a  from the data bank  112 . This causes the oscillator  120  to be sequenced through the various channel frequencies. Each of these channel frequencies is tested (without modulation) so that the data processor  108  can evaluate and, if necessary, modify the frequency control data stored within the data bank  112 . For example, a conventional least means square (LMS) search algorithm can be used to cycle the oscillator  120  through the various channel frequencies and make any necessary adjustments to the frequency control data stored within the data bank  112 . 
     Referring to FIG. 2, as noted above, the frequency control DAC  116  drives the oscillator  120  during each of the guard time slots using the appropriate frequency control data  113   a ,  113   b  which has been compensated for any modulation occurring during the data transmission time slots. During data transmission time slot N, the switch  124  is opened and the modulation DAC  114  modulates the oscillator  120 . During this time slot N, the feedback counter  102  is counting the cycles of the output signal. The resulting frequency count data  103 , which includes “errors” due to the presence of modulation in the output signal, and modulation data  111   b  are processed by the processor  108  during data transmission time slot N+1. The data processor  108  corrects these “errors” using the modulation data  111   b  from the modulator  110 , thereby causing compensated, or corrected, frequency control data  113   a ,  113   b  to be presented to the frequency control DAC  116  and VCO  120 . Accordingly, the correct analog frequency control signal  117  becomes available for driving the oscillator circuit  120  during the next appropriate guard time slot. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.

Technology Category: h