Patent Document

This application claims priority from U.S. Provisional Patent Application No. 60/055,349, entitled, “SLDRAM Architecture,” filed Aug. 11, 1997, naming as inventors Kevin Ryan et al., with Attorney Docket No.  017938-000900 , and under an obligation of assignment to the Assignee of the instant invention. U.S. Provisional Patent Application No. 60/055,349 is incorporated herein by reference for all purposes. 
     This application also claims priority from U.S. Provisional Patent Application No. 60/057,092, entitled, “SLDRAM Architecture,” filed Aug. 27, 1997, naming as inventors David B. Gustavson et al., and under an obligation of assignment to the Assignee of the instant invention. U.S. Provisional Patent Application No. 60/057,092 is incorporated herein by reference for all purposes. 
     This application also claims priority from U.S. Provisional Patent Application No. 60/055,368, entitled, “A High-Speed Memory Interface (SyncLink),” filed Aug. 11, 1997, naming as inventors David B. Gustavson et al., and under an obligation of assignment to the Assignee of the instant invention. U.S. Provisional Patent Application No. 60/055,368 is incorporated herein by reference for all purposes. 
     This application also claims priority from U.S. Patent Application No. 08/909,299, entitled, “Bifurcated Data and Command/Address Communication Bus Architecture for Random Access Memories Employing Synchronous Communication Protocols,” filed Aug. 11, 1997, naming as inventors David B. Gustavson et al., and under an obligation of assignment to the Assignee of the instant invention. U.S. Patent Application No. 08/909,299 is incorporated herein by reference for all purposes. 
    
    
     BACKGROUND OF THE INVENTION 
     FIG. #_ 1  illustrates a memory circuit #_ 100  according to the prior art. The memory circuit #_ 100  includes a controller #_ 110  and DRAMs #_ 120   a, #_ 120     b, . . . , #_ 120 α. The controller #_ 110  and the DRAMs #_ 120  are communicatively connected by means of a data bus #_ 130  and a clock bus #_ 140 . A resistor R   t  #_ 150  ties each of the busses #_ 130  and #_ 140  to a voltage source #_ 160  at a threshold voltage V t . 
     The circuit components #_ 110 , #_ 120  each includes a D latch #_ 1 A 0 , a receive clock buffer #_ 170  and transmit clock and data drivers #_ 180  and #_ 190 . The data input of the D latch #_ 1 A 0  is coupled to the data bus #_ 130 . The clock input of the D latch is coupled to the internal clock signal output from the receive clock buffer #_ 230 . 
     Digital logic implements each of the drivers #_ 170 , #_ 180  and #_ 190 . The input-output function of the drivers is essentially a threshold function. 
     The data bus #_ 130  is a read/write bidirectional link. The circuit #_ 100  uses the bus #_ 130  to transfer write data from the controller #_ 110  to a DRAM #_ 120  and to transfer read data from a DRAM #_ 120  to the controller #_ 110 . 
     The operation of the data bus #_ 130  occurs at a sufficiently high speed to require timing information with both read and write data. The data clock is used to latch the data. 
     FIG. #_ 2  illustrates example clock and data signals #_ 210  and #_ 220 , asserted on the clock and data busses #_ 140  and #_ 130 , as well as an example internal clock signal #_ 230  as received in a receiving device. As FIG. #_ 2  illustrates, the data and clock busses #_ 130  and #_ 140  terminate to the midpoint threshold reference voltage V t . 
     When the memory circuit #_ 100  passes control among the controller #_ 110  and the DRAMs #_ 120 , the device A relinquishing control disables its data output and data clock drivers #_ 180  and #_ 190 . The disabling allows the busses #_ 130 , #_ 140  to return to a high impedance state. The device B taking control begins driving the data and clock busses #_ 130 , #_ 140 . 
     A problem occurs, however, in the device C (which may be the same as A) receiving the data: During the (brief) period of transition of control from one circuit #_ 100  component #_ 110 , #_ 120  to another, the clock input #_ 210  through the buffer #_ 170  can be at a high impedance state at or near the threshold voltage V t . The receiving device C may receive spurious clock edges #_ 250 , corrupting the data received. 
     FIG. #_ 3  illustrates another memory circuit #_ 300  according to the prior art. The memory circuit #_ 300  includes a controller #_ 310  and DRAMs #_ 320   a, #_ 320     b, . . . , #_ 320 β. The controller #_ 310  and the DRAMs #_ 320  are communicatively connected by the data bus #_ 130  and the clock bus #_ 140  tied by resistors R   t  #_ 150  to the voltage source #_ 160 . 
     The data bus #_ 130  is a read/write bidirectional link. The circuit #_ 300  transfers write data from the controller #_ 310  to a DRAM #_ 320  on the bus #_ 130  and transfers read data from a DRAM #_ 320  to the controller #_ 310  on the bus #_ 130 . 
     Each of the circuit #_ 300  components #_ 310 , #_ 320  includes a D latch #_ 1 A 0 , a receive clock buffer #_ 340  and transmit clock and data drivers #_ 180  and #_ 190 . The data input of the D latch #_ 1 A 0  is coupled to the data bus #_ 130 . The clock input of the D latch is coupled to the internal clock signal output from the receive clock buffer #_ 340 . 
     The clock input buffers #_ 340  have input-output functions with hysteresis. As the graph of FIG. #_ 6  shows, the output of a buffer #_ 340  depends on both the input voltage and the history of the input to the buffer. 
     When the memory circuit #_ 100  passes control among the controller #_ 110  and the DRAMs #_ 120 , the device relinquishing control disables its data output drivers #_ 180  and data clock drivers #_ 190 . The disabling allows the busses #_ 130 , #_ 140  to return to a high impedance state. The device taking control begins driving the data and clock busses #_ 130 , #_ 140 . 
     FIG. #_ 6  illustrates the example data signal #_ 210  asserted on the data bus #_ 130  of the circuit #_ 300  and an example internal clock signal #_ 350  as received in a receiving device through a buffer #_ 340 , given the clock signal #_ 210 . As FIG. #_ 6  shows, the hysteretic buffer #_ 340  defeats the spurious clock edges #_ 250 . 
     The buffers #_ 340 , however, also defeat the predetermined matched delay of the data and clock paths using the D latch #_ 1 A 0  and the clock buffer #_ 170 . The mismatch between clock and data also depends on the input slew rate. 
     Further, the hysteretic buffer #_ 340  has less input drive differential for equal amplitude signal. This reduces the speed potential of such a memory circuit. 
     According, there is a need for a memory circuit that, in operation, does not generate spurious clock edges as a clock signal approaches the high impedance state. One objective of the invention is such a memory circuit. 
     These and other objectives of the invention will be readily apparent to one of ordinary skill in the art on the reading of the background above and the description below. 
     SUMMARY OF THE INVENTION 
     Herein is disclosed a memory circuit with glitchless transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads. 
     In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. #_ 1  illustrates a memory circuit according to the prior art; 
     FIG. #_ 2  illustrates sample clock, data and internal clock signals asserted on the clock and data busses of FIG. #_ 1 ; 
     FIG. #_ 3  illustrates a memory circuit according to the prior art; 
     FIG. #_ 4  is a timing diagram illustrating a series of Page Read and Page Write commands issued by the memory controller to the DRAMs 
     FIG. #_ 5  illustrates a memory circuit according to the invention; an 
     FIG. #_ 6  illustrates sample clock, data and internal clock signals asserted on the clock and data busses of FIG. #_ 3 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. #_ 5  illustrates a memory circuit #_ 500  according to one embodiment of the invention. The circuit #_ 500  includes a controller #_ 510  and loads #_ 520 . A load #_ 520  can be a single DRAM device, a buffered module comprising many DRAMs or a similar load. 
     The controller #_ 510  and the loads #_ 520  are communicatively coupled by means of a command link #_ 530 . The unidirectional command link #_ 530  sends command, address and control information to the loads #_ 520 . 
     The controller #_ 510  and the loads #_ 520  are also communicatively coupled by means of a data link #_ 5 A 0 . The bidirectional data link #_ 5 A 0  conveys read and write data between the controller #_ 510  and the loads #_ 520 . The data link #_ 5 A 0  includes a data bus #_ 5 A 1 , a first data clock (and its logical inverse) #_ 5 A 2   a , as well as a second data clock (and its logical inverse) #_ 5 A 2   b . A data clock is single-ended or, as described here, differential. 
     A differential clock #_ 5 A 2  accompanies read and write data packets. (In one embodiment, such clocked packets have a minimum burst length of 4 clock phases (“4N”)). The two sets of DCLKs #_ 5 A 2  allow one circuit component #_ 510 , #_ 520  to pass control of the data link #_ 5 A 0  to another component #_ 510 , #_ 520  with minimum gap. 
     When the circuit #_ 500  passes control of the data link #_ 5 A 0  from one device #_ 510 , #_ 520  to another, the data link #_ 5 A 0  remains at a midpoint voltage level for nominally 2N. Indeterminate logic levels and multiple transitions may appear at the input buffers in the components #_ 510 , #_ 520 . 
     This is acceptable for the data lines DQ #_ 5 A 1  themselves but not for the data clocks #_ 5 A 2  used to strobe data. 
     To address this problem, each data clock #_ 5 A 2  has a 00010 preamble before the clock transition associated with the first bit of the corresponding data. The device #_ 510 , #_ 520  receiving the data enables its DCLK input buffer anytime during the first 000 period. The dummy  10  transition in the preamble removes pulse width-dependent skew from the DCLK signal #_ 5 A 2 . The receiving device #_ 510 , #_ 520  ignores the first rising and falling edges of the DCLK #_ 5 A 2  and begins clocking data on the second rising edge. 
     Providing two data clocks accommodates gapless 4N write bursts to different DRAMs and 4N read bursts from different DRAMs. 
     The controller #_ 510  indicates in each command packet which DCLK #_ 5 A 2  is to be used. 
     The controller #_ 510  transmits CCLK edges coincident with edges of CA and FLAG data. DCLK edges originating from the controller #_ 510  coincide with DQ data. The DRAMs #_ 520  add fractional delay to incoming CCLK and DCLKs #_ 5 A 2  to sample commands and write data at the optimum time. The controller #_ 510  programs the DRAMs #_ 520  to add fractional delay to the DCLKs #_ 5 A 2 , allowing the controller read data input registers to directly strobe in read data using the received DCLK #_ 5 A 2  without the need for any internal delay adjustments. 
     FIG. #_ 4  is a timing diagram illustrating a series of Page-Read and Page-Write commands issued by the memory controller #_ 510  to the DRAMs #_ 520 . (For purposes of illustration, all burst lengths are 4N, although the controller #_ 510  can dynamically mix 4N and 8N bursts.) 
     The read access time to an open bank, the Page-Read Latency, is shown here as 12N. The first two commands Read A #_ 450  and #_ 460  are Page Reads to different banks in the DRAM #_ 520   a . The read data Read A #_ 470  appears on the data bus #_ 5 A 1  along with DCLKO #_ 5 A 2   a . The data clock DCLKO #_ 5 A 2   a  provides the memory controller #_ 510  the necessary edges to strobe in the read data. 
     Since the first two Page-Read commands #_ 450 , #_ 460  are for the same DRAM #_ 520   a , no gap is necessary between the two 4N data bursts #_ 470 , #_ 480 . The DRAM #_ 520   a  itself continuously drives DCLKO #_ 5 A 2   a  without any glitch. However, a 2N gap precedes the data burst #_ 490  for the following Page Read #_ 4 A 0  to DRAM #_ 520   b  to allow for settling of the data link #_ 5 A 0  and for timing uncertainty between the DRAMs #_ 520   a  and #_ 520   b.    
     The circuit #_ 500  inserts a 2N gap any time control of the data link #_ 5 A 0  passes from one device #_ 510 , #_ 520  to another, as in reads to different DRAMs #_ 520  or read-to-write and write-to-read transitions between the DRAMs #_ 520  and the memory controller #_ 510 . The controller #_ 510  creates the 2N gap between data by inserting a 2N gap between commands. The DCLK 1  clock #_ 5 A 2 b accompanies data for the Read B command #_ 4 A 0 , allowing the DRAM #_ 520   b  to begin driving the DCLK lines #_ 5 A 2   b  well in advance of the actual data burst #_ 490 . 
     The next command is a write command #_ 4 B 0  using DCLKO #_ 5 A 2   a  to strobe write data #_ 4 C 0  into the DRAM #_ 520   c . The Page-Write Latency of the DRAM is programmed to equal the Page-Read Latency less 2N. To create a 2N gap between the Read B data #_ 490  and Write C data #_ 4 C 0  on the data link #_ 5 A 0 , the controller #_ 510  delays the Write C command #_ 4 B 0  4N after the Read B command #_ 4 A 0 . 
     Programming write latency in this manner creates an open 4N command slot on the Command Link #_ 530 , which slot may be used for non-data commands such as row open or close, register write or refresh. These non-data commands do not affect the utilization of the data link #_ 5 A 0 . 
     The following read command #_ 4 D 0  to DRAM #_ 520   d  does not use delay to achieve the 2N gap on the data link #_ 5 A 0 . 
     The final burst of three consecutive write commands #_ 4 E 0 , #_ 4 F 0 , #_ 4 G 0  shows that a 2N gap between data bursts is not required when writing to different DRAM devices #_ 520 . Different DCLKs #_ 5 A 2  are used so that each DRAM #_ 520  can identify the start of its write data burst. Since all write data originates from the memory controller #_ 510 , no glitches on the DCLKs #_ 5 A 2  occur. 
     Such embodiments as are described herein are by way of example and not limitation. Modifications to the invention as described will be readily apparent to one of ordinary skill in the art. For example, the number of data clocks can be more than two (and, correspondingly, the FLAG signal more than one bit.) 
     Indeed, the invention described herein is not limited to DRAMs or even to memories. This invention applies to any shared synchronous bus in which a clock accompanies data, as in source synchronous clocking. Accordingly, the scope of the invention is to be determined by the metes and bounds of the claims which immediately follow:

Technology Category: 3