Patent Document

This appln is a Division of Ser. No. 09/281,111, filed Mar. 29, 1999, U.S. Pat. No. 6,288,452. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device and a method for manufacturing it, and in particular to a method for manufacturing a box mark for automatic overlay measurement used in a lithography process. 
     2. Description of the Related Art 
     In semiconductor device manufacture, the lithography process is required to form each of layers of a semiconductor device in a predetermined shape. In this process, it is needed when forming a resist pattern in a certain layer to conduct it while aligning a mask pattern with its underlying layer according to a predetermined standard. The predetermined standard concerning the pattern overlay accuracy is becoming strictly as the semiconductor devices become fine. 
     Hereafter, a box mark for automatic overlay measurement between a mask pattern and its underlying layer used in a conventional lithography process will be described. 
     FIGS. 1A through 1F are sectional views for description of manufacture processes of the conventional method. FIG. 2 is a top view for description of the conventional method. Word lines and bit lines are formed on a semiconductor substrate having devices formed thereon. Thereafter, a capacity contact pattern is formed between word lines and bit lines in a lithography process. Here, the lithography process is shown. 
     As shown in FIG. 1A, element isolation regions  102  are first formed on a semiconductor substrate  101 . 
     Subsequently, as shown in FIG. 1B, word lines  105  each having a polycide structure are formed. At this time, an integral outside box mark  105   a  for automatic misalignment measurement is also formed on a scribe line simultaneously with formation of the word lines  105 . 
     Subsequently, as shown in FIG. 1C, pad polysilicon regions  10  are formed on predetermined areas on the word lines  105 . Thereafter, an oxide film  103  having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on the oxide film  103  to planarize the oxide film  103 . 
     As shown in FIG. 1D, a resist  107  is applied to the surface of the oxide film  103 . By using a mask for forming a contact hole  109  having an inside box mark  11  for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, a misalignment value from the inside box mark  11  formed over the outside box mark  105   a  is read by using an automatic overlay measuring instrument. Thereby, a misalignment value between the word line  105  and the contact hole  109  is measured. 
     In succession, the misalignment value is inputted as an offset value of an aligner. A resist  107  is applied on the surface of the oxide film  103  again, and exposure of the contact hole  109  is conducted. 
     Subsequently, as shown in FIG. 1E, a predetermined region of the oxide film  103  is removed, by using the photoresist  107  formed so as to have a predetermined pattern shape, as a mask, and by using anisotropic etching or the like. A contact hole  109  is thus formed. Furthermore, by way of a predetermined process, WSi is buried in the contact hole  109 , and in addition, WSi serving as a bit line  111  is deposited. 
     Thereafter, in the same way as the word line  105 , exposure and development are conducted by using a mask for forming the bit lines  111  having an integral outside box mark  111   a  for automatic overlay measurement added thereto. The bit lines  111  are thus formed, and the outside box mark  111   a  is newly formed. At this time, misalignment of the bit lines  111  is measured by using the box mark  111   a  formed at the time of contact described before. 
     Subsequently, as shown in FIG. 1F, an oxide film  150  having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on the oxide film  150  to planarize the oxide film  150 . 
     Thereafter, a photoresist film  113  is applied to the surface of the oxide film  150 . By using a mask for forming capacity contacts  114  having an inside box mark  17  for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, by using the automatic overlay measuring instrument, a misalignment value in the X direction (the lateral direction of FIGS. 1A through 1F) is read from the outside box mark  105   a  formed in the process of FIG. 1B, and a misalignment value in the Y direction (the depth direction of FIGS. 1A through 1F) is read from the outside box mark  111   a  formed in the process of FIG.  1 E. Between wiring lines forming the shape of #, the capacity contacts  114  are thus formed. 
     In the above described integral outside box mark for automatic overlay measurement, however, two box marks are required to measure the misalignment values in the X direction (word line) and Y direction (bit line) when forming capacity contacts between word lines and between bit lines. Therefore, there is a problem that it takes a time to measure the misalignment values and analyze the measurement results. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a method for shortening, in the manufacture processes of a semiconductor device, the time for measuring the overlay between the underlying layer and a mask pattern at the time of lithography, and the time for analyzing the measurement result. 
     A semiconductor device according to the present invention has such patterns of a plurality of layers formed on a substrate that respective layers are laminated in predetermined position relations. In the present invention, a first mark disposed at the time of first pattern formation and a second mark disposed at the time of second pattern formation form one misalignment measurement mark, and position aligning for third or subsequent pattern formation is conducted with the misalignment measurement mark. 
     In accordance with another aspect of the present invention, a semiconductor device includes: a first mark forming a part of a misalignment measurement mark disposed in a predetermined position of a substrate at the time of first pattern formation; and a second mark forming another part of said misalignment measurement mark disposed at the time of second pattern formation, wherein the first mark and the second mark form one of the misalignment measurement mark, and the misalignment measurement mark is used for position aligning with a mark of mask side at the time of third or subsequent pattern formation. 
     A manufacture method according to the present invention, said semiconductor device having such patterns of a plurality of layers formed on a substrate that respective layers are laminated in predetermined position relations, includes the steps of: forming a first mark in a predetermined position of the substrate at the time of first pattern formation, the first mark forming a part of a misalignment measurement mark used in a subsequent pattern forming step; forming a second mark forming another part of said misalignment measurement mark at the time of second pattern formation; and positioning and adjusting a mark of mask side at the time of third or subsequent pattern formation by using the misalignment measurement mark produced in previous pattern forming process, and conducting third pattern formation or subsequent pattern formation. 
     In accordance with a method for manufacturing a semiconductor device according to the present invention, a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines, as an outside box mark for automatic overlay measurement formed on a semiconductor substrate. Thereby, a misalignment value from the word line and a misalignment value from the bit line can be measured by using one box mark. As a result, it becomes also possible to shorten the time required for measuring the misalignment values and analyzing the measurement result. Furthermore, by using a #-shaped box mark of slit type, the measurement accuracy can be further improved. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIGS. 1A through 1F are sectional views showing a conventional method for manufacturing a semiconductor device in the order of process; 
     FIG. 2 is a plan view showing a conventional semiconductor device; 
     FIGS. 3A through 3F are sectional views showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of process; 
     FIG. 4 is a plan view showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention; and 
     FIGS. 5A through 5F are sectional views showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention in the order of process. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereafter, preferred embodiments of the present invention will be described concretely by referring to accompanying drawing. FIGS. 3A through 3F are sectional views showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in the order of process. FIG. 4 is its plan view. A method for manufacturing a semiconductor device having at least three wiring layers laminated on a substrate includes the steps of disposing outside box mark (word lines)  205   a  extending in one direction in a predetermined position when forming the word lines  205 , disposing outside box mark (bit lines)  211   a  extending in a direction perpendicular to the outside box mark (word lines) when forming the bit lines  211 , thereby forming one misalignment measurement mark  205   a  and  211   a , disposing an inside box mark  27  on the substrate by using a mask for forming capacity contacts, measuring misalignment values of the misalignment measurement mark and the inside box mark, inputting the values to the aligner as offset values, and forming a pattern of the capacity contacts  214 . 
     In the same way as the conventional example, the first embodiment shows a lithography process for forming a pattern of capacity contacts  214  arranged between word lines  205  and bit lines  211 , after the word lines and the bit lines  211  have been formed on a semiconductor substrate  201  having elements formed thereon. 
     As shown in FIG. 3A, device isolation regions  202  are first formed on the semiconductor substrate  201 . 
     Subsequently, as shown in FIG. 3B, word lines  205  each having a polycide structure are formed. At this time, an outside box mark (word lines)  205   a  for automatic misalignment measurement is also formed on scribe lines  204  simultaneously with formation of the word lines  205 . 
     Thereafter, as shown in FIG. 3C, pad polysilicon regions  20  are formed on predetermined areas on the word lines  205 . Thereafter, an oxide film  203  having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on the oxide film  203  to planarize the oxide film  203 . 
     As shown in FIG. 3D, a resist  207  is applied to the surface of the oxide film  203 . By using a mask for forming a contact hole  209  having an inside box mark  21  for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, a misalignment value from the inside box mark  21  formed over the outside box mark (word lines)  205   a  is read by using an automatic overlay measuring instrument. Thereby, a misalignment value between the word line  205  and the contact hole  209  is measured. 
     In succession, the misalignment value is inputted as an offset value of an aligner. A resist  207  is applied on the surface of the oxide film  203  again, and exposure of the contact hole  209  is conducted. 
     Subsequently, as shown in FIG. 3E, a predetermined region of the oxide film  203  is removed, by using the photoresist  207  formed so as to have a predetermined pattern shape, as a mask, and by using anisotropic etching or the like. A contact hole  25  is thus formed. Furthermore, by way of a predetermined process, WSi is buried in the contact hole  25 , and in addition, WSi serving as a bit line  211  is deposited. 
     Thereafter, in the same way as the word line  205 , exposure and development are conducted by using a mask for forming the bit lines having an outside box mark (bit lines)  211   a  for automatic overlay measurement added thereto. The bit lines  211  are thus formed, and in addition the outside box mark (bit lines)  211   a  is formed so as to overlie the outside box mark  205   a  formed of word lines. At this time, misalignment of the bit lines  211  is measured by using the outside box mark (bit lines)  211   a  formed at the time of contact described before. 
     Subsequently, as shown in FIG. 3F, an oxide film  250  having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on the oxide film  250  to planarize the oxide film  250 . 
     Thereafter, a photoresist film  213  is applied to the surface of the oxide film  250 . By using a mask for forming capacity contacts having an inside box mark  213   a  for automatic overlay measurement added thereto, exposure and development are conducted by using a mask for forming capacity contacts. Thereafter, by using the automatic overlay measuring instrument, the #-shaped outside box mark ( 205   a  and  211   a ) formed of the word lines  205  and the bit lines  211 , and the inside box mark  213   a  are measured. Thereby, a misalignment value in the X direction (the lateral direction of FIGS. 3A through 3F) is read from the outside box mark  205   a  formed of the word lines, and a misalignment value in the Y direction (the depth direction of FIGS. 3A through 3F) is read from the outside box mark  211   a  formed of the bit lines  211 . Between wiring lines forming the shape of #, the capacity contacts  214  are thus formed. 
     By referring to FIGS. 5A through 5F, a second embodiment of the present invention will now be described. 
     Processes in the second embodiment are basically the same as those in the first embodiment. Principally, changed points will now be described. 
     In the second embodiment, device isolation regions  302  are formed on a semiconductor substrate  301  in the same way as FIG. 3A, and thereafter an outside box mark (word lines)  305   a  of slit type for automatic overlay measurement is formed on scribe lines simultaneously with formation of the word lines  305  as shown in FIG.  5 B. 
     Thereafter, pad polysilicon regions  30  and an oxide film  303  are formed in the same way as FIGS. 3C through 3D. 
     By using a resist  307  formed in a predetermined shape, as a mask, a predetermined area of the oxide film  303  is removed by anisotropic etching or the like and a contact hole  35  is formed as shown in FIGS. 5D and 5E. 
     At this time, the oxide film  303  is buried in the outside box mark (word lines)  305   a  of slit type for automatic overlay measurement formed on the scribe lines simultaneously with the word lines  305 . Thereafter, exposure and development are conducted by using a bit line forming mask having an outside box mark (bit lines)  311   a  for automatic overlay measurement added thereto. Thus, bit lines  311  are formed, and in addition, the outside box mark (bit lines)  311   a  is formed so as to overlie the outside box mark (word lines)  305   a  of slit type formed of the word lines  305 . 
     As a result, edges of a #-shaped box mark formed by the outside box mark (word lines)  305   a  of slit type and outside box mark (bit lines)  311   a  become sharp. And the overlay measurement accuracy of the automatic overlay measuring instrument is improved. 
     Furthermore, by changing the outside box mark (bit lines)  311   a  as well to a box mark of slit type, a further improvement of the measurement accuracy can be expected. 
     In the embodiments heretofore described, capacity contacts formed between word lines and between bit lines have been described. However, it can be applied between other processes as well in the same way.

Technology Category: 5