Patent Document

[0001]    This application is a continuation of U.S. patent application Ser. No. 10/971,374 filed on Oct. 22, 2004, which is a divisional of U.S. patent application Ser. No. 10/269,202 filed on Oct. 10, 2002, now issued as U.S. Pat. No. 6,825,511, which claims the benefit of foreign priority to Korean Patent Application No. 2001-0068159, filed on Nov. 2, 2001, the disclosures of all of which are herein incorporated by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to semiconductor devices. More particularly, this invention relates to a semiconductor device having a redundancy circuit and a fuse circuit, as well as to methods of fabricating the same. 
         [0004]    2. Description of the Related Art 
         [0005]    As design rules of semiconductor memory devices decrease, high-density memory devices (e.g., 256 MB Dynamic Random Access Memories (DRAMs)) have become popular. In high-density memory devices, a memory device will not operate properly even if only one of its many memory cells is defective. Unfortunately, however, as the integration density of DRAMs increases, the probability of a defect occurring in the memory cells also increases. This can therefore significantly decrease the total yield of semiconductor device fabrication, even if only a few memory cells turn out to be defective. In a conventional method of increasing the yield, defective cells are replaced using a redundant memory cell circuit included in each of the semiconductor devices. 
         [0006]    This method has been applied primarily to DRAMS (e.g., 64-256 MB DRAMs). According to this method, if main cells are defective, addresses allotted to the defective main cells are replaced by addresses (e.g., column/row lines) corresponding to redundant cells in a redundant memory cell circuit. Accordingly, when a wafer fabrication process is completed, an electrical test is used to distinguish between defective memory cells and normal main cells. The addresses of the defective memory cells are then replaced with addresses of replacement cells in the redundant memory cell circuit through a repair process, such as a laser repair process, for example. The laser repair process is performed by cutting fuses in a fuse circuit that connects main cells to redundant cells. 
         [0007]    Accordingly, during operation, when an address corresponding to a defective cell is input, the address of the defective cell is replaced with a preliminary address in the redundant memory cell circuit. The semiconductor memory device can thereby operate properly despite the presence of defective memory cells. 
         [0008]      FIG. 1  is a schematic diagram of a conventional semiconductor device having a fuse circuit. Referring to  FIG. 1 , a general memory circuit (e.g., DRAM) of the conventional semiconductor device, is divided into a cell region  30  and a peripheral region  40 . Memory cells are formed in the cell region  30 . The number of memory cells corresponds to the storage capacity of the memory circuit. A decoder is used to operate unit cells in the cell region  30 . A buffer circuit, a redundancy circuit, and a fuse circuit  14 ′ are formed in the peripheral region  40 . The peripheral region  40  includes all of the regions of the memory circuit except for the cell region  30 . 
         [0009]    A pad redistribution pattern  22  is a conductive pattern used to redistribute a pad  16  formed under a passivation layer  18  of a semiconductor device. The pad redistribution pattern  22  is used in manufacturing a wafer level package (WLP).  FIG. 2  is a cross-sectional view of a conventional semiconductor device used to form a WLP having a fuse circuit. Referring to  FIG. 2 , a DRAM device having a conventional fuse circuit is manufactured by forming a lower structure  12  on a semiconductor substrate  11 . The lower structure  12  can be a DRAM circuit having a cell region and a peripheral region. The lower structure  12  includes a gate electrode, a bit line, a capacitor, and a metal wiring layer (not shown). A pad  16  is formed to provide an external contact for the DRAM circuit. A passivation layer  18  and a first insulating layer  20  are sequentially formed on the resulting structure and are patterned to expose the pad  16 . 
         [0010]    A pad redistribution pattern  22  is formed on the first insulating layer  20  and is connected to the pad  16 . A second insulating layer  24  is then formed to expose a predetermined portion of the pad redistribution pattern  22 , to which an external connection terminal can be attached. The external connection terminal used in the WLP process can, for example, be a conductive bump, e.g., a solder ball, or any other suitable external connection terminals. 
         [0011]    Unfortunately, conventional semiconductor devices with fuse circuits have several problems. Among others, since a fuse circuit  14  occupies a predetermined area in a peripheral region of a semiconductor memory device, there is a limit to the amount by which the integration density of the semiconductor memory device can be increased. 
         [0012]    In addition, when manufacturing a small outline package (SOP) or a quad flat package (QFP), there is no need to form the first insulating layer  20 , the pad redistribution pattern  22 , and the second insulating layer  24  on the passivation layer  18 . Accordingly, for these devices, it is not difficult to cut a fuse pattern  14  under the passivation layer  18  using laser beams. When manufacturing a WLP, however, the first insulating layer  20 , pad redistribution pattern  22 , and the second insulating layer  24  are formed on the passivation layer  18 . There is accordingly a much greater distance between the top surface of the semiconductor memory device, to which laser beams are applied, and the fuse pattern  14 . Problems may therefore occur during a laser repair process. For example, the laser beams applied to the top surface of the semiconductor memory device may be out of focus. To correct this problem, the width of the fuse pattern  14  is increased. This decreases the integration density of the semiconductor memory device. 
       SUMMARY OF THE INVENTION 
       [0013]    The present invention provides a semiconductor device that can be highly integrated easily and can solve problems occurring in a laser repair process. 
         [0014]    According to one embodiment of the present invention, a semiconductor device includes a semiconductor substrate, a cell region formed on a predetermined portion of the semiconductor substrate, a peripheral region formed on the other portion of the semiconductor substrate, and a fuse circuit formed in the cell region. 
         [0015]    According to the present invention, since a fuse circuit is installed in not a peripheral region but a cell region of a semiconductor memory device having a redundancy circuit and the fuse circuit, it is possible to increase the integration density of the semiconductor memory device. In addition, according to one embodiment of the present invention, since the fuse circuit is formed overlying a passivation layer not under the passivation layer, it reduces problems that may occur in cutting the fuse circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0016]    The foregoing objects and advantages of the present invention will become more readily apparent through the following detailed description of preferred embodiments thereof, made with reference to the attached drawings, in which: 
           [0017]      FIG. 1  is a schematic plan view of a conventional semiconductor device having a fuse circuit; 
           [0018]      FIG. 2  is a cross-sectional view of a conventional semiconductor device having a fuse circuit; 
           [0019]      FIG. 3  is a schematic plan view of a semiconductor device having a fuse circuit according to one embodiment of the present invention; 
           [0020]      FIG. 4  provides schematic cross-sectional views a conventional semiconductor device (taken along line A-A′ of  FIG. 1 ) and a semiconductor device constructed according to principles of the present invention (taken along line B-B′ of  FIG. 3 ) to provide a size comparison; 
           [0021]      FIGS. 5 through 8  are cross-sectional views of the semiconductor device of  FIG. 3 , illustrating a method of fabricating the same; 
           [0022]      FIGS. 9 through 12  are cross-sectional views of a semiconductor device constructed according to another embodiment of the invention, illustrating a method of fabricating the same; and 
           [0023]      FIGS. 13 and 14  are cross-sectional views of a fuse pattern illustrating alternative fuse circuit embodiments, according to further principles of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0024]    The present invention will now be described more fully with reference to various preferred embodiments of the invention as shown in the accompanying drawings. It should be noted, however, that the principles of the present invention may be embodied in many different forms and should not be construed as being limited to the particular embodiments set forth herein. Rather, these embodiments are provided simply by way of example, and not of limitation. 
         [0025]    Accordingly, various changes in form and details may be made to the described embodiments without departing from the spirit and scope of the invention as defined by the appended claims. Among others, the principles of the invention apply to many types of semiconductor devices and are not limited to any particular type of device, such as a DRAM. The present invention can, for instance, be applied to a ferroelectric random access memory (FRAM), a static random access memory (SRAM), and a non-volatile memory (NVM), as well as a DRAM. In addition, although a solder ball can be used to provide an external connection terminal, other suitable external connection could also be used. 
         [0026]      FIG. 3  illustrates a semiconductor device  100  having a fuse circuit  116  formed therein according to an embodiment of the present invention. Referring to  FIG. 3 , unlike in the prior art in which a fuse circuit is formed in a peripheral region, a fuse circuit  116  according to this embodiment is formed in a cell region  122 . A pad redistribution pattern  110  can also be primarily located in the cell region  122 . 
         [0027]      FIG. 4  includes a cross-sectional view of a conventional semiconductor device  10 , taken along line A-A′ of  FIG. 1 , and a cross-sectional view of a semiconductor device  100  embodying principles of the present invention, taken along line B-B′ of  FIG. 3 . These cross-sectional views provide a comparison between the integration densities of the two devices. As can be seen from  FIG. 4 , by moving the fuse circuit  116  from the peripheral region  124  to the cell region  122 , the area of a semiconductor device can be reduced by an amount D. The distance D corresponds to a reduced amount of area on the surface of the semiconductor device, and results in an increase in the number of chips that can be arranged on one wafer. 
         [0028]    Referring to  FIGS. 3 and 4 , the semiconductor device  100  having a redundant circuit and a fuse circuit  116  according to an embodiment of the present invention includes a semiconductor substrate  101  having a cell region  122  and a peripheral region  124  formed on predetermined areas thereof. A fuse circuit  116  is formed in the cell region  122 .  FIGS. 5 through 8  are cross-sectional views illustrating a method of fabricating a semiconductor device  100  having a fuse circuit  116  formed in a cell region  122  thereof, according to one embodiment of the present invention. In addition, as shown in  FIGS. 5 through 8 , a pad redistribution pattern  110  can convert a center-type bond pad into a peripheral bond pad. 
         [0029]    Referring to  FIG. 5 , a lower structure  102 , for example, a DRAM circuit unit, which includes a field oxide layer, a gate electrode, a bit line, a capacitor, and a metal wiring layer, (not shown for simplicity) is formed in a peripheral region and a cell region of a semiconductor substrate  101 . Next, a passivation layer  106  is deposited on the lower structure  102  and is patterned to expose a pad  104 . 
         [0030]    Referring to  FIG. 6 , a conductive layer, used to form a pad redistribution pattern  110 , is formed on the passivation layer  106 . The conductive layer can be chrome (Cr), copper (Cu), nickel (Ni), gold (Au), aluminium (Al), titanium (Ti), and/or titanium nitride (TiN). Next, the conductive layer is patterned to form the pad redistribution pattern  110  and a fuse pattern  116   a.    
         [0031]    The pad redistribution pattern  110  and the fuse pattern  116   a  can be formed on substantially the same plane but preferably do not overlap with each other. In this embodiment, the pad redistribution pattern  110  converts a center-type bond pad into a peripheral bond pad. The fuse pattern  116  is preferably formed in the cell region, not in the peripheral region. Another passivation layer  107  is preferably formed on the semiconductor substrate  101 , after the pad redistribution pattern  110  has been formed. This passivation layer  107  can be patterned to expose a peripheral bond pad  126 . 
         [0032]      FIG. 7  illustrates the conversion of the center-type bond pads to the peripheral bond pads. Referring to  FIG. 7 , the semiconductor device  100 A having center-type bond pads  104  is converted to a device  100 B having peripheral bond pads  126 , using the pad redistribution pattern. In other words, the semiconductor device  100 A does not include the pad redistribution pattern  110 , while the device  100 B has been converted into a peripheral bond pad device from the center-type bond pad device  100 A by forming a pad redistribution pattern. 
         [0033]    Referring to  FIG. 8 , a ball bond  128  is formed using wires, for example, gold wires, on the exposed peripheral bond pad  126  to permit external electrical connection of the semiconductor device  100 . The passivation layers  106  and  107  may be formed as a single layer or a multi-layer and may also be embodied in different forms. 
         [0034]      FIGS. 9 through 12  are cross-sectional views of a semiconductor device  100 C having a fuse circuit formed in cell region at various steps during its fabrication. These figures illustrate a method of fabricating a semiconductor device according to another embodiment of the present invention. In this embodiment, a pad redistribution pattern is introduced to form a solder ball pad. 
         [0035]    Referring to  FIG. 9 , a lower structure  102 , for example, a DRAM circuit unit, is formed in a peripheral region and a cell region of the semiconductor device  100 C on a substrate  101 . The lower structure  102  preferably includes a field oxide layer, a gate electrode, a bit line, a capacitor, and a metal wiring layer. Next, a passivation layer  106  is deposited on the semiconductor substrate  101  over the lower structure  102  and is patterned to expose a pad  104 . 
         [0036]    Referring to  FIG. 10 , a first insulating layer  108  is formed on the passivation layer  106 . The first insulating layer  108  may be a single layer or a multi-layer made of a high-density plasma (HDP) oxide layer, a benzicyclobutene (BCB) layer, a polybenzoxazole (PBO) layer, and/or a polyimide layer, for example. 
         [0037]    Next, a patterned photoresist layer is formed on the first insulating layer  108 . The first insulating layer  108  and the passivation layer  106  are patterned by photolithography and etching to form a via hole therethrough to be connected to a bit line or word line. The via hole is then filled with a conductive material, thereby forming a plug  112 . 
         [0038]    A conductive layer is formed on the resulting structure. The conductive layer is patterned to form the pad redistribution pattern  110  and the fuse pattern  116   a  simultaneously in the same process. The conductive layer may be a single layer or a multi-layer containing tungsten (W), chrome (Cr), titanium (Ti), and/or titanium tungsten (TiW). 
         [0039]    In the prior art, a fuse circuit, including the fuse pattern  116   a , is formed by extending bit line/word line wiring layers of the lower structure  102  to a peripheral region. In the foregoing embodiments of the present invention, however, the fuse pattern  116   a  is formed in a cell region. 
         [0040]    Referring to  FIG. 11 , a second insulating layer  114  is formed on the first insulating layer  108 . The second insulating layer  114  may be a single layer or a multi-layer containing a polyimide, for example. A patterned photoresist layer is then formed on the second insulating layer  114 . The second insulating layer is then patterned by photolithography and etching to form a solder ball pad  118 , through which a predetermined portion of the pad redistribution pattern  110  is exposed. 
         [0041]    Referring to  FIG. 12 , a laser repair process can then be performed on the resulting structure, including the semiconductor substrate  101 , on which the solder ball pad  118  has been formed, in which a fuse pattern  116   b  is selectively cut. In this process, cells in a cell region that are identified as defective cells through an electrical test can be replaced by redundant memory cells in a redundancy circuit. An external connection terminal, for example, a conductive bump, e.g., a solder ball  120 , can then be attached to the resulting structure after the laser repair process is completed. Other external connections can be used instead of the solder ball  120 . 
         [0042]    In the prior art, since the fuse pattern is arranged under the passivation layer  106 , it is difficult to selectively cut the fuse pattern by irridating laser beams to the fuse pattern through the passivation layer  106 . This is because the laser beams may be out of focus. Thus, the width of the fuse pattern  116   b  needs to be increased. According to principles of the present invention, however, because the fuse pattern  116   b  is formed close to the top surface of a semiconductor device, the distance traveled by the laser beams to reach the fuse pattern  116   b  can be reduced. Thus, the problem of the prior art, in which laser beams are out of focus, can be solved. In addition, since the fuse pattern  116   b  is formed not in a peripheral region but rather in a cell region, the integration density of a semiconductor device can be increased. 
         [0043]      FIGS. 13 and 14  are cross-sectional views illustrating alternative embodiments of a fuse pattern of a fuse circuit according to another aspect of the present invention. In the previously described embodiments, the fuse pattern  116   b  is formed having almost the same thickness as the pad redistribution pattern  110 . In this alternative embodiment, however, a pad redistribution pattern  210  is formed of chrome (Cr), copper (Cu), nickel (Ni), gold (Au), aluminium (Al), titanium (Ti), and/or titanium nitride (TiN) as a multi-layer on a first insulating layer  208 . A fuse pattern  216 A is then etched so that the thickness of the fuse pattern  216 A is substantially less than the thickness of the pad redistribution pattern  210 . Accordingly, it becomes easier to cut the fuse pattern  216 A using laser beams. It is thereby possible to increase the yield of a semiconductor device in a laser repair process. The fuse pattern  216 A having a smaller thickness than the pad redistribution pattern  210  may be formed of chrome (Cr), copper (Cu), nickel (Ni), gold (Au), aluminium (Al), titanium (Ti), and/or titanium nitride (TiN) in a single layer or a multi-layer. A second insulating layer  214  can also be provided. 
         [0044]    As described above, according to various embodiments of the present invention, a chip is designed so that a fuse circuit can be located in a cell region, not a peripheral region, to increase the integration density of a semiconductor memory chip. In addition, by forming the fuse circuit on a passivation layer, the problem of the prior art, in which laser beams applied in a laser repair process to cut a fuse pattern are out of focus, can be solved. Furthermore, because the fuse pattern is formed to have a smaller thickness than a pad redistribution pattern through etching, it is possible to easily perform a fusing process. 
         [0045]    While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Category: h