Patent Document

FIELD OF THE INVENTION 
     This invention relates to integrated circuit devices, and more particularly to testing of integrated circuit devices. 
     BACKGROUND OF THE INVENTION 
     Integrated circuit devices, such as integrated circuit memory devices and integrated circuit logic devices, are widely used in consumer and commercial applications. 
     Recently, merged memory and logic (MML) integrated circuits have been developed. MML integrated circuits generally include a large capacity memory and a large logic block that are merged in one integrated circuit. The large capacity memory is generally divided into a plurality of memory blocks, also referred to as “memories”. The logic block may also be referred to as a “logic circuit” or simply as a “logic”. Thus, an MML integrated circuit can replace discrete memory and logic chips that are used in personal computers and other consumer and commercial devices. 
     MML integrated circuits present new challenges for the testing thereof. In particular, the MML integrated circuit generally provides a large number of internal data pads between the memory block and the logic block. For example, up to 256 or more internal pads may be provided. Since many of these internal pads are not brought out to external MML integrated circuit pads, it may be difficult to access all of the internal data pads in order to test the memory block. 
     Stated differently, in order to test a conventional memory integrated circuit, test equipment is connected to the pads of the memory integrated circuit. However, the memory block in an MML integrated circuit may be difficult to test because the memory is connected to the external pads through the logic block. Accordingly, additional pads may be needed to test the memory of the MML integrated circuit. Unfortunately, the addition of large numbers of test pads may increase the cost, size and/or complexity of the MML integrated circuit. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide improved testing circuits and methods for MML integrated circuits. 
     It is another object of the present invention to provide testing methods and circuits for MML integrated circuits that can reduce the number of additional pads that are used for memory testing. 
     These and other objects are provided, according to the present invention, by providing a memory test control circuit in an MML integrated circuit. The memory test control circuit is connected to a first pad which receives memory control signals to control first and second memories of the MML circuit. The memory test control circuit is also connected to a second pad which receives memory data signals for the first and second memories. The memory test control circuit is also connected to the logic block and to the first and second memories. The memory test control circuit transmits the memory control signals and the memory data signals to the first and second memories when the first and second memories are tested and transmits the memory control signals and the memory data signals to the logic block during normal operation of the MML integrated circuit. Accordingly, the memory test control circuit allows pass-through of memory data and control signals directly to the memory blocks during test mode, and provides the memory data and control signals to the logic block during normal operations. 
     In a preferred embodiment of the present invention, the memory test control circuit includes means for generating a first control signal to indicate a test of a first one of the memory blocks, for generating a second control signal to indicate a test of the second one of the plurality of memory blocks, and for generating a third control signal to indicate the normal operation mode for the MML integrated circuit, in response to the test control signal. First means for controlling the first and second memory blocks and the logic block is provided. The first means transmits the memory control signals from the first pad to the first memory block in response to the first control signal, transmits the memory control signals from the first pad to the second memory block in response to the second control signal and transmits the memory control signals from the first pad to the logic block in response to the third control signal. Second means for controlling the first and second memory blocks and the logic block is also provided. The second means transmits the memory data signals from the second pad to the first memory block in response to the first control signal, transmits the memory data signals from the second pad to the second memory block in response to the second control signal and transmits the memory data signals from the second pad to the logic block in response to the third control signal. Analogous methods of operating MML integrated circuits are also provided. 
     The memory test control circuit may include a memory control signal controller that transmits the memory control signals from the first pads to the first and second memories and to the logic block. The memory data controller transmits the memory data signals from the second pad to the first and second memories and transmits memory data signals generated from the first and second memories and the logic block to the second pad. A main control signal generator is connected to the memory control signal controller and to the memory data controller. The main control signal generator generates main control signals to control transmission of the memory control signals to the first and second memories and to the logic block in response to a test control signal, to control transmission of the memory data signals to the first and second memories and the logic block and to control transmission of the memory data signals generated from the first and second memories and the logic block to the second pad. Preferred embodiments of the memory control signal controller, the memory data controller and the main control signal generator are also provided. Accordingly, testing of memory blocks in an MML integrated circuit may be accomplished without the need to add large numbers of pads to the MML integrated circuit for internal access to the memory blocks. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a merged memory and logic (MML) integrated circuit according to a first embodiment of the present invention; 
     FIG. 2 is a block diagram according to the first embodiment of a memory test control circuit of FIG. 1; 
     FIG. 3 is a circuit diagram of a memory control signal controller of FIG. 2; 
     FIG. 4 is a circuit diagram of a memory data controller of FIG. 2; 
     FIG. 5 is a block diagram according to a second embodiment of a memory test control circuit of FIG. 1; 
     FIG. 6 is a circuit diagram of a memory control signal controller of FIG. 5; 
     FIG. 7 is a circuit diagram of a first memory data controller of FIG. 5; and 
     FIG. 8 is a circuit diagram of a second memory data controller of FIG.  5 . 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. 
     FIG. 1 is a block diagram of a merged memory and logic (MML) integrated circuit according to a preferred embodiment of the present invention. Referring to FIG. 1, the MML integrated circuit  5  includes pads  7 ,  8 ,  9  and  10 , a memory test control circuit  13 , a logic block  15  (also referred to herein as a logic or a logic circuit) and first and second memory blocks (also referred to herein as memories). 
     The memory test control circuit  13  is connected to the pads  7 ,  8 ,  9  and  10 , and the logic  15 . The first and second memories  17  and  19 , e.g., DRAM banks, are also connected to the memory test control circuit  13 . 
     A memory control signal PC for controlling the first and second memories  17  and  19  is applied to the first pad  8 , and test control signals TESTMD 0  and TESTMD 1  for controlling the memory test control circuit  13  are applied to the pads  9  and  10 . Also, a memory data signal DQi is input/output to the first and second memories  17  and  19  is applied to the second pad  7 . The pads  7  and  8  preferably are existing pads for using the first and second memories  17  and  19 , and the pads  9  and  10  may be added pads to control the memory test control circuit  13 . 
     A memory tester is connected to the pads  7 ,  8 ,  9  and  10  to test functions of the first and second memories  17  and  19  of the MML device  5 . The memory tester inputs the memory control signal PC and the memory data signal DQi to the memory test control circuit  13  through the pads  7  and  8 . Also, the memory test control circuit  13  is controlled by a combination of the test control signals TESTMD 0  and TESTMD 1 . Accordingly, in the testing of the first and second memories  17  and  19 , the memory test control circuit  13  applies the memory control signal PC and the memory data signal DQi to the first and second memories  17  and  19 . The first and second memories  17  and  19  operate by the memory control signal PC and the memory data signal DQi, and then the result is transmitted to the memory test control circuit  13 . The memory test control circuit  13  transmits signals from the first and second memories  17  and  19  to the memory tester through the pads  7  and  8 . Accordingly, the memory tester can analyze signals transmitted through the pads  7  and  8  to evaluate the functions of the first and second memories  17  and  19 . 
     When the MML  5  operates normally without testing the first and second memories  17  and  19 , the memory test control circuit  13  is partially disabled due to the combination of test control signals TESTMD 0  and TESTMD 1 . When the memory control signal PC and the memory data signals DQis are applied externally to perform normal operation of the MML  5 , the applied signals are input to the logic  15 , which controls the first and second memories  17  and  19  through the memory test control circuit  13 . 
     The embodiment of the present invention illustrated in FIG. 1 is employed for a merged memory logic device having two memories, however, the invention may be employed for a merged memory logic semiconductor device having one or more memories. Moreover, the number of pads that are used can vary. 
     As described above, a merged memory logic semiconductor device  5  according to an embodiment of the present invention may test the first and second memories  17  and  19  using the conventional pads  7  and  8 . 
     FIG. 2 is a block diagram of a memory test control circuit  13  of FIG. 1 according to a first embodiment. Referring to FIG. 2, the memory test control circuit  13  according to the first embodiment includes a main control signal generator  23 , a memory control signal controller  25  and a memory data controller  27 . 
     In the main control signal generator  23 , the test control signals TESTMD 0  and TESTMD 1  are applied to an input terminal, and an output terminal is connected to the memory control signal controller  25  and the memory data controller  27 . The main control signal generator  23  generates main control signals MEMTEST 1 , MEMTEST 2  and NORMAL, in response to the test control signals TESTMD 0  and TESTMD 1 . For example, the main control signal generator  23  has truth values as shown in Table 1. 
     
       
         
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Function 
                 TESTMD0 
                 TESTMD1 
                 Main control signal 
               
               
                   
               
             
             
               
                 First memory test 
                 ‘L’ 
                 ‘L’ 
                 MEMTEST1 
               
               
                 Second memory test 
                 ‘H’ 
                 ‘L’ 
                 MEMTEST2 
               
               
                 Normal operation 
                 ‘L’ 
                 ‘H’ 
                 NORMAL 
               
               
                   
                 ‘H’ 
                 ‘H’ 
                 Hold present state 
               
               
                   
               
             
          
         
       
     
     As shown in Table 1, when the test control signals TESTMD 0  and TESTMD 1  are logic low ‘L’, the main control signal MEMTEST 1  is made active to test the first memory  17  of FIG. 1, and when the test control signal TESTMD 0  is activated to logic high ‘H’ and the test control signal TESTMD 1  is logic low ‘L’, the main control signal MEMTEST 2  is active to test the second memory  19  of FIG.  1 . Also, when the test control signal TESTMD 0  is logic low ‘L’ and the test control signal TESTMD 1  is logic high ‘H’, a signal NORMAL is active to normally operate the logic  15  of FIG.  1 . When the test control signals TESTMD 0  and TESTMD 1  are logic high ‘H’, the previous state is maintained. 
     The memory control signal controller  25  receives the memory control signal PC applied through the pad  8 , and is controlled by the main control signals MEMTEST 1 , MEMTEST 2  and NORMAL to transmit the memory control signal PC to the first and second memories  17  and  19  of FIG.  1  and to the logic  15  of FIG.  1 . The memory control signal PC includes a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, an output enable signal OEB, and an address signal Ai. 
     The memory data controller  27  receives the memory data signal DQi applied through the pad  7 , and is controlled by the main control signals MEMTEST 1 , MEMTEST 2  and NORMAL to transmit the memory data signal DQi input externally to the first and second memories  17  and  19  of FIG. 1 or the logic  15  of FIG. 1, and to transmit the memory data signal DQi generated from the first and second memories  17  and  19  of FIG. 1 or the logic  15  of FIG. 1 to the pad  7 . 
     As described above, the memory test control circuit  13  according to the first embodiment of the present invention may test the first and second memories  17  and  19  of FIG. 1 using the conventional pads  7  and  8  of FIG. 1 without the logic  15 . 
     FIG. 3 is a circuit diagram of a memory control signal controller  25  of FIG.  2 . Referring to FIG. 3, the memory control signal controller  25  includes a buffer  31 , a logic gate  33  and a memory controller  35 . 
     The buffer  31  receives a memory control signal PC, and transmits the output to the logic gate  33 . The buffer  31  changes the voltage level of the memory control signal PC. For example, a voltage of a transistor transistor logic (TTL) level is converted into a voltage of a complementary metal oxide semiconductor (CMOS) level. 
     The logic gate  33  receives an output of the buffer  31 , and transmits the output to the memory controller  35 . The logic gate  33  includes first through third AND gates  33   a ,  33   b  and  33   c.    
     The first AND gate  33   a  receives the output of the buffer  31  and the main control signal MEMTEST 1 . When the output of the buffer  31  or the main control signal MEMTEST 1  is logic low, the first AND gate  33   a  generates a logic low signal, and when the output of the buffer  31  and the main control signal MEMTEST 1  are logic high, the first AND gate  33   a  generates a logic high signal. 
     The second AND gate  33   b  receives the output of the buffer  31  and the main control signal NORMAL and transmits the output to the logic  15  of FIG.  1 . When the output of the buffer  31  or the main control signal NORMAL is logic low, the second AND gate  33   b  generates a logic low signal, and when the output of the buffer  31  and the main control signal NORMAL are logic high, the second AND gate  33   b  generates a logic high signal. 
     The third AND gate  33   c  receives the output of the buffer  31  and the main control signal MEMTEST 2 . When the output of the buffer  31  or the main control signal MEMTEST 2  is logic low, the third AND gate  33   b  generates a logic low signal, and when the output of the buffer  31  and the main control signal MEMTEST 2  are logic low, the third AND gate  33   c  generates a logic high signal. 
     The memory controller  35  includes first and second multiplexers  35   a  and  35   b.    
     A 2-input, 1-output multiplexer is used as the first multiplexer  35   a . The first multiplexer  35   a  receives the output of the first AND gate  33   a  and the output of the logic  15  of FIG. 1, and is controlled by the main control signals NORMAL and MEMTEST 1 , to transmit the output of the first AND gate  33   a  and the output of the logic  15  of FIG. 1 to the first memory  17  of FIG.  1 . That is, when the main control signal NORMAL is active, the first multiplexer  35   a  transmits signals generated from the logic  15  of FIG. 1 to the first memory  17  of FIG. 1, and when the main control signal MEMTEST 1  is active, the first multiplexer  35   a  transmits the signals generated from the first AND gate  33   a  to the first memory  17  of FIG.  1 . 
     A 2-input, 1-output multiplexer is used as the second multiplexer  35   b . The second multiplexer  35   b  receives the output of the third AND gate  33   c  and the output of the logic  15  of FIG. 1, and is controlled by the main control signals NORMAL and MEMTEST 2 , to transmit the output of the third AND gate  33   c  and the output of the logic  15  of FIG. 1 to the second memory  19  of FIG.  1 . That is, when the main control signal NORMAL is active, the second multiplexer  35   b  transmits the signals generated from the logic  15  of FIG. 1 to the second memory  19  of FIG. 1, and when the main control signal MEMTEST 2  is active, the second multiplexer  35   b  transmits the signal generated from the third AND gate  33   c  to the second memory  19  of FIG.  1 . 
     FIG. 4 is a circuit diagram of the memory data controller  27  of FIG.  2 . Referring to FIG. 4, the memory data controller  27  includes an input/output buffer  41 , a logic gate  43 , a memory controller  45 , an output controller  47  and an output buffer controller  49 . 
     The input/output buffer  41  includes an input buffer  41   a  and an output buffer  41   b.    
     The input buffer  41   a  receives the memory data signal DQi, and transmits the output to the logic gate  43 . The input buffer  41   a  changes the voltage level of the memory data signal DQi. For example, a voltage of a TTL level is converted to a voltage of a CMOS level. 
     The output buffer  41   b  is controlled by the output buffer controller  49  to transmit the output of the output controller  47  externally. That is, when output of the output buffer controller  49  is active, the output buffer  41   b  is activated to transmit the output of the output controller  47  externally, and when the output of the output buffer controller  49  is inactive, the output buffer  41   b  is inactive to prevent transmission of the output of the output controller  47  externally. 
     The logic gate  43  receives the output of the input buffer  41   a  and signals MEMTEST 1 , NORMAL and MEMTEST 2 , and transmits the output to the memory controller  45 . The logic gate  43  includes first through third AND gates  43   a ,  43   b  and  43   c.    
     The first AND gate  43   a  receives the output of the input buffer  41   a  and the main control signal MEMTEST 1 , and transmits the output to the memory controller  45 . When the output of the input buffer  41   a  or the main control signal MEMTEST 1  is logic low, the first AND gate  43   a  generates a logic low signal, and when the output of the input buffer  41   a  and the main control signal MEMTEST 1  are logic high, the first AND gate  43   a  generates a logic high signal. 
     The second AND gate  43   b  receives the output of the input buffer  41   a  and the main control signal NORMAL, and transmits the output to the logic  15  of FIG.  1 . When the output of the input buffer  41   a  or the main control signal NORMAL is logic low, the second AND gate  43   b  generates signals of logic low, and when the output of the input buffer  41   a  and the main control signal NORMAL are logic high, the second AND gate  43   b  generates a logic high signal. 
     The third AND gate  43   c  receives the output of the input buffer  41   a  and the main control signal MEMTEST 2 , and transmits the output to the memory controller  45 . When the output of the input buffer  41   a  or the main control signal MEMTEST 2  is logic low, the third AND gate  43   c  generates a logic low signal, and when the output of the input buffer  41   a  and the main control signal MEMTEST 2  are logic high, the third AND gate  43   c  generates a logic high signal. 
     The memory controller  45  includes first and second multiplexers  45   a  and  45   b.    
     A 2-input, 1-output multiplexer is used as the first multiplexer  45   a . The first multiplexer  45   a  receives the output of the first AND gate  43   a  and the output of the logic  15  of FIG. 1, and is controlled by the main control signals NORMAL and MEMTEST 1 , to transmit the output of the first AND gate  43   a  and the output of the logic  15  of FIG. 1 to the first memory  17  of FIG.  1 . That is, when the main control signal NORMAL is active, the first multiplexer  45   a  transmits signals generated from the logic  15  of FIG. 1 to the first memory  17  of FIG. 1, and when the main control signal MEMTEST 1  is active, the first multiplexer  45   a  transmits signals generated from the first AND gate  43   a  to the first memory  17  of FIG.  1 . 
     A 2-input, 1-output multiplexer is used as the second multiplexer  45   b . The second multiplexer  45   b  receives the output of the third AND gate  43   c  and the output of the logic  15  of FIG. 1, and is controlled by the main control signals NORMAL and MEMTEST 2 , to transmit the output of the third AND gate  43   c  and the output of the logic  15  of FIG. 1 to the second memory  19  of FIG.  1 . That is, when the main control signal NORMAL is active, the second multiplexer  45   b  transmits signals generated from the logic  15  of FIG. 1 to the second memory  19  of FIG. 1, and when the main control signal MEMTEST 2  is active, the second multiplexer  45   b  transmits signals generated from the third AND gate  43   c  to the second memory  19  of FIG.  1 . 
     The output controller  47  receives signals generated from the logic  15  of FIG.  1  and the first and second memories  17  and  19  of FIG. 1, and transmits the output to the output buffer  41   b . A 3-input, 1-output multiplexer is used as the output controller  47 . The output controller  47  is controlled by the main control signals NORMAL, MEMTEST 1  and MEMTEST 2 . That is, when the main control signal NORMAL is active, the output controller  47  transmits signals generated from the logic  15  of FIG. 1 output controller  47  transmits signals from the first memory  17  of FIG. 1 to the output buffer  41   b , and when the main control signal MEMTEST 2  is active, the output controller  47  transmits signals generated from the second memory  19  of FIG. 1 to the output buffer  41   b.    
     The output buffer controller  49  includes first through third logic gates  49   a ,  49   b  and  49   d , a fourth AND gate  49   c  and a NAND gate  49   e.    
     The first logic gate  49   a  receives the main control signals MEMTEST 1  and MEMTEST 2 . When one of the main control signals MEMTEST 1  and MEMTEST 2  is logic high, the first logic gate  49   a  generates a logic high signal, and when all of the main control signals MEMTEST 1  and MEMTEST 2  are logic low, the first logic gate  49   a  generates a logic low signal. 
     The second logic gate  49   b  receives a first output buffer enable signal TRST 1  generated from the first memory  17  of FIG. 1 and a second output buffer enable signal TRST 2  generated from the second memory  19  of FIG.  1 . When the first output buffer enable signal TRST 1  or the second output buffer enable signal TRST 2  is logic high, the second logic gate  49   b  generates a logic high signal, and when both the first output buffer enable signal TRST 1  and the second output buffer enable signal TRST 2  are logic low, the second logic gate  49   b  generates a logic low signal. 
     The fourth AND gate  49   c  receives the output of the first logic gate  49   a  and the output of the second logic gate  49   b . When the output of the first logic gate  49   a  or the output of the second logic gate  49   b  is logic low, the fourth AND gate generates a logic low signal, and both the output of the first logic gate  49   a  and the output of the second logic gate  49   b  are logic high, the fourth AND gate generates a logic high signal. 
     The third logic gate  49   d  receives the output of the fourth AND gate  49   c  and the main control signal NORMAL. When the output of the fourth AND gate  49   c  or the main control signal is logic high, the third logic gate  49   d  generates a logic high signal, and both the output of the fourth AND gate  49   c  and the main control signal are logic low, the third logic gate  49   d  generates a logic low signal. 
     The NAND gate  49   e  receives the output of the third logic gate  49   d  and a power supply voltage VCC, and transmits the output to a control terminal of the output buffer  41   b . The NAND gate  49   e  transmits the output of the third logic gate  49   d  to the control terminal of the output buffer  41   b . That is, when the output of the third logic gate  49   d  is logic high, the NAND gate  49   e  generates a logic low signal, and when the output of the third logic gate  49   d  is logic low, the NAND gate  49   e  generates a logic high signal. When the output of the NAND gate  49   e  is logic low, i.e., active, the output buffer  41   b  is activated, and when the output of the NAND gate  49   e  is logic high, i.e., inactive, the output buffer  41   b  is deactivated. 
     FIG. 5 is a block diagram of a second embodiment of the memory test control circuit of FIG.  1 . Referring to FIG. 5, the memory test control circuit  13  according to the second embodiment includes a main control signal generator  51 , a memory control signal controller  53 , a first memory data controller  55  and a second memory data controller  57 . 
     The main control signal generator  51  receives a test control signal TESTMD 0  applied through the pad  9 , and transmits the output to the memory control signal controller  53 , the first memory data controller  55  and the second memory data controller  57 . The main control signal generator  51  generates main control signals, i.e., a main control signal MEMTEST and a main control signal NORMAL, in response to the test control signal TESTMD 0 . For example, the main control signal generator  51  has truth values as shown in Table 2. 
     
       
         
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Function 
                 TESTMD0 
                 Main control signal 
               
               
                   
                   
               
             
             
               
                   
                 First and second memory 
                 ‘L’ 
                 MEMTEST 
               
               
                   
                 test 
               
               
                   
                 Normal operation 
                 ‘H’ 
                 NORMAL 
               
               
                   
                   
               
             
          
         
       
     
     As shown in Table 2, when the test control signal TESTMD 0  is logic low, the main control signal MEMTEST is active, to test the first and second memories  17  and  19  of FIG. 1, and when the test control signal TESTMD 0  is logic high ‘H’, the main control signal NORMAL is activated, to normally operate the logic  15  of FIG.  1 . 
     The memory control signal controller  53  receives a memory control signal PC applied through the pad  8 , and is controlled by the main control signals MEMTEST and NORMAL, to transmit the memory control signal PC to the first and second memories  17  and  19  of FIG. 1 or the logic  15  of FIG.  1 . The memory control signal PC includes a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, an output enable signal OEB and an address signal Ai. 
     The first memory data controller  55  receives memory data signals DQ 1 i applied through the pad  7 , and is controlled by the main control signals MEMTEST and NORMAL to transmit the memory data signal DQ 1 i to the first memory  17  of FIG. 1 or the logic  15  of FIG. 1, and the memory data signal DQ 1 i generated from the first memory  17  of FIG. 1 or the logic  15  of FIG. 1 to outside the pad  7 . 
     The second memory data controller  57  receives a memory data signal DQ 2 i applied through the pad  7 ′, and is controlled by the main control signals MEMTEST and NORMAL, to transmit the memory data signal DQ 2 i to the second memory  19  of FIG. 1 or the logic  15  of FIG. 1, and the memory data signal DQ 2 i generated from the second memory  19  of FIG. 1 or the logic  15  of FIG. 1 to the pad  7 ′. 
     As described above, the memory test control circuit  13  according to the second embodiment of the present invention can test the first and second memories  17  and  19  of FIG. 1 using conventional pads  7 ,  8  and  7 ′ without the logic  15  of FIG.  1 . 
     FIG. 6 is a circuit diagram of the memory control signal controller  53  of FIG.  5 . Referring to FIG. 6, the memory control signal controller  53  includes a buffer  61 , a logic gate  63  and a memory controller  65 . 
     The buffer  61  receives a memory control signal PC, and transmits the output to the logic gate  63 . The buffer  61  changes the voltage level of the memory control signal PC. For example, a voltage of a TTL level is converted to a voltage of a CMOS level. 
     The logic gate  63  receives the output of the buffer  61 , and transmits the output to the memory controller  65 . The logic gate  63  includes first through third AND gates  63   a ,  63   b  and  63   c.    
     The first AND gate  63   a  receives the output of the buffer  61  and the main control signal MEMTEST. When the output of the buffer  61  or the main control signal MEMTEST is logic low, the first AND gate  63   a  generates a logic low signal, and when the output of the buffer  61  and the main control signal MEMTEST are logic high, the first AND gate  63   a  generates a logic high signal. 
     The second AND gate  63   b  receives the output of the buffer  61  and the main control signal NORMAL and transmits the output to the logic  15  of FIG.  1 . When the output of the buffer  61  or the main control signal NORMAL is logic low, the second AND gate  63   b  generates a logic low signal, and when the output of the buffer  61  and the main control signal NORMAL are logic high, the second AND gate  63   b  generates a logic high signal. 
     The third AND gate  63   c  receives the output of the buffer  61  and the main control signal MEMTEST. When the output of the buffer  61  or the main control signal MEMTEST are logic high, the third AND gate  63   c  generates a logic high signal. 
     The memory controller  65  includes first and second multiplexers  65   a  and  65   b.    
     A 2-input, 1-output multiplexer is used as the first multiplexer  65   a . The first multiplexer  65   a  receives the output of the first AND gate  63   a  and the output of the logic  15  of FIG. 1, and is controlled by the main control signals NORMAL and MEMTEST to transmit the output of the first AND gate  63   a  and the output of the logic  15  of FIG. 1 to the first memory  17  of FIG.  1 . That is, when the main control signal NORMAL is active, the first multiplexer  65   a  transmits the signal generated from the logic  15  of FIG. 1 to the first memory  17  of FIG. 1, and when the main control signal MEMTEST is active, the first multiplexer  65   a  transmits the signal generated from the first AND gate  63   a  to the first memory  17  of FIG.  1 . 
     A 2-input, 1-output multiplexer is used as the second multiplexer  65   b . The second multiplexer  65   b  receives the output of the third AND gate  63   c  and the output of the logic  15  of FIG. 1, and is controlled by the main control signals NORMAL and MEMTEST, to transmit the output of the third AND gate  63   c  and the output of the logic  15  of FIG. 1 to the second memory  19  of FIG.  1 . That is, when the main control signal NORMAL is active, the second multiplexer  65   b  transmits a signal generated from the logic to the second memory  19  of FIG. 1, and when the main control signal MEMTEST is active, the second multiplexer  65   b  transmits the signal generated from the third AND gate  63   c  to the second memory  19  of FIG.  1 . 
     FIG. 7 is a circuit diagram of the first memory data controller  55  of FIG.  5 . Referring to FIG. 7, the first memory data controller  55  includes a first input/output buffer  71 , a first logic gate  73 , a first memory controller  75 , a first output controller  77  and a first output buffer controller  79 . 
     The first input/output buffer  71  includes the first input buffer  71   a  and the first output buffer  71   b.    
     The first input buffer  71   a  receives the memory data signal DQ 1 i and transmits the output to the first logic gate  73 . The first input buffer  71   a  changes the voltage level of the memory data signal DQ 1 i. For example, a voltage of the TTL level is converted to a voltage of the CMOS level. 
     The first output buffer  71   b  is controlled by the first output buffer controller  79  to transmit the output of the first output controller  77  externally. That is, when the output of the first output buffer controller  77  is active, the first output buffer  71   b  is activated to transmit the output of the first output controller  77  externally, and when the output of the first output buffer controller  79  is inactive, the first output buffer  71   b  is inactive to transmit the output of the first output controller  77  externally. 
     The first logic gate  73  receives the output of the first input buffer  71   a  and transmits the output to the first memory controller  75 . The first logic gate  73  includes first and second AND gates  73   a  and  73   c.    
     The first AND gate  73   a  receives the output of the first input buffer  71   a  and the main control signal MEMTEST. When the output of the first input buffer  71   a  or the main control signal MEMTEST is logic low, the first AND gate  73   a  generates a logic low signal, and when the output of the first input buffer  71   a  and the main control signal MEMTEST are logic high, the first AND gate  73   a  generates a logic high signal. 
     The second AND gate  73   c  receives the output of the first input buffer  71   a  and the main control signal NORMAL and transmits the output to the logic  15  of FIG.  1 . When the output of the first input buffer  71   a  or the main control signal NORMAL is logic low, the second AND gate  73   c  generates a logic low signal, and when the output of the first input buffer  71   a  and the main control signal NORMAL are logic high, the second AND gate  73   c  generates a logic high signal. 
     The first memory controller  75  includes a 2-input, 1-output multiplexer. The first memory controller  75  receives the output of the first AND gate  73   a  and the output of the logic  15  of FIG. 1, and is controlled by the main control signals NORMAL and MEMTEST to transmit the output of the first AND gate  73   a  and the output of the logic  15  of FIG. 1 to the first memory  17  of FIG.  1 . That is, when the main control signal NORMAL is active, the first memory controller  75  transmits signals generated from the logic  15  of FIG. 1 to the first memory  17  of FIG. 1, and when the main control signal MEMTEST is active, the first memory controller  75  transmits signals generated from the first AND gate  73   a  to the first memory  17  of FIG.  1 . 
     The first output controller  77  includes a 2-input, 1-output multiplexer. The second output controller  77  receives signals generated from the logic  15  of FIG.  1  and the first memory  17  of FIG. 1, and transmits the output to the first output buffer  71   b . The first output controller  77  is controlled by the main control signals NORMAL and MEMTEST. That is, when the main control signal NORMAL is active, the first output controller  77  transmits signals generated from the logic  15  of FIG. 1 to the first output buffer  71   b , and when the main control signal MEMTEST is active, the first output controller  77  transmits signals generated from the first memory  17  of FIG. 1 to the first output buffer  71   b.    
     The first output buffer controller  79  includes a third AND gate  79   a , a first logic gate  79   c  and a first NAND gate  79   d.    
     The third AND gate  79   a  receives the main control signal MEMTEST and the first output buffer enable signal TRST 1 . When the main control signal MEMTEST or the first output buffer enable signal TRST 1  is logic low, the third AND gate  79   a  generates a logic low signal, and when both the main control signal MEMTEST and the first output buffer enable signal TRST 1  are logic high, the third AND gate  79   a  generates a logic high signal. 
     The first logic gate  79   c  receives output of the third AND gate  79   a  and the main control signal NORMAL. When output of the third AND gate  79   a  or the main control signal NORMAL is logic high, the first logic gate  79   c  generates a logic high signal, and when the output of the third AND gate  79   a  and the main control signal NORMAL are logic low, the first logic gate  79   a  generates a logic low signal. 
     The first NAND gate  79   d  receives the output of the first logic gate  79   a  and a power supply voltage VCC and transmits the output to a control terminal of the first output buffer  71   b . The first NAND gate  79   d  transmits the output of the first logic gate to the control terminal of the first output buffer  71   b . That is, when output of the first logic gate  79   c  is logic low, the first NAND gate  79   d  generates signals of logic high, and when the output of the first logic gate  79   c  is logic high, the first NAND gate  79   d  generates signals of logic low. When the output of the first NAND gate  79   d  is logic low, i.e., active, the first output buffer  71   d  is activated, and when the output of the NAND gate  79   d  is logic high, i.e., inactive, the first output buffer  71   b  is inactive. 
     FIG. 8 is a circuit diagram of the second memory data controller  57  of FIG.  5 . Referring to FIG. 8, the second memory data controller  57  includes a second input/output buffer  81 , a second logic gate  83 , a second memory controller  85 , a second output controller  87  and a second output buffer controller  89 . 
     The second input/output buffer  81  includes a second input buffer  81   a  and a second output buffer  81   b.    
     The second input buffer  81   a  receives the memory data signal DQ 2 i and transmits the output to the second logic gate  83 . The second input buffer  81   a  changes the voltage level of the memory data signal DQ 1 i. For example, a voltage of the TTL level is converted to a voltage of the CMOS level. 
     The second output buffer  81   b  is controlled by the second buffer controller  89  and transmits the output of the second output controller  87  externally. That is, when the output of the second output buffer controller  89  is active, the second output buffer  81   b  transmits the output of the second output controller  87  externally, and when the output of the second output buffer controller  89  is inactive, the second output buffer  81   b  is inactive, and thus the output of the second output controller  87  is not transmitted externally. 
     The second logic gate  83  receives the output of the second input buffer  81   a  and transmits the output to the second memory controller  85 . The second logic gate  83  includes fourth and fifth AND gates  83   a  and  83   c.    
     The fourth AND gate  83   a  receives the output of the second input buffer  81   a  and the main control signal MEMTEST. When the output of the second input buffer  81   a  or the main control signal MEMTEST is logic low, the fourth AND gate  83   a  generates a logic low signal, and when the output of the second input buffer  81   a  and the main control signal MEMTEST are logic high, the fourth AND gate  83   a  generates a logic high signal. 
     The fifth AND gate  83   c  receives the output of the second input buffer  81   a  and the main control signal NORMAL and transmits the output to the logic  15  of FIG.  1 . When the output of the second input buffer  81   a  or the main control signal NORMAL is logic low, the fifth AND gate  83   c  generates a logic low signal, and when the output of the second input buffer  81   a  and the main control signal NORMAL are logic high, the fifth AND gate  83   c  generates a logic high signal. 
     The second memory controller  85  includes a 2-input, 1-output multiplexer. The second memory controller  85  receives the output of the fourth AND gate  83   a  and the output of the logic  15  of FIG. 1, and is controlled by the main control signals NORMAL and MEMTEST to transmit the output of the fourth AND gate  83   a  or the output of the logic  15  of FIG. 1 to the second memory  19  of FIG.  1 . That is, when the main control signal NORMAL is active, the second memory controller  85  transmits signals generated from the logic  15  of FIG. 1 to the second memory  19  of FIG. 1, and when the main control signal MEMTEST is active, the second memory controller  85  transmits signals generated from the fourth AND gate  83   a  to the second memory  19  of FIG.  1 . 
     The second output controller  87  includes a 2-input, 1-output multiplexer. The second output controller  87  receives signals generated from the logic  15  of FIG.  1  and the second memory  19  of FIG. 1, and transmits the output to the second output buffer  81   b . The second output controller  87  is controlled by the main control signals NORMAL and MEMTEST. That is, when the main control signal NORMAL is active, the second output controller  87  transmits signals generated from the logic  15  of FIG. 1 to the second output buffer  81   b , and when the main control signal MEMTEST is active, the second output controller  87  transmits signals generated from the second memory  19  of FIG. 1 to the second output buffer  81   b.    
     The second output buffer controller  89  includes a sixth AND gate  89   a , a second logic gate  89   c  and a second NAND gate  89   d.    
     The sixth AND gate  89   a  receives the main control signal MEMTEST and the output buffer enable signal TRST 1  generated from the second memory  19  of FIG.  1 . When the main control signal MEMTEST or the output buffer enable signal TRST 2  is logic low, the sixth AND gate  89   a  generates a logic low signal, and when both the main control signal MEMTEST and the output buffer enable signal TRST 1  are logic high, the sixth AND gate  89   a  generates a logic high signal. 
     The second logic gate  89   c  receives the output of the sixth AND gate  89   a  and the main control signal NORMAL. When the output of the sixth AND gate  89   a  or the main control signal NORMAL is logic high, the second logic gate  89   c  generates a logic high signal, and when both the output of the sixth AND gate  89   a  and the main control signal NORMAL are logic low, the second logic gate  89   c  generates a logic low signal. 
     The second NAND gate  89   d  receives the output of the second logic gate  89   c  and a power supply voltage VCC and transmits the output to a control terminal of the second output buffer  81   b . The second NAND gate  89   d  transmits the output of the second logic gate to the control terminal of the second output buffer  81   b . That is, when the output of the second logic gate  89   c  is logic low, the second NAND gate  89   d  generates signals of logic high, and when the output of the second logic gate  89   c  is logic high, the second NAND gate  89   d  generates a logic low signal. When the output of the second NAND gate  89   d  is logic low, i.e., active, the second output buffer  81   b  is activated, and when the output of the NAND gate  89   d  is logic high, i.e., inactive, the second output buffer  81   b  is inactive. 
     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Technology Category: g