Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 11/122,444, filed on May 5, 2005, which application claims priority of U.S. Provisional Patent Application Ser. No. 60/622,195, filed on Oct. 26, 2004. The disclosures of the above applications are incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates to electrical circuits that provide an output port having a programmable slew rate. 
   BACKGROUND OF THE INVENTION 
   Referring now to  FIG. 1 , a computer system  10  is shown. A plurality of computing devices  12 - 1 ,  12 - 2 , . . . ,  12 -M, collectively referred to as computing devices  12 , are connected by a communication cable  14 . The communication cable  14  connects to differential signal bus interfaces  16 - 1 ,  16 - 2 , . . . ,  16 -M, such as small computer system interfaces (SCSI interfaces), associated with respective computing devices  12 . The interfaces  16 - 1 ,  16 - 2 , . . . ,  16 -M are collectively referred to as the interfaces  16 . The computing devices  12  may include a host controller, disk drive and/or any other device having a compatible SCSI interface. Terminators T- 1  and T- 2  include terminating bias resistors  18 - 1  and  18 - 2 , referred to collectively as bias resistors  18 , which are connected across conductors at opposite ends of the communication cable  14 . In some applications, a single terminator T is used at one end of the communication cable  14 . In practice, a plurality of cables  14  and terminating bias resistors  18  would connect the interfaces  16  to form a parallel data bus  20 . The data bus  20  may have several channels that each carry a bit of data per cycle. The data bus  20  may include additional channels for control signals. For purposes of clarity, only one channel of the parallel data bus  20  is described herein. 
   Turning now to  FIG. 2 , an output driver  22  of the prior art is shown. The output driver  22  provides an output port  24  that connects to the communication cable  14  and the bias resistor  18 . A p-channel field effect transistor (PFET) Q 1  has a gate connected to a PFET predriver  26 . A drain of the PFET Q 1  is connected to a voltage source VDD. A source of the PFET Q 1  is connected to a drain of an n-channel field effect transistor (NFET) Q 2 . A gate of the NFET Q 2  is connected to an NFET predriver  28 . A source of the NFET Q 2  is connected to a reference voltage VSS. The connection between the source of the PFET Q 1  and the drain of the NFET Q 2  provides one node of the output port  24 . A PFET Q 3  has a gate connected to a PFET predriver  30 . A drain of the PFET Q 3  is connected to the voltage source VDD. A source of the PFET Q 3  is connected to a drain of an NFET Q 4 . A gate of the NFET Q 4  is connected to an NFET predriver  32 . A source of the NFET Q 4  is connected to the reference voltage VSS. The connection between the source of the PFET Q 3  and the drain of the NFET Q 4  provides the second node of the output port  24 . Such an arrangement of the PFETs and NFETs Q 1 -Q 4  may be referred to as an “H-bridge.” 
   When the PFET Q 1  and the NFET Q 4  are turned on, and the PFET Q 3  and the NFET Q 2  are turned off, then current flows in a first direction through the output port  24 . When the PFET Q 1  and the NFET Q 4  are turned off, and the PFET Q 3  and the NFET Q 2  are turned on, then current flows in a second direction through the output port  24 . As the current flows through the output port  24  in the first and second directions, high and low voltages are developed across the bias resistor  18 . The high and low voltages typically range from +0.5V to −0.5V, and provide a data signal representing digital ones and zeros on the communication cable  14 . Drive voltages applied to the gates of the PFETS and NFETS Q 1 -Q 4  by the PFET and NFET predrivers  26 ,  28 ,  30 , and  32 , may be adjusted. The drive voltages determine a slew rate during transitions between the high and low voltages across the bias resistor  18 . Such a configuration is described in U.S. Pat. No. 6,597,233, the specification of which is incorporated herein by reference. While the output port  24  of the prior art provides an adjustable slew rate, the actual slew rate obtained may vary undesirably depending on variables such as a length of the communication cable  14  and manufacturing variables of the PFETs and NFETs Q 1 -Q 4 . 
   SUMMARY OF THE INVENTION 
   A small computer system interface (SCSI) driver circuit having a programmable slew rate comprises N cascaded delay cells each including a data bit input, a delayed data bit output that communicates with the data bit input of an adjacent one of the N cascaded delay cells, and a delay time input that receives a programmable delay time value for setting a variable delay between receiving data at the data bit input and generating the delayed data bit output. N predrivers receive an output enable signal and a corresponding one of the N delayed data bit outputs and generate a predriver output signal based on the output enable and the corresponding one of the N delayed data bit outputs. N drivers have inputs that receive predriver output signals from corresponding ones of the N predrivers. An output port communicates with outputs of the N drivers. 
   In other features, a delay control module generates the delay times for the N cascaded delay cells. A bit of data input to a first of the N data bit inputs cascades through the N cascaded delay cells. The N drivers sequentially respond to the outputs of the N predrivers to provide the predetermined slew rate at the output port. The delay control module includes a digital-to-analog converter (DAC) that receives a digital delay signal and that generates an analog delay signal and a bias generator that receives the analog delay signal and that biases the N cascaded delay cells. 
   In still other features, each of the N cascaded delay cells further comprise a charge storage device that is charged by the output voltage and that provides the delay time. The charge storage device includes a capacitor. The N drivers include H-bridges. Each of the N drivers further comprises a current source. Each of the N drivers further comprises a reference current source that provides a reference current for the current sources. A computing device comprises a plurality of the SCSI drivers. Each of the N predrivers includes an enable input, a predriver output, and a mapping circuit that maps a corresponding one of the N delayed data bit outputs and the enable input to a corresponding predriver output signal. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment(s) of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1  is a functional block diagram of computing devices connected by a communication cable; 
       FIG. 2  is a schematic diagram of a driver of the prior art; 
       FIG. 3  is a functional block diagram of an output port circuit for connection to a communication bus; 
       FIG. 4  is a schematic diagram of driver stages of an output port circuit; 
       FIG. 5  is a truth table of a predriver stage; 
       FIG. 6  is a schematic diagram of a bias-voltage generator of a delay stage; 
       FIG. 7  is a schematic diagram of a delay cell of a delay stage; 
       FIG. 8  illustrates signal diagrams of an output driver circuit; and 
       FIG. 9  illustrates a family of output signals of an output port. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module and/or device refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. For purposes of clarity, the same reference numerals will be used to identify similar elements. References to logical 1, true, and on are equivalent to each other, and references to logical 0, false, and off are equivalent to each other, unless otherwise noted. Parts or all of the invention may also be implemented with equivalent embodiments using logic that is inverted from that disclosed. 
   Referring now to  FIG. 3 , an output port circuit  40  is shown. The output port circuit  40  is connected to the bias resistor  18  by the communication cable  14 . An output port  42  provides an output signal having a predetermined slew rate. A delay setting module  43  programmably sets slew rate by applying a delay signal to a delay time input  44 . The delay setting module  43  may program all of the delay modules individually to two or more delay values and/or collectively to a common delay value. 1 to N conductors may be used to connect the delay setting module to the delay to the delay cells  46 . In some implementations, the delay time input  44  may be a 3-bit wide parallel binary input providing 2 3 =8 unique slew rates. Cascaded delay cells  46 - 1 ,  46 - 2 , . . . ,  46 -N, referred to collectively as the cascaded delay cells  46 , each receive the delay signal. Each of the cascaded delay cells  46  has an input  48 - 1 ,  48 - 2 , . . . ,  48 -N, referred to collectively as the data inputs  48 , that receive a data bit. Each of the cascaded delay cells  46  also has a delayed data output  50 - 1 ,  50 - 2 , . . . ,  50 -N, referred to collectively as the delayed data outputs  50 . Each of the data inputs  48 - 2  through  48 -N is connected to a delayed data output  50 - 1 ,  50 - 2 ,  50 -(N−1) of the preceding cascaded delay cell  46 . The data input  48 - 1  of the first cascaded delay cell  46 - 1  receives a data bit from an associated computing device  12 . Each cascaded delay cell  46  propagates its data bit from its input  48  to its delayed data output  50  after the delay time. Therefore, the data bit applied to the first input  48 - 1  propagates to the last delayed data output  50 -N after N multiples of the delay time. In a preferred embodiment, N=8 and each cascaded delay cell  46  provides a delay time between about 125 picoseconds and 375 picoseconds. The preferred embodiment thereby provides a slew rate adjustable between about 1 nanosecond and 3 nanoseconds, although other delay ranges can be used. 
   An output enable line  52  is active high and connected to a plurality of predrivers  54 - 1 ,  54 - 2 , . . . ,  54 -N, referred to collectively as the predrivers  54 . Each of the predrivers  54  has a data input connected to the delayed data output  50  of a respective one of the cascaded delay cells  46 . Each of the predrivers  54  implements a truth table, described later herein. The truth table uses the output enable line  52  and the delayed data output  50  to generate four output signals. The four output signals are communicated over output lines  56 - 1 ,  56 - 2 , . . . ,  56 -N, referred to collectively as output lines  56 , of each respective predriver  54 . 
   The output lines  56  of each predriver  54  are connected to a respective driver  58 - 1 ,  58 - 2 , . . . ,  58 -N, referred to collectively as the drivers  58 . Each of the drivers  58  has an input for a reference current signal  60  and a driver output port  62 . The driver output ports  62  are connected in parallel to form the output port  42 . When the output enable line  52  is high, a data bit propagates through the cascaded delay cells  46  and causes the driver output ports  62  to turn on or off in succession. As each output port  62  turns on or off, a magnitude of a signal appearing at the output port  42  increases or decreases, respectively, thereby providing a predetermined slew rate. 
   Turning now to  FIG. 4 , a partial schematic diagram is shown of the output port circuit  40 . The three lines of delay time input  44  are shown individually as  44 - 1 ,  44 - 2 , and  44 - 3 . The delay time input  44  is connected to a digital-to-analog converter (current DAC)  63 . A current output of the DAC  63  is applied to a bias voltage generator  64 . The DAC  63  receives the delay signal and converts it to a current as is described later. The bias voltage generator  64  converts the current to a positive bias voltage  66  and a negative bias voltage  68 . The positive and negative bias voltages  66 ,  68  are applied to each of the cascaded delay cells  46 . The cascaded delay cells  46  use the positive and negative bias voltages  66 ,  68  to operate internal circuitry as described later. 
   Circuitry of the drivers  58  will now be described. For the purpose of clarity, only the driver  58 -N will be described. The four output signals  56  from the predriver  54  are connected to an H-bridge. An output signal PP is connected to a gate of a PFET Q 5 . An output signal NP is connected to a gate of an NFET Q 6 . An output signal NN is connected to a gate of an NFET Q 7 . An output signal PN is connected to a gate of a PFET Q 8 . A source of the NFET Q 6  is connected to a source of the NFET Q 7 . A source of the PFET Q 5  is connected to a source of PFET Q 8 . A drain of the NFET Q 6  is connected to a drain of the PFET Q 5  and provides a negative node of the driver output port  62 . A drain of the NFET Q 7  is connected to a drain of the PFET Q 8  and provides a positive node of the driver output port  62 . An NFET Q 9  is configured as a current mirror and has a drain connected to the sources of the NFETs Q 6  and Q 7 . A PFET Q 10  is configured as a current mirror and has a drain connected to the sources of the PFETs Q 5  and Q 8 . 
   A current source is formed from NFETs Q 11 , Q 12 , and a PFET Q 13 . A gate and a drain of the NFET Q 11  are connected to the reference current source  60  and a gate of the NFET Q 12 . A source of the NFET Q 11  is connected to a source of the NFET Q 12 . A drain of the NFET Q 12  is connected to a drain and a gate of the PFET Q 13 . The sources of the NFETs Q 11  and Q 12  are connected to a source of each NFET Q 9  in the drivers  58 . A source of the PFET Q 13  is connected to a source of each PFET Q 10  in the drivers  58 . The NFET Q 12  and the PFET Q 13  mirror the reference current signal  60  flowing through the NFET Q 11  and provide current to the drivers  58 . The NFET Q 9  and PFET Q 10  assure that the driver circuit output has a predetermined source impedance substantially free from influences resulting from process variations in manufacturing the NFETs and PFETs. 
   Turning now to  FIG. 5 , a truth table  70  is shown. The truth table  70  has a first input column for the delayed data bit appearing at the delayed data output  50 . A second input column is has a state of the output enable (OE) line  52 . Four predriver output columns are provided, one for each of the predriver output signals PP, NN, PN, and NP. Entries in the four columns parenthetically indicate whether the associated PFET or NFET Q 5 -Q 8  is turned on or turned off. A rightmost output column indicates a logic state appearing at the driver output port  62 . The OE line  52  is a active high signal. When the OE line  52  is low, or zero, the PFETs and NFETs Q 5 -Q 8  are turned off and the driver output port  62  is electrically open (3-state). When the OE line  52  is high and the delayed data bit is low, or logical 0, the PFET Q 5  and the NFET Q 7  are turned off, and the PFET Q 8  and the NFET Q 6  are turned on. This combination results in a logical 0 appearing at the driver output port  62 . When the OE signal is high and the delayed data bit is high, or logical 1, the PFET Q 5  and the NFET Q 7  are turned on, and the PFET Q 8  and the NFET Q 6  are turned off. This combination results in a logical 1 appearing at the driver output port  62 . Conventional combinatorial logic may be used to implement the truth table  70  in each of the predrivers  54 . 
   Turning now to  FIG. 6 , a schematic diagram is shown of the current DAC  63  and the bias voltage generator  64 . The current DAC  63  has an operational transconductance amplifier (OTA) with an output connected to gates of PFETs Q 14 , Q 15 , Q 16 , Q 17 , and Q 18 . An inverting input  74  of the OTA  72  is connected to a constant voltage source VREF. A non-inverting input  76  of the OTA  72  is connected to a drain of the PFET Q 14  and to one end of a resistor  65 . The other end of the resistor  65  is connected to the reference voltage VSS. The output of the OTA  72  provides a current proportional to a voltage difference across the non-inverting  74  and inverting  76  inputs. A drain of the PFET Q 15  is connected to the supply voltage VDD and to the drains of the PFETs Q 15 , Q 16 , and Q 18 . The three lines of the delay time input  44  are connected to gates of PFETs Q 19 , Q 20 , and Q 21 , respectively. A source of the PFET Q 19  is connected to a drain of the PFET Q 15 . A source of the PFET Q 20  is connected to a drain of the PFET Q 16 . A source of the PFET Q 21  is connected to a drain of the PFET Q 17 . Drains of the PFETs Q 18 -Q 21  are connected together and provide a programmable current output  78 . 
   Operation of the current DAC  63  will now be described. The PFET Q 14  mirrors a current provided by the output of the OTA  72 . A magnitude of the current is established by adjusting a resistance of the resistor  65 . When the PFET Q 19  is turned on by the first delay time input line  44 - 1 , the PFET Q 15  mirrors the current flowing through the PFET Q 14 . When the PFET Q 20  is turned on by the second delay time input line  44 - 2 , the PFET Q 16  mirrors the current flowing through the PFET Q 14 . When the PFET Q 21  is turned on by the third delay time input line  44 - 3 , the PFET Q 17  mirrors the current flowing through the PFET Q 14 . As the number of PFETs Q 19 -Q 21  being turned on by the delay time input lines  44  increases, an increasing current flow is established through the programmable current output  78 . The sizes of PFETs Q 15 -Q 18  can be unequal to provide up to eight discrete levels of current flow through the programmable current output  78  in accordance with delay time input lines  44  turning on/off the PFETs Q 19 , Q 20 , and Q 21 . 
   In the bias voltage generator  64 , the current flow from the programmable current output  78  is applied to a drain and a gate of an NFET Q 22 . A source of the NFET Q 22  is connected to the reference voltage VSS, a source of an NFET Q 23 , and a source of an NFET Q 24 . A drain of the NFET Q 23  is connected to a drain and a gate of a PFET Q 25 . A source of the PFET Q 25  is connected to the voltage source VDD. A drain and a gate of the NFET Q 24  are connected to a drain of a PFET Q 26 . A gate of the PFET Q 26  is connected to the gate and the drain of the PFET Q 25 . A source of the PFET Q 26  is connected to the supply voltage VDD. The drain of the PFET Q 25  provides the positive bias voltage  66 , and the drain of the NFET Q 24  provides the negative bias voltage  68 . 
   Operation of the bias voltage generator  64  will now be described. The current flow from the programmable current output  78  is mirrored by the NFET Q 22 . The NFET Q 23  mirrors the current flowing through the NFET Q 22 . The PFET Q 25  drops a voltage across its source and drain as it mirrors the current flowing through the NFET Q 23 . The drain of the PFET Q 25  thereby provides the positive voltage  66  with VDD less the voltage dropped across PFET Q 25 . The PFET Q 26  mirrors the current flowing through the PFET Q 25 . The NFET Q 24  drops a voltage across its source and drain as it mirrors the current flowing through the PFET Q 26 . The drain of the NFET Q 24  thereby provides the negative voltage  68  with a voltage equal to its source-drain voltage drop. The positive  66  and negative  68  bias voltages are applied to the delay cells  46 . 
   Turning now to  FIG. 7 , a schematic diagram of a delay cell  46  is shown. A source of a PFET Q 27  is connected to the supply voltage VDD. A gate of the PFET Q 27  is connected to the positive bias voltage  66 . A drain of the PFET Q 27  is connected to a source of a PFET Q 28 . A gate of the PFET Q 28  is connected to the data bit input  48  of the delay cell  46 . A drain of the PFET Q 28  is connected to a drain of an NFET Q 29 , to one end of a capacitor C 1 , and to an input of an inverter  80 . The other end of the capacitor C 1  is connected to the reference voltage VSS. A source of the NFET Q 29  is connected to a drain of an NFET Q 30 . A gate of the NFET Q 29  is connected to the data bit input  48  of the delay cell  46 . A source of the NFET Q 30  is connected to the reference voltage VSS. A gate of the NFET Q 30  is connected to the negative bias voltage  68 . An output of the inverter  80  provides the delayed data output  50 . 
   Operation of the delay cell  46  will now be described. A magnitude of the positive  66  and negative  68  bias voltages establishes drain-source resistances of the PFET Q 27  and the NFET Q 30 . If a logical 1 is applied to the data bit input  48 , the PFET Q 28  turns off and the NFET Q 29  turns on, thereby allowing the capacitor C 1  to discharge through the NFETs Q 29  and Q 30 . A rate of discharge is determined by the magnitude of the negative bias voltage  68 . With the capacitor C 1  discharged, a logical 0 appears at the input of the inverter  80  and a logical 1 appears at the output of the inverter  80 . The rate of discharge determines the delay time for the delay cell  46 . Alternatively, if a logical 0 is applied to the data bit input  48 , the NFET Q 29  turns off and the PFET Q 28  turns on, thereby allowing the capacitor C 1  to charge through the PFETs Q 27  and Q 28 . A rate of charge is determined by the magnitude of the positive bias voltage  66 . When capacitor C 1  is charged, a logical 1 appears at the input of the inverter  80  and a logical 0 appears at the output of the inverter  80 . The rate of charge is preferably equal to the rate of discharge. 
   Turning now to  FIG. 8 , waveforms are shown for an example output port circuit  40  having N=8 cascaded delay cells  46 , predrivers  54 , and drivers  58 . A horizontal axis of each plot indicates time in nanoseconds and a vertical axis of each plot represents volts. The column of plots at a left side of  FIG. 8  shows waveforms for a rising edge at the output port  42  caused by a logical 1 being applied to the data input  48 - 1  while the OE input  52  is high. 
   A plot  82  shows a set of time correlated curves  84  representing the output signals NN from the predrivers  54 . Each output signal NN begins rising after its associated cascaded delay cell  46  propagates the logical 1 data bit. 
   A plot  86  shows a set of time correlated curves  88  representing the output signals PP from the predrivers  54 . Each output signal PP begins falling after its associated cascaded delay cell  46  propagates the logical 1 data bit. 
   A plot  90  shows a set of time correlated curves  92  representing the output signals NP from the predrivers  54 . Each output signal NP begins falling after its associated cascaded delay cell  46  propagates the logical 1 data bit. 
   A plot  94  shows a set of time correlated curves  96  representing the output signals PN from the predrivers  54 . Each output signal PN begins rising after its associated cascaded delay cell  46  propagates the logical 1 data bit. 
   A plot  98  shows a signal voltage  100  rising at a controlled slew rate in unison with each driver output port  62  applying the logical 1 date bit to the output port  42 . The signal voltage  100  rises as the drivers  58  activate in succession according to the output signals NN, PP, NP, and PN. 
   The column of plots at a right side of  FIG. 8  shows waveforms for a falling edge at the output port  42  caused by a logical 0 being applied to the data input  48 - 1  while the OE input  52  is high. 
   A plot  102  shows a set of time correlated curves  104  representing the output signals NN from the predrivers  54 . Each output signal NN begins falling after its associated cascaded delay cell  46  propagates the logical 0 data bit. 
   A plot  106  shows a set of time correlated curves  108  representing the output signals PP from the predrivers  54 . Each output signal PP begins rising after its associated cascaded delay cell  46  propagates the logical 0 data bit. 
   A plot  110  shows a set of time correlated curves  112  representing the output signals NP from the predrivers  54 . Each output signal NP begins rising after its associated cascaded delay cell  46  propagates the logical 0 data bit. 
   A plot  114  shows a set of time correlated curves  116  representing the output signals PN from the predrivers  54 . Each output signal PN begins falling after its associated cascaded delay cell  46  propagates the logical 0 data bit. 
   A plot  118  shows a signal voltage  120  falling at a controlled slew rate in unison with each driver output port  62  applying the logical 0 data bit to the output port  42 . The signal voltage  120  falls as the drivers  58  activate in succession according to the output signals NN, PP, NP, and PN. 
   A time between each successive rising edge and/or each successive falling edge in the families of curves is equal to the delay time of the cascaded delay cells  46 . 
   Turning now to  FIG. 9 , families of waveforms are shown for the example output port circuit  40  having N=8 cascaded delay cells  46 , predrivers  54 , and drivers  58 . Each of the cascaded delay cells  46  provide the delay time in accordance with the delay time signal  44 . A horizontal axis of each plot indicates time in nanoseconds and a vertical axis of each plot represents volts. A plot  122  shows a family of eight rising edge waveforms  124 . Each rising edge waveform is generated at the output port  42  with the cascaded delay cells  46  using a different one of eight discrete delay times. It can be seen from the family of rising edge waveforms  124  that increasing the delay time decreases the slew rate of the output port  42 . 
   A plot  126  shows a family of eight falling edge waveforms  128 . Each falling edge waveform is generated at the output port  42  with the cascaded delay cells using a different one of the eight discrete delay times. It can be seen from the family of rising edge waveforms  124  that decreasing the delay time increases the slew rate of the output port. 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.

Technology Category: h