Patent Document

BACKGROUND 
     1. Technical Field 
     Embodiments of the present disclosure relate generally to voltage regulators, and more specifically to a linear voltage regulator design for generating sub-reference output voltages. 
     2. Related Art 
     Linear voltage regulators generally refer to voltage regulators that receive an unregulated power source as input and provide a regulated output voltage, the regulation being achieved by controlling, using feedback techniques, the ON-resistance of a pass-device (such as a pass transistor) operated in its linear or saturation region of operation, depending on the type of the pass-device (e.g., whether a bipolar junction transistor or MOS transistor). A desired value of the regulated output voltage is typically set by comparing a fraction of the output voltage with a reference voltage, and adjusting the ON-resistance of the pass-device based on the difference of the output voltage and the reference voltage. 
     It is often desirable to use a linear voltage regulator to provide a sub-reference output voltage, i.e., an output voltage less than the reference voltage used in the regulator. Some prior techniques for generating such sub-reference output voltages are associated with drawbacks such as larger area for implementation, greater noise associated with the regulated output voltage, etc. 
     SUMMARY 
     This Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 
     A linear voltage regulator comprises a voltage reference, a pass transistor, a voltage divider network, a first amplifier and a second amplifier. The voltage reference is designed to generate a reference voltage. The pass transistor is coupled between an external power source and an output terminal of the voltage regulator, an output of the voltage regulator being provided at the output terminal. The voltage divider network coupled between the output terminal and a constant reference potential. The first amplifier compares the reference voltage and a voltage at a first node in the voltage divider network and controls an impedance of the pass transistor. The second amplifier compares an output voltage of the output and a voltage at a second node in the voltage divider network, and injects a current into the first node, the current being proportional to a difference of the output voltage and the voltage at the second node. 
     Several embodiments of the present disclosure are described below with reference to examples for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the embodiments. One skilled in the relevant art, however, will readily recognize that the techniques can be practiced without one or more of the specific details, or with other methods, etc. 
    
    
     
       BRIEF DESCRIPTION OF THE VIEWS OF DRAWINGS 
       Example embodiments will be described with reference to the accompanying drawings briefly described below. 
         FIG. 1  is a diagram of a conventional (prior) linear voltage regulator. 
         FIG. 2  is a diagram illustrating relevant details of a linear voltage regulator designed to generate sub-reference output voltages, in an embodiment. 
         FIG. 3  is a block diagram of an example receiver system. 
     
    
    
     The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. 
     DETAILED DESCRIPTION 
     Various embodiments are described below with several examples for illustration. 
     1. Linear Voltage Regulator 
       FIG. 1  is a diagram of a conventional linear voltage regulator. Low-dropout regulator (LDO)  100  is shown containing voltage reference  110 , operation amplifier (OPAMP)  120 , pass-transistor  130 , and resistors  140  and  150 . Capacitor  160  represents the output capacitance at output node  149 . 
     Voltage reference  110 , which may be implemented as a band-gap reference, generates a reference voltage on path  112 , which is connected to the inverting input (−) of OPAMP  120 . Resistors  140  and  150  implement a voltage divider network, and the voltage at node  145  is fed back to the non-inverting input (+) of OPAMP  120 . Output  123  of OPAMP  120  controls the ON-resistance of pass transistor  130  to maintain output voltage  149  at a desired constant voltage (regulated voltage). The connection of node  145  back to OPAMP  120  implements a closed-loop feedback for regulating output voltage  149 . Terminal  101  receives an unregulated voltage from a power source such as, for example, a battery (not shown). 
     One drawback with the conventional implementation shown in  FIG. 1  is that the regulated output voltage  149  (in the steady state) cannot be lower than the value of reference voltage  112 . Output voltage  149  is specified by the following equation:
 
 Vo=VBG *(1 +R 140 /R 150)  Equation 1
 
     wherein, 
     VBG is value of reference voltage  112 , and 
     R 140  and R 150  are respectively the resistances of resistors  140  and  150 . 
     It may be observed from Equation 1, that the minimum value of Vo obtainable is VBG. One prior technique for obtaining an output voltage less than VBG is to scale down VBG using a resistive divider, and connecting the scaled-down voltage to the inverting (−) terminal of OPAMP  120 . However, such an approach may be associated at least with power dissipation in the resistive divider (used to obtain the scaled-down VBG), higher noise in the output voltage due to the resistive divider, and increased implementation area (to accommodate the resistive divider). Further, such an approach may also be associated with start-up issues such as longer time post start-up (e.g., power-ON) for output voltage Vo to settle within an acceptable margin of its steady-state value. 
     2. Generating Sub-Reference Output Voltages 
       FIG. 2  is a diagram illustrating relevant details of a linear voltage regulator designed to generate sub-reference output voltages, in an embodiment. The term ‘sub-reference output voltage’ means that the steady-state value of the output voltage of the linear voltage regulator is less than the value of the output voltage of the voltage reference used in the linear voltage regulator. The specific details of  FIG. 2  are shown merely to illustrate the architecture of a linear voltage regulator capable of generating sub-reference output voltages. However, specific implementations of such a linear voltage regulator may additionally include other components or circuitry as well. 
     Low-dropout regulator (LDO)  200  is shown containing voltage reference  210 , OPAMPs  220  (first amplifier) and  270  (second amplifier), pass-transistor  230 , and resistors  240  (R 1 ),  250  (R 2 ) and  260  (R 3 ). Output capacitor  280  is also shown connected to the output terminal  290  of LDO  200 , and is provided to improve the regulation provided by LDO  200 . Terminal  291  represents the output terminal of voltage regulator  200 , and generates an output voltage Vout. Although not shown, one or more units (e.g., voltage reference  210 , OPAMP s  220  and  270 ) may be powered directly by node  201 . The series combination of resistors R 1 , R 2  and R 3  operates as a voltage divider network. 
     Voltage reference  110 , OPAMP  220 , pass-transistor  230 , and resistors R 2  and R 3  correspond respectively to voltage reference  110 , OPAMP  120 , pass-transistor  130 , and resistors  140  and  150  of  FIG. 1 , and their description and operation are not repeated here in the interest of conciseness. Voltage reference  210 , which may be implemented as a band-gap reference, generates a voltage Vbg on path  212 . Node  201  receives an unregulated power supply from a source such as, for example, a battery. 
     OPAMP  220  operates in closed-loop negative feedback configuration to maintain the voltage at node  245  equal to Vbg generated by voltage reference  210 . 
     OPAMP  270  is implemented as a transconductance amplifier, and generates an output current that is proportional to the difference in the voltages at the non-inverting (+) and inverting (−) input terminals of OPAMP  270 . The non-inverting (+) input of OPAMP  270  is connected to output terminal  291 . The inverting (−) input of OPAMP  270  is connected to node  256 . The voltage (VSUB-BG-TAP) at node  256  (second node) is always less than the voltage (VFB) at node  245  (first node), and thus also less than Vbg. With corresponding changes in the connections components of  FIG. 2  (e.g., with transistor  230  being an N-type MOS (NMOS) transistor rather than a P-type MOS (PMOS) transistor as shown in  FIG. 2 , and with changes in the connections of OPAMP  220 ), LDO  200  may be designed to receive a negative voltage on node  201  and provide negative output voltages (with respect to ground). In such configurations, VSUB-BG-TAP is always greater than VFB. Thus, in general, the absolute value of VSUB-BG-TAP is always less than the absolute value of VFB. OPAMP  270  is connected in negative feedback configuration, as may be observed from  FIG. 2 . 
     OPAMP  270  operates to maintain output voltage Vout at the same magnitude as the magnitude of the voltage VSUB-BG-TAP at node  256  by controlling the currents I 1  and  12  respectively flowing through the resistor R 1 , and the series combination of resistors R 2  and R 3 . Since VSUB-BG-TAP is at a lower voltage than FB, regulated output voltage Vout is also lower than Vbg, and equals the voltage VSUB-BG-TAP. OPAMP  270  ‘pushes’ current into the feedback node ( 245 ) of OPAMP  220 , thereby causing current to flow in the reverse direction (i.e., from node  245  to node  291 ) in resistor R 1 . As a result, output voltage Vout is reduced below the reference voltage Vbg. By suitable selection of the ratio of R 2  and R 3 , desired sub-reference values of Vout can be obtained. 
     The operation of LDO  200  to generate a sub-reference output voltage Vout may be viewed as occurring as follows: 
     Assume that each of OPAMPs  220  and  270  are operating normally, Vout is being regulated at the target output voltage of VBG*R 3 /(R 2 +R 3 ). Assuming that that an upward perturbation at the output occurs, raising the Vout a little, the output current of OPAMP  270  would increase. A portion of the ‘extra current’ (due to the increase in the output current of OPAMP  270 ) flows through R 1  (from node  245  to terminal  291 ), and the rest of the extra current flows through the series connection of R 2  and R 3 , thereby increasing VFB. The output of OPAMP  220  therefore increases, thereby decreasing Vout, and thus nullifying the perturbation at Vout. 
     At steady-state, the following equalities are satisfied:
 
 VFB=Vbg,  
 
 V out= VSUB - BG -TAP,
 
 VSUB - BG -TAP= VFB*R 3/( R 2 +R 3),
 
Thus,  V out= Vbg*R 3/( R 2 +R 3),
 
     wherein, 
     R 3  and R 2  respectively represent the resistances of resistors  260  and  250 . 
     The expressions for currents I 1  and I 2  are provided below:
 
 I 1=( VFB−V out)/ R 1 =Vbg *( R 2/( R 1*( R 2 +R 3)))
 
 I 2 =VFB /( R 2 +R 3)= VBG /( R 2 +R 3)
 
     Total output current generated by OPAMP  270  equals (I 1 +I 2 ), and therefore equals VBG*(1+R 2 /R 1 )/(R 2 +R 3 ). 
     Several advantages of the technique of  FIG. 2  may now be apparent. LDO  200  does not require a voltage divider to scale down the reference voltage Vbg, as in the prior technique noted above. Hence, there is no area penalty that might otherwise be associated with the implementation of such a voltage divider. There are also no start-up issues as in the prior technique. Further, the output of OPAMP  220  is associated with lesser noise than it would have if a voltage divider as in the prior technique were used. 
     LDO  200 , implemented as described above, can be incorporated in a device or system, as described next. 
     3. Example System 
       FIG. 3  is a block diagram of an example receiver system  300 . Receiver system  300  may correspond to a mobile phone, and is shown containing antenna  301 , analog processor  320 , ADC  350 , processing unit  390 , low-dropout voltage regulator (LDO)  200 , battery  310  and output capacitor  280 . 
     Antenna  301  may receive various signals transmitted on a wireless medium. The received signals may be provided to analog processor  320  on path  302  for further processing. Analog processor  320  may perform tasks such as amplification (or attenuation as desired), filtering, frequency conversion, etc., on the received signals and provides the resulting processed signal on path  325 . 
     ADC  350  converts the analog signal received on path  325  to corresponding digital values, which are provided on path  359  for further processing. Processing unit  390  receives the data values on path  359 , and processes the data values to provide various user applications. LDO  200  provides a regulated voltage (with battery  310  being the power source) for the operation of each of analog processor  320 , ADC  350 , and processing unit  390 . LDO  200  may be implemented as described in detail above. 
     While in the illustrations of  FIGS. 1 ,  2 , and  3 , although terminals/nodes are shown with direct connections to (i.e., “connected to”) various other terminals, it should be appreciated that additional components (as suited for the specific environment) may also be present in the path, and accordingly the connections may be viewed as being “electrically coupled” to the same connected terminals. In the instant application, power supply and ground terminals are referred to as constant reference potentials. 
     Further, while in  FIG. 2 , LDO  200  is shown as providing a positive value of output voltage, corresponding changes can be made to the connections and components of  FIG. 2  to enable generation of negative voltages as well, as would be apparent to one skilled in the relevant arts. It should also be appreciated that the specific type of transistors (such as NMOS, PMOS, etc.) noted above with respect to  FIG. 2  are merely by way of illustration. However, alternative embodiments using different configurations and other types of transistors, such as bipolar junction transistors (BJT) or a combination of MOS and BJT, will be apparent to one skilled in the relevant arts by reading the disclosure provided herein. For example, NMOS transistors and PMOS transistors may be swapped, while also interchanging the connections to power and ground terminals. Accordingly, in the instant application, the source (emitter) and drain (collector) terminals (through which a current path is provided when turned ON and an open path is provided when turned OFF) of transistors are termed as current terminals, and the gate (base) terminal is termed as a control terminal. 
     While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Technology Category: g