Patent Document

BACKGROUND 
       [0001]    Aspects of the present invention are directed to an in-line characterization with temperature profiling. 
         [0002]    Reliable in-line characterization is becoming increasingly critical in the development of new technologies and in product manufacturing. At least one reason for this is that certain reliability degradation mechanisms are relatively sensitive to the choice of manufacturing processes to be employed and the materials used in the processes. Degradation mechanisms leading to bias temperature instability (BTI) are examples of these and are key reliability concerns in at least advanced integrated circuit (IC) technologies. 
         [0003]    Accurate in-line BTI testing is not generally possible, however, due to the tendencies for devices under test conditions to recover from applied stress relatively quickly (i.e., fast recovery) after a point, such as the beginning of a test, where the stress is no longer applied. The tendency for devices to recover quickly is a particular concern at elevated stress temperatures. In these cases, negative-bias-temperature-instability (NBTI) in p-channel metal oxide semiconductor field-effect transistors (PMOSFETs) typically consists of two degradation mechanisms, which include, for example, interface-state generation between a channel (Si) and gate dielectrics (such as SiO 2 ). Interface-state generation is a thermally activated process that degrades the device and circuit performance. 
         [0004]    It has been observed that the NBTI-shift due to interface-state generation recovers quickly during device tests after the stress bias is removed. Special high-speed instruments are needed in order to capture the real degradation before recovery occurs. The use of such instruments is generally impractical in production environments. 
       SUMMARY 
       [0005]    In accordance with an aspect of the invention, an apparatus is provided and includes a thermally isolated device under test to which first and second voltages are sequentially applied, a local heating element to impart first and second temperatures to the device under test substantially simultaneously while the first and second voltages are sequentially applied, respectively and a temperature-sensing unit to measure the temperature of the device under test. 
         [0006]    In accordance with an aspect of the invention, an apparatus is provided and includes a thermally isolated device under test to which first and second voltages are sequentially applied, a local heating element to impart first and second temperatures to the device under test independently of the first and second voltages being sequentially applied and a sensor to measure a characteristic of the device under test. 
         [0007]    In accordance with an aspect of the invention, a method of conducting an in-line test of a device under test is provided and includes thermally isolating the device under test, with the device under test thermally isolated, applying first and second voltages to the device under test and, during the applying of the voltages, imparting first and second temperatures to the device under test independently of the applying of the voltages. 
     
    
     
       BRIEF DESCRIPTIONS OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0008]    The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other aspects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0009]      FIG. 1  is a diagram of a test methodology in accordance with an embodiment of the invention; 
           [0010]      FIG. 2  is a diagram of a test methodology in accordance with another embodiment of the invention; 
           [0011]      FIG. 3  is a diagram of a test methodology in accordance with another embodiment of the invention; 
           [0012]      FIG. 4  is a diagram of a test methodology in accordance with another embodiment of the invention; 
           [0013]      FIG. 5  is a diagram of a test methodology in accordance with another embodiment of the invention; 
           [0014]      FIGS. 6A and 6B  are schematic illustrations of a structure of a device under test; 
           [0015]      FIG. 7  is a flow diagram illustrating a method of conducting an in-line test of the structure of  FIGS. 6A and 6B ; 
           [0016]      FIG. 8  is a schematic illustration of a structure of a device under test; and 
           [0017]      FIG. 9  is a flow diagram illustrating a method of conducting an in-line test of the structure of  FIG. 8 . 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    Fast temperature switching between a stress condition and a test condition of a device under test (DUT) accelerates a degradation mechanism of the DUT to be in-line monitored during the stress condition and then “freezes” or halts the degradation during the test condition to avoid recovery. A test of bias temperature instability (BTI) stress of the DUT can thereby be conducted at elevated temperatures to accelerate shift, while a subsequent test can be carried out at lower temperatures to capture real BTI induced shift before significant recovery occurs. The methodology and structures for achieving this enables convenient and fast temperature changes during in-line testing so that general characterization of temperature-dependent device properties can be implemented. 
         [0019]    Normally, as an example, testing of an in-line BTI mechanism of the DUT involves increasing a chuck temperature of a chuck on which the DUT is situated to a stress condition and holding the chuck temperature in that stress condition. The chuck temperature is typically about 85° C. or above in order to accelerate degradation of the DUT. After the chuck temperature is stabilized, which usually requires about 30 minutes, the DUT is biased at a stress point for a period of time, which is typically about 10 seconds or more. The biasing may refer to application of a stress voltage to the DUT. After the stress period, voltage is lowered to and stabilized at a test point before the first test data is taken. This may occur within about 1 second. 
         [0020]    The set of tests to be conducted may include several drain-current versus gate-voltage curves at various bias conditions at each node, and the complete test sequence usually takes more than a few seconds in order to fully characterize the BTI-induced shifts in device parametrics. In any case, the chuck temperature stays at the elevated stress temperature even during the test sequence. Therefore, the results only represent those of a recovered device and do not reflect the real degradation of the DUT. In an example, there may be about 50% recovery after a mere one second delay in a test. 
         [0021]    With reference to  FIG. 1 , a new test methodology is provided. Here, the chuck temperature is maintained at or about room temperature or even lower, while the elevated stress temperature is achieved by an embedded on-chip local heating element that is located proximate to or adjacent to the DUT. The local heater can be formed of resistive elements, such as doped polysilicon strips, diffusion resistors, or back-end-of-line (BEOL) TaN resistors, which can provide over 100° C. of localized heating. A degree of the localized heating may be a function of the power applied to the local heating element, which can be tailored by tuning the supply power to achieve a wide range of temperatures for various stress and test conditions. The time needed to reach the designated temperature with the local heater is on the order of milli-seconds (msec). As such, since the local heating can be eliminated substantially immediately once the local heater is powered off, an in-line test condition following a stress condition can be conducted with relatively high resolution in both time and temperature. This also allows for accurate results to be achieved before relaxation occurs. 
         [0022]    In particular, as shown in  FIG. 1 , the local heater heats the DUT to the local stress temperature, T local     —     stress , while a voltage V stress  is applied to the DUT during the stress condition time. At the initiation of the test condition, the local heater is powered off and the local temperature immediately returns to the chuck temperature, T local     —     test , while the applied voltage is reduced to V test . At this point, degradation measurement of the DUT begins with, e.g., a measurement of the change in drain current through the DUT, ΔId. 
         [0023]    Since local temperature control may be independent of a voltage/current bias, a wide variety of temperature/bias stress and test conditions can be carried out. For example,  FIG. 2  shows another stress/test sequence with a relatively low-temperature T 0  test on a fresh device added before the stress procedure. In sequence of  FIG. 2 , a methodology similar to that of  FIG. 1  is preceded by an initial condition during T 0  when the local temperature is T chuck  and the applied voltage is V test . 
         [0024]    As shown in  FIG. 3 , another sequence may be characterized as a relatively high-temperature AC stress condition followed by low-temperature test condition. In another case, shown in  FIG. 4 , the sequence is characterized as thermal cycle stress conditions with intermediate characterization of a resistance change, ΔR, at a relatively low temperature. In yet another case, the sequence is characterized as a general in-line device characterization of temperature-dependent device properties, as shown in  FIG. 5 , where the measurement of the driving current as a function of temperature, Ion(T), of the DUT is taken. 
         [0025]    With reference to  FIGS. 6A and 6B , a structure  60  or apparatus to implement the in-line test methodology is shown. In the structure  60 , a DUT  61  (i.e., device A) is surrounded by a local heater  62 , such as diffusion resistors or some other suitable devices, and is enclosed by a thermal insulator  63  to increase the heating efficiency. The thermal insulator  63  may be, for example, a shallow-trench isolation STI, airgaps defined around the DUT  61  and/or buried oxides (BOX) positioned underneath the DUT  61  in silicon-on-insulator SOI technologies. A temperature-sensing unit  64 , such as a resistor, a metal wire, a diode or some other suitable device, can be added proximate to or adjacent the DUT  61  within the local heater  62  to monitor a temperature inside a region of interest. Other characteristics of DUT  61 , such as changes in drain current, changes in resistance or changes in driving current, may be determined by external test equipments through probing pads connected to DUT  61 . As shown in  FIG. 6B , a probing unit  67  is disposed proximate to the DUT  61  to connect to external test equipments for conducting the testing of the DUT  61 . 
         [0026]    As shown in  FIG. 7 , a method of conducting an in-line test using the structure of  FIGS. 6A and 6B  may include setting a chuck temperature T at operation  700 . Subsequently, a variable N is set to 1 (operation  710 ), a local temperature is adjusted by way of the local heater  62  (operation  720 ) and the local temperature is checked by way of the temperature sensing unit  64  (operation  730 ). If the local temperature is determined to not be within predefined parameters (operation  740 ), control returns to operation  720  by way of first loop  741 . If, on the other hand, the local temperature is determined to be within the predefined parameters at operation  740 , bias is applied to the DUT  61  for the Nth stress test (operation  750 ). Device parameters, such as drain current, resistance and driving current, are then measured at time T(N) (operation  760 ). The variable N is then set to N+1 (operation  770 ) and control returns to operation  710  along loop  771 . 
         [0027]    With reference to  FIG. 8 , to further increase a sensitivity of the in-line test in characterizing temperature-dependent device properties, a reference DUT  65  (i.e., device B) can be added in the outside of the heating area which stays at chuck temperature throughout the measurement. The test nodes from the DUT  61 , such as a drain of a MOSFET, an anode of a resistor, etc., and that from the reference DUT  65  are fed into a differential amplifier  66  to determine the differentials between the DUT  61  and the reference DUT  65 . Therefore, the temperature-dependent device properties can be characterized relative to the reference DUT  65  with relatively improved accuracy. As shown in  FIG. 6A , the reference DUT  65  can be included within the thermal insulator  63  and used for comparison measurements relative to those of the DUT  61  without the aid of the differential amplifier  66 . 
         [0028]    As shown in  FIG. 9 , a method of conducting an in-line test using the structure of  FIG. 8  may include setting a chuck temperature T at operation  900 . Subsequently, a variable N is set to 1 (operation  910 ), a local temperature is adjusted by way of the local heater  62  (operation  920 ) and the local temperature is checked by way of the temperature sensing unit  64  (operation  930 ). If the local temperature is determined to not be within predefined parameters (operation  940 ), control returns to operation  920  by way of first loop  941 . If, on the other hand, the local temperature is determined to be within the predefined parameters at operation  940 , bias is applied to the DUT  61  and the reference DUT  65  for the Nth stress test (operation  950 ). Device parameters for the DUT  61  and the reference DUT  65 , such as drain current, resistance and driving current, are then measured at time T(N) (operation  960 ) and the measurements are compared (operation  965 ). The variable N is then set to N+1 (operation  970 ) and control returns to operation  710  along loop  971 . 
         [0029]    While the disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the disclosure not be limited to the particular exemplary embodiment disclosed as the best mode contemplated for carrying out this disclosure, but that the disclosure will include all embodiments falling within the scope of the appended claims.

Technology Category: g