Patent Document

FIELD OF THE INVENTION  
       [0001]     The present invention relates to the field of switching regulator and more particularly to smart start-up circuit for switching regulators.  
       BACKGROUND ART  
       [0002]     Switching regulator is a vitally important device. Switching regulators are building blocks used extensively in power systems, industry, motor, communication, networks, digital systems, consumer electronics, computers, and any other fields that high efficient voltage regulating functions.  
         [0003]     Switching regulators (i.e., DC-TO-DC converters) can provide output voltages which can be less than, greater than, or of opposite polarity to the input voltage. Prior Art  FIG. 1  illustrates a basic architecture of a conventional switching regulator  100 . The conventional switching regulator  100  basically consists of an oscillator, a reference circuit  102 , an error amplifier, a modulator including a comparator, resistors, and a control logic circuit. Control technique of switching regulators has typically used two modulators: a pulse-width modulator and a pulse-frequency modulator. The output DC level is sensed through the feedback loop including two resistors. An error amplifier compares two input voltages: the sampled output voltage and the reference voltage. The output of the error amplifier is compared against a periodic ramp generated by the saw tooth oscillator. The pulse-width modulator output passes through the control logic to the power switch. The feedback system regulates the current transfer to maintain a constant output voltage within the load limits. In other words, it insures that the output voltage level reaches the equilibrium. When the output voltage level reaches the equilibrium, V F  is equal to V REF , as shown in Prior Art  FIG. 1 .  
         [0004]     However, it takes a vast amount of time until the output voltage level reaches the equilibrium from an initial condition after the switching regulator of Prior Art  FIG. 1  starts. Therefore, power and time are consumed until the switching regulator&#39;s output voltage level reaches the equilibrium. In addition, it takes a long time to simulate and verify the conventional switching regulator  100  before fabrication since its simulation time is absolutely proportional to time that is required the switching regulator&#39;s output voltage level to reach the equilibrium. Hence, this long simulation adds additional cost and serious bottleneck to design time-to-market. In other words, the slow start-up of the switching regulator increases design simulation time. For these reasons, the conventional switching regulator  100  of Prior Art  FIG. 1  is very inefficient to implement in system-on-chip (SOC) or integrated circuit (IC).  
         [0005]     Thus, what is needed is a fast starting-up switching regulator that can be highly efficiently implemented with a drastic improvement in a very fast start-up time, start-up time controllability, performance, time-to-market, power consumption, power and time management, efficiency, cost, and design time. It is highly desirable to enable all of the switching regulators&#39; output voltage levels to reach the equilibrium immediately for much higher power efficiency or according to schedule. The present invention satisfies these needs by providing five embodiments.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention provides five types of the smart start-up circuits for switching regulators. The smart start-up circuits simultaneously enable any switching regulator&#39;s output voltage level to reach the equilibrium according to schedule. The basic architecture of the smart start-up circuits consists of a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor senses a voltage at its input. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the output voltage reaches the midpoint voltage. The time to reach the midpoint voltage at the load is simply equal to the charge stored at the load divided by the current, which can be scaled.  
         [0007]     Consequently, all smart start-up circuits provide a significant reduction in the difference between the initial output voltage level and the expected output voltage level in order to overcome serious drawbacks simultaneously. The smart start-up time of the present invention enables all systems to be managed in terms of power, stand-by time, and start-up time. The present invention provides five different embodiments which achieve a drastic improvement in a very fast start-up time, start-up time controllability, performance, time-to-market, power consumption, power and time management, efficiency, cost, and design time.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     The accompanying drawings, which are incorporated in and form a part of this specification, illustrate five embodiments of the invention and, together with the description, serve to explain the principles of the invention:  
         [0009]     Prior Art  FIG. 1  illustrates a block diagram of a conventional switching regulator (i.e., DC-TO-DC converter).  
         [0010]      FIG. 2  illustrates a block diagram of two types of smart start-up circuits for switching regulator in accordance with the present invention.  
         [0011]      FIG. 3  illustrates a circuit diagram of a basic smart start-up circuit according to the present invention.  
         [0012]      FIG. 4  illustrates a circuit diagram of a smart start-up circuit in accordance with the present invention.  
         [0013]      FIG. 5  illustrates a circuit diagram of a dual smart start-up circuit according to the present invention.  
         [0014]      FIG. 6  illustrates a circuit diagram of a p-type smart start-up circuit in accordance with the present invention.  
         [0015]      FIG. 7  illustrates a circuit diagram of a p-type dual smart start-up circuit according to the present invention.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0016]     In the following detailed description of the present invention, five types of the smart start-up circuits, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, CMOS digital gates, components, and metal-oxide-semiconductor field-effect transistor (MOSFET) device physics have not been described in detail so as not to unnecessarily obscure aspects of the present invention.  
         [0017]      FIG. 2  illustrates two types of the smart start-up circuits for switching regulators in accordance with the present invention. One type of the smart start-up circuit is applied for switching regulators driving a load  216  connected between V OUT  and ground, as seen in the switching regulator system  210  shown in  FIG. 2 . The other type of the smart start-up circuit called “p-type smart start-up circuit” is applied for switching regulators driving a load  226  connected between V DD  and V OUT , as seen in the switching regulator system  220  shown in  FIG. 2 . To reduce the difference between the initial output voltage level and the expected output voltage level of the switching regulator, the output of all the smart start-up circuits is coupled to the output terminal of switching regulators, as shown in  FIG. 2 . The switching regulator  212  represents all types of the switching regulators (i.e., DC-TO-DC converter) driving a load  216  connected between V OUT  and ground without regard to the types of switching regulators because the applications of the smart start-up circuit  214  are independent of architectures and types of switching regulators. The switching regulator  222  represents all types of the switching regulators (i.e., DC-TO-DC converter) driving a load  226  connected between V DD  and V OUT  without regard to the types of switching regulators because the applications of the p-type smart start-up circuit  224  are independent of architectures and types of switching regulators. If loads  216  and  226  are multiple-order, then they will be approximated to the first-order load with neglecting resistor and inductor in the load for simplicity.  
         [0018]      FIG. 3  illustrates a basic smart start-up circuit according to the present invention. This basic smart start-up circuit  300  does not have power-down mode in order to show the fundamental concept of the invention clearly. The basic smart start-up circuit  300  is a feedback circuit that consists of lower-voltage sensing inverters  302  and  312  (i.e., an even number of inverters), higher-voltage sensing inverters  304  and  324  (i.e., an even number of inverters), two stacked PMOS transistors  306  and  308 , two stacked NMOS transistors  326  and  328 , and a feedback line  310 . The gate terminal of a PMOS transistor  308  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  326  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.).  
         [0019]     It is assumed that the output of the basic smart start-up circuit  300  is at ground. Since the first lower-voltage sensing inverter  302  initially senses a voltage less than the lower midpoint voltage of the first lower-voltage sensing inverter  302 , the output voltage of the second lower-voltage sensing inverter  312  is low enough to turn on the PMOS transistor  306 . At the same time, the output voltage of the second higher-voltage sensing inverter  324  is low enough to turn off the NMOS transistor  328 . Thus, the PMOS transistor  306  provides a current (i.e., I P ,) to the output until the output voltage (i.e., V OUT ) goes up to the lower midpoint voltage of the first lower-voltage sensing inverter  302 . The time to reach the lower midpoint voltage at the load connected between V OUT  and ground is as follows:  
         Δ   ⁢           ⁢   t     =         V   M     ⁢     C   P         I   P           
 
 where V M  is the lower midpoint voltage determined by the device aspect ratios of the first lower-voltage sensing inverter  302  and C P  is the value of the capacitor in the load. Also, assuming that V M  is closer to the output voltage level that reaches the equilibrium in switching regulators, the start-up time of the switching regulators is approximately given by  
           V   M     ⁢     C   P         I   P         
 
 This start-up time is varied by the current I P  depending on the size of the PMOS transistor  306 . 
 
         [0020]     It is assumed that the output of the basic smart start-up circuit  300  is at power supply. Since the first higher-voltage sensing inverter  304  initially senses a voltage greater than the higher midpoint voltage of the first higher-voltage sensing inverter  304 , the output voltage of the second higher-voltage sensing inverter  324  is high enough to turn on the NMOS transistor  328 . At the same time, the output voltage of the second lower-voltage sensing inverter  312  is high enough to turn off the PMOS transistor  306 . Thus, the NMOS transistor  328  provides a current (i.e., I N ) to the output until the output voltage (i.e., V OUT ) goes down to the higher midpoint voltage of the first higher-voltage sensing inverter  304 . The time to reach the higher midpoint voltage at the load connected between V OUT  and power supply is as follows:  
         Δ   ⁢           ⁢   t     =         (       V   DD     -     V     M   ⁡     (   H   )           )     ⁢     C   P         I   N           
 
 where V M(H)  is the higher midpoint voltage determined by the device aspect ratios of the first higher-voltage sensing inverter  304  and C P  is the value of the capacitor in the load. Also, assuming that V M(H)  is closer to the output voltage level that reaches the equilibrium in switching regulators, the start-up time of the switching regulators is approximately given by  
           (       V   DD     -     V     M   ⁡     (   H   )           )     ⁢     C   P         I   N         
 
 This start-up time is varied by the current I N  depending on the size of the NMOS transistor  328 . 
 
         [0021]     The midpoint voltage is a voltage where the input voltage and the output voltage of the inverter are equal in the voltage transfer characteristic. At the midpoint voltage, the transistors of the inverter operate in the saturation mode. This midpoint voltage of inverter is expressed as  
             V   DD     -     V     T   n       -          V     T   P                1   +         K   n       K   p             +       V     T   n       ⁢           ⁢   where         
           K   n       K   p       =         μ   n     ⁢         C   OX     ⁡     (     W   L     )       n           μ   p     ⁢         C   OX     ⁡     (     W   L     )       p             
 
         [0022]     In design of the basic smart start-up circuit of  FIG. 3 , it is also desirable to use a value for the lower midpoint voltage, V M , less than V OUT ′ and a value for the higher midpoint voltage, V M(H) , greater than V OUT ′. V OUT ′ is the output voltage level that reaches the equilibrium in switching regulators.  
         [0023]      FIG. 4  illustrates a smart start-up circuit  400  according to the present invention. A power-down input voltage, V PD , is defined as the input voltage for power-down mode. The power-down enable system is in power-down mode when V PD  is V DD  and it is in normal mode when V PD  is zero. The smart start-up circuit  400  is a feedback circuit that consists of lower-voltage sensing inverters  402  and  412  (i.e., an even number of inverters), two stacked PMOS transistors  406  and  408 , two stacked NMOS transistors  426  and  428 , a feedback line  410 , and a power-down NMOS transistor  442 . In addition, the gate terminal of a PMOS transistor  408  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  426  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.). Furthermore, the gate terminal of a NMOS transistor  428  is shorted and thus no current flows into the drains of the NMOS transistors  426  and  428 .  
         [0024]     The circuit mode changes from power-down mode to normal mode in  FIG. 4 . Since the first lower-voltage sensing inverter  402  initially senses a voltage less than the lower midpoint voltage of the first lower-voltage sensing inverter  402 , the output voltage of the second lower-voltage sensing inverter  412  is low enough to turn on the PMOS transistor  406 . The PMOS transistor  406  generates a current (i.e., I P ) to the output until the output voltage (i.e., V OUT ) goes up to the lower midpoint voltage of the first lower-voltage sensing inverter  402 . Furthermore, assuming that V M  is closer to the output voltage level that reaches the equilibrium in switching regulators, the start-up time of the switching regulators is approximately given by  
           V   M     ⁢     C   P         I   P         
 
 Also, V M  is the lower midpoint voltage determined by the device aspect ratios of the first lower-voltage sensing inverter  402  and C P  is the value of the capacitor in the load. The start-up time is varied by the current I P  depending on the size of the PMOS transistor  406 . 
 
         [0025]     In design of the smart start-up circuit of  FIG. 4 , it is also desirable to use a value for the lower midpoint voltage, V M , less than V OUT ′. V OUT  ′ is the output voltage level that reaches the equilibrium in switching regulators. The smart start-up circuit  400  is used for all types of switching regulators driving the load connected between V OUT  and ground. Since the power-down NMOS transistor  442  is on during power-down mode, it provides an output pull-down path to ground. Thus, V OUT  of the smart start-up circuit  400  is zero so that no current flows into the circuits during power-down mode.  
         [0026]      FIG. 5  illustrates a dual smart start-up circuit  500  in accordance with the present invention. The dual smart start-up circuit  500  is a modification of the circuit described in  FIG. 4 . The gate terminal of a PMOS transistor  508  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  526  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.). Furthermore, compared to  FIG. 4 , the first difference to note is that the higher-voltage sensing inverters  504  and  524  (i.e., an even number of inverters) are added into  FIG. 5  in order to provide the higher-voltage sensing function. The second difference to note is that the output of the second higher-voltage sensing inverter  524  is connected to the gate terminal of a NMOS transistor  528 . Therefore, the dual smart start-up circuit  500  is able to sense the lower-voltage as well as the higher-voltage while the smart start-up circuit  400  is able to sense only the lower-voltage.  
         [0027]     No current flows into the drains of the NMOS transistors  526  and  528  assuming V OUT &lt;V M(H)  where V M(H)  is the higher midpoint voltage decided by the device aspect ratios of the first higher-voltage sensing inverter  504 . If V OUT  is greater than V M(H) , the gate voltage of the NMOS transistor  528  is V DD . As a result, a current flows into the drains of the NMOS transistors  526  and  528  until V OUT  goes down to V M(H) .  
         [0028]     In design of the dual smart start-up circuit of  FIG. 5 , it is also desirable to use a value for the lower midpoint voltage, V M , less than V OUT  ′ and a value for the higher midpoint voltage, V M(H)  greater than V OUT ′ . V OUT  ′ is the output voltage level that reaches the equilibrium in switching regulators. V M  is the lower midpoint voltage decided by the device aspect ratios of the first lower-voltage sensing inverter  502 . The dual smart start-up circuit  500  is used for all types of switching regulators driving the load connected between V OUT  and ground. Zero dc volt at V OUT  ensures that no current flows into the circuits during power-down mode.  
         [0029]      FIG. 6  illustrates a p-type smart start-up circuit  600  according to the present invention. The power-down input voltage, V PD , is defined as the input voltage for the p-type power-down mode as well as for the power-down mode. The p-type power-down enable system is in power-down mode when V PD  is V DD  and it is in normal mode when V PD  is zero. The p-type smart start-up circuit  600  is a feedback circuit that consists of a higher-voltage sensing inverters  604  and  624  (i.e., an even number of inverters), two stacked PMOS transistors  606  and  608 , two stacked NMOS transistors  626  and  628 , a feedback line  610 , a power-down inverter  614 , and a power-down PMOS transistor  642 . In addition, the gate terminal of a PMOS transistor  608  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  626  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.). Furthermore, since the PMOS transistor  606  is turned off, no current flows out of the drains of the PMOS transistors  606  and  608 .  
         [0030]     The circuit mode changes from p-type power-down mode to normal mode in  FIG. 6 . Since the first higher-voltage sensing inverter  604  initially senses a voltage greater than V M(H) , the output voltage of the second higher-voltage sensing inverter  624  is high enough to turn on the NMOS transistor  628 . V M(H)  is the higher midpoint voltage decided by the device aspect ratios of the first higher-voltage sensing inverter  604 . The NMOS transistor  628  generates a current (i.e., I N ) to the output until the output voltage (i.e., V OUT ) goes down to V M(H) . Assuming that V M(H)  is closer to the output voltage level that reaches the equilibrium in switching regulators, the start-up time of the switching regulators is approximately given by  
           (       V   DD     -     V     M   ⁡     (   H   )           )     ⁢     C   P         I   N         
 
 Also, C P  is the value of the capacitor in the load. The start-up time is varied by the current I N  depending on the size of the NMOS transistor  628 . 
 
         [0031]     In design of the p-type smart start-up circuit of  FIG. 6 , it is also desirable to use a value for the higher midpoint voltage, V M(H) , greater than V OUT ′. V OUT  ′ is the output voltage level that reaches the equilibrium in switching regulators. The p-type smart start-up circuit  600  is used for all types of switching regulators driving the load connected between V OUT  and power supply. The output voltage of the power-down inverter  614 , V PDB , is zero during power-down mode. As a result, the power-down PMOS transistor  642  is turned on and thus provides an output pull-up path to V DD . Therefore, V OUT  of the p-type smart start-up circuit  600  is V DD  so that no current flows into the circuits during power-down mode. On the contrary, it was stated earlier that V OUT , must be zero when power-down mode occurs in  FIG. 4  and  FIG. 5 .  
         [0032]      FIG. 7  illustrates a p-type dual smart start-up circuit  700  in accordance with the present invention. The p-type dual smart start-up circuit  700  is a modification of the circuit described in  FIG. 6 . The gate terminal of a PMOS transistor  708  is connected to a proper fixed-bias voltage (not shown) or ground (e.g., “0”, low, etc.). The gate terminal of a NMOS transistor  726  is connected to a proper fixed-bias voltage (not shown) or power supply voltage (e.g., V DD , “1”, high, etc.). Compared to  FIG. 6 , the first difference to note here is that the lower-voltage sensing inverters  702  and  712  (i.e., an even number of inverters) are added into  FIG. 7  in order to sense the lower-voltage. The second difference to note here is that the output of the second lower-voltage sensing inverter  712  is connected to the gate terminal of the PMOS transistor  706 . The p-type dual smart start-up circuit  700  is able to sense the lower-voltage as well as the higher voltage while the p-type smart start-up circuit  600  is able to sense only the higher voltage.  
         [0033]     No current flows out of the drains of the PMOS transistors  706  and  708  if V OUT  is greater than V M . V M  is the lower midpoint voltage decided by the device aspect ratios of the first lower-voltage sensing inverter  702 . If V OUT  is less than V M , the PMOS transistor  706  is turned on until V OUT  goes up to V M . In design of the p-type dual smart start-up circuit of  FIG. 7 , it is also desirable to use a value for the higher midpoint voltage, V M(H) , greater than V OUT  ′ and a value for the lower midpoint voltage, V M , less than V OUT ′. V OUT  ′is the output voltage level that reaches the equilibrium in switching regulators. The p-type dual smart start-up circuit  700  is used for all types of switching regulators driving the load connected between V OUT  and power supply. V OUT =V DD  in the p-type dual smart start-up circuit  700  ensures that no current flows into the circuits during power-down mode.  
         [0034]     In summary, the five smart start-up circuits of the present invention within switching regulators simply control how fast the output voltage level reaches the equilibrium from an initial output voltage level. The balance between PMOS output resistance and NMOS output resistance is important to obtain high output resistance. Furthermore, the CMOS process variations usually must be considered so that the proper value of the midpoint voltage is chosen for all the smart start-up circuits  300 ,  400 ,  500 ,  600 , and  700 . Each bulk of two stacked PMOS transistors can be connected to its own N-well to obtain better immunity from substrate noise in all the smart start-up circuits  300 ,  400 ,  500 ,  600 , and  700 .  
         [0035]     The smart start-up circuit  214  shown in  FIG. 2  represents the basic smart start-up circuit  300 , the smart start-up circuit  400 , and the dual smart start-up circuit  500 , as shown in  FIG. 3 ,  FIG. 4 , and  FIG. 5 , respectively. Also, the p-type smart start-up circuit  224  shown in  FIG. 2  represents the basic smart start-up circuit  300 , the p-type smart start-up circuit  600  and the p-type dual smart start-up circuit  700 , as shown in  FIG. 3 ,  FIG. 6 , and  FIG. 7 , respectively. The conventional switching regulator  100  and the switching regulator system  210  including the basic smart start-up circuit  300  are simulated using the same components. As a result, the total simulation time of the conventional switching regulator  100  is 40 hours and that of the switching regulator system  210  using (W/L) MP1 =6u/1u of the PMOS transistor  306  is 3 hours. This improvement can be accomplished by simply inserting a proper one of the smart start-up circuits into any conventional switching regulator, and the simulation time can be reduced by a factor of 13. It should be noted that the same time step has been used for the SPICE simulation in order to accurately measure and compare the simulation time of all circuits.  
         [0036]     All the smart start-up circuits of the present invention are very efficient to implement in system-on-chip (SOC) or integrated circuit (IC). The present invention provides five different embodiments which achieve a drastic improvement in a very fast start-up time, start-up time controllability, performance, time-to-market, power consumption, power and time management, efficiency, cost, and design time. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as being limited by such embodiments, but rather construed according to the claims below.

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