Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    This application claims the benefit under 35 U.S.C.§119(e) of Provisional Appl. No. 61/629,231, filed Nov. 14, 2011, which is incorporated herein by reference in its entirety. 
     
    
       [0002]    Embodiments of the present embodiments relate to a power supply protection circuit to temporarily maintain a functional power supply level for an integrated circuit in the event of power failure. 
         [0003]    Power failure in integrated circuits may occur for a variety of reasons including external power failure, faulty battery contacts, sudden shock to portable devices such as dropping a cell phone, or circuit failure due to hardware or software problems. Power failure is often harmless, and integrated circuits are typically designed to provide an orderly shut down when a power failure is detected. This, however, may require large decoupling capacitors to maintain a functional power supply level and may be inadequate in the event of critical circuit operations. For example, if a power failure occurs during a write operation in a nonvolatile memory, data may be lost. Likewise, if a power failure occurs during transmission of a data frame, data may be lost. If a power failure occurs during a transfer of control in a processor circuit, a jump or subroutine call instruction may produce an incorrect address in an instruction pointer, thereby causing the processor circuit to “hang up.” Alternatively, if a power failure occurs during a disk write operation, incorrect data may be written to the disk resulting in a corrupt data file. Unexpected power failure in electronic devices, therefore, tends to cause temporary or permanent data loss in a wide variety of electronic devices. 
       BRIEF SUMMARY OF THE INVENTION 
       [0004]    In a preferred embodiment of the present invention, a method of protecting a power supply voltage is disclosed. The method includes storing charge in a charge reservoir capacitor, receiving a power supply sample voltage, and receiving a load power supply voltage. The power supply sample voltage is compared to the load power supply voltage, and charge is added from the charge reservoir capacitor to the load power supply in response to the step of comparing. The present invention maintains a substantially constant load power supply voltage in the event of a power failure during a memory access cycle, a transmit cycle, or other critical operation where data may otherwise be lost. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0005]      FIG. 1  is a simplified schematic diagram of a power supply protection circuit of the present invention; 
           [0006]      FIG. 2  is a more detailed schematic diagram of the power supply protection circuit of  FIG. 1 ; 
           [0007]      FIG. 3  is an alternative embodiment of the circuit diagram of  FIG. 2 ; 
           [0008]      FIG. 4  is a schematic diagram showing a latch circuit for producing a power fail signal; 
           [0009]      FIG. 5  is a timing diagram illustrating operation of the circuit of  FIG. 2 ; and 
           [0010]      FIG. 6  is a table of normalized values for C P  and C R  in relation to C L . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0011]    The preferred embodiments of the present invention provide significant advantages of power supply protection over integrated circuits of the prior art as will become evident from the following detailed description. 
         [0012]    Referring to  FIG. 1 , there is a simplified schematic diagram of a power supply protection circuit of the present invention. Here and in the following discussion the same reference numerals of various figures refer to the same elements. The circuit includes capacitor C S    140  arranged to store a power supply sample voltage, a charge reservoir capacitor C R    142 , and a pump capacitor C P    144 . Comparator  150  has one input terminal coupled to capacitor C S  and a second input terminal coupled to capacitor C P . The output terminal of comparator  150  is coupled to a control terminal of p-channel transistor  126 . P-channel transistor  126  has a current path coupled between capacitor C R  and capacitor C P . Capacitor C P  is coupled to load power supply VDDL terminal  102 . The load power supply VDDL provides a power supply voltage to load circuit  160 . N-channel transistor  128  is coupled to receive complementary power fail signal/PFAIL on lead  106 . The circuit also includes p-channel transistors  120 - 124  having control terminals coupled to receive power fail signal PFAIL on lead  104 . Each of p-channel transistors  120 - 124  has a respective current path to couple power supply voltage VDD terminal  100  to respective circuit elements as will be discussed in detail. Each of p-channel transistors  120 - 124  also has an n-well bulk terminal (not shown) coupled to the respective current path terminal opposite power supply VDD terminal  100 . This prevents forward biasing parasitic PNP transistors if power supply voltage VDDL becomes more positive than power supply voltage VDD. During power up, therefore, the ramp rate of power supply voltage VDD should be regulated to prevent a voltage across any of p-channel transistors  120 - 124  from exceeding a diode drop. 
         [0013]    In normal operation, power fail signal PFAIL remains low and complementary power fail signal/PFAIL remains high. In this state, p-channel transistors  120 - 124  and n-channel transistor  128  are on. P-channel transistor  120  charges capacitor C S    140  to power supply voltage VDD. P-channel transistor  121  applies power supply voltage VDD to load power supply VDDL terminal  102  and to comparator  150 . P-channel transistor  122  applies power supply voltage VDD to the control terminal of p-channel transistor  126 , so that it remains off in normal operation. P-channel transistor  124  charges capacitor C R    142  to power supply voltage VDD. N-channel transistor  128  connects terminal  112  to ground or reference supply terminal VSS as indicated by the small triangle to charge capacitor C P  to power supply voltage VDD or load power supply voltage VDDL. 
         [0014]    Referring now to  FIG. 2 , there is a more detailed schematic diagram of the power supply protection circuit of  FIG. 1 . In this embodiment, comparator circuit  150  includes p-channel transistors  200 - 202  and n-channel transistors  204 - 206  and  216 . P-channel transistor  208  and n-channel transistor  212  produce a reference voltage at the control gate of n-channel transistor  216 . In normal operation, however, power fail signal PFAIL remains low so that n-channel transistors  210  and  214  remain off. This disables both the reference circuit ( 208 ,  212 ) and the comparator circuit ( 202 - 206  and  216 ) so that no power is consumed by either circuit during normal operation. 
         [0015]    Referring next to  FIG. 4 , there is a latch circuit that may be used to produce power fail signal PFAIL and complementary power fail signal/PFAIL. NAND gate  400  is coupled to receive power fail signal PFAIL* and control signal ACTIVE. Power fail signal PFAIL* is typically produced by a memory controller or other control circuit powered by VDD. Alternatively, power fail signal PFAIL* may be generated by a comparator circuit which compares power supply voltage VDD to a predetermined threshold. During normal operation, therefore, power fail signal PFAIL* remains low. Control signal ACTIVE goes high to indicate a critical operation is in progress. This may be an active memory cycle, a transmit signal, a transfer of control operation in a processor circuit, a disk write operation, or any other operation that should be completed before a complete power loss occurs. NAND gates  400 - 404  are preferably powered by load power supply voltage VDDL and latch the state of the power fail signal PFAIL*. 
         [0016]    In normal operation, power fail signal PFAIL* remains low, so the output on NAND gate  400  is high. When control signal ACTIVE is low, complementary power fail signal/PFAIL at the output of NAND gate  404  is high. The high levels of both input signals at the input terminals of NAND gate  402  produces a low level of power fail signal PFAIL at lead  104 . When control signal ACTIVE at lead  410  goes high, there is no change in the state of the latch circuit, since the low level of power fail signal PFAIL at lead  104  disables NAND gate  404 . 
         [0017]    Turning now to  FIG. 5 , operation of the power supply protection circuit of  FIG. 2  and the latch circuit of  FIG. 4  will be explained in detail. During normal operation, control signal ACTIVE at lead  410  goes high at time t 0 , thereby indicating the start of a critical circuit operation. At time t 1  a failure of power supply VDD and load power supply VDDL begins  500 . The power supply failure is detected at time t 2    502 , and power fail signal PFAIL* goes high. The high level of PFAIL* and control signal ACTIVE produce a low level output from NAND gate  400 . The low level from NAND gate  400  produces a high level output from NAND gate  402  of power fail signal PFAIL at lead  104 . The high level of power control signal PFAIL at lead  104  together with the high level of control signal ACTIVE at lead  410  produce a low level output of complementary power fail signal/PFAIL at lead  106 . The latch circuit remains in this state while control signal ACTIVE remains high without regard to the state of power fail signal PFAIL*. 
         [0018]    Returning now to  FIGS. 2 and 4 , the low level of complementary power fail signal/PFAIL turns off n-channel transistor  128  so that terminal  112  of capacitor C P  is no longer connected to reference voltage VSS or ground. The high level of power fail signal PFAIL at lead  104  performs several operations. First, it turns on n-channel transistors  210  and  214 . This produces a reference voltage at the control gate of n-channel transistor  216  and enables comparator circuit  150  ( 200 - 206 ,  216 ). At the same time, the high level of power fail signal PFAIL turns off p-channel transistors  120 - 124  and produces several results. First, the off state of P-channel transistor  120  stores a power supply sample voltage VDDL on capacitor C S . Thus, the control gate of n-channel transistor  206  remains at VDDL. Second, the off state of p-channel transistor  121  isolates power supply voltage VDD at lead  100  from load power supply voltage VDDL at lead  102 . Third, the off state of p-channel transistor  122  isolates power supply voltage VDD at lead  100  from the control gate of p-channel transistor  126 , so the conductivity of p-channel transistor  126  is determined by the output of comparator circuit  150  at lead  110 . Finally, the off state of p-channel transistor  124  isolates power supply voltage VDD at lead  100  from capacitor C R    142 . In this state, if power supply voltage VDDL at the control gate of n-channel transistor  204  falls below the power supply sample voltage on capacitor C S    140 , the output voltage of comparator  150  at lead  110  goes lower. This lower output voltage makes p-channel transistor  126  more conductive. As a result, the voltage at lead  108  decreases as the voltage at lead  112  increases at time t 3  ( FIG. 5 ). The increasing voltage at lead  112  pumps current through capacitor C P    144  to restore load power supply voltage VDDL on lead  102  to substantially the same voltage as the power supply sample voltage on capacitor C S    140 . In other words, the current through capacitor C P    144  is substantially the same as the current consumed by load circuit  160 . Thus, load power supply voltage VDDL remains substantially constant. Finally, control signal ACTIVE at lead  410  returns to a low level at time t 4  indicating the end of the critical circuit operation. The low level of control signal ACTIVE resets the latch circuit of  FIG. 4 . Thus, power fail signal PFAIL at lead  104  returns to a low level, and complementary power fail signal/PFAIL at lead  106  returns to a high level. 
         [0019]    The present power supply protection circuit is highly advantageous for several reasons. First, it maintains a relatively constant power supply voltage for specific circuits during critical operations even when an external power supply voltage may fail. Second, it consumes no additional power during normal circuit operation except to initially charge capacitors C S , C R , and C P . Third, load current is supplied at the rate required by load circuit  160 , so that load power supply voltage VDDL remains constant even with varying load current. 
         [0020]    Referring now to  FIG. 3 , there is an alternative embodiment of the power supply protection circuit of  FIG. 2 . In this embodiment, boost capacitor C B    300  is added to the power supply protection circuit of  FIG. 2  as shown. Recall from the discussion of  FIG. 5  that load power supply voltage VDDL degraded until a power failure was detected and power fail signal PFAIL* was produced. After this, load power supply voltage VDDL remained substantially equal to the voltage on capacitor C S . According to the embodiment of  FIG. 3 , boost capacitor C B  couples voltage to capacitor C S  in response to the rising edge of power fail signal PFAIL. Thus, the voltage on capacitor C S  is approximately equal to the original value of load power supply voltage VDDL rather than the degraded value at time t 3 . Responsively, the power supply protection circuit of  FIG. 2  with the modification of  FIG. 3  restores and maintains load power supply voltage VDDL at the original value at time t 0  rather than the degraded value at time t 3 . 
         [0021]    Referring now to  FIG. 6 , there is a table of normalized values for C P  and C R  in relation to C L . Here, for the purpose of discussion it is assumed that load circuit  160  comprises load capacitor C L  and that no load current is consumed. This assumption is useful to determine the charge or voltage coupled to load capacitor C L  for various values of reservoir capacitor C R    142  and pump capacitor C P    144 . The table of  FIG. 6  includes three columns and twenty rows. The first column is a ratio of C R /C L  and varies from 0.1 to 2.0. The second column is a ratio of C P /C R  and corresponds to the values of C R /C L  in the first column. The third column dV shows normalized values of the voltage coupled to capacitor C L  for the values of C R  and C P  in the same row. For example, if C R  is charged to 1.0 V, for C R /C L =1.0 and C P /C R =1.4, 0.389 V is coupled to capacitor C L . In general, as the ratio of C R /C L  increases, dV may increase. However, this also depends on the value pump capacitor C P . The ratio of C P /C R  in the second column is selected to minimize the value of total capacitance divided by dV ((C R +C P +C L )/dV). In other words, in the previous the ratio of total capacitance to dV is 8.743e-10 for C L =1e-10. If the ratio C P /C R  is reduced to 1.3, the ratio of total capacitance to dV increases to 8.758e-10. Correspondingly, if the ratio C P /C R  is increased to 1.5, the ratio of total capacitance to dV increases to 8.750e-10. Thus, the second column is the ratio of C P /C R  that produces a local minimum of the ratio of total capacitance to dV. 
         [0022]    The present invention advantageously reduces the need for a decoupling capacitor in parallel with load circuit  160 . For example, if the capacitance of load circuit  160  is taken as C L  and the ratio of C R /C L  is taken as 1.0, then C P /C R  may be 1.4. In this example, C R =C L  and C P =1.4 C L . When a power supply failure is detected, reservoir capacitor C R  pumps all available charge to load circuit  160 . Power supply voltage VDDL then degrades to 90% of the supply voltage prior to failure at time T. In order to simply attain 90% of the initial supply voltage prior to failure at time T a decoupling capacitor in parallel with load circuit  160  must be 6.44 C L . By way of comparison, the 90% supply voltage at time T is achieved with only 2.4 C L  (C P +C R ) with the present invention. Thus, the value of C P +C R  is only 37% of the size of a decoupling capacitor (6.44 C L ) that would be added in parallel with load circuit  160  to achieve the 90% value at time T. 
         [0023]    Still further, while numerous examples have thus been provided, one skilled in the art should recognize that various modifications, substitutions, or alterations may be made to the described embodiments while still falling with the inventive scope as defined by the following claims. Embodiments of the present invention may be applied to virtually any circuit to temporarily maintain a functional power supply voltage should an unexpected power supply failure occur during a critical circuit operation. Other combinations will be readily apparent to one of ordinary skill in the art having access to the instant specification.

Technology Category: 5