Patent Document

TECHNICAL FIELD 
       [0001]    The present disclosure relates to a non-volatile logic circuit and a method for operating the same comprising a laminate formed of a ferroelectric film and a semiconductor film. 
       BACKGROUND 
       [0002]    Patent Document 1 discloses a non-volatile switching device.  FIGS. 8A and 8B  show a conventional non-volatile switching device disclosed in FIG. 3 of Patent Document 1. 
         [0003]    As shown in  FIG. 8A , the non-volatile switching device comprises a substrate  11 , a control electrode  12 , a ferroelectric layer  13 , a semiconductor layer  14 , and first to third electrodes  15   a  to  15   c . The control electrode  12 , the ferroelectric layer  13 , and the semiconductor layer  14  are stacked in this order on the substrate  11 . The first to third electrodes  15   a  to  15   c  are provided on the semiconductor layer  14 . 
         [0004]    A voltage is applied between the control electrode  12  and the first to third electrodes  15   a  to  15   c  to change the polarization direction of the ferroelectric layer  13 . 
         [0005]    In a case where a part of the ferroelectric layer  13  has an upward polarization direction, the part of the semiconductor layer  14  stacked on the part of the ferroelectric layer  13  has low resistance. This corresponds to the ON-state. 
         [0006]    On the contrary, in a case where a part of the ferroelectric layer  13  has a downward polarization direction, the part of the semiconductor layer  14  stacked on the part of the ferroelectric layer  13  has high resistance. This corresponds to the OFF-state. 
         [0007]    In  FIG. 8A , only the part of the ferroelectric layer  13  positioned below the third electrode  15   c  has downward polarization direction. Accordingly, as shown in  FIG. 8B , a current flows selectively from the first electrode  15   a  to the second electrode  15   b.    
       PRIOR ARTS 
     Patent Document 
       [0000]    
       
         [Patent Document1] Japanese laid-open patent publication No. 2009-099606 
       
     
       SUMMARY 
       [0009]    The purpose of the present disclosure is to provide a novel non-volatile logic circuit and a method for operating the same utilizing the change of resistance states shown in  FIG. 8 . 
         [0010]    In order to accomplish above described purpose, one aspect of the present disclosure provides a method of operating a non-volatile logic circuit. This method comprises the following steps (a) to (c): A step (a) is preparing the non-volatile logic circuit. The non-volatile logic circuit comprises a control electrode, a ferroelectric layer, a semiconductor layer, and an electrode group. The control electrode, the ferroelectric layer, the semiconductor layer, and the electrode group are stacked in this order. The electrode group comprises a electric current power electrode, an output electrode, a first input electrode, and a second input electrode. When X direction, Y-direction, and Z-direction denote a longitudinal direction of the ferroelectric layer, a direction orthogonal to the longitudinal direction, and a stacking direction, respectively, the first input electrode and the second input electrode are interposed between the electric current power electrode and the output electrode along the X-direction, and the first input electrode is next to the second input electrode along the Y-direction, 
         [0011]    A step (b) is writing one state selected from the group consisting of first, second, third, and fourth states into the non-volatile logic circuit. V 1 , Va, and Vb are voltages applied to the control electrode, the first input electrode, and the second input electrode, respectively. When the first state is written, voltages being applied which satisfy inequalities: V 1 &gt;Va and V 1 &gt;Vb. When the second state is written, voltages being applied which satisfy inequalities: V 1 &lt;Va and V 1 &gt;Vb. When the third state is written, voltages being applied which satisfy inequalities: V 1 &gt;Va and V 1 &lt;Vb. When the fourth state is written, voltages being applied which satisfy inequalities: V 1 &lt;Va and V 1 &lt;Vb. The first, second and third states are low resistant states, and the fourth state is a high resistant state. 
         [0012]    A step (c) is measuring current generated by applying an voltage between the electric current power electrode and the output electrode to determine on the basis of the current which of the high or low resistant state the non-volatile logic circuit has. 
         [0013]    The method may further comprise the following step between the step (a) and the step (b): applying a voltage Vin to the first and second input electrodes and a voltage Vreset (the Vreset&gt;the Vin) to the control electrode to reset the non-volatile logic circuit. 
         [0014]    In the step (b), a first input signal which is either true or false may be input to the first input electrode, and a second input signal which is either true or false may be input to the second input electrode. In the step (c), the high resistant state may correspond to false of logical disjunction on the basis of the first and second input signals, and the low resistant state may correspond to true of logical disjunction on the basis of the first and second input signals. 
         [0015]    The method may further comprise the following step between the step (a) and the step (b): turning off the non-volatile logic circuit. 
         [0016]    The present subject matter provides a novel non-volatile logic circuit and a method for operating the same. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0017]      FIG. 1A  shows an exemplary top view of the nonvolatile logic circuit according to the embodiment 1. 
           [0018]      FIG. 1B  shows a cross-sectional view of A-A′ line in  FIG. 1A . 
           [0019]      FIG. 2  shows an exemplary top view of the nonvolatile logic circuit according to the embodiment 1. 
           [0020]      FIG. 3  shows a table of the truth value in the embodiment 1. 
           [0021]      FIG. 4  shows the voltages of the input electrodes  17   a - 17   b  during writing. 
           [0022]      FIG. 5A  shows an exemplary top view of the input electrodes  17   a - 17   b  in the first condition. 
           [0023]      FIG. 5B  shows an exemplary top view of the input electrodes  17   a - 17   b  in the second condition. 
           [0024]      FIG. 5C  shows an exemplary top view of the input electrodes  17   a - 17   b  in the third condition. 
           [0025]      FIG. 5D  shows an exemplary top view of the input electrodes  17   a - 17   b  in the fourth condition. 
           [0026]      FIG. 6  shows a polarization condition of the ferroelectric film  13  and the condition of the semiconductor film  14  when the voltage of −10 volts and the voltage of 10 volts are applied to the first input electrode  17   a  and the second input electrode  17   b , respectively. 
           [0027]      FIG. 7  shows resistance values calculated in the first to fourth states. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0028]    The embodiment of the present subject matter is described below with reference to the drawings. 
       Embodiment 1 
       [0029]      FIG. 1A  shows a top view of the nonvolatile logic circuit according to the embodiment 1.  FIG. 1B  shows a cross-sectional view of the A-A′ line in  FIG. 1A . 
         [0030]    As shown in  FIG. 1A  and  FIG. 1B , a ferroelectric film  13  and a semiconductor film  14  are stacked on a substrate  11 . A control electrode  12  is interposed between the ferroelectric film  13  and the substrate  11 . 
         [0031]    An electrode group is formed on the semiconductor film  14 . The electrode group comprises a power electrode  15 , an output electrode  16 , a first input electrode  17   a , and a second input electrode  17   b . In a top view, the input electrodes  17   a - 17   b  are interposed between the power electrode  15  and the output electrode  16 . 
         [0032]    The disposition relationship of the input electrodes  17   a - 17   b  is described below in more detail. 
         [0033]    As shown in  FIG. 1A  and  FIG. 1B , X-direction, Y-direction, and Z-direction denote the longitudinal direction of the ferroelectric film  13 , the direction orthogonal to the longitudinal direction, and the stacking direction of the films  13 - 14 , respectively. 
         [0034]    The first input electrode  17   a  and the second input electrode  17   b  are interposed between the power electrode  15  and the output electrode  16 . 
         [0035]    Along the X-direction, the first input electrode  17   a  is interposed between the power electrode  15  and the output electrode  16 . The second input electrode  17   b  is interposed between the power electrode  15  and the output electrode  16 . 
         [0036]    Along the Y-direction, the first input electrode  17   a  is adjacent to the second input electrode  17   b.    
         [0037]    In the nonvolatile logic circuit  20 , the current flowing through the semiconductor film  14  is determined depending on the direction of the polarization in the ferroelectric film  13 . Namely, when the polarization direction of the ferroelectric film  13  agrees with the +Z direction, the electrons induced in the semiconductor film  14  causes the semiconductor film  14  to have low resistance. On the contrary, when the polarization direction of the ferroelectric film  13  agrees with the −Z direction, the expulsion of the electrons from the semiconductor film  14  causes the semiconductor film  14  to have high resistance. 
         [0038]    Voltages between the input electrodes  17   a - 17   b  and the control electrode  12  are applied to modify the resistance value of the semiconductor film  14 . As a result, the resistance value between the power electrode  15  and the output electrode  16  varies. 
         [0039]    The nonvolatile logic circuit  20  performs a logical disjunction of two inputs-one output. Two input signals are consisted of a first input signal and a second input signal. As shown in  FIG. 2 , the first input signal and the second input signal are input to the first input electrode  17   a  and the second input electrode  17   b , respectively. The execution result of the logical disjunction is output on the basis of the table of the truth value shown in  FIG. 3 . 
         [0040]    (Writing into the Non-Volatile Logic Circuit  20 ) 
         [0041]    Next, the writing data into the non-volatile logic circuit  20  is described with reference to  FIG. 4 ,  FIG. 5 , and  FIG. 6 . 
         [0042]      FIG. 4  shows the voltages of the input electrodes  17   a - 17   b  during writing. A voltage of −10 V is input as “1” shown in  FIG. 3 . A voltage of 10 V is input as “0”. The voltage at the control electrode  12  is maintained at a constant value, which is preferably 0 volts. 
         [0043]      FIG. 5A  shows a top view of the input electrodes  17   a - 17   b  in the first condition. 
         [0044]      FIG. 5B  shows a top view of the input electrodes  17   a - 17   b  in the second condition. 
         [0045]      FIG. 5C  shows a top view of the input electrodes  17   a - 17   b  in the third condition. 
         [0046]      FIG. 5D  shows a top view of the input electrodes  17   a - 17   b  in the fourth condition. 
         [0047]      FIG. 6  illustrates the polarization condition of the ferroelectric film  13  and the condition of the semiconductor film  14  when the voltage of −10 volts and the voltage of 10 volts are applied to the first input electrode  17   a  and the second input electrode  17   b . The semiconductor region  31  located below the input electrode  33 , to which −10 V is applied, has low resistance because of accumulation of electrons caused by the polarization  30   a  of the ferroelectric film  13 . On the contrary, the semiconductor region  32  located below the input electrode  34 , to which 10 V is applied, has high resistance because the electrons have been expelled due to the polarization  30   b  of the ferroelectric film  13 . 
         [0048]    The writing procedures of the first, second, third and fourth conditions are described below. 
         [0049]    Preferably, a reset operation is performed before starting the writing operation. In the reset operation, a voltage Vin is applied to the input electrodes  17   a - 17   d , and a voltage Vreset, which satisfies Vin&lt;Vreset, is applied to the control electrode  12 . Specifically, it is preferred that 0 volts be applied to the input electrodes  17   a - 17   d  while 10 volts be applied to the control electrode  12 . Thus, all of the polarization directions in the ferroelectric film  13  are configured to be upward. 
         [0050]    The reset operation allows the nonvolatile logic circuit  20  to be operated with high reproducibility. 
         [0051]    During writing, V 1 , Va, and Vb are applied respectively to the control electrode  12 , the first input electrode  17   a , and the second input electrode  17   b  to polarize the respective portions of the ferroelectric film  13  located below the input electrodes  17   a - 17   b . This polarization causes the respective regions of the semiconductor film  14  located below the input electrodes  17   a - 17   b  to have high or low resistance. One condition selected from the first, second, third, and fourth conditions is written into the nonvolatile logic circuit  20 . 
         [0052]    When the first state is written, the voltages V 1 , Va, and Vb, which satisfy the following relationship (I), are applied: 
         [0000]      V1&gt;Va and V1&gt;Vb  (I).
 
         [0053]    Specifically, while V 1  is maintained at 0 volts, Va of −10 volts, and Vb of −10 volts are applied. 
         [0054]    When −10V and +10V correspond to true (1) and false (0) respectively, true (1) and true (1) are input to the first input electrode  17   a  and the second input electrode  17   b , respectively, in the first state. 
         [0055]    When the second state is written, the voltages V 1 , Va, and Vb, which satisfy the following relationship (II), are applied: 
         [0000]      V1&lt;Va and V1&gt;Vb  (II).
 
         [0056]    Specifically, while V 1  is maintained at 0 volts, Va of +10 volts, and Vb of −10 volts are applied. 
         [0057]    False (0) and true (1) are input to the first input electrode  17   a  and the second input electrode  17   b , respectively, in the second state. 
         [0058]    When the third state is written, the voltages V 1 , Va, and Vb, which satisfy the following relationship (III), are applied: 
         [0000]      V1&gt;Va and V1&lt;Vb  (III).
 
         [0059]    Specifically, while V 1  is maintained at 0 volts, Va of −10 volts, and Vb of +10 volts are applied. 
         [0060]    True (1) and false (0) are input to the first input electrode  17   a  and the second input electrode  17   b , respectively, in the third state. 
         [0061]    When the fourth state is written, the voltages V 1 , Va, and Vb, which satisfy the following relationship (IV), are applied: 
         [0000]      V1&lt;Va and V1&lt;Vb  (IV).
 
         [0062]    Specifically, while V 1  is maintained at 0 volts, Va of +10 volts, and Vb of +10 volts are applied. 
         [0063]    False (0) and false (0) are input to the first input electrode  17   a  and the second input electrode  17   b , respectively, in the fourth state. 
         [0064]    In the first, second, and third states, the resistance between the power electrode  15  and the output electrode  16  is high. In the fourth state, the resistance between the power electrode  15  and the output electrode  16  is low. 
         [0065]    As understood from the relationship between true (1) and false (0) which are input in the first to fourth states, the first input signal, which is either true or false, is input to the first input electrode  17   a . The second input signal, which is either true or false, is input to the second input electrode  17   b.    
         [0066]    (Reading from the Nonvolatile Logic Circuit  20 ) 
         [0067]    An example of the reading data from the nonvolatile logic circuit  20  is described below. 
         [0068]    While, for example, 0 volts is applied to the control electrode  12  and the input electrodes  17   a - 17   b , a potential difference is applied between the power electrode  15  and the output electrode  16  to measure the current flowing through the semiconductor film  14 . 
         [0069]    The potential difference applied between the power electrode  15  and the output electrode  16  is preferably one-fifth times or less of the voltage applied to the input electrodes  17   a - 17   b  in the writing. For example, the potential difference applied between the power electrode  15  and the output electrode  16  may be 0.1 volts. 
         [0070]    The resistance value is determined depending on the value of the current. Namely, based on the current measured, it is determined which of high-resistance state or low-resistance state the nonvolatile logic circuit  20  has. As described above, the first, second, and third states are the low-resistance states. The fourth state is the high-resistance state. 
         [0071]    The high-resistance state corresponds to the “false” of the logical addition (OR) based on the first input signal and the second input signal. The low-resistance state corresponds to the “true” of the logical addition (OR) based on the first input signal and the second input signal. In this matter, the nonvolatile logic circuit  20  serves as a nonvolatile logical addition circuit (i.e., an OR circuit). 
       EXAMPLE 
       [0072]    The following example describes the present subject matter in more detail. 
       Example 1 
       [0073]    As a substrate  11 , a silicon substrate having a surface covered by a silicon oxide film was prepared. 
         [0074]    (1) The control electrode  12  was formed on the substrate  11  in accordance with the following procedure. A Ti film with a thickness of 5 nanometers and a Pt film with a thickness of 30 nanometers were formed in this order by an electron gun deposition method. Next, a SrRuO 3  (hereinafter, referred to as “SRO”) film with a thickness of 10 nanometers was formed by a pulse laser deposition method. 
         [0075]    (2) The substrate was heated to 700 degrees Celsius, and the ferroelectric film  13  consisted of Pb(Zr,Ti)O 3  with a thickness of 450 nanometers was formed by pulse laser deposition method. 
         [0076]    (3) The substrate temperature is set at 400 degrees Celsius, and the semiconductor film  14  consisted of ZnO with thickness of 30 nanometers was formed. 
         [0077]    (4) A resist pattern was formed on the semiconductor film  14  with the use of photolithography. Subsequently, the portion of the semiconductor film  14  which the resist pattern did not cover was removed by etching with use of nitric acid. 
         [0078]    (5) Subsequently, the resist on the semiconductor film  14  was patterned with use of photolithography. A Ti film with a thickness of 5 nanometers and a Pt film with a thickness of 30 nanometers were formed by an electron gun deposition method. The resist was removed to form the power electrode  15 , the output electrode  16 , and the input electrodes  17   a - 17   b.    
         [0079]    The obtained nonvolatile logic circuit had 100-square-micrometer input electrodes and an electrode interval of 10 micrometers. The first to fourth states were written into the nonvolatile logic circuit on the basis of  FIG. 4  and  FIG. 5 . Subsequently, a voltage of 0.1 volts was applied between the power electrode  15  and the input electrode  16  to measure the current flowing between the power electrode  15  and the input electrode  16 . The resistance value of the nonvolatile logic circuit was calculated from the measured current. 
         [0080]      FIG. 7  shows resistance values calculated in the first to fourth states. As understood from  FIG. 7 , the first, second, and third states have low resistance values. On the contrary, the fourth state has a high resistance value. 
         [0081]    In the present example, the control electrode  12  having a laminate of SRO/Pt/Ti, the power electrode  15  having a laminate of Pt/Ti, the output electrode  16 , and the input electrodes  17   a - 17   b  were used. A laminate including other materials may be also used. 
         [0082]    As the material of the ferroelectric film  13 , other ferroelectric materials such as Sr(Bi,Ta)O x  or BiTiO x  may be used. As the material of the semiconductor  14 , other semiconductor materials such as GaN or InGaZnO x  may be used. 
       INDUSTRIAL APPLICABILITY 
       [0083]    The present subject matter provides a novel nonvolatile logic circuit and a method for operating the nonvolatile logic circuit. 
       REFERENCE SIGNS LIST 
       [0000]    
       
         
           
               11 : substrate 
               12 : control electrode 
               13 : ferroelectric film 
               14 : semiconductor film 
               15 : power electrode 
               16 : output electrode 
               17   a : first input electrode 
               17   b : second input electrode 
               20 : nonvolatile logic circuit 
               30   a : upward polarization in the ferroelectric film 
               30   b : downward polarization in the ferroelectric film 
               31 : low resistance portion in the semiconductor film 
               32 : high resistance portion in the semiconductor film 
               33 : input electrode in which the signal “1” is inputted 
               34 : input electrode in which the signal “0” is inputted

Technology Category: 5