Patent Document

FIELD OF THE INVENTION 
     The present invention relates to a complementary metal-oxide semiconductor (CMOS) fabrication process. More particularly, the present invention relates to a CMOS fabrication process using dual-doped gate structures. 
     BACKGROUND OF THE INVENTION 
     Ultra-large-scale integrated (ULSI) circuits often include more than one million CMOS transistors. The transistors can have gate lengths of less than 0.25 microns (e.g., deep submicrometer devices). The transistors typically have polysilicon gate conductors disposed between drains and sources. The polysilicon gate conductors are heavily doped for increased conductivity. 
     The polysilicon gate conductors can be dual-doped gate structures where the gate structures are heavily doped with N-type dopants (N+) for N-channel metal-oxide semiconductor field effect transistors (MOSFETS) and are heavily doped with P-type dopants (P+) for P-channel MOSFETS. Utilizing a dual-doped gate structure allows the active regions associated with the N-channel and P-channel MOSFETS and the polysilicon gate structures associated with the MOSFETS to be advantageously doped during the same process steps. 
     Dual-doped gate structures are susceptible to mutual diffusion. For example, the dopant in an N-type portion of the gate can diffuse into the adjacent P-type portion of the gate. Alternatively, the dopant in the P-type gate can diffuse into an adjacent N-type portion of the gate. Dopant mutual diffusion causes dopant compensation in regions where the N-type portion of the gate meets or neighbors a P-type portion of the gate. Dopant compensation causes several negative effects including severe gate depletion, reduction of effective channel width, and an increase of gate sheet resistance. Severe gate depletion, which occurs near the interface of the polysilicon and gate dielectric, degrades the transistor drive current and hence reduces circuit speed. Similarly, reduction of the effective gate width causes degradation of transistor drive current and hence reduction of circuit speed. Increased gate sheet resistance also degrades the speed of the transistor. 
     In conventional processes, mutual diffusion of the dopants in the dual-doped gate structures is suppressed by spacing N-active and P-active regions and N-well and P-well regions sufficiently far apart. However, such a solution can significantly reduce the packing density of integrated circuits and hence, the number of transistors which can be provided on an integrated circuit (IC). 
     Thus, there is a need for a dual-doped gate structure which is not susceptible to mutual diffusion and which does not require large spacings between N and P regions. Further still, there is a need for a process for making such a structure. Even further still, there is a need for a dual-doped gate structure which can be efficiently produced in a compacted structure. 
     SUMMARY OF THE INVENTION 
     The present invention relates to a method of manufacturing an integrated circuit including a plurality of first transistors and a plurality of second transistors. The first transistors have first gates doped with first type dopants. The second transistors have second gates doped with second type dopants. The method includes selectively implanting inert ions into a polysilicon layer at locations, selectively doping the polysilicon layer with the first type dopants for the first gates, and selectively doping the polysilicon layer with the second type dopants for the second gates. The locations are between the first gates and the second gates. The inert ions suppress dopant diffusion. 
     The present invention still further relates to a method of manufacturing an integrated circuit having an isolation region between a P+ gate conductor region and an N+ gate conductor region. The method includes providing a first photoresist layer over a substrate having a gate conductor layer, exposing the substrate to inert ions to provide the inert ions to the isolation region, providing a second photoresist layer exclusive of the P+ gate conductor region, exposing the substrate to P dopants to provide the P dopants to the P+ conductor region, providing a third photoresist layer exclusive of the N gate conductor region, and exposing the substrate to N dopants to provide the N dopants to the N+ conductor region. 
     The present invention still further relates to a method of manufacturing an ultra-large-scale integrated circuit having P-channel field effect transistors with heavily doped P-type polysilicon gates and N-channel field effect transistors having heavily doped N-type polysilicon gates. The method includes providing a polysilicon gate layer and implanting inert ions in the polysilicon gate layer at locations between the N-channel field effect transistors and the P-channel field effect transistors. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will hereafter be described with reference to the accompanying drawings, wherein like numerals denote like elements and: 
     FIG. 1 is a top view of a portion of semiconductor substrate having a dual-doped gate structure in accordance with a exemplary embodiment of the present invention; 
     FIG. 2 is a cross sectional view of the portion of the integrated circuit illustrated in FIG. 1 about line  2 — 2 ; 
     FIG. 3 is a cross-sectional view of the portion illustrated in FIG. 1 about line  2 — 2  showing an ion implantation step; 
     FIG. 4 is a cross-sectional view of the portion illustrated in FIG. 1 about line  2 — 2 , showing a photoresist removal step; 
     FIG. 5 is a cross-sectional view about line  2 — 2  of the portion illustrated in FIG. 1, showing a N-type dopant implant step; and 
     FIG. 6 is a cross-sectional view of the portion illustrated in FIG. 1 about line  2 — 2 , showing a P-type dopant implant step. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     With reference to FIGS. 1 and 2, a portion  10  of an integrated circuit (IC) or chip includes a transistor  12  and a transistor  14 . Portion  10  is preferably provided as part of an ultra-large-scale integrated (ULSI) circuit including at least one million transistors. Portion  10  is part of an IC manufactured as part of a semiconductor wafer. 
     Transistor  12  is preferably an N-channel metal oxide semiconductor field effect transistor (N-MOSFET), and transistor  14  is preferably a P-channel metal oxide semiconductor field effect transistor (P-MOSFET). Transistor  12  includes an active area  16  which is heavily doped with n-type dopants (N+ region), and transistor  14  includes an active area  18  which is heavily doped with p-type dopants (P+ region). Transistors  12  and  14  share a gate conductor line  20 . 
     Gate conductor line  20  has an N+ doped region  22  associated with transistor  12  and a P+ doped region  24  associated with transistor  14 . Regions  22  and  24  are separated by an inert ion implantation region  26 . Gate conductor line  20  is part of the gate structure associated with transistor  12  and the gate structure associated with transistor  14 . 
     Active regions  16  and  18  are preferably separated by a trench isolation structure  28  (FIG.  2 ). Gate conductor line  20  is provided on top of a gate dielectric layer  32  provided over active regions  16  and  18  associated with a semiconductor substrate  34 . Gate conductor line  20  is preferably a polysilicon material. Region  26  is part of line  20  which is doped or implanted with inert ions such as nitrogen or oxygen. The polysilicon film or material associated with line  20  is implanted with a sufficiently high dose (e.g., larger than 1×10 15  ion/cm 2 ) to provide a diffusion barrier for dopants in regions  22  and  24 . 
     Region  22  is doped with N-type dopants, preferably to a concentration of greater than 1×10 19  dopants per centimeter cubed. Region  24  is doped with P-type dopants, preferably to a concentration of greater than 1×10 19  dopants per centimeter cubed. N-type dopants can be phosphorus, and P-type dopants can be boron. Alternatively, regions  16 ,  18 ,  22  and  24  can be doped with arsenic, indium or boron difluoride. 
     Alternatively, region  26  can be provided over a local oxidation (LOCOS) region, substrate  34 , or other non-trench structure. Since region  26  operates as a diffusion barrier, the spacing between region  22  and  24  can be decreased, thereby increasing the packing density of portion  10  and the IC. Preferably, region  26  is doped to have a peak level of inert ions in the middle (from a vertical perspective) of gate conductor line  20 . The inert ions can be oxygen, nitrogen, xenon, or other material which has a sufficiently high activation energy so that it will not become activated during subsequent heating steps. 
     With reference to FIGS. 2-6, the fabrication of portion  10  is described below. In FIG. 3, substrate  34  is preferably silicon and includes a trench isolation structure  28 . Structure  28  can be provided by etching and deposition of silicon dioxide. A gate dielectric layer  32  is thermally grown over substrate  34 . A polysilicon layer  24 , (gate conductor line  20  in FIG.  2 ), is provided over layer  32 . Polysilicon layer  24  is preferably deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) to a thickness of between 150 and 200 nanometers (nm). 
     A photoresist layer  36  is selectively applied via a photolithographic process onto layer  24 . Photoresist layer  36  may be patterned in accordance with an inverse active region mask or layer  36  may be patterned in accordance with a trench isolation mask. Alternatively, the same mask may be utilized for the photoresist layer  36  and other layers depending upon the type of photoresist utilized. Therefore, additional masks are not necessary to implant ions into region  26 . Photoresist layer  36  includes an aperture  38  approximately 1.5 features wide or 0.2 to 0.3 nm wide. Portion  10  is exposed to inert ions via an ion implantation process. Nitrogen, oxygen or other inert ions can be implanted into region  26  through aperture  38 . Region  26  is defined by ion implantation in aperture  38 . Inert ions are implanted before layer  24  is etched in the preferred embodiment, but the ions may be provided after layer  24  is etched (not shown). 
     Generally ion implantation of region  26  involves providing a material, preferably inert ions, e.g., nitrogen, oxygen or xenon, into gate conductor line  20 . Inert ions are charged up to 10-100 kiloelectron volts (keVs) and implanted into conductor  20  at region  26 . The ions can be any type of material that has a sufficiently high activation energy so the material will not become activated during subsequent thermal annealing, i.e., the step that activates other doped regions, e.g., source and drain regions in active regions  16  and  18 . The ions may be implanted by any type of implantation device used in conventional implanting processes, e.g., Varin E220, Varin E1000, or Vista 80, manufactured by the Varin Corp., Palo Alto, Calif. or the AMT-9500 device manufactured by Applied Materials, Inc, the Genius 1520 manufactured by Genius Corp. Additional benefits of the present invention can be obtained by implanting nitrogen ions as opposed to oxygen ions because implantation of oxygen ions can encourage undesirable oxygen-enhanced diffusion in gate conductor line  20 . Heavier inert ions can be utilized when a deeper implantation is desired. 
     With reference to FIG. 4, photoresist layer  36  is removed, and portion  10  is subjected to rapid thermal annealing which allows layer  24  and region  26  to recover from defects associated with the ion implantation process. Rapid thermal annealing involves heating substrate  34  in a chamber. A pulsed heating process can be utilized. 
     With reference to FIG. 5, a photoresist layer  39  is provided partially over region  26  and exclusive of regions  16  and  22 . Portion  10  is subjected to a N-type dopant process during which regions  16  and  22  are heavily doped (e.g., more than 1×10 19  dopants per centimeter cubed) with phosphorous or other N-type dopant. Layer  39  prevents dopants from entering the location of regions  18  and  24 . 
     In FIG. 6, photoresist layer  40  is provided over regions  16  and  22  and partially over region  26  in a photolithographic process. After layer  40  is provided, portion  10  is subjected to a P-type dopant implant or doping process during which regions  18  and  24  are heavily doped with boron or other P-type dopant. With reference to FIG. 2, layer  40  is stripped to provide portion  10 . 
     Region  26  can be implanted immediately after the gate patterning process and before the gate doping process. The rapid thermal annealing step can be performed immediately after the ion implant so that the thermal budget associated with shallow source and drain junction doping is not exceeded. Sources and drains associated with transistors  12  and  14  can be provided with the doping step discussed with reference to FIGS. 5 and 6. It should be noted that portion  10  is shown throughout FIGS. 1-6 in a form which is simplified (without interconnections, source and drain regions, etc.,) to more clearly describe the present invention. 
     It is understood that while the detailed drawings, specific examples, and particular values are given to provide a preferred exemplary embodiment of the present invention, the preferred exemplary embodiment is for the purpose of illustration only. The method and apparatus of the invention is not limited to the precise details and conditions disclosed. For example, although particular polysilicon gate structures and MOS transistors are described, other types of gate structures can be utilized. Various changes may be made to the details disclosed without departing from the spirit of the invention which is defined by the following claims.

Technology Category: h