Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a programmable gain Metal-Oxide-Semiconductor (MOS) amplifier, and more particularly, to a linear-to-dB programmable gain MOS amplifier. 
         [0003]    2. Description of the Prior Art 
         [0004]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a conventional linear-to-dB Bipolar-Junction-Transistor (BJT) amplifier  100 . As shown in  FIG. 1 , the linear-to-dB BJT amplifier  100  comprises BJTs B 1 , B 2 , B 3 , and B 4 , and a resistor R B . The collector of the BJT B 1  receives an input current signal I IN , the base of the BJT B 1  receives a control current signal I CON , and the emitter of the BJT B 1  is coupled to a biasing source V SS  (for example, ground). The collector of the BJT B 2  is coupled to a biasing source V DD , the base of the BJT B 2  receives the input current signal I IN , and the emitter of the BJT B 2  receives the control current signal I CON . The collector of the BJT B 3  is coupled to the biasing source V DD , the base of the BJT B 3  receives the input current signal I IN , and the emitter of the BJT B 3  receives the control current signal I CON  through the resistor R B . The first end of the resistor R B  is coupled to the emitter of the BJT B 3 , and the second end of the resistor R B  is coupled to the base of the BJT B 4 . The base of the BJT B 4  is coupled to the second end of the resistor R B  and receives the control current signal I CON , the emitter of the BJT B 4  is coupled to the biasing source V SS , and the collector of the BJT B 4  outputs the output current signal I OUT . 
         [0005]    All the BJTs in  FIG. 1  are appropriately biased, and thus, the relation between base-emitter voltages V BE s of all the BJTs can be described as an equation as follows: 
         [0000]        V   BE1   +V   BE2   =V   BE3   +I   CON   ×R   B   +V   BE4   (1), 
         [0000]    where V BE1  represents the base-emitter voltage of the BJT 1 , V BE2  represents the base-emitter voltage of the BJT 2 , V BE3  represents the base-emitter voltage of the BJT 3 , and V BE4  represents the base-emitter voltage of the BJT 4 . Since the relation between the base-emitter voltage V BE  of a BJT and the current flowing from the BJT can be described as an equation as follows: 
         [0000]        I   E   =I   S   e   VBE/VT   (2), 
         [0000]    where e represents natural exponent, I E  represents the current flowing from the emitter of the BJT, V BE  represents the base-emitter voltage of the BJT, V T  represents the threshold voltage of the BJT, and the I S  represents the saturation current of the BJT, the further equations can be derived from the equations (1) and (2): 
         [0000]        V   T  ln( I   IN   /I   S )+ V   T  ln( I   CON   /I   S )= V   T  ln( I   CON   /I   S )+ I   CON   ×R   B   +V   T  ln( I   OUT   /I   S )  (3) 
         [0000]      ln( I   OUT   /I   IN )=(− I   CON   ×R   B )/ V   T   (4) 
         [0000]        I   OUT   =I   IN   ×e   (−ICON×RB)/VT   (5) 
         [0000]        G   100   =e   (−ICON×RB)/VT   (6) 
         [0000]        G   100 =20×(1/ln 10)×[(− I   CON   ×R   B )/ V   T ](dB)  (7) 
         [0000]    where G 100  represent the gain of the BJT amplifier  100 , and the difference between the equations (6) and (7) is that G 100  in equation (7) is expressed in dB (decibel). Therefore, according to the equation (7), the gain G 100  of the BJT amplifier  100  can be adjusted in dB units by linearly adjusting the control current signal I CON . More particularly, the gain G 100  of the BJT amplifier  100  can be adjusted in dB linearly as the control current signal I CON  is linearly adjusted, which provides great convenience. 
         [0006]    However, since the exponential characteristic does not exist between the gate-source voltage (V GS ) of a MOS and its corresponding output current I D , it is complicated to achieve adjusting the gain in dB linearly by linearly adjusting the magnitude of the controlling signal with a MOS amplifier. 
       SUMMARY OF THE INVENTION 
       [0007]    The present invention provides a programmable gain MOS amplifier for outputting an amplified signal at a first end of a load with a programmable gain. The programmable gain MOS amplifier comprises a first gain provider for providing a first predetermined gain, comprising a MOS transistor having a first predetermined aspect ratio corresponding to the first predetermined gain, the MOS transistor comprising a control end coupled to an input end of the programmable gain MOS amplifier for receiving an input signal; a biasing end coupled to a biasing source; and an output end; and a first gain tuner for adjusting the first predetermined gain, comprising a gain enabling module, comprising a MOS transistor, comprising a control end for receiving a first controlling signal; a first end coupled to the first end of the load; and a second end coupled to the output end of the MOS transistor of the first gain provider; and a gain decreasing module, comprising a first MOS transistor, comprising a control end for receiving a second controlling signal; a first end coupled to a second end of the load; and a second end coupled to the output end of the MOS transistor of the first gain provider; wherein when the first controlling signal turns on the MOS transistor of the gain enabling module of the first gain tuner, the programmable gain equals the G1; when the first controlling signal turns on the MOS transistor of the gain enabling module of the first gain tuner and the second controlling signal turns on the first MOS transistor of the gain decreasing module of the first gain tuner, the programmable gain equals [M1/(M1+M2)]×G1; M1 represents an aspect ratio of the MOS transistor of the gain enabling module of the first gain tuner, M2 represents an aspect ratio of the first MOS transistor of the gain decreasing module of the first gain tuner, and G1 represents the first predetermined gain. 
         [0008]    The present invention further provides a programmable gain MOS amplifier for outputting an amplified signal at a first end of a load with a programmable gain according to a gain level data. The programmable gain MOS amplifier comprises a decoder for decoding the gain level data to a plurality of controlling signals; a plurality of gain providers, each gain provider providing a predetermined gain, each gain provider comprising a MOS transistor having a predetermined aspect ratio corresponding to a corresponding predetermined gain, the MOS transistor comprising a control end coupled to an input end of the programmable gain MOS amplifier for receiving an input signal; a biasing end coupled to a biasing source; and an output end; and a plurality of gain tuners, each gain tuner adjusting a predetermined gain from corresponding one of the plurality of the gain providers, each gain tuner comprising a gain enabling module, comprising a MOS transistor, comprising a control end, coupled to the decoder, for receiving a corresponding controlling signal; a first end coupled to the first end of the load; and a second end coupled to the output end of the MOS transistor of the corresponding gain provider; wherein a predetermined gain provided from one of the plurality of the gain providers is added to the programmable gain of the MOS amplifier when the MOS transistor of the gain enabling module of the corresponding gain tuner is turned on by the corresponding controlling signal decoded from the gain level data. 
         [0009]    The present invention further provides a programmable gain MOS amplifier for outputting an amplified signal at a first end of a load with a programmable gain according to a gain level data. The programmable gain MOS amplifier comprises a decoder for decoding the gain level data to a plurality of controlling signals; a first gain provider for providing a first predetermined gain, comprising a first MOS transistor having a first predetermined aspect ratio corresponding to the first predetermined gain, the first MOS transistor comprising a control end coupled to an input end of the programmable gain MOS amplifier for receiving an input signal; a biasing end coupled to a biasing source; and an output end; and a first gain tuner for adjusting the first predetermined gain, comprising a gain enabling module, comprising a second MOS transistor, comprising a control end coupled to the decoder for receiving a corresponding controlling signal; a first end coupled to the first end of the load; and a second end coupled to the output end of the second MOS transistor of the first gain provider; and a gain decreasing module, comprising M third MOS transistors, each third MOS transistor comprising a control end coupled to the decoder for receiving a corresponding controlling signal; a first end coupled to a second end of the load; and a second end coupled to the output end of the corresponding third MOS transistor of the first gain provider; a second gain provider for providing a second predetermined gain, comprising a fourth MOS transistor having a second predetermined aspect ratio corresponding to the second predetermined gain, the fourth MOS transistor comprising a control end coupled to the input end of the programmable gain MOS amplifier for receiving the input signal; a biasing end coupled to the biasing source; and an output end; and a second gain tuner for adjusting the second predetermined gain, comprising a gain enabling module, comprising a fifth MOS transistor, comprising a control end coupled to the decoder for receiving a corresponding controlling signal; a first end coupled to the first end of the load; and a second end coupled to the output end of the fifth MOS transistor of the second gain provider; wherein the second predetermined gain is higher than the first predetermined gain; wherein the programmable gain is obtained from the first predetermined gain adjusted by the first gain tuner and the second predetermined gain adjusted by the second gain tuner. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a diagram illustrating a conventional linear-to-dB BJT amplifier. 
           [0012]      FIG. 2  is a diagram illustrating a MOS amplifier according to a first embodiment of the present invention. 
           [0013]      FIG. 3  is a diagram illustrating a realization of the linear-to-dB MOS amplifier according to the first embodiment of the present invention. 
           [0014]      FIG. 4  is a diagram illustrating a MOS amplifier according to a second embodiment of the present invention. 
           [0015]      FIG. 5  is a diagram illustrating a MOS amplifier according to a third embodiment of the present invention. 
           [0016]      FIG. 6  is a diagram illustrating the magnitude, and the magnitude in dB, corresponding to the gain level of the MOS amplifier according to the third embodiment of the present invention. 
           [0017]      FIG. 7  is a diagram illustrating the controlling signals of each gain level of the MOS amplifier according to the third embodiment of the present invention. 
           [0018]      FIG. 8  is a diagram illustrating a decoder as an auxiliary component for the MOS amplifier according to the third embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating a MOS amplifier  200  according to a first embodiment of the present invention. As shown in  FIG. 2 , the MOS amplifier  200  comprises N gain providers GP 1 ˜GP N , and N gain tuners GT 1 ˜GT N . 
         [0020]    Each gain tuner further comprises a gain enabling module GEM and a gain decreasing module GDM. For example, the gain tuner GT 1  comprises the gain enabling module GEM 1  and the gain decreasing module GDM 1 . Each gain enabling module GEM is realized with a MOS transistor. For example, the gain enabling module GEM 1  is realized with the MOS transistor Q 11  having an aspect ratio M 11 . Each gain decreasing module GDM is realized with three MOS transistors. For example, the gain decreasing module GDM 1  is realized with the MOS transistors Q 12 , Q 13 , and Q 14  having aspect ratio M 12 , M 13 , and M 14 , respectively. Each gain tuner corresponds to a gain provider. For example, the gain tuner GT 1  corresponds to the gain provider GP 1 . Additionally, the sum of the aspect ratios of the gain decreasing module equals the aspect ratio of the corresponding gain enabling module. For example, in the gain tuner GT 1 , the sum of the aspect ratios (M 12 +M 13 +M 14 ) for the gain decreasing module GDM 1  equals the aspect ratio (M 11 ) for the gain enabling module GEM 1 . However, the aspect ratios of the gain enabling module and the gain decreasing module can be set depending on design, which means the sum of the aspect ratios of one decreasing module does not have to be the same as the aspect ratio of the corresponding gain enabling module, and furthermore, the number of the MOS transistors employed by each gain decreasing module can be set as desired and is not limited to be the same as others. The present embodiment is only illustrated as an exemplary embodiment for easier understanding. 
         [0021]    The gain provider is realized with a MOS transistor. For example, the gain provider GP 1  is realized with the MOS transistor Q 1  having an aspect ratio M 1 . Therefore, as shown in  FIG. 2 , the control end (gate) of the MOS transistor Q 1  is coupled to an input end of the MOS amplifier  200  for receiving an input signal V IN , the biasing end (source) of the MOS transistor Q 1  is coupled to a biasing source V SS , and the output end of the MOS transistor Q 1  is coupled to the corresponding gain tuner GT 1 . 
         [0022]    In the gain enabling module GEM 1 , the control end (gate) of the MOS transistor Q 11  receives a controlling signal S 11 , the first end (drain) of the MOS transistor Q 11  is coupled to a first end of a load, and the second end (source) of the MOS transistor Q 11  is coupled to the output end of the MOS transistor Q 1 . In the gain decreasing module GDM 1 , the control end (gate) of the MOS transistor Q 12  receives a controlling signal S 12 , the first end (drain) of the MOS transistor Q 12  is coupled to a second end of the load, and the second end (source) of the MOS transistor Q 12  is coupled to the output end of the MOS transistor Q 1 ; the control end (gate) of the MOS transistor Q 13  receives a controlling signal S 13 , the first end (drain) of the MOS transistor Q 13  is coupled to the second end of the load, and the second end (source) of the MOS transistor Q 13  is coupled to the output end of the MOS transistor Q 1 ; the control end (gate) of the MOS transistor Q 14  receives a controlling signal S 14 , the first end (drain) of the MOS transistor Q 14  is coupled to a second end of the load, and the second end (source) of the MOS transistor Q 14  is coupled to the output end of the MOS transistor Q 1 . 
         [0023]    The rest gain providers, gain tuners, gain enabling modules, and gain decreasing modules have similar structure and connections as described above and therefore the related description is omitted. The first end of the load is set as the output end of the MOS amplifier  200  for outputting an output signal V OUT , and the second end of the load is coupled to a biasing source V DD . Of course, the output signal V OUT  is amplified according to the programmable gain of the MOS amplifier  200  from the input signal V IN . Additionally, the MOS transistors of the gain providers are utilized as amplifiers, and the MOS transistors of the gain enabling modules and the gain decreasing modules are only utilized as switches merely. 
         [0024]    Each gain provider provides a gain of different value as desired. However, same value of the gains of some gain providers can be designed as well. Under the condition that a MOS transistor is appropriately biased, when the MOS transistor is utilized as a common source amplifier, the gain of the amplifier is proportional to the aspect ratio M of the MOS transistor. Therefore, the MOS transistors Q 1 ˜Q N  of the gain providers GP 1 ˜GP N  are designed with different aspect ratios M 1 ˜M N  and the corresponding gains G 1 ˜G N  are obtained. Assuming the gain G 1  is G INI , and thus the gain G 2  is (M 2 /M 1 )G INI , the gain G 3  is (M 3 /M 1 )G INI , and so on. 
         [0025]    When a gain enabling module is turned on (by the corresponding controlling signal), the gain of the corresponding gain provider is added to the total gain of the MOS amplifier  200 . For example, when the gain enabling module GEM 1  is enabled, which means that the MOS transistor Q 11  is turned on by the controlling signal S 11 , the total gain of the MOS amplifier  200  is added with the gain G 1 , which is G INI ; when the gain enabling modules GEM 1  and GEM 2  is enabled, the total gain of the MOS amplifier  200  is added with the gains G 1  and G 2 , which equals to [(M 2 +M 1 )/M 1 ]G INI ; when all the gain enabling modules GEM 1 ˜GEM N  are enabled, the total gain of the MOS amplifier  200  is [(M N +M (N−1) + . . . +M 3 +M 2 +M 1 )/M 1 ]G INI . 
         [0026]    When a gain decreasing module is turned on while the corresponding gain enabling module is turned on, the gain of the corresponding gain provider is decreased, and the decreasing degree can be set by controlling the gain decreasing module. In other words, when a gain enabling module is turned on, the current sunk by the MOS transistor of the corresponding gain provider directly flows from the load to the output end of the MOS transistor, and the gain of the MOS transistor of the corresponding gain provider is completely added to the total gain of the MOS amplifier  200 ; when a gain decreasing module is turned on while the corresponding gain enabling module is turned on, the current sunk by the MOS transistor of the corresponding gain provider partially flows from the load and partially flows from the biasing source V DD  through the MOS transistors turned on in the gain decreasing module, the gain of the MOS transistor of the corresponding gain provider is partially added to the total gain of the MOS amplifier  200 . For example, when the MOS transistor Q 11  is turned on, the gain of the MOS amplifier  200  is G 1 ; when the MOS transistor Q 11  and Q 12  are turned on, the gain of the MOS amplifier  200  is [M 11 /(M 11 +M 12 )]×G 1 ; when the MOS transistor Q 11 , Q 12 , and Q 13  are turned on, the gain of the MOS amplifier  200  is [M 11 /(M 11 +M 12 +M 13 )]×G 1 ; when the MOS transistor Q 11 , Q 12 , Q 13 , and Q 14  are turned on, the gain of the MOS amplifier  200  is [M 11 /(M 11 +M 12 +M 13 +M 14 )]×G 1 . 
         [0027]    Therefore, the total gain of the MOS amplifier  200  can be adjusted by controlling the on/off states of the MOS transistors of the gain enabling modules and the gain decreasing modules of the MOS amplifier  200 . 
         [0028]    Please refer to  FIG. 3 .  FIG. 3  is a diagram illustrating a realization of the linear-to-dB MOS amplifier  300  according to the first embodiment of the present invention. As shown in  FIG. 3 , the basic structure of the MOS amplifier  300  is similar to the MOS amplifier  200  and the related description is omitted. The aspect ratios of the MOS transistors Q 1 ˜Q N  are designed to be M A , 2M A , 4M A , 8M A , . . . , 2 (N−1) M A , respectively, and the gain of the MOS transistor Q 1  is assumed to be G INI . In each gain tuner, the aspect ratio of the MOS transistor of the gain enabling module is designed to be 8 M B , the aspect ratios of the three MOS transistors of the gain decreasing module are designed to be M B , 2M B , and 5M B , respectively. 
         [0029]    When the gain enabling module GEM 1  is turned on, the gain provided is G INI ; when the gain enabling module GEM 2  is turned on, the gain provided is 2G INI ; when the gain enabling module GEM 3  is turned on, the gain provided is 4G INI ; . . . ; when the gain enabling module GEM N  is turned on, the gain provided is 2 (N−1) G INI . In this way, the gain generated from one gain enabling module is double than the gain generated from the previous gain enabling module, and thus the gain difference between each adjacent gain enabling module equals to be 6 dB (20 log 2=20×(0.3010)≈6). Consequently, the gain of the MOS amplifier  300  increases with the interval of 6 dB by only controlling the on/off states of the MOS transistors Q 11 ˜Q N1  of the gain enabling modules GEM 1 ˜GEM N . 
         [0030]    The design of the aspect ratios of the MOS transistor of the gain enabling module and the MOS transistors of the gain decreasing module in one gain tuner in the MOS amplifier  300  allows the gain of the MOS amplifier  300  to adjusted with 1 dB per gain step in the 6 dB gap. For example, when the transistors Q 11 ˜Q 14  are turned on, the gain of the MOS amplifier  300  is (0.5)G INI  (−6 dB×G INI ); when the transistors Q 11 , Q 12 , and Q 14  are turned on, the gain of the MOS amplifier  300  is (0.57)G INI  (−5 dB×G INI ); when the transistors Q 11  and Q 14  are turned on, the gain of the MOS amplifier  300  is (0.61)G INI  (−4 dB×G INI ); when the transistors Q 11 , Q 12  and Q 13  are turned on, the gain of the MOS amplifier  300  is (0.72)G INI  (−3 dB×G INI ); when the transistors Q 11  and Q 13  are turned on, the gain of the MOS amplifier  300  is (0.8)G INI  (−2 dB×G INI ); when the transistors Q 11  and Q 12  are turned on, the gain of the MOS amplifier  300  is (0.88)G INI  (−1 dB×G INI ); when only the transistor Q 11  is turned on, the gain of the MOS amplifier  300  is (1)G INI  (0 dB×G INI ). 
         [0031]    Therefore, the gain of the linear-to-dB MOS amplifier  300  can be adjusted with 1 dB per gain step and adjusted to any value as desired by turning on the MOS transistors of the gain enabling modules and the gain decreasing modules of the gain tuners respectively. 
         [0032]    Please refer to  FIG. 4 .  FIG. 4  is a diagram illustrating a MOS amplifier  400  according to a second embodiment of the present invention. As shown in  FIG. 4 , the MOS amplifier  400  comprises two gain providers GP 1  and GP 2 , two gain tuners GT 1  and GT 2 , N gain providers GP T1 ˜GP TN , and N gain tuners GT TI ˜GT TN . 
         [0033]    The functional description for the gain providers, the gain tuners in  FIG. 4  is similar to those components in  FIG. 2  and is omitted. However, structurally, MOS amplifier  400  is slightly changed according to the MOS amplifier  200 . As shown in  FIG. 4 , only two gain providers GP 1  and GP 2  and their corresponding gain tuners GT 1  and GT 2  are utilized for low gain adjustment range, but N gain provider GP T1 ˜GP TN  and their corresponding gain tuners GT T1 ˜GT TN  are utilized for high gain adjustment range. More particularly, the aspect ratios of the MOS transistors Q 1  and Q 2  respectively of the gain providers GP 1  and GP 2  can be designed to be M 1  and 2M 1  and the aspect ratio of the MOS transistor Q T1  of the gain provider GP T1  can be designed to be 4M 1 , the aspect ratio of the MOS transistor Q T2  of the gain provider GP T2  can be designed to be 8M 1 , and in such manner, the aspect ratio of the MOS transistor Q TN  can be designed to be 2 (N+1) M 1 . Therefore, the gain providers GP 1  and GP 2  provide G INI , the gain provider GP T1  provides 4G INI , the gain provider GP T2  provides 8G INI , . . . , and the gain provider GP TN  provide 2 (N+1) G INI . Additionally, the number of the gain providers GP T1 ˜GP TN  depends on the total gain adjustment range as desired. That is, if the gain adjustment range goes higher, the number N goes higher as well, and vice versa. 
         [0034]    It is noticeable that as for each of the gain tuners GT T1 ˜GT TN  (for the high gain adjustment), the corresponding gain enabling module and the corresponding gain decreasing module employ only one MOS transistor respectively and both of the employed MOS transistors have the same aspect ratio as that of the MOS transistor of the corresponding gain provider. Therefore, when the MOS transistor of the gain enabling module for the high gain adjustment is turned on and the MOS transistor of the gain decreasing module for the high gain adjustment is turned off, the gain of the corresponding gain provider for the high gain adjustment is added to the MOS amplifier  400 , which means the branch for that one particular high gain adjustment is turned on. On the other hand, when the MOS transistor of the gain enabling module for the high gain adjustment is turned off and the MOS transistor of the gain decreasing module for the high gain adjustment is turned on, the gain of the corresponding gain provider for the high gain adjustment is not added to the MOS amplifier  400 , which means the branch for that one particular high gain adjustment is turned off. The above-mentioned mechanism is designed for keeping the input impedance (from where V IN  is inputted) the same without the relations of the on/off states of MOS transistors of the gain enabling modules and the gain decreasing modules for the high gain adjustment. However, if the input impedance variation is not important in the design, the gain decreasing modules for the high gain adjustment can be removed from the design. 
         [0035]    The design of the MOS amplifier  400  saves MOS transistors for the gain tuners because for the high gain adjustment range, only two MOS transistors are used for each gain tuners, and still provides the same advantage as the MOS amplifier  200 . 
         [0036]    Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating a MOS amplifier  500  according to a third embodiment of the present invention. The MOS amplifier  500  is disclosed as a design example for 36 dB gain adjustment range. As shown in  FIG. 5 , the MOS amplifier  500  comprises the gain providers GP 5 , GP 6 , GP 7 , GP 8 , GP 9 , and GP 10 , and the gain tuners GT 5 , GT 6 , GT 7 , GT 8 , GT 9 , and GT 10 . It is noticeable that each of the gain tuners GT 5 , GT 8 , GT 9 , and GT 10  only comprises the gain enabling module, and the corresponding gain decreasing module is saved. It is noticeable that the embodiment as shown in  FIG. 5  is designed as the above-mentioned mechanism that when the input impedance variation is not important in the design, the gain decreasing modules for the high gain adjustment can be removed. 
         [0037]    The aspect ratios of the MOS transistors Q 5 , Q 6 , Q 7 , Q 8 , Q 9 , and Q 10  of the gain providers GT 5 , GT 6 , GT 7 , GT 8 , GT 9 , and GT 10  are designed to be M 5 , M 5 , 2M 5 , 4M 5 , 8M 5 , and 16M 5 , respectively. In the gain tuner GT 6 , the aspect ratio of the MOS transistor Q 61  of the gain enabling module GEM 6  is designed to be 8M 6 , the aspect ratios of the MOS transistors Q 62 , Q 63 , Q 64  of the gain decreasing module GDM 6  are respectively designed to be M 6 , 2M 6 , 5M 6 . In the gain tuner GT 7 , the aspect ratio of the MOS transistor Q 71  of the gain enabling module GEM 7  is designed to be 16M 7 , the aspect ratios of the MOS transistors Q 72 , Q 73 , Q 74  of the gain decreasing module GDM 7  are respectively designed to be 2M 7 , 4M 7 , 7M 7 . 
         [0038]    The MOS transistors Q 51 , Q 61 , Q 62 , Q 63 , Q 64 , Q 71 , Q 72 , Q 73 , Q 74 , Q 81 , Q 91 , and Q 101  are turned on/off respectively according to the controlling signals S 0 , S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 , S 9 , S 10 , and S 11 . 
         [0039]    Please refer to  FIG. 6  and  FIG. 7 .  FIG. 6  is a diagram illustrating the magnitude, and the magnitude in dB, corresponding to the gain level of the MOS amplifier  500 .  FIG. 7  is a diagram illustrating the controlling signals of each gain level of the MOS amplifier  500 . Since the gain range of the MOS amplifier  500  is 36 dB and the 36 dB gain range is divided into 36 gain levels, increasing one gain level is adding 1 dB of the gain of the MOS amplifier  500 . As shown in  FIG. 6 , each gain level corresponds to a gain magnitude and the gain magnitude in dB, and the gain level can be the combination of other gain levels. For example, the gain level “15” corresponds to 2.488889 and 7.92011 dB (≈8 dB), and the gain level “15” is generated by combining the gain level “11” and the gain level “6”. The gain level “37” corresponds to 31.6 and 29.99374 dB (≈30 dB), and the gain level “37” is generated by combining the gain levels “0”, “3”, “13”, “19”, “25”, and “31”. As shown in  FIG. 7 , to achieve each gain level, the controlling signals S 0 ˜S 11  are accordingly set. For example, to achieve the gain level “15”, the controlling signals S 0 ˜S 11 , are set as [011001010000]. To achieve the gain level “37”, the controlling signals S 0 ˜S 11  are set as [110011000111]. 
         [0040]    Please refer to  FIG. 8 .  FIG. 8  is a diagram illustrating a decoder  800  as an auxiliary component for the MOS amplifier  500 . For controlling convenience, the decoder  800  is disposed between the gain level data D 0 ˜D 5  and the controlling signals S 0 ˜S 11 . For example, to achieve the gain level “15”, the gain level data D 0 ˜D 5  are [001111], and the controlling signals S 0 ˜S 11  are [011001010000] decoded by the decoder  800  according to the gain level data [0011111]. To achieve the gain level “37”, the gain level data D 0 ˜D 5  are [100101], and the controlling signals S 0 ˜S 11  are [110011000111] decoded by the decoder  800  according to the gain level data [100101]. 
         [0041]    To sum up, as those disclosed above, the programmable gain MOS amplifier of the present invention provides adjusting gain in dB domain linearly by linearly adjusting the controlling data, and for the high gain adjustment, the programmable gain MOS amplifier of the present invention provides an easier mechanism to save required components, which increases great convenience. 
         [0042]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Technology Category: 5