Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device including a semiconductor element with a protection circuit and its testing method. 
     2. Description of Related Art 
     In a prior art semiconductor device including a semiconductor element so-called a gate-insulating-type transistor such as a power MOS transistor and an insulated gate bipolar transistor (IGBT), if an excessive voltage is applied to the gate of the gate-insulating-type transistor, the gate insulating layer thereof would be electrostatically destroyed. Therefore, in order to prevent the gate insulating layer from being electrostatically destroyed, a protection circuit is connected between the gate and source of the gate-insulating-type transistor to clamp the difference in voltage thereof. 
     The protection circuit is constructed by one or more diodes, and has an anode connected to an anode pad and a cathode connected to a source pad of the gate-insulating-type transistor. The anode pad is connected by a bonding wire to a gate pad of the gate-insulating-type transistor. On the other hand, in order to remove semiconductor devices with low gate breakdown voltages, a gate breakdown voltage test operation is carried out in a wafer state before bonding the bonding wire. In this case, a predetermined test voltage is applied to the gate of a gate-insulating-type transistor to determine whether or not the gate-insulating-type transistor is normally operated. 
     The above-described prior art semiconductor device is disclosed in Japanese Unexamined Patent Publication (Kokai) No. P2005-175054 A. This will be explained later in detail. 
     However, the inventor has recognized that, since the anode pad whose size is very large, is required for the protection circuit, the above-described prior art semiconductor device becomes large in size, which would increase the manufacturing cost. 
     SUMMARY 
     The present invention seeks to solve the above-described problem. 
     In one embodiment, in a semiconductor device including a semiconductor element to be protected having first and second electrodes, and a protection circuit coupled between the first and second electrodes, a switch circuit is inserted between the first and second electrodes in series to the protection circuit. The switch circuit is turned ON by such a voltage that turns ON the semiconductor element. 
     Thus, a pad specialized for the protection circuit would be unnecessary. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments as compared with the prior art, taken in conjunction with the accompanying drawings, wherein: 
         FIG. 1  is a circuit diagram illustrating a prior art semiconductor device; 
         FIG. 2  is a detailed circuit diagram of the semiconductor device of  FIG. 1  in a gate breakdown voltage test mode; 
         FIG. 3  is a circuit diagram illustrating a first embodiment of the semiconductor device according to the present invention; 
         FIG. 4  is a detailed circuit diagram of the semiconductor device of  FIG. 3  in a gate breakdown voltage test mode; 
         FIG. 5  is a circuit diagram illustrating a modification of the semiconductor device of  FIG. 3 ; 
         FIG. 6  is a detailed circuit diagram of the semiconductor device of  FIG. 5  in a gate breakdown voltage test mode; 
         FIG. 7  is a circuit diagram illustrating a second embodiment of the semiconductor device according to the present invention; 
         FIG. 8  is a detailed circuit diagram of the semiconductor device of  FIG. 7  in a gate breakdown voltage test mode; 
         FIG. 9  is a circuit diagram illustrating a modification of the semiconductor device of  FIG. 7 ; 
         FIG. 10  is a detailed circuit diagram of the semiconductor device of  FIG. 9  in a gate breakdown voltage test mode; 
         FIGS. 11A and 11B  are circuit diagrams illustrating other modifications of the semiconductor devices of  FIGS. 3 and 7 , respectively; 
         FIGS. 12A and 12B  are circuit diagrams further illustrating other modifications of the semiconductor devices of  FIGS. 3 and 7 , respectively; 
         FIGS. 13A and 13B  are circuit diagrams further illustrating still other modifications of the semiconductor devices of  FIGS. 3 and 7 , respectively; and 
         FIGS. 14A and 14B  are circuit diagrams illustrating third and fourth embodiments of the semiconductor device according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Before describing the present invention, the prior art will be explained in detail with reference to  FIGS. 1 and 2  in order to facilitate the understanding of the present invention (see: FIGS. 1 and 2 of Japanese Unexamined Patent Publication (Kokai) No. P2005-175054 A). 
     In  FIG. 1 , a semiconductor device (chip)  1  is constructed by an n-channel MOS transistor  11   n  and a protection circuit  12  formed by one diode or two or more serially-connected diodes to clamp the difference in voltage between a gate and source of the n-channel MOS transistor  11   n . For example, if the number of diodes in the protection circuit  12  is four, a clamp voltage is four times the forward voltage of one diode. 
     The n-channel MOS transistor  11   n  has a drain connected to a drain pad P D . Also, the gate is connected to a gate pad P G , and the source is connected to a source pad P S . 
     The protection circuit  12  has an anode connected to an anode pad P A  and a cathode connected to the source pad P S . 
     The semiconductor device  1  is mounted on a board (motherboard or interposer) on which external terminals T 1 , T 2  and T 3  are provided. 
     The anode pad P A  is connected by a bonding wire W 0  to the gate pad P G . Also, the drain pad P D , the gate pad P G  and the source pad P S  are connected by bonding wires W 1 , W 2  and W 3  to the external terminals T 1 , T 2  and T 3 , respectively. 
     Thus, the protection circuit  12  is connected between the gate and source of the n-channel MOS transistor  11   n . Therefore, even when an excessive voltage higher than the clamp voltage of the protection circuit  12  is applied between the gate pad P G  and the source pad P S , the protection circuit  12  is in a conductive state, thus preventing the gate insulating layer of the n-channel MOS transistor  11   n  from being electrostatically destroyed. 
     A gate breakdown voltage test operation is performed upon the semiconductor device  1  of  FIG. 1  which is in a wafer state as illustrated in  FIG. 2 . In  FIG. 2 , the bonding wires W 0 , W 1 , W 2  and W 3  of  FIG. 1  are not provided, and test probes TP G  and TP S  are in contact with the gate pad P G  and the source pad P S , respectively. Thus, since the protection circuit  12  is not connected to the gate of the n-channel MOS transistor  11   n , the protection circuit  12  is invalidated. In this state, a test voltage can be applied between the probes TP G  and TP S  without consideration of the clamp voltage of the protection circuit  12 . 
     After the gate breakdown voltage test operation has been completed, the semiconductor device  1  of  FIG. 2  is diced and mounted on a board, and then, a bonding operation is performed thereupon to obtain the semiconductor device  1  of  FIG. 1 . 
     In the semiconductor device  1  of  FIG. 1 , however, since the anode pad P A  whose size is about 100 μm×100 μm, for example, is required, the semiconductor device  1  of  FIG. 1  becomes large in size, which would increase the manufacturing cost. 
     In  FIG. 3 , which illustrates a first embodiment of the semiconductor device according to the present invention, the anode pad P A  and the bonding wire W 0  of  FIG. 1  are replaced by a switch circuit  13 , to form a semiconductor device  2 . That is, the switch circuit  13  is connected between the gate of the n-channel MOS transistor  11   n  and the anode of the protection circuit  12 . 
     The switch circuit  13  is constructed by a p-channel MOS transistor  131   p  connected between the gate of the n-channel MOS transistor  11   n  and the anode of the protection circuit  12 , a fuse  132  connected between the source and gate of the p-channel MOS transistor  131   p , and a resistor  133  serving as a pull-down resistor connected between the gate of the p-channel MOS transistor  131   p  and the source of the n-channel MOS transistor  11   n  (the cathode of the protection circuit  12 ). 
     In  FIG. 3 , the fuse  132  is melted. Note that the fuse  132  is a laser-melted fuse which does not require a melting current (voltage) pad. 
     Thus, even when an excessive voltage higher than the clamp voltage of the protection circuit  12  is applied between the gate pad P G  and the source pad P S , the source-to-gate voltage of the p-channel MOS transistor  131   p  is increased to turn ON the p-channel MOS transistor  131   p , so that the protection circuit  12  is in a conductive state, thus preventing the gate insulating layer of the n-channel MOS transistor  11   n  from being electrostatically destroyed. 
     A gate breakdown voltage test operation is performed upon the semiconductor device  2  of  FIG. 3  which is in a wafer state as illustrated in  FIG. 4 . In  FIG. 4 , the bonding wires W 1 , W 2  and W 3  of  FIG. 3  is not provided and the fuse  132  is not melted. Also, test probes TP G  and TP S  are in contact with the gate pad P G  and the source pad P S , respectively. Thus, since the p-channel MOS transistor  131   p  is turned OFF, the protection circuit  12  is invalidated. In this state, a test voltage can be applied between the probes TP G  and TP S  without consideration of the clamp voltage of the protection circuit  12 . 
     After the gate breakdown voltage test operation has been completed, the fuse  132  is melted by laser trimming. The semiconductor device  2  of  FIG. 4  is diced and mounted on a board, and then, a bonding operation is performed thereupon to obtain the semiconductor device  2  of  FIG. 3 . 
     In the semiconductor device  2  of  FIG. 3 , since the anode pad P A  of  FIG. 1  is not required, the semiconductor device  2  of  FIG. 3  becomes small in size, which would decrease the manufacturing cost. 
     In  FIG. 5 , which illustrates a modification of the semiconductor device  2  of  FIG. 3 , a fuse  134  is added to the switch circuit  13  of  FIG. 3 . The fuse  134  is connected in parallel with the protection circuit  12 . 
     Even in  FIG. 5 , the fuse  134  is melted. Note that the fuse  134  is also a laser-melted fuse which does not require a melting current (voltage) pad. 
     A gate breakdown voltage test operation is performed upon the semiconductor device  2  of  FIG. 5  which is in a wafer state as illustrated in  FIG. 6 . In  FIG. 6 , the bonding wires W 1 , W 2  and W 3  of  FIG. 5  are not provided and the fuses  132  and  134  are not melted. Also, test probes TP G  and TP S  are in contact with the gate pad P G  and the source pad P P S , respectively. Thus, since the p-channel MOS transistor  131   p  is turned OFF, the protection circuit  12  is invalidated. In this state, a test voltage is applied so that a leakage current I LK  may flow through the p-channel MOS transistor  131   p  as indicated in  FIG. 6 . Even in this case, the leakage current I LK  flows through the fuse  134 , not the protection circuit  12 . As a result, such a test voltage can be applied between the probes TP G  and TP S  without consideration of the clamp voltage of the protection circuit  12 . 
     After the gate breakdown voltage test operation, the fuse  134  together with the fuse  132  is trimmed by laser. 
     In  FIG. 7 , which illustrates a second embodiment of the semiconductor device according to the present invention, the anode of the protection circuit  12  of  FIG. 3  is connected to the gate of the n-channel MOS transistor  11   n , and the switch circuit  13  of  FIG. 3  is replaced by a switch circuit  14 , to form a semiconductor device  3 . That is, the switch circuit  14  is connected between the cathode of the protection circuit  12  and the source of the n-channel MOS transistor  11   n.    
     The switch circuit  14  is constructed by a p-channel MOS transistor  141   p  connected between the cathode of the protection circuit  12  and the source of the n-channel MOS transistor  11   n , a fuse  142  connected between the anode of the protection circuit  12  and the gate of the p-channel MOS transistor  141   p , and a resistor  143  serving as a pull-down resistor connected between the gate and drain of the p-channel MOS transistor  141   p.    
     In  FIG. 7 , the fuse  142  is melted. Note that the fuse  142  is a laser-melted fuse which does not require a melting current (voltage) pad. 
     Thus, even when an excessive voltage higher than the clamp voltage of the protection circuit  12  is applied between the gate pad P G  and the source pad P S , the source-to-gate voltage of the p-channel MOS transistor  141   p  is increased to turn ON the p-channel MOS transistor  141   p , so that the protection circuit  12  is in a conductive state, thus preventing the gate insulating layer of the n-channel MOS transistor  11   n  from being electrostatically destroyed. 
     A gate breakdown voltage test operation is performed upon the semiconductor device  3  of  FIG. 7  which is in a wafer state as illustrated in  FIG. 8 . In  FIG. 8 , the bonding wires W 1 , W 2  and W 3  of  FIG. 7  are not provided and the fuse  142  is not melted. Also, test probes TP G  and TP S  are in contact with the gate pad P G  and the source pad P S , respectively. Thus, since the p-channel MOS transistor  141   p  is turned OFF, the protection circuit  12  is invalidated. In this state, a test voltage can be applied between the probes TP G  and TP S  without consideration of the clamp voltage of the protection circuit  12 . 
     After the gate breakdown voltage test operation has been completed, the fuse  142  is melted by laser trimming. The semiconductor device  3  of  FIG. 8  is diced and mounted on a board, and then, a bonding operation is performed thereupon to obtain the semiconductor device  3  of  FIG. 7 . 
     In the semiconductor device  3  of  FIG. 7 , since the anode pad P A  of  FIG. 1  is not required, the semiconductor device  3  of  FIG. 7  becomes small in size, which would decrease the manufacturing cost. 
     In  FIG. 9 , which illustrates a modification of the semiconductor device  3  of  FIG. 7 , a fuse  144  is added to the switch circuit  14  of  FIG. 7 . The fuse  144  is connected in parallel with the protection circuit  12 . 
     Even in  FIG. 9 , the fuse  144  is melted. Note that the fuse  144  is also a laser-melted fuse which does not require a melting current (voltage) pad. 
     A gate breakdown voltage test operation is performed upon the semiconductor device  3  of  FIG. 9  which is in a wafer state as illustrated in  FIG. 10 . In  FIG. 10 , the bonding wires W 1 , W 2  and W 3  of  FIG. 9  are not provided and the fuses  142  and  144  are not melted. Also, test probes TP G  and TP S  are in contact with the gate pad P G  and the source pad P S , respectively. Thus, since the p-channel MOS transistor  141   p  is turned OFF, the protection circuit  12  is invalidated. In this state, a test voltage is applied so that a leakage current I LK  may flow through the p-channel MOS transistor  141   p  as indicated in  FIG. 10 . Even in this case, the leakage current I LK  flows through the fuse  144 , not the protection circuit  12 . As a result, such a test voltage can be applied between the probes TP G  and TP S  without consideration of the clamp voltage of the protection circuit  12 . 
     After the gate breakdown voltage test operation, the fuse  144  together with the fuse  142  is trimmed by laser. 
     In the semiconductor devices  2  and  3  of  FIGS. 3 to 10 , the size of the switch circuits  13  and  14  is smaller than that of the anode pad P A  of  FIG. 1 . For example, the size of the p-channel MOS transistor  131   p  ( 141   p ) is about 5 μm×50 μm (=250 μm 2 ) and the size of the resistor  133  ( 143 ) is about 1 μm×5 μm (=5 μm 2 ). Also, since connections serve as the fuses  132  and  134  ( 142  and  144 ), the size of the fuses  132  and  134  ( 142  and  144 ) is trivial. Therefore, the size of the switch circuit  13  ( 14 ) is about 300 μm 2 , while the size of the anode pad P A  of  FIG. 1  is 10000 μm 2 . Thus, the size of the semiconductor devices  2  and  3  of  FIGS. 3 to 10  is much smaller than that of the semiconductor device  1  of  FIGS. 1 and 2 . 
     In the semiconductor devices  2  and  3  of  FIGS. 3 to 10 , the transistor  11   n  is of an n-type and the transistors  131   p  and  141   p  are of a p-type. The transistors  131   p  and  141   p  can be replaced by n-channel MOS transistors  131   n  and  141   n , respectively, as illustrated in  FIGS. 11A and 11B  corresponding to  FIGS. 3 and 7 , respectively. In  FIGS. 11A and 11B , the switch circuits  13  and  14  of  FIGS. 3 and 7  are replaced by switch circuits  13 ′ and  14 ′, respectively, where the transistor  131   n  ( 141   n ) is provided instead of the transistor  131   p  ( 141   p ), and the fuse  132  ( 142 ) and the resistor  133  ( 143 ) are exchanged with each other. 
     In  FIGS. 11A and 11B , note that fuses  134  and  144  can be added to the switch circuits  13 ′ and  14 ′, respectively. 
     Also, the transistor  11   n  can be replaced by a p-channel MOS transistor  11   p  as illustrated in  FIGS. 12A and 12B  corresponding to  FIGS. 3 and 7 , respectively. In  FIGS. 12A and 12B , the semiconductor devices  2  and  3  of  FIGS. 3 and 7  are replaced by semiconductor devices  2 ′ and  3 ′, respectively, where the transistor  11   p  is provided instead of the transistor  11   n  of  FIGS. 3 and 7 . 
     In  FIGS. 12A and 12B , note that fuses  134  and  144  can be added to the switch circuits  13  and  14 , respectively. 
     Further, the transistors  131   p  and  141   p  can be replaced by n-channel MOS transistors  131   n  and  141   n , respectively, and also, the transistor  11   n  can be replaced by a p-channel MOS transistor  11   p , as illustrated in  FIGS. 13A and 13B  corresponding to  FIGS. 3 and 7 , respectively. In  FIGS. 13A and 13B , the semiconductor devices  2  and  3  of  FIGS. 3 and 7  are replaced by semiconductor devices  2 ″ and  3 ″, respectively, where the transistor  11   p  is provided instead of the transistor  11   n  of  FIGS. 3 and 7 , and the switch circuits  13  and  14  of  FIGS. 3 and 7  are replaced by switch circuits  13 ′ and  14 ′, respectively, where the transistor  131   n  ( 141   n ) is provided instead of the transistor  131   p  ( 141   p ), and the fuse  132  ( 142 ) and the resistor  133  ( 143 ) are changed with each other. 
     In  FIGS. 13A and 13B , note that fuses  134  and  144  can be added to the switch circuits  13 ′ and  14 ′, respectively. 
     Additionally, the protection circuit  12  can be constructed by a Zener diode whose breakdown voltage serves as a clamp voltage (see:  FIGS. 14A and 14B ). 
       FIGS. 14A and 14B  illustrate third and fourth embodiments, respectively, of the semiconductor device according to the present invention. That is, the switch circuits  13  ( 13 ′) and  14  ( 14 ′) of  FIGS. 3 and 7  ( FIGS. 11A and 11B ) can be applied to a CMOS device as illustrated in  FIGS. 14A and 14B , where the p-channel MOS transistor  11   p  and the n-channel MOS transistor  11   n  are connected in series between power supply lines V DD  and V SS . The gates of the transistors  11   p  and  11   n  are connected to an input line IN and the drains of the transistors  11   p  and  11   n  are connected to an output line OUT. 
     In  FIGS. 14A and 14B , the switch circuits  13  and  14  are connected between the source and drain of the p-channel MOS transistor  11   p  and between the source and drain of the n-channel MOS transistor  11   n.    
     In  FIG. 14A , Zener diodes  12 ′ serving as protection circuits  12  of  FIG. 3  are connected between the power supply line V DD  and the input line IN, between the input line IN and the power supply line V SS , between the power supply line V DD  and the output line OUT, and between the output line OUT and the power supply line V SS . Switch circuits which are the same as the switch circuit  13  of  FIG. 3  are connected to the cathodes of the Zener diodes  12 ′, the power supply line V DD  (or the power supply line V SS ) and the input line IN (or the output line OUT). Also, an input pad P IN , a power supply pad P VDD , output pad P OUT  and a power supply pad P VSS  are connected by bonding wires W 11 , W 12 , W 13  and W 14  to external terminals T 11 , T 12 , T 13  and T 14 , respectively. Thus, a semiconductor device  4  is formed. 
     In  FIG. 14B , Zener diodes  12 ′ serving as protection circuits  12  of  FIG. 7  are also connected between the power supply line V DD  and the input line IN, between the input line IN and the power supply line V SS , between the power supply line V DD  and the output line OUT, and between the output line OUT and the power supply line V SS . Switch circuits which are the same as the switch circuit  14  of  FIG. 7  are connected to the anodes of the Zener diodes  12 ′ and the power supply line V DD  (or the power supply line V SS ) and the input line IN (or the output line OUT). Also, an input pad P IN , a power supply pad P VDD , and output pad P OUT  and a power supply pad P VSS  are connected by bonding wires W 21 , W 22 , W 23  and W 24  to external terminals T 21 , T 22 , T 23  and T 24 , respectively. Thus, a semiconductor device  5  is formed. 
     In  FIGS. 14A and 14B , when a gate breakdown voltage test operation is performed upon the semiconductor devices  4  and  5  in a wafer state where the fuses  132  and  142  are not melted, test probes (not shown) are in contact with the input pad P IN , the power supply pad P VDD  and the power supply pad P VSS ) respectively. In this case, the transistor  131   p  or  131   n  is turned OFF so that the Zener diodes  12 ′ are invalidated. Therefore, a test voltage can be applied the pad P IN  to observe the breakdown voltage of the p-channel MOS transistor  11   p  and the breakdown voltage of the n-channel MOS transistor  11   n . In this case, the test voltage needs to be increased or decreased within a large voltage range from 0V to 30V, for example. That is, voltages of 30V and 0V are applied to the pads P VDD  and P VSS , respectively, while the switch circuits  13  and  14  are turned OFF. Note that, if the switch circuits  13  and  14  are absent, a high voltage of 30V cannot be applied between the source and drain of the p-channel MOS transistor  11   p  and between the source and drain of the n-channel MOS transistor  11   n  due to the small Zener voltage of the Zener diode  12 ′. 
     Note that, in  FIG. 14A , the switch circuit  13  can be replaced by the switch circuit  13 ′ of  FIG. 11A . Also, in  FIG. 14B , the switch circuit  14  can be replaced by the switch circuit  14 ′ of  FIG. 11B . 
     In the above-described embodiments, the semiconductor devices  2 ,  2 ′,  2 ″,  3 ,  3 ′,  3 ″,  4  and  5  are connected by the bonding wires W 1 , W 2 , W 3 , W 11 , W 12 , W 13 , W 14 , W 21 , W 22 , W 23  and W 24  to the external terminals T 1 , T 2 , T 3 , T 11 , T 12 , T 13 , T 14 , T 21 , T 22 , T 23  and T 24  of a lead frame, a motherboard or an interposer. However, the present invention can be applied to a flip-chip type semiconductor device (bare chip) which is connected to solder balls of a lead frame, a motherboard or an interposer without bonding wires. 
     It is apparent that the present invention is not limited to the above-described embodiments, but may be modified and changed without departing from the scope and sprit of the present invention.

Technology Category: 5