Patent Document

RELATED APPLICATIONS 
   The present application is a continuation of U.S. patent application Ser. No. 10/948,610, filed Sep. 23, 2004, now U.S. Pat. No. 7,285,810 which is a continuation of U.S. patent application Ser. No. 10/136,991, filed May 2, 2002, now U.S. Pat. No. 6,844,583, the disclosures of which are hereby incorporated herein by reference. U.S. patent application Ser. No. 10/136,991 claims the benefit of Korean Patent Application No. 2001-36624, filed on Jun. 26, 2001, and Korean Patent Application No. 2002-06192 filed on Feb. 4, 2002. 

   BACKGROUND OF THE INVENTION 
   The present invention relates to memory devices and methods of fabrication therefor, and more particularly, to ferroelectric memory devices and methods of fabrication therefor. 
   Typical ferroelectric memory devices can retain data even when de-energized. Similar to DRAMs and SRAMs, ferroelectric memory devices typically operate with a low power supply voltage. Thus, ferroelectric devices are attractive for use in smart cards or the like. 
   A conventional method of fabricating a ferroelectric memory device will be described with reference to  FIG. 1  through  FIG. 3 . Referring now to  FIG. 1 , a device isolation layer  13  is formed in a predetermined area of a semiconductor substrate  11  to define an active region. A plurality of insulated gate electrodes  15 , i.e., local word lines, is formed across the active region and the device isolation layer  13 . Thereafter, impurities are implanted into the active region between the gate electrodes  15  to form source/drain regions  17   s  and  17   d . A first lower interlayer insulating layer  19  is formed on the resultant structure. The first lower interlayer insulating layer  19  is patterned to form storage node contact holes that expose the source regions  17   s . Contact plugs  21  are then formed in the storage node contact holes. 
   Referring to  FIG. 2 , ferroelectric capacitors  32  are arrayed on the contact plugs  21 . Each of the ferroelectric capacitors  32  is composed of a bottom electrode  27 , a ferroelectric layer  29 , and a top electrode  31 . Each of the bottom electrodes  27  covers a respective contact plug  21 . A first upper interlayer insulating layer  33  is formed on the ferroelectric capacitors  32 . A plurality of main word lines  35 , which are local gate lines  15 , are then formed on the first upper interlayer insulating layer  33 . Each of the main word lines  35  generally controls four local word lines  15 . 
   Referring now to  FIG. 3 , a second upper interlayer insulating layer  37  is formed on the main word lines  35 . The second and first interlayer insulating layers  37  and  33  are patterned to form via holes  39  that expose the top electrodes  31 . A plurality of plate lines  41  are formed that contact the top electrodes  31  through the via holes  39 . The plate lines  41  are arranged to be parallel with the word lines  35 . 
   To reduce an aspect ratio of each of the via holes  39 , wet and dry etch techniques can be used. In this case, the via hole  39  tends to have an inclined upper sidewall  39   a , as shown in  FIG. 3 . Unfortunately, excessive wet-etch may result in exposure of the main word lines  35 . 
   As another approach to reduce an aspect ratio of the via hole  39 , the diameter of the via hole  39  can be increased. However, a spacing between the via hole  39  and an adjacent main word line  35  tends to decrease with an increase in integration level. This makes precise alignment during a photo process for forming the via hole  39  desirable. 
   According to the foregoing prior art, decreasing an aspect ratio of the via holes leads to a strong probability that the main word lines will be exposed. Therefore, it is hard to avoid an electric short between the plate line and the main word line as well as a contact failure between the top electrode and the plate line. 
   SUMMARY OF THE INVENTION 
   According to some embodiments of the present invention, a ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. In some embodiments, the ferroelectric capacitors include an upper electrode, and the plurality of plate lines includes a plurality of local plate lines that contact the upper electrodes of the ferroelectric capacitors. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. 
   According to other embodiments of the present invention, a ferroelectric memory device is fabricated. A plurality of ferroelectric capacitors is formed on a microelectronic substrate, the plurality of ferroelectric capacitors arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines are formed on the substrate, overlying the ferroelectric capacitors and extending along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plate lines may include local plate lines. An insulating layer may be formed on the plate lines, and a plurality of main plate lines may be formed on the insulating layer, respective ones of which contact respective ones of the local plate lines through openings in the insulating layer. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1-3  are cross-sectional views illustrating a conventional process for fabricating a ferroelectric memory device. 
       FIG. 4  is a top plan view of a ferroelectric memory device according to embodiments of the present invention. 
       FIG. 5  is a perspective view illustrating a ferroelectric memory device according to some embodiments of the present invention. 
       FIG. 6  is a perspective view illustrating a ferroelectric memory device according to further embodiments of the present invention. 
       FIG. 7  is a perspective view illustrating a ferroelectric memory device according to still other embodiments of the present invention. 
       FIGS. 8-14  are cross-sectional views of intermediate fabrication products illustrating operations for fabricating a ferroelectric memory device according to some embodiments of the present invention. 
       FIGS. 15-19  are cross-sectional views of intermediate fabrication products illustrating operations for fabricating a ferroelectric memory device according to other embodiments of the present invention. 
       FIGS. 20-26  are cross-sectional views of intermediate fabrication products illustrating operations for fabricating a ferroelectric memory device according to farther embodiments of the present invention. 
   

   DETAILED DESCRIPTION 
   The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which typical embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like numbers refer to like elements throughout. 
   Referring now to  FIG. 4  and  FIG. 5 , a device isolation layer  53  is located at a predetermined area of a semiconductor substrate  51  to define a plurality of active regions  53   a . A plurality of insulated gate electrodes  57  (i.e., a plurality of word lines) are arranged across the active regions  53   a  and the device isolation layer  53 . The gate electrodes  57  are parallel and extend along a row direction (y-axis). Each of the active regions  53   a  intersects a couple of gate electrodes  57  to divide each of the active regions  53   a  into three parts. A common drain region  61   d  is formed at an active region  53   a  between the pair of the gate electrodes  57 . Source regions  61   s  are formed at active regions  53   a  that are located at both sides of the common drain region  61   d . Cell transistors are formed at points where the gate electrodes  57  intersect the active regions  53   a . The cell transistors are arrayed along a column direction (x-axis) and the row direction (y-axis). 
   The cell transistors are covered with a lower interlayer insulating layer  74 . A plurality of bit lines  71  are arranged in the lower interlayer insulating layer  74 , transverse to the word lines  57 . The bit lines  71  are electrically connected to the common drain regions  61   d  through bit line contact holes  71   a . The source regions  61   s  are exposed by storage node contact holes  75   a  that penetrate the lower interlayer insulating layer  74 . Preferably, an upper sidewall of the storage node contact hole  75   a  has a sloped profile. Each of the storage node contact holes  75   a  is filled with contact plugs  75 . An upper diameter of the contact plug  75  is larger than a lower diameter thereof, as shown in  FIG. 5 . 
   A plurality of ferroelectric capacitors  82  (CP shown in  FIG. 4 ) are arrayed along the column direction (x-axis) and the row direction (y-axis). Each of the ferroelectric capacitors  32  includes a bottom electrode  77 , a ferroelectric layer pattern  79 , and a top electrode  81 . Respective ones of the bottom electrodes  77  are located on respective ones of the contact plugs  75 . As a result, the bottom electrodes  77  are electrically connected to the source regions  61   s  through the contact plugs  75 . Preferably, gaps between the ferroelectric capacitors  82  are filled with insulating layer patterns  85   a.    
   Preferably, a hydrogen barrier layer pattern  83   a  is disposed between the insulating layer pattern  85   a  and the ferroelectric capacitors  82 . Preferably, the hydrogen barrier layer pattern  83   a  is made of titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), silicon nitride (Si 3 N 4 ), or a combination thereof. This makes it possible to prevent hydrogen atoms from penetrating into the ferroelectric layer pattern  79 . If hydrogen atoms are implanted into the ferroelectric pattern  79 , a reliability of the ferroelectric pattern  79  may be degraded. For example, if hydrogen atoms are injected into a ferroelectric layer such as PZT (Pb, Zr, TiO 3 ) layer, oxygen atoms in the PZT layer may react with the hydrogen atoms to cause an oxygen vacancy therein. Owing to the oxygen vacancy, a polarization characteristic of the ferroelectric layer may deteriorate and cause malfunction. If hydrogen atoms are captured in interface traps between the ferroelectric layer pattern and top/bottom electrodes, an energy barrier therebetween may be lowered. Accordingly, leakage current characteristics of the ferroelectric capacitors may be deteriorated. 
   A plurality of local plate lines  87  (PL shown in  FIG. 4 ) are arranged on the ferroelectric capacitors  82  and the insulating layer pattern  85   a . The local plate lines  87  extend along the row direction (y-axis). A respective one of the local plate lines  87  covers a respective pair of adjacent rows of ferroelectric capacitors  82 . The local plate line  87  directly contacts with the top electrodes  81  of the underlying adjacent rows of capacitors  82 . The local plate lines  87  are covered with an upper interlayer insulating layer. The upper interlayer insulating layer may include first and second upper interlayer insulating layers  89  and  93 . 
   A plurality of main word lines  91  may be disposed between the first and second upper interlayer insulating layers  89  and  93 . Generally, each of the main word lines  91  controls four word lines  57  using a decoder. A main plate line  97  may be arranged in the upper interlayer insulating layer between the main word lines  91 . The main plate lines  97  are electrically connected to the local plate lines  87  through a slit-type via hole  95  penetrating the upper interlayer insulating layer. The slit-type via hole  95  extends in parallel along the row direction (y-axis). A width of the slit-type via hole  95  is larger than a diameter of the via hole ( 39  of  FIG. 3 ) of the prior art. The local plate line  87  directly contacts the upper surfaces of the top electrodes  81 . 
   In some embodiments, a plate line may be composed of the local plate line  87  and the main plate line  97 . In other embodiments, the plate line may be composed of only the local plate line  87  or only the main plate line  97 . Particularly, if the plate line is composed of only the main plate line  97 , the insulating layer pattern  85   a  is preferably made of material having an etch selectivity with respect to the upper interlayer insulating layer. For example, if the upper interlayer insulating layer is made of silicon oxide, the insulating pattern  85   a  is preferably made of silicon nitride. 
   A ferroelectric memory device according to second embodiments of the invention is shown in  FIG. 6 . In these embodiments, cell transistors, a lower interlayer insulating layer, and contact plugs have the same configuration as those in the embodiments of  FIG. 5 . Further description of these components is therefore omitted in light of the foregoing description. 
   Referring to  FIG. 4  and  FIG. 6 , a plurality of ferroelectric capacitors covering the contact plugs  75  are located on the lower interlayer insulating layer  74 . Therefore, the ferroelectric capacitors are 2-dimensionally arranged along the row and column directions. Each of the ferroelectric capacitors includes a bottom electrode  101 , a ferroelectric layer pattern  103 , and a common top electrode  109 . The common top electrode  109  is extended to cover ferroelectric layer patterns  103  in adjacent rows. The common top electrode  109  extends along the row direction, similar to the local plate line PL shown in  FIG. 4 . Preferably, gaps between the ferroelectric patterns  103  and between the bottom electrodes  101  are filled with an insulating layer pattern  107   a . Preferably, a hydrogen barrier layer pattern  105   a  is disposed between the lower insulating layer pattern  107   a  and at least the ferroelectric layer pattern  103 . 
   The common top electrode  109  is covered with an upper insulating layer  111 . The upper insulating layer  111  has a slit-type contact hole that exposes the common top electrode  109 . The slit-type contact hole extends along the row direction (y-axis) and is covered with a local plate line  113  (PL shown in  FIG. 4 ). The local plate line  113  is electrically connected to the common top electrode  109  through the slit-type contact hole. The local plate line  113  is covered with an upper interlayer insulating layer including first and second upper interlayer insulating layers  115  and  119 . 
   A plurality of main word lines  117  may be disposed between the first and second upper interlayer insulating layers  115  and  119 . The main word lines  117  extend in parallel along the row direction. A main plate line  123  may be located in the upper interlayer insulating layer between the main word lines  117 . The main plate line  123  is electrically connected to the local plate line  113  through a slit-type via hole  121  that penetrates the upper interlayer insulating layer. The slit-type via hole  121  extends along the row direction (y-axis). 
   A plate line includes the local plate line  113  and the main plate line  123 . Alternatively, the plate line may consist of only the local plate line  113  or only the main plate line  123 . 
   A ferroelectric memory device according to third embodiments of the invention is shown in  FIG. 7 . In these embodiments, cell transistors, a lower interlayer insulating layer, and contact plugs have the same configuration as those in the embodiments of  FIG. 5 . Further description of these components will therefore be omitted in light of the foregoing description. 
   Referring to  FIG. 4  and  FIG. 7 , a plurality of ferroelectric capacitors covering respective ones of the contact pugs  75  is arranged on the lower interlayer insulating layer  74 , such that the ferroelectric capacitors are arrayed along row and column directions. Each of the ferroelectric capacitors includes a bottom electrode  151 , a common ferroelectric layer pattern  155 , and a common top electrode  157 . The common ferroelectric pattern  155  is extended to cover the bottom electrodes  151  of at least two adjacent rows. The common top electrode  157  is stacked on the common ferroelectric layer pattern  155 . Therefore, the common ferroelectric pattern  155  and the common top electrode  157  extend along the row direction, similar to the local plates line PL shown in  FIG. 4 . 
   Preferably, a gap area between the bottom electrodes  151  is filled with a lower insulating layer pattern  153   a , and gap areas between the common ferroelectric layer patterns  155  and between the common top electrodes  157  are filled with a top insulating layer pattern  161 . A hydrogen barrier layer pattern  159  may be disposed between the top insulating layer pattern  161  and at least the common ferroelectric layer pattern  155 . 
   A local plate line  163  (e.g., corresponding to the plate line PL shown in  FIG. 4 ) is located on the common top electrode  157 . The local plate line  163  extends in the row direction. The local plate line  163  is covered with an upper interlayer insulating layer, which includes first and second upper interlayer insulating layers  165  and  169 . 
   A plurality of main word lines  167  may be disposed between the first and second upper interlayer insulating layers  165  and  169 . The main word lines  167  extend in parallel along the row direction. A main plate line  173  may be disposed in the upper interlayer insulating layer between the main word lines  167 . The main plate line  173  is electrically connected to the local plate line  163  through a slit-type via hole  171  that penetrates the upper interlayer insulating layer. The slit-type via hole  171  extends along the row direction (y-axis). 
   A plate line includes the local plate line  163  and the main plate line  173 . Alternatively, the plate line may consist of only the local plate line  163  or only the main plate line  173 . 
   A method of fabricating a ferroelectric memory device according to some embodiments of the present invention will now be described more fully hereinafter with reference to  FIG. 8  through  FIG. 14 . 
   Referring now to  FIG. 8 , a device isolation layer  53  is formed in a predetermined area of a semiconductor substrate  51  to define a plurality of active regions  53   a . A gate insulating layer, a gate conductive layer, and a capping insulating layer are sequentially formed on the semiconductor substrate  51 . The capping insulating layer, the gate conductive layer, and the gate insulating layer are successively patterned to form a plurality of gate patterns  60  crossing over the active regions and the device isolation layer  53 . Each of the gate patterns  57  includes a gate insulating layer pattern  55 , a gate electrode  57 , and a capping insulating layer pattern  59 . 
   Using the gate patterns  60  and the device isolation layer  53  as ion implantation masks, impurities are implanted into the active regions to form three impurity regions in each of the active regions. A central impurity region corresponds to a common drain region  61   d , and the other regions correspond to source regions  61   s . Therefore, a couple of cell transistors are formed in each of the active regions. The cell transistors are arrayed on the semiconductor substrate  51  along row and column directions. Then, a spacer  63  is formed on a sidewall of the gate pattern  60  using, for example, conventional processes. 
   Referring now to  FIG. 9 , a first lower interlayer insulating layer  65  is formed on the semiconductor substrate. The first lower interlayer insulating layer  65  is patterned to form pad contact holes exposing the source/drain regions  61   s  and  61   d . A conventional technique may be used to form storage node pads  67   s  and bit line pads  67   d  in the pad contact holes. The storage node pads  67   s  are connected to the source regions  61   s , and the bit line pad  67   d  is connected to the common drain region  61   d . A second lower interlayer insulating layer  69  is formed on the pads  67   s  and  67   d . The second lower interlayer insulating layer  69  is patterned to form a bit line contact hole ( 71   a  shown in  FIG. 4 ) exposing the bit line pad  67   d . A bit line  71  is formed, contacting the bit line pad  67   d.    
   Referring now to  FIG. 10 , a third lower interlayer insulating layer  73  is formed on the bit line  71 . The second and third lower interlayer insulating layers  69  and  73  are patterned to form storage node contact holes ( 75   a  shown in  FIG. 4 ) exposing the storage node pads  67   s . The storage node contact hole may be formed by a wet and/or dry etch process to increase an upper diameter thereof. Accordingly, an upper sidewall of the storage node contact hole may have a sloped profile, as shown in the drawing. This is aimed at decreasing in an electrical resistance between a lower electrode, formed in a subsequent process, and the source region  61   s . Contact plugs  75  are formed in the storage node contact holes. 
   Referring now to  FIG. 11 , a conductive bottom electrode layer, a ferroelectric layer, and a conductive top electrode layer are sequentially formed on the contact plugs  75  and the lower interlayer insulating layer  74 . The top electrode layer, the ferroelectric layer, and the bottom electrode layer are successively patterned to form a plurality of ferroelectric capacitors  82  (CP shown in  FIG. 4 ) that are arrayed along row and column directions. Each of the ferroelectric capacitors  82  includes a bottom electrode  77 , a ferroelectric layer pattern  79 , and a top electrode  81 . Respective ones of the bottom electrodes  77  are in contact with respective ones of the contact plugs  75 . Thus, respective ones of the ferroelectric capacitors  82  are electrically connected to respective ones of the source regions  61   s . An insulating layer  85  is formed on the resultant structure. Prior to formation of the insulating layer  85 , a conformal hydrogen barrier layer  83  may be formed. Preferably, the hydrogen barrier layer  83  is made of titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), silicon nitride (Si 3 N 4 ), or combination thereof. 
   Referring now to  FIG. 12 , the insulating layer  85  and the hydrogen barrier layer  83  are planarized to expose the top electrodes  81 . Thus, a hydrogen barrier layer pattern  83   a  and an insulating layer pattern  85   a  are formed between the ferroelectric capacitors  82 . The hydrogen barrier layer pattern  83   a  covers sidewalls of the ferroelectric capacitors  82  (i.e., sidewalls of the ferroelectric layer patterns  79 ), thereby preventing hydrogen atoms from being injected into the ferroelectric layer patterns  79 . If hydrogen atoms are injected into, the ferroelectric layer patterns  79 , characteristics of ferroelectric capacitors  82 , such as a polarization characteristic or a leakage current characteristic, may be deteriorated. As a result, the hydrogen barrier layer pattern  83   a  can improve characteristics of the ferroelectric capacitors  82 . 
   A conductive lower plate layer is formed on an entire surface of the semiconductor substrate including the insulating layer pattern  85   a . The conductive lower plate layer is patterned to form local plate line  87  (PL shown in  FIG. 4 ) that extends parallel with the word lines  57 . The local plate line  87  directly contacts the common electrode  81 . An upper interlayer insulating layer is formed on the local plate line  87 . The upper interlayer insulating layer is formed by sequentially stacking first and second upper interlayer insulating layers  89  and  93 . Prior to formation of the second upper interlayer insulating layer  93 , a plurality of parallel main word lines  91  may be formed on the first upper interlayer insulating layer  89 . One main word line  91  may control four word lines  57  through a decoder. 
   Referring now to  FIG. 13 , the upper interlayer insulating layer is patterned to form a slit-type via hole  95  exposing the local plate line  87 . The slit-type via hole  95  is formed between the main word lines  91 , in parallel with the main word lines  91 . Compared with a prior art, the slit-type via hole  95  has greater width, as shown in the drawing. Nevertheless, a spacing (A) between the slit-type via hole  95  and the adjacent main word lines  91  can be greater, compared with the prior art. This can lead to a significant decrease in the probability that the word lines  91  will be exposed, even though the slit-type via hole  95  is formed by wet and dry etch in order to lower an aspect ratio thereof. 
   A conductive upper plate layer, such as a metal layer, is formed on the resultant structure, passing through the slit-type via hole  95  to contact the common top electrode  87 . The upper plate layer may exhibit good step coverage because the aspect ratio of the slit-type via hole  95  may be kept relatively low. The upper plate layer is patterned to form a main plate line  97 . 
   Modifications of the embodiments described in  FIGS. 8-13  will now be described with reference to  FIG. 14 . These modified embodiments differ in the manner in which local plate lines  87  are formed. In the modified embodiments, not only the top electrodes  81 , but also the insulating layer pattern  85   a  therebetween, are exposed during formation of the slit-type via hole  95 . Accordingly, the insulating layer pattern  85   a  is preferably made of material (e.g., silicon nitride) having an etch selectivity with respect to the upper interlayer insulating layer. 
   Operations for fabricating a ferroelectric memory device according to additional embodiments of the invention will now be described with reference to  FIG. 15  through  FIG. 19 . In these embodiments, cell transistors, a lower interlayer insulating layer, and contact plugs can be formed in the same manner as the embodiments described in  FIGS. 8-13 . 
   Referring now to  FIG. 15 , a conductive bottom electrode layer and a ferroelectric layer are sequentially formed on the lower interlayer insulating layer  74  and the contact plugs  75 . The ferroelectric layer and the bottom electrode layer are successively patterned to form a plurality of bottom electrodes  101  covering the contact plugs  75 , and a plurality of ferroelectric layer patterns  103  stacked on the bottom electrodes  101 . A hydrogen barrier layer  105  and a lower insulating layer  107  are sequentially formed on the ferroelectric layer patterns  103 . 
   Referring now to  FIG. 16 , the lower insulating layer  107  and the hydrogen barrier layer  105  are planarized to expose the ferroelectric layer patterns  103 . Thus, a lower insulating layer pattern  107   a  and a hydrogen barrier layer pattern  105   a  are formed in gaps between the ferroelectric layer patterns  103  and between the bottom electrodes  101 . A conductive top electrode layer is formed on the lower insulating layer pattern  107   a , the hydrogen barrier layer pattern  105   a , and the ferroelectric layer patterns  103 . The top electrode layer is patterned to form a common top electrode  109  that extends parallel to the word lines  57 . The common top electrode  109  covers the ferroelectric layer patterns  103 . 
   Referring now to  FIG. 17 , an upper insulating layer  111  is formed on the common top electrode  109 . The upper insulating layer  111  is patterned to form a slit-type contact hole exposing the common top electrode  109 . A conductive lower plate layer is formed, contacting the common top electrode  109  through the slit-type contact hole. The lower plate layer is patterned to form a local plate line  113  (PL shown in  FIG. 4 ). First and second upper interlayer insulating layers  113  and  119  are sequentially formed on the local plate line. A plurality of main word lines  117  may be formed between the first and second interlayer insulating layers  113  and  119 . The main word lines  117  are formed in the same manner as in the previously described embodiments. Referring to  FIG. 18 , a slit-type via hole  121  is formed in the upper interlayer insulating layer. A main plate line  123  is then formed as previously described. 
   Modifications of the embodiments described in  FIGS. 15-18  will now be described with reference to  FIG. 19 . The modified embodiments are identical to the embodiments of  FIGS. 15-18 , except that the local plate line  115  is not formed. In this case, the slit-type via hole  121  exposes the common top electrode  109 . 
   A method of fabricating a ferroelectric memory device according to further embodiments of the invention will now be described with reference to  FIG. 20  through  FIG. 24 . In these embodiments, cell transistors, a lower interlayer insulating layer, and contact plugs are formed in the same manner as in the previously described embodiments. 
   Referring now to  FIG. 20 , a conductive bottom electrode layer is formed on the lower interlayer insulating layer  74  and the contact plugs  75 . The bottom electrode layer is patterned to form a plurality of bottom electrodes  151  covering the contact plugs  75 . A lower insulating layer  153  is formed on the bottom electrodes  151 . 
   Referring now to  FIG. 21 , the lower insulating layer  153  is planarized to expose upper surfaces of the bottom electrodes  151 , thus forming an insulating layer pattern  153   a  in a gap between the bottom electrodes  151 . A ferroelectric layer and a conductive top electrode layer are sequentially formed on the lower insulating layer pattern  153   a  and the bottom electrodes  151 . The upper electrode layer and the ferroelectric layer are successively patterned to form a common ferroelectric layer pattern  155  and a common top electrode  157 . The common ferroelectric layer pattern  155  covers the adjacent bottom electrodes  151 . A hydrogen barrier layer pattern  159  and an upper insulating layer pattern  161  are formed in gaps adjacent the common ferroelectric pattern  155  and the common top electrode  157 . 
   Referring now to  FIG. 22 , a conductive lower plate layer is formed on the upper insulating layer pattern  161 . The lower plate layer is patterned to form a local plate line  163  (PL shown in  FIG. 4 ) covering the common top electrode  163 . An upper interlayer insulating layer is formed on the local plate line  163 . The upper interlayer insulating layer is formed by sequentially stacking first and second upper interlayer insulating layers  165  and  169 . A plurality of parallel main word lines  167  may be formed between the first and second upper interlayer insulating layers  165  and  169 . The main word lines  167  may be formed as in previously described embodiments. 
   Referring now to  FIG. 23 , a slit-type via hole  171  is formed in the upper interlayer insulating layer. A conductive main plate line  173  is formed, extending through the slit-type via hole  171 . The slit-type via hole  171  and the main plate line  173  may be formed as in the previously described embodiments. 
   A modification of the embodiments of  FIGS. 20-23  will now be described with reference to  FIG. 24 . The modified embodiments are identical to the embodiments of  FIGS. 20-23  except that the local plate line  163  is omitted. In this case, the slit-type via hole  171  exposes the common top electrode  157 . 
   In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Technology Category: 5