Patent Document

FIELD OF THE INVENTION 
       [0001]    The invention relates to Electrostatic Discharge (ESD) devices. In particular it relates to an ESD solution for narrow ESD protection window applications such as high output power arrays. 
       BACKGROUND OF THE INVENTION 
       [0002]    Electrostatic Discharge (ESD) protection becomes challenging when the ESD protection window is very narrow. For instance in protecting the power train of a magnetic DC-DC converter, especially when hot plug-in specification is taken into account, the ESD protection is very narrow due to the high output power array associated with the converter. Ideally therefore the I-V characteristics of the ESD protection device should be substantially vertical. One type of device commonly used for ESD protection is a lateral PNP bipolar junction transistor (BJT), an example of which is shown in  FIG. 1   FIG. 1  shows a prior art lateral PNP in cross-section. It includes a p-type emitter  100 , a p-type base  102  formed underneath the p-type emitter  100  and extending laterally toward a p-type collector  104 . The emitter  100  includes an emitter contact region  110 , and the collector includes a collector contact region  114 . The contact to the base, which is to the left of the emitter contact, is not shown in  FIG. 1 . The lateral PNP has the advantage that it provides high holding voltages and typically can handle relatively high currents. However, at values above those corresponding to the holding voltage, the current flowing through the device tends to saturate (typically in the milliamp range). In order increase the protection window and allow the PNP to operate at higher currents requires the size of the device to be increased, resulting in a large footprint. 
         [0003]    One ESD protection solution with high current carrying capability is offered by SCR devices, which due to double injection of current can handle higher currents than PNP BJTs (approximately 10 mA/um compared to approximately 1 mA/um for PNPs). A cross section through a prior art SCR is shown in  FIG. 2 . Like the lateral PNP of  FIG. 1 , the SCR in  FIG. 2  includes a p-type emitter  200  with emitter contact  210 , an n-type base  202 , which extends underneath the emitter  200  and continues laterally toward a p-type collector  204  with its collector contact  214 . As shown in  FIG. 2 , the emitter contact  210  is connected to the base contact  212  in this case. However, the SCR structure differs from a lateral PNP in that it further includes an n-type region  206  (referred to herein as an n-emitter) with contact  216  on the low voltage side to define a pnpn structure with the emitter  200 , base  202 , and collector  204 . This gives the SCR its double injection characteristics. However SCRs also have a down side caused by the double injection. They have a lower holding voltage than PNPs. 
         [0004]    The present invention provides a new ESD protection structure that offers the high holding characteristics of a PNP device as well as the higher current handling capacity provided by an SCR. 
       SUMMARY OF THE INVENTION 
       [0005]    According to the invention there is provided an ESD protection circuit, comprising a PNP structure with a p-type emitter defining an anode, a p-type collector defining a cathode, an n-type base defining a control gate, the ESD protection circuit further comprising an n-type emitter on the cathode side of the control gate, and an auto-biasing circuit connected to the n-type emitter for controlling electron flow into the n-type emitter. The auto-biasing circuit may comprise an NMOS transistor. The NMOS transistor may be controlled by a reference Zener diode connected to a gate of the NMOS transistor. The Zener may be connected between a high voltage node, e.g. a pad, and the NMOS gate. The auto-biasing circuit may include a resistor connected between the gate and ground. 
         [0006]    Further, according to the invention, there is provided a method of selectively increasing the current carrying capacity of an ESD device implemented as a PNP transistor that includes a p-type emitter, an n-type base, and a p-type collector, the method comprising providing an n-type emitter on the collector side of the base, and injecting electrons into the n-type emitter only during an ESD event. The injecting of electron current may comprise connecting a transistor between the n-type emitter and ground and controlling the transistor to conduct current only during an ESD event. The transistor may be controlled to conduct current during only part of the ESD event. The transistor may include a control gate, and controlling the transistor may comprise controlling the voltage on the control gate. Controlling the voltage may comprise connecting a Zener diode between the control gate and a protected node. The transistor may comprise an NMOS transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  is a cross-section through a prior art PNP BJT, 
           [0008]      FIG. 2  is a cross-section through a prior art SCR device, 
           [0009]      FIG. 3  a circuit diagram of one embodiment of an ESD protection device of the invention controlled by a MOSFET with reference Zener, and 
           [0010]      FIG. 4  shows a graph of pad voltage vs In-emitter/Itotal based on simulation results for an ESD protection device of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0011]    The present invention defines an ESD protection circuit that provides for the characteristics of a PNP BJT (such as that illustrated in  FIG. 1 ) when there is no ESD event, but that includes an n-type emitter region on the low voltage side to define an SCR structure. The ESD protection circuit differs from a conventional SCR in that it provides the ability to selectively engage the features and characteristics of an SCR by including an auto-biasing circuit for selectively engaging the n-type emitter region. 
         [0012]    As discussed in the implementation of  FIG. 3 , a resistor may be provided between the emitter and base contacts. One embodiment of an ESD protection circuit of the invention is shown in  FIG. 3 . The SCR structure includes a PNP device comprising an emitter  300 , a base  302  and a collector  304 . In addition, to provide the pnpn configuration for an SCR, the structure includes an n-type region in the form of a low side n-emitter, which is depicted by the additional contact  306 . In this embodiment, the base  302  of the ESD protection structure is controlled by a low voltage reference Zener  310 . The base  302  is thus connected through a resistor  312  to pad  320 , and via the Zener  310  to ground. In accordance with the invention, an auto-biasing circuit is provided to control current flow to the n-emitter  306 . In this embodiment the auto-biasing circuit comprises an NMOS  330  controlled by a reference Zener diode  332 , which connects the gate of the NMOS  330  to the pad  320 . The gate of the NMOS is also connected via a resistor  334  to ground to establish a current path to ground. 
         [0013]    When the pad voltage is lower than the breakdown voltage of the Zener diode  332  the gate voltage of the NMOS  330  is close to zero since it is tied to ground via the resistor  334 . Thus the NMOS  330  is not conducting and the n-emitter contact  306 , which is connected to the drain of the NMOS, is floating. Thus the device behaves like a PNP BJT with a correspondingly high holding voltage. 
         [0014]    Once the pad voltage exceeds the breakdown voltage of the Zener diode  332  the NMOS starts conducting and the channel current provides an electrical connection for the n-emitter  306 . This creates the condition for additional electron current and thus injects additional electrons into the conductivity modulation region of the SCR structure as define by the pnpn regions formed by the p-emitter, n-base, p-collector and n-emitter, as discussed above with respect to  FIG. 2 . It will however be appreciated that at this stage the additional electrons injected into the device also provide for additional space charge compensation resulting in lower holding voltage. On the other hand the on-state resistance of the ESD protection structure is greatly improved to where it is substantially zero. This corresponds to an ideal vertical I-V characteristic. Simulations have demonstrated that as the fraction of the ESD protection structure current flowing through the n-emitter increases the pad voltage (which corresponds to the total current level of 10 mA/um) decreases drastically at about 0.75 as shown in  FIG. 4 . 
         [0015]    The holding voltage can be engineered to the desired value by selecting a Zener diode  332  with the desired properties since the effective clamp voltage (Vhclamp) is related to the PNP transistor holding voltage (Vhpnp) and the breakdown voltage of Zener  332  (Vbredzl) by the relationship 
         [0000]      Vhclamp=min (Vhpnp, Vbredzl) 
         [0016]    The present ESD protection structure therefore provides a new solution for power train protection. 
         [0017]    While a particular configuration for the auto-biasing circuit was discussed above with respect to the embodiment of  FIG. 3 , it will be appreciated that the invention is not limited to the particular auto-biasing circuit. Current into the n-emitter can be controlled in different ways to coincide with an ESD event. For example instead of using an NMOS transistors to control the n-emitter of the SCR, a bipolar junction transistor (BJT), e.g. NPN or PNP can be used to control electron current to the n-emitter.

Technology Category: h