Patent Document

BACKGROUND 
     1. Field 
     The disclosure relates generally to a voltage reference circuit and low voltage oscillator and, more particularly, to a system for a low power consumption thereof. 
     2. Description of the Related Art 
     Voltage reference circuits and oscillator circuits consume power which impacts the total system power consumption. Voltage reference circuits and oscillators are used in conjunction with semiconductor devices, integrated circuits (IC), and other applications. The requirement for a stable reference voltage is often required in electronic design. Voltage reference circuits that provide a stable reference voltage are sometimes bandgap voltage reference circuits. 
     A traditional bandgap reference circuit, the voltage difference between two p-n junctions (e.g. diodes, or bipolar transistors), operated at different current densities or at different transistor sizes, can be used to generate a proportional to absolute temperature (PTAT) current in a first resistor. This current can then be used to generate a voltage in a second resistor. This voltage, in turn, is added to the voltage of one of the junctions. The voltage across a diode operated at a constant current, or herewith a PTAT current, is complementary to absolute temperature (CTAT). If the ratio between the first and second resistor is chosen properly, the first order effects of the temperature dependency of the diode and the PTAT current will cancel out. In this fashion, a circuit can be independent of temperature variation, and provide a constant voltage reference. 
     Circuits of this nature that are temperature insensitive are referred to as bandgap voltage reference circuits. The resulting voltage is about 1.2-1.3V, depending on the particular technology and circuit design, and is close to the theoretical silicon bandgap voltage of 1.22 eV at 0 degrees Kelvin. The remaining voltage change over the operating temperature of typical integrated circuits is on the order of a few millivolts. Because the output voltage is by definition fixed around 1.25V for typical bandgap reference circuits, the minimum operating voltage is about 1.4V. A circuit implementation that has this characteristic is called a Brokaw bandgap reference circuit. 
     In voltage reference circuits, operation below the bandgap voltage level is desirable. These voltage reference circuits are known as sub-bandgap voltage references. Technology scaling of the physical dimensions of integrated electronics allows for higher density circuits. To maintain reliability of semiconductor components, dimensional technology scaling also requires scaling of the power supply voltage. This is known as constant electric field scaling theory. But, with the technology scaling, silicon remains the most commonly used technology. Hence, voltage reference circuits with power supply voltages as low 1.1 V will require sub-bandgap operation. 
     With mixed voltage interfaces, it is also desirable to provide voltage reference circuits and oscillators above the bandgap voltage level. Voltage reference circuits and oscillators that operate to 3.6V power supply levels are also needed. Systems power supply rail voltages can range from 1.1V to 3.6V. In semiconductor technologies, typically having at least two transistors, with different MOSFET gate oxide thickness, typically referred to as thin-oxide MOSFET and thick oxide MOSFET. The thick oxide MOSFET uses dual oxide, or triple oxide thicknesses to provide higher power supply voltage tolerance for higher voltage operation and applications. Voltage tolerance for circuits can also be achieved by using “stacks” of MOSFETs (for example cascode MOSFET circuits) to lower the voltage across any given thin-oxide MOSFET transistor. 
     In some system applications, voltage reference and oscillators can be turned on, and turned off, sequence dependent, sequence independent, as well as “always on” systems. In the case of an “always on” system, power consumption is an issue. It is desirable to have voltage reference and oscillators in an “always on” state which has a low power consumption. A target level for low power consumption is typically 3 μA for the portable business. 
     A prior art sub-bandgap voltage reference is depicted in  FIG. 1 . A low voltage power supply rail voltage V CC    10  and a ground rail  20  provides power to the circuit. The voltage reference output  30  is between the power supply voltage and the ground potential. The differential amplifier  40  supplies an output voltage to the gates of p-channel MOSFET P 1   50 A, P 2   50 B, and P 3   50 C. The p-channel MOSFET P 1   50 A drain is connected to the parallel combination of resistor R 1   60 , and diode  70 . The p-channel MOSFET P 2   50 B is connected to an array of diode elements  80  and a resistor R 3   90 . A second resistor R 2   95  is in parallel with the array of diodes  80  and resistor R 3   90 . The output reference voltage  30  is electrically coupled to the p-channel transistor P 3   50 C and resistor element R 4   97 . 
     In the prior art circuit of  FIG. 1 , the technology that is used only allows for a “stack” of one MOSFET gate-to-source voltage, VGS, and one MOSFET drain-to-source voltage, VDS for a low voltage rail. Furthermore, the power supply rail is as low as 1.1V, traditional bandgap voltage reference networks can not be used. Different implementations can not only use this network, but also operational amplifiers. Operational amplifier circuit topologies always need a at least one MOSFET drain-to-source voltage, VDS, for tail current generation, one MOSFET drain-to-source voltage, VDS, for the V-mode comparison, and one MOSFET gate-to-source voltage for the output p-channel MOSFET (PMOS) to drive. As a result, these structures are not suitable for a minimum power supply voltage of 1.1V. Operational amplifier circuits add significant increase in the number of circuit branches, leading to more complexity, more complications, and more power consumption. 
     For oscillator circuits, low power consumption and accuracy are important design objectives.  FIG. 2  illustrates a relaxation oscillator circuit. The circuit is powered by VCC  150 . A comparator  100  evaluates two incoming signals from the voltage on a capacitor VC  105  with respect to a reference voltage VREF  110 . The current reference IREF  120  provides current for the charging of the capacitor C  140 . A switch  130  is activated by a feedback loop from the COMPOUT (oscillator out signal)  160 . The switch  130  is in parallel with capacitor  140 . The comparator adds at least four branches to the circuit (e.g. a differential pair, a bias and an output stage). Additionally, it requires a voltage of a MOSFET gate-to-source voltage VGS, and two MOSFET drain-to-source voltages, 2 VDS, to operate properly. Hence, this limits the ability to use this circuit for sub-bandgap voltages, and low voltage applications. The generation of IREF  120  requires an extra operational amplifier to divide the voltage reference by a resistance of value R. Hence, the oscillator introduces a number of current branches increasing the complexity of the network. 
     With technology scaling, according to constant electric field scaling theory, the power supply voltage, V DD , continues to decrease to maintain dielectric reliability. In current and future semiconductor process technology, having minimum dimensions of, for example, 0.18 μm, and 0.13 μm, the native power supply voltage (or internal power supply voltage) is 1.5V internal supply voltage for digital circuits, and other sensitive analog circuitry. For technologies whose minimum dimension is below 0.13 μm, the issue is also a concern. 
     In oscillators, a low voltage wide frequency oscillator has been described. As discussed in U.S. Patent Application US 2013/0229238 to Wadhwa describes a low voltage oscillator that is controlled by latch networks. The implementation includes multiple delay elements, in which each delay element includes two inverters, a control input, a plurality of delay elements, a latching element, and a plurality of current-source devices. 
     Low power oscillators have been disclosed. As discussed in U.S. Pat. No. 8,390,362 to Motz et al, a low power, high voltage integrated circuit allows for both low power, and high voltage in a given implementation. The circuit controls a sleep/wake mode, or a duty cycle. 
     Low voltage oscillators can utilize capacitor-ratio selectable duty cycle. As discussed in U.S. Pat. No. 7,705,685 to Ng et al., discloses an oscillator operating at very low voltage yet has a duty cycle set by a ratio of capacitors, with an S-R flip-flop latch that drives the oscillator inputs. 
     Low voltage bandgap voltage references utilize low voltage operation. As discussed in U.S. Pat. No. 5,982,201 to Brokaw et al., a low voltage current mirror based implementation shows a bipolar current mirror network, a resistor divider network, an output transistor that allows for operation with supply voltages of less than two junction voltage drops. 
     A low voltage oscillator can also have oscillation frequency selection. As discussed in U.S. Pat. No. 4,591,807 to Davis, describes a low power, fast startup oscillator circuit comprising of an amplifier, a current mirror, a feedback biasing means, and a tuned circuit for selecting the frequency of oscillation. 
     In these prior art embodiments, the solution to improve the operability of a low voltage bandgap circuit and oscillators utilized various alternative solutions. 
     It is desirable to provide a solution to address the disadvantages of the low voltage operation of a bandgap reference circuits and oscillators. 
     SUMMARY 
     A principal object of the present disclosure is to provide a voltage reference circuit which allows for operation for low power supply voltages. 
     A principal object of the present disclosure is to provide an oscillator circuit which allows for operation for low power supply voltages. 
     A principal object of the the present disclosure is to provide a voltage reference and oscillator circuit that is always “on.” 
     Another further object of the present disclosure is to provide a voltage reference circuit and oscillator that operate in the range of 1.1V to 3.6V. 
     Another further object of the present disclosure is provide a voltage reference and oscillator circuits that consumes low power and is voltage tolerant to higher power supply voltages. 
     Another further object of the present disclosure is to provide a voltage reference and oscillator circuit which simplifies the network with reduction of the number of current branches. 
     Another further object of the present disclosure is to provide a voltage reference and oscillator circuit which avoids stacking of more than two circuit elements allowing for lowering of the power supply voltage. 
     As such, a sub-bandgap reference circuit and oscillator circuit with an improved operation for low power supply voltages is disclosed. 
     In summary, a voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage comprising a current mirror function providing matching and sourcing network branches, a voltage generator network sourced from said current mirror providing a base-emitter voltage, a current drive function network electrically sourced from said current mirror function, and an output network function sourced from said current mirror providing a voltage reference output voltage. 
     In addition, a voltage reference circuit with improved operation at low voltage power supply is disclosed, where the voltage reference circuit between a power supply node and a ground node and configured for generating a reference voltage, and a current mirror function providing matching and sourcing network branches, a voltage generator-current mirror replica function network sourced from a current mirror providing a base-emitter voltage, a current drive function network electrically sourced from the current mirror function, and a current feedback sub-loop function, and an output network function sourced from the current mirror providing a voltage reference output voltage electrically coupled to the current feedback sub-loop function. 
     In addition, an oscillator circuit is disclosed. An oscillator circuit between a power supply node and a ground node and configured for generating an oscillating signal, and a current mirror function providing matching and sourcing network branches, a current drive function network electrically sourced from said current mirror function, an output network function sourced from said current mirror providing a capacitor oscillator output voltage, a first pull-up current source connected to said current drive function, a second pull-up current source connected to an output network function, and output network function, and lastly, a feedback loop network providing reset function. 
     In addition, a second embodiment of an oscillator is disclosed. An oscillator circuit between a power supply node and a ground node and configured for generating an oscillating signal, comprising a current mirror function providing matching and sourcing network branches, a current drive function network electrically sourced from the current mirror function, a first output network function sourced from the current mirror providing a first capacitor oscillator output voltage, a second output network function sourced from the current mirror providing a second capacitor oscillator output voltage, a first pull-up current source connected to said current drive function, a second pull-up current source connected to a first output network function, a third pull-up current source connected to a second output network function, a first capacitor providing charge storage and a first output network function, a second capacitor providing charge storage and a second output network function, a S-R flip-flop whose inputs are from said first output network function and the second output network function, a first feedback loop network connected to said first output of said S-R flip-flop providing reset function for a first switch, and a second feedback loop network connected to the second output of the S-R flip-flop providing reset function for a second switch. 
     In addition, a method of a voltage reference circuit is comprising the following steps: a first step of providing a voltage reference circuit between a power supply node and a ground node comprising a current mirror function, a voltage generator network, a current drive function network, and an output network function, a second step of providing matching and sourcing network branches from said current mirror function, a third step of providing a base-emitter voltage from said voltage generator network, and a fourth step of providing a voltage reference output voltage. 
     In addition, a method of an oscillator circuit is comprising the following steps: a first step providing an oscillator comprising of a power supply node, a ground node, a oscillating signal a current mirror function, a current drive function network, an output network function, a first pull-up current source, a second pull-up current source, a capacitor, and a feedback loop, a second step of providing matching and sourcing network branches using a current mirror function, a third step of sourcing a current from a current drive function network, a fourth step of sourcing current to a capacitor from an output network function, a fifth step of sourcing current from the first pull-up current source, a sixth step of sourcing current from said second pull-up current source, a seventh step of providing charge storage using a capacitor, and an eighth step of resetting the capacitor voltage providing a feedback loop network reset function. 
     Other advantages will be recognized by those of ordinary skill in the art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure and the corresponding advantages and features provided thereby will be best understood and appreciated upon review of the following detailed description of the disclosure, taken in conjunction with the following drawings, where like numerals represent like elements, in which: 
         FIG. 1  is a prior art example of a current mode sub-bandgap voltage reference circuit; 
         FIG. 2  is a prior art example circuit schematic of a single branch relaxation oscillator; 
         FIG. 3  is a circuit schematic of a low voltage reference in accordance with a first embodiment of the disclosure; 
         FIG. 4  is a circuit schematic of a low voltage reference in accordance with a second embodiment of the disclosure; 
         FIG. 5  is a circuit schematic of a low voltage reference in accordance with a third embodiment of the disclosure; 
         FIG. 6  is a circuit schematic of an oscillator in accordance with a fourth embodiment of the disclosure; 
         FIG. 7  is a circuit schematic of an oscillator in accordance with a fifth embodiment of the disclosure; 
         FIG. 8  is a method for providing a voltage reference circuit in accordance with an embodiment of the disclosure; and, 
         FIG. 9  is a method for providing an oscillator in accordance with an embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a prior art example of a current mode sub-bandgap voltage reference circuit. A low voltage power supply rail voltage V CC    10  and a ground rail  20  provides power to the circuit. The voltage reference output  30  is between the power supply voltage and the ground potential. The differential amplifier  40  supplies an output voltage to the gates of p-channel MOSFET P 1   50 A, P 2   50 B, and P 3   50 C. The p-channel MOSFET P 1   50 A drain is connected to the parallel combination of resistor R 1   60 , and diode  70 . The p-channel MOSFET P 2   50 B is connected to an array of diode elements  80  and a resistor R 3   90 . A second resistor R 2   95  is in parallel with the array of diodes  80  and resistor R 3   90 . The output reference voltage  30  is electrically coupled to the p-channel transistor P 3   50 C and resistor element R 4   97 . 
     In the prior art circuit of  FIG. 1 , the technology that is used only allows for a “stack” of one MOSFET gate-to-source voltage, VGS, and one MOSFET drain-to-source voltage, VDS for a low voltage rail. Furthermore, the power supply rail is as low as 1.1V, traditional bandgap voltage reference networks can not be used. Different implementations can not only use this network, but also operational amplifiers. Operational amplifier circuit topologies always need a at least one MOSFET drain-to-source voltage, VDS, for tail current generation, one MOSFET drain-to source voltage, VDS, for the V-mode comparison, and one MOSFET gate-to-source voltage VGS for the output PMOS. As a result, these structures are not suitable for a minimum power supply voltage of 1.1V. Operational amplifier circuits add significant increase in the number of circuit branches, leading to more complexity, more complications, and more power consumption. 
       FIG. 2  is a prior art example circuit schematic of a single branch relaxation oscillator. The circuit is powered by VDD  150 . A comparator  100  evaluates two incoming signals from the voltage on a capacitor VC  105  with respect to a reference voltage VREF  110 . The current reference IREF  120  provides current for the charging of the capacitor C  140 . A switch  130  is activated by a feedback loop from the COMPOUT (oscillator out signal)  160 . The switch  130  is in parallel with capacitor  140 . The comparator adds at least four branches to the circuit (e.g. a differential pair, a bias and an output stage). Additionally, it requires a voltage of a MOSFET gate-to-source voltage VGS, and two MOSFET drain-to-source voltages, 2 VDS, to operate properly. Hence, this limits the ability to use this circuit for sub-bandgap voltages, and low voltage applications. The generation of IREF  120  requires an extra operational amplifier to divide the voltage reference by a resistance of value R. Hence, the oscillator introduces a number of current branches increasing the complexity of the network. 
       FIG. 3  is a circuit schematic of a low voltage reference in accordance with a first embodiment of the disclosure. The voltage reference output value VREF  177  is between the power supply VDD  175  and ground rail VSS  176 . The current I 1  is supported by the p-channel MOSFET MP 1   180 A, which forms a current mirror with p-channel MOSFET MPOA  180 C. The current I 2  is supported by the p-channel MOSFET MP 2   180 B, and the current I 3  is supported by p-channel MOSFET MP 3   180 D. The MOSFET gate electrode of MPOA  180 C, MP 1   180 A, MP 2   180 B, and MP 3   180 D are all connected. Two branches are matched for the current using the mirror MP 1  and MP 2 . 
     The n-channel MOSFET M 1   188  establishes a VBE 1 , and whose gate voltage is designated as VGN. N-channel MOSFET  185  establishes a voltage VBEN. The first and second n-channel MOSFET transistors, M  188  and MN  185  are of different physical size. The transistor MN  185  is N times wider than M 1   188 . Given the MN  185  and M 1   188  operate in weak inversion, the bipolar transistor current-voltage law can be applied. The n-channel MOSFET MN  185  gate electrode is connected to the drain, and whose source is electrically connected to the ground rail  176 . Current I 2  flows into the resistor RPTAT  186  and RS  187 . The resistor RPTAT  186  is electrically connected to the MOSFET gate and drain of n-channel MOSFET MN  185 . The resistor RPTAT  186  establishes a proportional to absolute temperature (PTAT) for the voltage reference network. The n-channel MOSFET M 1   188  drain is electrically connected to the MOSFET gate of MNOA  189 . An output resistor ROUT  190  is connected to the output VREF  177 . 
     Two branches are matched for the current using the mirror MP 1   180 A and MP 2   180 B. Given that the identical resulting currents I 1  and I 2  are small, the current I 2  is not large enough to pull up the gate of transistor M 1   188  (e.g. gate voltage VGN). In this condition, transistor M 1188  does not lead to a high current drive. As consequence, the drain of transistor M 1   188  rises, and transistor MNOA  189  turns on, driving a significant amount of current through transistor MPOA  180 C; this leads to an increase in the current flow increasing the current flow in current I 1  and current I 2 . 
     This system thus reaches a steady, regulated state where VGN is VBE 1 . Whereas the transistor M 1   188  is a MOSFET transistor, it is labeled VBE 1  to imply bipolar-like operation in weak inversion (e.g. it is deliberately called VBE 1  to remind that M 1   188  and MN  185  operate in weak-inversion, so close to the behavior of NPN). As a result, the regulating system is reduced to the single branch {MNOA  189 , MPOA  180 C}. This operational state simplifies the solution, and is a significant reduction from prior art operational amplifier-type solutions. 
     The current I 2  can be expressed as
 
 I 2=( VBE 1( I 1)/ RS )+( VBE 1( I 1)− VBEN ( I 2− VBE 1( I 1)/ RS ))/ R PTAT  (1),
 
where we name VBE 1 (I 1 ): voltage on the gate-source of the transistor M 1   188  biased at the current I 1 . There is at this step an important approximation, where voltage VBE 1 (I 1 )/RS is neglected compared to current I 2 ,
 
 I 2− VBE 1( I 1)/ RS˜I 2= I 1
 
and finally the equation (1) can be written as
 
 I 2=( VBE 1( I 1)/ RS )+Δ VBE/R PTAT(2).
 
ΔVBE is the PTAT voltage, obtained from the approximation.
 
     With the mirroring function, the current I 2  is then copied into the current I 3  and injected into ROUT. This leads to the temperature compensated reference:
 
 V REF=( R OUT/ RS )· VBE 1+( R OUT/ R PTAT)Δ VBE  
 
     In the embodiment in this disclosure, there are typically twice less branches than for the prior art. Additionally, each branch does not require more voltage than the sum of the gate-to-source voltage and the drain-to-source voltage (VGS+VDS). 
     Alternative implementations are possible for the PTAT. The PTAT {M 1 , RPTAT, MN, RS} can include the stacking another NX-transistor in series with RS to change the temperature compensation, or use another type of transistors for M 1 , MN. Transistors M 1   188  and MN  185  can be bipolar junction transistors (BJT) instead of MOSFET transistors. 
       FIG. 4  is a circuit schematic of a low voltage reference in accordance with a second embodiment of the disclosure. The voltage reference output value VREF  177  is between the power supply VDD  175  and ground rail VSS  176 . The current is supported by the p-channel MOSFET MP 1   180 A, which forms a current mirror with p-channel MOSFET MPOA  180 C. Additionally, currents is supported by the p-channel MOSFET MP 2   180 B, and by p-channel MOSFET MP 3   180 D. In this embodiment, an additional transistor MOSFET MP 4   180 E is required for a “startup” circuit function. The MOSFET gate electrode of MPOA  180 C, MP 1   180 A, MP 2   180 B, MP 3   180 D, and MP 4   180 E are all connected. Two branches are matched for the current using the mirror MP 1  and MP 2 . 
     The n-channel MOSFET M 1   188  establishes a VBE 1 , and whose gate voltage is designated as VGN. N-channel MOSFET  185  establishes a voltage VBEN. The first and second n-channel MOSFET transistors, M 1   188  and MN  185  are of different physical size. The transistor MN  185  is N times wider than M 1   188 . Given the MN  185  and M 1   188  operate in weak inversion, the bipolar transistor current-voltage law can be applied. The n-channel MOSFET MN  185  gate electrode is connected to the drain, and whose source is electrically connected to the ground rail  176 . Current flows into the resistor RPTAT  186  and RS  187 . The resistor RPTAT  186  is electrically connected to the MOSFET gate and drain of n-channel MOSFET MN  185 . The resistor RPTAT  186  establishes a proportional to absolute temperature (PTAT) for the voltage reference network. The n-channel MOSFET M 1   188  drain is electrically connected to the MOSFET gate of MNOA  189 . An output resistor ROUT  190  is connected to the output VREF  177 . 
     A startup system comprises of p-channel MOSFET MP 4   180 E connected to power supply voltage VDD  175 . The startup system utilizes a p-channel MOSFET MSTART  190  whose gate is connected to the drain of MP 4   180 E, a device element RSTART  191 , whose source is connected to the power supply voltage VDD  175  and whose gate is connected to transistor M 1   188 . The startup system is added to force the electrical circuit to choose its stable, non-zero bias state (the other stable state being all the branches at I=0). As long as the system has not started, MP 4   180 E, that copies I 1  and I 2 , drives no current and device element RSTART  191  sinks the gate of the PMOS MSTART  190 . This PMOS  190  is “on” and charges the gate of MNOA (single-branch operational amplifier)  189 . Once the system is active, RSTART  191  is sized to deactivate MSTART  190 . A compensation capacitor CCOMP  192  is a compensation capacitor set on the highest impedance node to ensure the stability of both the main loop and the startup loop. In this embodiment, device element RSTART  191  can be other circuit elements that provide the same functional equivalence, such as a current source. The device element RSTART  191  can be an inherent resistor, parasitic resistor, and/or a current source. 
       FIG. 5  is a circuit schematic of a low voltage reference in accordance with a third embodiment of the disclosure. This third embodiment is aimed at avoiding the approximation done used in the prior equations of the first and second embodiments. It is worth noting that this previous approximation results in a non-ideal ΔVBE, and thus a degradation of the temperature behavior. The reference circuit of the  FIG. 3 , over all the corners (process, temperature), has a total spread of [−10%; +10%]. 
     The voltage reference output value VREF  177  is between the power supply VDD  175  and ground rail VSS  176 . The current is supported by the p-channel MOSFET MP 1   180 A, which forms a current mirror with p-channel MOSFET MPOA  180 C. Additionally, currents is supported by the p-channel MOSFET MP 2   180 B. P-channel MOSFET MP 3   180 D is connected to the power supply voltage, and whose drain is connected to VREF  177 , and output resistor ROUT  190 . The MOSFET gate electrode of MPOA  180 C, MP 1   180 A, MP 2   180 B, MP 3  are all connected. The gate of MOSFET MP 3  is connected to MOSFET MPSUBOA  195  and p-channel MOSFET  200 . The voltage on the gate of MPSUBOA is designated as VGSUBOA. P-channel MOSFET  200  drain and gate are connected to n-channel MOSFET MINV  205 . The MOSFET MINV  205  source is connected to ground  176 , and whose gate is connected to MP 2   180 B and a sense transistor MSENSE  185 B. The transistor MSENSE  185 B and MN  185 A form a current mirror network. 
     The n-channel MOSFET M 1   188  establishes a VBE 1 , and whose gate voltage is designated as VGN. N-channel MOSFET  185  A establishes a voltage VBEN. The first and second n-channel MOSFET transistors, M 1   188  and MN  185 A are of different physical size. The transistor MN  185 A is N times wider than M 1   188 . Given the MN  185 A and M 1   188  operate in weak inversion, the bipolar transistor current-voltage law can be applied. The n-channel MOSFET MN  185 A gate electrode is connected to the drain, and whose source is electrically connected to the ground rail  176 . Current flows into the resistor RPTAT  186  and RS  187 . The resistor RPTAT  186  is electrically connected to the MOSFET gate and drain of n-channel MOSFET MN  185 A. The resistor RPTAT  186  establishes a proportional to absolute temperature (PTAT) for the voltage reference network. The n-channel MOSFET M 1   188  drain is electrically connected to the MOSFET gate of MNOA  189 . An output resistor ROUT  190  is connected to the output VREF  177 . 
     So as to match exactly the currents in MN  185 A and in M 1   188  (and thus being able to create an exact ΔVBE), the current through MN  185 A is sensed by copying it (possibly with a scaling factor) using MSENSE  185 B. The result (IPTAT) is then compared to a replica of the current through M 1   188  (mirror MP 1   180 A, MP 2   180 B). If I(MN) is too low, then the gate of MINV  205  is pulled up, thus increasing the current through MPSUBOA  195  (sub-operational amplifier that makes a local loop). Eventually, the current I 2  becomes
 
 VBE 1( I 1)/ RS +( VBE 1( I 1)− VBEN ( I 1))/ R PTAT,
 
and this is the new current needing to be copied to the output. The results is
 
 V REF=( R OUT/ RS )· VBE 1+( R OUT/ R PTAT)Δ VBE  
 
     This time this is a true ΔVBE, and the total accuracy [−5%; +5%] reflects this second-order correction. However, it is worth noting that the two loops are competing. The sub-loop needs to be much faster than the main loop so that when MNOA slowly adjusts I 1 , then I 2  spontaneously reaches its value to match IPTAT with I 1 . If not, the sub-loop is an extra pole and degrades the stability of the main loop. Two solutions for the embodiment can be applied:
         (1) Increase the current budget in the sub-loop to increase its speed   (2) Use an external compensation for the main loop to make it much slower.
 
This embodiment, although intrinsically more precise, has less integration and standby advantages.
       

       FIG. 6  is a circuit schematic of an oscillator in accordance with a fourth embodiment of the disclosure. The circuit is sourced by power supply VDD  175 , and ground supply  176 . P-channel MOSFET transistor MPC  210 A, MPOA  210 B, and MPR  210 C form a current mirror source for the circuit. The transistor MPC  210 A provides current IP. The transistor MPR  210 C also provides current IP. The current source  220 A provides the current I 1 A to the gate of re-channel MOSFET device MNOA  232 . An additional capacitor element, in parallel with the MOSFET MNOA  232 , can be added between the gate of the n-channel MOSFET device MNOA  232  and ground connection  176 . The current source  220 B provides current IlB for the output of the oscillator COMPOUT (oscillator out). Transistor  210 C sources current IP to resistor element R  231  and n-channel MOSFET NA  230 . Transistor MPC  210 A sources a replica current IP to n-channel MOSFET NB  240  as well as the parallel configuration of capacitor  250  and switch  251 . A feedback loop  265  is electrically connecting the oscillator output  260  and activates the switch  251 . 
     Current sources can lead to significant variation. A very poor (300% variation) current source is used for the matched pull-ups I 1 A and I 1 B that have the same values. These currents are injected into matched NMOS NA  230  and NMOS NB  240 . The branch {MNOA, MPGA} acts as a single-branch operational amplifier as follows:
         For low current IP, the gate voltage on MOSFET NA  230 , VR, is low, and MOSFET NA  230  is not able to drive current source I 1 A  220 A. When the gate of MNOA  232  rises up, and transistor MNOA  232  adjusts the current in transistor MPOA  210 B, then a copy is formed on transistor MPR  210 C; this regulates the current IP such that the current in MOSFET NA  230  I(NA)=I 1 A. Thus, the current, IP=VGSNA(I 1 A)/R.   The current regulated by the transistor MPOA  210 B is also copied onto transistor MPC  210 A and injected into the capacitor C  250 . The current is equal to the derivative of the voltage on the capacitor with respect to time, (e.g. IP=dVC/dt) as well as also equal to the gate to source voltage of MOSFET NA  230  divided by the resistor R  231 , VGSNA(IP)/R.   The capacitor voltage, VC, increases, and eventually reaches the value VGSNA(IP) after the time t=T. This can be expressed as IP=VGSNA(IP)/R, also=C.VGSNA(IP)/T and thus T=RC. At this time, the transistor NB  240  is matched with transistor NA  230 , then transistor NB  240  carries the current I 1 B just transistor NA  230  carries current I 1 A. This condition corresponds to the tripping point for COMPOUT  260  The oscillator out COMPOUT  260  voltage value decrease can be used to generate a reset pulse to set capacitor voltageVC back to 0V, and restart a T-duration cycle.   Without the need of reference voltage, VREF, or any precise current, a switching frequency F=1/(RC) is obtained with the other process effects (transistors and bias currents) being cancelled assuming a good matching of the components.       

       FIG. 7  is a circuit schematic of an oscillator in accordance with a fifth embodiment of the disclosure. The circuit is sourced by power supply VDD  175 , and ground supply  176 . P-channel MOSFET transistor MPCB  210 BB, MPOA  210 B, and MPR  210 CC form a current mirror source for the circuit. The transistor MPC  210 BB and MPCC  210 CC provides current IP. The transistor MPR  210 C also provides current IP. The current source  220 A provides the current I 1 A to the gate of n-channel MOSFET device MNOA  232 . The current source  220 B provides current I 1 B for the output of the oscillator OUTB  260 B. Transistor  210 C sources current IP to resistor element R  231  and n-channel MOSFET NA  230 . Transistor MPCB  210 BB sources a replica current IP to the gate of the n-channel MOSFET NB  240 B as well as the parallel configuration of capacitor  250 B and switch  251 B. A feedback loop  265  B is electrically connected to QB of S-R flip-flop  270  and activates the switch  251 B. The current source  220 C provides current I 1 C for the output of the oscillator OUTC  260 C. Transistor MPCC  210 CC sources a replica current IP to the gate of the n-channel MOSFET NC  240 C as well as the parallel configuration of capacitor  250 C and switch  251 C. A feedback loop  265 C is electrically connected to Q of S-R flip-flop  270  and activates the switch  251 C. 
     In practice, and similarly to the relaxation oscillators ( FIG. 2 ), the C-branches are duplicated to cancel the frequency drift that would come from the reset-pulse duration. The final implementation is depicted in the  FIG. 7 . The generation of IP=VGSNA(I 1 )/R current reference. This current IP is copied twice onto two capacitor branches, to generate two saw-teeth voltage of capacitor B, VCB and voltage of capacitor C, VCC. When the voltage of capacitor B, VCB is ramped, then VCC is reset (stuck to 0V) and vice versa. When the voltage of capacitor B VCB reaches VGSNA(I 1 )/R, then the signal OUTB  260 B goes to a low state, and sets the latch: Q=1 sticks the capacitor voltage, VCB, to 0V, and QB=0 releases the capacitor voltage VCC that ramps up (e.g. rises). 
     A similar calculation shows that all the process dependences are cancelled (at exception of R, C) assuming that transistors NA  230 , NB  240 B, and NC  240 C are properly matched, as well as I 1 A  220 A, I 1 B  220 B, and I 1 C  220 C. 
     This invention can also profit from trimming, because R can be a temperature compensated polysilicon resistor, and C has a very low temperature coefficient. Post-trimming achievable total spread can be as low as [−5%; +5%]. 
       FIG. 8  is a method for providing a voltage reference circuit in accordance with an embodiment of the disclosure. A method for a voltage reference circuit consists of a first step ( 1 ) providing a voltage reference circuit between a power supply node and a ground node comprising a current mirror function, a voltage generator network, a current drive function network, and an output network function  300 , a second step ( 2 ) providing matching and sourcing network branches from the current mirror function  310 , a third step ( 3 ) providing a base-emitter voltage from the voltage generator network  320 , and a fourth step ( 4 ) providing a voltage reference output voltage  330 . 
       FIG. 9  is a method for providing an oscillator in accordance with an embodiment of the disclosure. The steps comprise of a first step ( 1 ) providing an oscillator comprising of a power supply node, a ground node, a current mirror function, a current drive function network, an output network function, a first pull-up current source, a second pull-up current source, a capacitor, and a feedback loop  350 , a second step ( 2 ) providing matching and sourcing network branches using a current mirror function  360 , a third step ( 3 ) sourcing a current from a current drive function network  370 , a fourth step ( 4 ) sourcing current to a capacitor from an output network function  380 , a fifth step ( 5 ) sourcing current from the first pull-up current source  390 , a sixth step ( 6 ) sourcing current from the second pull-up current source  400 , a seventh step ( 7 ) providing charge storage using a capacitor  410 , and the last step ( 8 ) resetting the capacitor voltage providing a feedback loop network reset function  420 . 
     Equivalent embodiments can utilize bipolar elements in place of the MOSFET elements in the circuit. An additional embodiment can utilize pnp bipolar transistors instead of the p-channel MOSFET devices. An additional embodiment can utilize npn bipolar junction transistors (BJT) instead of n-channel MOSFET devices. 
     Other advantages will be recognized by those of ordinary skill in the art. The above detailed description of the disclosure, and the examples described therein, has been presented for the purposes of illustration and description. While the principles of the disclosure have been described above in connection with a specific device, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the disclosure.

Technology Category: h