Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims the priority benefit of Taiwan application serial no. 93136441, filed on Nov. 26, 2004. All disclosure of the Taiwan application is incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a circuit board and processing method thereof. More particularly, the present invention relates to a circuit board and processing method thereof that can increase the wiring density of the circuit board. 
   2. Description of the Related Art 
   In today&#39;s information critical society, the market for electronic devices that facilitate information exchange expands at a tremendous pace. To increase the processing speed, provide more powerful functions, raise the level of integration and miniaturization and lower the selling price, chip packaging techniques are all aiming toward a higher degree of miniaturization and a higher degree of packaging density. In order to match this trend, the carrier in chip packaging, in particular, the ball grid array (BGA) and the pin grid array (PGA), has a higher integration level of wiring layout. Because a rigid substrate can provide a circuit layout with a higher wiring density and a higher pin count, it has become one of the most commonly used carriers in high-density chip packaging production. At present, the processes of fabricating a multi-layered rigid substrate having organic dielectric material layer can be categorized into the lamination method and the build-up method. 
     FIG. 1  is a schematic cross-sectional view of a conventional laminated circuit substrate. As shown in  FIG. 1 , the circuit substrate  100  mainly comprises a plurality of circuit layers  112 ,  114 ,  116 ,  118 , a plurality of dielectric layers  122 ,  124 ,  125 , two solder mask layers  132 ,  134  and a plurality of plated through holes (PTHs)  140 . The circuit layers  112 ˜ 118  and the dielectric layers  122 ˜ 126  are alternately laminated over each other. The two solder mask layers  132 ,  134  are disposed on the topmost circuit layer  112  and the bottommost circuit layer  118  respectively to expose a portion of each of the circuit layers  112  and  118  so that they can connect electrically with a chip or other carrier in a subsequent operation. The plated through holes  140  pass through the circuit layers  112 ˜ 118  and the dielectric layers  122 ˜ 126 , and electrically connect with the circuit layers  112 ˜ 118 . 
   The conventional method of forming the plated through holes  140  includes performing a mechanical drilling process to form a plurality of through holes passing through various layers after the circuit layers  112 ˜ 118  and the dielectric layers  122 ˜ 126  are pressed together. Thereafter, the through holes are filled using a conductive material. Since the drilling density in all circuit layers  112 ˜ 118  is identical, the circuit wiring area between the top circuit layer  112  and the bottom circuit layer  118  is reduced. Thus, some of the circuits is forced to route through the inner circuit layers  114  and  116  and damage the integrity of the circuit layers  114  and  116  for serving as a ground plane and a power plane. In other words, the electrical performance of the circuit board  100  is compromised. Similarly, too high a drilling density in the inner circuit layer  114  and  116  will also lead to the aforementioned problem. In addition, routing the circuit lines is increasingly difficult when the density of drilled holes in the laminated circuit board  100  is too high. In some cases, even the costlier built-up type of circuit board or a laminated circuit board with more layers is required. 
   SUMMARY OF THE INVENTION 
   Accordingly, at least one objective of the present invention is to provide a circuit board suitable for increasing wiring integration and lowering production cost. 
   At least a second objective of the present invention is to provide a circuit board process suitable for increasing the wiring integration and lowering production cost. 
   To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a circuit board fabrication process. First, a first laminated structure is provided. The first laminated structure has at least three first circuit layers and two first dielectric layers. The first circuit layers and the first dielectric layers are alternately laminated and any two adjacent first circuit layers have a first dielectric layer disposed between them. The first dielectric layers do not have a conductive via that passes through single first dielectric layer only. At least a first plated through hole (PTH) that passes through the first laminated structure is formed. Thereafter, a middle dielectric layer and a second laminated structure are laminated over the first laminated structure. The middle dielectric layer is disposed between the first laminated structure and the second laminated structure. Finally, at least a second plated through hole (PTH) that pass through the first laminated structure, the middle dielectric layer and the second laminated structure is formed. 
   The present invention also provides a circuit board comprising a first laminated structure, at least a first plated through hole (PTH), at least a second laminated structure, a middle dielectric layer and at least a second plated through hole (PTH). The firs laminated structure has at least three first circuit layers and at least two first dielectric layers. The first circuit layer and the first dielectric layer are alternately laminated and any two adjacent first circuit layers have a first dielectric layer disposed between them. The first dielectric layers do not have a conductive via that passes through single first dielectric layer only. The first plated through hole passes through the first laminated structure. The second laminated structure has at least a second circuit layer. The second laminated structure is laminated above the first laminated structure. The middle dielectric layer is disposed between the first laminated structure and the second laminated structure. The second plated through hole passes through the first laminated structure, the middle dielectric layer and the second laminated structure. 
   In brief, the process of fabricating the circuit board includes forming a portion of the laminated layer of the circuit board such as the alternately laminated three circuit layers and the two dielectric layers and the first plated through holes before pressing the remaining laminated layers together. Thereafter, a second plated through hole that passes through all the layers of the circuit board is formed. In other words, not all of the plated through holes passes through each circuit layer of the completed circuit board, thereby minimizing the waste in area utilization due to the presence of the plated through holes. Ultimately, the degree of integration of wiring layout is increased and overall production cost is reduced. 
   It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
       FIG. 1  is a schematic cross-sectional view of a conventional laminated circuit substrate. 
       FIGS. 2A through 2G  are schematic cross-sectional views showing the steps for fabricating a circuit board according to one preferred embodiment of the present invention. 
       FIGS. 3A and 3B  are schematic cross-sectional views showing the steps for fabricating a circuit board according to another preferred embodiment of the present invention. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     FIGS. 2A through 2G  are schematic cross-sectional views showing the steps for fabricating a circuit board according to one preferred embodiment of the present invention. As shown in  FIG. 2A , the process of fabricating a circuit board in the present invention includes providing a dielectric layer  212  and two conductive layers  222   a  and  224   a . The conductive layers  222   a  and  224   a  are disposed on each side of the dielectric layer  212 . The conductive layers  222   a  and  224   a  are copper foils disposed on the surfaces of the dielectric layer  212  by the lamination method, for example. 
   As shown in  FIG. 2B , photolithographic and etching techniques are applied to pattern the conductive layer  222   a  and  224   a  into a first circuit layer  222  and a second circuit layer  224  respectively. 
   As shown in  FIG. 2C , a dielectric layer  214  and a circuit layer  226  are sequentially laminated over the circuit layer  224 . The dielectric layer  214  is disposed between the circuit layer  226  and the circuit layer  224 . The dielectric layer  214  includes none of the conductive via that only passes through a single dielectric layer. Obviously, the circuit layer  226  is formed in the same way as the circuit layers  222  and  224 , that is, by patterning a conductive layer. In fact, all subsequently formed circuit layers are formed in a similar way. Thereafter, a through hole O 1  that passes through the circuit layers  222 ,  224 ,  226  and the dielectric layers  212 ,  214  are formed. The method of forming the through hole O 1  includes mechanical drilling, for example. 
   As shown in  FIG. 2D , a conductive material is deposited to fill the through hole O 1  and form a first plated through hole D 1 . The first plated through holes D 1  form a path for electrically connecting various circuit layers  222 ,  224  and  226 . 
   As shown in  FIG. 2E , a dielectric layer  216  and a circuit layer  228  are sequentially laminated over the circuit layer  222 . The dielectric layer  216  is disposed between the circuit layer  222  and the circuit layer  228 . The dielectric layer  216  includes none of the conductive via that only passes a single dielectric layer. Thereafter, at least a through hole O 2  that passes through the dielectric layers  212 ,  214 ,  216  and the circuit layers  222 ,  224 ,  226  and  228  is formed. The method of forming the through hole O 2  includes mechanical drilling, for example. 
   As shown in  FIG. 2F , a conductive material is deposited to fill the through hole O 2  and form a second plated through hole D 2 . Thus, the process of forming the circuit board is almost complete. 
   As shown in  FIG. 2G , solder mask layers  232  and  234  are formed on the top circuit layer  226  and the bottom circuit layer  228  respectively. The solder mask layers  232  and  234  expose a portion of each of the circuit layer  226  and  228  respectively, wherein the exposed portions of the circuit layer  226  and  228  form a plurality of bonding pads for electrical connection with a chip or other carriers in a subsequent operation. 
   As shown in  FIG. 2G , the circuit board  200  according to one preferred embodiment of the present invention essentially comprises a first laminated structure L 1 , a first plated through hole D 1 , a second laminated structure L 2 , a dielectric layer  216  and a second plated through hole D 2 . The first laminated structure L 1  is disposed above the second laminated structure L 2 . The first laminated structure L 1  comprises a lamination of circuit layers  222 ,  224 ,  226  and dielectric layers  212 ,  214 . The first plated through hole D 1  passes through the three circuit layers  222 ,  224  and  226  of the first laminated structure L 1 . The second laminated structure L 2  comprises a circuit layer  228 . The second plated through hole D 2  passes through the first laminated structure L 1  and the second laminated structure L 2 . The dielectric layers  212  and  214  have none of the conductive via that only passes through a single dielectric layer. 
   In addition, the dielectric layer  212  is fabricated using a mixture containing fiberglass and a resin so that the circuit board  200  is structurally reinforced. Moreover, the dielectric layers  214  and  216  are fabricated using a resin, for example. 
   Because the first plated through hole D 1  passes through the first laminated structure L 1 , the area labeled ‘B’ in  FIG. 2G  can be used for routing other circuits. Hence, the circuit board  200  can have a higher degree of wiring integration. 
     FIGS. 3A and 3B  are schematic cross-sectional views showing the steps for fabricating a circuit board according to another preferred embodiment of the present invention. As shown in  FIGS. 3A and 3B , the process of fabricating the circuit board according to the present embodiment includes providing a first laminated structure L 3  and a second laminated structure L 4 . 
   As shown in  FIG. 3A , the first laminated structure L 3  comprises three circuit layers  322 ,  324  and  326  and two dielectric layers  312  and  314  alternately laminated together. The dielectric layers  312  and  314  have none of the conductive via that only passes through a single dielectric layer. The first laminated structure L 3  has a plurality of first plated through holes D 3  that passes through the first laminated structure L 3 . 
   The second laminated structure L 4  comprises three circuit layers  328 ,  330  and  332  and two dielectric layers  318  and  320  alternately laminated together. The dielectric layers  318  and  320  have none of the conductive via that only passes through a single dielectric layer. The second laminated structure L 4  has a plurality of second plated through holes D 4  that passes through the second laminated structure L 4 . 
   Thereafter, the first laminated structure L 3  and the second laminated structure L 4  are laminated on each side of a dielectric layer  316 . The dielectric layer  316  has none of the conductive via that passes through a single dielectric layer. Then, at least one third plated through hole D 5  that passes through the first laminated structure L 3 , the second laminated structure L 4  and the dielectric layer  316  is formed. Up to this stage, the process of fabricating a circuit board  300  is almost complete. 
   As shown in  FIG. 3B , the circuit board  300  in another preferred embodiment of the present invention essentially comprises a first laminated structure L 3 , a dielectric layer  316 , a second laminated structure L 4  and a plurality of third plated through holes D 5 . The second laminated structure L 4  is disposed over the first laminated structure L 3 . The third plated through holes D 5  passes through the first laminated structure L 3 , the dielectric layer  316  and the second laminated structure L 4 . The first laminated structure L 3  and the second laminated structure L 4  have a fine structure identical to the aforementioned description. The dielectric layers  314  and  318  are fabricated using a mixture containing fiberglass and a resin so that the circuit board  300  is structurally reinforced. Moreover, the dielectric layers  312 ,  316  and  320  are fabricated using a resin, for example. Because the first plated through holes D 3  and the second plated through holes D 4  do not pass through the entire circuit board  300 , other areas of the circuit board  300  can be used for routing other circuits. Hence, the circuit board  300  can have a higher degree of wiring integration. 
   It should be noted that the four-layered circuit board and the six-layered circuit board in the aforementioned embodiments served as an illustration only and should not be used to limit the scope of the present invention. The present invention can be applied to a circuit board having five layers or seven and more layers. In addition, the spirit of the present invention is to form conductive material filled plated through holes in various laminated structures before laminating the laminated structures together. After that, through holes passing through the laminated structures are formed and then the through holes are filled to form plated through holes that pass through all the laminated structures. Therefore, there is no blind via between various neighboring circuit layers in the circuit board of the present invention. 
   In summary, because some of the plated through holes in the present invention do not pass through the entire circuit board, the emptied space can accommodate the connection between two neighboring circuit lines that carry an identical signal, or the routing for other circuits. Thus, the difficulty of routing circuit lines is reduced significantly and the wiring density can be increased. In some cases, a conventional package having a six-layered circuit board can even be replaced by a four-layered circuit board according to the present invention, thereby reducing the production time and saving production cost. Moreover, with an increase in the available space inside the circuit board, the length, width and separation of various circuit lines inside the circuit board can be flexibly adjusted on demand and the integrity of the ground plane and the power plane is increased. Ultimately, the circuit board can have a better electrical performance. 
   It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Technology Category: 4