Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefits of TW 103107793, filed Mar. 7, 2014, and TW 103124262, filed Jul. 15, 2014, both of which are fully incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an AC-powered LED light engine able to gradually gear up and down the number and current of excited LED sub-arrays in accordance with the voltage level of the rectified sinusoidal input voltage, and able to smoothly dim up and down the extrinsic LED sub-arrays via a shared current sense and modulation unit while keeping the quasi-sinusoidal line current waveform in good shape as well as maintaining almost the same high Power Factor (PF) and almost the same low Total Harmonic Distortion (THD) throughout the entire dimming range. 
     2. Description of the Prior Art 
     LED-based lighting devices are gradually becoming the preferred lighting equipment because of having a longer lifetime to reduce maintenance cost, and being less likely to get damaged than legacy lighting devices. 
     Technically, an AC sinusoidal input voltage would normally be rectified into a rectified sinusoidal one before coming into use for the DC-driven LEDs. In the vicinity of the beginning and end of each DC pulse cycle (aka “dead time”) where the input voltage is less than the combined forward voltage drop of the LEDs, the LEDs cannot be forward-biased to light up. The dead time in union with the conduction angle constitutes a full period of the rectified sinusoidal input voltage. A longer dead time translates to a smaller conduction angle, and hence a lower power factor because the line current is getting too thin to be similar in shape to the line voltage. 
     Traditional LED drivers would usually come along with the following application problems. The first problem would be the need for a more complicated and more expensive driving circuit consisting of an EMI filter, a bridge rectifier, a short-life Power Factor Corrector (PFC), etc. to drive LEDs. The second problem would be the flicker phenomenon due to no current flow through the LEDs during the dead time. The third problem would be a lower power factor exhibited by a low-power PFC with a loop current too weak to be precisely sensed to correctly shape the AC input current into a sinusoidal waveform. If the loop current appears too low to be precisely sensed by the current-sensing circuitry in the PFC stage, the PFC would fail to properly keep the line current in phase and in shape with the line voltage to achieve a high PF. Often mentioned in the same breath with the issue of a low PF is the issue of a high THD. The THD resulting from the discontinuous or jumping points in the AC input current waveform would have much to do with the existence of the dead time. 
     Besides, traditional phase-cut dimming, be it leading-edge or trailing-edge TRIAC dimming, would achieve dimming function by means of cutting off some conducting phase from the line current waveform, leading to significant deterioration of PF and THD. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to an AC-powered LED light engine able to gear up and down the number and current of excited LED sub-arrays in accordance with the voltage level of the rectified sinusoidal input voltage, more particularly, to an AC-powered LED light engine with a shared current sense and modulation unit to dim up and down the extrinsic LED sub-arrays without significantly deteriorating high PF and low THD. 
     In one aspect, the present invention discloses novel AC-powered LED light engines able to achieve a high PF and a low THD without using a traditional PFC by taking advantage of a divide-and-conquer strategy, i.e. divide an LED array with a relatively large forward voltage drop into several LED sub-arrays with relatively small forward voltage drops for the rectified sinusoidal input voltage to get over in sequence and parallel each LED sub-array with a corresponding normally closed bypass switch commanded by a corresponding three-terminal switch controller to steer the circuit operations and shuttling between three switch states: ON, REGULATION, and OFF in accordance with a current sense signal so as to shape the line current into a quasi-sinusoidal waveform. With no need for bulky, costly, and heavy magnetic components, short-life electrolytic capacitor, and EMI-causing fast switching in the traditional PFC, the disclosed AC-powered LED light engines facilitate a cost-effective, energy-efficient, and spick-and-span LED driver design while eliminating the weakest link (short-life electrolytic capacitor) in a chain (LED driver) and reducing the Total Cost of Ownership (TOC). The disclosed AC-powered LED light engines adopt a shared current sense and modulation unit connected to and shared by the switch controllers via a resistor as well as providing an original current sense signal for the switch controllers. The first terminal and the second terminal of each switch controller compare a scaled-down or original current sense signal and an original or scaled-up reference voltage to turn a corresponding bypass switch on via the third terminal when the scaled-down or original current sense signal is below the original or scaled-up reference voltage level (below reference), turn a corresponding bypass switch on and off via the third terminal when the scaled-down or original current sense signal is at the original or scaled-up reference voltage level (at reference), and turn a corresponding bypass switch off via the third terminal when the scaled-down or original current sense signal is above the original or scaled-up reference voltage level (above reference). 
     In another aspect, the present invention sheds light upon the feasibility and possibility of encapsulating any type of the disclosed LED light engines into an integrated circuit to reduce apparent parts count and manufacture cost. 
     In still another aspect, the present invention gives examples of illuminating apparatuses based on the disclosed LED light engines. On top of being TRIAC-dimmable via legacy phase-cut dimmers, the disclosed LED light engines could also be made PWM-, analog-, or rheostat-dimmable with the incorporation of an appropriate dimming circuit to modulate the average LED current. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing conceptions and their accompanying advantages of the present invention will get more readily appreciated after being better understood by referring to the following detailed description, in conjunction with the accompanying drawings, wherein: 
         FIG. 1  illustrates a block diagram of an illuminating apparatus  1  equipped with an AC-powered LED light engine  10  in accordance with an embodiment of the present invention; 
         FIG. 2  illustrates a block diagram of an illuminating apparatus  2  equipped with an AC-powered LED light engine  20  in accordance with another embodiment of the present invention; 
         FIG. 3  illustrates two waveforms showing the shaped LED current in response to the rectified sinusoidal input voltage as the disclosed AC-powered LED light engine gears up and down the LED sub-arrays G 1 , G 2 , G 3 , and G 4  within a period according to preferred embodiments of the present invention; 
         FIG. 4  illustrates a schematic diagram of an integrated circuit having the AC-powered LED light engine  10  shown in  FIG. 1  according to an embodiment of the present invention; 
         FIG. 5  gives an example of the illuminating apparatus  1  equipped with the AC-powered LED light engine  10  shown in  FIG. 1 ; 
         FIG. 6  gives an example of an illuminating apparatus  6  equipped with an AC-powered LED light engine  30  in accordance with preferred embodiments of the present invention; 
         FIG. 7  illustrates a superordinate schematic diagram of all the disclosed illuminating apparatuses in collocation with PWM-, analog-, and rheostat-dimming schemes on the basis of a shared current sense and modulation unit  16  in the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The detailed explanation of the present invention is described as follows. The preferred embodiments are presented for purposes of illustrations and description, and not intended to limit the spirit and scope of the present invention. 
       FIG. 1  illustrates a block diagram of an illuminating apparatus  1  equipped with an AC-powered LED light engine  10  designed to gear up from the bottom up and gear down from the top down the extrinsic LED sub-arrays (G 1 , G 2 , G 3 , and G 4 ) in accordance with an embodiment of the present invention. The illuminating apparatus  1  comprises a rectifier  100  coupled to an AC mains, an AC-powered LED light engine  10 , and a shared current sense and modulation unit  16 , and is loaded up with a plurality of extrinsic LED sub-arrays (G 1 , G 2 , G 3 , and G 4 ). 
     The AC-powered LED light engine  10  is coupled between the rectifier  100  and the extrinsic LED sub-arrays (G 1 , G 2 , G 3 , and G 4 ), and has a normally closed current regulator  120  coupled to the rectifier  100  via its high-side terminal and used to regulate the highest LED current level near the rectified sinusoidal input voltage peak, a plurality of normally closed bypass switches (S 1 , S 2 , and S 3 ) each connected in parallel with a corresponding LED sub-array except for the bottommost LED sub-array G 4  and shuttling between three switch states: ON, REGULATION, and OFF according to a corresponding current sense signal, and a switch controller module  14  having a plurality of switch controllers ( 140 ,  142 , and  144 ), each having a first terminal, a second terminal, and a third terminal, coupled between the shared current sense and modulation unit  16  via its first terminal and a corresponding bypass switch via its third terminal as a feedback network and taking control of the three switch states. A plurality of resistors r 0 , r 4 , and r 8 , connected between the high-side terminal of the shared current sense and modulation unit  16  and the first terminals of the switch controllers ( 140 ,  142 , and  144 ), in pairs with a plurality of resistors r 2 , r 6 , and r 10 , connected between the first and the second terminals of the switch controllers ( 140 ,  142 , and  144 ), form a bank of voltage dividers to scale down the current sense signal. In one embodiment, the configuration of the normally closed bypass switches each can also connected in parallel with a corresponding LED sub-array except for the topmost LED sub-array. 
     The rectifier  100  could be but will not be limited to a full-wave or a half-wave rectifier. Each of the normally closed bypass switches S 1 , S 2 , and S 3  could be but will not be limited to an enhancement-mode or a depletion-mode n-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in collocation with an adequate switch controller. Each of the switch controllers  140 ,  142 , and  144  could be but will not be limited to a Bipolar Junction Transistor (BJT)-based, a Shunt Regulator (SR)-based, or a Photo Coupler (PC)-based gate-driving circuitry in control of the three switch states. The switch controllers  140 ,  142 , and  144 , assumed for simplification, not for limitation, to have exactly the same reference voltage V REF  used for comparison with scaled-down current sense signals, respectively rule over the three switch states of the normally closed bypass switches S 1 , S 2 , and S 3  according to the sensed voltage across the shared current sense and modulation unit  16 . 
     Please cross-refer to  FIGS. 1 and 3 . To simplify the description, the voltage divider consisting of resistors R 1  and R 2  in series would firstly be neglected, i.e. R 1  is replaced with an open circuit having a resistance of infinity and R 2  is replaced with a short circuit having a resistance of zero. During the first half of the period, the rectified sinusoidal input voltage goes up from zero to its peak. When the rising input voltage (vi) is still less than the forward voltage drop of the bottommost LED sub-array G 4  (0≦vi&lt;V G4 ), no current flows into the circuit and this interval (0≦t&lt;t 0 ) is commonly called the dead time. When the rising input voltage (vi) has been high enough to forward-bias the extrinsic LED sub-array G 4  but is still less than the combined forward voltage drop of the extrinsic LED sub-arrays G 3  and G 4  (V G4 ≦vi&lt;V G3+G4 ), a constant current I 1 , flowing downstream through the normally closed current regulator  120 , the normally closed bypass switch S 1 , the normally closed bypass switch S 2 , the current-regulating bypass switch S 3 , and the current sense and modulation unit  16 , lights up the extrinsic LED sub-array G 4  during the interval of (t 0 ≦t&lt;t 1 ). 
     The constant current I 1  would be regulated by the bypass switch S 3  via the switch controller  144  in accordance with the design formula 
                   I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10         =     V   REF       ,         
i.e.
 
               r   ⁢           ⁢   10     =       r   ⁢           ⁢   8           I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16       V   REF       -   1             
and
 
               I   ⁢           ⁢   1     ⁢           =         V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10             .           
If the constant current I 1  goes above its preset current level
 
                 V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10             ,         
the switch controller  144  turns off the bypass switch S 3  for the constant current I 1  to go down to
 
                 V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10             .         
If the constant current I 1  goes below its preset current level
 
                 V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10             ,         
the switch controller  144  turns on the bypass switch S 3  for the constant current I 1  to go up to
 
                 V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10             .         
That is to say, the switch controller  144  detects a scaled-down, at-reference current sense signal
 
               (         I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16   ×           ⁢   r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10         =     V   REF       )     ,         
so the bypass switch S 3  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-array G 4  at a constant current level I 1  preset with a scaled-down resistance of the shared current sense and modulation unit  16 
 
               (       R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10           )     ,         
wherein R 16  stands for the resistance of the current sense and modulation unit  16 . The switch controllers  142  and  140  each detect a scaled-down, below-reference current sense signal
 
               (           I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2         &lt;       I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6         &lt;     V   REF       =       I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10           )     ,         
so the normally closed bypass switches S 1  and S 2  remain in their ON state to short out the extrinsic LED sub-arrays G 1  and G 2 . Detecting a below-reference current sense signal via an unshown current-sensing resistor, the current regulator  120  stays in its ON state and acts like a normally closed switch.
 
     When the rising input voltage (vi) has been high enough to forward-bias the combined LED sub-arrays G 3  and G 4  but is still less than the combined forward voltage drop of the extrinsic LED sub-arrays G 2 , G 3 , and G 4  (V G3+G4 ≦vi&lt;V G2+G3+G4 ), a constant current I 2  lights up the extrinsic LED sub-arrays G 3  and G 4  during the interval of (t 1 ≦t&lt;t 2 ). The switch controller  144  detects a scaled-down, above-reference current sense signal 
               (         I   ⁢           ⁢   2   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10         &gt;     V   REF       )     ,         
so the bypass switch S 3  stays in its OFF state to free up the extrinsic LED sub-array G 3 . The constant current I 2  would be regulated by the bypass switch S 2  via the switch controller  142  in accordance with the design formula
 
                   I   ⁢           ⁢   2   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6         =     V   REF       ,         
i.e.
 
               r   ⁢           ⁢   6     =       r   ⁢           ⁢   4           I   ⁢           ⁢   2   ×   R   ⁢           ⁢   16       V   REF       -   1             
and
 
               I   ⁢           ⁢   2     =         V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   4       r   ⁢           ⁢   6             .           
That is to say, the switch controller  142  detects a scaled-down, at-reference current sense signal
 
               (         I   ⁢           ⁢   2   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6         =     V   REF       )     ,         
so the bypass switch S 2  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-arrays G 3  and G 4  at a constant current level I 2  preset with a scaled-down resistance of the shared current sense and modulation unit
 
             16   ⁢       (       R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   4       r   ⁢           ⁢   6           )     .           
The switch controller  140  detects a scaled-down, below-reference current sense signal
 
               (         I   ⁢           ⁢   2   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2         &lt;     V   REF       )     ,         
so the normally closed bypass switch S 1  remains in its ON state to short out the extrinsic LED sub-array G 1 . Detecting a below-reference current sense signal via an unshown current-sensing resistor, the current regulator  120  stays in its ON state and acts like a normally closed switch.
 
     When the rising input voltage (vi) has been high enough to forward-bias the combined LED sub-arrays G 2 , G 3 , and G 4  but is still less than the combined forward voltage drop of the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  (V G2+G3+G4 ≦vi&lt;V G1+G2+G3+G4 ), a constant current I 3  lights up the extrinsic LED sub-arrays G 2 , G 3 , and G 4  during the interval of (t 2 ≦t&lt;t 3 ). The constant current I 3  would be regulated by the bypass switch S 1  via the switch controller  140  in accordance with the design formula 
                   I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2         =     V   REF       ,         
i.e.
 
               r   ⁢           ⁢   2     =       r   ⁢           ⁢   0           I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16       V   REF       -   1             
and
 
               I   ⁢           ⁢   3     =         V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   0       r   ⁢           ⁢   2             .           
That is to say, the switch controller  140  detects a scaled-down, at-reference current sense signal
 
               (         I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2         =     V   REF       )     ,         
so the bypass switch S 1  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-arrays G 2 , G 3 , and G 4  at a constant current level I 3  preset with a scaled-down resistance of the shared current sense and modulation unit  16 
 
               (       R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   0       r   ⁢           ⁢   2           )     .         
The switch controllers  142  and  144  each detect a scaled-down, above-reference current sense signal
 
               (           I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10         &gt;       I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6         &gt;     V   REF       =       I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2           )     ,         
so the bypass switches S 2  and S 3  stay in their OFF state to free up the extrinsic LED sub-arrays G 2  and G 3 . Detecting a below-reference current sense signal via an unshown current-sensing resistor, the current regulator  120  stays in its ON state and acts like a normally closed switch.
 
     When the input voltage (vi) is high enough to forward-bias all of the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  (V G1+G2+G3+G4 ≦vi), a constant current I 4  preset with an unshown current-sensing resistor in the normally closed current regulator  120  lights up all the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  in the vicinity of the peak of the rectified sinusoidal input voltage (t 3 ≦t&lt;t 3′ ). The aforementioned constant current levels are ranked in the order of 
                 I   ⁢           ⁢   4     &gt;     I   ⁢           ⁢   3       =           V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   0       r   ⁢           ⁢   2             &gt;     I   ⁢           ⁢   2       =           V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   4       r   ⁢           ⁢   6             &gt;     I   ⁢           ⁢   1       =       V   REF         R   ⁢           ⁢   16       1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10                       
for an active current regulator or bypass switch to deactivate its downstream bypass switches, calling for the resistance sequence of r 10 &gt;r 6 &gt;r 2 , assuming the resistance equalization of r 8 =r 4 =r 0 . In this way, the AC-powered LED light engine  10  gears up each extrinsic LED sub-array from the bottom up.
 
     During the second half of the period, the rectified sinusoidal input voltage goes down from its peak to zero. When the falling input voltage (vi) is still high enough to forward-bias the combined LED sub-arrays G 2 , G 3 , and G 4  but has been less than the combined forward voltage drop of the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  (V G2+G3+G4 ≦vi&lt;V G1+G2+G3+G4 ), the switch controller  140  detects a scaled-down, at-reference current sense signal 
               (         I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2         =     V   REF       )     ,         
so the bypass switch S 1  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-arrays G 2 , G 3 , and G 4  at the preset constant current level I 3  during the interval of (t 3′ ≦t&lt;t 2′ ). The switch controllers  142  and  144  each detect a scaled-down above-reference current sense signal
 
               (           I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   10               ⁢       r   ⁢           ⁢   8     +     r   ⁢           ⁢   10           &gt;       I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6         &gt;     V   REF       =       I   ⁢           ⁢   3   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2           )     ,         
so the bypass switches S 2  and S 3  stay in their OFF state to free up the extrinsic LED sub-arrays G 2  and G 3 . Detecting a below-reference current sense signal via an unshown current-sensing resistor, the current regulator  120  stays in its ON state and acts like a normally closed switch.
 
     When the falling input voltage (vi) is still high enough to forward-bias the combined LED sub-arrays G 3  and G 4  but has been less than the combined forward voltage drop of the extrinsic LED sub-arrays G 2 , G 3 , and G 4  (V G3+G4 ≦vi&lt;V G2+G3+G4 ), the switch controller  144  detects a scaled-down, above-reference current sense signal 
               (         I   ⁢           ⁢   2   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10         &gt;     V   REF       )     ,         
so the bypass switch S 3  stays in its OFF state to free up the extrinsic LED sub-array G 3  during the interval of (t 2′ ≦t&lt;t 1′ ). The switch controller  142  detects a scaled-down, at-reference current sense signal
 
               (         I   ⁢           ⁢   2   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6         =     V   REF       )     ,         
so the bypass switch S 2  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-arrays G 3  and G 4  at the preset constant current level I 2 . The switch controller  140  detects a scaled-down, below-reference current sense signal
 
               (         I   ⁢           ⁢   2   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2         &lt;     V   REF       )     ,         
so the normally closed bypass switch S 1  goes back to its ON state to short out the extrinsic LED sub-array G 1 . Detecting a below-reference current sense signal via an unshown current-sensing resistor, the current regulator  120  stays in its ON state and acts like a normally closed switch.
 
     When the falling input voltage (vi) is still high enough to forward-bias the extrinsic LED sub-array G 4  but has been less than the combined forward voltage drop of the extrinsic LED sub-arrays G 3  and G 4  (V G4 ≦vi&lt;V G3+G4 ), the switch controller  144  detects a scaled-down, at-reference current sense signal 
               (         I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10         =     V   REF       )     ,         
so the bypass switch S 3  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-array G 4  at the preset constant current level I 1  during the interval of (t 1′ ≦t&lt;t 0′ ). The switch controllers  140  and  142  each detect a scaled-down, below-reference current sense signal
 
               (           I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2         &lt;       I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6         &lt;     V   REF       =       I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16   ×   r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10           )     ,         
so the normally closed bypass switches S 1  and S 2  go back to their ON state to short out the extrinsic LED sub-arrays G 1  and G 2 . Detecting a below-reference current sense signal via an unshown current-sensing resistor, the current regulator  120  stays in its ON state and acts like a normally closed switch. In this way, the AC-powered LED light engine  10  gears down each extrinsic LED sub-array from the top down till all of the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  go out. The number of the aforementioned constant current levels for the AC-powered LED light engine  10 , translating to the number of the bypass switches and the switch controllers devised to draw a quasi-sinusoidal line current waveform from the AC sinusoidal line voltage source, could be arbitrarily chosen with a design tradeoff between performance and cost.
 
       FIG. 2  illustrates a block diagram of an illuminating apparatus  2  equipped with an AC-powered LED light engine  20  designed to gear up from the bottom up and gear down from the top down the extrinsic LED sub-arrays (G 1 , G 2 , G 3 , and G 4 ) in accordance with an embodiment of the present invention. The illuminating apparatus  2  comprises a rectifier  100  coupled to an AC mains, an AC-powered LED light engine  20 , and a shared current sense and modulation unit  16 , and is loaded up with a plurality of extrinsic LED sub-arrays (G 1 , G 2 , G 3 , and G 4 ). 
     The AC-powered LED light engine  20  is coupled between the rectifier  100  and the extrinsic LED sub-arrays (G 1 , G 2 , G 3 , and G 4 ), and has a normally closed current regulator (such as the current-regulating switch S 0 ) coupled to the rectifier  100  via its high-side terminal and used to regulate the highest LED current level near the rectified sinusoidal input voltage peak, a plurality of normally closed bypass switches (S 1 , S 2 , and S 3 ) each connected in parallel with a corresponding LED sub-array except for the bottommost LED sub-array G 4  and shuttling between the three switch states according to a corresponding current sense signal, and a switch controller module  15  having a plurality of switch controllers ( 150 ,  152 ,  154 , and  156 ) each coupled between the shared current sense and modulation unit  16  and a corresponding current-regulating switch or bypass switch as a feedback network and taking control of the three switch states. A plurality of anti-clamping resistors Rx 1 , Rx 2 , and Rx 3 , connected between the high-side terminal of the shared current sense and modulation unit  16  and the first terminals of the switch controllers ( 140 ,  142 , and  144 ), would prevent the terminal voltage across the shared current sense and modulation unit  16  from being clamped at lower reference voltage levels so as not to miss out on higher current regulation levels. 
     The normally closed bypass switches S 1 , S 2 , and S 3  as well as the switch controllers  150 ,  152 ,  154 , and  156  in  FIG. 2  could be identical to those in  FIG. 1 . The switch controllers  150 ,  152 ,  154 , and  156 , respectively ruling over the three switch states of the current-regulating switch S 0  as well as the normally closed bypass switches S 1 , S 2 , and S 3  in accordance with the sensed voltage across the shared current sense and modulation unit  16 , are assumed for simplification, not for limitation, to have exactly the same reference voltage V REF . The scaled-up reference voltages actually used for comparison with current sense signals are set up by means of connecting the first terminal of a lower switch controller to the second terminal of an upper switch controller via an optional Zener diode (Zd 1 , Zd 2 , and Zd 3 ) to make non-integer multiples possible, and could be ranked in the following order: V 150A,REF =4V REF +V Zd1 +V Zd3 &gt;V 152A,REF =3V REF +V Zd2 +V Zd3 &gt;V 154A,REF =2V REF +V Zd3 &gt;V 156A,REF =V REF , wherein V Zd1 , V Zd2 , and V Zd3  are breakdown voltages of the optional Zener diodes Zd 1 , Zd 2 , and Zd 3 . 
     Please cross-refer to  FIGS. 2 and 3 . During the first half of the period, the rectified sinusoidal input voltage goes up from zero to its peak. When the rising input voltage (vi) is still less than the forward voltage drop of the bottommost LED sub-array G 4  (0≦vi&lt;V G4 ), no current flows into the circuit and this interval (0≦t&lt;t 0 ) is referred to as the dead time. When the rising input voltage (vi) has been high enough to forward-bias the extrinsic LED sub-array G 4  but is still less than the combined forward voltage drop of the extrinsic LED sub-arrays G 3  and G 4  (V G4 ≦vi&lt;V G3+G4 ), a constant current I 1  lights up the extrinsic LED sub-array G 4  during the interval of (t 0 ≦t&lt;t 1 ). 
     The constant current I 1  would be regulated by the bypass switch S 3  via the switch controller  156  in accordance with the design formula 
                 I   ⁢           ⁢   1   ×   R   ⁢           ⁢   16     =     V   REF       ,         i   .   e   .           ⁢   I     ⁢           ⁢   1     =         V   REF       R   ⁢           ⁢   16       .             
That is to say, the switch controller  156  detects an at-reference current sense signal (I 1 ×R 16 =V REF ), so the bypass switch S 3  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-array G 4  at a constant current level I 1  preset with the resistance R 16  of the shared current sense and modulation unit
 
               (       I   ⁢           ⁢   1     =       V   REF       R   ⁢           ⁢   16         )     .         
The switch controllers  154 ,  152 , and  150  each detect a below-reference current sense signal (I 1 ×R 16 =V REF &lt;2V REF +V Zd3 &lt;3V REF +V Zd2 +V Zd3 &lt;4V REF +V Zd1 +V Zd2 +V Zd3 ), so the current-regulating switch S 0  as well as the normally closed bypass switches S 1  and S 2  remain in their ON state to short out the extrinsic LED sub-arrays G 1  and G 2 .
 
     When the rising input voltage (vi) has been high enough to forward-bias the combined LED sub-arrays G 3  and G 4  but is still less than the combined forward voltage drop of the extrinsic LED sub-arrays G 2 , G 3 , and G 4  (V G3+G4 ≦vi&lt;V G2+G3+G4 ), a constant current I 2  lights up the extrinsic LED sub-arrays G 3  and G 4  during the interval of (t 1 ≦t&lt;t 2 ). The switch controller  156  detects an above-reference current sense signal (I 2 ×R 16 &gt;V REF ), so the bypass switch S 3  stays in its OFF state to free up the extrinsic LED sub-array G 3 . The constant current I 2  would be regulated by the bypass switch S 2  via the switch controller  154  in accordance with the design formula I 2 ×R 16 =2V REF +V Zd3 , i.e. 
               I   ⁢           ⁢   2     =           2   ⁢           ⁢     V   REF       +     V     Zd   ⁢           ⁢   3           R   ⁢           ⁢   16       .           
That is to say, the switch controller  154  detects an at-reference current sense signal (I 2 ×R 16 =2V REF +V Zd3 ), so the bypass switch S 2  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-arrays G 3  and G 4  at a constant current level I 2  preset with two times the reference voltage 2V REF  plus the optional
 
                 V     Zd   ⁢           ⁢   3       (       I   ⁢           ⁢   2     =         2   ⁢           ⁢     V   REF       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   3           R   ⁢           ⁢   16         )     .         
The switch controllers  150  and  152  each detect a below-reference current sense signal (I 2 ×R 16 =2V REF +V Zd3 &lt;3V REF +V Zd2 +V Zd3 &lt;4V REF +V Zd1 +V Zd2 +V Zd3 ), so the current-regulating switch S 0  and the normally closed bypass switch S 1  remain in their ON state to short out the extrinsic LED sub-array G 1 .
 
     When the rising input voltage (vi) has been high enough to forward-bias the combined LED sub-arrays G 2 , G 3 , and G 4  but is still less than the combined forward voltage drop of the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  (V G2+G3+G4 ≦vi&lt;V G1+G2+G3+G4 ), a constant current I 3  lights up the extrinsic LED sub-arrays G 2 , G 3 , and G 4  during the interval of (t 2 ≦t&lt;t 3 ). The constant current I 3  would be regulated by the bypass switch S 1  via the switch controller  152  in accordance with the design formula I 3 ×R 16 =3V REF +V Zd2 +V Zd3 , i.e. 
               I   ⁢           ⁢   3     =           3   ⁢           ⁢     V   REF       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   2       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   3           R   ⁢           ⁢   16       .           
That is to say, the switch controller  152  detects an at-reference current sense signal (I 3 ×R 16 =3V REF +V Zd2 +V Zd3 ), so the bypass switch S 1  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-arrays G 2 , G 3 , and G 4  at a constant current level I 3  preset with three times the reference voltage 3V REF  plus the optional V Zd2  and
 
                 V     Z   ⁢           ⁢   d   ⁢           ⁢   3       (       I   ⁢           ⁢   3     =         3   ⁢           ⁢     V   REF       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   2       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   3           R   ⁢           ⁢   16         )     .         
The switch controllers  156  and  154  each detect an above-reference current sense signal (I 3 ×R 16 =3V REF +V Zd2 +V Zd3 &gt;2V REF +V Zd3 &gt;V REF ), so the bypass switches S 2  and S 3  stay in their OFF state to free up the extrinsic LED sub-arrays G 2  and G 3 . The switch controller  150  detects a below-reference current sense signal (I 3 ×R 16 =3V REF +V Zd2 +V Zd3 &lt;4V REF +V Zd1 +V Zd2 +V Zd3 ), so the current-regulating switch S 0  stays in its ON state and acts like a normally closed switch.
 
     When the input voltage (vi) is high enough to forward-bias all of the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  (V G1+G2+G3+G4 ≦vi), a constant current I 4  lights up all the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  during the interval of (t 3 ≦t&lt;t 3′ ). The constant current I 4  would be regulated by the current-regulating switch S 0  via the switch controller  150  in accordance with the design formula I 4 ×R 16 =4V REF +V Zd1 +V Zd2 +V Zd3 , i.e. 
               I   ⁢           ⁢   4     =           4   ⁢           ⁢     V   REF       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   1       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   2       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   3           R   ⁢           ⁢   16       .           
That is to say, the switch controller  150  detects an at-reference current sense signal (I 4 ×R 16 =4V REF ++V Zd1 +V Zd2 +V Zd3 ), so the current-regulating switch S 0  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-arrays G 1 , G 2 , G 3 , and G 4  at a constant current level I 4  preset with four times the reference voltage 4V REF  plus the optional and V Zd1 , V Zd2 , and V Zd3 
 
               (       I   ⁢           ⁢   4     =         4   ⁢           ⁢     V   REF       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   1       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   2       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   3           R   ⁢           ⁢   16         )     .         
The switch controllers  152 ,  154 , and  156  each detect an above-reference current sense signal (I 4 ×R 16 =4V REF +V Zd1 +V Zd2 +V Zd3 &gt;3V REF +V Zd2 +V Zd3 &gt;2V REF +V Zd3 &gt;V REF ), so the bypass switches S 1 , S 2 , and S 3  stay in their OFF state to free up the extrinsic LED sub-arrays G 1 , G 2 , and G 3 . In this way, the AC-powered LED light engine  20  gears up each extrinsic LED sub-array from the bottom up.
 
     During the second half of the period, the rectified sinusoidal input voltage goes down from its peak to zero. When the falling input voltage (vi) is still high enough to forward-bias the combined LED sub-arrays G 2 , G 3 , and G 4  but has been less than the combined forward voltage drop of the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  (V G2+G3+G4 ≦vi&lt;V G1+G2+G3+G4 ), the switch controller  152  detects an at-reference current sense signal (I 3 ×R 16 =3V REF +V Zd2 +V Zd3 ), so the bypass switch S 1  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-arrays G 2 , G 3 , and G 4  at the preset constant current level I 3  during the interval of (t 3′ ≦t&lt;t 2′ ). The switch controllers  154  and  156  each detect an above-reference current sense signal (I 3 ×R 16 =3V REF +V Zd2 +V Zd3 &gt;2V REF +V Zd3 &gt;V REF ), so the bypass switches S 2  and S 3  stay in their OFF state to free up the extrinsic LED sub-arrays G 2  and G 3 . The switch controller  150  detects a below-reference current sense signal (I 3 ×R 16 =3V REF +V Zd2 +V Zd3 &lt;4V REF +V Zd1 +V Zd2 +V Zd3 ), so the current-regulating switch S 0  stays in its ON state and acts like a normally closed switch. 
     When the falling input voltage (vi) is still high enough to forward-bias the combined LED sub-arrays G 3  and G 4  but has been less than the combined forward voltage drop of the extrinsic LED sub-arrays G 2 , G 3 , and G 4  (V G3+G4 ≦vi&lt;V G2+G3+G4 ), the switch controller  156  detects an above-reference current sense signal (I 2 ×R 16 &gt;V REF ), so the bypass switch S 3  stays in its OFF state to free up the LED sub-array G 3  during the interval of (t 2′ ≦t&lt;t 1′ ). The switch controller  154  detects an at-reference current sense signal (I 2 ×R 16 =2V REF +V Zd3 ), so the bypass switch S 2  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-arrays G 3  and G 4  at the preset constant current level I 2 . The switch controllers  150  and  152  each detect a below-reference current sense signal (I 2 ×R 16 =2V REF +V Zd3 &lt;3V REF +V Zd2 +V Zd3 &lt;4V REF +V Zd1 +V Zd2 +V Zd3 ), so the current-regulating switch S 0  remains in its ON state, and the normally closed bypass switch S 1  goes back to their ON state to short out the extrinsic LED sub-array G 1 . 
     When the falling input voltage (vi) is still high enough to forward-bias the LED sub-array G 4  but has been less than the combined forward voltage drop of the extrinsic LED sub-arrays G 3  and G 4  (V G4 ≦vi&lt;V G3+G4 ), the switch controller  156  detects an at-reference current sense signal (I 1 ×R 16 =V REF ), so the bypass switch S 3  gets into its REGULATION state to regulate the LED current flowing through the downstream LED sub-array G 4  at the preset constant current level I 1  during the interval of (t 1′ ≦t&lt;t 0′ ). The switch controllers  150 ,  152 , and  154  each detect a below-reference current sense signal (I 1 ×R 16 =V REF &lt;2V REF +V Zd3 &lt;3V REF +V Zd2 +V Zd3 &lt;4V REF +V Zd1 +V Zd2 +V Zd3 ), so the current-regulating switch S 0  remains in its ON state, and the normally closed bypass switches S 1  and S 2  go back to their ON state to short out the extrinsic LED sub-arrays G 1  and G 2 . 
     In this way, the AC-powered LED light engine  20  gears down each extrinsic LED sub-array from the top down till all of the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  go out. The number of the aforementioned constant current levels for the AC-powered LED light engine  20 , translating to the number of the bypass switches and the switch controllers devised to draw a quasi-sinusoidal line current waveform from the AC sinusoidal line voltage source, could be arbitrarily chosen with a design tradeoff between performance and cost. It is worth mentioning that the AC-powered LED light engines  10  and  20  could proportionally dim up and down each extrinsic LED sub-array by means of varying the resistance R 16  (unshown) of the shared current sense and modulation unit  16 , keeping the quasi-sinusoidal line current waveform in good shape as well as maintaining almost the same high Power Factor (PF) and almost the same low Total Harmonic Distortion (THD) throughout the entire dimming range. 
     In this embodiment, the current-regulating switch S 0  controlled by the switch controller  150  can be replaced by the current regulator  120  shown in  FIG. 1 . Similarly, the current-regulating switch S 0  controlled by the switch controller  150  can replace the current regulator  120  employed in other embodiments. The major difference between the current-regulating switch S 0  and the current regulator  120  would be: the highest current level I 4  regulated by the current-regulating switch S 0 , acting in concert with other bypass switches S 1 , S 2 , and S 3 , would be in proportion to the lower current levels I 3 , I 2 , and I 1 , while the highest current level I 4  regulated by the current regulator  120 , standing alone for current regulation, would be out of proportion to the lower current levels I 3 , I 2 , and I 1 . 
       FIG. 4  illustrates an integrated circuit having the AC-powered LED light engine  10  shown in  FIG. 1  in accordance with an embodiment of the present invention. As is shown in  FIG. 4 , the integrated circuit  12  has six pins A, B, C, D, E, and F, three bypass switches S 1 , S 2 , and S 3 , as well as three switch controllers  140 ,  142 , and  144 . The shared current sense and modulation unit  16  is placed outside the integrated circuit  12  to make the current levels programmable to circuit designers of the illuminating apparatus. 
     The integrated circuit  12  has its pin A coupled to the low-side terminal of the current regulator  120 , the anode of the LED sub-array G 1 , and the third terminal of the bypass switch S 1 , its pin B coupled to the output terminal of the voltage divider (the node between the resistors R 1  and R 2 ), the low-side terminals of the resistors r 2 , r 6 , and r 10 , as well as the second terminals of the switch controllers  140 ,  142 , and  144 , its pin C coupled to the second terminal of the bypass switch S 1 , the cathode of the LED sub-array G 1 , and the anode of the LED sub-array G 2 , its pin D coupled to the second terminal of the bypass switch S 2 , the third terminal of the bypass switch S 3 , the cathode of the LED sub-array G 2 , and the anode of the LED sub-array G 3 , its pin E coupled to the second terminal of the bypass switch S 3 , the cathode of the LED sub-array G 3 , and the anode of the LED sub-array G 4 , and its pin F coupled to the high-side terminals of the resistors r 0 , r 4 , and r 8 , the high-side terminal of the shared current sense and modulation unit  16 , and the cathode of the LED sub-array G 4 . 
     In this embodiment, the integrated circuit  12  encapsulates the AC-powered LED light engine  10  shown in  FIG. 1 . It goes without saying any type of the AC-powered LED light engines based on the spirit and scope of the present invention can be encapsulated in the form of an integrated circuit to reduce the apparent parts count and enable a more compact circuit design. Moreover, a plurality of resulting integrated circuits of the same type could be connected in series to extend the voltage rating or in parallel to extend the current rating, depending on practical requirements for given applications. 
       FIG. 5  gives an example of an illuminating apparatus  5  equipped with the an AC-powered LED light engine  10  shown in  FIG. 1 , wherein the AC-powered LED light engine  10  is coupled between the rectifier  100  and the extrinsic LED sub-arrays (G 1 , G 2 , G 3 , and G 4 ). 
     The illuminating apparatus  5  comprises a rectifier  100  coupled to an AC mains, an AC-powered LED light engine  10 , a plurality of extrinsic LED sub-arrays (G 1 , G 2 , G 3 , and G 4 ), and a shared current sense and modulation unit  16 . The AC-powered LED light engine  10  comprises a normally closed current regulator  120 , a plurality of normally closed bypass switches (S 1 , S 2 , and S 3 ) each connected in parallel with a corresponding LED sub-array except for the bottommost LED sub-array G 4  and shuttling between the three switch states according to a corresponding current sense signal, and a switch controller module  114  having a plurality of switch controllers B 1 , B 2 , and B 3  each coupled between the shared current sense and modulation unit  16  and a corresponding bypass switch as a feedback network and taking control of the three switch states. Each of the normally closed bypass switches S 1 , S 2 , and S 3  is a depletion-mode n-channel MOSFET in collocation with an adequate switch controller. Each of the switch controllers is a BJT-based gate-driving circuit, comprising a corresponding gate-discharging resistor (r 7 , r 9 , and r 11 ) for turning on a corresponding bypass switch (S 1 , S 2 , and S 3 ) as well as a corresponding voltage-comparing BJT (B 1 , B 2 , and B 3 ), a corresponding voltage-dividing resistor pair (r 0  and r 2 , r 4  and r 6 , as well as r 8  and r 10 ), a corresponding voltage-dividing resistor (r 1 , r 3 , and r 5 ), and a corresponding voltage-clamping Zener diode (Z 1 , Z 2 , and Z 3 ) for turning off a corresponding bypass switch (S 1 , S 2 , and S 3 ), in control of the three switch states. 
     In  FIG. 5 , the first part of the voltage-dividing resistor pair (r 0 , r 4 , and r 8 ) is connected between the high-side terminal of the shared current sense and modulation unit  16  and the bases of the voltage-comparing BJTs (B 1 , B 2 , and B 3 ), while the second part of the voltage-dividing resistor pair (r 2 , r 6 , and r 10 ) could be either connected between the bases of the voltage-comparing BJTs (B 1 , B 2 , and B 3 ) and ground or between the bases and the emitters of the voltage-comparing BJTs (B 1 , B 2 , and B 3 ), as is shown in  FIG. 1 . 
     In this embodiment, the normally closed current regulator  120  comprises a current-regulating switch M 1  (an enhancement-mode n-channel MOSFET), a gate-charging resistor Ra, a voltage-comparing BJT B 0 , and a current-sensing resistor Rb. The current-regulating switch M 1  has its drain coupled to the rectifier  100  (the high-side terminal of the gate-charging resistor Ra), its gate coupled to the low-side terminal of the gate-charging resistor Ra (the collector of the voltage-comparing BJT B 0 ), and its source coupled to the high-side terminal of the current-sensing resistor Rb (the base of the voltage-comparing BJT B 0 ). 
     It is crystal clear that a depletion-mode n-channel MOSFET is essentially a normally closed switch. Only the current-regulating switch M 1  needs to get initialized as a normally closed switch after the random power-on of the illuminating apparatus  5 . More specifically, in the initial state, M 1 &#39;s intrinsic gate-source capacitor could rapidly be charged up to above its threshold voltage level via a corresponding gate-charging resistor Ra so as to make its channel normally closed once the rectified sinusoidal input voltage could forward-bias the bottommost LED sub-array G 4 . 
     Based on the comparison between an applied gate-source voltage V GS  and a negative threshold voltage V th , a depletion-mode n-channel MOSFET would operate in its ON state (V GS &gt;V th ) due to discharging of its intrinsic gate-source capacitor via a corresponding gate-discharging resistor when a corresponding below-reference current sense signal turns a corresponding voltage-comparing BJT off, in its REGULATION state (V GS =V th ) due to discharging and charging of its intrinsic gate-source capacitor via a corresponding gate-discharging resistor as well as a corresponding voltage-comparing BJT, a corresponding voltage-dividing resistor, and a corresponding voltage-clamping Zener diode when a corresponding at-reference current sense signal turns a corresponding voltage-comparing BJT off and on, or in its OFF state (V GS &lt;V th ) due to charging of its intrinsic gate-source capacitor via a corresponding voltage-comparing BJT, a corresponding voltage-dividing resistor, and a corresponding voltage-clamping Zener diode when a corresponding above-reference current sense signal turns a corresponding voltage-comparing BJT on. As such, all of the normally closed bypass switches S 1 , S 2 , and S 3  would shuttle between the three switch states except for the normally closed current-regulating switch M 1  excluding its OFF state from the three switch states. 
     A voltage divider, comprising resistors R 1  and R 2  in series, adds a scaled-down sample of the rectified sinusoidal input voltage 
             (         v   i     ×   R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2         )         
to the emitters of the voltage-comparing BJTs B 1 , B 2 , and B 3  so that scaled-down current sense signals would be compared with a sinusoidal-modulated reference voltage
 
               V   REF     +         v   i     ×   R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2               
rather than a fixed reference voltage V REF  to further smooth a stepping current waveform into a more sinusoidal one for getting an even higher PF and an even lower THD. In this embodiment, a flicker-suppressing capacitor (Cg 1 , Cg 2 , Cg 3 , and Cg 4 ), coupled in parallel with a corresponding LED sub-array and functioning as an auxiliary supply of LED current, and a corresponding charge-retaining diode (D 1 , D 2 , D 3 , and D 4 ), coupled between a corresponding normally closed bypass switch and a corresponding flicker-suppressing capacitor to prevent capacitor charge from being consumed by other unintended circuit components instead of a corresponding LED sub-array, are also incorporated to improve the flicker issue without any detriment to the high PF and low THD because each flicker-suppressing capacitor is merely charged up to a corresponding LED sub-array forward voltage drop and would not set up an even higher voltage barrier for the rectified sinusoidal input voltage to get over. The aforementioned flicker-suppressing capacitors, applicable to any embodiment of the present invention, could be implemented with short-life electrolytic capacitors or, even better, an equivalent M×N matrix of non-electrolytic capacitors, such as ceramic capacitors, tantalum capacitors, or solid-state capacitors for a much longer lifespan, where the rows number M and the columns number N are associated with the voltage rating and the current rating, respectively.
 
       FIG. 6  illustrates a schematic diagram of an illuminating apparatus  6  equipped with the AC-powered LED light engine  30 . The illuminating apparatus  6  comprises a rectifier  100  coupled to an AC mains, an AC-powered LED light engine  30 , a string of extrinsic LED sub-arrays (G 1 , G 2 , G 3 , and G 4 ), as well as a shared current sense and modulation unit  16  for providing current sense signals. The AC-powered LED light engine  30  comprises a normally closed current regulator  120 ′, a string of normally closed bypass switches (S 1 , S 2 , and S 3 ) each connected in parallel with a corresponding LED sub-array except for the bottommost LED sub-array G 4  and shuttling between the three switch states according to a corresponding current sense signal, and a switch controller module  215  having a plurality of switch controllers (B 1 , B 2 , and B 3 ) each coupled between the shared current sense and modulation unit  16  and a corresponding bypass switch as a feedback network and taking control of the three switch states. 
     Each of the normally closed bypass switches S 1 , S 2 , and S 3  is an enhancement-mode n-channel MOSFET in collocation with an adequate switch controller. The gate-charging resistors (Ra, Ra 1 , Ra 2 , and Ra 3 ) are used to charge the intrinsic gate-source capacitors of the current regulator  120  as well as the bypass switches S 1 , S 2 , and S 3  up to above their threshold voltage so as to initialize them as normally closed switches after the random power-on of the illuminating apparatus  6 . Understandable from that of  FIG. 5 , the initialization process of  FIG. 5  would not be repeated herein. Each of the switch controllers is a BJT-based gate-driving circuit, comprising a corresponding gate-charging resistor (Ra 1 , Ra 2 , and Ra 3 ) for turning on a corresponding bypass switch (S 1 , S 2 , and S 3 ) as well as a corresponding voltage-comparing device (BJTs B 1 , B 2 , and B 3  in conjunction with optional Zener diodes Zd 1  and Zd 2 ), a corresponding anti-clamping resistor (Rx 1 , Rx 2 , and Rx 3 ), a corresponding current-limiting resistor (Rg 1 , Rg 2 , and Rg 3 ), and a corresponding gate-discharging diode (Dg 1 , Dg 2 , and Dg 3 ) for turning off a corresponding bypass switch (S 1 , S 2 , and S 3 ), in control of the three switch states. In this embodiment, the normally closed current regulator  120 ′ comprises a current-regulating switch M 1  (an enhancement-mode n-channel MOSFET), a gate-charging resistor Ra, a shunt regulator X, and a current-sensing resistor Rx. Obviously, a BJT B 0  and a shunt regulator X both used for voltage comparison in the present invention are interchangeable. 
     Based on the comparison between an applied gate-source voltage V GS  and a positive threshold voltage V th , an enhancement-mode n-channel MOSFET would operate in its ON state (V GS &gt;V th ) due to charging of its intrinsic gate-source capacitor via a corresponding gate-charging resistor when a corresponding below-reference current sense signal turns a corresponding voltage-comparing BJT off, in its REGULATION state (V GS =V th ) due to charging and discharging of its intrinsic gate-source capacitor via a corresponding gate-charging resistor as well as a corresponding voltage-comparing device, a corresponding anti-clamping resistor, a corresponding current-limiting resistor, and a corresponding gate-discharging diode when a corresponding at-reference current sense signal turns a corresponding voltage-comparing BJT off and on, or in its OFF state (V GS &lt;V th ) due to discharging of its intrinsic gate-source capacitor via a corresponding voltage-comparing device, a corresponding anti-clamping resistor, a corresponding current-limiting resistor, and a corresponding gate-discharging diode when a corresponding above-reference current sense signal turns a corresponding voltage-comparing BJT on. As such, all of the normally closed bypass switches S 1 , S 2 , and S 3  would shuttle between the three switch states except for the normally closed current-regulating switch M 1  excluding its OFF state from the three switch states. 
     A voltage divider, comprising resistors R 1  and R 2  in series, adds a scaled-down sample of the rectified sinusoidal input voltage 
             (         v   i     ×   R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2         )         
to the emitter of the bottommost voltage-comparing BJT B 3  so that current sense signals would be compared with a sinusoidal-modulated reference voltage
 
             (         V   REF     +         v   i     ×   R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,       2   ⁢           ⁢     V   REF       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   2       +         v   i     ×   R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,           
and
 
                 3   ⁢           ⁢     V   REF       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   1       +     V     Z   ⁢           ⁢   d   ⁢           ⁢   2       +         v   i     ×   R   ⁢           ⁢   2         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           )         
rather than a fixed reference voltage (V REF , 2V REF +V Zd2 , and 3V REF +V Zd1 +V Zd2 ) to further smooth a stepping current waveform into a more sinusoidal one for getting an even higher PF and an even lower THD. The flicker-suppressing capacitor (Cg 1 , Cg 2 , Cg 3 , and Cg 4 ) and the corresponding charge-retaining diode (D 1 , D 2 , D 3 , and D 4 ) are the same as those in  FIG. 5 , and therefore do not need any elaboration.
 
       FIG. 7  illustrates a superordinate schematic diagram of all the disclosed illuminating apparatuses in collocation with PWM-, analog-, and rheostat-dimming schemes in accordance with preferred embodiments of the present invention. To simplify the description, the voltage divider comprising resistors R 1  and R 2  in series would again be overlooked and an LED light engine  10  employing a bank of voltage dividers would simultaneously be assumed. 
     When it comes to the PWM-dimming scheme, the shared current sense and modulation unit  16  would consist of a fixed resistor Rc (providing a current sense signal for switch controllers), a fixed resistor Rd (superimposing a scaled-down analog-dimming signal on the current sense signal), a voltage buffer (preventing the extracted analog-dimming signal against loading effect), and an RC low-pass filter (extracting the average voltage from the inputted PWM-dimming signal). Equating the PWM-dimmed, scaled-down current sense signals and the reference voltage V REF  would lead to the following equations: 
             {                 [       I   ⁢           ⁢   1   ×     (     Rc   //   Rd     )       +         V   AVE     ×   Rc       Rd   +   Rc         ]     ×       r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10           =     V   REF                     [       I   ⁢           ⁢   2   ×     (     Rc   //   Rd     )       +         V   AVE     ×   Rc       Rd   +   Rc         ]     ×       r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6           =     V   REF                     [       I   ⁢           ⁢   3   ×     (     Rc   //   Rd     )       +         V   AVE     ×   Rc       Rd   +   Rc         ]     ×       r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2           =     V   REF             ⇒     {               I   ⁢           ⁢   1     =       1     Rc   //   Rd       ×     [         (     1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10         )     ×     V   REF       -         V   AVE     ×   Rc       Rd   +   Rc         ]                     I   ⁢           ⁢   2     =       1     Rc   //   Rd       ×     [         (     1   +       r   ⁢           ⁢   4       r   ⁢           ⁢   6         )     ×     V   REF       -         V   AVE     ×   Rc       Rd   +   Rc         ]                     I   ⁢           ⁢   3     =       1     Rc   //   Rd       ×     [         (     1   +       r   ⁢           ⁢   0       r   ⁢           ⁢   2         )     ×     V   REF       -         V   AVE     ×   Rc       Rd   +   Rc         ]               ,               
where V AVE  is the extracted average voltage of the inputted PWM-dimming signal in proportion to the PWM duty ratio. By adjusting the PWM duty ratio, the average current flowing through the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  to emit light could correspondingly be modulated because all the current levels I 1 , I 2 , and I 3  would decrease with an increased average voltage V AVE , so the resulting light apparatus would be PWM-dimmable.
 
     When it comes to the analog-dimming scheme, the shared current sense and modulation unit  16  would retain the fixed resistor Rc and the fixed resistor Rd. The voltage buffer and the RC low-pass filter, both becoming unnecessary, could be removed. Equating the analog-dimmed, scaled-down current sense signals and the reference voltage V REF  would lead to the following equations: 
             {                 [       I   ⁢           ⁢   1   ×     (     Rc   //   Rd     )       +         V   ANALOG     ×   Rc       Rd   +   Rc         ]     ×       r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10           =     V   REF                     [       I   ⁢           ⁢   2   ×     (     Rc   //   Rd     )       +         V   ANALOG     ×   Rc       Rd   +   Rc         ]     ×       r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6           =     V   REF                     [       I   ⁢           ⁢   3   ×     (     Rc   //   Rd     )       +         V   ANALOG     ×   Rc       Rd   +   Rc         ]     ×       r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2           =     V   REF             ⇒     {               I   ⁢           ⁢   1     =       1     Rc   //   Rd       ×     [         (     1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10         )     ×     V   REF       -         V   ANALOG     ×   Rc       Rd   +   Rc         ]                     I   ⁢           ⁢   2     =       1     Rc   //   Rd       ×     [         (     1   +       r   ⁢           ⁢   4       r   ⁢           ⁢   6         )     ×     V   REF       -         V   ANALOG     ×   Rc       Rd   +   Rc         ]                     I   ⁢           ⁢   3     =       1     Rc   //   Rd       ×     [         (     1   +       r   ⁢           ⁢   0       r   ⁢           ⁢   2         )     ×     V   REF       -         V   ANALOG     ×   Rc       Rd   +   Rc         ]               ,               
where V ANALOG  is the inputted analog-dimming signal level. By adjusting the analog-dimming signal level, the average current flowing through the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  to emit light could correspondingly be modulated because all the current levels I 1 , I 2 , and I 3  would decrease with an increased analog-dimming signal level V ANALOG , so the resulting light apparatus would be analog-dimmable.
 
     When it comes to the rheostat-dimming scheme, the shared current sense and modulation unit  16  would merely take on a rheostat Rc. The fixed resistor Rd, the voltage buffer, and the RC low-pass filter, having nothing to do, could all be removed. Equating the rheostat-dimmed, scaled-down current sense signals and the reference voltage V REF  would lead to the following equations: 
             {                   (     I   ⁢           ⁢   1   ×   Rc     )     )     ×       r   ⁢           ⁢   10         r   ⁢           ⁢   8     +     r   ⁢           ⁢   10           =     V   REF                       (     I   ⁢           ⁢   2   ×   Rc     )     )     ×       r   ⁢           ⁢   6         r   ⁢           ⁢   4     +     r   ⁢           ⁢   6           =     V   REF                       (     I   ⁢           ⁢   3   ×   Rc     )     )     ×       r   ⁢           ⁢   2         r   ⁢           ⁢   0     +     r   ⁢           ⁢   2           =     V   REF             ⇒     {               I   ⁢           ⁢   1     =       1     R   ⁢           ⁢   c       ×     (     1   +       r   ⁢           ⁢   8       r   ⁢           ⁢   10         )     ×     V   REF                     I   ⁢           ⁢   2     =       1     R   ⁢           ⁢   c       ×     (     1   +       r   ⁢           ⁢   4       r   ⁢           ⁢   6         )     ×     V   REF                     I   ⁢           ⁢   3     =       1     R   ⁢           ⁢   c       ×     (     1   +       r   ⁢           ⁢   0       r   ⁢           ⁢   2         )     ×     V   REF               ,               
where R 16  is the variable resistance. By adjusting the variable resistance Rc, the average current flowing through the extrinsic LED sub-arrays G 1 , G 2 , G 3 , and G 4  to emit light could correspondingly be modulated because all the current levels I 1 , I 2 , and I 3  would decrease with an increased variable resistance Rc, so the resulting light apparatus would be rheostat-dimmable. Not only can the aforementioned variable resistance come from a single rheostat acting as the one and only variable resistor in a narrow sense, but it can also result from a series, a parallel, or a mixed combination of a number of current-sensing resistors under the control of a bank of electronic or mechanic switches in a broad sense.
 
     To sum up, all the preferred embodiments of the present invention could gear up and down the number and current of excited LED sub-arrays according to the voltage level of the rectified sinusoidal input voltage for obtaining a high PF and a low THD. If further equipped with the option of disclosed flicker-suppressing capacitors, the disclosed AC-powered LED light engines could improve the flicker phenomenon while maintaining exactly the same high PF and exactly the same low THD without any deterioration. In addition to being TRIAC-dimmable via legacy phase-cut dimmers, the disclosed AC-powered LED light engines are also PWM-, analog-, and rheostat-dimmable, broadening the scope of dimming applications. 
     While the present invention is susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the present invention should not be limited to the disclosed particular forms, but to the contrary, should cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims.

Technology Category: h