Patent Document

BACKGROUND OF THE INVENTION 
     This invention relates to programmable logic devices (PLDs), and, more particularly, to specialized processing blocks which may be included in such devices. 
     As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof. 
     One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations. 
     For example, a PLD sold by Altera Corporation, of San Jose, Calif., under the name STRATIX® II includes DSP blocks, each of which includes four 18-by-18 multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-by-18 multipliers, but also as four smaller multipliers, or as one larger (36-by-36) multiplier. In addition, one 18-by-18 complex multiplication (which decomposes into two 18-by-18 multiplication operations for each of the real and imaginary parts) can be performed. 
     Such a DSP block may be configured as a finite impulse response (FIR) filter, with 18-bit data and coefficients. Each block may be used to perform the summation of four 18-by-18 multiplications to form a 4-tap sub-block of a longer FIR filter. 
     Many types of FIR filters may be encountered. Two of those types are an interpolation FIR filter—in which the number of samples is increased by a factor of n by inserting (“interpolating”) n−1 samples between adjacent samples—and a decimation FIR filter—in which the number of samples is decreased by a factor of n by removing n−1 out of every n samples. A DSP block that may be configured as different types of filters, including an interpolation FIR filter and a decimation FIR filter, is shown in copending, commonly-assigned U.S. patent application Ser. No. 11/447,370, filed Jun. 5, 2006, which is hereby incorporated by reference herein in its entirety. 
     One application of interpolation and decimation filters is in wireless communication systems based on TDD (time division duplexing) mode, such as GSM, 3G LTE and TD-CDMA. In those systems, a filter may need to work some of the time in decimation mode, and some of the time in interpolation mode. For example, such systems include digital up-converters (DUCs), which include interpolation filters, and digital down-converters (DDCs), which include decimation filters. Separate filters can be included for the DUCs and the DDCs, but the DUCs and the DDCs never operate at the same time, meaning that at any one time, half of the filters would be idle. Therefore, there would be efficiencies, in terms of the number of multipliers used, if a single filter could operate in either interpolation mode or decimation mode on demand, changing modes in real time “on the fly.” However, it has heretofore been difficult to create a filter which can be switched between the two modes during run time, and at the same time uses as few multipliers as possible. 
     It would be desirable to be able to provide, in a PLD, a specialized processing block, such as a DSP block, that can be configured as a FIR filter capable of performing both interpolation and decimation and of changing modes in real time. 
     SUMMARY OF THE INVENTION 
     The present invention relates to specialized processing blocks for PLDs wherein a specialized processing block can be configured as a FIR filter capable of performing both interpolation and decimation, and of changing modes in real time. 
     As discussed in more detail below, it is apparent from the mathematics of interpolation filters and decimation filters that various coefficients, samples and products thereof are reused at least once. Therefore, by introducing appropriate delays and buffers, and selecting them when appropriate, a filter that can operate on demand as either an interpolation filter or a decimation filter can be provided. Because coefficients, samples and products may be reused, the filter can use as few as two multipliers. 
     Therefore, in accordance with the present invention, there is provided a FIR filter structure for selectively operating in one of an interpolation filter mode and decimation filter mode. The FIR filter structure includes a number of multipliers N, where N can be expressed as follows:
 
 N=INT[CT /( snSH )]+1 when MOD [ CT /( snSH )]≠0, and
 
 N=CT /( snSH ) when MOD [ CT /( snSH )]=0
 
where:
         C=the number of channels,   T=the number of taps,   s=1 for an asymmetric filter,   s=2 for a symmetric filter,   n=the interpolation/decimation factor,   S=timesharing factor (i.e., the number of clock cycles available to the system to process one input or output sample,   H is factor that represents whether the case is a fullband case (H=1) or a halfband case (H=2) in which all odd coefficients with the exception of the middle coefficient are zero,
 
MOD [ x]=x−INT[x ], and
   INT[x] is the largest integer in x.
 
This can be as few as one multiplier. Each of the N multipliers has a sample input and a coefficient input, and the coefficient input cycles through a plurality of coefficients. At least one circuit adds outputs of the multipliers to each other, with a respective selectable delay located at least one of (a) before, and (b) after, each of the adding circuits. The FIR filter structure to allow selection between an interpolation filter mode and a decimation filter mode during operation of said FIR filter structure, with the selection including selection of at least one of the respective selectable delays.
       

    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
         FIG. 1  is a schematic representation of a 5-tap FIR filter adapted to perform interpolation or decimation; 
         FIGS. 2 and 3  are representations of calculations needed to perform interpolation, and of intermediate values to be stored; 
         FIG. 4  is a block diagram of a FIR filter adapted to perform interpolation in accordance with  FIGS. 2 and 3 ; 
         FIG. 5  is a representation of calculations needed to perform decimation, and of intermediate values to be stored; 
         FIG. 6  is a block diagram of a FIR filter adapted to perform decimation in accordance with  FIG. 5 ; 
         FIG. 7  is a block diagram of a first preferred embodiment of a FIR filter in accordance with the present invention adapted to perform both interpolation and decimation; 
         FIG. 8  is a representation of calculations needed to perform interpolation and decimation in an 11-tap FIR filter; 
         FIG. 9  is a block diagram of a second preferred embodiment of a FIR filter in accordance with the present invention adapted to perform both interpolation and decimation; 
         FIG. 10  is a simplified block diagram of an illustrative system employing a programmable logic device incorporating the present invention; 
         FIG. 11  is a cross-sectional view of a magnetic data storage medium encoded with a set of machine-executable instructions for performing the method according to the present invention; and 
         FIG. 12  is a cross-sectional view of an optically readable data storage medium encoded with a set of machine executable instructions for performing the method according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A FIR filter calculates a weighted sum of a finite number of inputs, summing a number of multiplication results, where each multiplication is between a sample and a coefficient. Each such multiplication may be referred to as a “tap.” Mathematically, a FIR filter may be described as: 
               Y   k     =         ∑     i   =   0       Taps   -   1       ⁢           ⁢     ci   ·   Sk       -   i           
where Y k  is the kth output term, c i  is the ith coefficient, s k−i  is the (k−i)th sample, and Taps is the number of taps in the filter.
 
     In the case of interpolation, one inserts zeroes between the input samples before filtering. In the case, for example, of interpolation by two, one can fill all odd-numbered samples with zeroes, which introduces a regular pattern of zeroes into the equations. The same circuitry that is used as an ordinary FIR filter could be used to perform the interpolation filtering, but it would be idle half the time as the inputs would be zero, which would be wasteful. For interpolation by a higher factor n, the circuitry would be idle for (n−1)/n cycles. 
     Similarly in the case of decimation, no calculation is necessary on n−1 of every n cycles. Again, ordinary FIR filter circuitry could be used, computing each cycle and discarding the unneeded results, but that also would be wasteful. 
     The invention will now be described with reference to  FIGS. 1-9 . 
     Known 5-tap filter circuitry  10  of  FIG. 1  can be used for either interpolation or decimation. Circuitry  10  includes three multipliers  101 ,  102 ,  103  preferably followed by adder  12 . On the input side preferably are three coefficient memories or registers  13 , one preferably feeding a first input of each multiplier  101 - 103 . An adder  14  preferably is provided at the second input of each multiplier  101  and  102  and input sample chain  15  preferably loops around so that sample s t−2  is fed to the second input of multiplier  103 , while the sum of samples s t  and s t−4  is fed to the second input of multiplier  101  and the sum of samples s t−1  and s t−3  is fed to the second input of multiplier  102 . 
     At the beginning of sample chain  15 , sample interpolation circuitry  16  preferably is provided to insert n−1 zeroes between each sample for an interpolation factor of n. Thus, in a common case of n=2, one zero is inserted between each sample. 
     Similarly, at the output of adder  14 , result decimation circuitry  17  preferably is provided to delete n−1 out of every n results for an interpolation factor of n. Thus, in a common case of n=2, every other result is deleted. 
     While circuitry  10  can perform both interpolation and decimation on demand at run time, it does not take advantage of the zero-sample (in the case of interpolation) or zero-result (in the case of decimation) instances to reduce the number of multipliers needed. Thus, 5-tap interpolation/decimation filter  10  requires three multipliers. 
     However, review of the mathematics shown in  FIGS. 2 and 3  reveals that the interpolation circuit  40  of  FIG. 4  can be constructed.  FIG. 2  shows the eight results of the operation of circuitry  10  starting with an arbitrary sample s 0  (this actually includes references to samples as early as s −4 ). As can be seen, a number of terms are reused. Specifically, c 0 s n  is used in y n  and reused four cycles later in y n+4 . For example, c 0 s 0  is used in y 0  and y 4 . Similarly, c 1 s n  is used in y n+1  and reused two cycles later in y n+3 . In the case of interpolation by a factor of 2, every other input is going to be zero. This means that instead of using three multipliers for a 5-tap interpolation filter, one can use two multipliers and spread the computation of each term over two cycles (because the circuit will otherwise be computing a zero result at that time, based on the zero input). 
     This is illustrated in  FIG. 3 , where on the left, every other sample in the equations of  FIG. 2  has been set to zero. The boxes  30  of  FIG. 3  represent storage of the intermediate results computed as shown on the right side of  FIG. 3 . The values a and b are computed in alternate cycles, while the value a dly  represents the value a delayed by two cycles (i.e., the value a as computed during the previous cycle in which a was computed). 
     This is implemented in the circuitry  40  of  FIG. 4 . Circuitry  40  preferably includes two multipliers  401 ,  402 , preferably followed by adder  12 . In addition to feeding adder  12 , the output of multiplier  401  preferably also feeds a register  45  which preferably stores the value b of  FIG. 3 , and preferably also feeds a register  460  which preferably stores the value a of  FIG. 3  and in turn feeds a register  461  which preferably stores the value a dly  of  FIG. 3 . Registers  45 ,  461  preferably feed a multiplexer  47  which preferably can controllably select either register  45 ,  461  as appropriate. 
     On the input side, sample chain  41  preferably includes, in this 5-tap case, three registers  410 ,  411 ,  412  connected to feed respective first inputs of multipliers  401 ,  402  as shown. Because in interpolation every other sample s 1 , s 3 , s 5 , etc., is zeroed out, in accordance with the invention two steps are used to compute the results for the remaining samples, and therefore sample chain  41  preferably is supplied with each remaining sample s 0 , s 2 , s 4 , etc. twice as indicated. The respective second inputs of multipliers  401 ,  402  are fed by respective coefficient registers  420 ,  421 . In this 5-tap case, the value in register  420  alternates between coefficients c 0 , c 1 , while the value in register  421  alternates between coefficient c 2  and zero. The cycling of the coefficients occurs at a clock speed that is faster than the input sample rate by the interpolation factor—i.e., in this example the clock speed is twice the input sample rate. When the coefficients are set to c 0  and c 2 , multiplexer  47  selects register  461  containing the value a dly . When the coefficients are set to c 1  and zero, multiplexer  47  selects register  45  containing the value b. Adder  12  adds the output of multiplexer  47  to the products generated by multipliers  401 ,  402  to generate the filter output. 
     The decimation case is similar. Review of the mathematics shown in  FIG. 5  reveals that the decimation circuitry  60  of  FIG. 6  can be constructed.  FIG. 5  is similar to  FIG. 3 , except that different values are stored in b. One can see that in the case of decimation by a factor of 2, where every other computation is going to be deleted, the remaining computations can be broken in two and accumulated over two cycles, while the previous value is output for two cycles. This means that instead of using three multipliers for a 5-tap interpolation filter, one can use two multipliers. 
     This is implemented in the circuitry  60  of  FIG. 6 . Circuitry  60  preferably includes two multipliers  401 ,  402 , preferably followed by adder  12 . In addition to feeding adder  12 , the output of multiplier  401  preferably also feeds a register  45  which preferably stores the value b of  FIG. 5 , and preferably also feeds a register  460  which preferably stores the value a of  FIG. 5  and in turn feeds a register  461  which preferably stores the value a dly  of  FIG. 5 . Registers  45 ,  461  preferably feed a multiplexer  67  which preferably can controllably select either register  45 ,  461  as appropriate. 
     On the input side, sample chain  61  preferably includes, in this 5-tap case, three registers  410 ,  411 ,  412  in series. Register  410  preferably is connected to feed the first input of multiplier  401  through multiplexer  62 , as shown. Multiplexer  62  also can select the output of register  412  to feed the first input of multiplier  401 . Register  412  preferably also feeds the first input of multiplier  402 . The respective second inputs of multipliers  401 ,  402  are fed by respective coefficient registers  420 ,  421 . In this 5-tap case, the value in register  420  alternates between coefficients c 0 , c 1 , while the value in register  421  alternates between coefficient c 2  and zero. The cycling of the coefficients occurs at a clock speed that is the same as the input sample rate. In clock cycles in which the coefficients are set to c 0  and c 2  (these may be referred to as “odd” cycles), samples s t  and s t−2  are needed, and multiplexer  62  selects the output or register  410 . At the same time, multiplexer  67  selects register  461  containing the value a dly . In “even” cycles, in which the coefficients are set to c 1  and zero, sample s t−1  is needed and multiplexer  62  selects the output of register  412  (it will be appreciated from  FIG. 6 , which shows an odd cycle, the by the next even cycle, s t−1  will have moved into register  412 ). At the same time, multiplexer  67  selects register  45  containing the value b. 
     Adder  12  adds the output of multiplexer  67  to the products generated by multipliers  401 ,  402 . That sum is accumulated over two cycles using register  63  and adder  64 . The accumulated output is registered at  65  and output on two successive clock cycles as the filter output. 
     As can be seen, circuitry  60  is identical to circuitry  40  except for the addition, in circuitry  60 , of multiplexer  62  between registers  410 ,  412  and multiplier  402 , and the addition of output adder  64  and registers  63 ,  65  to accumulate the output. Thus, in accordance with the present invention, circuitry on a PLD, preferably including DSP blocks as discussed above, can be configured as circuitry  70  ( FIG. 7 ), which can function in either interpolation or decimation mode on demand. Circuitry  70  is substantially identical to circuitry  60 , with the addition only of output multiplexer  71  to select either the direct output of adder  12  or the accumulated, registered output of register  65 . In interpolation mode, multiplexer  62  always selects register  410 , and output multiplexer  71  selects adder  12 . In decimation mode, multiplexer  62  selects either register  410  or register  412  as in circuitry  60 , and multiplexer  71  selects register  65 . The switch between interpolation mode and decimation mode thus requires only changing the control signals for multiplexers  62 ,  71 , which is easily done at run time, as well as adjustments to the timing which also is easily done at run time. 
     Circuitry  70  can be implemented in a PLD by using the multipliers of a DSP block such as that described in above-incorporated application Ser. No. 11/447,370. If the DSP block has an input register stage and an input multiplexer stage as described in application Ser. No. 11/447,370, then registers  411 ,  411 ,  412  and multiplexer  62  can be implemented inside the DSP block. But if the DSP block does not have an input multiplexer stage, then registers  411 ,  411 ,  412  and multiplexer  62  would have to be implemented outside the DSP block, in the programmable logic of the PLD. Multiplexer  47  cannot be implemented in the DSP block of application Ser. No. 11/447,370. Therefore, multiplexer  67  and everything that follows it would have to be implemented outside the DSP block, in the programmable logic of the PLD, although there may be a PLD having a DSP block in which multiplexer  67  and at least some of the subsequent circuitry can be implemented within the DSP block. 
     The number N of multipliers can be expressed as follows:
 
 N=INT[CT /( snSH )]+1 when MOD [ CT /( snSH )]≠0, and
 
 N=CT /( snSH ) when MOD [ CT /( snSH )]=0
 
where:
         C=the number of channels,   T=the number of taps,   s=1 for an asymmetric filter,   s=2 for a symmetric filter,   n=the interpolation/decimation factor,   S=timesharing factor (i.e., the number of clock cycles available to the system to process one input or output sample,   H is factor that represents whether the case is a fullband case (H=1) or a halfband case (H=2) in which all odd coefficients with the exception of the middle coefficent are zero,
 
MOD [ x]=x−INT[x ], and
   INT[x] is the largest integer in x.       

     For a one-channel, fullband, symmetric case without timesharing, this reduces to:
 
 N=INT[T /(2 n )]+1 when MOD [ T /(2 n )]≠0, and
 
 T /(2 n ) when MOD [ T /(2 n )]=0
 
Thus, for a 5-tap symmetric filter with an interpolation/decimation factor of 2, N=INT[5/4]+1=INT[1.25]+1=2.
 
     As the number of taps increases, the number of storage elements increases as well, as does the depth of the storage elements (i.e., the number of cycles of delay required for each storage element). Thus, for a one-channel, fullband, symmetric 9-tap FIR filter with an interpolation/decimation factor of 2, N=INT[9/4]+1=INT[2.25]+1=3. In addition to storage elements a and b, two additional storage elements aa and bb would be needed, one of which would have a depth of 3 and the other of which would have a depth of 4. In general, the depth is equal to the distance from the tap in question to the center tap, meaning, for N taps where N is odd, that the maximum depth of any storage element in the filter would be ((N+1)/2)−1. This agrees with the example just given, where ((9+1)/2)−1=4. 
     In an alternative case of a halfband 11-tap FIR filter, the mathematics of interpolation and decimation by a factor of 2 can be reduced to that shown in  FIG. 8 . As can be seen, there is significant overlap between the interpolation case and the decimation case, with the only difference being the terms involving coefficient c 5 . Although this overlap only arises in the case of interpolation or decimation by 2, that is a commonly-used case. Thus, in accordance with the present invention, circuitry on a PLD, preferably including DSP blocks as discussed above, can be configured as circuitry  90  for performing interpolation or decimation in accordance with  FIG. 8  (i.e., only in cases where the interpolation or decimation factor is 2), as shown in  FIG. 9 . 
     Circuitry  90  preferably includes two multipliers  401 ,  402 , preferably followed by adder  12 . A multiplexer  92  can select either the output of multiplier  402  or the value 0 to input to adder  12 , while multiplier  401  preferably feeds adder  12  directly. 
     On the input side, sample chain  91  preferably includes, in this 11-tap case, eleven registers  901 - 911  in series. Registers  901  and  904  preferably are connected to feed a multiplexer  920  which selects the first input of an adder  930  which feeds a first input of multiplier  401 . Registers  910  and  911  preferably are connected to feed a multiplexer  921  which selects the second input of adder  930 . Registers  905  and  907  preferably are connected to feed an adder  931  which provides the first input of a multiplexer  922  which feeds a first input of multiplier  402 . The second input of multiplexer  922  is the output of register  907  in the decimation case, or the output of register  906  in the interpolation case, as selected by multiplexer  923 . The respective second inputs of multipliers  401 ,  402  are fed by respective coefficient registers  420 ,  421 . In this special 11-tap case with an interpolation/decimation factor of 2, the value in register  420  alternates between coefficients c 0 , c 2 , while the value in register  421  alternates between coefficients c 4 , c 5 . 
     On the output side, following adder  12 , adder  94  and one-cycle delay  95  allow accumulation of the output of adder  12 . A two-cycle delay  96  is provided on the output of multiplier  402 . Output multiplexer  97  selects between accumulator  94 / 95  and delay  96 . 
     For interpolation, the lower sequence of input samples is provided at  98 , and the upper sequence of outputs is generated at  99 , while for decimation, the upper sequence of input samples is provided at  98 , and the lower sequence of outputs is generated at  99 . 
     For decimation, in the first clock cycle, c 0 ×(s t +s t−10 )+c 4 ×(s t−4 +s t−6 ) is calculated, and stored in the accumulator. In the second clock cycle, c 2 ×(s t−2 +s t−8 )+c 5 ×s t−5  are calculated. By the second cycle, the samples have moved one step to the left in the pipeline of registers  901 - 911 , which is why  FIG. 9  shows the use of s t−3 , s t−6  and s t−9  in the latter calculation instead of s t−2 , s t−5  and s t−8 . The results are fed into the accumulator  94 / 95 , where they get added to the result of c 0 ×(s t +s t−10 )+c 4 ×(s t−4 +s t−6 ) from the previous clock cycle. 
     For interpolation, n the first clock cycle, c 0 ×(s t +s t−10 )+c 4 ×(s t−4 +s t−6 ) is calculated, and stored in the accumulator, as before. In the second clock cycle, c 2 ×(s t−2 +s t−8 ) and c 5 ×s t−4  are calculated. The result of c 2 ×(s t−2 +s t−8 ) is added into accumulator  94 / 95 . c 5 ×s t−4  is stored separately in delay  96 , and multiplexer  97  then switches the accumulator  94 / 95  or delay  96  to the output in alternative clock cycles. When delay  96  is selected by multiplexer  97 , multiplexer  923  selects its 0 input. 
     As in the case of circuitry  70 , the selections needed to switch between interpolation and decimation in circuitry  90  are easily performed at run time. 
     Circuitry  90  maps better onto a DSP block such as that of application Ser. No. 11/447,370 because there is nothing between multipliers  401 ,  402  and adder  12  except multiplexer  923 , which can be provided in that DSP block. Moreover, this circuitry follows the expression above for the number of multipliers. Thus, in this symmetric halfband case with n=2, N=INT[11/(2×2×2)]+1=INT[11/8]+1=INT[1.375]+1=2, meaning there should be two multipliers as shown. Note that in the fullband symmetric 11-tap case, N=INT[11/4]+1=INT[2.75]+1=3, meaning there would be a third multiplier, as well as a third register with cycling coefficients, but two-cycle delay  96  would not be needed. 
     Thus it is seen that a FIR filter structure that can be implemented in a specialized processing block of a programmable logic device, and switched in real time between interpolation and decimation modes, has been provided. 
     A PLD  280  incorporating such circuitry according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system  900  shown in  FIG. 10 . Data processing system  900  may include one or more of the following components: a processor  281 ; memory  282 ; I/O circuitry  283 ; and peripheral devices  284 . These components are coupled together by a system bus  285  and are populated on a circuit board  286  which is contained in an end-user system  287 . 
     System  900  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD  280  can be used to perform a variety of different logic functions. For example, PLD  280  can be configured as a processor or controller that works in cooperation with processor  281 . PLD  280  may also be used as an arbiter for arbitrating access to a shared resources in system  900 . In yet another example, PLD  280  can be configured as an interface between processor  281  and one of the other components in system  900 . It should be noted that system  900  is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims. 
     Various technologies can be used to implement PLDs  280  as described above and incorporating this invention. 
     Instructions for carrying out the method according to this invention may be encoded on a machine-readable medium, to be executed by a suitable computer or similar device to implement the method of the invention for programming PLDs. For example, a personal computer may be equipped with an interface to which a PLD can be connected, and the personal computer can be used by a user to program the PLD using a suitable software tool, such as the QUARTUS® II software available from Altera Corporation, of San Jose, Calif. 
       FIG. 11  presents a cross section of a magnetic data storage medium  600  which can be encoded with a machine executable program that can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium  600  can be a floppy diskette or hard disk, or magnetic tape, having a suitable substrate  601 , which may be conventional, and a suitable coating  602 , which may be conventional, on one or both sides, containing magnetic domains (not visible) whose polarity or orientation can be altered magnetically. Except in the case where it is magnetic tape, medium  600  may also have an opening (not shown) for receiving the spindle of a disk drive or other data storage device. 
     The magnetic domains of coating  602  of medium  600  are polarized or oriented so as to encode, in manner which may be conventional, a machine-executable program, for execution by a programming system such as a personal computer or other computer or similar system, having a socket or peripheral attachment into which the PLD to be programmed may be inserted, to configure appropriate portions of the PLD, including its specialized processing blocks, if any, as a filter in accordance with the invention. 
       FIG. 12  shows a cross section of an optically-readable data storage medium  700  which also can be encoded with such a machine-executable program, which can be carried out by systems such as the aforementioned personal computer, or other computer or similar device. Medium  700  can be a conventional compact disk read only memory (CD-ROM) or digital video disk read only memory (DVD-ROM) or a rewriteable medium such as a CD-R, CD-RW, DVD-R, DVD-RW, DVD+R, DVD+RW, or DVD-RAM or a magneto-optical disk which is optically readable and magneto-optically rewriteable. Medium  700  preferably has a suitable substrate  701 , which may be conventional, and a suitable coating  702 , which may be conventional, usually on one or both sides of substrate  701 . 
     In the case of a CD-based or DVD-based medium, as is well known, coating  702  is reflective and is impressed with a plurality of pits  703 , arranged on one or more layers, to encode the machine-executable program. The arrangement of pits is read by reflecting laser light off the surface of coating  702 . A protective coating  704 , which preferably is substantially transparent, is provided on top of coating  702 . 
     In the case of magneto-optical disk, as is well known, coating  702  has no pits  703 , but has a plurality of magnetic domains whose polarity or orientation can be changed magnetically when heated above a certain temperature, as by a laser (not shown). The orientation of the domains can be read by measuring the polarization of laser light reflected from coating  702 . The arrangement of the domains encodes the program as described above. 
     It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.

Technology Category: h