Patent Document

BACKGROUND 
     Field 
     Various features relate to signal amplifiers, and more specifically, to single-ended high dynamic range amplifiers featuring distortion nulling. 
     Background 
     Many modern wireless communication applications require high performance radio frequency (RF) amplifiers that exhibit low noise, low power consumption, and high linearity, among other things. Third order intermodulation (IM 3 ) distortion in such RF amplifiers threatens these high performance characteristics. 
     IM 3  distortion is the result of extra product terms produced when multiple continuous (CW) signals are presented to a linear circuit. When two tone stimulus frequencies f 1  and f 2  are applied to a linear circuit, the result at the output of the circuit is the fundamental terms f 1  and f 2  and 2f 1 ,2f 2 , (f 1 +f 2 ), (f 1 −f 2 ), (2f 1 −f 2 ), and (2f 2 −f 1 ). The most important IM 3  products are located at (2f 1 −f 2 ), and (2f 2  f 1 ). These terms are the most important because they are typically closest in frequency to the fundamental tones f 1  and f 2 . A figure of merit for measuring effects of IM 3  is referred to as the third order intercept point (IP 3 ). The parameter IP 3  is the measure of an amplifier&#39;s linearity. The mathematical expression of IP 3  is given by dBc/2+P n , where dBc is the relative difference in amplitude between fundamental frequency tone and the IM 3  product term. P n  is the fundamental power measured in dBm reference to 50 ohms. 
     The IM 3  product terms degrade the quality of a signal being amplified. In order to improve IP 3 , Veff=Vgs−V t  of the amplifier&#39;s input transistor can be increased by increasing the direct current (DC) power consumption. Since Veff is directly proportional to third order harmonics, an amplifier designer can make the tradeoff of improving IP 3  at the expense of increased DC power consumption. This, however, may not be feasible for applications requiring low power. 
     Another approach is to cancel out IM 3  product terms using IM 3  correction circuits. Low noise, low power, radio frequency (RF) amplifiers in most communication applications have a single-ended input in order to achieve low noise figure as well as achieve good matching at the antenna interface. In order to achieve IM 3  cancellation in a wideband, single-ended amplifier circuit, IM 3  correction circuitry must also be wideband, low power, and single-ended. 
     Single-ended, common gate based correction utilizing mirroring circuitry can be used, and one such example found in the prior art is shown in  FIG. 1 . However, for wideband high frequency applications p-channel metal oxide semiconductor field effect transistor (PMOS) mirror devices, such as P 1  and P 2  shown in  FIG. 1 , are too slow due to mobility μp of PMOS devices being 2.5 to 3 times slower than n-channel metal oxide semiconductor field effect transistor (NMOS) devices&#39; mobility μn. PMOS devices do not provide adequate bandwidth to achieve large reduction in the IM 3  products as operating frequencies are increased. Consequently the IP 3  performance of the circuit shown in  FIG. 1  is inherently limited. Moreover, parasitic capacitance introduced by the mirroring circuitry (e.g., P 1  and P 2 ) may add substantial delay unless care is taken to minimize it. This delay will create an undesirable phase shift at the summing node, which will further reduce IP 3  performance. 
     Thus, there is a need for low power, highly linear, low noise RF amplifiers having IM 3  distortion nulling that feature great IP 3  performance even for wideband and high frequency applications. Such amplifiers should have correction circuitry that does not significantly impact DC power consumption, increase noise, or suffer from significant non-linearity due to delay like the correction circuitry of the prior art. 
     SUMMARY 
     Highly integrated, wideband, system-on-chip (SOC) devices using small geometry complementary metal oxide semiconductor field effect transistor (CMOS) or bipolar junction transistor plus CMOS (BiCMOS) processes will be the next evolution of wireless and wireline communication integrated circuits. In one aspect, the present disclosure generally relates to low power, wideband, single-ended, IM 3  nulling for wideband RF amplifier applications. Various aspects disclosed herein provide a simultaneous increase in a receiver&#39;s front end dynamic range while reducing the DC power of the front end. This counter-intuitive finding is a result of the novel attributes of aspects of the disclosure described herein. 
     One feature pertains to an integrated circuit comprising a main amplifier circuit having a single-ended signal input and a single-ended signal output with a signal path existing there between, and a correction circuit coupled to the main amplifier circuit, the correction circuit including an auxiliary transistor having a gate or a base coupled to the single-ended signal input of the main amplifier circuit and a drain or a collector coupled to the signal path to reduce intermodulation products generated by the main amplifier circuit. According to one aspect, the correction circuit includes only one active component, the one active component being the auxiliary transistor. According to another aspect, the auxiliary transistor is a solitary active device of the correction circuit that receives an input signal from the single-ended signal input and provides an intermodulation product cancellation signal to the signal path to reduce the intermodulation products generated by the main amplifier circuit. 
     According to one aspect, the auxiliary transistor is an n-channel device. According to another aspect, the auxiliary transistor is a p-channel device. According to yet another aspect, the main amplifier circuit includes a first transistor and a second transistor arranged in a two-stage common gate or two-stage common base architecture with the single-ended signal input coupled to a source or an emitter of the first transistor and the single-ended signal output coupled to a drain or a collector of the second transistor, a drain or a collector of the first transistor coupled to a source or an emitter of the second transistor at a common point, and the drain or the collector of the auxiliary transistor coupled to the common point. 
     According to one aspect, the first, second, and auxiliary transistors are n-channel devices. According to another aspect, the first, second, and auxiliary transistors are p-channel metal oxide semiconductor field effect transistor (PMOS) devices. According to yet another aspect, the main amplifier circuit includes a first transistor and a second transistor arranged in a two-stage common source or a two-stage common emitter architecture, the first transistor receiving the single-ended signal input and the second transistor providing the single-ended signal output, and the drain or the collector of the auxiliary transistor coupled to a common point of the main amplifier circuit where the first and second transistors are coupled to each other. 
     According to one aspect, the main amplifier circuit includes a first transistor and a second transistor arranged in a two-stage common drain or a two-stage common collector architecture, the first transistor receiving the single-ended signal input and the second transistor providing the single-ended signal output, and the drain or the collector of the auxiliary transistor coupled to a common point of the main amplifier circuit where the first and second transistors are coupled to each other. According to another aspect, the auxiliary transistor has a width and a length that is sized relative to a width and a length of an input transistor of the main amplifier circuit such that third order intermodulation products generated by the auxiliary transistor and provided to the signal path have a magnitude that is substantially same as a magnitude of third order intermodulation products generated by the main amplifier circuit. According to yet another aspect, an input signal gain of the correction circuit is between 15 dB to 40 dB less than a signal gain between the single-ended signal input and the single-ended signal output of the main amplifier circuit. 
     According to one aspect, the correction circuit includes at least one biasing capacitor and a biasing resistor that provide a biasing voltage to the auxiliary transistor. According to another aspect, a capacitance value of the capacitor and a resistance value of the resistor cause the auxiliary transistor to have a gate-source voltage or a base-emitter voltage that is scaled relative to a gate-source voltage or a base-emitter voltage of an input transistor of the main amplifier circuit. 
     Another feature provides a radio frequency (RF) amplifier comprising a main amplifier circuit having a single-ended signal input and a single-ended signal output, the main amplifier circuit including a signal path between the single-ended signal input and the single-ended signal output, and a correction circuit coupled to the main amplifier circuit, the correction circuit including a solitary auxiliary transistor providing an intermodulation product cancellation signal to the signal path to reduce intermodulation products generated by the main amplifier circuit, the intermodulation product cancellation signal based on an input signal provided to the single-ended signal input. According to one aspect, the auxiliary transistor is an n-channel device. According to another aspect, the main amplifier circuit includes a first transistor and a second transistor arranged in a two-stage common gate or two-stage common base architecture with the single-ended signal input coupled to a source or an emitter of the first transistor and the single-ended signal output coupled to a drain or a collector of the second transistor, a drain or a collector of the first transistor coupled to a source or an emitter of the second transistor at a common point, and the solitary auxiliary transistor providing the intermodulation product cancellation signal to the signal path at the common point. According to yet another aspect, the auxiliary transistor has a width and a length that is sized relative to a width and a length of an input transistor of the main amplifier circuit such that third order intermodulation products generated by the auxiliary transistor and provided to the signal path have a magnitude that is substantially same as a magnitude of third order intermodulation products generated by the main amplifier circuit. 
     Another feature provides a radio frequency (RF) amplifier comprising a main amplifier circuit including an input transistor having a single-ended input and a second transistor having a single-ended output, the input transistor and the second transistor coupled to each other and arranged in a common gate or a common base architecture, the main amplifier circuit having a signal path through the input transistor and the second transistor that is adapted to amplify an input signal provided to the single-ended input, and a correction circuit coupled to the main amplifier circuit, the correction circuit including a solitary auxiliary transistor having a gate or a base adapted to receive the input signal and a drain or a collector adapted to provide an intermodulation product cancellation signal to the signal path to reduce intermodulation products generated by the main amplifier circuit, the intermodulation product cancellation signal based on the input signal received at the gate or the base of the solitary auxiliary transistor. According to one aspect, a signal gain of the correction circuit is at least 15 dB less than a signal gain between the single-ended input and the single-ended output of the main amplifier circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a single-ended, common gate based correction circuitry utilizing a PMOS mirror topology found in the prior art. 
         FIG. 2  illustrates a high-level schematic of a wideband RF amplifier featuring IM3 distortion nulling. 
         FIG. 3  illustrates a first exemplary novel wideband RF amplifier with correction circuitry. 
         FIG. 4  illustrates a first exemplary schematic of the correction circuit for the RF amplifier shown in  FIG. 3 . 
         FIG. 5  illustrates a second exemplary novel wideband RF amplifier having correction circuitry. 
         FIG. 6  illustrates a third exemplary novel RF amplifier  600  having correction circuitry. 
         FIG. 7  illustrates a graph of a transient simulation for a two-tone input signal applied to a two-stage common gate RF amplifier without correction circuitry found in the prior art. 
         FIG. 8  illustrates a graph of a transient simulation for a two-tone input signal applied to a two-stage common gate RF amplifier with PMOS current mirror-based correction circuitry found in the prior art. 
         FIG. 9  illustrates a graph of a transient simulation for a two-tone input signal applied to the two-stage common gate RF amplifier shown in  FIGS. 3 and 4 . 
         FIG. 10  illustrates a table that summarizes and compares the IIP3 performance and DC power consumption of various RF amplifier simulations shown and described with respect to  FIGS. 7-9 . 
         FIG. 11  illustrates a noise figure simulation comparing the noise figure of a prior art two-stage common gate amplifier with no correction circuitry to the RF amplifier having NMOS based correction circuitry shown in  FIGS. 3 and 4 . 
     
    
    
     DETAILED DESCRIPTION 
     In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular aspects, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. 
     An aspect is an implementation or example. Reference in the specification to “an aspect,” “one aspect,” “some aspects,” “various aspects,” or “other aspects” means that a particular feature, structure, or characteristic described in connection with the aspects is included in at least some aspects, but not necessarily all aspects, of the present techniques. The various appearances of “an aspect,” “one aspect,” or “some aspects” are not necessarily all referring to the same aspects. Elements or aspects from an aspect can be combined with elements or aspects of another aspect. 
     Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular aspect or aspects. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element. 
     It is to be noted that, although some aspects have been described in reference to particular implementations, other implementations are possible according to some aspects. Additionally, the arrangement and/or order of circuit elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some aspects. 
     In each figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary. 
     Overview 
     Low noise, low power, RF amplifiers in most communication applications have a single-ended input in order to achieve low noise figure as well as achieve good matching at the antenna interface. In order to achieve IM 3  cancellation in a wideband, single-ended amplifier circuit, IM 3  correction circuitry should also be wideband, low power as well as single-ended. In order for the correction to be wideband and operate at high RF frequencies n-channel devices may be utilized due to their relatively high mobility compared to p-channel devices. However, p-channel devices may also be used for certain applications assuming the circuit delay through the cancellation circuitry is minimized. 
     The RF amplifiers described herein include a main amplifier and a correction circuit (e.g., correction section). The correction circuit may also be referred to as an “auxiliary amplifier.” The active devices of the auxiliary amplifiers described herein are preferably composed of a single device (e.g., single NMOS, PMOS, or NPN device) that is coupled to a single-ended main amplifier. One critical function of the auxiliary amplifier is to correct the IM 3  products produced in the main amplifier. In one aspect, the auxiliary amplifier may be constructed from a single n-channel device (e.g., NMOS or NPN) thereby exhibiting minimal delay so that it provides very high bandwidth capability especially over p-channel based cancellation circuits of the prior art. This is due to the mobility of n-channel devices having a mobility that is 2-3 times faster than the mobility of p-channel devices. In other aspects, the auxiliary amplifier may be constructed from a single p-channel device (e.g., PMOS or PNP) to also minimize delay. Such a configuration may be used if the main amplifier to which it is coupled is composed of p-channel devices. 
     The auxiliary amplifier provides a scaled down magnitude of the main amplifier&#39;s fundamental signal as well as an in-phase IM 3  term, and both of these terms are summed at a common point in the main amplifier. At this critical point, the undesired third order terms will cancel, resulting in a reduction of overall IM 3 . This results in substantial improvement in IP 3  over a wide range of frequencies because of the reduced delay inside the auxiliary amplifier. This improvement allows the DC power dissipation of the overall amplifier to be significantly reduced, as the main amplifier distortion is reduced by an order of magnitude as a result of IM 3  cancellation. 
     Various Aspects of RF Amplifier Featuring IM 3  Distortion Nulling 
       FIG. 2  illustrates a high-level schematic of a wideband RF amplifier  200  featuring IM 3  distortion nulling according to one aspect. The RF amplifier  200  includes a main amplifier circuit  210  and a correction circuit  250  (e.g., “auxiliary amplifier”). The main amplifier  210  generates a main signal current i main  that includes signal component i sig , a DC component i DC1 , and a third order nonlinear current i NL3a . The ratio of the third order nonlinear current component i NL3a  to the signal current component i sig  represents the IM 3  performance for the main amplifier  210  alone. 
     The correction circuit  250  generates an auxiliary signal current i aux  that includes a DC component i DC2  and a scaled down version of the main amplifier&#39;s signal current component N*i sig . The auxiliary signal also includes a third order nonlinear current i NL3b , which is on the order of the third order nonlinear current i NL3a  in the main amplifier  210 . Essentially, the correction circuit  250  is a low power version of the main amplifier  210  but the signal gain is deliberately lowered in order to generate a replica of the main amplifier&#39;s  210  IM 3  with the same magnitude and opposite phase. According to one aspect, the correction circuit  250  has an input signal gain that is at least 5 dB less than the input signal gain (i.e., signal gain between V in  and V out ) of the main amplifier circuit. According to one aspect, the correction circuit  250  has an input signal gain that is at least 10 dB less than the input signal gain of the main amplifier circuit. According to one aspect, the correction circuit  250  has an input signal gain that is at least 15 dB less than the input signal gain of the main amplifier circuit. According to one aspect, the correction circuit  250  has an input signal gain that is at least 15 dB to 40 dB less than the input signal gain of the main amplifier circuit. 
     The resultant output signal current of the RF amplifier  200  is given by: i out =i main +i aux . If the correction circuit  250  is based on n-channel active devices then the correction circuit  250  inverts the phase of the current terms i DC2 , N*i sig , and i NL3b  and the output signal current of the RF amplifier  200  is given by i out =i main +i aux =(i DC1 +i DC2 )+(i sig −N*i sig )+(i NL3a −i NL3b ) where N is a scaling factor much less than one (1). Moreover, the IM 3  terms also substantially cancel each other out since they are largely the same magnitude and opposite phase. This results in an RF amplifier  200  output i out  having reduced IM 3  distortion and consequently an improvement in IP 3  performance. 
       FIGS. 3 and 4  illustrate a first exemplary novel wideband RF amplifier  200  according to one aspect of the disclosure. The RF amplifier  200  shown in  FIGS. 3 and 4  is a CMOS, wideband amplifier having a common gate architecture (e.g., two-stage common gate). The RF amplifier  200  includes the main amplifier  210  and the correction circuit  250 . The main amplifier includes a first NMOS transistor M 1  (e.g., “input transistor”) having a transconductance (gm) that establishes a real 50 ohms impedance at the input node V in  given by the equation Rin=1/gm, where Rin is the input real impedance. Passive devices C 1  and L 1  resonate out the effects of the amplifier&#39;s  200  package bondwire inductance as well as parasitic capacitance lumped at the input node V in  Active devices M 1  and M 2  form a first and second common gate stage in the main amplifier  210  and provide isolation between the input node V in  and the output node V out . Passive devices R 1  and C 4  form an RC low-pass filter, which rejects undesired common mode, low frequency noise on the power supply V dd . The main DC bias voltage V bias  is generated by devices C 2 , R 2 , and M 3 . I ref  is a DC bias current which will create a gate-source voltage (Vgs) across the gate of NMOS transistor M 3 . This voltage is mirrored across the gate-source voltage Vgs of the first transistor M 1  thereby putting the NMOS transistor M 1  in a saturation mode of operation and allowing the wideband main amplifier circuit  210  to amplify a given signal at the input V in . 
       FIG. 4  illustrates a first exemplary schematic of the correction circuit  250  according to one aspect of the disclosure. As previously mentioned, the correction circuit  250  is coupled to the main amplifier  210  and provides an intermodulation product cancellation signal to the main amplifier&#39;s signal path to cancel out IM 3  distortion products produced by the main amplifier  210 . In the example illustrated in  FIG. 4 , the correction circuit&#39;s  250  active components includes a single NMOS transistor M 4  (e.g., auxiliary transistor) that has a gate terminal  402  coupled to the input signal V in  and a drain terminal  404  coupled to the common point CP (“common node”) of the main amplifier&#39;s active devices M 1  and M 2 . The correction circuit  250  will produce a scaled down version of the main amplifier circuit&#39;s  210  signal current. Specifically, the correction circuit&#39;s  250  signal current N*i sig  is equal to gm M4 *Vgs M4 , where the transconductance gm M4 =gm M1 *N. The fraction N is equal to SQRT[(W M4 /L M4 )/(W M1 /L M1 )], where W and L refer to the device width and length, respectively. 
     Passive devices C 3  and R 3  provide the correction circuit&#39;s  250  DC biasing and provide alternating current (ac) coupling between the main amplifier (Node A) and M 4 &#39;s input terminal  402 . The Vgs of M 4  (i.e., Vgs M4 ) is biased such that it is a scaled version of the main amplifier&#39;s first transistor M 1  Vgs (i.e., Vgs M1 ). For example, the width W 4  of M 4  is chosen in order to supply M 4  with the appropriate Vgs according to the equation Vgs M4 =SQRT[2i/(μC ox  (W M4 /L M4 ))] V t , where i (e.g., i Aux ) is the output current of M 4 , μ is the carrier mobility, and C ox  is the gate-to-channel capacitance per unit area. 
     The DC and signal currents of the main amplifier  210  and the correction circuit  250  are summed at the common point CP. That is, the signal i Aux  provided by the correction circuit  250  is summed at the common point CP so that i Aux  is subtracted from the main amplifier&#39;s signal path. It is at the common point CP where the IM 3  terms (e.g., i NL3a  and i NL3b ) will cancel. 
       FIG. 5  illustrates a second exemplary novel wideband RF amplifier  500  according to one aspect of the disclosure. The RF amplifier  500  shown in  FIG. 5  is a bipolar transistor-based, wideband amplifier having a common base architecture (e.g., two-stage common base). The RF amplifier  500  includes the main amplifier  510  and the correction circuit  550 . Like its CMOS counterpart shown in  FIGS. 3 and 4 , the bipolar transistor-based design also includes a single transistor for the correction circuit  550 , which greatly reduces delay and increases IP 3  performance. 
     The transconductance gm of the NPN transistor Q 1  provides the 50 ohm real input impedance needed to interface with outside devices based on the equation Rin=1/gm. Passive devices C 1  and L 1  resonate out any parasitic inductance seen at the package level and internal gate source parasitic capacitance (Cgs) of device Q 1 . Active devices Q 1  and Q 2  provide isolation between V in  and V out  and form a first and second common gate stage of the main amplifier  510 . Passive devices R 1  and C 4  low-pass filter out any low frequency noise on the supply V cc . The main DC bias voltage V bias  is generated by devices R 2  and Q 3 . Feedback resistor R 2  will compensate for the input transistor&#39;s Q 1  kickback base current given by I Base =I Collector /β, where β is the current gain parameter. Capacitor C 2  low-pass filters any common mode noise that can come from reference current I ref . 
     The cancellation circuit  550  is coupled to the main amplifier  510  and provides an intermodulation product cancellation signal to the main amplifier&#39;s signal path to cancel out the IM 3  distortion products produced by the main amplifier  510 . The cancellation circuit shown in  FIG. 5  consists of a single active device, which is an NPN transistor Q 4  (e.g., “auxiliary transistor”), that produces a scaled down version of the main amplifier&#39;s signal current in addition to the IM 3  third order nonlinear current. The DC biasing of the cancellation circuit&#39;s transistor Q 4  is achieved with passive devices R 3  and C 3 . In some aspects, the resistor R 3  may be excluded. The base-emitter voltage V BE  of Q 4  is equal to η*KT/q*ln(Ic/Is), where η is the area of the transistor Q 4 , KT/q is a constant 25 mV built-in voltage and Ic and Is are the collector and saturation currents, respectively. The transistor Q 4  is scaled down by making its area smaller than the area of the main amplifier&#39;s input transistor Q 1 . The DC and signal currents of the main amplifier  510  and the correction circuit  550  are summed at the common point CP. That is, the signal i Aux  provided by the correction circuit  550  is summed at the common point CP so that i Aux  is subtracted from the main amplifier&#39;s signal path. It is at the common point CP where the IM 3  terms (e.g., i NL3a  and i NL3b ) will cancel. 
     The single transistor M 4 /Q 4  design of the correction circuit  250  shown in  FIGS. 4 and 5  allows the correction circuit  250  to provide a signal to the main amplifier signal path that cancels the IM 3  distortion products with very little delay. Less delay means less phase and less non-linearity, and consequently greater IM 3  product cancelation. The n-channel design also allows the RF amplifier  200  to operate at relatively high frequencies and thus the cancellation circuit  250  allows the RF amplifier  200  to operate effectively across a wide band of frequencies. 
       FIG. 6  illustrates a third exemplary novel RF amplifier  600  according to one aspect of the disclosure. The RF amplifier  600  shown in  FIG. 6  is a CMOS, wideband amplifier having a common gate architecture (e.g., two-stage common gate). The RF amplifier  600  includes the main amplifier  610  and the correction circuit  650 . The main amplifier includes a first PMOS transistor M 1  (e.g., “input transistor”) having a transconductance (gm) that establishes a real 50 ohms impedance at the input node V in  given by the equation Rin=1/gm, where Rin is the input real impedance. Passive devices C 1  and L 1  resonate out the effects of the amplifier&#39;s  600  package bondwire inductance as well as parasitic capacitance lumped at the input node V in  Active devices M 1  and M 2  form a first and second common gate stage in the main amplifier  610  and provide isolation between the input node V in  and the output node V out . Passive devices R 1  and C 4  form an RC low-pass filter, which rejects undesired common mode, low frequency noise on the ground line. The main DC bias voltage V bias  is generated by devices C 2 , R 2 , and M 3 . I ref  is a DC bias current which will create a gate-source voltage (Vgs) across the gate of PMOS transistor M 3 . This voltage is mirrored across the gate-source voltage Vgs of the first transistor M 1  thereby putting the PMOS transistor M 1  in a saturation mode of operation and allowing the wideband main amplifier circuit  610  to amplify a given signal at the input V in . 
     The correction circuit  650  is coupled to the main amplifier  610  and provides an intermodulation product cancellation signal to the main amplifier&#39;s signal path to cancel out IM 3  distortion products produced by the main amplifier  610 . In the example illustrated in  FIG. 6 , the correction circuit&#39;s  650  active components includes a single PMOS transistor M 4  (e.g., auxiliary transistor) that has a gate terminal  602  coupled to the input signal V in  and a drain terminal  604  coupled to the common point CP (“common node”) of the main amplifier&#39;s active devices M 1  and M 2 . The correction circuit  650  will produce a scaled down version of the main amplifier circuit&#39;s  610  signal current. Specifically, the correction circuit&#39;s  650  signal current N*i sig  is equal to gm M4 *Vgs M4 , where the transconductance gm M4 =gm M1 *N. The fraction N is equal to SQRT[W M1 /L M1 )/(W M4 /L M4 )], where W and L refer to the device width and length, respectively. 
     Passive devices C 3  and R 3  provide the correction circuit&#39;s  650  DC biasing. The Vgs of M 4  (i.e., Vgs M4 ) is biased such that it is a scaled version of the main amplifier&#39;s first transistor M 1  Vgs (i.e., Vgs M1 ). The DC and signal currents of the main amplifier  610  and the correction circuit  650  are summed at the common point CP. That is, the signal i Aux  provided by the correction circuit  650  is summed at the common point CP so that i Aux  is subtracted from the main amplifier&#39;s signal path. It is at the common point CP where the IM 3  terms (e.g., i NL3a  and i NL3b ) will cancel. 
     The RF amplifiers  200 ,  500 ,  600  described above with respect to  FIGS. 3-6  include a two-stage common gate main amplifier  210 ,  510 ,  610  section. However, this is merely exemplary. The cancellation circuits  250 ,  550 ,  650 , described above may be coupled to main amplifiers having different architecture in order to provide IM 3  distortion nulling for such amplifiers. Some non-limiting, non-exclusive examples of other RF amplifier architectures that the cancellation circuits  250 ,  550 ,  650  may be applied to include one or more stage common source/emitter amplifier architectures, one or more stage common drain/collector amplifier architectures, tuned CMOS or bipolar amplifier architectures, etc. 
     Moreover, in the exemplary cancellation circuits  210 ,  510 ,  610  described above with respect to  FIGS. 3-6 , the cancellation circuits  210 ,  510 ,  610  include a solitary active device M 4 /Q 4 , meaning that it is the only active device of the cancellation circuit  210 ,  510 ,  610 . However, in other aspects, the cancellation circuits  210 ,  510 ,  610  may include additional active components that are not positioned along the intermodulation product cancellation signal path of the cancellation circuit  210 ,  510 ,  610 . 
       FIG. 7  illustrates a graph of a transient simulation for a two-tone input signal applied to a two-stage common gate RF amplifier  110  (see  FIG. 1 ) without correction circuitry  150  found in the prior art. The main signal tones are spaced 10 MHz apart and have center frequencies of 1.500 GHz and 1.510 GHz. Each tone has a power of −20 dBm referenced to 50 ohms. The graph shows that such an RF amplifier circuit without correction has a simulated input IP 3  (IIP3) of +2.2 dBm and 44.4 dBc. 
       FIG. 8  illustrates a graph of a transient simulation for a two-tone input signal applied to a two-stage common gate RF amplifier  110  (see  FIG. 1 ) with correction circuitry  150  found in the prior art. The main signal tones are spaced 10 MHz apart and have center frequencies of 1.500 GHz and 1.510 GHz. Each tone has a power of −20 dBm referenced to 50 ohms. The graph shows that such an RF amplifier circuit with PMOS mirror correction has a simulated IIP3 of +3.05 dBm and 46.0 dBc. 
       FIG. 9  illustrates a graph of a transient simulation for a two-tone input signal applied to the two-stage common gate RF amplifier  200  shown in  FIGS. 3 and 4 . The main signal tones are spaced 10 MHz apart and have center frequencies of 1.500 GHz and 1.510 GHz. Each tone has a power of −20 dBm referenced to 50 ohms. The graph shows that the novel RF amplifier circuit  200  has a simulated IIP3 of +6.5 dBm and 52.6 dBc, which is much improved over the prior art correction circuitry  150  (see  FIG. 1 ). Thus, the short delay NMOS correction circuitry  250  (see  FIG. 4 ) improves IIP3 considerably by about 3.5 to 4.3 dBm over two-stage common gate amplifiers having no correction circuitry or those have PMOS mirror based correction circuitry  150 . Similarly, dBc performance is also improved by at least 6.6 dBc. 
       FIG. 10  illustrates a table that summarizes and compares the IIP3 performance and DC power consumption of the RF amplifier simulations shown and described with respect to  FIGS. 7-9 . As indicated in the table, the best performance of the three is obtained by the RF amplifier featuring short delay NMOS correction circuitry (i.e., RF amplifier  200  of  FIGS. 3 and 4 ) whose IIP3 value is greater than both the RF amplifier having no correction circuitry (i.e., RF amplifier  110  in  FIG. 1 ) and the RF amplifier having the PMOS mirror based correction circuitry (i.e., RF amplifier  100  in  FIG. 1 ). Its DC power consumption is also lower than the RF amplifier having the PMOS mirror based correction circuitry. 
       FIG. 11  illustrates a noise figure simulation comparing the noise figure of a prior art two-stage common gate amplifier  110  (see  FIG. 1 ) with no correction circuitry to the RF amplifier  200  having NMOS based correction circuitry shown in  FIGS. 3 and 4 . The simulation shows that the correction circuitry contributes a relatively minor noise amount of 0.408 dB. The noise contribution of is mainly due to auxiliary transistor M 4  shown in  FIG. 4 . This significant improvement in IIP3 performance and minimal DC power consumption more than justifies the slight increase in noise contributed by the correction circuitry. 
     Thus, an improved RF amplifier with IM 3  distortion nulling has been disclosed herein that incorporates a single transistor design to minimize delay through the correction circuit. Moreover, when the single transistor is an n-channel transistor, bandwidth of the amplifier is significantly improved due to the fast mobility (μn) of re-channel devices in order to achieve wideband cancellation of IM 3  products created in the main wideband amplifier. 
     It is to be understood that the described aspect is merely illustrative of some of the many specific aspects that represent applications of the principals of the present application. Although the concept has been demonstrated in CMOS and bipolar technologies, it would be obvious to one skilled in the art to apply the concepts described here to any process technology. The implementation of the concept is not integrated circuit process dependent, and resultantly, the concept is applied equally well to any process technology. 
     Moreover, it to be understood that specifics in the aforementioned examples may be used anywhere in one or more aspects. The present techniques are not restricted to the particular details listed herein. Indeed, those skilled in the art having the benefit of this disclosure will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present techniques. Accordingly, it is the following claims including any amendments thereto that define the scope of the techniques.

Technology Category: h