Patent Document

BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a pixel modulation apparatus and a method thereof, and more particularly to a pixel modulation apparatus capable of performing high-accuracy pulse width modulation for controlling the light emission of a laser on a pixel basis in an image forming apparatus which uses the laser to form an image, and a method of such pixel modulation. 
   2. Related Background Art 
   An image forming apparatus using a laser beam has been used as one of apparatus performing the control of the quantity of a laser beam by means of a pulse width modulation. As for such an image forming apparatus, first, a color image forming apparatus is simply described as an example thereof. 
   A color image forming process of such an color image forming apparatus generally uses four kinds of toners of yellow (Y), cyan (C), magenta (Mg) and black (Bk) severally. Such a color image forming process takes a time four times as long as the time necessary for an image forming process of a conventional image forming apparatus forming a monochrome image if no measures for shortening the time are taken. Because of this, an image forming process adopts use of four photosensitive drums for the respective four colors and use of a two-beam laser capable of writing two lines at the same time. 
     FIG. 1  is a schematic diagram of a conventional four-drum type image forming apparatus. In the apparatus, photosensitive drums  18   a ,  18   b ,  18   c  and  18   d  are disposed in a line. A different color is allotted to each of the photosensitive drums  18   a - 18   d . The toner of each color is sequentially transferred to a photographic printing paper  26 , and a color image is reproduced on the photographic printing paper  26 . Each of the photosensitive drums  18   a - 18   d  is provided with an image writing portion shown in FIG.  2 . The image writing portion forms an electrostatic latent image on the photosensitive drum by means of a laser beam. The operations of the image writing portion shown in  FIG. 2  are described in the following. 
   DESCRIPTIONS OF IMAGE WRITING PORTION 
   A laser chip  21  is one of a two-beam type having laser diodes a and b. The laser chip  21  also has a photodiode c receiving the back light from each of the laser diodes a and b. 
   Driving currents Id 1  and Id 2  for controlling the emission of light of each of the laser diodes b and a, respectively, are supplied to the laser diodes a and b from a laser diode (LD) driver  22 . The photodiode c outputs monitor current Im according to the quantity of the back light. The monitor current Im is input into the LD driver  22 . The LD driver  22  performs the auto-power control (APC) of the quantities of the light emitted by the laser diodes a and b on the basis of the monitor current Im. The interval between the laser emission points of the laser chip  21  cannot be equal to the interval between pixels (about 42 μm in case of 600 dots per inch (dpi)) owing to the limitation on the manufacture of the laser chip  21 . Because of this problem, as shown in  FIG. 3 , the laser diodes a and b are obliquely disposed such that two beams A and B are spotted at positions distant from each other by, for example, 16 pixels in the laser scanning direction in pixel regions enclosed by grid lines. 
   Laser beams emitted by the laser chip  21  are deflected by a polygon mirror  16  fixed on a motor shaft to rotate in the direction shown by an arrow in FIG.  2 . Thereby, the deflected laser beams scan on a photosensitive drum  18 . A f-θ lens  17  is for collecting the deflected laser beams on the photosensitive drum  18  such that their linear velocities are constant. If the photosensitive drum  18  and the toner for printing are previously charged electrostatically by the predetermined quantities of electrostatic charges, the quantity of the toner for printing adhering to the photosensitive drum  18  changes according to the quantity of the light irradiating the photosensitive drum  18 . Consequently, it becomes possible to print an image having intermediate gradations. A BD mirror  19  is disposed at a position in a mechanically fixed positional relation to the photosensitive drum  18 . Laser beams reflected by the BD mirror  19  are input into a light receiving diode  20 . The received laser beams are used for the detection of the positions on the photosensitive drum  18 , from which information is written. An output of the light receiving diode  20  is input into a horizontal synchronizing signal generating circuit  24 , and the horizontal synchronizing signal generating circuit  24  generates a horizontal synchronizing signal BD. 
   The horizontal synchronizing signal BD is input into a pixel modulation circuit  23 . The pixel modulation circuit  23  generates a pixel clock synchronized with the horizontal synchronizing signal BD or a pixel clock having a frequency which is a coefficient multiple of the frequency of the horizontal synchronizing signal. Read clocks RK 1  and RK 2  for the reading of pixel data are input into a pixel data generating unit  25  on the basis of the pixel clock. 
   The pixel data generating unit  25  outputs pixel data D 1  and D 2  and respective write clocks WK 1  and WK 2  to the pixel modulation circuit  23 . The pixel data generating unit  25  generates the pixel data D 1  and D 2  by reading an original with a scanner or the like. The pixel modulation circuit  23  outputs pixel modulation signals ON 1  and ON 2  for making it possible to modulate the quantity of laser light desirably, to the LD driver  22  on the basis of the pixel data D 1  and D 2 . The pixel modulation signals ON 1  and ON 2  are pulse width modulation signals for controlling the quantity of laser light on the basis of the periods of laser irradiation time.  FIG. 4A  shows an example of a pixel modulation signal taking different pulse widths P 1 , P 2 , P 3  and P 4 . If a laser diode is turned on in accordance with these pulse widths P 1 -P 4 , the desired control of quantity of light to the photosensitive drum  18  can be realized. There are two major methods of pixel modulation, which are applicable to the pixel modulation circuit  23 . 
   Digital Pixel Modulation 
   A pixel modulation circuit for the use of a character image adopts the serial modulation of, for example, four bits to process a pixel (composed of e.g. 600 dpi) by dividing the pixel into four pixels (composed of 2400 dpi). Dithering and the error diffusion method are used jointly to improve reproducibility of the gradation of a video image. 
   Analog Image Modulation 
   It is general that a pixel modulation circuit needed to reproduce a further higher image quality is provided with a triangular wave signal generation circuit for generating an analog pixel data signal by converting input pixel data D 1  and D 2  by digital-analogue (D/A) conversion to generate a triangular wave signal having a predetermined pixel period, and a pulse width modulation circuit for generating a pulse width modulation signal by comparing the signal level of the triangular wave signal and the signal level of the aforementioned analog pixel data signal. 
   However, the digital pixel modulation and the analog pixel modulation, which are used in the conventional image forming apparatus, have the following problems. 
   Problem 1. 
   Input images generally have characters and video images that are mixed together. For such input images, the conventional digital pixel modulation could not secure sufficient number of pixel divisions, and thereby, a predetermined video image quality could not be secured. 
   Problem 2. 
   In the conventional analog pixel modulation, because a stable fast triangular wave signal generation circuit cannot be realized by the complementary metal-oxide semiconductor (CMOS) large scale integrated circuit (LSI) technique, the stable fast triangular wave signal generation circuit has been realized by the bipolar LSI technique. Consequently, a pixel modulation circuit for video has been expensive. 
   Problem 3. 
     FIG. 4A  shows an example of a pixel modulation signal including different pulse widths P 1 -P 4 . If the laser diodes a and b are lightened in accordance with the pulse widths, a desired control of the quantity of light on the photosensitive drum  18  can be realized. However, laser diodes do not emit light immediately after the supply of a driving current Id to them, but emit light after the passing of a delay time Td in principle. On the other hand, when the driving current Id is cut off, the laser diodes stops their light emission in a short time. Consequently, as shown in  FIG. 4B , the periods of light emission of the laser diodes become shorter than the periods of being on of the pixel modulation signal by the delay time Td of light emission. The laser diodes do not emit light during the period of the pulse width P 2 . Consequently, the desired control of the light emission of laser diodes could not performed in the conventional digital image modulation, and thereby the quality of printing has been deteriorated. 
   SUMMARY OF THE INVENTION 
   In view of the back ground mentioned above, an object of the present invention is to provide a pixel modulation apparatus that can easily generate a laser control signal suitable for various images such as gradated images and character images and can accurately change the quantity of laser light and further can be constructed by, for example, a pure CMOS process and still further is low in cost, and a method thereof. 
   Accordingly, according to a preferable embodiment of the invention, a pixel modulation apparatus for converting pixel data D composed of N 1  bits input at a pixel period T 0 , to a pixel data signal composed of one bit comprising: a first data conversion unit which converts the pixel data D to pixel data D 1  expanded to N 2  bits (N 2 &gt;N 1 ) at the period T 0 ; a second data conversion unit which converts the pixel data D 1  to pixel data D 2  composed of N 3 /m bits at a period T 0 /m; a third data conversion unit which inputs n data from among the pixel data D 2  and pixel data Dd 2  constituting the pixel data D 2  preceding by the period T 0 /m to execute logical sum operations a predetermined number (equal to or less than n) of times to convert the input n data to pixel data D 3  composed of N 3  bits including additional data corresponding to the predetermined number; and a fourth data conversion unit which converts the pixel data D 3  to the pixel data signal composed of one bit at the period T 0 /m. 
   Moreover, a pixel modulation method according to an another preferable embodiment of the invention, of converting pixel data D composed of N 1  bits input at a pixel period T 0 , to a pixel data signal composed of one bit, comprising: a first data conversion step of converting the pixel data D to pixel data D 1  expanded to N 2  bits (N 2 &gt;N 1 ) at the period T 0 ; a second data conversion step of converting the pixel data D 1  to pixel data D 2  composed of N 3 /m bits at a period T 0 /m; a third data conversion step of inputting n data from among the pixel data D 2  and pixel data Dd 2  constituting the pixel data D 2  preceding by the period T 0 /m to execute logical sum operations a predetermined number (equal to or less than n) of times to convert the input n data to pixel data D 3  composed of N 3  bits, including additional data corresponding to the predetermined number; and a fourth data conversion step of converting the pixel data D 3  to the pixel data signal composed of one bit at the period T 0 /m. 
   Other objects, features and advantages of he invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a conventional four-drum type image forming apparatus; 
       FIG. 2  is a block diagram showing the configuration of the image writing portion of the image forming apparatus; 
       FIG. 3  is a diagram for illustrating the disposition relation between two laser diodes; 
     FIG.  4 A and  FIG. 4B  are timing charts for illustrating the operation of a conventional pixel modulation circuit; 
       FIG. 5  is a block diagram of a pixel modulation circuit according to the present invention; 
       FIG. 6  is a block diagram of the data conversion circuit  2  shown in  FIG. 5 ; 
       FIG. 7  is a block diagram of a high precision four-bit serial conversion circuit to be used in the data conversion circuits  2  and  4 ; 
       FIGS. 8A ,  8 B,  8 C,  8 D,  8 E,  8 F,  8 G,  8 H and  8 I are timing charts for illustrating the operation of the data conversion circuit  2 ; 
       FIGS. 9A ,  9 B,  9 C and  9 D are timing charts for illustrating the operation of the pixel modulation apparatus according to the present invention; 
       FIG. 10  is a block diagram of the data conversion circuit  3  shown in  FIG. 5 ; 
       FIG. 11  is a diagram showing a data adding circuit to be used in the data conversion circuit  3 ; 
       FIG. 12  is a truth table of a decoder circuit to be used in the data conversion circuit  3 ; 
       FIG. 13  is a diagram showing the decoder circuit to be used in the data conversion circuit  3 ; 
       FIG. 14  is a diagram showing a DLL circuit to be used in the pixel modulation apparatus; 
       FIG. 15  is a diagram showing a controlled delay circuit to be used in the DLL circuit shown in  FIG. 14 ; 
       FIGS. 16A ,  16 B,  16 C,  16 D,  16 E,  16 F,  16 G,  16 H,  16 I,  16 J,  16 K,  16 L,  16 M,  16 N and  16 O are timing charts for illustrating the operation of the data conversion circuit  4 ; 
       FIG. 17  is a block diagram of the data conversion circuit  4  shown in  FIG. 5 ; 
       FIGS. 18A ,  18 B and  18 C are timing charts showing the operation of the pixel modulation circuit according to the present invention; and 
       FIG. 19  is a diagram showing a high precision twofold multiplied clock generating circuit to be used in the data conversion circuit  4 . 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 5  shows a pixel modulation circuit according to the present invention applied to a color printer using four color pieces of toner of yellow (Y), cyan (Cy), magenta (Mg) and black (Bk). The pixel modulation circuit is composed of four data conversion circuits  1 - 4 . The pixel modulation circuit is provided for each laser beam. The other configuration of the image writing portion provided with the pixel modulation circuit is the same as that shown in FIG.  2 . 
   Description of Data Conversion Circuit  1   
   Each of pixel data D (composed of six bits in this case) generated by picking up an object image with a scanner or the like and a write clock WK are input into a 6-to-32-bit data conversion circuit  1  for converting 6 bit data to 32 bit data. Then, the pixel data D are converted to 32 bit data D 1 . 
   The 6-to-32-bit data conversion circuit  1  is, for example, a 64-word random access memory (RAM). One word is composed of 32 bits. The pixel data D are input to the address lines of the RAM, and the pixel data D 1  are output from the word lines of the RAM as data D 131  to D 100  synchronized with read clocks CK 1  and CK 2 . The pixel data D is previously written into each of desired word data in the RAM by use of serial transfer lines including serial transferring clocks KS, transferring serial data DS and transferring data load signals LS. It is needless to say that the data conversion circuit  1  may be a read only memory (ROM) in which the contents have previously been written fixedly. 
   Description of Data Conversion Circuit  2   
   The pixel data D 1  are input into a 32-to-8-bit data conversion circuit  2 . The input pixel data D 1  is serially converted to 8-bit image data D 2  by means of input clocks K 1 . 
   As shown in  FIG. 6 , the data conversion circuit  2  is composed of eight 4-bit serial conversion circuits  11   a ,  11   b ,  11   c ,  11   d ,  11   e ,  11   f ,  11   g  and  11   h . It is desirable to use the 4-bit serial conversion circuit that is shown in FIG.  7  and is composed of only inverters and two-input inverters, both being suitable for high speed operation. 
   As clock inputs k 0 , k 1 , k 2  and k 3 , four-phase clocks K 10 , K 11 , K 12  and K 13 , which are respectively shown in  FIGS. 8D  to  8 G and are obtained by the dividing of a clock signal having the period of T 0 /4 (T 0  indicates a pixel period) shown in  FIG. 8A  into a frequency of one fourth of the frequency of the clock signal shown in  FIG. 8A , are respectively input. The clock signal having the period of T 0 /4 can easily be generated by means of a phase-locked loop (PLL) circuit. 
   Data d 3  are output to a serial data output ps 4  terminal in a region z 1  shown in  FIGS. 8A-8I  by the clock inputs k 0  and k 1 . Data d 2  are output to a serial data output ps 4  terminal in a region z 2  by the clock inputs k 1  and k 2 . Data d 1  are output to a serial data output ps 4  terminal in a region z 3  by the clock inputs k 2  and k 3 . Data d 0  are output to a serial data output ps 4  terminal in a region z 4  by the clock inputs k 3  and k 0 . Thereby the four-bit seal conversions of input data d 3  to d 0  are realized. 
   As shown in  FIG. 6 , as the input data d 3  to d 0  of the serial conversion circuits  11   a - 11   h , the following data are respectively input. As for the uppermost bit pixel data D 27 , data D 131 , D 123 , D 115  and D 107  are input. As for pixel data D 26 , data D 130 , D 122 , D 114  and D 106  are input. As for pixel data D 25 , data D 129 , D 121 , D 113  and D 105  are input. As for pixel data D 24 , data D 128 , D 120 , D 112  and D 104  are input. As for pixel data D 23 , data D 127 , D 119 , D 111  and D 103  are input. As for pixel data D 22 , data D 126 , D 118 , D 110  and D 102  are input. As for pixel data D 21 , data D 125 , D 117 , D 109  and D 101  are input. As for pixel data D 20 , data D 124 , D 116 , D 108  and D 100  are input. 
   Incidentally, for the ensuring of the operation of data conversion circuit  2 , it is desirable to generate the high order input data D 131 -D 116  of pixel data D 1  as shown in  FIG. 8H  by means of the clock CK 1  shown in  FIG. 8B , and to generate the low order input data D 115  to D 100  of the pixel data D 1  as shown in  FIG. 8I  by means of the clock CK 2  shown in FIG.  8 C. Thereby, the operation of the data conversion circuit  2  is stabilized. 
     FIGS. 9A  to  9 D are referred to while the data conversion operation mentioned above is described. The input 6-bit pixel data D having the period T 0  shown in  FIG. 9A  are expanded to the 32-bit pixel data D 1  having the period T 0  shown in FIG.  9 B. The 32-bit pixel data D 1  are then converted to the 8-bit pixel data D 2  having the period T 0 /4 as shown in FIG.  9 C. 
   Description of Data Conversion Circuit  3   
   The pixel data D 27  to D 20  are input into the data conversion circuit  3 . The configuration of the data conversion circuit  3  is shown in FIG.  10 . In  FIG. 10 , the pixel data D 27  to D 20  are latched by latch circuits  8   a  and  8   b  by use of a clock CK 3  having the period T 0 /4 and a predetermined phase to generate pixel data Da 7 , Da 6 , Da 5 , Da 4 , Da 3 , Da 2 , Da 1  and Da 0 , and Db 6 , Db 5 , Db 4 , Db 3 , Db 2 , Db 1  and Db 0  delayed from the pixel data Da 7  to Da 0 , respectively. The pixel data Da 7  to Da 0  and Db 6  to Db 0  are input into eight data adding circuit  10   a ,  10   b ,  10   c ,  10   d ,  10   e ,  10   f ,  10   g  and  10   h  having the same structure severally. The data adding circuits  10   a  to  10   h  respectively output converted pixel data D 37 , D 36 , D 35 , D 34 , D 33 , D 32 , D 31  and D 30 . Moreover, control signals s 1 , s 2 , s 3 , s 4 , s 5 , s 6  and s 7  are input to each of the data adding circuit  10   a  to  10   h . The control signals s 1  to s 7  are generated by a decoder  9  to which pulse width adding data L 2 , L 1  and L 0  are input. 
   The data adding circuits  10   a  to  10   h  are severally configured as an OR circuit of eight data Din, Dx 1 , Dx 2 , Dx 3 , Dx 4 , Dx 5 , Dx 6  and Dx 7 , as shown in FIG.  11 . Incidentally, because the other input terminal of a two-input NAND circuit to which the data Din is input is connected with a power supply C, the data Din is always output. The OR operation of the data Din with the other data Dx 1  to Dx 7  is executed when the control signals s 1  to s 7  take an H level, respectively. Then, data Dout is output. 
   In the data adding circuit  10   h , the pixel data Da 0 , Da 1 , Da 2 , Da 3 , Da 4 , Da 5 , Da 6  and Da 7  are input as the data Din, Dx 1 , Dx 2 , Dx 3 , Dx 4 , Dx 5 , Dx 6  and Dx 7 , respectively, and the converted pixel data D 30  is output. 
   In the data adding circuit  10   g  the pixel data Da 1 , Da 2 , Da 3 , Da 4 , Da 5 , Da 6 , Da 7  and Db 0  are input as the data Din, Dx 1 , Dx 2 , Dx 3 , Dx 4 , Dx 5 , Dx 6  and Dx 7 , respectively, and the converted pixel data D 31  is output. 
   In the data adding circuit  10   f , the pixel data Da 2 , Da 3 , Da 4 , Da 5 , Da 6 , Da 7 , Db 0  and Db 1  are input as the data Din, Dx 1 , Dx 2 , Dx 3 , Dx 4 , Dx 5 , Dx 6  and Dx 7 , respectively, and the converted pixel data D 32  is output. 
   In the data adding circuit  10   e , the pixel data Da 3 , Da 4 , Da 5 , Da 6 , Da 7 , Dab 0 , Db 1  and Db 2  are input as the data Din, Dx 1 , Dx 2 , Dx 3 , Dx 4 , Dx 5 , Dx 6  and Dx 7 , respectively, and the converted pixel data D 33  is output. 
   In the data adding circuit  10   d , the pixel data Da 4 , Da 5 , Da 6 , Da 7 , Db 0 , Db 1 , D 62  and Db 3  are input as the data Din, Dx 1 , Dx 2 , Dx 3 , Dx 4 , Dx 5 , Dx 6  and Dx 7 , respectively, and the converted pixel data D 34  is output. 
   In the data adding circuit  10   c , the pixel data Da 5 , Da 6 , Da 7 , Db 0 , Db 1 , Db 2 , Db 3  and Db 4  are input as the data Din, Dx 1 , Dx 2 , Dx 3 , Dx 4 , Dx 5 , Dx 6  and Dx 7 , respectively, and the converted pixel data D 35  is output. 
   In the data adding circuit  10   b , the pixel data Da 6 , Da 7 , Db 0 , Db 1 , Db 2 , Db 3 , Db 4  and Db 5  are input as the data Din, Dx 1 , Dx 2 , Dx 3 , Dx 4 , Dx 5 , Dx 6  and Dx 7 , respectively, and the converted pixel data D 36  is output. 
   In the data adding circuit  10   a , the pixel data Da 7 , Db 0 , Db 1 , Db 2 , Db 3 , Db 4 , Db 5  and Db 6  are input as the data Din, Dx 1 , Dx 2 , Dx 3 , Dx 4 , Dx 5 , Dx 6  and Dx 7 , respectively, and the converted pixel data D 37  is output. 
     FIG. 12  shows an example of a logical truth table for the generation of the control signals s 1  to s 7  on the basis of the pulse width adding data L 2  to L 0 . On such a truth table, the data adding circuits  10   a  to  10   h  add the data Dx 1  to Dx 7  logically as the value of the pulse width adding data L increases. When the value of the pulse width adding data L is zero, the data conversion circuit  3  outputs the pixel data D 2  as they are as pixel data D 3 . The following is each logical expression of the control signals s 1  to s 7 .
   S   1 = L   2 + L   1 + L   0     S   2 = L   2 + L   1     S   3 = L   2 +({double overscore ( L   1 )}{overscore (+)}{double overscore ( L   0 )}) S 4 =L 2     S   5 = L   2 ×({double overscore ( L   1 )}{overscore (×)}{double overscore ( L   0 )})   S   6 = L   2 × L   1     S   7 = L   2 × L   1 × L   0   
     FIG. 13  shows a circuit configuration of the decoder  9  of each logical expression. 
   Description of Data Conversion Circuit  4   
   The 8-bit pixel data D 3  is input into the data conversion circuit  4 , which converts data from eight bits to four bits. The 8-bit pixel data D 3  is converted into 1-bit laser control signal ON by mean of a clock CK 4  and a multi-phase clock k 2 , and the laser control signal ON is output from the data conversion circuit  4 . The multi-phase clock k 2  is generated by a DLL circuit shown in  FIG. 14. A  clock K having a period T 0 /4 is input into a delay circuit  12   a . Delay circuits  12   a ,  12   b ,  12   c ,  12   d ,  12   e ,  12   f ,  12   g ,  12   h  and  12   i  all have the same structure, and each is a variable delay circuit having a delay time changeable by a control signal Vd. The delay circuits  12   a - 12   i  can severally be configured by, for example, a CMOS circuit shown in FIG.  15 . Because the CMOS circuit shown in  FIG. 15  is composed of differential circuits, the CMOS circuit can stably realize its high speed operation. 
   The output signals of the delay circuits  12   a  and  12   i  are input into a phase comparison circuit  13 , and the phase comparison circuit  13  outputs an up-pulse U and a down-pulse D. The up-pulse U and the down-pulse D are input into a charge pump circuit  14 . The charge pump circuit  14  generates an error signal on the basis of the up-pulse U and the down-pulse D. The error signal is input into a control signal generation circuit  15 . The control signal generation circuit  15  converts the input error signal to the control signal Vd. The control signal Vd output from the control signal generation circuit  15  is input into each of the delay circuits  12   a  to  12   i . The DLL circuit shown in  FIG. 14  is controlled by the control signal Vd such that the phases of the output signals of the delay circuit  12   a  and  12   i  agree with each other. Consequently, output clocks K 20 , K 21 , K 22 , K 23 , K 24 , K 25 , K 26  and K 27  of the respective delay circuits  12   a ,  12   b ,  12   c ,  12   d ,  12   e ,  12   f ,  12   g  and  12   h  are the multi-phase clocks the phases of which are shifted from each other by T 0 /32 as shown in  FIGS. 16A ,  16 B,  16 C,  16 D,  16 E,  16 F,  16 G and  16 H respectively. The clock K 20  is also used as the clock CK 3  of the aforementioned data conversion circuit  3 . 
   The configuration of the data conversion circuit  4  is shown in FIG.  17 . Because the pixel data D 3  are latched by the clock CK 3  (or clock K 20 ), the pixel data D 3  is input into the data conversion circuit  4  at a timing shown in FIG.  16 I. The lower four bits D 33  to D 30  of the pixel data D 3  are latched by a latch circuit  7 . If the output clock K 24  is used as the clock CK 4 , data Dc 3 , Dc 2 , Dc 1  and Dc 0  of the latch circuit  7  are output as shown in FIG.  16 J. The higher four bit D 37  to D 34  of the pixel data D 3 , the data Dc 3  to Dc 0  and clocks K 20  to K 27  are input into two serial conversion circuits  5   a  and  5   b  and twofold multiplied clock generating circuit  6 . 
   It is preferable to configure the serial conversion circuits  5   a  and  5   b  in the configuration of  FIG. 7 , which is suitable for high speed operation. The clocks K 24 , K 26 , K 26 , K 20 , K 20 , K 22 , K 22  and K 24  are input into the serial conversion circuits  5   a  and  5   b  as the respective clock inputs k 0 , k 1 , k 2 , k 3 , k 4 , k 5 , k 6  and k 7  thereof. Moreover, the data D 37 , D 34 , Dc 3  and Dc 0  are input into the serial conversion circuit  5   a  as the data d 3 , d 2 , d 1  and d 0  thereof. The data D 36 , D 35 , Dc 2  and Dc 1  are input into the serial conversion circuit  5   b  as the data d 3 , d 2 , d 1  and d 0  thereof. Consequently, as shown in  FIGS. 16K and 16L , output signals DS 1  and DS 2  of the serial conversion circuit  5   a  and  5   b  are respectively output as the following serially converted data. That is, the pixel data D 37  and D 36  are output in a region (z 1 +z 2 ). The pixel data D 34  and D 35  are output in a region (z 3 +z 4 ). The pixel data D 33  and D 32  are output in a region (z 5 +z 6 ). The pixel data D 30  and D 31  are output in a region (z 7 +z 8 ). 
   It is preferable that the configuration of the twofold multiplied clock generating circuit  6  is a configuration shown in  FIG. 19  in the case where the serial conversion circuits  5   a  and  5   b  are configured as the configuration of FIG.  7 . The clocks K 25 , K 27 , K 21 , K 23 , K 27 , K 21 , K 23  and K 25  are input into the twofold multiplied clock generating circuit  6  as the clock inputs k 0 , k 1 , k 2 , k 3 , k 4 , k 5 , k 6  and k 7  thereof, respectively. In this case, a twofold multiplied clock x 2 k 1  is output as a signal shown in FIG.  16 M. That is, the twofold multiplied clock x 2 k 1  takes an L level in a region (z 2 +z 3 ) and a region (z 6 +z 7 ), and takes an H level in a region (z 4 +z 5 ) and a region (z 1 +z 8 ), as shown in FIG.  16 M. On the other hand, a twofold multiplied clock x 2 k 2  is output as a signal shown in FIG.  16 N. That is, the twofold multiplied clock x 2 k 2  takes the L level in the region (z 1 +z 8 ) and the region (z 4 +z 5 ), and takes the H level in the region (z 2 +z 3 ) and the region (z 6 +z 7 ), as shown in FIG.  16 N. The output signals DS 1  and DS 2  and the twofold multiplied clocks x 2 k 1  and x 2 k 2  are input into a selection circuit composed of three two-input NAND circuit. The selection circuit outputs the laser control signal ON in the regions z 1 , z 2 , z 3 , z 4 , z 5 , z 6 , z 7  and z 8 , which is shown in FIG.  16 O and is serially converted from the pixel data D 3  to D 30 . 
   The pixel modulation circuit, which is shown in FIG.  5  and is described above, can serially convert the laser control signal ON in the pixel period T 0  by dividing the 32-bit pixel data D 1 , which have been expanded arbitrarily from the input pixel data D, into 32 parts, which is more fine in comparison with the related art, as shown in FIG.  9 D. Consequently, the image processing, which is a pixel modulation technique to be used in the reproduction of a video (or gradation) image and is composed of techniques such as center pulse width modulation (PWM), left growing PWM, right growing PWM, contour processing in the reproduction of a highly fine character, and the like, can all be realized easily by the advance registration of data for the execution of the image processing in a memory in the data conversion circuit  1 . 
   For example, a 64-word memory (or a RAM) (one word is composed of 32 bits) using the input pixel data D (composed of six bits) as address inputs is prepared as the memory in the data conversions circuit  1  for the achievement of the aforementioned image processing. Desired data conversion pattern data (composed of 32 bits) corresponding to the input pixel data D (or the address data) is previously written in this RAM. 
   As a method of the registration, a serial transferring method is preferable. For the serial transfer, three signal lines for the serial transferring clocks KS, the transferring serial data DS and the transferring data load signals LS are generally used. The transferring serial data DS includes an address signal corresponding to the input pixel data D, desired data conversion pattern data (composed of 32 bits) and a signal for switching over the RAM to its write mode, and the transferring serial data DS transfers the signals and the data to the RAM. When the data conversion circuit  1  receives the load signals LS, the data conversion circuit  1  begins to write the transferring serial data DS into the RAM. When the writing has finished, the RAM is switched over to its read mode. Moreover, the pulse width of the laser control signal ON can be increased T 0 /32 by Tp/32 from a pulse width Tw defined by the pixel data D 1  to a pulse width (Tw+7T 0 /32) as the value of the pulse width adding data L increases, which is input into the data conversion circuit  3 , from zero to seven. Moreover, the operation is not limited by the output form of the laser control signal ON. Consequently, pulses, which are shown in  FIG. 18B , of the laser control signal ON can be generated with the addition of a predetermined pulse width to each of the pulses P 1 , P 2 , P 3  and P 4  of the conventional laser control signal ON (a state where the pulse width adding data L is 0 h) shown in  FIG. 18A  on the basis of the pulse width adding data L. Thereby, the light emission delay phenomenon being a fundamental characteristic of a laser diode can be cancelled equivalently. Thus, the laser emission signal that has been subjected to a desired control can easily be obtained as shown in FIG.  18 C. All of the components of the pixel modulation circuits can be realized by a pure CMOS semiconductor process, which can highly integrates semiconductor elements. 
   Incidentally, although the descriptions concerning the aforementioned embodiment are made on the assumption that the laser beam is used as a beam for forming an image, any beam may be applied to the present invention as long as the beam can form an image. 
   According to the present embodiment, the input pixel data D can be expanded finely based on the pixel period, and consequently the laser control signal ON suitable for various images such as video (gradation) images, character images and the like can easily be generated. 
   Moreover, because a pulse width addition function for the generation of the laser control signal ON in order that a desired laser emission can be obtained from input pixel data can be realized, the modulation of the quantity of laser light more accurate than any other related art can be performed. Consequently, the high image quality can be achieved. 
   Moreover, because all of the components of the pixel modulation apparatus can be structured by a pure CMOS process, the pixel modulation apparatus of the present invention can be realized cheap in cost. Consequently, the pixel modulation apparatus of the present invention is advantageous to a multi-beam/multi-drum type laser beam image forming apparatus, which needs a plurality of pixel modulation apparatus. 
   In other words, the foregoing description of embodiments has been given for illustrative purpose only and not to be construed as imposing any limitation in every respect. 
   The scope of the invention is, therefore, to be determined solely by the following claims and not limited by the text of the specifications and alterations made within a scope equivalent to the scope of the claims falling within the true sprit and scope of the invention.

Technology Category: h