Patent Document

FIELD OF THE INVENTION 
     The present invention relates generally to antifuse circuits in integrated circuit devices. More specifically, the present invention relates to methods and apparatus for improving the gate oxide reliability in an antifuse latch circuit. 
     BACKGROUND OF THE INVENTION 
     Antifuse latch circuits may be included in integrated circuit memory devices as part of an address detection circuit. Address detection circuits monitor the row and column addresses of integrated memory cell arrays and enable a redundant row or column within the array when the address of a defective row or column is received. U.S. Pat. No. 5,631,862 to Cutter et al., assigned to the assignee of the present invention and incorporated by reference herein in its entirety, discloses an antifuse bank address detection circuit that includes a bank of self-decoupling antifuse circuits. 
     For purposes of discussion, an exemplary self-decoupling antifuse latch circuit  10  is shown in FIG.  1 . In a program mode, antifuse latch circuit  10  may be programmed to blow antifuse  28 . In a normal operation mode, latch output signal FA may be read to determine whether antifuse  28  has been blown or not. For example, latch output signal FA will be a logic high when antifuse  28  is blown and latch output signal FA will be a logic low when antifuse  28  is not blown. 
     Antifuse latch circuit  10  includes an output latch  12  and a latch control section  14 . Output latch  12  includes three PMOS transistors  16 ,  18 ,  20 , an inverter  22 , and two NMOS transistors  24 ,  26 . PMOS transistors  18 ,  20  are coupled in parallel with their sources coupled to the drain of PMOS transistor  16  and their drains coupled to the input of inverter  22 . The gate of PMOS transistor  18  is coupled to signal RDFUS and the gate of PMOS transistor  20  is coupled to the output of inverter  22 . The source of PMOS transistor  16  is coupled to voltage V cc  and its gate is coupled to signal MRG. NMOS transistors  24 ,  26  are coupled in series between the drains of PMOS transistors  18 ,  20  and ground. The gate of NMOS transistor  24  is coupled to signal RDFUS and the gate of NMOS transistor  26  is coupled to the output of inverter  22 . The output of inverter  22  is the latch output signal FA. 
     Latch control section  14  includes three NMOS transistors  30 ,  32 ,  34  and an antifuse  28 . Antifuse  28  is coupled between signal CGND and the drain of NMOS drop transistor  30 . As used herein, NMOS drop transistor  30  is also known as the “protection device.” The gate of protection device  30  is coupled to voltage V CCP  through protection device gate input  36  and its source is coupled to the drain of NMOS transistor  32  at control node  38 . The gate of NMOS transistor  32  is coupled to the fuse selection signal FS and its source is coupled to signal BSEL. NMOS transistor  34  is coupled between control node  38  and the input of inverter  22  in the output latch  12 . The gate of NMOS transistor  34  is coupled to signal DVC 2 F, which is typically V CC /2 + NMOS threshold voltage, V t . Signal DVC 2 F may be used to limit the amount of voltage across the dielectric of unblown antifuses so that the antifuse dielectric does not receive a higher voltage stress across it than the memory cells in the memory array. For example, if DVC 2 F=V CC /2 + NMOS V t , then the maximum voltage across an unblown antifuse will be V CC /2, which is what the cell plate of the array is typically set to. 
     Unblown antifuse  28  forms an open circuit. To blow antifuse  28 , thus reducing its resistance and allowing current to flow through it, a voltage of approximately +12 Vdc is temporarily placed across its two terminals. This is accomplished by switching signal BSEL to ground, turning on NMOS transistor  32  by ensuring that fuse selection signal FS is a logic high and switching signal CGND to +12 Vdc. Note that protection device  30  does not need to be turned on to complete the path from antifuse  28  to ground since the gate of protection device  30  is already coupled to voltage V CCP . V CCP  is typically V CC +1.4 volts, or V CC + the threshold voltage, V T , of the access device+an additional voltage margin to cover process variation. While in this program mode, protection device  30  limits the maximum voltage applied to control node  38  to the voltage V CCP  minus the threshold voltage V T  of protection device  30 . Thus, protection device  30  limits the drain-to-gate voltage of NMOS transistor  32  and the source-to-gate voltage of NMOS transistor  34  to limit the breakdown of the gate oxide and improve reliability. However, when antifuse  28  is blown, a large voltage stress is placed across the gate oxide of protection device  30 . This high voltage stress can cause pinholes in the gate oxide of protection device  30  during the burn-in stress portion of the manufacturing process and can reduce the reliability of the antifuse latch circuit  10  during normal operation. 
     Thus, it would be advantageous to develop a technique and device for reducing or removing the high voltage stress placed across the gate oxide of the protection device  30  once the antifuse  28  has been blown and during normal operation of an antifuse latch circuit. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention relates to methods and apparatus for improving the gate oxide reliability in an antifuse latch circuit. 
     An antifuse latch circuit with improved gate oxide reliability according to the present invention includes a voltage converter circuit configured to selectively alter the voltage level applied to the gate input of a protection device of the antifuse latch circuit upon receiving a signal. In one embodiment of the invention, the voltage converter is configured to selectively reduce or increase the voltage level of a single signal to be applied to the protection device gate input. In another embodiment of the invention, the voltage converter is configured to selectively switch the protection device gate input between at least two voltage levels. 
     In yet another embodiment of the invention, the voltage converter circuit comprises a cascade voltage switch logic circuit coupled to the gates of two PMOS transistors. Each PMOS transistor is coupled between the protection device gate input and a separate and distinct voltage level. The cascade voltage logic circuit is configured to selectively switch the protection device gate input between the two voltage levels coupled to the two PMOS transistors. 
     A method of improving the gate oxide reliability in an antifuse latch circuit according to the present invention comprises applying a signal at a first voltage level to the gate of a protection device of an antifuse latch circuit during the programming of the antifuse and applying the signal at a second voltage level to the gate of the protection device during the reading of the antifuse and during normal operation. 
     Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The drawings illustrate exemplary embodiments of the present invention, wherein, like reference numerals refer to like parts in different views or embodiments in the drawings. 
     FIG. 1 is a schematic diagram of an exemplary antifuse latch circuit suitable for use with the present invention. 
     FIG. 2 is a block diagram of the antifuse latch circuit of FIG. 1 coupled to a voltage converter circuit configured to selectively reduce or increase the voltage level of a single signal to be applied to the gate input of a protection device of the antifuse latch circuit. 
     FIG. 3 is a block diagram of the antifuse latch circuit of FIG. 1 coupled to a voltage converter circuit configured to selectively switch the protection device gate input of the antifuse latch circuit between two voltage levels. 
     FIG. 4 is a schematic diagram of the antifuse latch circuit of FIG. 1 coupled to a voltage converter circuit comprising a cascade voltage switch logic circuit coupled to the gates of two PMOS transistors. 
     FIG. 5 is a block diagram of a computer system comprising a memory device using an address detection circuit with an improved antifuse latch circuit according to the present invention. 
     FIG. 6 is a flow chart of a method for improving the gate oxide reliability in an antifuse circuit including an antifuse coupled to a switching device. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As discussed above, protection device  30  of FIG. 1 provides gate oxide protection for NMOS transistors  30 ,  32 . During programming of antifuse  28 , such protection is necessary since the large voltage (typically around +12 Vdc) provided by signal CGND in order to blow antifuse  28  would be present at control node  38 , thus reducing the gate oxide reliability of NMOS transistors  30 ,  32 . However, during reading of the fuses and during normal operation, signal CGND is switched to a ground potential. Therefore, the drain-to-gate voltage of NMOS transistor  32  and the source-to-gate voltage of NMOS transistor  34  no longer need to be limited to V CCP  minus the threshold voltage V T  of protection device  30 . Thus, in order to improve the gate oxide reliability of protection device  30 , the voltage applied to the gate of protection device  30  may be lowered. 
     FIG. 2 shows a block diagram of an embodiment of an improved antifuse latch circuit  40  according to the present invention. Improved antifuse latch circuit  40  may include antifuse latch circuit  10 , as shown in FIG. 1, coupled to a voltage converter circuit  42  through protection device gate input  36 . V CC , may be approximately 2 volts, V CCP  may be approximately 3.4 volts and V CCR &lt;V CCP . Voltage converter circuit  42  is configured to receive voltage V CCP , convert it to a lower voltage V CCR  (FIG. 3) and output the lower voltage V CCR  onto the protection device gate input  36 . This can be accomplished by attenuating V CCP , as is known in the art. As used herein, voltage V CCR  is at a voltage level sufficiently below V CCP  to provide the necessary gate oxide protection to protection device  30  of FIG.  1 . Voltage V CCR  may be a voltage signal typically used in integrated circuit devices and available to antifuse latch circuits. 
     Voltage converter circuit  42  may also be configured to convert voltage V CCP  to the lower voltage upon receipt of signal AF 13  Prog. Thus, when signal AF 13  Prog indicates that the antifuse latch circuit  10  is in program mode, voltage converter circuit  42  will pass voltage V CCP  through to protection device gate input  36 . Conversely, when signal AF 13  Prog indicates that the antifuse latch circuit  10  is in normal operation mode, voltage converter circuit  42  will reduce the voltage V CCP  it receives and output V CCR  to the protection device gate input  36 . One of ordinary skill in the art will recognize that voltage converter circuit  42  may, in the alternative, be configured to receive a lower voltage and increase the output on the protection device gate input  36  to voltage V CCP  only during program mode. 
     FIG. 3 shows a block diagram of another embodiment of an improved antifuse latch circuit  46  according to the present invention. Improved antifuse latch circuit  46  may include the antifuse latch circuit  10 , as shown in FIG. 1, coupled to a voltage converter circuit  44  through protection device gate input  36 . Voltage converter circuit  44  is configured to switch its output onto protection device gate input  36  between voltages V CCP  and V CCR . Voltage converter circuit  44  may also be configured to switch its output between V CCP  and V CCR  in response to signal AF 13  Prog. Thus, when signal AF 13  Prog indicates that the antifuse latch circuit  10  is in program mode, voltage converter circuit  44  will switch voltage V CCP  to the protection device gate input  36 . Conversely, when signal AF 13  Prog indicates that the antifuse latch circuit  10  is in normal operation mode, voltage converter circuit  44  will switch voltage V CCR  to the protection device gate input  36 . 
     FIG. 4 shows a schematic diagram of the latch control section  14  of the antifuse latch circuit  10  of FIG. 1 coupled to a voltage converter circuit  50 . For simplicity, the output latch  12  of the antifuse latch circuit  10  of FIG. 1 is not shown. Like voltage converter circuit  44  of FIG. 3, voltage converter circuit  50  is configured to switch its output onto protection device gate input  36  between voltages V CCP  and V CCR . Voltage converter circuit  50  comprises a cascade voltage switch logic circuit  52  coupled to the gates of two PMOS transistors  54 ,  56 . As used herein, PMOS transistors  54 ,  56  are also referred to as “PMOS pull-up devices”  54 ,  56 . 
     Cascade voltage switch logic circuit  52  comprises two PMOS transistors  58 ,  60 , two NMOS transistors  62 ,  64 , and two inverters  66 ,  68 . The sources of PMOS transistors  58 ,  60  are each coupled to voltage V CCP . The gate of PMOS transistor  58  is coupled to the drain of PMOS transistor  60  at node  70  and the gate of PMOS transistor  60  is coupled to the drain of PMOS transistor  58  at node  72 . The sources of NMOS transistors  62 ,  64  are coupled to ground. The drain of NMOS transistor  62  is coupled to the drain of PMOS transistor  58  at node  72 . The gate of NMOS transistor  62  is coupled to the output of inverter  68  and the input of inverter  66 . The drain of NMOS transistor  64  is coupled to the drain of PMOS transistor  60  at node  70  and its gate is coupled to the output of inverter  66 . The input of inverter  68  is coupled to signal AF 13  Prog. 
     Signal AF 13  Prog is also coupled to the gate of PMOS transistor  56 . The gate of PMOS transistor  54  is coupled to the cascade voltage switch logic circuit  52  at node  70 . The protection device input gate  36  of antifuse latch circuit  10  is coupled to the drains of PMOS transistors  54 ,  56 . The source of PMOS transistor  54  is coupled to voltage V CCP  and the source of PMOS transistor  56  is coupled to V CCR . 
     When signal AF 13  Prog is at logic high (V CCR ), indicating program mode has been entered, PMOS transistor  56  is turned off. Additionally, NMOS transistor  64  is turned on and a logic low passes from ground to node  70 . The logic low at node  70  turns on PMOS transistor  54  to pull protection device gate input  36  to a voltage level of V CCP . Therefore, during programming of antifuse  28 , protection-device gate input  36  may be switched to a voltage V CCP  by setting signal AF 13  Prog to a high logic level in order to provide gate oxide protection for NMOS transistors  30 ,  32 . 
     When signal AF 13  Prog is at logic low, indicating normal operation mode has been entered, NMOS transistor  64  is turned off and NMOS transistor  62  is turned on. As NMOS transistor  62  is turned on, node  72  is pulled down to ground. The logic low level at node  72  turns on PMOS transistor  60 , which allows a high logic level of V CCP  to pass to node  70  and turn PMOS transistor  54  off. Further, the logic low AF 13  Prog signal turns on PMOS transistor  56  to pull protection device gate input  36  to a level of V CCR . Therefore, during reading of antifuse  28  and normal operation of antifuse latch circuit  10 , protection device gate input  36  may be lowered to a voltage V CCR  by setting signal AF 13  Prog to a low logic level in order to remove the large voltage stress placed across the gate oxide of protection device  30 . 
     FIG. 5 is a block diagram of a computer system  74  employing an improved antifuse latch circuit  78  according to the present invention. Computer system  74  may include computer circuitry  80  coupled to input device  82 , output device  84  and data storage device  86 . Computer circuitry  80  typically performs computer functions such as executing software to perform desired calculations and tasks. Computer circuitry  80  may include a processor  90 , a memory device  76  and control circuitry  88 . Control circuitry  88  may be used to produce the signals described in connection with FIGS. 2 through 4. 
     Input device  82  may include, by way of example only, an Internet or other network connection, a mouse, a keypad or any device that allows an operator to enter data into the computer circuitry  80 . Output device  84  may include, by way of example only, a printer or a video display device. Data storage device  86  may include, by way of example only, a drive that accepts hard and floppy discs, a tape cassette, CD-ROM or DVD-ROM drives. Memory device  76  may include an address detection circuit  92  comprising at least one antifuse latch circuit  78 . Antifuse latch circuit  78  may comprise any one of the embodiments  42 ,  44  or  50  described above in connection with FIGS. 2 through 4. 
     FIG. 6 is a flow chart of a method  600  for improving the gate oxide reliability in an antifuse circuit including an antifuse coupled to a switching device. Method  600  may include providing  602  a protection device between the antifuse and the switching device. Method  600  may further include applying  604  a programming voltage to the switching device through the protection device during programming of the antifuse and applying  606  an operating voltage lower than the programming voltage to the switching device through the protection device during times other than during the programming of the antifuse. 
     Another method is disclosed for improving the gate oxide reliability in an antifuse circuit including an antifuse and a protection device coupled between the antifuse and at least one transistor or switching device. The method may include in a first mode, limiting a maximum voltage coupled to the at least one transistor through the protection device by applying a first signal at a first voltage level to the protection device. The method may further include, in a second mode, applying a second signal at a second voltage level, less than the first voltage level, to the protection device. According to this method, the antifuse may be blown, or programmed, in the first mode. Limiting the maximum voltage coupled to the at least one transistor increases the gate oxide reliability of the at least one transistor during the first mode. Applying the second signal at the second voltage level to the protection device increases the gate oxide reliability of the protection device during the second mode. 
     Applying the second signal at the second voltage level to the protection device may include receiving the first signal at the first voltage level, attenuating the first signal from the first voltage level to the second voltage level and applying the second voltage level to the protection device. Applying the first signal at the first voltage level in the first mode and the second signal at the second voltage level in the second mode to the protection device may include receiving the first signal at the first voltage level and the second signal at the second voltage level, switching an input to the protection device to the first signal during the first mode and switching the input to the protection device to the second signal during the second mode. 
     According to the circuit, system, and method of the present invention, when signal AF 13  Prog is low, indicating normal operation in which V CCR  is applied to the gate of the protection device, there still exists a voltage of V CCP  across the gate oxide of a p-channel transistor in a voltage translator circuit. While this voltage of V CCP  across the gate oxide of a p-channel transistor may still raise a potential gate oxide reliability problem for that p-channel transistor, this is still a significant improvement over conventional devices and methods. 
     The improvement in gate oxide reliability comes from placing the stress of V CCP  across a single gate rather than hundreds or thousands of antifuse protection gates in a typical memory device. For example, in prior art devices, all of the gates of protection devices have V CCP  connected to them, thus, all blown antifuses would have V CCP  across the gate oxide. A typical 128 Mb dynamic random access memory (DRAM) has approximately 4000 antifuses on it. For a typical die, about half of the approximately 4000 antifuses are programmed and, thus, the protection devices attached to these antifuses are the candidates for gate oxide reliability problems. Therefore, the circuit, system, and method of the present invention significantly reduces the gate oxide reliability problem of conventional devices and methods, by reducing the gate oxide area on the integrated circuit die exposed to the high programming voltage, V CCP . 
     While the present invention has been disclosed in detail, those of ordinary skill in the art will recognize and appreciate that the invention is not so limited. Those of ordinary skill in the art will recognize and appreciate that many additions, deletions and modifications to the disclosed embodiment and its variations may be implemented without departing from the scope of the invention, which is limited only by the appended claims and their legal equivalents.

Technology Category: g