Patent Document

BACKGROUND 
       [0001]    Higher memory density is always in demand to provide smaller devices with higher memory capacity. Forming memory devices laterally on a surface of a semiconductor chip uses a great deal of chip real estate. Improved memory devices are needed with new configurations to further increase memory density beyond traditional laterally formed memory devices. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0002]      FIG. 1  shows a memory device according to an embodiment of the invention. 
           [0003]      FIG. 1A  shows a cross section along line  1 A- 1 A from  FIG. 1  according to an embodiment of the invention. 
           [0004]      FIG. 1B  shows a cross section along line  1 B- 1 B from  FIG. 1  according to an embodiment of the invention. 
           [0005]      FIG. 2A  shows a memory device during an erase operation according to an embodiment of the invention. 
           [0006]      FIG. 2B  shows a block diagram of a portion of the memory device from  FIG. 2A  during an erase operation according to an embodiment of the invention. 
           [0007]      FIG. 3  shows a memory device during a program operation according to an embodiment of the invention. 
           [0008]      FIG. 4  shows a memory device during a read operation according to an embodiment of the invention. 
           [0009]      FIG. 5  shows selected stages of forming a memory device according to an embodiment of the invention. 
           [0010]      FIG. 6  shows an information handling system using a memory device according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and logical, electrical changes, etc. may be made. 
         [0012]    The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a substrate, such as a wafer or die, regardless of the orientation of the substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the substrate, regardless of the orientation of the substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
         [0013]      FIGS. 1 ,  1 A, and  1 B show a memory device  100  formed on a substrate  102 . A charge storage layer(s)  112  (e.g., a combination of a tunnel dielectric layer, a polysilicon layer, and a charge blocking layer; a combination of a nitride layer, an oxide layer, and a nitride layer; or other any other layer or combination of layers that can provide a charge storage function, whether currently known or future developed), substantially surrounds an elongated body region  110  to form a respective charge structure corresponding to each of a plurality of gates  114  (which may also substantially surround respective cross sections of the elongated body region  110  and charge storage layer(s)  112 ). A first select gate  120  and a second select gate  122  are shown to selectively couple the elongated body region  110  to drain region  132  and a source region  130 , respectively. A dielectric  104  can fill in spaces between components such as those described above. 
         [0014]      FIG. 1A  shows an embodiment where the elongated body region  110  forms a “U” shape with a pair of upward facing ends  111 ,  113 . Another example configuration (not shown) includes a linear, vertical, elongated body region  110  with one end facing upward, and the other end facing downward. Another example configuration (not shown) includes a horizontal, linear, elongated body region  110  with ends on either side. Embodiments with two upward facing ends,  111 ,  113 , such as the “U” shaped configuration, can enable easier formation of some components at the ends  111 ,  113  of the elongated body region  110  during manufacture, compared to embodiments where components are formed deeper in the structure. 
         [0015]    In one example, the elongated body region  110  is formed from a p type semiconductor material, such as p-type polysilicon. The elongated body region  110  can be formed in multiple process steps, such as where a first end  111  is formed in a different polysilicon deposition step than that used to form other portions of the elongated body region  110 , such as second end  113 . Accordingly, in at least some embodiments, first end  111  may be higher than second end  113 . A source region  130  and a drain region  132  are shown coupled to the first end  111  and the second end  113  of the elongated body region  110 , respectively. In one example, the source region  130  and the drain region include n type semiconductor material, such as n+ polysilicon. In operation, the pathway of source region  130 , to elongated body region  110 , to drain region  132  acts as an n-p-n transistor, with select gates  120 ,  122 , and gates  114  operating to allow, or inhibit signal transmission along the way. 
         [0016]    A source line  126  and a data line, such as bitline  128 , are shown coupled to the source region  130  and the drain region  132  respectively. In one embodiment, a plug  124  is used to directly couple (e.g., directly physically connect to form an electrical connection, or otherwise form an electrical connection without a potential for a n-p or p-n junction breakdown) the bitline  128  to the drain region  132 . Each of the source line  126 , bitline  128  and plug  124  can comprise, consist of, or consist essentially of metal, such as aluminum, copper, or tungsten, or alloys of these or other conductor metals. In the present disclosure, the term “metal” further includes metal nitrides, or other materials that operate primarily as conductors. 
         [0017]    As noted above,  FIG. 1  shows the drain region  132  directly coupled to the plug  124 , which effectively couples the drain region  132  to the bitline  128 . The source region  130  is shown directly coupled to the source line  126 . The elongated body region  110  is also directly coupled to the source line  126 . 
         [0018]    The cross section along line  1 B- 1 B shows the select gates  120  and  122 . As can be seen in the cross section, in one embodiment, the select gates  120  and  122  are substantially continuous along a row. In this configuration, actuation of a select gate  120  or  122  actuates a plurality of elongated body regions at a time. 
         [0019]    The cross section shown along line  1 A- 1 A shows a number of drain regions  132  and a source region  130 . As can be seen in the cross section, in one embodiment, the drain regions  132  are separate, while the source region  130  is substantially continuous, with a single source region  130  used for a plurality of elongated body regions  110 . In one example the source region  130  substantially surrounds a cross section of a first end  111  of each of a plurality of elongated body regions  110 . 
         [0020]    By directly coupling the elongated body region  110  to the source line  126 , the elongated body region  110  has the ability to be biased, and operate less as a floating body element. Biasing of the elongated body region  110  via a direct coupling can provide reliable memory operations such as an erase operation in particular. 
         [0021]    An example erase operation, according to an embodiment of the invention, is illustrated with respect to  FIGS. 2A and 2B . A memory device  200 , similar to embodiments described above, is shown with an example memory cell string  202  circled in the figures. According to one such erase operation embodiment, with the bitline  228  and select gates  220 ,  222  of string  202  floating, the source line  226 , and thus the elongated body region  210  of the string  202 , is biased to an erase voltage (e.g., approximately 20 volts), and the gates  214  of the string  202  are biased to a selected voltage (e.g., approximately 0 volts). Given the provided example biasing voltages, the select gates  220 ,  222  of string  202  are thus coupled up to approximately 15 volts, while the bit line  228  (and plug  124 ) is coupled up to approximately 20 volts. The potential difference between the body region  110  and gates  214  (e.g., 20 volts to zero volts) is used to erase stored charge from the charge storage structure adjacent to each individual gate  214  in the memory cell string  202 . 
         [0022]    Because the elongated body region  210  is directly coupled to the source line  226 , the elongated body region  210  is biased when a bias is applied to the source line  226 . Direct coupling between the elongated body region  210  and the source line  226  provides a charge pathway between the elongated body region  210  and the source line  226  that avoids junction breakdown between an n-type region and a p type region. 
         [0023]    In  FIG. 2B , the direct coupling of the elongated body region  210  to the source line  226  can be seen at a first end  211  of the elongated body region  210 . In contrast, a second end  213  of the elongated body region  210  is indirectly coupled to the bitline  228  through the drain region  232 . 
         [0024]      FIG. 3  shows a memory device  200  undergoing an example program operation according to an embodiment of the invention. The memory device  200  from previous Figures is used as an example. As in  FIG. 2A , an example memory cell string  202  is circled. 
         [0025]    With  FIG. 3  as a reference, the bitline  228 , source line  226  and source select gate  222  are biased to respective program enable voltages (e.g., approximately zero volts each). A selected gate  314  is biased with a program voltage (e.g., approximately 20 volts), while the drain select gate  220  of the selected string  202  is biased to, e.g., approximately 2 volts. The potential difference between the selected gate  314  and the body region of the selected string  202  (e.g., 20 volts to zero volts) is used to transfer charge to the charge storage structure adjacent to the selected gate  314  in the selected memory cell string  202 . To avoid programming a memory cell corresponding to selected gate  314  in the adjacent, unselected string, the drain select gate of that string can be biased to, for example, approximately zero volts. Unselected gates  214  are biased with an inhibit voltage (e.g., approximately 10 volts) to couple up the body region of the unselected string to an inhibit voltage. 
         [0026]      FIG. 4  shows a memory device  200  undergoing an example read operation according to an embodiment of the invention. The memory device  200  from previous Figures is used as an example. As in previous Figures, an example memory cell string  202  circled. 
         [0027]    With  FIG. 4  as a reference, the bitline  228  is biased to, for example, approximately 0.5 volts, and the source line  226  is biased to, for example, approximately zero volts. A selected gate  314  is biased with a read voltage (e.g., between approximately 0 volts and approximately 4 volts, such as depending upon what program state is being read), while the drain select gate  220  of the selected string  202  is biased to, e.g., approximately 2 volts. Unselected gates  214  are biased to a pass voltage (e.g., approximately 6 volts) to permit a signal to pass along the elongated body region of the selected string. If gate  314  is erased, then the signal will pass through the elongated body region of the selected string and be detected. To avoid reading a memory cell corresponding to selected gate  314  in an adjacent, unselected string, the drain select gate of that string can be biased to, for example, approximately zero volts. 
         [0028]      FIG. 5  illustrates an example process flow to form selected portions of a memory device according to an embodiment of the invention. In particular, the example process flow of  FIG. 5  illustrates one method of directly coupling an elongated body region to a sourceline. Operation  510  illustrates a planarization and etch stop operation. In one embodiment, an etch stop layer  512  is a silicon nitride (SiN) layer. Operation  520  illustrates a dielectric layer  522  deposition and patterning step. A number of openings  524  are shown formed in the dielectric layer  522  by etching or other suitable process. Operation  530  illustrates formation of source regions and drain regions by filling in the number of openings  524  with an n doped semiconductor. In one embodiment, the number of openings  524  are filled with an n+ polysilicon material 
         [0029]    Operation  540  illustrates formation of a second number of openings  542  within the filled portion that will become source regions. In operation  550 , the second number of openings  542  are filled to form an extension of the elongated body regions. In one example, the second number of openings  542  are filled with the same material as the elongated body region. In one example, the second number of openings  542  are filled with p+ polysilicon. Operation  560  illustrates a routing layer formation. Sourcelines  562 , plugs  564  and bitlines  566  may be formed as part of the routing layer formation. 
         [0030]    An embodiment of an information handling system such as a computer is included in  FIG. 6  to show an embodiment of a high-level device application for the present invention.  FIG. 6  is a block diagram of an information handling system  600  incorporating a memory device according to embodiments of the invention as described above. Information handling system  600  is merely one embodiment of an electronic system in which decoupling systems of the present invention can be used. Other examples include, but are not limited to, tablet computers, cameras, personal data assistants (PDAs), cellular telephones, MP3 players, aircraft, satellites, military vehicles, etc. 
         [0031]    In this example, information handling system  600  comprises a data processing system that includes a system bus  602  to couple the various components of the system. System bus  602  provides communications links among the various components of the information handling system  600  and may be implemented as a single bus, as a combination of busses, or in any other suitable manner. 
         [0032]    Chip assembly  604  is coupled to the system bus  602 . Chip assembly  604  may include any circuit or operably compatible combination of circuits. In one embodiment, chip assembly  604  includes a processor  606  that can be of any type. As used herein, “processor” means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit. 
         [0033]    In one embodiment, a memory device  607  is included in the chip assembly  604 . In one embodiment, the memory device  607  includes a NAND memory device according to embodiments described above. 
         [0034]    In one embodiment, additional logic chips  608  other than processor chips are included in the chip assembly  604 . An example of a logic chip  608  other than a processor includes an analog to digital converter. Other circuits on logic chips  608  such as custom circuits, an application-specific integrated circuit (ASIC), etc. are also included in one embodiment of the invention. 
         [0035]    Information handling system  600  may also include an external memory  611 , which in turn can include one or more memory elements suitable to the particular application, such as one or more hard drives  612 , and/or one or more drives that handle removable media  613  such as compact disks (CDs), flash drives, digital video disks (DVDs), and the like. A semiconductor memory die constructed as described in examples above is included in the information handling system  600 . 
         [0036]    Information handling system  600  may also include a display device  609  such as a monitor, additional peripheral components  610 , such as speakers, etc. and a keyboard and/or controller  614 , which can include a mouse, trackball, game controller, voice-recognition device, or any other device that permits a system user to input information into and receive information from the information handling system  600 . 
         [0037]    While a number of embodiments of the invention are described, the above lists are not intended to be exhaustive. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon studying the above description.

Technology Category: 3