Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of U.S. Provisional Application No. 60/531,609, filed Dec. 23, 2003, which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The invention relates generally to the field of oscillators. More specifically, this invention relates to voltage controlled oscillators for signal generation in wireless communication applications.  
       BACKGROUND OF THE INVENTION  
       [0003]     A voltage-controlled oscillator (VCO) is a circuit that produces an oscillating signal using amplification, feedback and a resonant circuit to generate a repeating voltage waveform, such that its output frequency is proportional to its input voltage.  
         [0004]     In wireless communication applications, VCOs operate over large frequency ranges. VCO&#39;s generally comprise a tank circuit and an amplifier circuit, operation of which will be well known. Biasing of such circuits is also known and described in U.S. Pat. No. 6,674,333 to Peckham et al, which describes a method for operating a band switchable VCO in different frequency bands. In typical band switching circuits, biasing of the amplifier or a tank circuit introduces noise which results in phase noise being present in the output of the VCO.  
         [0005]     It is, therefore, desirable to provide a method and apparatus for reduced noise band switching circuits.  
       SUMMARY OF THE INVENTION  
       [0006]     It is an object of the present invention to obviate or mitigate at least one disadvantage of previous voltage control oscillator circuits.  
         [0007]     In a first aspect, the present invention provides a low-phase noise voltage control oscillator (VCO) comprising a voltage source for supplying a control voltage to the VCO core; a phase lock loop, having an output connected to an input of the voltage source; a VCO core, including an amplifier circuit and a tank circuit; having an output connected to an input of the phase lock loop; a capacitance divider circuit attenuator, located between the voltage source and the VCO core, for reducing noise from the voltage source to the VCO core to reduce frequency variation of the voltage source.  
         [0008]     In a further embodiment, there is provided a method of reducing noise in a voltage control oscillator (VCO) comprising the steps of providing an attenuated voltage to a VCO core comprising an amplifier circuit and a tank circuit; and biasing the amplifier circuit via an amplifier bias including amplifier switches and the tank circuit via a tank bias including tank switches, to reduce noise in an output of the VCO core.  
         [0009]     Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:  
         [0011]      FIG. 1  is prior art of a block diagram of for a typical VCO;  
         [0012]      FIG. 2  is a graph of frequency versus voltage for a typical VCO;  
         [0013]      FIG. 3  is a block diagram outlining the general structure of the VCO;  
         [0014]      FIG. 4  is a graph of frequency versus voltage for a VCO of the present invention;  
         [0015]      FIG. 5  is a diagram of a first embodiment of an attenuator;  
         [0016]      FIG. 6  is a diagram of a second embodiment of an attenuator;  
         [0017]      FIG. 6A  is a graph showing the relationship between an input voltage and an output voltage of the attenuator of  FIG. 6 ;  
         [0018]      FIG. 7  is a diagram of a third embodiment of an attenuator;  
         [0019]      FIG. 8  is a diagram of the bias control, the amplifier bias and the VCO core;  
         [0020]      FIG. 8   a  is a graph showing a set of control signals for the apparatus of  FIG. 8 ; and  
         [0021]      FIG. 9  is a diagram of the bias control, the tank bias and the VCO core. 
     
    
     DETAILED DESCRIPTION  
       [0022]     Generally, the present invention provides a method and apparatus for reduced noise band switching circuits.  
         [0023]     Turning to  FIG. 1 , a schematic diagram of a prior art voltage-controlled oscillator (VCO) is shown. The VCO  10  comprises a bias control  12  which is connected to an amplifier bias  14  and a tank bias  16 . A voltage source  18  and a digital control  20 , along with the amplifier bias  14  and tank bias  16 , are connected to a VCO core  22 . The VCO core  22  comprises an amplifier  24 , and a tank  26 . The outputs from the amplifier  24  and the tank  26  are transmitted as an output voltage  28 .  
         [0024]      FIG. 2  provides a graph  30  of the output voltage  28  with respect to the frequency at which the VCO  10  is operating.  
         [0025]     Turning now to  FIG. 3 , apparatus for a reduced noise band switching circuit is shown. The apparatus is directed at a VCO for signal generation in wireless radio frequency (RF) applications. The apparatus, or VCO,  50  comprises a bias control  52  connected to an amplifier bias  54  and a tank bias  56 . The two biases  54  and  56  are connected, along with a voltage source  58  which has been attenuated by attenuator  60 , to a VCO core  62 . The VCO core  62  comprises an amplifier, or amplifier circuit  64  and a tank, or tank circuit  66  and has its output connected to a phase locked loop (PLL)  68  which is connected to the input of the voltage source  58 . Within the VCO core  62 , the amplifier circuit  64  is coupled to the tank circuit  66  with the amplifier circuit  64  being biased by the amplifier bias  54  and the tank circuit  66  being biased by the tank bias  56 .  
         [0026]     In operation, the voltage source  58  generates an input voltage for the tank circuit  66  of the VCO core  62 . Simultaneously, the bias control  12  transmits a first set of control signals to the amplifier bias  54  and a second set of control signal to the tank bias  56 .  
         [0027]     After the input voltage has been generated, it is transmitted to the attenuator  60  before being transmitted to the tank circuit  66 . While the input voltage is being attenuated, the amplifier bias  54  and the tank bias  56  control operation of the amplifier circuit  64  and the tank circuit  66  by providing a noiseless bias voltage as will be described below. The combination of the attenuated input voltage and the noiseless biasing voltage results in an output which is also noiseless which results in a cleaner output signal. An example of the output is shown in  FIG. 4  which shows the result of attenuation on the output frequency (f out ) in relation to the output voltage (V out ).  
         [0028]     With attenuation, the slope of f out  versus source voltage, or K vco , decreases so that for any change in source voltage, there is a small change in f out . A lower K vco , results in a reduction in phase noise as shown in the following equation:  
         phase  noise     =       α   2     ⁢         V   2     ⁡     (       K   vco     f     )       2           
 
         [0029]     Therefore, the attenuation of the input voltage provides a reduced noise signal to the tank circuit, further allowing the output of the VCO core to be reduced in noise.  
         [0030]     Turning to  FIG. 5 , a first embodiment of the attenuator  60  is shown which is in the form of a capacitance voltage divider. The attenuator  60  comprises a first capacitor  70 , also designated as C 1  in the equation below, connected in series with a second capacitor  72 , designated as C 2  in the equation below, to ground  74 . The attenuator  60  also includes a switch  71 . The first capacitor  70  receives its input (V in ) from the voltage source  58  and an output (V out )  80  of the attenuator  60  goes to the tank circuit  66  in the VCO core  62 . The output  80  of the attenuator  60  is between the first and second capacitors  70  and  72 . The capacitance voltage divider attenuates the input voltage as:  
         V   out     =     α   ⁢           ⁢     V   in           
         where   ⁢           ⁢   α     =       C   1         C   1     +     C   2             
 
         [0031]     When an input voltage is delivered, the phase lock loop  68  start operating and the switch  71  is closed (in the ON state) to create a path to charge the second capacitor  72  to the value of the input voltage (V in ). After the phase lock loop  68  has been able to lock, the capacitance voltage divider is seen as in a enabled state and therefore only a small loop gain is experienced at point A which also allows for the noise of the voltage signal to be reduced which, in turn, results in small variations in frequency due to noise. This is because the DC portion of the input voltage is relatively constant and the AC portion of the input voltage has been attenuated which causes the noise from the input voltage to also attenuate which, in turn, reduces the frequency variation due to noise.  
         [0032]     The output  80  of the attenuator is connected to the tank circuit and acts as a tuning, or control, voltage for the tank circuit  66 . The output of the attenuator is connected between a pair of varactors  108  as shown in  FIG. 9 .  
         [0033]      FIG. 6  shows an alternate embodiment of the attenuator  60 . In this embodiment, the attenuator  60  is similar to the embodiment of  FIG. 5  with the addition of a diode  80 . The diode  80  is preferably forward biased. Furthermore, an output  81  of the attenuator  60  is also fed back via a switch  79  to the input, V in , of the attenuator in a negative phase lock loop  83 . The feedback loops allows for correction of any variation in the input voltage to pull V out  back to a desired voltage. Any loss in charge due to the leakage path resistance (the path provider by the resistor  78 ) is also corrected by the feedback loop  83  and the diode  80 .  
         [0034]     When an input voltage is delivered, the switch  79  is closed (in the ON state) to create a path to charge the second capacitor  72  to the value of the input voltage (V in ). After the second capacitor  72  reaches the value of Vin, the capacitance voltage divider is seen as in a enabled state and therefore only a small loop gain is experienced at point A which also allows for small variations in frequency due to noise.  
         [0035]      FIG. 6   a  shows a comparison of V out  and input voltage V i n over time.  
         [0036]     With the negative feedback loop  83 , when V in  fluctuates to 5V, V out  increases to 2.5 volts as determined by the capacitance divider equation, V out  is then fed back to, which corrects the voltage source pulling V in  back down to 1V.  
         [0037]      FIG. 7  shows a further embodiment of the attenuator  60 . In this embodiment, the attenuator  60  comprises a double capacitance voltage divider. The attenuator  60  receives its input (V in ) from the voltage source  58  and comprises a first capacitor  82  connected in series to a second capacitor  84  and ground  86 . The first capacitor  82  is also connected to ground  86  via a third capacitor  88  and a fourth capacitor  90  which are connected in series. The third and fourth capacitors  88  and  90  are parallel to the second capacitor  84 . The capacitors  82 ,  84 ,  88  and  90  are connected in parallel with a forward biasing diode  92 . As further shown in the figure, a first capacitance voltage divider is divided by a second capacitance voltage divider such the first  82  and second  84  capacitors are divided by the third and fourth capacitors  88  and  90 . The first  82  and third  88  capacitors are in parallel with the forward biased diode  92 .  
         [0038]     The attenuator  60  also comprises a pair of switches  94  and  96  which are used to assist in the charging of the capacitors during the initial period when the phase lock loop  68  is attempting to lock.  
         [0039]     The output voltage V out  is attenuated by the equation shown below:  
         V   out     =     α   ⁢           ⁢     V   in           
         where   ⁢           ⁢   α     =       (       C   1         C   1     +     C   2         )     ⁢     (       C   3         C   3     +     C   4         )           
 
         [0040]     The attenuated output of the attenuator allows for a less noisy input voltage to the tank circuit  66  than if the voltage source  58  was connected directly to the tank circuit  66  since the double capacitance voltage divider lowers the value of a which in turn lowers the phase noise of the circuit.  
         [0041]     Turning to  FIG. 8 , a schematic diagram of part of the VCO  50  is shown. The bias control  52  is connected to the amplifier bias  54  which is connected to the amplifier circuit  64  of the VCO core  62 . Operation and the contents of the amplifier circuit  64  will be well known to one skilled in the art.  
         [0042]     The amplifier bias  54  comprises a pair of switches  100  which are controlled by the bias control  52  along with an amplifier biasing voltage source  102 . The bias control  52  also controls an amplifier biasing voltage source  102 . In order to provide a noiseless bias voltage to the amplifier circuit  64 , when the bias control  52  senses a logic high (indicating a power up state for the VCO  10 ), the first set of control signals are sent to the amplifier bias  54  and to the amplifier biasing voltage source  102 , comprising an amplifier switch control signal and a V biasampflifiercontrol  signal, respectively.  
         [0043]     Upon receipt of the amplifier switch control signal, the switches  100  in the amplifier bias  54  close and, upon receipt of the V biasamplifiercontrol  signal, the biasing voltage source  102  starts. The amplifier biasing voltage source  102  charges across the switches  100  to provide an output voltage to the amplifier circuit  64 .  
         [0044]     After a predetermined period of time, the bias control  52  transmits a signal to the amplifier bias  54  to open the switches  100 . This occurs after the output voltage of the switches  100  has attained a predetermined value.  
         [0045]     By opening the switches  100  after the predetermined voltage has been reached, the voltage being transmitted from the switches  100  to the amplifier circuit  64  may be seen as noiseless since there is no direct connection between the amplifier biasing voltage source  102  and the amplifier circuit  64 . Therefore, the VCO core  62  may operate under noiseless bias conditions. A sample timing diagram is shown in  FIG. 8   a.    
         [0046]     Turning to  FIG. 9 , a schematic diagram of the VCO core, the tank bias circuit and the bias control is shown. The bias control  52  is connected to the tank bias  56  which is connected to the tank circuit  66  of the VCO core  62 . Operation and the contents of the tank circuit  64  will be well known to one skilled in the art.  
         [0047]     As with the amplifier bias, the tank bias  56  comprises a pair of switches  104  which are controlled by the bias control  52  by the second set of control signals which includes a tank switch control signal. A tank bias voltage source  106  is controlled by a V biastankcontrol  control signal which is transmitted by the bias control  52 . Operation of the tank bias  56  is similar to the operation of the amplifier bias  54 , as disclosed above with respect to  FIG. 8 .  
         [0048]     Due to the size and costs of the parts required for the attenuators of the present invention, it will be understood that these attenuators are beneficial for use in integrated circuits.  
         [0049]     The provision of an attenuated voltage and the bias control voltage to the VCO core, provides a reduced noise band switching circuit.  
         [0050]     The above-described embodiments of the invention are intended as examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Technology Category: 5