Patent Document

CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of U.S. Provisional Application No. 60/755,068 filed Jan. 3, 2006, in the United States Patents and Trademark Office, the disclosure of which is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     An aspect of the present invention relates to a digital broadcasting transmission system and a method thereof. More particularly, an aspect of the present invention relates to a digital broadcasting transmission system enabling an improved receptivity, by using a variety of methods to code a turbo stream, and a method thereof.  
         [0004]     2. Description of the Related Art  
         [0005]     According to the Advanced Television System Committee (ATSC) Digital Vestigial Side Band (VSB) technologies, the U.S. oriented terrestrial digital broadcasting system uses a single carrier and field sync signal of 312-segment unit. This system has poor receptivity particularly in the bad channel such as Doppler fading channel.  
         [0006]      FIG. 1  is a block diagram of a conventional ATSC VSB broadcasting transmission apparatus, and  FIG. 2  shows the frame structure of data used in the system of  FIG. 1 .  
         [0007]     More specifically,  FIG. 1  shows an EVSB system, which makes and sends out a dual transport stream (TS) by adding robust data to the normal data of an existing ATSC VSB system.  
         [0008]     Referring to  FIG. 1 , the transmission of the conventional digital broadcasting transmission system is explained below.  
         [0009]     A normal stream, a place holder packet and a turbo stream are fed to a TS constructor  11  in which a dual TS is constructed.  
         [0010]     The dual TS is randomized at the randomizer  13 , a parity bit is appended to the transmitted stream for error correction at a Reed-Solomon (RS) encoder  15 , and a packet is re-constructed at a packet formatter  17 . Additionally, the re-constructed packet is interleaved at an interleaver  19 , and the interleaved data is trellis-encoded at a trellis encoder  21 . The trellis encoder  21  generates a compatible parity bit through an interaction with a compatible parity generator  23 .  
         [0011]     After the data is error-corrected at the trellis encoder  21 , the error-corrected data is multiplexed at a multiplexer (MUX)  27  which inserts field sync and segment sync signals in the data. Then the processes of pilot signal insertion, VSB conversion and up-conversion to RF channel signal levels, are performed and the data is transmitted through the channel. The above operations may be controlled by the control signal from a controller  25 .  
         [0012]     As shown in  FIG. 2 , a data frame that is applied to the digital broadcasting transmission apparatus of  FIG. 1  has consecutive packets M 0  through M 51 , and is formatted at a packet formatter  17  and outputted. As shown, the turbo stream and the normal stream are arranged at the rate of 1:3.  
         [0013]     A problem of the VSB system is performance degradation due to dynamic multipath interference and a weak signal. However, notwithstanding the fact that they use a dual TS which includes normal stream added with turbo stream, the conventional digital broadcasting transmission systems, as the ones shown in  FIGS. 1 and 2 , could hardly improve bad receptivity by the transmission of a normal stream in the multipath channel.  
         [0014]     Additionally, at relatively high power levels, that is, as 4th level power used among the existing  8  levels of power, average power consumption of the stream increases. If many turbo streams are used, quality of normal stream will relatively deteriorate. Therefore, adding a turbo stream to the normal stream has to be limited.  
       SUMMARY OF THE INVENTION  
       [0015]     An Aspect of the present invention is to provide a digital broadcasting transmission system which is capable of adding as many turbo streams as is necessary, without being limited to a certain rate, by applying P2-VSB coding to the turbo stream.  
         [0016]     In accordance with the above aspect of the present invention, the digital broadcasting transmission system, comprises an RS encoder to encode a dual transport stream (TS) which includes a normal stream and a plurality of turbo streams multiplexed together, an interleaver to interleave the encoded dual TS, a turbo processor to detect the turbo streams from the interleaved dual TS and to encode the detected turbo stream, and a trellis encoder to pseudo2 (P-2) vestigial sideband (VSB) code the turbo-processed dual TS, and, then, to perform trellis encoding, and a main multiplexer (MUX) to multiplex the trellis-encoded dual TS by adding a field synchronous signal and a segment synchronous signal thereto.  
         [0017]     In accordance with another aspect of the present invention, a digital broadcasting transmission method, comprises encoding a dual transport stream (TS) which includes a normal stream and a plurality of turbo streams that are multiplexed together; interleaving the encoded dual TS, detecting the turbo streams from the interleaved dual TS and encoding the detected turbo stream, and pseudo2 (P-2) VSB coding the turbo-processed dual TS, and then performing trellis encoding, and multiplexing the trellis-encoded dual TS by adding a field synchronous signal and a segment synchronous signal thereto.  
         [0018]     Additional and/or other aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     These and/or other aspects and advantages of the invention will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:  
         [0020]      FIG. 1  is a block diagram of a conventional ATSC digital broadcasting transmission system;  
         [0021]      FIG. 2  illustrates the frame structure of data used in the system of  FIG. 1 ;  
         [0022]      FIG. 3  is a block diagram of a digital broadcasting transmission system according to an exemplary embodiment of the present invention;  
         [0023]      FIG. 4  is a block diagram of the TS constructor of  FIG. 3 ;  
         [0024]      FIGS. 5A through 5C  are views illustrating a packet output from the TS constructor;  
         [0025]      FIG. 6  is a block diagram of the turbo processor of  FIG. 3 ;  
         [0026]      FIG. 7  illustrate inner structure of a trellis encoder of  FIG. 3 ;  
         [0027]      FIG. 8  illustrates a first encoder of  FIG. 7 ;  
         [0028]      FIG. 9  is a block diagram of a digital broadcasting transmission system according to another exemplary embodiment of the present invention;  
         [0029]      FIGS. 10 and 10 B show transmission stream which includes SRS data;  
         [0030]      FIG. 11  is a block diagram of a SRS inserter of  FIG. 9 ;  
         [0031]      FIG. 12  illustrates a trellis encoder of  FIG. 9 ;  
         [0032]      FIG. 13  illustrates a first encoder of  FIG. 12 ;  
         [0033]      FIG. 14  is a block diagram of a digital broadcasting reception system applied to the present invention;  
         [0034]      FIGS. 15A and 15B  are diagrams showing the operation of viterbi decoder of  FIG. 14 ;  
         [0035]      FIG. 16  is a block diagram of a turbo decoder of  FIG. 14 ;  
         [0036]      FIG. 17  is a flowchart provided to explain a method of digital broadcasting transmission according to an exemplary embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0037]     Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.  
         [0038]      FIG. 3  is a block diagram of a digital broadcasting transmission system according to an exemplary embodiment of the present invention. As shown in  FIG. 3 , a digital broadcasting system according to an exemplary embodiment of the present invention includes a TS constructor  110 , a randomizer  120 , an RS encoder  130 , a parity formatter  140 , an interleaver  150 , a turbo processor  160 , a trellis encoder  170 , a compatible parity generator  180 , a controller  190 , a main multiplexer (MUX)  200 , a pilot inserter  310 , a vestigial sideband (VSB) modulator  320 , and a radio frequency (RF) converter  330 .  
         [0039]     The TS constructor  110  receives an input of a normal stream and a plurality of turbo streams, and processes the turbo streams from among the received data. The TS constructor  110  then multiplexes the normal stream and the turbo stream to construct a dual transport stream (TS). The TS constructor  110  will be explained in greater detail below with reference to  FIGS. 4, 5A ,  5 B and  5 C.  
         [0040]     The randomizer  120  randomizes the dual TS received from the TS constructor  110 . By the operation of the randomizer  201 , a utilization of channel space is increased.  
         [0041]     The RS encoder  130  encodes the dual TS which is randomized at the randomizer  120 . The RS encoder  130  may be implemented as a concatenated coder which adds a parity bit to the transmission stream in order to correct a channel-generated error during the transmission.  
         [0042]     The parity formatter  140  determines the position of the parity bit in the RS encoded dual TS. Therefore, the parity formatter  140  does not operate with respect to the packet having normal data only, but, rather, determines the position of the packet having turbo data, in order to prevent the parity bit from proceeding to the turbo data position after the interleaving.  
         [0043]     With reference to an example of the packet as shown in  FIG. 5B , the parity formatter  140  changes the parity bit to predetermined data. The parity formatter  140  calculates the position of the parity bit by the following: 
 
 m =(52 *n+k )%207  [Mathematical Expression]
 
         [0044]     where, m refers to the position of a parity bit before interleaving, n is the position of parity bit after interleaving (n=0, 1, . . . , 206), and k is the result of calculating the order of packets in a field by module  52  (k=0, 1, . . . , 51).  
         [0045]     The above mathematical expression is used to calculate the value of m from 187 to 206, and does not take the result if the parity bit is located in the PID, AF header and normal data. The position of the parity bit is determined by iteratively applying the above mathematical expression while changing the starting position one by one.  
         [0046]     Taking the example of the 10 th  segment which includes 128 byte turbo data, and 54 byte normal data, the parity bit overlaps the PID, AF header and normal data by 21 bytes. In this case, the position of the parity bit is calculated by applying the above mathematical expression 1 to 176 to 206 and a 20 byte parity bit position is determined.  
         [0047]     Accordingly, the parity formatter  140  first inserts predetermined data to the position of the parity bit excluding the PID, AF header and normal data, and then inserts turbo data in the remaining parts, to construct a new packet structure.  
         [0048]     The interleaver  150  interleaves the dual TS. The ‘interleaving’ changes the position of the data in frame but does not change the data, per se.  
         [0049]     The turbo processor  150  separates the normal stream and the turbo stream from the dual TS which is interleaved at the interleaver  150 , and encodes the separated turbo stream to strengthen the turbo stream. The turbo processor  160  will be explained in greater detail below with reference to  FIGS. 7 and 8 .  
         [0050]     The trellis encoder  170  pseudo 2-VSB (P-2 VSB) codes the turbo-processed dual TS, and performs trellis encoding. The trellis encoder  170  will be explained in greater detail below with reference to  FIGS. 9 and 10 .  
         [0051]     The compatible parity generator  180  generates a compatible parity bit for the compatibility with a receiver device, through an interaction with the trellis encoder  170 . The compatible parity generator  180  may generate a compatible parity bit based on the dual TS packet, which is appended with the parity at the RS encoder  130 , and the dual TS, which is encoded at the trellis encoder  170 .  
         [0052]     The controller  190  controls the normal stream and the turbo stream at the TS constructor  110 , the parity formatter  140 , the turbo processor  160  and the trellis encoder  170  according to a predetermined control signal.  
         [0053]     The main MUX  200  appends field sync and segment sync signals to the dual TS provided from the trellis encoder  170 , to multiplex the streams.  
         [0054]     According to one aspect of the present invention, the turbo stream processed at the turbo processor  160 , the turbo stream processed at the turbo processor  160  and P2-VSB coded at the trellis encoder  170 , the turbo stream processed at the turbo processor  160 , and the turbo stream P2-VSB coded and trellis encoded at the trellis encoder  170 , and the normal stream may all be multiplexed.  
         [0055]     The pilot inserter  310  appends a pilot signal to the dual TS which is appended with the field sync and segment sync signals at the main MUX  200 . The pilot signal appears as a relatively small DC phase voltage is applied to an 8-VSB base band immediately before the modulation, so that a relatively small carrier appears in the zero frequency point of the modulated spectrum. The pilot signal synchronizes the signal to the RF PLL circuit of the receiver device, regardless of the transmission signal.  
         [0056]     The VSB modulator  320  pulse-shapes the transmission stream which is appended with the pilot signal at the pilot inserter  310 , and loads the transmission stream to the intermediate frequency carrier so as to perform VSB modulation which modulates amplitude.  
         [0057]     The RF converter  330  RF-converts the VSB-modulated transmission stream at the VSB modulator  320 , and amplifies and transmits the transmission stream to a predetermined band through an allotted channel.  
         [0058]      FIG. 4  is a block diagram of the TS constructor of  FIG. 3 . As shown in  FIG. 4 , the TS constructor  110  applied to the digital broadcasting transmission system according to one exemplary embodiment of the present invention includes an input MUX  112 , an RS encoder  114 , a packet formatter  116  and a TS MUX  118 . The input MUX  112  multiplexes a plurality of turbo streams which are inputted to the TS constructor  110 . One of the plurality of turbo streams goes through the turbo coding, another goes through the P2-VSB coding, and another goes through the turbo coding and then P2-VSB coding. The RS encoder  114  RS-encodes the turbo stream, which is multiplexed at the input MUX  112 . The packet formatter  116  re-constructs the packet of the turbo stream which is RS-encoded at the RS encoder  114 . The TS MUX  118  multiplexes the turbo stream whose packet is reconstructed at the packet formatter  116 , with the normal stream, and, thus, constructs a dual TS.  
         [0059]      FIGS. 5A through 5C  are views to show an exemplary packet being outputted from the TS constructor  110 .  
         [0060]     Generally, a packet applied to the digital broadcasting includes a 1-byte synchronous signal, a 3-byte header and a 184-byte payload. The header of the packet includes a packet identifier (PID). The data in the payload is categorized into either a normal stream and/or at least one turbo stream according to the type of data included in the payload.  
         [0061]     As shown in  FIG. 5A , the normal stream (a) is inputted to the TS constructor  100 , and the normal data (b) is included in the payload part. Additionally, there is an adaptation field showing the normal data mixed with the turbo data. The adaptation field includes 2-byte AF header and (N)-byte turbo data+null data space.  FIG. 5B  shows the two packets having a turbo stream and a normal stream, respectively, which may be combined with each other at the TS constructor at the rate of 1:3 or 2:2.  FIG. 5C  shows an exemplary structure of the packet corresponding to one field which is constructed in the form as shown in  FIG. 5B  at the TS constructor  110 , and which is inputted to the randomizer  120 . The normal data and the turbo data are combined in the 3:1 rate.  
         [0062]      FIG. 6  is a block diagram of the turbo processor of  FIG. 3 . As shown in  FIG. 6 , the turbo processor  160  applied to the digital broadcasting transmission system of the present invention includes a turbo extractor  162 , an outer encoder  164 , an outer interleaver  514  and a processor MUX  168 . The turbo extractor  162  extracts a turbo stream from the dual TS which is inputted to the turbo processor  160 . The outer encoder  164  performs convolution encoding with respect to the turbo stream which is extracted at the turbo extractor  162 . The outer interleaver  514  interleaves the turbo stream which is convolution-encoded at the outer encoder  164 . The processor MUX  168  multiplexes the turbo stream and the normal stream interleaved at the outer interleaver  514 , and outputs the resultant stream.  
         [0063]      FIG. 7  shows the inner structure of the trellis encoder of  FIG. 3 , and  FIG. 8  shows the first encoder. As shown in  FIG. 7 , the trellis encoder  170  includes a first encoder  172  for P-2 VSB coding, and a second encoder  174  for general trellis encoding.  
         [0064]     Referring to  FIG. 8 , as shown in  FIG. 8 , the first encoder  172  includes a first MUX  172   a , a second MUX  172   b , a third MUX  172   c , a first adder  172   d  and a control signal generator (not shown). The first MUX  172   a  selectively outputs one among the first and the second inputs X 1  and X 2 . The first input X 1  is also inputted to the second MUX  172   b . The first adder  172   d  adds the output from the first MUX  172   a  and the input from a predetermined register D 0 , and outputs the resultant value. The register D 0  may be the first register of the second encoder. The second MUX  172   b  selectively outputs one among the first input X 1  and the output from the first adder  172   d . The output X 2 ′ of the second MUX  172  is input to the second encoder  174 . The third MUX  172   c  selectively outputs either the second input X 2  or the output of the first MUX  172 . The output X 1 ′ of the third MUX  172   c  is input to the second encoder.  
         [0065]     The control signal generator (not shown) provides a control signal to select one among the plurality of inputs from the first through third MUXes  172   a  through  172   c.    
         [0066]     Accordingly, the first encoder  172  removes a pre-coding effect so that two outputs of the trellis encoding, with respect to the data for P-2 VSB coding among the plurality of turbo streams inputted to the TS constructor, may have the same value.  
         [0067]     The second encoding is processed using the outputs from the first encoder  172 , as the one shown in  FIG. 8 . Referring to  FIG. 7 , the second encoder  174  includes first through third registers D 0 , D 1 , D 2 , the second adder  174   a  and the third adder  174   b.    
         [0068]     The first through third registers D 0 , D 1 , D 2  have predetermined bit-values.  
         [0069]     The second adder  174   a  adds one X 2 ′ among the outputs from the first encoder, with the stored value of the first register D 0 , and outputs the resultant data and stores the output Z 2  in the first register D 0 .  
         [0070]     The third adder  174   b  adds another one X 1 ′ among the outputs from the first encoder, with the stored value of the second register D 1 , and outputs the resultant data and stores the output Z 0  in the first register D 0 .  
         [0071]     According to one exemplary embodiment of the present invention, as the data go through the processes of turbo coding at the turbo processor  160  and the P-2 VSB coding at the first encoder  172 , new data, which is different from the conventional packet data, is formed. Accordingly, incorrect RS decoding is possible at the receiver device. In order to prevent incorrect RS decoding, the compatible parity generator  180  generates a compatible parity bit to be inserted in the parity bit location of the data from the first encoder  172 .  
         [0072]      FIG. 9  is a block diagram of a digital broadcasting transmission system according to another exemplary embodiment of the present invention.  FIGS. 10A through 10B  show the transmission stream including supplementary reference signal (SRS) data therein.  
         [0073]     As shown in  FIG. 9 , the digital broadcasting transmission system according to another exemplary embodiment of the present invention includes a TS constructor  110 , a randomizer  120 , an SRS inserter  125 , an RS encoder  130 , a parity formatter  140 , an interleaver  150 , a turbo processor  160 , a trellis encoder  170 , a compatible parity generator  180 , a controller  190 , a main MUX  200 , a pilot inserter  310 , a VSB modulator  320  and an RF converter  330 .  
         [0074]     The digital broadcasting transmission system according to this exemplary embodiment of the present invention has a similar structure as the one shown in  FIG. 3 . Accordingly, the like elements are given the same reference numerals and only the different parts of the embodiment will be explained below.  
         [0075]     From the packet including adaptation field as shown in  FIG. 5A , a dual TS, which includes a stuffing region in the adaptation field, is inputted to the randomizer  120 .  
         [0076]     The SRS inserter  125  inserts a supplementary reference signal (SRS) to the stuffing region of the dual TS which is randomized at the randomizer  120 . According to the AF header and the stuff bytes inserted in the dual TS, a loss of payload due to the SRS and a mixing rate may be determined. This will be explained in greater below with reference to the SRS inserter  125  as shown in  FIG. 11 .  
         [0077]      FIGS. 10A and 10B  show the packet which includes SRS data inserted by the SRS inserter  125 . As shown, both the normal stream and the robust stream include S-byte of SRS data.  
         [0078]     Explanation of the remaining elements will be omitted for the sake of brevity, as it has already been explained above with reference to  FIG. 3 .  
         [0079]      FIG. 11  is a block diagram of the SRS inserter of  FIG. 9 . As shown in  FIG. 11 , the SRS inserter  125  includes an SRS pattern memory  125   a , and an SRS MUX  125   b . The SRS pattern memory  125   a  stores an SRS pattern for insertion in the stuffing region. The SRS pattern is made compatible with the receiver device in advance, and can be used in the equalizer of the receiver device. The SRS MUX  125   b  adds the SRS pattern stored in the SRS pattern memory  125   a , to the normal stream and the turbo stream, to perform multiplexing.  
         [0080]      FIG. 12  shows the trellis encoder of  FIG. 9 , and  FIG. 13  shows the first encoder of  FIG. 12 . As shown in  FIG. 12 , the trellis encoder  170  according to one exemplary embodiment of the present invention includes a first encoder  172  and a second encoder  174 . The second encoder  174  includes first through third registers D 0 , D 1 , D 2 , a second adder  174   a , and a third adder  174   b , in the identical structure as the second encoder as shown in  FIG. 7 . The first encoder  172  of  FIG. 13  includes first through third MUXes  172   a  through  172   c , and the first adder  172   b , in the same structure as the first encoder  172  as shown in  FIG. 8 .  
         [0081]     A difference of this embodiment from other embodiments of the present invention is in the P-2 VSB coding of the first encoder  172 , which is performed before the trellis encoding of the second encoder  174 . The SRS initialization signal is inputted to the second and the third MUXes  172   b ,  172   c . The SRS initialization signal initializes the first through third registers D 0 , D 1 , D 2  of the second encoder  174 , that is, D 0 =D 1 =D 2 =0.  
         [0082]      FIG. 14  is a block diagram of a digital broadcasting reception system applied to the present invention, and  FIGS. 15A and 15B  are diagrams showing the viterbi decoder in use. As shown in  FIG. 14 , the digital broadcasting reception system includes a demodulator  120 , an equalizer  420 , a viterbi decoder  430 , a receiver MUX  440 , a first deinterleaver  450 , an RS decoder  460 , a first derandomizer  470 , a first de-MUX  480 , a turbo decoder  510 , a second deinterleaver  150 , a parity eraser  530 , a second derandomizer  540 , and a second de-MUX  550 .  
         [0083]     The demodulator  410  receives dual TS which is transmitted from the digital broadcasting transmission system as shown in  FIG. 3  or  FIG. 9 , detects synchronization according to the synchronous signal added to the baseband signal, and performs demodulation.  
         [0084]     The equalizer  420  equalizes the dual TS which is demodulated at the demodulator  410 . Accordingly, the equalizer  420  compensates for channel distortion due to multipath of the channel, and, thus, removes interferences of the received symbols.  
         [0085]     The viterbi decoder  430  corrects errors of the normal stream of the dual TS, decodes the error-corrected symbol, and, thus, outputs a symbol packet. The viterbi decoder  430  decodes the normal data using the diagram as shown in  FIG. 15A , while decoding P-2 VSB-coded data using the diagram as shown in  FIG. 15B .  
         [0086]     The receiver MUX  440  multiplexes the normal stream which is error-corrected at the viterbi decoder  430 , and the turbo stream which is decoded at the turbo decoder  510 .  
         [0087]     The first deinterleaver  450  deinterleaves the normal stream which is viterbi-decoded at the viterbi decoder  430 .  
         [0088]     The RS decoder  460  RS-decodes the normal stream which is deinterleaved at the first deinterleaver  450 .  
         [0089]     The first derandomizer  470  derandomizes the normal stream which is RS-decoded at the RS decoder  460 , and outputs the resultant stream.  
         [0090]     The turbo decoder  510  decodes the turbo stream of the dual TS which is equalized at the equalizer  420 . The turbo decoder  510  will be explained in greater detail below with reference to  FIG. 16 .  
         [0091]     The second deinterleaver  150  deinterleaves the turbo stream which is decoded at the turbo decoder  510 .  
         [0092]     The parity eraser  530  removes a parity bit, which is appended to the turbo stream deinterleaved at the second deinterleaver  150 .  
         [0093]     The second derandomizer  540  derandomizes the turbo stream from which parity is removed at the parity eraser  530 .  
         [0094]     The second de-MUX  550  demultiplexes the turbo stream which is derandomized at the second derandomizer  540 .  
         [0095]      FIG. 16  is a block diagram of turbo decoder of  FIG. 14 . As shown in  FIG. 16 , the turbo decoder  510  includes a TCM map decoder  511 , an outer deinterleaver  512 , an outer map decoder  513 , an outer interleaver  514 , a frame formatter  515 , and a symbol deinterleaver  516 . The TCM map decoder  511  trellis-decodes the turbo stream. The outer deinterleaver  512  deinterleaves the turbo stream which is trellis-decoded at the TCM map decoder  511 . The outer map decoder  513  convolution-decodes the turbo stream which is deinterleaved at the outer deinterleaver  512 . The outer interleaver  514  interleaves the turbo stream which is convolution-decoded at the outer map decoder  513   
         [0096]     The frame formatter  515  adds the decoding data of the outer map decoder  513  to a location of the frame having the normal stream and the turbo stream mixed therein, corresponding to the location of the turbo stream.  
         [0097]     When information exchange is completed between the outer deinterleaver  512  and the outer interleaver  514  of the TCM map decoder  511  and the outer map decoder  513 , the decoding data of the TCM map decoder  511  is outputted to use in the reception of normal stream, while the decoding data of the outer map decoder  513  is provided to the frame formatter  515 .  
         [0098]      FIG. 17  is a flowchart provided to explain a method of digital broadcasting transmission according to an exemplary embodiment of the present invention.  
         [0099]     Hereinbelow, the digital broadcasting reception method according to the exemplary embodiment of the present invention will be explained with reference to  FIGS. 3 through 17 .  
         [0100]     The TS constructor  110  receives an input of a normal stream and a plurality of turbo streams, and performs RS-encoding and packet formatting with respect to the turbo streams. The TS constructor  110  then multiplexes the processed turbo streams and the normal stream, to construct a dual transport stream (TS) (op  600 ).  
         [0101]     The dual TS constructed at the TS constructor  110  is randomized at the randomizer  120  (op  610 ), RS-encoded at the RS encoder  130  (op  620 ), determined with the location of parity at the parity formatter  140  and formatted (op  630 ), and interleaved at the interleaver  150  (op  640 ).  
         [0102]     The interleaved dual TS is separated into the normal stream and the turbo streams at the turbo processor  160 , and the turbo streams are turbo-coded (op  650 ).  
         [0103]     After the turbo coding, the trellis encoder  170  performs P-2 VSB coding with the first encoder  172 , and trellis encoding with the second encoder  174 . At this time, through the interaction of the trellis encoder  170  and the compatible parity generator  180 , a compatible parity may be generated (op  660  to op  670 ).  
         [0104]     Accordingly, the turbo-processed turbo stream, the turbo stream which is turbo-processed, P-2 VSB-coded at the trellis encoder  170 , and the turbo stream which is turbo processed, P-2 VSB coded and trellis-encoded at the trellis encoder  170 , are formed, and the three types of turbo streams are multiplexed with the normal stream at the main MUX  200  and constructed into a new dual TS (op  690 ).  
         [0105]     After the dual TS constructed at the main MUX  200  goes through the process in which a pilot signal is inserted by the pilot inserter  310 , and the processes of VSB modulation at the VSB modulator  320 , and RF conversion at the RF converter  330 , the dual TS is transmitted through the predetermined channel (op  692 ).  
         [0106]     As is described above, the dual TS transmitted from the digital broadcasting transmission system is received at the digital broadcasting reception system, and goes through the processes such as modulation, equalization, viterbi decoding, deinterleaving, RS decoding, derandomization and de-MUXing, and is thus recovered to the normal TS packet, the P-2 VSB TS packet, and the turbo TS packet.  
         [0107]     As is described above, the digital broadcasting transmission system and method thereof receives a normal stream and a plurality of turbo streams, applies a variety of coding methods, and, therefore, is able to add turbo streams without being limited to a certain mixing rate. Additionally, data reception at the poor channel environment is also improved.  
         [0108]     Although a few embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

Technology Category: h