Patent Document

BACKGROUND OF THE INVENTION 
     1. The Field of the Invention 
     The present invention relates to analog integrated circuit design, and more particularly, to low voltage, enhanced output impedance current mirrors. 
     2. Background and Related Art 
     Computing technology has revolutionized the way people work and play and has contributed enormously to the advancement of humankind. Computing technology is largely enabled by various integrated circuit designs. In many analog circuit designs, it is often desirable to mirror a current from one portion of the circuit to another. While there are various types of current mirrors, FIG. 1 illustrates a specialized conventional current mirror that mirrors an input current I IN  from one branch in the circuit to another branch of the circuit in the form of I OUT . 
     The current mirroring is enabled by connecting the gates of both n-type Metal-Oxide Semiconductor Field Effect Transistors (hereafter also referred to as an “nMOSFET”) m and ml to each other and to the drain terminal of nMOSFET m. It is well known to those of ordinary skill in the art that the configuration of nMOSFET m 2  with the Operational Amplifier AMP and with the rest of the circuitry as shown in FIG. 1 results in a current mirror often referred to as an “enhanced output impedance current mirror” since the use of the amplifier significantly increases output impedance R OUT  as compared to a basic cascoded current mirror. The circuit is also known as a “regulated cascode current source” since gain is used to enhance the output impendence of the current source. Specifically, the output impedance R OUT  of the illustrated current mirror is defined by the following equation (1): 
     
       
           R   OUT =( r   dsl )×( g   m2   ×r   ds2 )×( A+ 1)  (1) 
       
     
     where r dsl  is the drain-source resistance of the nMOSFET m 1 , g m2  is the transconductance of nMOSFET m 2 , r ds2  is the drain-source resistance of the nMOSFET m 2 , and A is the open-loop gain of the amplifier AMP. A traditional cascode current mirror would have an output impedance according to the following equation (2): 
     
       
           R   OUT =(r dsl )×(g m2   ×r   ds2 )  (2) 
       
     
     Accordingly, the enhanced output impedance current mirror increases output impedance by a factor of (A+1). 
     It is advantageous for the output impedance of the enhanced output impedance current mirror to remain large for small values of V OUT . As V OUT  is decreased, the output impedance will remain close to its nominal value until nMOSFET m 2  enters the linear region when the drain-to-source voltage V ds2  of nMOSFET m 2  decreases to the saturation voltage V dsat2  of nMOSFET m 2 , which is equal to the gate-source voltage V gs2  of nMOSFET m 2  minus the threshold voltage V i2  of nMOSFET m 2 . In other words, nMOSFET m 2  enters the linear region when the following equation (3) holds: 
     
       
           V   ds2   =V   dsat2   =V   gs2   −V   2   (3) 
       
     
     Since the amplifier AMP has minimal offset, the voltage at the negative terminal of the amplifier (namely, V dsl ) is equal to the voltage at the positive terminal of the amplifier (namely, V REF ). Accordingly, the minimum output voltage V OUTmin  is equal to the reference voltage V REF  plus the saturation voltage V dsat2  of the nMOSFET m 2  according to the following equation (4): 
     
       
           V   OUTmin   =V   REF   +V   dsat2   (4) 
       
     
     Accordingly, since it is advantageous to minimize V OUTmin , it is also advantageous to minimize V REF . This can be done so long as V REF  is greater than V dsatl  (V dsatl =V gsl −V tl ). Any further reduction would push the nMOSFET ml into the linear region thereby degrading the current mirroring function. 
     Since V dsatl  is process and temperature dependent, biasing nMOSFET ml so that V dsl  exceeds V dsatl  by a minimal amount can be challenging. Accordingly, what would be advantageous would be a circuit that allows for the proper biasing of nMOSFET ml to allow a small minimum output voltage with little additional circuitry to occupy additional chip space. 
     BRIEF SUMMARY OF THE INVENTION 
     The foregoing problems with the prior state of the art are overcome by the principles of the present invention, which are directed towards an enhanced output impedance current mirror that properly biases the transistor while using less additional circuitry than a standard enhanced output current mirror. 
     As in conventional enhanced output impedance current mirrors, the new enhanced output impedance current mirror includes an nMOSFET M 1  having a source terminal that is connected to a low voltage source, and an nMOSFET M 2  having a source terminal that is connected to a drain terminal of the first nMOSFET M 1 . The current is mirrored from a different part of circuit by applying appropriate biases to the gate terminal of nMOSFET M 1  as is conventionally known. The output current is the current going into the source terminal of nMOSFET M 2 , and the output impedance is the impedance looking into the source terminal of nMOSFET M 2 . 
     A uniquely designed circuit is connected to nMOSFETs M 1  and M 2  so as to apply the appropriate biases to nMOSFET M 1  such that the minimum output voltage may be only the sum of the saturation voltages of both of the nMOSFETs M 1  and M 2 . The operational amplifier also provides the necessary gain to enhance output impedance thereby serving two roles with just a few additional components configured in a certain previously unknown way described hereinafter. 
     As in a conventional operational amplifier, the operational amplifier includes a current source (I) having a first terminal connected to a high voltage source. In this description and in the claims, one node in a circuit is “connected” to another node in the circuit if charge carriers freely flow (even through some devices) between the two nodes during normal operation of the circuit. A differential pair is then provided having gate terminals as input terminals to the operational amplifier. Specifically, one pMOSFET M 3  has a gate terminal connected to the source terminal of the nMOSFET M 2 . A source terminal of the pMOSFET M 3  is connected to a second terminal of the current source (I). A drain terminal of the pMOSFET M 3  is connected to a gate terminal of the second nMOSFET (M 2 ). Similarly a second pMOSFET (M 4 ) has a source terminal connected to the second terminal of the current source (I). 
     Unlike conventional enhanced output impedance current mirrors, however, the operational amplifier includes four nMOSFETs M 5 -M 8  having a common gate terminal that is connected to the drain of pMOSFET M 4 . By properly designing the length to width ratios as will be described further below, a desired reference voltage and drain-source voltage of transistor M 1  may be obtained to thereby significantly reduce the lowest output voltage of the enhanced output impedance current mirror. 
     Another embodiment of the invention may be accomplished by substituting all nMOSFETs with pMOSFETs, and vice versa, and by tying any terminals that were connected to a lower voltage source to a high voltage source, and vice versa. Accordingly, an enhanced output impedance current mirror is obtained using minimal additional devices while allowing for a reduced minimum output voltage. 
     Additional features and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In order to describe the manner in which the above-recited and other advantages and features of the invention can be obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which: 
     FIG. 1 illustrates an enhanced output impedance current mirror in accordance with the prior art. 
     FIG. 2 illustrates an enhanced output impedance current mirror in accordance with a first embodiment of the present invention; 
     FIG. 3 illustrates an enhanced output impedance current mirror in accordance with a second embodiment of the present invention; 
     FIG. 4 illustrates an enhanced output impedance current mirror in accordance with a third embodiment of the present invention; 
     FIG. 5 illustrates an enhanced output impedance current mirror in accordance with a fourth embodiment of the present invention; 
     FIG. 6 illustrates an enhanced output impedance current mirror in accordance with a fifth embodiment of the present invention; 
     FIG. 7 illustrates an enhanced output impedance current mirror in accordance with a sixth embodiment of the present invention; and 
     FIG. 8 illustrates an enhanced output impedance current mirror in accordance with a seventh embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Enhanced output impedance current mirrors are conventionally used to mirror current from one portion of a circuit to another, while increasing the output impedance associated with the output current. Reducing the minimum output voltage is desirable. In addition, reducing circuit complexity is desirable so long as the functioning of the circuit is not sacrificed. The principles of the present invention provide an enhanced output impedance current mirror in which very low output voltages are possible with few additional devices as compared to conventional enhanced output impedance current mirrors. 
     FIG. 2 illustrates an enhanced output impedance current mirror  200  in accordance with a first embodiment of the present invention. As in conventional enhanced output impedance current mirrors, the enhanced output impedance current mirror  200  includes an nMOSFET M 1  having a source terminal that is connected to a low voltage source LOW, and an nMOSFET M 2  having a source terminal that is connected to a drain terminal of the first nMOSFET M 1 . The current is mirrored from a different part of circuit by applying appropriate biases to the gate terminal of nMOSFET M 1  as is conventionally known and as is illustrated in FIG.  1 . The output current I OUT  is the current going into the source terminal of nMOSFET M 2 , and the output impedance is the impedance looking into the source terminal of nMOSFET M 2 . 
     A uniquely designed operation amplifier (namely, the circuitry to the right of nMOSFETs M 1  and M 2 ) is connected to nMOSFETs M 1  and M 2  so as to apply the appropriate biases to nMOSFET M 1  such that the minimum output voltage may be as low as the sum of the saturation voltages of both of the nMOSFETs M 1  and M 2 . The operational amplifier also provides the necessary gain to enhance output impedance thereby serving two roles with just a few additional devices configured in a certain previously unknown way. 
     As in a conventional operational amplifier, the operational amplifier includes a current source (I) having a first terminal connected to a high voltage source. A differential pair is then provided having gate terminals as input terminals to the operational amplifier. Specifically, one pMOSFET M 3  has a gate terminal connected to the source terminal of the nMOSFET M 2 . A source terminal of the pMOSFET M 3  is connected to a second terminal of the current source (I). A drain terminal of the pMOSFET M 3  is connected to a gate terminal of the second nMOSFET M 2 . Similarly, a second pMOSFET M 4  has a source terminal connected to the second terminal of the current source (I). 
     Unlike conventional enhanced output impedance current mirrors, however, the operational amplifier includes four nMOSFETs M 5 -M 8  having a common gate terminal that is connected to the drain of pMOSFET M 4 . More specifically, nMOSFET M 5  has a gate terminal connected to a drain terminal of pMOSFET M 4 , and has a drain terminal connected to the drain terminal of pMOSFET M 3 . nMOSFET M 6  has a gate terminal connected to the gate terminal of nMOSFET M 5 , has a drain terminal connected to the drain terminal of pMOSFET M 4 , and has a source terminal connected to a gate terminal of the second pMOSFET M 4 . nMOSFET M 7  has a gate terminal connect to the gate terminal of nMOSFET M 5 , has a drain terminal connected to the source terminal of the nMOSFET M 5 , and has a source terminal connected to the low voltage source. nMOSFET M 8  has a gate terminal connected to the gate terminal of nMOSFET M 5 , has a drain terminal connected to the source terminal of nMOSFET M 6 , and has a source terminal connected to the low voltage source LOW. 
     In this configuration, the reference voltage V REF  would be defined by the following equation (5):                V   REF     =         I     β   6              (             β   6     +     β   8           β   6          β   8           -   1     )               (   5   )                                
     where β 6  is the channel length-to-width ratio of the nMOSFET M 6 , and β 8  is the channel length-to-width ratio of the nMOSFET M 8 . 
     The channel length-to-width ratios are parameters that may be chosen by the circuit designer. Accordingly, the reference voltage V REF  may be chosen to be a minimal value above the saturation voltage (V dsatl ) of the nMOSFET M 1 . A typical minimal value might be for example, 100 millivolts above the saturation voltage. In a broader embodiment of the present invention, the minimal value may be any voltage greater than or equal to the saturation voltage. In yet another embodiment, the reference voltage V REF  is somewhat below the saturation voltage (V dsatl ) of the nMOSFET M 1 . In that case, the performance of the current mirror would be somewhat degraded but may still be better than the conventional enhanced output impedance current mirror. If the reference voltage were chosen to be exactly V dsatl , then the lowest possible output voltage would be just the sum of the saturation voltages of the two nMOSFETs M 1  and M 2 . 
     Furthermore, since process and temperature variations that apply to nMOSFET M 1  would also tend to apply to nMOSFETs M 5  through M 8  through device matching, the voltage V REF  would tend to increase and decrease more proportionally with V dsatl  with temperature and process variations, thereby reducing the impact of such process and temperature variations. 
     Another embodiment of the invention may be accomplished by substituting all nMOSFETs with pMOSFETs, and vice versa, and by tying any terminals that were connected to a lower voltage source to a high voltage source, and vice versa. FIG. 3 illustrates such an embodiment in which pMOSFETs N 1  through N 8  are similar to MOSFETs M 1  through M 8 , except that p-type MOSFETS are switched for n-type MOSFETS, and visa versa. Furthermore, current source J is connected to a low voltage supply instead of current source I being connected to a high voltage source. Also, MOSFETs N 1 , N 7  and N 8  are connected to high voltage source HIGH, instead of MOSFETs M 1 , M 7  and M 8  being connected to low voltage source LOW. 
     Additional embodiments of an enhanced output impedance current mirror will become apparent to those of ordinary skill in the art after having reviewed this description. For example, FIG. 4 illustrates an enhanced output impedance current mirror  400  that is similar to the enhanced output impedance current mirror  200  of FIG.  2  and the enhanced output impedance current mirror  300  of FIG. 3 except for the following characteristics. The ampl is a general amplifier that replaces the specific amplifier configuration of FIG. 2 that includes transistors M 3 , M 4 , M 5  and M 6  (or the specific amplifier configuration of FIG. 3 that includes transistors N 3 , N 4 , N 5  and N 6 ). In addition, resistive elements r 1  and r 2  replace the transistors M 7  and M 8  of FIG. 2 (or the transistors N 7  and N 8  of FIG. 3) in respective current return paths. Furthermore, the current source K replaces the transistor M 1  of FIG. 2 (or the transistor N 1  of FIG.  3 ). The terminal of the current source that is connected to the transistor O 2  will be also be referred to herein as the “first current electrode” of the transistor O 2 . The terminal on the other side of the channel region of the transistor O 2  will also be referred to as the “second current electrode” of the transistor O 2 . 
     The current mirror operates to effectively increase output impedance Rin when one of the resistive elements is properly sized so that the voltage drop across the resistor, when summed with the offset voltage between inverting terminal and the non-inverting terminal of the amplifier ampl, provides a voltage the current source K such that the current source K provides a predictable current. 
     FIG. 5 illustrates an enhanced output impedance current mirror  500  that is similar to the enhanced output impedance current mirror  400  of FIG. 4, except that a specific amplifier configured comprising transistors P 3 , P 4 , P 5 , P 6  is used to perform amplification similar to how amplification was performed using transistors M 3 , M 4 , M 5  and M 6  of FIG.  2 . In addition, NMOS transistor P 2  replaces transistor O 2 , which could have been an NMOS or PMOS transistor. Current Source L of FIG. 5 may be similar to current source K of FIG. 4, and resistive elements r′ 1  and r′ 2  of FIG. 5 may be similar to resistive elements r 1  and r 2  of FIG.  4 . 
     FIG. 6 illustrates an enhanced output impedance current mirror  600  that is similar to the enhanced output impedance current mirror  500  of FIG. 5, except that transistors Q 7  and Q 8  replace resistive element r′ 1  and r′ 2 . Transistors Q 3 , Q 4 , Q 5 , Q 6 , Q 7  and Q 8  may be similar to the transistors M 3 , M 4 , M 5 , M 6 , M 7  and M 8 , respectively, of FIG.  2 . Also, current source M may be similar to the current source L of FIG.  5 . 
     FIG. 7 illustrates an enhanced output impedance current mirror  700  that is similar to the enhanced output impedance current mirror  600  of FIG. 6, except that the sources of transistors R 5  and R 6  are both tied to the drain of transistor R 8 , and transistor R 7  is absent. Transistors R 2 , R 3 , R 4 , R 5  and R 6  may be similar to the transistors M 2 , M 3 , M 4 , M 5  and M 6  of FIG.  2 . Also, current source N may be similar to the current source M of FIG.  6 . 
     FIG. 8 illustrates an enhanced output impedance current mirror  800  that is similar to the enhanced output impedance current mirror  700  of FIG. 7, except that the there is no resistance in the return current paths. Instead, the voltage across the current source O is maintained by an intentional offset voltage imposed by passing different current densities through the resistors S 3  and S 4 . Transistors S 2 , S 3 , S 4 , S 5  and S 6  may be similar to the transistors M 2 , M 3 , M 4 , M 5  and M 6  of FIG.  2 . Also, current source O may be similar to the current source N of FIG.  7 . 
     Accordingly, an enhanced output impedance current mirror is obtained using minimal additional devices while allowing for a reduced minimum output voltage. The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes, which come within the meaning and range of equivalency of the claims, are to be embraced within their scope.

Technology Category: 3