Patent Document

TECHNICAL FIELD  
         [0001]    This invention relates to operational amplifiers, and more particularly to dual-mode multiple stage operational amplifiers.  
         BACKGROUND  
         [0002]    Two-stage CMOS operational amplifiers are advantageous in many circuits because they are able to provide a large transconductance, a fast settling time and sufficiently high gain.  
           [0003]    Two-stage operational amplifier techniques are well known. Certain common two-stage operational amplifiers include compensation components, such as, for example, a nulling resistor, and/or pole-splitting capacitor, configured to generate a zero and separate a dominant pole and a second order pole.  
           [0004]    Compensating a two-stage operational amplifier presents a challenge in a CMOS process that does not include a capacitor layer. One area-effective way to create a capacitor, is to utilize the gate capacitance of a MOSFET device with a formed channel. To keep the compensation capacitor turned on, however, the voltage difference between the two operational amplifier stages needs to be larger than the MOSFET threshold voltage under all of the process, supply, and temperature conditions. Such a solution may not be suitable for certain devices.  
           [0005]    Thus, there is a continuing need for improved operational amplifiers that are suitable for implementation in a CMOS integrated circuitry and perhaps other types of circuitry.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    A more complete understanding of the various methods and arrangements of the present invention may be had by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:  
         [0007]    [0007]FIG. 1. is a block diagram depicting a device having various component circuits including a memory module that includes an interface cell with output circuitry suitable for employing an operational amplifier in accordance with certain implementations of the present invention.  
         [0008]    [0008]FIG. 2 is a schematic diagram depicting an exemplary output circuit, as in FIG. 1.  
         [0009]    [0009]FIGS. 3 a - b  are schematic diagrams depicting conventional two-stage operational amplifiers having compensation circuits.  
         [0010]    [0010]FIGS. 4 a - b  are simplified schematic diagrams depicting a reconfigurable dual mode multiple stage operational amplifier having a compensation portion, in accordance with certain exemplary implementations of the present invention.  
         [0011]    [0011]FIG. 5 is a time-line chart depicting exemplary controlling signals for use with a reconfigurable dual mode multiple stage operational amplifier, in accordance with certain other exemplary implementations of the present invention.  
         [0012]    [0012]FIG. 6 is a block diagram depicting a pulse-generating portion of a reconfigurable dual mode multiple stage operational amplifier, in accordance with certain exemplary implementations of the present invention.  
         [0013]    [0013]FIGS. 7 a - b  are simplified schematic diagrams depicting reconfigurable dual mode multiple stage operational amplifiers that do not require compensation portions, in accordance with certain exemplary implementations of the present invention.  
         [0014]    [0014]FIGS. 8 a - b  are more detailed schematic diagrams depicting two different reconfigurable dual mode multiple stage operational amplifiers, as in FIGS. 4 a - b,  having compensation portions, in accordance with certain exemplary implementations of the present invention.  
         [0015]    [0015]FIGS. 9 a - b  are more detailed schematic diagrams depicting two different reconfigurable dual mode multiple stage operational amplifiers, as in FIGS. 7 a - b,  without compensation portions, in accordance with certain further exemplary implementations of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0016]    [0016]FIG. 1 is a block diagram depicting a device  100 , e.g., a computer or like appliance, having a main circuit board  101  configured to interconnect a memory device  102  to a processor  104 , for example through a chip set  106 . As depicted, memory device  102  includes an interface cell  108 . Interface cell  108  includes an output subsystem  110  having an output driver circuit  112 .  
         [0017]    [0017]FIG. 1 is just an exemplary implementation that includes an output driver circuit  112 . Those skilled in the art will recognize that an output driver circuit  112 ′ may also be a separate circuit, or part of another circuit too. The description that follows will, however, focus on certain exemplary implementations of output driver circuit  112  as used in memory device  102 , and more specifically on an operational amplifier portion of output driver circuit  112 .  
         [0018]    In certain conventional output subsystems  112 , output driver transistors are arranged in a geometric series of legs allowing 2 7  levels of output current. The legs of the output driver circuit  112  are formed by a plurality of two-transistor stacks (see, e.g., stack  210  in FIG. 2). Here, the bottom transistor is driven by an output pre-driver that carries the output data.  
         [0019]    The output subsystem circuit  112  shown in FIG. 2 is a simplified diagram of an output subsystem circuit having an operational amplifier  200 . Here, the output impedance of the output driver circuit  112  is significantly controlled by a V ictrl  voltage on the upper transistor of the output stacks  210 . Current control is accomplished by connecting the gate nodes of the upper transistors to the outputs of the V gate  distribution circuit. The V gate  distribution circuit logically combines current control values and an enable signal to produce the output driver leg-enable signals. The leg-enable signals have a logic “1” voltage level equal to V gate  voltage. Here, the V gate  voltage is regulated by operational amplifier  200 . In certain implementations, a single operational amplifier is configured to regulate the V gate  voltage for nine output drivers within a byte.  
         [0020]    As depicted in FIG. 2, output driver circuit  112  is shown as a single two-transistor stack  210 , wherein the bottom transistor is driven by the predriver and the upper transistor is driven by V ictrl , which is controlled by signal “Enable_b”. When the output driver is active, Enable_b is asserted, and V ictrl  is connected to V gate  through PMOS transistor  204 . When the output driver is inactive, Enable_b is de-asserted, and V ictrl  is discharged to ground through NMOS transistor  206 . The capacitor “C decouple    208  (e.g., 200-300 pF) is configured to minimize the noise on V ictrl .  
         [0021]    Operational amplifier  200  is configured as a unity gain buffer that regulates its output to a reference voltage V gRef . Voltage V gRef  is adjusted to an appropriate level to control the output impedance of output driver circuit  112 . Capacitor C vgate    212  at the output of operational amplifier  200  acts to stabilize the regulating operational amplifier.  
         [0022]    When the signal Enable_b is asserted, V ictrl  is pulled from ground to the level of V gRef , within 10 nS. Operational amplifier  200  has to be designed to have enough transconductance and a fast enough settling time to meet this timing requirement. Operational amplifier  200  also needs to have enough gain to pull V ictrl  significantly close to V gRef .  
         [0023]    A two-stage CMOS operational amplifier  200  is able to provide the large transconductance, fast settling time and high enough gain.  
         [0024]    Two-stage operational amplifier techniques are well known and have been published extensively. The most common technique is to use a nulling resistor, pole-splitting capacitor and Miller effect, to generate a zero and to separate the dominant pole and the second order pole. For an exemplary reference, see  MOS Operational Amplifier Design—A tutorial Overview,  by Paul R. Gray and Robert G. Meyer, published in the IEEE Journal Of Solid State Circuits, Vol. SC-17, No. 6, pp. 969-982, December  1982 . This article is incorporated herein, by reference.  
         [0025]    Exemplary schematics of a couple of conventional compensation techniques are provided in FIGS. 3 a - b.  In FIG. 3 a,  exemplary operational amplifier  200  includes a first stage  300  and a second stage  302 . Here, the necessary compensation  304  is provided by a capacitor. Similarly, exemplary operational amplifier  200  in FIG. 3 b  includes compensation  304 ′ as provided by a resistor and capacitor.  
         [0026]    Compensating a two-stage operational amplifier presents a challenge in a CMOS process that does not include a capacitor layer. One area-effective way to create a capacitor, however, is to utilize the gate capacitance of a MOSFET device with a formed channel. To keep the compensation capacitor turned on, the voltage difference between the two operational amplifier stages must be larger than the MOSFET threshold voltage under all of the process, supply, and temperature conditions. Using conventional compensation techniques, the dominant pole is created by the compensation capacitance. Even with a Miller effect, the compensation capacitance required to create a dominant pole is still large enough when the operational amplifier drives a large load capacitance. It takes a large layout area to create a large compensation capacitance by not using turned-on gate capacitance of a MOSFET device in a CMOS process without a capacitor layer. As a result, in the previous memory module designs to save layout area, the dominant pole is created from the loading of the operational amplifier. Contrary to other techniques the compensation capacitance created a zero and a higher order pole. The zero is used to improve the phase margin of the operational amplifier. In this way, the compensation capacitance value is greatly reduced, resulting in better layout area utilization.  
         [0027]    With this in mind, in the output subsystem  112  of FIG. 2, to decouple the noise in V ictrl , the value of C decouple    208  is about 300 pF. Depending on whether Enable_b is asserted, regulating operational amplifier  200  sees different capacitances on its output and its dominant pole location varies greatly. For example, at certain times (i.e., when transistor  204  is on) operational amplifier  200  sees both C vgate    212  and C decouple    208 , while at other times (i.e., when transistor  204  is off) it only sees C vgate    212 .  
         [0028]    One possible approach is to design the operational amplifier such that it is well compensated with the minimum output load (i.e., when Enable_b is de-asserted). However, this requires a large capacitance value for C vgate    212 , thereby resulting in higher power compensation and a greater layout area. This result would be unacceptable for many applications.  
         [0029]    Thus, there is a need for an improved regulating operational amplifier that is suitable for implementation in a CMOS integrated circuitry and perhaps other types of circuitry.  
         [0030]    The above stated need and others are satisfied by a reconfigurable dual-mode multiple stage operational amplifier  400 . Simplified diagrams are shown in FIGS. 4 a - b.  Here, operational amplifier  400  changes modes of operation according to the position of three switches (SW1  406 , SW2  408  and SW3  410 ).  
         [0031]    As depicted in FIG. 4 a , when SW1  406  is open, SW2  408  is closed and SW3  410  is connected to ground, operational amplifier  400  is configured in a single-pole mode.  
         [0032]    As depicted in FIG. 4 b , when SW1  406  is closed, SW2  408  is open and SW3  410  connects a compensation circuit  404  (e.g., similar to  304 / 304 ′) between the outputs of the first and second stages, operational amplifier  400  is configured in a two-pole mode.  
         [0033]    With reference once again to FIG. 2 (with operational amplifier  400  substituted for operational amplifier  200 ), when the signal Enable_b is asserted, operational amplifier  400  will see a large output loading. In that case, operational amplifier  400  will be configured in the two-pole mode and stabilized by compensation circuit  404 . When Enable_b is de-asserted, operational amplifier  400  will be placed in the one-pole mode (with compensation circuit  404  disabled) to drive the resulting smaller output loading.  
         [0034]    In this arrangement, operational amplifier  400  will have sufficient phase margin in both modes and most of the capacitance can be placed on V ictrl  to minimize noise. The resulting design is more robust, and area and power efficient.  
         [0035]    Furthermore, certain memory devices  102  (FIG. 1) have several power states for power saving features. For example, certain implementations include an “active” mode in which operational amplifier  400  is in a high power state and consumes more current. Operational amplifier  400  can be placed in one-pole mode or two-pole mode depending upon whether Enable_b is asserted. Thus, a high power state could be supported by placing operational amplifier  400  in a two-pole mode. Certain memory devices also have a “standby” mode, wherein operational amplifier  400  could be placed in one-pole mode.  
         [0036]    More detailed examples of such operational amplifiers are depicted in FIGS. 8 a - b.    
         [0037]    [0037]FIG. 8 a  depicts an exemplary operational amplifier  800  having a first stage  801 , a second stage  802 , a mirroring portion  804 , and a compensation circuit  404 . Here, with reference back to FIGS. 4 a - b,  SW 1   406  of is provided by transistors  806 , SW2  408  is provided by transistors  808 , and SW3  410  is provided by transistors  810 . Transistors  806 ,  808  and  810  are each configured to be selectively configured by either an Enable_b signal or the inverted version, Enable. A conventional inversion process is depicted by inverter  812 .  
         [0038]    [0038]FIG. 8 b  depicts yet another exemplary implementation of an operational amplifier having compensation circuit  404 . Here, operational amplifier  800 ′ is provided with a first stage  801 ′ that uses transistors  814 ,  816  and  810  to act as SW1  406 , SW2  408  and SW 410 , respectively.  
         [0039]    Another important aspect of this novel type of reconfigurable dual-mode operational amplifier is that if a simple pulse generator is added, the operational amplifier will work without a compensation circuit.  
         [0040]    If an appropriate width of pulse is generated from the edge assertion of signal Enable_b, for example, the pulse can then be used to selectively configure the operational amplifier. A time-line diagram depicting this signal generating process is provided in FIG. 5. Here, a conventional pulse generator  600 , as depicted in the block diagram of FIG. 6, generates a pulse signal  502  based on an edge detection of Enable_b signal  500 . Thus, during the assertion of the pulse, an operational amplifier  700  (see, FIG. 7 b ) will be configured in the two-pole mode. In a two-pole mode, operational amplifier  700  exhibits lower output impedance and it can pull the output from ground to a voltage level close to V gRef . Since this configuration does not use a compensation circuit, operational amplifier  700  may not have a sufficient phase margin and may ring around the final value at the end of the pulse. However, after the de-assertion of the pulse, operational amplifier  700  (see FIG. 7 a ) will be configured in the one-pole mode and will have a sufficient phase margin to settle its output to the final value. Thus, eliminating the compensation circuit results in a very simple and robust design.  
         [0041]    With reference to the diagrams in FIGS. 7 a - b,  by removing the compensation circuit, the design of operational amplifier  700  has been simplified in that there are only two switches (SW1  704  and SW2  706 ) in the first stage  701 . Note that the second stage  702  is essentially unchanged from second stage  402 , with the exception that there is no longer the need for a connection to any compensation components.  
         [0042]    More detailed examples of such alternative operational amplifiers are depicted in FIGS. 9 a - b.    
         [0043]    [0043]FIG. 9 a  depicts an exemplary operational amplifier  900  (without a compensation circuit) having a first stage  901 , a second stage  902 , and a mirroring portion  904 . Here, SW1  704  of FIGS. 7 a - b  is provided by transistors  906 . Similarly, SW2  706  of FIGS. 7 a - b  is provided by transistors  908 . Transistors  906  and  908  are each arranged to be selectively configured by either a Pulse signal or the inverted version, Pulse_b. A conventional inversion process is depicted by inverter  910 .  
         [0044]    [0044]FIG. 9 b  depicts yet another exemplary implementation of an operational amplifier without a compensation circuit. Here, operational amplifier  900 ′ is provided with a first stage  901 ′ that uses transistors  912  and  914  to act as SW1  704  and SW2  706 , respectively.  
         [0045]    Although the above examples have included PMOS and NMOS transistors, the techniques disclosed herein are also adaptable to circuits having other types of transistors, e.g., bipolar transistors, etc.  
         [0046]    Although some preferred implementations of the various methods and arrangements of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the exemplary implementations disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.

Technology Category: 5