Patent Document

BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Application  
           [0002]    The present invention is directed toward an EEPROM circuit, in particular a microcontroller that includes an EEPROM for storing program code and data that is capable of being written to and read from simultaneously. More specifically, the present invention relates to an EEPROM circuit comprising:  
           [0003]    a program array of a matrix of EEPROM cells arranged in columns and rows,  
           [0004]    a data array of a matrix of EEPROM cells arranged in columns and rows, said cells of said program and data array capable of being written, read, and erased;  
           [0005]    a reference voltage circuit coupled to said program array capable of producing voltages used to write to and erase data from said program array; and  
           [0006]    a current generation circuit coupled to said program array for supplying current to said array in operation.  
           [0007]    2. Description of the Related Art  
           [0008]    Many microcontrollers require embedded non-volatile memory blocks to store the system code, or programs that the microcontrollers execute. For some applications, a ROM memory can be used to store this system code, but this prohibits later changes from being made to the code. If the system code needs to be changed, a flash PROM is sometimes used.  
           [0009]    Additionally, many microcontrollers store data from computation results. In this case, use of an EEPROM is preferred, rather than the flash PROM used above, because of the ability to selectively delete some of the data stored That is, using an EEPROM, it is possible to delete only a portion of the previously stored data while leaving the desired data untouched. Flash PROMs do not have this sectional erase capability.  
           [0010]    If a particular microcontroller requires an EEPROM for a data storage section, then the non-volatile memory that stores the system code must also be an EEPROM, because it is prohibitively expensive and inconvenient to produce both an EEPROM and a Flash PROM on a single substrate for the microcontroller. It is expensive to produce such a chip because the processes that make EEPROMs and Flash PROMs are vastly different and incompatible with one another. Therefore, in those microcontrollers that store both programs and data, because the data storage cells must be EEPROMs, the program storage cells must also be EEPROMs.  
           [0011]    Microcontrollers that have two EEPROM sections normally have two complete and separate EEPROM macrocells. An EEPROM macrocell is a preformatted layout scheme that includes all of the necessary circuit sections for proper EEPROM operation. It includes a set of HV latches in which data to be programmed are temporarily latched prior to programming them into the EEPROM cells. It also includes a charge pump for generating the high voltages necessary to program and erase the EEPROM cells.  
           [0012]    It would be impossible to use a single EEPROM section to store both the system code and stored data from the computation results because of different functionality needed for these two processes. The system code portion needs to be executed (read) at the same time that data is being written (programmed). In conventional systems, this is impossible, because one task would have to wait for the other. It takes about 4/5 ms to program data into an EEPROM, during which time the system code could not be read. That time period is an impossibly long time period to have the microprocessor sit idle because no further portions of the system code could be read while data was being written. If the microprocessor was forced to be idle for this time period, it could not service interrupts during the entire 4/5 ms time period. Many systems specify that interrupts must be serviced much faster than 4/5 ms, thus the system code and data must be stored separately so that they can be accessed separately.  
           [0013]    Requiring two separate EEPROM macrocell blocks causes inefficiency, however. As noted above, most current designs use pre-made macroblocks to reduce design cost. That is, instead of creating a complete EEPROM portion from nothing, a standard cell library is used. In the case where two EEPROM portions are used, such as where both the system code and the data need to be in EEPROM blocks, using two standard macrocells causes many inefficiencies. One inefficiency is that typically the data EEPROM is much smaller than the EEPROM used to store the system code. Thus, using two identical preformatted macroblocks results in one EEPROM being underutilized. For example, a standard EEPROM macrocell may be 8 k in size, with 32 columns. That would mean there are 256 rows in that standard macrocell. It would be fairly easy to change this standard macrocell to be smaller, such as to 128 bytes, by simply removing the unnecessary rows. However, in that case, the charge pump and HV latches would be much larger than they would necessarily have to be, because they were originally designed to handle 32 columns and 256 rows, but are now only being used for 4 rows. The data storing EEPROM macrocell can be redesigned and optimized for efficiency to its size, for instance, by reducing the size of the charge pump and reducing the number of columns, but redesigning the smaller EEPROM results in an inefficiency that was hoped to be avoided by using the macrocell in the first place.  
           [0014]    The technical problem addressed by this invention is to provide an EEPROM that can have data written to a data memory array at the same time that data is read from a program memory array.  
         BRIEF SUMMARY OF THE INVENTION  
         [0015]    An embodiment of the present invention provides a single macrocell that can perform Read While Write (RWW) functions. Data and program (system code) memory space is provided in a single macrocell designed to eliminate redundant components.  
           [0016]    The macrocell includes two memory arrays, one for storing data, and one for storing the system code, or program. A charge pump for high voltage generation and high voltage latches remain similar to that of a single macrocell, but are shared across both the program and data memory arrays.  
           [0017]    Presented is an EEPROM circuit of the type described above and comprising:  
           [0018]    a program array of a matrix of EEPROM cells arranged in columns and rows;  
           [0019]    a data array of a matrix of EEPROM cells arranged in columns and rows, said cells of said program and data array capable of being written to, read from, and erased;  
           [0020]    a reference voltage circuit coupled to said program array capable of producing voltages used to write to and erase data from said program array;  
           [0021]    a current generation circuit coupled to said program array for supplying current to said program array in operation; wherein said reference voltage circuit and said current generation circuit are additionally coupled to said data array; and  
           [0022]    means for selectively connecting at least one of the rows of said program array to one of the rows of said data array, and for selectively connecting at least one of the columns of said program array to one of the columns of said data array.  
           [0023]    Also presented is a method of operating an EEPROM circuit of the type described above, the EEPROM circuit comprising:  
           [0024]    a program array of a matrix of EEPROM cells arranged in columns and rows,  
           [0025]    a data array of a matrix of EEPROM cells arranged in columns and rows, said cells of said program and data array capable of being written, read, and erased;  
           [0026]    a reference voltage circuit coupled to said program and data arrays capable of producing voltages used to write to and erase data from said arrays;  
           [0027]    a current generation circuit coupled to said program and data arrays for supplying current to said arrays in operation, the method comprising:  
           [0028]    accepting signals to the EEPROM circuit for writing data to said program array and writing data to said program array;  
           [0029]    accepting signals to the EEPROM circuit for writing data to said data array and writing data to said data array;  
           [0030]    accepting signals to the EEPROM circuit for reading data from said program array and reading data to said program array;  
           [0031]    accepting signals to the EEPROM circuit for reading data from said data array and writing data to said data array; and  
           [0032]    accepting signals to the EEPROM circuit for reading data from said program array while writing data to said data array and simultaneously writing data to said data array while reading data from said program array. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0033]    The characteristics and advantages of the device according to the invention will be seen from the description, following herein, of an embodiment given as an indication and not limiting with reference to the attached drawings in which:  
         [0034]    [0034]FIG. 1 shows a block diagram of an EEPROM structure according to the present invention;  
         [0035]    [0035]FIG. 2 schematically shows a high voltage latch according to a standard EEPROM cell;  
         [0036]    [0036]FIG. 3 schematically shows a high voltage latch according to the EEPROM structure shown in FIG. 1;  
         [0037]    [0037]FIG. 4 schematically shows a control-gate line latch according to a standard EEPROM cell;  
         [0038]    [0038]FIG. 5 schematically shows a control-gate line latch according to the EEPROM structure shown in FIG. 1;  
         [0039]    [0039]FIG. 6 shows a standard pre-coder according to a standard EEPROM cell; and  
         [0040]    [0040]FIG. 7 shows a read while write pre-coder according to the EEPROM structure shown in FIG. 1. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0041]    Shown in FIG. 1 is a block diagram of an EEPROM memory architecture  10  according to an embodiment of the present invention. Main blocks of the memory architecture  10  are shown along with their interconnections.  
         [0042]    The inventive EEPROM circuit  10  includes a program array  20  and a data array  30  of EEPROM memory cells, each formed in a matrix of rows and columns. These arrays are used to store the system code and the temporary data stored in a microcontroller, respectively. Each of the arrays  20 ,  30  are coupled to a decoder in a standard fashion. There is a program row decoder  22  for the program array  20 , and a data row decoder  32  for the data array  30 .  
         [0043]    Also included in the circuit  10  are a set of high voltage analog circuits  40 , which include a reference voltage circuit  40 A and a current generator  40 B. In one embodiment, this can include a band-gap reference circuit, and a charge pump, respectively. The set of high voltage analog circuits  40  is coupled to an interaction circuit  42  including a set of HV latches and a column decoder. The HV latches of the circuit  42  include a bit-line latch  140  and a control gate (CG) line latch  240  as described below with respect to FIGS. 3 and 5. The column decoder portion of the interaction circuit  42  is a multiplexer as also described in greater detail below. The interaction circuit  42  is coupled to both the program array  20  and the data array  30 . In this way, the interaction circuit  42  services both arrays  20 ,  30 , and the need for independent interaction circuits for each array, as is required by the prior art, is eliminated.  
         [0044]    The interaction circuit  42  is also coupled to a set of sense amplifiers  44 , which are used for both the program array  20  and the data array  30 . In one embodiment, eight sense amplifiers are included in the set of sense amplifiers  44  for use providing an eight bit output.  
         [0045]    Also included in the EEPROM circuit  10  are a set of row predecoders  50  and a set of column predecoders  52 . The row predecoders  50  couple to both the program row decoder  22  and the data row decoder  32 , and include a standard predecoder  300  and a modified predecoder  330  as described with reference to FIGS. 6 and 7 below. The set of column predecoders  52  is coupled to the interaction circuit  42 , which in turn is coupled to the program array  20  and the data array  30 .  
         [0046]    Further, the inventive EEPROM circuit  10  includes a logic interface  60  used to interface with signals of a microcontroller.  
         [0047]    One of the major differences in the EEPROM circuit  10  from those of the prior art concerns the interaction circuit  42 , which is made from HV latches and a column decoder. A standard HV latch  100  for a conventional macrocell is shown in FIG. 2. The standard HV latch  100  includes a typical latch structure  102 , supplied by a high voltage HV  104  and having an input node  106 . The latch structure  102  has an output  108  and a negated output  110 .  
         [0048]    The output  108  of the latch structure  102  is coupled to the control gate of a pass transistor  116 . This pass transistor  116  is used to couple a high voltage for programming (shown as BLP  120 ) to a bit line BL  122  that is coupled to the HV latch  100 . In the embodiment shown in FIG. 2, the pass transistor  116  is an NMOS transistor, so the high voltage BLP  120  is connected to the bit line BL  122  when the latch is set, so that the output  108  of the latch structure  102  is HIGH.  
         [0049]    During “read” mode, every latch structure  102  coupled to the specific bit lines  122  are in the reset state. In that state, the output  108  of the latch structure  102  is LOW. This keeps the pass transistor  116  OFF, which in turn keeps the high voltage BLP  120  separated from the bit lines BL  122 . In this condition, the bit lines BL  122  are instead coupled to the respective column decoders, which reduce the necessary size of the array, for instance, to 8 bits for an 8 bit bus. Additionally, sense amplifiers are coupled to a bus  128  for reading the data from the cells over the bit lines BL  122 .  
         [0050]    During “write” mode, the same bus  128  is used when the data stored in the HV latches are required to be written. In this situation, a load signal  130  activates to HIGH and the bus  128  is kept to 0 if the latch structure  102  is desired to be set (output  108  HIGH), and is kept at 1 if the latch is desired to be kept in the reset state (output  108  LOW).  
         [0051]    In a preferred embodiment, the EEPROM circuit  10  (FIG. 1) allows reading of the program array  20  while writing to the data array  30 , but not vice-versa. It would be within the knowledge of one skilled in the art to reverse these requirements, and to make either array available while writing to the other. However, in a microprocessor, it is necessary to read program code while writing data, and not vice-versa, so the preferred embodiment shown in FIG. 1 will most often be implemented.  
         [0052]    A modified HV latch  140 , as used as a component of the interaction circuit  42  of FIG. 1, is shown in FIG. 3. In FIG. 3, the HV latch  140  is similar to the HV latch  100  of FIG. 2. A difference lies with the addition of an extra coupling transistor  146  that couples the bit line for the program array, BL  122 , with a bit line for the data array, BLDATA  142 , when the coupling transistor is driven by a PW/DR signal. The PW/DR signal stands for program write/data read and is used when either of these conditions are true, as further described below. The program bit line BL  122  is directly coupled to the read-path, while data memory is directly connected to the write-path. In this way, when the coupling transistor  146  is OFF, the bit line BLDATA  142  can simultaneously be coupled to the high voltage line BLP  120  (for programming (writing)) from the high voltage analog circuits  40  while the bit line BL  122  is coupled to the bus  128  for reading. The coupling transistor  146  in effect “de-couples” these circuits from one another when the PW/DR signal is OFF.  
         [0053]    Another set of HV latches are located on the control-gate line latch, and are shown in FIG. 4 (a standard HV latch  200 ) and FIG. 5 (the inventive latch  240 ).  
         [0054]    In FIG. 4, the standard HV latch  200  includes the same typical latch structure  102  as shown in FIGS. 2 and 3. The output  108  of the latch structure  102  controls a pass transistor  210 , which is coupled between a high voltage node CG  220  and a program control gate line CGT  222 . The remainder of the HV latch  200  is similar but not identical to the HV latch  100  of FIG. 2.  
         [0055]    [0055]FIG. 5 shows the inventive HV latch  240 , which is similar to the standard HV latch  200  of FIG. 4, but also contains an additional pass transistor  246  that connects the control gates of the program array CGTEXE  242  to the high voltage node CG  220  only when programming is requested in the programming array  20  (FIG. 1). The PW/DR signal that drives the additional pass transistor  246  is the same signal that also drives the extra coupling transistor  146  in FIG. 3.  
         [0056]    The connection between program and data bit lines  122  BL and  142  BLDATA (FIG. 3), and also the connection between the data and program CG lines CGT 222  and CGTEXE  242  (FIG. 5) is made when the PW/DR signal is HIGH, through the action of the pass transistors  146  and  246 , respectively. The PW/DR signal that drives these pass transistors  146 ,  246  is generated by the logic interface  60  of FIG. 1. In particular, the PW/DR signal is HIGH when there is a request to program the program array  20 , or when data is requested to be read from the data array  30 .  
         [0057]    With the configuration as shown in FIGS. 3 and 5 and as described above, while the program array  20  is being programmed, the data array  30  cannot be read. During this time period when the PW/DR signal is HIGH, the program array  20  and data array  30  are connected together. All of the rows in the data array  30  are grounded, so high voltages directed to the program array  20  don&#39;t reach any of the cells in the data array  30 .  
         [0058]    Additionally, the PW/DR signal is HIGH when data is read from the data array  30 . During this phase, programming cells in the program array  20  is not possible. Even in this case, the program array  20  and data array  30  are connected together by the actions of the pass transistors  146  and  246 . When data is requested to be read from the data array  30 , all of the rows in the program array  20  are grounded to prevent any crossing of signals.  
         [0059]    In other situations, the program and data arrays  20 ,  30  are not connected together. Reading from the program array  20  (prior to executing the system code) is possible even if data is being written in the data array  30  because bit lines and control gate lines are independent.  
         [0060]    Another modification has been introduced on row-predecoder circuitry  50  of FIG. 1. In a RWW configured EEPROM, both precoder blocks  300  (FIG. 6),  330  (FIG. 7) are present in the row predecoder  50 , while in a standard program EEPROM, only the standard predecoder  300  is present.  
         [0061]    In the FIGS. 6 and 7, predecoder signals have been named P&lt;i&gt;. The logical AND of P 0 &lt;i&gt;, P 1 &lt;j&gt;, P 2 &lt;k&gt;, P 3 &lt;l&gt;, constitutes the last stage of the rowdecoder. FIGS. 6 and 7 show the difference between generator of P 0 &lt;i&gt;signals for the program array  20  and P 0 DATA&lt;i&gt;signals for the data array  30 .  
         [0062]    RX(i) and RNX(i) are the row addresses buffered or inverted respectively. They are seen in both FIGS. 6 and 7. These row addresses are generated by a circuit that controls global programming, where all rows must be selected together. In this situation all RX and RNX are set to logic  1 .  
         [0063]    The standard predecoder circuit  300  of FIG. 6 is composed of normal AND of RX(i) signals through a set of NAND gates  310  and inverters  312 . POCTL is a signal that disables all rows in the program array  20  when it is low (this situation is obtained with P 0 &lt;i&gt;=0 for each i). It is used to deselect all rows when the memory is not selected or when a reading operation is wanted in the data array  30 . In this situation all rows in the program array  20  have to be grounded.  
         [0064]    The modified predecoder  330  for the data array  30 , shown in FIG. 7, introduces a series of latches  320 , in addition to the NAND gates  310  of the predecoder circuit shown in FIG. 6. These latches  320  are necessary when the user is performing a writing operation in the data array  30 . The latched row (where the programming operation will be done) must be the row on which all writing cycles are accomplished But during this phase, it is possible that reading cycles in the program array  20  are required and so RX(i) and RNX(i) can change. Therefore, latching row predecoder signals for the data array  30  is necessary for keeping track of last data-writing operation.  
         [0065]    A signal LATCHPDATAN, which is an input to the latches  320 , is used for this reason. This signal is HIGH (the not latching situation) when either only reading operations are required, or, if writing data to the data array  30 , only after the address is stable and the data in the data array  30  is actually being written.  
         [0066]    A signal DATASELN is the signal that forces all of the P 0 DATA&lt;i&gt;signals to 0, and therefore all rows in the data array  30  are grounded when the signal is present. All of the rows in the data array  30  are grounded when it is either not selected, or when a programming operation is required in the program array  20 . In this case the program and data arrays  20 ,  30  are coupled together, but only the selected row in the program array  20  has to be selected.  
         [0067]    It should be noted that, because the RX&lt;i&gt;and RNX&lt;i&gt;signals are common to both the program and data arrays  20 ,  30  it is not possible to simultaneously perform a global program in the data array  30  while the program array  20  is being read. Thus, the RWW feature enabled by the inventive EEPROM structure  10  is not available whenever a global operation is requested on all of the cells of the data array  30  (global request). This constraint is not really a large problem because global requests are normally only used during testing algorithms, and not during normal user-activities.  
         [0068]    The proposed configuration is being implemented on 0.5 um FLOTOX EEPROM process. In that production, the size of the data array  30  is 128 bytes and the size of the program array  20  can be up to 8 kbytes. The gain in area-saving is about 19% for an 8 kb sized program array  20 , and 37% for a 1 kbyte sized program array  20 . These figures do not take into consideration the extra savings that can be realized from optimally designing a separate small EEPROM data array  30 , but, as mentioned above, that process is time consuming and expensive in resources. With the present solution, the data array  30  can be made of rows identical to those in the program array  20 , thereby also increasing the design efficiency by using a standard modular design.  
         [0069]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Technology Category: g