Patent Document

RELATED APPLICATION 
   This application claims priority to U.S. Provisional Application Ser. No. 60/498,862, filed Aug. 22, 2003, the disclosure of which is incorporated by reference herein. 

   TECHNICAL FIELD 
   This invention relates to voltage level shifters and more particularly, to level shifters that shift from high voltages to lower voltages. 
   BACKGROUND 
   Historically, the primary mode of reducing power consumption in electronic circuits has been to aggressively scale down the power supply voltage. This power supply reduction follows naturally for CMOS technologies since the Moore&#39;s Law scaling of processes into the nanometer range has resulted in gate oxide breakdown voltages on the order of 3.3 volts, 2.5 volts, 1.8 volts and lower. While effective in mitigating power consumption, this reduced breakdown voltage places significant limitations on the interconnection of these devices with other higher voltage systems. Such high voltage systems include 5 volt Legacy hardware and 28 volt aerospace hardware. 
   A typical solution to this problem is to add intermediate control circuitry between the integrated circuit and the external high voltage system. In this manner the system logic is performed at efficient low voltage levels, while the output is driven from an external source. This solution is viable, however the size and complexity of the overall design is increased considerably. A second typical solution is to use an integrated circuit process that is capable of laying down thick as well as thin gate oxides. This enables low voltage as well as high voltage transistors to be laid down on the same substrate. However, this alteration of the original fabrication process is prohibitively expensive in many applications. Further both of these solutions suffer from another problem—something external to the desired integrated circuit fabrication process must be added to the final design. In extreme environment applications (i.e. high temperature, low temperature, high radiation, high pressure, corrosive, etc.) this is not always acceptable. The integrated circuit fabrication process has been chosen for its temperature, radiation, and pressure characteristics. By adding external devices or altering the fabrication process these required characteristics can be lost. 
   This invention arose out of a need to develop a high voltage to low voltage logic level shifters that can be fully integrated onto the same substrate as the low voltage logic circuitry that controls it. That is, without altering the fabrication process in any way, this invention creates a means by which to control high voltage signals that exceed the breakdown voltage of the process used for fabrication. 
   SUMMARY 
   A shifter circuit comprises, in one embodiment, an input voltage divider stage comprising multiple transistors arranged in a transistor stack defining a plurality of intermediate nodes. The transistor stack is connected between an input signal and ground and has at least one output. An inverting buffer stage is connected to a supply voltage and coupled to the input voltage divider&#39;s output. The inverting buffer stage is configured to provide an inverted output signal. Means are provided for stepping up the current drive capability of the inverted output signal, receiving the stepped up output signal and providing a level-shifted output signal at a voltage level lower than that of the input signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of an exemplary circuit in accordance with one embodiment. 
       FIG. 2  is a schematic diagram of an exemplary circuit in accordance with one embodiment. 
       FIG. 3  is a schematic diagram of an exemplary circuit in accordance with one embodiment. 
       FIG. 4  is a schematic diagram of an exemplary circuit in accordance with one embodiment. 
   

   DETAILED DESCRIPTION 
   Overview 
     FIG. 1  shows an exemplary circuit diagram of a high voltage to low voltage level shifter circuit in accordance with one embodiment generally at  100 . The illustrated circuit comprises an input voltage divider stage  102 , an inverting buffer stage  104 , a buffer stage  106  and an output stage  108 . 
   The level shifter circuit described below is particularly well-suited for use in connection with low voltage, deep sub-micron processes, e.g. SOI processes. It is to be appreciated and understood, however, that the described circuit is not limited to SOI contexts. Rather, other types of fabrication processes can be utilized to implement the illustrated circuit, e.g. bulk processes, non silicon processes, and others, as will be appreciated by the skilled artisan. In the SOI context, however, the design about to be described takes advantage of SOI properties, as will become apparent below. 
   It is to be appreciated and understood that the described circuit is not limited to any one particular high voltage level or to any one particular low voltage level. Rather, the circuit can be configured and scaled to arbitrarily high levels and arbitrarily low levels. 
   In this embodiment, an input logic signal V in  drives input voltage divider stage  102  and the voltage divider stage is tied between V in  and ground. The inverting buffer stage  104  taps the input voltage divider from one or more points to generate the low voltage level at its output. Advantageously, in the SOI embodiment, this stage takes advantage of the low capacitances of SOI transistors, as will be appreciated by the skilled artisan. The buffer stage  106  steps up the current capability of inverting buffer stage  104 , while maintaining its voltage level, to better drive a large output stage. 
   Exemplary Circuit 
     FIG. 2  shows an exemplary high voltage to low voltage level shifter circuit in accordance with one embodiment, generally at  100   a . Like numerals from the  FIG. 1  example have been used where appropriate, with differences being indicated with the suffix “a”. Accordingly, circuit  100   a  comprises an input voltage divider stage  102   a , an inverting buffer stage  104   a , a buffer stage  106   a  and an output stage  108   a.    
   Input voltage divider stage  102   a  comprises, in this example, transistors in the form of MOSFETs  208 ,  210 ,  212  and  214 . In this particular example, each transistor has its source tied to the bulk contact. This is because the circuit is implemented using an SOI process. As noted above, however, such need not necessarily be the case. Hence, in other implementations, the source/bulk connection need not be made. 
   In this particular implementation, transistors  208  and  210  are p-channel devices and have their gates tied to their respective drains. Similarly, transistors  212  and  214  are n-channel devices and have their gates tied to their respective drains. Such arrangement, as will be appreciated by the skilled artisan, constitutes a diode connection. Transistors  208 ,  210 ,  212  and  214  constitute a transistor stack having intermediate nodes interconnecting the transistors, as will become apparent. 
   Transistor  208  is connected by its drain to the source of transistor  210 . The connection between these transistors constitutes an intermediate node. Transistor  210  has its drain connected to the drain of transistor  212  which constitutes another intermediate node. Transistor  212  has its source connected to the drain of transistor  214  which, in turn, constitutes another intermediate node. The source of transistor  208  is tied to V in , which is the input signal that is being level shifted. The source of transistor  214  is tied to ground. 
   Each of the inverting buffer stage  104   a , buffer stage  106   a  and output stage  108   a  is connected between V dd  (the level being shifted to) and ground. In this embodiment, the output of the input voltage divider stage  102   a  is taken from two intermediate nodes. A first output is taken from the node connecting the drains of transistors  210  and  212 , and is used to drive the gate of transistor  216  (a p-channel device) in the inverting buffer stage  104   a . A second output is taken from the node connecting the source of transistor  212  and the drain of transistor  214 , and is used to drive the gate of transistor  218  (an n-channel device) in the inverting buffer stage  104   a.    
   The output of the inverting buffer stage  104   a  is taken from the node that ties together the drains of transistors  216  and  218  and is used to drive the gates of transistor  220  (a p-channel device) and transistor  222  (an n-channel device) in the buffer stage  106   a . The drains of transistors  220  and  222  are tied together to define a node that drives the gates of transistor  224  (a p-channel device) and transistor  226  (an n-channel device) in buffer stage  106   a.    
   The output of buffer stage  106   a  is taken from the node that ties the drains of transistors  224  and  226  together and is used to drive the gates of transistor  228  (a p-channel device) and transistor  230  (an n-channel device) in output stage  108   a.    
   The output V out  of output stage  108   a  is taken from the node that ties together the drains of transistors  228  and  230 . 
   In Operation 
   The primary level shifting function, in accordance with the  FIG. 2  embodiment, is performed by input voltage divider stage  102   a  and inverting buffer stage  104   a . Input voltage divider stage  102   a  is configured, in this embodiment, as a diode stack that has been sized to cause the appropriate voltage drop across each device. It is extended or shortened depending on the required input level. Inverting buffer stage  104   a , as noted above, is an inverting buffer that is driven by two points on the diode stack. 
   As an example of how this circuit can be employed, consider  FIG. 3  and assume that the circuit is being used to shift down from 5 volts to 2.5 volts. Here, V dd  is the supply voltage for the circuit and is the voltage level to which the circuit is shifting—in this example 2.5 volts. V in  is the input voltage and is pulsing between 0 and 5 volts. When V in  is at 5 volts, the input voltage divider stack is sized to divide the signal down to 2.5 volts on the node connecting the drains of transistors  210  and  212 . Accordingly, the voltage at the node just below (i.e. the node connecting the source of transistor  212  and the drain of transistor  214 ) is 1.25 volts. The 2.5 volts that drives the gate of transistor  216  turns that transistor off (indicated by the dashed transistor), while the 1.25 volts that-drives the gate of transistor  218  turns that transistor on. When this happens, there is a 0 volt signal at the common drain point between transistors  216 ,  218 . 
   When the V in  falls from 5 volts to 0 volts, there will be 0 volts across the input voltage divider stage  102   a . This causes all of the intermediate nodes in that stage to fall to 0 volts. When this happens, as shown in  FIG. 4 , transistor  218  is turned off and transistor  216  is turned on. This, in turn, causes the voltage at the common drain between transistors  216 ,  218  to rise to 2.5 volts. 
   The buffer stage  106   a  then steps up the current capability of inverting buffer stage  104   a , while maintaining its voltage level, to better drive a large output stage, such as output stage  108   a , as will be appreciated by the skilled artisan. 
   By driving inverting buffer stage  104   a  by two points rather than one, difficulties created by small process deviations that can cause malfunction and device failure in low breakdown processes can be mitigated. Also, this allows for greater deviation from the nominal input signal level, while still maintaining the appropriate output level. 
   As will be appreciated by the skilled artisan, one challenge in using a large diode stack for level shifting is that the diode stack has a significant output resistance that is in parallel with the gate capacitance of any following stage. This resistance/capacitance parallel combination creates an RC decay effect when the device switches from a high state to a low state. Since the output resistance is a fixed value, the gate capacitance of the inverting buffer stage should be minimized. Accordingly, using an SOI process, which has inherently lower gate capacitances, constitutes a very desirable design feature. 
   Additionally, very small or minimum geometry transistors can be utilized to reduce gate capacitance to the extent possible. The advantages gained by this design are higher frequencies of operation, quicker overall system response, and greater scalability to higher input voltages. For example, in one implementation, the circuit was used, with a larger transistor stack in the input voltage divider stage  102   a , in connection with an application that shifted from 28 volts to 2.5 volts. 
   In Use 
   Uses of the above-described circuit include, by way of example and not limitation the following: providing an interface between low voltage integrated circuit technologies and other integrated circuit technologies that operate at higher logic levels, control of electromechanical actuators, control of gas and liquid apertures, control of high pressure propellant apertures, MEMS device control, system-on-chip power management, and power converter feedback control loops. Further, various embodiments find wide use in extreme environment applications, where the processes used for fabrication of the integrated circuits are chosen specifically for there tolerance to environmental variables, not breakdown voltage. As stated previously, the levels used here are not fixed, but can vary as application is needed. 
   Although the invention has been described in language specific to structural features and/or methodological steps, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or steps described. Rather, the specific features and steps are disclosed as preferred forms of implementing the claimed invention.

Technology Category: 5