Patent Document

BACKGROUND 
     Unless otherwise indicated, the foregoing is not admitted to be prior art to the claims recited herein and should not be construed as such. 
     Modern portable applications may require power management devices that connect directly to Li-ion batteries. Such configurations can subject the sensitive circuits of the power management devices to voltages of 4.8V or higher. In 28 nm CMOS technologies, standard IO devices can have a maximum rating (V max ) of about 2.3V. Higher voltage devices with V max  of 5V can be fabricated in 28 nm technology, but at significantly higher mask costs and incurring power efficiency degradation. V max  typically refers to the gate-source voltage (V gs ) or gate-drain voltage (V gd ) of the device. 
     Merely to illustrate this point,  FIG. 4  shows an example of a power stage using 28 nm technology FETs. For this example, suppose V max  is 2.3V and the input voltage V in  is 3×V max . The output V out  of the power stage will therefore swing from 0V to 3×V max . The gates of Q 1  and Q 2  may be driven by a gate driver; for example, a switching power supply, a Class D amplifier, etc.  FIG. 4  shows a configuration of a switching supply in which the power stage outputs 3×V max . In order for V out  to output 3×V max , the gate of Q 2  needs to be grounded in order to turn OFF Q 2  (the gate of Q 1  is driven to 2×V max  in order to turn ON Q 1 ). However, driving the gate of device Q 2  to ground when its drain is at 3×V max  creates a condition where V gd  of Q 2  exceeds its V max  rating, which over time can break down the gate oxide layer. 
     SUMMARY 
     A circuit in accordance with the present disclosure may include an output transistor having an output terminal and a control terminal. A capacitive coupling between the control terminal and the output terminal may be configured to drive the control terminal with a coupled signal that continuously tracks an output signal on the output terminal. A biasing circuit connected to the control terminal may be configured to provide a DC bias voltage that is combined with the coupled signal to provide a drive signal on the control terminal. 
     In some aspects, the circuit may further include a first transistor device and a second transistor device. The second transistor device may be a cascode of the first transistor device. The first transistor device may have an input terminal configured for a connection to an input voltage, wherein the capacitive coupling includes a first capacitance between the control terminal of the output transistor device and the output terminal of the output transistor device and a second capacitance between the input terminal of the first transistor device and the control terminal of the output transistor device. 
     In some aspects, the capacitive coupling between the control terminal of the output transistor device and the output terminal of the output transistor device may be a parasitic capacitance between the control terminal and the output terminal. In some aspects, the capacitive coupling may be a capacitor connected between the control terminal and the output terminal. 
     A circuit in accordance with the present disclosure may include a first stack comprising a first transistor, a second transistor, and a third transistor. The third transistor may have a control terminal and an output terminal. The circuit may further include a second stack connected to the first stack at a node. A biasing circuit may be connected to the control terminal of the third transistor device. A capacitive coupling between the control terminal of the third transistor and the output terminal of the third transistor may be configured to couple an output signal at the output terminal as a coupled signal to the control terminal. 
     The biasing circuit may be configured to provide a DC bias voltage that combines with the coupled signal to produce a drive signal on the control terminal. The biasing circuit may be further configured to respond substantially without delay to changes in a voltage level of the drive signal and vary a voltage level of the DC bias voltage to remain between a first voltage level and a second voltage level in response to changes in the voltage level of the drive signal. 
     In some aspects, the capacitive coupling may include a parasitic capacitance between the output terminal of the third transistor device and the control terminal of the third transistor device. In some aspects, the capacitive coupling may further include a second capacitor between the output terminal of the third transistor device and the control terminal of the third transistor device. 
     A method in a circuit in accordance with the present disclosure may include providing a divided output signal at an output terminal of the transistor as a coupled signal to a control terminal of the transistor using a capacitive coupling between the output terminal and the control terminal. A DC bias voltage may be generated and combined with the coupled signal to provide a drive signal on the control terminal of the transistor. The method may include responding, substantially without delay, to variations in a voltage level of the drive signal by varying a voltage level of the DC bias voltage to remain between a first voltage level and a second voltage level. 
     A circuit in accordance with the present disclosure may include means for providing a divided output signal at an output terminal of a transistor in the circuit as a coupled signal to a control terminal of the transistor using a capacitive coupling between the output terminal and the control terminal, means for generating a DC bias voltage, means for providing a drive signal on the control terminal of the transistor by combining the DC bias voltage with the coupled signal, and means for responding, substantially without delay, to variations in a voltage level of the drive signal by varying a voltage level of the DC bias voltage to remain between a first voltage level and a second voltage level. 
     The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       With respect to the discussion to follow and in particular to the drawings, it is stressed that the particulars shown represent examples for purposes of illustrative discussion, and are presented in the cause of providing a description of principles and conceptual aspects of the present disclosure. In this regard, no attempt is made to show implementation details beyond what is needed for a fundamental understanding of the present disclosure. The discussion to follow, in conjunction with the drawings, makes apparent to those of skill in the art how embodiments in accordance with the present disclosure may be practiced. In the accompanying drawings: 
         FIG. 1  illustrates a high level block diagram of a power supply in accordance with embodiments of the present disclosure. 
         FIGS. 2 and 2A  illustrate cascode stacks in accordance with the present disclosure. 
         FIG. 3  illustrates an example of a biasing circuit. 
         FIG. 4  illustrates a conventional design. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be evident, however, to one skilled in the art that the present disclosure as expressed in the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein. 
       FIG. 1  shows a switched power supply  10  configured in accordance with the present disclosure to supply an output voltage V out  from an input supply voltage V in . The configuration shown in  FIG. 1  represents a buck converter. However, persons of ordinary skill will appreciate that any switched power supply architecture may be configured in accordance with the present disclosure; e.g., boost converter, Class D amplifier, and the like. A control section  12  may receive the output voltage V out  of the switched power supply  10  as feedback signal to control a gate driver section  14 . The gate driver section  14  may generate drive signals  14   a  to drive a HI-side stack  102  and drive signals  14   b  to drive a LO-side stack  104 . Inductor L and output capacitor C out  may complete the buck converter. 
     As shown in  FIG. 2 , in some embodiments, the HI-side stack  102  and LO-side stack  104 , each, may comprise a cascode stack configuration. The HI-side stack  102  and LO-side stack  104  may connect at an output node  203 . For the purposes of explanation, the supply voltage V in  will be 3×V max  and V out  can swing between 0V and 3×V max , where V max  represents the maximum transistor V gd . For example, if V max  is 1.8V, then V out  can swing from 0V to 5.4V. For a configuration where V in =3×V max  and V max  is 1.8V, HI-side stack  102  may comprise three transistor devices P 1 , P 2 , P 3 . In some embodiments, the transistor devices may be PMOS devices. Likewise, the LO-side stack  104  may comprise three transistor devices N 1 , N 2 , N 3 , which in some embodiments may be NMOS devices. It will be appreciated that the HI-side stack  102  and LO-side stack  104  may be configured with different numbers of transistors depending on parameters such as V in  and V max . 
     In some embodiments, the HI-side drive signal  14   a  may be coupled to the gate of P 1 . The HI-side drive signal  14   a  may be a pulse that swings between 3×V max  and 2×V max . The LO-side drive signal  14   b  may be coupled to the gate of N 1 . The LO-side drive signal  14   b  may be a pulse that swings between 0V and V max . In accordance with the present disclosure, the gates of P 2  and N 2  are not driven by the gate drive circuitry and may be biased at fixed voltages. In some embodiments, for example, the gate of P 2  may be biased at a fixed DC level of 2×V max , and similarly, the gate of N 2  may be biased at a fixed DC level of V max . 
     In accordance with the present disclosure, a biasing circuit  212  may be connected to the gate of P 3 . A biasing capacitor C p  may be connected between a supply rail for V in  and the gate of P 3 . A biasing circuit  214  may be connected to the gate of N 3 , and a biasing capacitor C n  may be connected between ground potential and the gate of N 3 . The biasing circuits  212 ,  214  may be configured as means for generating a DC bias V bias ±Δ. V bias  may be a value between 2×V max  and V max . In some embodiments, for example, V bias  may be 1.5×V max . 
     The drain of P 3  may be capacitively coupled to the gate of P 3 , thus coupling an output signal at node  203 , as a coupled signal, to the gate of P 3 . The output of the biasing circuit  212  may be combined with the coupled signal as means for providing a drive signal on the gate of P 3 . Likewise, the drain of N 3  may be capacitively coupled to the gate of N 3 , thus coupling the output signal at node  203 , as a coupled signal, to the gate of N 3 . The output of the biasing circuit  214  may be combined with the coupled signal as means for providing a drive signal on the gate of N 3 . 
     In some embodiments, the parasitic capacitances C x1 , C x2 , respectively, of transistors P 3  and N 3  may provide the respective capacitive coupling. As persons of ordinary skill understand, parasitic capacitances arise within the structures of transistor device, such as the gate and drain regions. In other embodiments, explicit capacitors may used.  FIG. 2A  for example, illustrates an embodiment using explicit capacitive elements C 1 , C 2 , in addition to respective parasitic capacitances C x1 , C x2 . The capacitive elements C 1 , C 2  are explicit or discrete devices in the same way that the transistors P 3  and N 3  are explicit or discrete devices. 
       FIG. 3  shows an illustrative example of a biasing circuit  212  shown in  FIG. 2 , in accordance with some embodiments of the present disclosure. The biasing circuit  214  may be similarly constructed. 
     The V bias  voltage sets the DC bias level of the biasing circuit  212 . Node  302  connects to the gate of P 3 , as shown in  FIG. 2 . When the voltage at the gate of P 3  deviates (up or down) from V bias  by an amount Δ, transistor MN src  or MP snk  will turn ON to compensate. In some embodiments, the Δ may be the transistors&#39; V th  (threshold voltage). In some embodiments, additional compensation (R src , MP src  and R snk , MN snk ) can be provided. 
     In operation, suppose the voltage at node  302  rises above V bias +Δ, this event will turn ON MP snk  as compensation to drive down the voltage at node  302 . When the voltage at node  302  reaches or falls below V bias +Δ, MP snk  will turn OFF. Depending on how much current is being sinked across R snk , MN snk  may turn ON as well to provide further compensation. 
     Conversely, if the voltage at node  302  falls below V bias −Δ, this event will turn ON MN src  as compensation to drive up the voltage at node  302 . When the voltage at node  302  reaches or exceeds below V bias −Δ, MN src  will turn OFF. Depending on how much current is being sourced across R src , MP src  may turn ON as well to provide further compensation. 
     The biasing circuit  212  shown in  FIG. 3  can therefore maintain the DC bias level between V bias +Δ and V bias −Δ in real time; the only delay is due to signal propagation delays between the transistor devices that comprise the biasing circuit  212 . The biasing circuit  212  illustrates an example of a means for responding, substantially without delay, to variations in a voltage level at node  302  to maintain the DC bias voltage between V bias +Δ and V bias −Δ. It will be appreciated of course that the circuit shown in  FIG. 3  is merely illustrative of a biasing circuit in accordance with some embodiments of the present disclosure. Persons of ordinary skill can readily implement other equivalent circuits. 
     A brief discussion of the operation of the cascode stack shown in  FIG. 2  will now be given. The gate driver section  14  ( FIG. 1 ) can cycle the HI-side stack  102  and the LO-side stack  104  between a conductive state and a non-conductive state. For example, when the gate driver section  14  drives HI-side stack  102  to be conductive, the LO-side stack  104  is driven non-conductive, and vice-versa when the gate driver section  14  drives HI-side stack  102  to be non-conductive, the LO-side stack  104  is driven conductive. 
     In a first cycle, for example, suppose the HI-side stack  102  is driven conductive and the LO-side stack  104  is driven non-conductive. On the HI-side stack  102 , the gate driver section  14  can drive the gate of P 1  to 2×V max  to turn ON P 1 . Consequently, the voltage at node  201  will rise to 3×V max . Since the gate of P 2  is DC-biased at 2×V max , P 2  will turn ON. Consequently, the voltage at node  202  will rise to 3×V max . 
     Recall from the discussion above, that the biasing circuit  212  provides a bias voltage V bias  at the gate of P 3  between 2×V max  and V max . Accordingly, P 3  will turn ON, since node  202  is at 3×V max . As the voltage at node  203  rises to 3×V max , so too will the gate voltage of P 3  rise by virtue of the capacitive coupling (e.g., C x1 ), which couples at least a portion of the output voltage at node  203  to the gate of P 3 . For example, the bias capacitor C p  and C x1  (or C 1  in  FIG. 2A ) may define a capacitive voltage divider configured as means for providing a divided potion of the output voltage a node  203  to the gate of P 3 . As a result of the capacitive coupling, the gate voltage at P 3  can track in real time, substantially without delay, the output voltage at node  203  so that V gd  of P 3  does not exceed V max . Since the biasing circuit  212  is configured to maintain the gate voltage of P 3  between 2×V max  and V max , the gate voltage of P 3  will be limited (clamped) to a maximum voltage of 2×V max  as node  203  continues to rise to 3×V max . 
     Turning to operation of the LO-side stack  104 , in the first cycle the gate driver section  14  may drive the LO-side stack  104  to a non-conductive state. The gate driver section  14  may drive the gate of N 1  to ground potential, thus turning OFF N 1 . Since the gate of N 2  is DC-biased at V max , node  205  will rise to V max , thus ensuring that N 2  is OFF. 
     At N 3 , as the voltage at node  203  rises to 3×V max , so too will the gate voltage of N 3  rise by virtue of the capacitive coupling (e.g., C x2 ), which couples at least a portion of the output voltage at node  203  to the gate of N 3 . For example, the bias capacitor C n  and the C x2  (or C 2  in  FIG. 2A ) may define a capacitive voltage divider that provides a divided potion of the output voltage a node  203  to the gate of N 3 . As a result, the gate voltage at N 3  can track in real time substantially without delay the output voltage at node  203  so that V gd  of N 3  does not exceed V max . Since the biasing circuit  214  is configured to maintain the gate of N 3  between 2×V max  and V max , the gate voltage of N 3  will be limited (clamped) to 2×V max  as node  203  continues to rise to 3×V max . The voltage at node  204  will rise to the gate voltage of N 3 , namely 2×V max , thus ensuring that N 3  is OFF. By limiting the maximum gate voltage of N 3  to 2×V max , the V gd  of N 3  will not exceed the V max  rating of N 3  when the voltage at node  203  reaches 3×V max . 
     Consider next a second cycle, that follows the first cycle, in which the HI-side stack  102  can be driven non-conductive and the LO-side stack  104  can be driven conductive. On the LO-side stack  104 , the gate driver section  14  may drive the gate of N 1  to V max , thus turning ON N 1  and bringing node  205  to ground potential. Since the gate of N 2  is DC-biased at V max , N 2  will also turn ON and bring node  204  to ground potential. Recall from the first cycle, the gate voltage of N 3  is at 2×V max . Accordingly, N 3  turns ON and node  203  will go from 3×V max  to ground potential. As the node  203  goes to ground potential, so too will the gate voltage of N 3  as the gate voltage of N 3  tracks in real time substantially without delay the output signal at node  203  by virtue of the capacitive coupling (e.g., C x2 ). The biasing circuit  214 , however, will limit the minimum voltage level at the gate of N 3  to V max . 
     Turning to the HI-side stack  102 , in the second cycle the gate driver section  14  can drive the HI-side stack  102  to a non-conductive state. The gate driver section  14  can drive the gate of P 1  to 3×V max , which will turn OFF P 1 . With P 1  in the OFF state, the voltage at node  201  will equalize with the gate voltage of P 2 , namely 2×V max , thus turning OFF P 2 . Likewise, with P 2  in the OFF state, the voltage at node  202  will equalize with the gate voltage at P 3 . Recall from the first cycle, the gate voltage of P 3  is at 2×V max , and so the node  202  will become 2×V max , and P 3  will turn OFF. 
     As the node  203  goes from 3×V max  to ground potential, so too will the gate voltage of P 3  as the gate voltage of P 3  tracks in real time substantially without delay the output signal at node  203  by virtue of the capacitive coupling (e.g., C x1 ). The biasing circuit  212 , however, will limit the minimum voltage level at the gate of P 3  to V max . By limiting the minimum gate voltage of P 3  to V max , the V gd  of P 3  will not exceed the V max  rating of P 3  when the voltage at node  203  drops to ground potential. 
     The above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims.

Technology Category: 5