Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an information processing system, or more particularly, to an information processing system in which memory devices and copies of tags are accessed in response to access requests issued from a plurality of processing units. 
     2. Description of the Related Art 
     In recent years, an art for enabling an information processing system to operate at a high speed using as small a number of logic devices, and as little wiring, as possible has been demanded in conformity with the trend toward a higher density of components and a higher operating speed. 
     A control sequence for controlling access to memories or memory access in a known information processing system will be described. 
     The known information processing system comprises a plurality of processing units, memory devices, tag RAMs, and a system controller. Each processing unit has a cache memory and a tag RAM. In the tag RAMs, copies of tags of all the processing units are stored. 
     When each processing unit accesses a memory, first, the processing unit attempts to index and update the contents of its own tag. If desired data is stored in its own cache memory, the processing unit accesses the cache memory. If the desired data is not stored in its own cache memory, the processing unit issues a memory access request to the system controller. The system controller indexes and updates the copies of tags stored in the tag RAM. If it is found as a result of indexing that the desired data is not stored in any other processing unit, access to memory, or a memory access, is needed. The memory device is therefore activated. 
     In the known information processing system, as the number of processing units increases, the competition among the processing units for a memory access control unit becomes fierce. Consequently, the efficiency of memory access deteriorates. 
     SUMMARY OF THE INVENTION 
     The present invention attempts to solve the above problem. An object of the present invention is to provide an information processing system including a plurality of processing units each having a cache memory while improving the efficiency of access to memories, or memory access, using a simple circuit. 
     The present invention attempts to accomplish the above object. According to the present invention, there is provided an information processing system in which: processing units having memories and a system controller are interconnected over a bus; the system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to memory devices; and thus controls access to memories, or memory access, gained by the processing units. A plurality of memory interfaces are included for making it possible to access the memory devices on an interleaved basis. A term “way” is used for distinguish each of the memory devices on an interleaved basis. Furthermore, the same numbers of copies of tags and memory access control units as the number of the memory interfaces are included for making it possible to access the tags on an interleaved basis. 
     Since it becomes possible to access memories or tags on an interleaved basis, even if the number of processing units increases, competition for the memory access control units subsides. Consequently, the performance of memory access can be improved. 
     Moreover, according to the present invention, the memory access control units may each include a means for varying the number of ways permitting interleaving of the second memories. This makes it possible to set the number of memory devices to be mounted in one information processing system to any value. 
     When the number of ways leading to memories is varied, the number of ways permitting interleaving of tags may be varied or fixed. When the number of ways leading to tags is fixed, even if the memory access control units decrease the number of ways permitting interleaving of the second memories, the memory access control units do not decrease the number of circuits to be operated among all the circuits for enabling access to the tags or tag access. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above object and features of the present invention will be more apparent from the following description of the preferred embodiment with reference to the accompanying drawings, wherein: 
     FIG. 1 shows the basic configuration of a known information processing system; 
     FIG. 2 shows the first example of the configuration of a system controller in the information processing system shown in FIG. 1; 
     FIG. 3 shows the second example of the configuration of the system controller in the information processing system shown in FIG. 1; 
     FIG. 4 shows the configuration of a system in accordance with the first embodiment of the present invention; 
     FIG. 5 shows the relationship between tags of processing units and tag RAMs shown in FIG. 4; 
     FIG. 6 shows the configuration of a memory access control unit shown in FIG. 1; 
     FIGS. 7A,  7 B,  7 C and  7 D show the configurations of masking circuits shown in FIG. 6; 
     FIG. 8 is a flowchart describing the operations of the system shown in FIG. 4; 
     FIG. 9 shows the configuration of a system in accordance with the second embodiment of the present invention; 
     FIG. 10 shows the configuration of a memory access control unit shown in FIG. 9; 
     FIGS. 11A,  11 B,  11 C and  11 D show the configurations of masking circuits shown in FIG. 10; 
     FIG. 12 shows way configuration information shown in FIG. 11; 
     FIGS. 13A,  13 B and  13 C show examples of arrangements of tag RAMs dependent on the number of ways in the second embodiment of the present invention; 
     FIGS. 14A,  14 B and  14 C show examples of arrangements of tag RAMs dependent on the number of ways in the third embodiment of the present invention; 
     FIG. 15 shows the configuration of a system controller in the third embodiment of the present invention; 
     FIG. 16 shows the configurations of memory access control units shown in FIG. 15 (part  1 ); 
     FIG. 17 shows the configurations of memory access control units shown in FIG. 15 (part  2 ); 
     FIGS. 18A and 18B show the configurations of destination determination circuits shown in FIG. 16; 
     FIGS. 19A,  19 B and  19 C show the configurations of merging circuits for merging activation requests shown in FIG. 15; 
     FIGS. 20A and 20B show the configurations of merging circuits for merging results of indexing shown in FIG. 15; 
     FIGS. 21A and 21B are flowcharts describing the operations of the system shown in FIG. 15; 
     FIGS. 22A,  22 B and  22 C show the conditions for activation of memory access control units in the third embodiment of the present invention; 
     FIG. 23 shows the configuration of a system controller in the fourth embodiment of the present invention; 
     FIG. 24 shows the configurations of memory access control units shown in FIG. 23 (art  1 ); 
     FIG. 25 shows the configurations of memory access control units shown in FIG. 23 (part  2 ); 
     FIGS. 26A,  26 B,  26 C and  26 D show the configurations of memory access request masking circuits shown in FIGS. 24 and 25; 
     FIGS. 27A,  27 B,  27 C and  27 D show the configurations of tag interface activation request. masking circuits shown in FIGS. 24 and 25; 
     FIGS. 28A,  28 B,  28 C and  28 D show the configurations of memory interface activation request masking circuits shown in FIGS. 24 and 25; 
     FIGS. 29A,  29 B and  29 C show the conditions for activation of memory access control units in the fourth embodiment of the present invention; 
     FIG. 30 is a flowchart describing the operations of the system shown in FIG. 23 (part  1 ); 
     FIG. 31 is a flowchart describing the operations of the system shown in FIG. 23 (part  2 ); 
     FIG. 32 shows a practical example of the contents of memory devices in accordance with the present invention; 
     FIGS. 33A,  33 B and  33 C show the relationships between memory devices and memory addresses in accordance with the present invention; 
     FIG. 34 shows the relationships between cache memories and tags in accordance with the present invention; and 
     FIGS. 35A,  35 B and  35 C show practical examples of the contents of tag RAMs in accordance with the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before describing the embodiments of the present invention, the related art and the disadvantage therein will be described with reference to the related figures. 
     FIG. 1 is a diagram showing the basic configuration of an information processing system including a plurality of processing units each having a cache memory. 
     In FIG. 1, there are shown a plurality of processing units  2   a  to  2   m , and a system controller  1 . The processing units  2   a  to  2   m  and the system controller I are interconnected over a bus  5 . The system controller  1  is connected to a memory device  50  and tag RAM  30 . The processing units  2   a  to  2   m  include cache memories  24   a  to  24   m  and tags  25   a  to  25   m  respectively. The tag RAM  30  stores copies of the tags  25   a  to  25   m  of the processing units  2   a  to  2   m.    
     When the processing units  2   a  to  2   m  access memories, first, the processing units index and update their own tags  25   a  to  25   m . If desired data is stored in the own memories  24   a  to  24   m , the processing units access the own memories. By contrast, if the desired data is not stored in the own memories  24   a  to  24   m , the processing units each issue a memory access request to the system controller  1 . The system controller  1  indexes and updates the copies of tags stored in the tag RAM  30 . If it is found as a result of indexing that the desired data is not stored in the other processing units  2   a  to  2   m , access to memories or memory access is needed. The system controller  1  then activates the memory device  50 . 
     FIGS. 2 and 3 show the configuration of the system controller  1  in the information processing system. In FIG. 2, the number of memory devices is  1 , that is, the number of ways leading to memories is  1 . In FIG. 3, memory devices are interleaved (the number of interleaved memory devices=n+ 1 ) in an effort to speed up memory access. 
     In FIGS. 2 and 3, there are shown the system controller  1 , the plurality of processing units  2   a  to  2   m  each having a cache memory, memory access requests  3   a  to  3   m  issued from the processing units  2   a  to  2   m , a memory access control unit l 0 , a tag interface  2   0 , a tag RAM  3   0 , memory interfaces  4   0  to  4   n , and memory devices  5   0  to  5   n . 
     The system controller  1  and processing units  2   a  to  2   m  are interconnected over the bus  5 . The memory access control unit  1   0  and tag interface  2   0  are linked by a tag interface activation request line  6   0  and tag RAM result-of-indexing line  9   0 . The tag interface  2   0  and tag RAM  3   0  are linked by a tag RAM control line  7   0  and tag RAM data line  8   0 . 
     One memory interface  4   0  or the plurality of memory interfaces  4   0  to  4   n  are linked to the memory access control unit  1   0  by a memory interface activation request line  10   0  or memory interface activation request lines  10   0  to  10   n . One memory device  5   0  or the plurality of memory devices  5   0  to  5   n  are linked to the memory interface  4   0  or the memory interfaces  4   0  to  4   n  by a memory control line  11   0  or memory control lines  11   0  to  11   n . 
     The information processing systems shown in FIGS. 2 and 3 control memory access according to a procedure described below. Memory access requests issued from the processing units  2   a  to  2   m  are reported to the system controller  1  over the bus  5 , and transferred as the memory access requests  3   a  to  3   m  to the memory access control unit  1   0  within the system controller  1 . The memory access control unit  1   0  arbitrates the memory access requests  3   a  to  3   m  and handles them one by one. 
     First, the memory access control unit  1   0  activates the tag interface  2   0  over the tag interface activation request line  6   0 . The activated tag interface  2   0  indexes and updates the contents of the tag RAM  3   0  over the tag RAM control line  7   0  and tag RAM data line  8   0 . The result of indexing is reported to the memory access control unit  1   0  over the tag RAM result-ofindexing line  9   0 . 
     If it is judged from the result of indexing sent over the tag RAM result-of-indexing line  9   0  that memory access is needed, the memory access control unit to activates the memory interfaces  4   0  to  4   n , over the memory interface activation request lines  10   0  to  10   n . The memory interfaces  4   0  to  4   n  activate the memory devices  5   0  to  5   n  over the memory control lines  11   0  to  11   n . 
     Embodiments of the present invention will be described in conjunction with the drawings. In the subsequent description, the same reference numerals will be assigned to components having the same functions. Duplicate descriptions will be omitted. 
     (First Embodiment) 
     FIG. 4 is a diagram of a system configuration in accordance with the first embodiment of the present invention. 
     In FIG. 4, there are shown a system controller  1 , a plurality of processing units  2   a  to  2   m  each having a cache memory, and memory access requests  3   a  to  3   m  issued from the processing units  2   a  to  2   m.    
     In the subsequent description, WAY 0  to WAY n  denote ways permitting interleaving of memories. In the system shown in FIG. 4, the number of ways is n+ 1 . Along the ways WAY 0  to WAY n , memory access control units  1 , tag interfaces  2   0  to  2   n , tag RAMs  3   0  to  3   n , memory interfaces  4   0  to  4   n , and memory devices  5   0  to  5   n  are installed. 
     FIG. 5 shows the relationships between the tags of the processing units  2   a  to  2   m  and the tag RAMs  3   0  to  3   n . The tags  25   a  to  25   m  of the processing units  2   a  to  2   m  are each divided into the same number of portions A to N as the number of ways, n. The copies of the portions are interleaved in the tag RAMs  3   0  to  3   n . 
     Referring back to FIG. 4, the system controller  1  and processing units  2   a  to  2   m  are interconnected over a bus  5 . The memory access control units  1   0  to  1   n  and tag interfaces  2   0  to  2   n  are linked by tag interface activation request lines  6   0  to  6   n  and tag RAM result-of-indexing lines  9   0  to  9   n . The tag interfaces  2   0  to  2   n  and tag RAMs  3   0  to  3   n  are linked by tag RAM control lines  7   0  to  7   n  and tag RAM data lines  8   0  to  8   n . 
     Moreover, the memory interfaces  4   0  to  4   n  are linked to the memory access control units  1   0  to  1   n  by memory interface activation request lines  10   0  to  10   n . The memory devices  5   0  to  5   n  are linked to the memory interfaces  4   0  to  4   n . The memory access requests  3   a  to  3   m , and signals sent over the tag interface activation request lines  6   0  to  6   n  and memory interface activation request lines  10   0  to  10   n  each contain added information such as an address and access type. 
     The information processing system shown in FIG. 4 controls memory access according to the procedure described below. 
     When the processing units  2   a  to  2   m  access memories, first, they index and update the contents of their own tags  25   a  to  25   m.  If desired data is stored in their own cache memories, the processing units access the cache memories. By contrast, if the desired data is not stored in the memories  24   a  to  24   m,  the processing units each issue a memory access request to the system controller  1 . 
     The memory access requests issued from the processing units  2   a  to  2   m  are reported to the system controller  1  over the bus  5 , and transferred as the memory access requests  3   a  to  3   m  to the memory access control units  1   0  to  1   n  within the system controller  1 . The memory access requests  3   a  to  3   m  are input to the associated memory access control units  1   0  to  1   n  by masking circuits included in the memory access control units l 0  to  1   n . The masking circuits will be described later. 
     When the memory access requests  3   a  to  3   m  compete for a memory access control unit, each of the memory access control units l 0  to  1   n  arbitrates and processes the memory access requests one by one. The arbitration technique is already known. A description of the arbitration technique will therefore be omitted. 
     The memory access control units  1   0  to  1   n  activate the tag interfaces  2   0  to  2   n  in response to requests sent over the tag interface activation request lines  6   0  to  6   n . The activated tag interfaces  2   0  to  2   n  index and update the contents of the tag RAMs  3   0  to  3   n  over the tag RAM control lines  7   0  to  7   n  and tag RAM data lines  8   0  to  8   n . The results of indexing are reported to the memory access control units  1   0  to  1   n  over the tag RAM result-of-indexing lines  9   0  to  9   n . 
     If it is judged from the results of indexing sent over the tag RAM result-of-indexing lines  9   0  to  9   n  that desired data is not stored, memory access is needed. In this case, the memory access control units  1   0  to  1   n  activate the memory interfaces  4   0  to  4   n  in response to the results of indexing sent over the memory interface activation request lines  10   0  to  10   n . The memory interfaces  4   0  to  4   n  activate the memory devices  5   0  to  5   n  over the memory control lines  11   0  to  11   n . 
     As described above, the memory access control units  1   0  to  1   n , tag interfaces  2   0  to  2   n , and tag RAMs  3   0  to  3   n  are included in one-to-one correspondence with the ways leading to the memories. The memory access requests  3   a  to  3   m  routed along different ways will be processed without competing with one another. This is enabled by the incorporation of the masking circuits  12   na  to  12   m  in the memory access control units  1   0  to  1   n . 
     The masking circuits will be described in conjunction with FIGS. 6 and 7. The masking circuits are associated with the memory access requests  3   a  to  3   m  and are included in each of the memory access control units  1   0  to  1   n . The masking circuits incorporated in the memory access control unit to are masking circuits  12   0a  to  12   0m . 
     The masking circuits incorporated in the memory access control unit l n  are masking circuits  12   na  to  12   nm . All the masking circuits are therefore masking circuits  12   na  to  12   nm . 
     FIG. 6 shows the configuration of one memory access control unit  1 . The memory access requests  3   a  to  3   m  issued from the processing units  2   a  to  2   m  are input to the masking circuits  12   0a  to  12   nm . Requests that are not masked by the masking circuits are input as memory access requests  14   0a  to  14   nm  to memory access control circuits  13   0  to  13   n . 
     FIGS. 7A,  7 B,  7 C and  7 D show the practical configurations of masking circuits. Herein, assume that the number of ways leading to the memories is four and the address of a memory determining a way is specified as a &lt; 7 : 6 &gt;. Shown are the last masking circuits  12   0m  to  14   4m  in the memory access control units  1   0  to  1   4 . The last memory access request  3   m  is therefore input to the masking circuits  12   0m  to  14   4M . 
     FIG. 7A shows the configuration of the masking circuit  12   0M  on the way WAY 0 . FIG. 7B shows the configuration of the masking circuit  12   1m  on the way WAY 1 . FIG. 7C shows the configuration of the masking circuit  12   2m  on the way way 2 . FIG. 7D shows the configuration of the masking circuit  12   3m  on the way WAY 3 . The masking circuits  12   0m  to  12   4m  gate the memory access request relative to the memory address at &lt; 7 : 6 &gt;. 
     Herein, assume that an access request for a memory having an address a &lt; 7 : 6 &gt;= 10  is issued from the processing unit  2   m  on the way WAY m  shown in FIG.  4 . The access request is reported as a memory access request  3   m  to all the memory access control units  1   0  to  1   3 . The access requests  3   m  in the memory access control units  1   0 ,  1   1  and  1   3  are masked by the masking circuit  12   0 ,  12   1 , and  12   3 . As a result, a memory access request  14   2m  is output only from the masking circuit  12   2 . Consequently, the memory access control unit  1   2  alone is activated. 
     The foregoing operations will be described in conjunction with FIG.  8 . 
     The memory access control units  1   0  to l n  judge whether or not the masking circuits  12   0a  to  12   nm  should mask access requests (step SI). Requests intended to be placed on ways other than accessible ways are masked (step S 2 ). 
     If a plurality of access requests are present, each of the memory access control circuits  13   0  to  13   n  arbitrates the requests. As for requests not masked at step S 2 , it is judged whether arbitration among the requests by the memory access control circuits  13   0  to  13   n  has succeeded (step S 3 ). When arbitration among the requests has succeeded, an activation request for an associated tag interface is produced (step S 4 ). 
     The tag interfaces  2   0  to  2   n  index and update the contents of the tags (step S 5 ), and transmit the results of indexing (step S 6 ). 
     The memory access control circuits  13   0  to  13   n  wait for the completion of the indexing of the contents of the tags (step S 7 ). When the indexing is completed, it is judged whether or not memory access is needed (step S 8 ). If memory access is needed, an activation request for an associated memory interface is produced and transmitted (step S 9 ). The memory interfaces  4   0  to  4   n  activate the memory devices  5   0  to  5   n  (step S 10 ). If it is judged at step S 8  that memory access is not needed, another sequencer is activated (step S 11 ). 
     (Second Embodiment) 
     In the aforesaid first embodiment, the number of ways leading to the memories within one system controller is fixed. A set number of memories alone can be connected to one unit. By contrast, the second embodiment makes it possible to provide a model in which the same system controller has a decreased number of ways leading to the memories. 
     FIG. 9 shows a system configuration in accordance with the second embodiment of the present invention, FIG. 10 shows the configuration of a memory access control unit, and FIGS. 11 a  to  11   d  show the configurations of masking circuits. 
     FIGS. 9,  10  and  11  show the same circuitries as those shown in the drawings relevant to the aforesaid first embodiment. Specifically, FIG. 9 corresponds to FIG. 4, FIG. 10 corresponds to FIG. 6, and FIGS. 11A,  11 B,  11 C and  11 D correspond to FIGS. 7A,  7 B,  7 C and  7 D. In the subsequent description, a constituent feature specific to the second embodiment will be described mainly. A duplicate description will be briefed. 
     The system configuration shown in FIG. 9 is different from the one of the first embodiment shown in FIG. 4 in a point that way configuration information  4  is input to the memory access control units  1   0  to  1   n  in addition to the memory access requests  3   a  to  3   m.  The other components are identical to those shown in FIG. 4. A duplicate description will be omitted. The way configuration information  4  specifies the number of ways leading to the memories. The output source of the way configuration information may be an output value of a register or a value obtained by calculating external pin contacts. 
     The memory access control units  1   0  to  1   n  shown in FIG. 10 are different from those shown in FIG. 6 according to the first embodiment in a point that the way configuration information  4  is input to the masking circuits  12   0a  to  12   nm  in addition to the memory access requests  3   a  to  3   m.  The other components are identical to those shown in FIG. 4. A duplicate description will be omitted. 
     FIGS. 11A,  11 B,  11 C and  1 D show practical examples of masking circuits. Assume that the number of ways leading to the memories is four and the address of a memory determining a way is specified as a &lt; 7 : 6 &gt;. A certain memory access request  3   m  is input to the last masking circuits  12   0m  to  12   4m  in the memory access control units  1   0  to  1   4 . 
     FIG. 11 a  shows the configuration of the masking circuit  12   0m  on the way WAY 0 , FIG. 11B shows the configuration of the masking circuit  12   2m  on the way WAY 2 , FIG. 11C shows the configuration of the masking circuit  12   2m  on the way WAY 2 , and FIG. 11D shows the configuration of the masking circuit  12   3   m . on the way WAY 3 . 
     The masking circuits  12   0m  to  12   4m  each has a gate. A condition for masking under which each gate operates is the AND of the address a&lt; 7 : 6 &gt; and way configuration information  4 . This enables a decrease in number of ways for reducing the size of the system. An example of the way configuration information is shown in FIG.  12 . 
     In FIG. 11A, for gating the memory access request  3   m,  way configuration information  00  and a memory address a&lt; 7 : 6 &gt;=xx (wherein x denotes any numeral) are ANDed, way configuration information  01  and a memory address a=x 0  are ANDed, and way configuration information  10  and a memory address a= 00  are ANDed. The OR of the ANDS and the memory access request  3   m  are then ANDed. A signal passed by the AND gate is output as a memory access request  14   0m  to the memory access control unit  1   0 . 
     In FIG. 11B, for gating the memory access request  3   m,  way configuration information  01  and a memory address a=x 0  are ANDed and way configuration information  10  and a memory address a= 01  are ANDed. The OR of the ANDS and the memory access request  3   m  are then ANDed. A signal passed by the gate is output as a memory access request 14 1m  to the memory access control unit  1   1 . 
     In FIG. 11C, for gating the memory access request  3   m,  way configuration information  10  and a memory address a= 10  are ANDed, and the AND and memory access request  3   m  are then ANDed. A signal passed by the gate is output as a memory access request  14   2m  to the memory access control unit  1   2 . In FIG. 11D, for gating the memory access request  3   m,  way configuration information  10  and a memory address a= 11  are ANDed, and the AND and memory access request  3   m  are then ANDed. A signal passed by the gate is output as a memory access request  14   3m  to the memory access control unit  1   3 . 
     When  1  is designated as the number of ways ( 00  is specified for way &lt; 1 : 0 &gt;), the condition for masking set in only the masking circuit  12   0m  on the way WAY 0  is met. When  2  is designated as the number of ways ( 01  is specified for way&lt; 1 : 0 &gt;), the conditions for masking set in the masking circuit  12   0m  on the way WAY 0  shown in FIG.  11 A and the masking circuit  12   1m  on the way WAY 1  shown in FIG. 11B are met. When  4  is designated as the number of ways ( 10  is specified for way&lt; 1 : 0 &gt;), the conditions for masking set in all the circuits shown in FIGS. 11A,  11 B,  11 C and  11 D are met. 
     When a configuration including one way is designated, the first memory access control unit  1   0  alone is enabled to operate with the memory access request  14   0m . When a configuration including two ways is designated, the first and second memory access control units  1   0  and  1   1  are enabled to operate. When a configuration including four ways is designated, all the memory access control units  1   1  to  1   n  are enabled to operate, and the same operations as those in the first embodiment are carried out. 
     If the number of ways leading to the memories is halved or quartered for reducing the size of the system, the number of ways leading to the tag RAMs is also halved or quartered. However, since the number of the cache memories in the processing units  2   a  to  2   m  is not decreased, rearrangement of the tag RAMs becomes necessary. 
     FIGS. 13A,  13 B and  13 C show rearranged states of the tag RAMs. FIG. 13A shows a rearranged state for a configuration including one way. In this configuration, one tag RAM  30  is mounted along the way WAY 0 . The contents of all the tag RAMs  3   0  to  3   3  shown in FIG. 9 are stored in the tag RAM  3   0 . FIG. 13B shows a rearranged state for a configuration including two ways. In this configuration, the tag RAM  3   0  and tag RAM  3   1  are mounted along the ways WAY 0  and WAY 1 . The contents of the tag RAMs  3   0  and  3   2  shown in FIG. 9 are stored in the tag RAM  3   0 , and the contents of the tag RAMs  3   1  and  3   3  are stored in the tag RAM  3   1 . FIG. 13C shows a rearranged state for a configuration including four ways. The tag RAMs  3   0  to  3   3  are mounted along the ways WAY 0  to WAY 3 , whereby the same configuration as that in the first embodiment is realized. 
     The operations in the foregoing second embodiment are nearly the same as those in the first embodiment except that the numbers of memory access control units, tag RAMs, and memory devices to be operated actually are different. A duplicate description of the operations will be omitted. 
     (Third Embodiment) 
     In the second embodiment, the number of ways leading to the tag RAMs is also decreased with a decrease in number of ways leading to the memories. Tag RAMs must therefore be, as shown in FIGS. 13A,  13 B and  13 C, rearranged according to a decrease in number of memories. In contrast, in the third embodiment, even when the number of ways leading to the memories is decreased, tag RAMs need not be rearranged. This will be described in conjunction with FIGS. 14A,  14 B,  14 C and  14 D. That is to say, when the number of ways leading to the memory devices  5   0  to  5   n  is changed to one as shown in FIG. 14A, two as shown in FIG. 14B, or four as shown in FIG. 14C, the tag RAMs  3   0  to  3   n  need not be rearranged. 
     In the description of the third embodiment, the number of ways shall be four. However, the maximum number of ways is not limited to four but may be the n-th power of  2 . Moreover, a decrease in number of tag RAMs to the n-th power of  2  should be supported, but it is unnecessary to support a decrease in number of tag RAMs to every value. 
     FIG. 15 shows the configuration of a system controller. In the system controller shown in FIG. 15, as in the one shown in FIG. 9 according to the second embodiment, the way configuration information  4  as well as the memory access requests  3   a  to  3   m  are input to the memory access control units  1   0  to  1   3 . Moreover, the tag interface activation requests  6   0  to  6   3  sent from the memory access control units  1   0  to  1   3  are output in the same manner as those shown in FIG. 9 according to the second embodiment. However, in FIG. 15, merging circuits  15   1  to  15   3  for merging activation requests and merging circuits  16   0  to  16   1  for merging results of indexing are inserted between the memory access control units  1   0  to  1   3  and tag interfaces  2   0  to  2   3 . 
     FIGS. 16 and 17 show the configurations of the memory access control units  1   0  to  1   3 . The way configuration information  4  as well as the memory access requests  3   a  to  3   m  are input to the masking circuits  12   0a  to  12   3m  in the memory access control units  1   0  to  1   3 . The configuration shown in FIG. 11 according to the second embodiment is adopted as the configuration of the masking circuits  12   0a  to  12   3   m . The memory access control units  1   0  to  1   3  selected depending on the number of ways specified in the way configuration information  4  are enabled to operate. 
     For activating a fixed number of tag RAMs  3   0  to  3   3 , by means a decreased number of memory access control units  1   0  to  1   3 , destination determination circuits  19   0  and  19   1  are included. 
     In the memory access control unit to enabled to operate to whichever value of  1  to  4  the number of ways is set, the destination determination circuit  19   0  is included for determining requests to be sent over the activation request lines  6   0  to  6   3  routed to all the four tag interfaces. In the memory access control unit  11  enabled to operate when the number of ways is  2  or  4 , the destination determination circuit  19   1  is included for determining requests to be sent over the two tag interface activation request lines  6   1  and  6   3 . In the memory access control units  12  and  1   3  enabled to operate only when the number of ways is  4 , no destination determination circuit is included. A request is output over the associated tag interface activation request line  62  or  6   3 . 
     FIGS. 18A and 18B show the configurations of the destination determination circuits. FIG. 18A shows the destination determination circuit  19   0  in the memory access control unit  10  enabled to operate when the number of ways is any of  1  to  4 . A way passing through a tag interface to be activated by the destination determination circuit  19   0  is determined with a memory address a&lt; 7 : 6 &gt;. For example, when  10  is specified for a memory address a&lt; 7 : 6 &gt;, a request to be sent over the tag interface activation request line  6   2  is made active. 
     FIG. 18B shows in detail the destination determination circuit  19   1  in the memory access control unit  1   1  enabled to operate when the number of ways is  2  or  4 . The destination determination circuit  19   1  gates an input relative to an address a&lt; 7 : 6 &gt;, whereby a tag interface to be activated is determined. For example, when an access request is issued for an address a&lt; 7 : 6 &gt;= 11 , the tag interface activation request  6   3  is made active. 
     The merging circuits  15   1  to  15   3  in FIG. 15 will be described. To the tag interface  2   0  on the way WAY 0 , a request is supplied from the memory access control unit  1   0  alone over the activation request line  6   0  without being passed through a merging circuit. To the tag interface  2   1  on the way WAY 0 , requests output from the two memory access control units l 0  and  1   1  over the activation request line  6   1  and merged by the merging circuit  15   1  are supplied as a merged activation request  17   1 . 
     To the tag interface  2   2  on the way WAY 2 , requests output from the two memory access control units  1   0  and  1   2  over the activation request line  6   2  and merged by the merging circuit  15   2  are supplied as a merged activation request  17   2 . To the tag interface  2   3  on the way WAY 3 , requests output from the three memory access control units  1   0 ,  1   1 , and  1   3  over the activation request line  6   3  and merged by the merging circuit  15   3  are supplied as a merged activation request  17   3 . The way configuration information  4  is input to the merging circuits  15   1  to  15   3 . 
     FIGS. 19A,  19 B and  19 C show the configurations of the merging circuits  15   1  to  15   3 . FIG. 19A shows the configuration of the merging circuit  151  on the way WAY 1 . A request output from the memory access control circuit  1   0  over the activation request line  6   1  is gated relative to the way configuration information  4  (way&lt; 1 : 0 &gt;= 00 ), and then output as an activation request  17   1  from the OR gate. A request output from the memory access control circuit  1   1  on the way WAY 1  over the activation request line  6   1  is output as the activation request  17   1  directly from the OR gate. 
     FIG. 19B shows the configuration of the merging circuit  15   2  on the way WAY 2 . A request output from the memory access control circuit  1   0  over the activation request line  6   2  is gated relative to the way configuration information  4  (way&lt; 1 : 0 &gt;= 0 x) and then output as an activation request  17   2  from the OR gate. A request output from the memory access control circuit  1   2  on the way WAY 2  is output as the activation request  17   2  directly from the OR gate. 
     FIG. 19C shows the configuration of the merging circuit  15   3  on the way WAY 3 . A request output from the memory access control circuit to over the activation request line  6   3  is gated relative to the way configuration information  4  (way &lt; 1 : 0 &gt;= 00 ) and then output as an activation request  17   3  from the OR gate. A request output from the memory access control line  1   1  on the way WAY 1  over the activation request line  6   3  is gated relative to the way configuration information  4  (way&lt; 1 : 0 &gt;= 01 ) and then output as an activation request  17   3  from the OR gate. The activation request  6   3  output from the memory access control circuit  1   3  on the way WAY 3  is output as an activation request  17   2  directly from the OR gate. 
     The merging circuits  16   0  and  16   1  for merging results of indexing shown in FIG. 15 will be described. Results of indexing  9   0  to  9   3  sent from all the tag interfaces  2   0  to  2   3  and the way configuration information  4  are input to the merging circuit  16   0  on the way WAY 0 . A merged result of indexing  18   0  is then output. Results of indexing sent from the tag interfaces  2   1  and  2   3  on the ways WAY 1  and WAY 3  over the resultof-indexing lines  9   1  and  9   3  and the way configuration information  4  are input to the merging circuit  16   1  on the way WAY 1 . A merged result of indexing  18   1  is then output. As for the ways WAY 1  and WAY 3 , a result of indexing sent from the tag interface  2   2  or  2   3  over the result-of-indexing line  9   2  or  9   3  is input directly to the memory access control unit  1   2  or  1   3 . 
     FIGS. 20A and 20B show the configurations of the merging circuits  16   0  and  16   1  for merging results of indexing. FIG. 20A shows the configuration of the merging circuit  16   0  on the way WAY 0 . A result of indexing output from the tag interface  2   0  over the result-ofindexing line  9   0  is output as a result of indexing  18   0  directly from the OR gate. A result of indexing output from the tag interface  2   1  over the result-of-indexing line  9   1  is gated relative to the way configuration information  4  (way &lt; 1 : 0 &gt;= 00 ) and then output as the result of indexing  18   0  from the OR gate. A result of indexing output from the tag interface  2   2  over the result-of-indexing line  9   2  is gated relative to the way configuration information  4  (way&lt; 1 : 0 &gt;= 0 x) and then output as the result of indexing  18   0  from the OR gate. A result of indexing output from the tag interface  2   3  over the result-of-indexing line  9   3  is gated relative to the way configuration information  4  (way&lt; 1 : 0 &gt;= 00 ) and then output as the result of indexing  18   0  from the OR gate. 
     FIG. 20B shows the configuration of the merging circuit  16   1  on the way WAY 1 . A result of indexing output from the tag interface  2   1  over the result-of-indexing line  9   1  is output as a result of indexing  18   1  directly from the OR gate. A result of indexing output from the tag interface  2   3  over the result-of-indexing line  9   3  is gated relative to the way configuration information  4  (way&lt; 1 : 0 &gt;= 0 x) and then output as the result of indexing  18   1  from the OR gate. 
     Referring to FIGS. 21A and 21B, the operations in the third embodiment of the present invention will be described. The flowchart of FIG. 21 is nearly identical to that of FIG. 8 concerning the first embodiment. Only a difference from the flowchart of FIG. 8 will be described. 
     When activation requests for tag interfaces are issued at step S 4 , destinations are determined by the destination determination circuits  19 n at step S 21 . Tag interface activation requests are then output. The requests are transmitted to the tag interfaces  2 n directly or via the merging circuits. Results of indexing output from the tag interfaces  2 n are transmitted to the memory access control units in directly or via the merging circuits. 
     As a result, in the third embodiment, the conditions for activation of the memory access control units are as listed in FIGS. 22A,  22 B and  22 C. FIG. 22A lists the conditions for activation to be met when a configuration including one way is designated. FIG. 22B lists the conditions for activation to be met when a configuration including two ways is designated. FIG. 22C lists the conditions for activation to be met when a configuration including four ways is designated. In each drawing, ◯ indicates that the memory access control unit is activated, and × indicates that the memory access control unit is not activated. 
     FIGS. 22A,  22 B and  22 C should be referenced as mentioned below. Referring to FIG. 22A, when a configuration including one way is designated, whichever of  00  to  11  is specified for a memory address a&lt; 7 : 6 &gt;, only the memory access control unit  1   0  on the way WAY 0  is activated. The memory access control unit to activates all the tag RAMs  3   0  to  3   3  and the memory  4   0  to which the way WAY 0  leads. 
     Referring to FIG. 22B, when a configuration including two ways is designated, if a= 00  or  10  is specified, the memory access control unit  1   0  on the way WAY 0  is activated. The memory access control unit to activates the tag RAMs  3   0  and  3   2  on the ways WAY 0  and WAY 2  and the memory  4   0  to which the way WAY 0  leads. If a=O 1  or  11  is specified, the memory access control unit  1   1  on the way WAY 1  is activated. The memory access control unit  1   1  activates the tag RAMs  3   1  and  3   3  on the ways WAY 1  and WAY 3  and the memory  4   1  to which the way WAY 1  leads. 
     Referring to FIG. 22C, when a configuration including four ways is designated, if a= 00  is specified, the memory access control unit to on the way WAY 0  is activated and in turn activates the tag RAM  3   0  and memory  4   0 . If a= 01  is specified, the memory access control unit  11  on the way WAY 1  is activated and in turn activates the tag RAM  3   1  and memory  4   1 . If a= 10  is specified, the memory access control unit  1   2  on the way WAY 2  is activated and in turn activates the tag RAM  3   2  and memory  4   2 . If a=I 1  is specified, the memory access control unit  1   3  on the way WAY 2  is activated and in turn activates the tag RAM  3   3  and memory  4   3 . 
     (Fourth Embodiment) 
     An example in which the number of connection signal lines linking the memory access control units  1   0  to  1   n  and the tag interfaces  2   0  to  2   n , which are included in the system of the third embodiment in which the number of ways leading to the memories can be changed, can be decreased drastically will be described as the fourth embodiment. Even in the fourth embodiment, the description will proceed on the assumption that the number of ways is four. 
     FIG. 23 shows the configuration of a system controller. The system controller will be described briefly. Like the system controller shown in FIG. 15 according to the third embodiment, the way configuration information  4  is input together with the memory access requests  3   a  to  3   m  to the memory access control units  1   0  to  1   3 . Requests sent from the memory access control units  1   0  to  1   3  over the tag interface activation request lines  6   0  to  6   3  are output directly to the tag interfaces  2   0  to  2   3 . 
     Results of indexing output from the tag interfaces  2   0  to  2   3  over the result-of-indexing lines  9   0  to  9   n  are, like those shown in FIG. 15 according to the third embodiment, input to the memory interfaces  4   0  to  4   3  via the merging circuits  16   0  and  16   1  or directly. Requests issued from the memory access control units  1   0  to  1   3  are also output to the memory interfaces  4   0  to  4   n  over the memory interface activation request lines  10   0  to  10   n . 
     FIGS. 24 and 25 show the configurations of the memory access control units  10  to  1   3 . The memory access control unit  1   0  on the way WAY 0  includes the memory access request masking circuits  12   0a  to  12   nm  tag interface activation request masking circuit  21   0 , and memory interface activation request masking circuit  22   0 . The memory access requests  3   a  to  3   m  issued from the processing units  2   a  to  2   m  and the way configuration information  4  are input to the memory access request masking circuits  12   0  to  12   n . The other memory access control units  11  to  13  on the ways WAY 1  to WAY 3  have the same configuration. 
     FIGS. 26A,  26 B, 26 C and  26 D show the configurations of the last memory access request masking circuits  12   0m  to  12   3m  in the memory access control units  10  to  13 . The last memory access request  3   m  is therefore input to the masking circuits  12   0m  to  12   3   m . 
     FIG. 26A shows the masking circuit  12   0m  on the way WAY 0 . For gating the memory access request  3   m,  way configuration information  00  and a memory address a&lt; 7 : 6 &gt;=xx (where x denotes any numeral) are ANDed, way configuration information  01  and a memory address a=x 0  are ANDed, and way configuration information  10  and a memory address a= 00  are ANDed. The OR of the ANDS and the memory access request  3   m  are then ANDed. A signal passed by the gate is output as a memory access request  14   0m  to the memory access control unit  10   1 . 
     FIGS. 26B,  26 C and  26 D show the masking circuits  12   1m  to  12   3m  on the ways WAY 1  to WAY 3  which have nearly the same configuration as that shown in FIG.  26 A. 
     FIGS. 27A,  27 B,  27 C and  27 D show the configurations of the tag interface activation request masking circuits. Specifically, FIGS. 27A,  27 B,  27 C and  27 D show the masking circuits  21   0  to  21   3  on the ways WAY 0  to WAY 3 . The tag interface activation requests  20   0  to  20   3  issued from the memory access control units  1   0  to  1   3  are gated relative to memory addresses a&lt; 7 : 6 &gt;= 00  to  11 , and output as requests over the tag interface activation request lines  6   0  to  6   3 . 
     The configuration of the merging circuits  16   0  and  16   1  shown in FIG. 23 is identical to that shown in FIG. 2 according to the third embodiment. Results of indexing output from the tag interfaces  2   0  to  2   3  over the result-of-indexing lines  9   0  to  9   3  are input as results of indexing  18   1  and  18   2  to the memory interfaces  4   0  to  4   3  via the merging circuits  16   0  and  16   1  or input as requests directly to the memory interfaces  4   0  to  4   3 . Aside from the results of indexing, requests are input from the memory access control unit  1   0  to  1   3  to the memory interfaces  4   0  to  4   3  over the memory interface activation request lines  10   0  to  10   3 . 
     FIGS. 28A,  28 B,  28 C and  28 D show the configurations of the memory interface activation request masking circuits in the memory access control units  1   0  to  1   3 . 
     To the masking circuit  22   0  on the way WAY 0  in FIG. 28A, the memory interface activation request  23   0  issued from the memory access control circuit  13   0  is input. For gating the activation request  23   0 , way configuration information  00  and a memory address a&lt; 7 : 6 &gt;=xx are ANDed, way configuration information  01  and a memory address a=x 0  are ANDed, and way configuration information  10  and a memory address a= 00  are ANDed. The OR of the ANDS and the activation request are then ANDed. A signal passed by the gate is output as a request to the memory interface  4   0  over the memory interface activation request line  10   0 . 
     To the masking circuit  22   1  on the way WAY 1  in FIG. 28B, the memory interface activation request  23   1  issued from the memory access control circuit  13   1  is input. For gating the activation request  23   1  , way configuration information  01  and a memory address a=x 1  are ANDed, and way configuration information  10  and a memory address a= 01  are ANDed. The OR of the ANDs and the activation request are then ANDed. A signal passed by the AND gate is output as a request to the memory interface  4   1  over the memory interface activation request line  10   1 . 
     To the masking circuit  22   2  on the way WAY 2  in FIG. 28C, the memory interface activation request  23   2  issued from the memory access control circuit  13   2  is input. Way configuration information  10  and a memory address a= 10  are ANDed. The AND and activation request are then ANDed. A signal passed by the gate is output as a request to the memory interface  4   2 over the memory interface activation request line  10   2 . 
     To the masking circuit  22   3  on the way WAY 3  in FIG. 28D, the memory interface activation request  23   3  issued from the memory access control circuit  13   3  is input. Way configuration information  10  and a memory address a= 11  are ANDed. The AND and activation request are then ANDed. A signal passed by the gate is output as a request to the memory interface  2   3  over the memory interface activation request line  10   3 . 
     As a result, according to the fourth embodiment, the conditions for activation of the memory access control units are those listed in FIGS. 29A,  29 B and  29 C. FIG. 29A lists the conditions for activation to be met when a configuration including one way is designated. FIG. 29B lists the conditions for activation to be met when a configuration including two ways is designated. FIG. 29C lists the conditions for activation to be met when a configuration including four ways is designated. In each drawing, ◯ indicates that the memory access control unit is activated and × indicates that the memory access control unit is not activated. 
     FIGS. 29A,  29 B and  29 C should be referenced as described below. Referring to FIG. 29A, when the configuration including one way is designated, all the memory access control units  1   0  to  1   3  are activated. The memory interface  4   0  on the way WAY 0  is activated by the memory access control unit  1   0  on the way WAY 0 . When a= 00  is specified, the tag interface  2   0  on the way WAY 0  is activated by the memory access control unit  1   0  on the way WAY 0 . When a= 01  is specified, the tag interface  2   1  on the way WAY 0  is activated by the memory access control unit  1   1  on the way WAY 0 . When a= 10  is specified, the tag interface  2   2  on the way WAY 2  is activated by the memory access control unit  1   2  on the way WAY 2 . When a= 11  is specified, the tag interface  2   3  on the way WAY 3  is activated by the memory access control unit  1   3  on the way WAY 3 . 
     Referring to FIG. 29B, when the configuration including two ways is designated, if a= 00  or  10  is specified, the memory access control units  1   0  and  1   2  on the ways WAY 0  and WAY 2  are activated. If a= 01  or  11  is specified, the memory access control units  1   1  and  1   3  on the ways WAY 1  and WAY 3  are activated. 
     If a= 00  is specified, the memory access control unit  1   0  on the way WAY 0  activates the tag interface  2   0  and memory interface  4   0  on the way WAY 0 . If a= 01  is specified, the memory access control unit  1   1  on the way WAY 0  activates the tag interface  2   1  and memory interface  4   1  on the way WAY 1 . If a= 10  is specified, the memory access control unit  1   0  on the way WAY 0  activates the memory interface  4   0  on the way WAY 0 , and the memory access control unit  1   2  on the way WAY 2  activates the tag interface  2   2  on the way WAY 2 . If a= 11  is specified, the memory access control unit  1   1  on the way WAY 1  activates the memory interface  4   1  on the way WAY 1 , and the memory access control unit  1   3  on the way WAY 3  activates the tag interface  3   3  on the way WAY 3 . 
     Referring to FIG. 29C, when the configuration including four ways is designated, if a= 00  is specified, the memory access control unit  1   0  on the way WAY 0  is activated and in turn activates the tag interface  2   0  and memory interface  4   0 . If a= 01  is specified, the memory access control unit  1   1  on the way WAY 0  is activated and in turn activates the tag interface  2   0  and memory interface  4   1 . If a= 10  is specified, the memory access control unit  1   1  on the way WAY 1  is activated and in turn activates the tag interface  2   2  and memory interface  4   2 . If a= 11  is specified, the memory access control unit  1   3  on the way WAY 3  is activated and in turn activates the tag interface  2   3  and memory interface  4   3 . 
     Referring to FIGS. 30 and 31, the operations in the foregoing fourth embodiment will be described. 
     Steps S 1  to S 4  are identical to those described in FIG. 8 according to the first embodiment or those described in FIG. 21 according to the third embodiment. When the tag interface activation requests are issued from the memory access control circuits  13   0  to  13   n  (step S 4 ), the tag interface masking circuits  21   0  to  21   n  judge whether or not the requests should be masked (step S 31 ). Requests that should be masked are masked (step S 32 ), and requests that should not be masked are output as tag interface activation requests  20   0  to  20   n  (step S 33 ). 
     The memory interface masking circuits  23   0  to  23   n  to which the memory interface activation requests are input (step S 34 ) judge whether or not the requests should be masked (step S 35 ). Requests that should be masked are masked (step S 36 ) and requests that should not be masked are output as the memory interface activation requests  10   0  to  10   n  (step S 37 ). 
     The tag interfaces  2   0  to  2   n  index and update the contents of the tags (step S 38 ), and output the results of tag indexing  9   0  to  9   n  (step S 39 ). 
     The results of tag indexing  9   0  to  9   n  and the requests sent over the memory interface activation request lines  10   0  to  10   n  are input to the memory interfaces  4   0  to  4   n . It is awaited that the tag indexing is completed (step S 7 ). When the tag indexing is completed, it is judged whether or not memory access is needed (step S 8 ). If memory access is needed, the memory interfaces  2   0  to  2   n  are activated (step S 10 ). If it is judged that memory access is not needed, another sequencer is activated (step S  1  ). Practical examples of memory devices, cache memories, tags, and tag RAMs 
     Practical examples of the contents of memory devices, cache memories, tags, and tag RAMs employed in the aforesaid embodiments will be described. Assume that the number of ways is four. 
     FIG. 32 shows practical examples of the contents of the memory devices  5   0  to  5   n  and reveals the relationships between memory addresses and the contents thereof to be established in the configurations including one way, two ways, and four ways respectively. First, it is seen that as long as the storage capacities of the memory devices  5   0  to  5   3  are the same, when the number of ways gets larger, the amount of data stored increases. Secondly, it is seen that in the configuration including one way, all the data is stored in the memory device  4   0  on the way WAY 0 , that in the configuration including two ways, all the data is interleaved in the memory devices  5   0  and  5   1  on the ways WAY 0  and WAY 1 , and that in the configuration including four ways, all the data is interleaved in the memory devices  5   0  to  5   3  on the ways WAY 0  to WAY 3 . 
     FIGS. 33A,  33 B and  33 C show the relationships between memory devices and memory addresses to be established in the configurations including different numbers of ways. In the drawings, x denotes any numeral. Referring to FIG. 33A, in the configuration including four ways, a way is specified with a memory address a &lt; 7 : 6 &gt;. Referring to FIG. 33B, in the configuration including two ways, a way is specified with a memory address a&lt; 6 &gt;. Referring to FIG. 33C, in the configuration including one way, the way WAY 0  is specified irrespective of a memory address. 
     FIGS. 34,  35 A,  35 B and  35 C show the relationships between cache memories in the processing units  2   a  to  2   m,  tags, and tag RAMs. FIG. 34 shows the relationships of correspondence between the cache memories in the processing units  2   a  to  2   m  and tags. FIGS. 35A,  35 B and  35 C show arrangements of data items stored in the tag RAMs according to the third embodiment. FIG. 35A shows the arrangements adopted for the configuration including four ways. FIG. 35B shows the arrangements adopted for the configuration including two ways. FIG. 35C shows the arrangements adopted for the configuration including one way. The contents of the tags shown in FIG. 34 ( 0   a  to  63   a,    0   b  to  63   b,  etc., and  0   n  to  63   n ) are, as shown in FIG. 35, stored in the tag RAMs or tag RAM in different manners depending on the number of ways. 
     As described so far, according to the present invention, the performance of memory access to be carried out in a configuration including ways can be improved. This contributes greatly to an increase in operating speed of an information processing system. Moreover, common use of a module or a decrease in number of signal lines linking modules can be achieved with the addition of a simple circuit. This contributes greatly to a reduction in period of logical or physical design and an increase in density of the components to be integrated.

Technology Category: g