Patent Document

FIELD OF INVENTION 
       [0001]    The present invention relates to display technologies, more specifically a method and system for driving light emitting device displays. 
       BACKGROUND OF THE INVENTION 
       [0002]    Recently active-matrix organic light-emitting diode (AMOLED) displays with amorphous silicon (a-Si), poly-silicon, organic, or other driving backplane have become more attractive due to advantages over active matrix liquid crystal displays. An AMOLED display using a-Si backplanes, for example, has the advantages that include low temperature fabrication that broadens the use of different substrates and makes flexible displays feasible, and its low cost fabrication. Also, OLED yields high resolution displays with a wide viewing angle. 
         [0003]    The AMOLED display includes an array of rows and columns of pixels, each having an organic light-emitting diode (OLED) and backplane electronics arranged in the array of rows and columns. Since the OLED is a current driven device, the pixel circuit of the AMOLED should be capable of providing an accurate and constant drive current. 
         [0004]      FIG. 1  illustrates conventional operation cycles for a conventional voltage-programmed AMOLED display. In  FIG. 1 , “Rowi” (i=1, 2, 3) represents a ith row of the matrix pixel array of the AMOLED display. In  FIG. 1 , “C” represents a compensation voltage generation cycle in which a compensation voltage is developed across the gate-source terminal of a drive transistor of the pixel circuit, “VT-GEN” represents a V T -generation cycle in which the threshold voltage of the drive transistor, V T , is generated, “P” represents a current-regulation cycle where the pixel current is regulated by applying a programming voltage to the gate of the drive transistor, and “D” represents a driving cycle in which the OLED of the pixel circuit is driven by current controlled by the drive transistor. 
         [0005]    For each row of the AMOLED display, the operating cycles include the compensation voltage generation cycle “C”, the V T -generation cycle “VT-GEN”, the current-regulation cycle “P”, and the driving cycle “D”. Typically, these operating cycles are performed sequentially for a matrix structure, as shown in  FIG. 1 . For example, the entire programming cycles (i.e., “C”, “VT-GEN”, and “P”) of the first row (i.e., Row 1 ) are executed, and then the second row (i.e., Row 2 ) is programmed. 
         [0006]    However, since the V T -generation cycle “VT-GEN” requires a large timing budget to generate an accurate threshold voltage of a drive TFT, this timing schedule cannot be adopted in large-area displays. Moreover, executing two extra operating cycles (i.e., “C” and “VT-GEN”) results in higher power consumption and also requires extra controlling signals leading to higher implementation cost. 
       SUMMARY OF THE INVENTION 
       [0007]    It is an object of the invention to provide a method and system that obviates or mitigates at least one of the disadvantages of existing systems. 
         [0008]    In accordance with an aspect of the present invention there is provided a display system which includes: a pixel array including a plurality of pixel circuits arranged in row and column. The pixel circuit has a light emitting device, a capacitor, a switch transistor and a drive transistor for driving the light emitting device. The pixel circuit includes a path for programming, and a second path for generating the threshold of the drive transistor. The system includes: a first driver for providing data for the programming to the pixel array; and a second driver for controlling the generation of the threshold of the drive transistor for one or more drive transistors. The first driver and the second driver drives the pixel array to implement the programming and generation operations independently. 
         [0009]    In accordance with a further aspect of the present invention there is provided a method of driving a display system. The display system includes: a pixel array including a plurality of pixel circuits arranged in row and column. The pixel circuit has a light emitting device, a capacitor, a switch transistor and a drive transistor for driving the light emitting device. The pixel circuit includes a path for programming, and a second path for generating the threshold of the drive transistor. The method includes the steps of: controlling the generation of the threshold of the drive transistor for one or more drive transistors, providing data for the programming to the pixel array, independently from the step of controlling. 
         [0010]    In accordance with a further aspect of the present invention there is provided a display system which includes: a pixel array including a plurality of pixel circuits arranged in row and column, The pixel circuit has a light emitting device, a capacitor, a switch transistor and a drive transistor for driving the light emitting device. The system includes: a first driver for providing data to the pixel array for programming; and a second driver for generating and storing an aging factor of each pixel circuit in a row into the corresponding pixel circuit, and programming and driving the pixel circuit in the row for a plurality of frames based on the stored aging factor. The pixel array is divided into a plurality of segments. At least one of signal lines driven by the second driver for generating the aging factor is shared in a segment. 
         [0011]    In accordance with a further aspect of the present invention there is provided a method of driving a display system. The display system includes: a pixel array including a plurality of pixel circuits arranged in row and column. The pixel circuit has a light emitting device, a capacitor, a switch transistor and a drive transistor for driving the light emitting device. The pixel array is divided into a plurality of segments. The method includes the steps of: generating an aging factor of each pixel circuit using a segment signal and storing the aging factor into the corresponding pixel circuit for each row, the segment signal being shared by each segment; and programming and driving the pixel circuit in the row for a plurality of frames based on the stored aging factor. 
         [0012]    This summary of the invention does not necessarily describe all features of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    These and other features of the invention will become more apparent from the following description in which reference is made to the appended drawings wherein: 
           [0014]      FIG. 1  illustrates conventional operating cycles for a conventional AMOLED display; 
           [0015]      FIG. 2  illustrates an example of a segmented timing schedule for stable operation of a light emitting light display, in accordance with an embodiment of the present invention; 
           [0016]      FIG. 3  illustrates an example of a parallel timing schedule for stable operation of a light emitting light display, in accordance with an embodiment of the present invention; 
           [0017]      FIG. 4  illustrates an example of an AMOLED display array structure for the timing schedules of  FIGS. 2 and 3 ; 
           [0018]      FIG. 5  illustrates an example of a voltage programmed pixel circuit to which the segmented timing schedule and the parallel timing schedule are applicable; 
           [0019]      FIG. 6  illustrates an example of a timing schedule applied to the pixel circuit of  FIG. 5 ; 
           [0020]      FIG. 7  illustrates another example of a voltage programmed pixel circuit to which the segmented timing schedule and the parallel timing schedule are applicable; 
           [0021]      FIG. 8  illustrates an example of a timing schedule applied to the pixel circuit of  FIG. 7 ; 
           [0022]      FIG. 9  illustrates an example of a shared signaling addressing scheme for a light emitting display, in accordance with an embodiment of the present invention; 
           [0023]      FIG. 10  illustrates an example of a pixel circuit to which the shared signaling addressing scheme is applicable; 
           [0024]      FIG. 11  illustrates an example of a timing schedule applied to the pixel circuit of  FIG. 10 ; 
           [0025]      FIG. 12  illustrates the pixel current stability of the pixel circuit of  FIG. 10 ; 
           [0026]      FIG. 13  illustrates another example of a pixel circuit to which the shared signaling addressing scheme is applicable; 
           [0027]      FIG. 14  illustrates an example of a timing schedule applied to the pixel circuit of  FIG. 13 ; 
           [0028]      FIG. 15  illustrates an example of an AMOLED display array structure for the pixel circuit of  FIG. 10 ; 
           [0029]      FIG. 16  illustrates an example of an AMOLED display array structure for the pixel circuit of  FIG. 13 ; 
           [0030]      FIG. 17  illustrates a further example of a pixel circuit to which the shared signaling addressing scheme is applicable; 
           [0031]      FIG. 18  illustrates an example of a timing schedule applied to the pixel circuit of  FIG. 17 ; 
           [0032]      FIG. 19  illustrates an example of an AMOLED display array structure for the pixel circuit of  FIG. 17 ; 
           [0033]      FIG. 20  illustrates a further example of a pixel circuit to which the shared signaling addressing scheme is applicable; 
           [0034]      FIG. 21  illustrates an example of a timing schedule applied to the pixel circuit of  FIG. 20 ; and 
           [0035]      FIG. 22  illustrates an example of an AMOLED display array structure for the pixel circuit of  FIG. 20 . 
       
    
    
     DETAILED DESCRIPTION 
       [0036]    Embodiments of the present invention are described using a pixel circuit having a light emitting device, such as an organic light emitting diode (OLED), and a plurality of transistors, such as thin film transistors (TFTs), arranged in row and column, which form an AMOLED display. The pixel circuit may include a pixel driver for OLED. However, the pixel may include any light emitting device other than OLED, and the pixel may include any transistors other than TFTs. The transistors in the pixel circuit may be n-type transistors, p-type transistors or combinations thereof. The transistors in the pixel may be fabricated using amorphous silicon, nano/micro crystalline silicon, poly silicon, organic semiconductors technologies (e.g. organic TFT), NMOS/PMOS technology or CMOS technology (e.g. MOSFET). In the description, “pixel circuit” and “pixel” may be used interchangeably. The pixel circuit may be a current-programmed pixel or a voltage-programmed pixel. In the description below, “signal” and “line” may be used interchangeably. 
         [0037]    The embodiments of the present invention involve a technique for generating an accurate threshold voltage of a drive TFT. As a result, it generates a stable current despite the shift of the characteristics of pixel elements due to, for example, the pixel aging, and process variation. It enhances the brightness stability of the OLED. Also it may reduce the power consumption and signals, resulting in low implementation cost. 
         [0038]    A segmented timing schedule and a parallel timing schedule are described in detail. These schedules extend the timing budget of a cycle for generating the threshold voltage V T  of a drive transistor. As described below, the rows in a display array are segmented and the operating cycles are divided into a plurality of categories, e.g., two categories. For example, the first category includes a compensation cycle and a V T -generation cycle, while the second category includes a current-regulation cycle and a driving cycle. The operating cycles for each category are performed sequentially for each segment, while the two categories are executed for two adjacent segments. For example, while the current regulation and driving cycles are performed for the first segment sequentially, the compensation and V T -generation cycles are executed for the second segment. 
         [0039]      FIG. 2  illustrates an example of the segmented timing schedule for stable operation of a light emitting display, in accordance with an embodiment of the present invention. In  FIG. 2 , “Row k ” (k=1, 2, 3, . . . , j, j+1, j+2) represents a kth row of a display array, an arrow shows an execution direction. 
         [0040]    For each row, the timing schedule of  FIG. 2  includes a compensation voltage generation cycle “C”, a V T -generation cycle “VT-GEN”, a current-regulation cycle “D”, and a driving cycle “P”. 
         [0041]    The timing schedule of  FIG. 2  extends the timing budget of the V T -generation cycle “VT-GEN” without affecting the programming time. To achieve this, the rows of the display array to which the segmented addressing scheme of  FIG. 2  is applied are categorized as few segments. Each segment includes rows in which the V T -generation cycle is carried out consequently. In  FIG. 2 , Row 1 , Row 2 , Row 3 , . . . , and, Row j  are in one segment in a plurality of rows of the display array. 
         [0042]    The programming of each segment starts with executing the first and second operating cycles “C” and “VT-GEN”. After that, the current-calibration cycle “P” is preformed for the entire segment. As a result, the timing budget of the V T -generation cycle “VT-GEN” is extended to j. τ P  where j is the number of rows in each segment, and τ P  is the timing budget of the first operating cycle “C” (or current regulation cycle). 
         [0043]    Also, the frame time τ F  is Z×n×τ P  where n is the number of rows in the display, and Z is a function of number of iteration in a segment. For example, in  FIG. 2 , the V T  generation starts from the first row of the segment and goes to the last row (the first iteration) and then the programming starts from the first row and goes to the last row (the second iteration). Accordingly, Z is set to 2. If the number of iteration increases, the frame time will become Z×n×τ P  in which Z is the number of iteration and may be greater than 2. 
         [0044]      FIG. 3  illustrates an example of the parallel timing schedule for stable operation of a light emitting light display, in accordance with an embodiment of the present invention. In  FIG. 3 , “Row k ” (k=1, 2, 3, . . . , j, j+1) represents a kth row of a display array. 
         [0045]    Similar to  FIG. 2 , the timing schedule of  FIG. 4  includes the compensation voltage generation cycle “C”, the V T -generation cycle “VT-GEN”, the current-regulation cycle “P”, and the driving cycle “D”, for each row. 
         [0046]    The timing schedule of  FIG. 3  extends the timing budget of the V T -generation cycle “VT-GEN”, whereas τ P  is preserved as τ F /n, where τ P  is the timing budget of the first operating cycle “C”, τ F  is a frame time, and n is the number of rows in the display array. In  FIG. 3 , Row 1  to Row j  are in a segment in a plurality of rows of the display array. 
         [0047]    According to the above addressing scheme, the current-regulation cycle “P” of each segment is preformed in parallel with the first operating cycles “C” of the next segment. Thus, the display array is designed to support the parallel operation, i.e., having capability of carrying out different cycles independently without affecting each other, e.g., compensation and programming, V T -generation and current regulation. 
         [0048]      FIG. 4  illustrates an example of an example of an AMOLED display array structure for the the timing schedules of  FIGS. 2 and 3 . In  FIG. 4 , SEL[a] (a=1, . . . , m) represents a select signal to select a row, CTRL[b] (b=1, . . . , m) represents a controlling signal to generate the threshold voltage of the drive TFT at each pixel in the row, and VDATA[c] (c=1, . . . , n) represents a data signal to provide a programming data. The AMOLED display  10  of  FIG. 4  includes a plurality of pixel circuits  12  which are arranged in row and column, an address driver  14  for controlling SEL[a] and CTRL[b], and a data driver  16  for controlling VDATA[c]. The rows of the pixel circuits  12  (e.g., Row 1 , . . . , Row m-h  and Row m-h+1 , . . . , Row m ) are segmented as described above. To implement certain cycles in parallel, the AMOLED display  10  is designed to support the parallel operation. 
         [0049]      FIG. 5  illustrates an example of a pixel circuit to the segmented timing schedule and parallel timing schedule are applicable. The pixel circuit  50  of  FIG. 5  includes an OLED  52 , a storage capacitor  54 , a drive TFT  56 , and switch TFTs  58  and  60 . A select line SEL 1  is connected to the gate terminal of the switch TFT  58 . A select line SEL 2  is connected to the gate terminal of the switch TFT  60 . The first terminal of the switch TFT  58  is connected to a data line VDATA, and the second terminal of the switch TFT  58  is connected to the gate of the drive TFT  56  at node A 1 . The first terminal of the switch TFT  60  is connected to node A 1 , and the second terminal of the switch TFT  60  is connected to a ground line. The first terminal of the drive TFT  56  is connected to a controllable voltage supply VDD, and the second terminal of the drive TFT  56  is connected to the anode electrode of the OLED  52  at node B 1 . The first terminal of the storage capacitor  54  is connected to node A 1 , and the second terminal of the storage capacitor  54  is connected to node B 1 . The pixel circuit  50  can be used with the segmented timing schedule, the parallel timing schedule, and a combination thereof. 
         [0050]    V T -generation occurs through the transistors  56  and  60 , while current regulation is performed by the transistor  58  through the VDATA line. Thus, this pixel is capable of implementing the parallel operation. 
         [0051]      FIG. 6  illustrates an example of a timing schedule applied to the pixel circuit  50 . In  FIG. 7 , “X 11 ”, “X 12 ”, “X 13 ”, and “X 14 ” represent operating cycles. X 11  corresponds to “C” of  FIGS. 2 and 3 , X 12  corresponds to “VT-GEN” of  FIGS. 2 and 3 , X 13  corresponds to “P” of  FIGS. 2 and 3 , and X 14  corresponds to “D” of  FIGS. 2 and 3 . 
         [0052]    Referring to  FIGS. 5 and 6 , the storage capacitor  54  is charged to a negative voltage (−Vcomp) during the first operating cycle X 11 , while the gate voltage of the drive TFT  56  is zero. During the second operating cycle X 12 , node B 1  is charged up to −V T  where V T  is the threshold of the drive TFT  56 . This cycle X 12  can be done without affecting the data line VDATA since it is preformed through the switch transistor  60 , not the switch transistor  58 , so that the other operating cycle can be executed for the other rows. During the third operating cycle X 13 , node A 1  is charged to a programming voltage V P , resulting in V GS =V P +V T  where V GS  represents a gate-source voltage of the drive TFT  56 . 
         [0053]      FIG. 7  illustrates another example of a pixel circuit to the segmented timing schedule and the parallel timing schedules are applicable. The pixel circuit  70  of  FIG. 7  includes an OLED  72 , storage capacitors  74  and  76 , a drive TFT  78 , and switch TFTs  80 ,  82  and  84 . A first select line SEL 1  is connected to the gate terminal of the switch TFTs  80  and  82 . A second select line SEL 2  is connected to the gate terminal of the switch TFT  84 . The first terminal of the switch TFT  80  is connected to the cathode of the OLED  72 , and the second terminal of the switch TFT  80  is connected to the gate terminal of the drive TFT  78  at node A 2 . The first terminal of the switch TFT  82  is connected to node B 2 , and the second terminal of the switch TFT  82  is connected to a ground line. The first terminal of the switch TFT  84  is connected to a data line VDATA, and the second terminal of the switch TFT  84  is connected to node B 2 . The first terminal of the storage capacitor  74  is connected to node A 2 , and the second terminal of the storage capacitor  74  is connected to node B 2 . The first terminal of the storage capacitor  76  is connected to node B 2 , and the second terminal of the storage capacitor  76  is connected to a ground line. The first terminal of the drive TFT  78  is connected to the cathode electrode of the OLED  72 , and the second terminal of the drive TFT  78  is coupled to a ground line. The anode electrode of the OLED  72  is coupled to a controllable voltage supply VDD. The pixel circuit  70  has the capability of adopting the segmented timing schedule, the parallel timing schedule, and a combination thereof. 
         [0054]    V T -generation occurs through the transistors  78 ,  80  and  82 , while current regulation is performed by the transistor  84  through the VDATA line. Thus, this pixel is capable of implementing the parallel operation. 
         [0055]      FIG. 8  illustrates an example of a timing schedule applied to the pixel circuit  70 . In  FIG. 8 , “X 21 ”, “X 22 ”, “X 23 ”, and “X 24 ” represent operating cycles. X 21  corresponds to “C” of  FIGS. 2 and 3 , X 22  corresponds to “VT-GEN” of  FIGS. 2 and 3 , X 23  corresponds to “P” of  FIGS. 2 and 3 , and X 24  corresponds to “D” of  FIGS. 2 and 3 . 
         [0056]    Referring to  FIGS. 7 and 8 , the pixel circuit  70  employs bootstrapping effect to add a programming voltage to the stored V T  where V T  is the threshold voltage of the drive TFT  78 . During the first operating cycle x 21 , node A 2  is charged to a compensating voltage, VDD-V OLED  where V OLED  is a voltage of the OLED  72 , and node B 2  is discharged to ground. During the second operating cycle X 22 , voltage at node A 2  is changed to the V T  of the drive TFT  78 . The current regulation occurs in the third operating cycle X 23  during which node B 2  is charged to a programming voltage V P  so that node A 2  changes to V P +V T . 
         [0057]    The segmented timing schedule and the parallel timing schedule described above provide enough time for the pixel circuit to generate an accurate threshold voltage of the drive TFT. As a result, it generates a stable current despite the pixel aging, process variation, or a combination thereof. The operating cycles are shared in a segment such that the programming cycle of a row in the segment is overlapped with the programming cycle of another row in the segment. Thus, they can maintain high display speed, regardless of the size of the display. 
         [0058]    A shared signaling addressing scheme is described in detail. According to the shared signaling addressing scheme, the rows in the display array are divided into few segments. The aging factor (e.g., threshold voltage of the drive TFT, OLED voltage) of the pixel circuit is stored in the pixel. The stored aging factor is used for a plurality of frames. One or more signals required to generate the aging factor are shared in the segment. 
         [0059]    For example, the threshold voltage V T  of the drive TFT is generated for each segment at the same time. After that, the segment is put on the normal operation. All extra signals besides the data line and select line required to generate the threshold voltage (e.g., VSS of  FIG. 10 ) are shared between the rows in each segment. Considering that the leakage current of the TFT is small, using a reasonable storage capacitor to store the V T  results in less frequent compensation cycle. As a result, the power consumption reduces dramatically. 
         [0060]    Since the V T -generation cycle is carried out for each segment, the time assigned to the V T -generation cycle is extended by the number of rows in a segment leading to more precise compensation. Since the leakage current of a-Si: TFTs is small (e.g., the order of 10 −14 ), the generated V T  can be stored in a capacitor and be used for several other frames. As a result, the operating cycles during the next post-compensation frames are reduced to the programming and driving cycles. Consequently, the power consumption associated with the external driver and with charging/discharging the parasitic capacitances is divided between the same few frames. 
         [0061]      FIG. 9  illustrates an example of the shared signaling addressing scheme for a light emitting light display, in accordance with an embodiment of the present invention. The shared signaling addressing scheme reduces the interface and driver complexity. 
         [0062]    A display array to which the shared signaling addressing scheme is applied is divided into few segments, similar to those for  FIGS. 2 and 3 . In  FIG. 9 , “Row [j, k]” (k=1, 2, 3, . . . , h) represents the k th  row in the j th  segment, “h” is the number of row in each segment, and “L” is the number of frames that use the same generated V T . In  FIG. 9 , “Row [j, k]” (k=1, 2, 3, . . . , h) is in a segment, and “Row [j−1, k]” (k=1, 2, 3, . . . , h) is in another segment. 
         [0063]    The timing schedule of  FIG. 9  includes compensation cycles “C &amp; VT-GEN” (e.g.  301  of  FIG. 9 ), a programming cycle “P”, and a driving cycle “D”. A compensation interval  300  includes a generation frame cycle  302  in which the threshold voltage of the drive TFT is generated and stored inside the pixel, compensation cycles “C &amp; VT-GEN” (e.g.  301  of  FIG. 9 ), besides the normal operation of the display, and L−1 post compensation frames cycles  304  which are the normal operation frame. The generation frame cycle  302  includes one programming cycle “P” and one driving cycle “D”. The L−1 post compensation frames cycle  304  includes a set of the programming cycle “P” and the driving cycle “D”, in series. 
         [0064]    As shown in  FIG. 9 , the driving cycle of each row starts with a delay of τ P  from the previous row where τ P  is the timing budget assigned to the programming cycle “P”. The timing of the driving cycle “D” at the last frame is reduced for each rows by i*τ P  where “i” is the number of rows before that row in the segment (e.g., (h−1) for Row [j, h]). 
         [0065]    Since τ P  (e.g., the order of 10 μs) is much smaller than the frame time (e.g., the order of 16 ms), the latency effect is negligible. However, to minimize this effect, the programming direction may be changed each time, so that the average brightness lost due to latency becomes equal for all the rows or takes into consideration this effect in the programming voltage of the frames before and after the compensation cycles. For example, the sequence of programming the row may be changed after each V T -generation cycle (i.e., programming top-to-bottom and bottom-to-top iteratively), 
         [0066]      FIG. 10  illustrates an example of a pixel circuit to which the shared signaling addressing scheme is applicable. The pixel circuit  90  of  FIG. 10  includes an OLED  92 , storage capacitors  94  and  96 , a drive TFT  98 , and switch TFTs  100 ,  102  and  104 . The pixel circuit  90  is similar to the pixel circuit  70  of  FIG. 7 . The drive TFT  98 , the switch TFT  100 , and the first storage capacitor  94  are connected at node A 3 . The switch TFTs  102  and  104 , and the first and second storage capacitors  94  and  96  are connected at node B 3 . The OLED  92 , the drive TFT  98  and the switch TFT  100  are connected at node C 3 . The switch TFT  102 , the second storage capacitor  96 , and the drive TFT  98  are connected to a controllable voltage supply VSS. 
         [0067]      FIG. 11  illustrates an example of a timing schedule applied to the pixel circuit  90 . In  FIG. 11 , “X 31 ”, “X 32 ”, “X 33 ”, “X 34 ”, and “X 35 ” represent operating cycles. X 31 , X 32  and X 33  correspond to the compensation cycles (e.g.  301  of  FIG. 9 ), X 34  corresponds to “P” of  FIG. 9 , and X 35  correspond to “D” of  FIG. 9 . 
         [0068]    Referring to  FIGS. 10 and 11 , the pixel circuit  90  employs a bootstrapping effect to add the programming voltage to the generated V T  where V T  is the threshold voltage of the drive TFT  98 . The compensation cycles (e.g.  301  of  FIG. 9 ) include the first three cycles X 31 , X 32 , and X 33 . During the first operating cycle X 31 , node A 3  is charged to a compensation voltage, VDD-V OLED . The timing of the first operating cycle X 31  is small to control the effect of unwanted emission. During the second operating cycle X 32 , VSS goes to a high positive voltage V 1  (for example, V 1 =20 V), and thus node A 3  is bootstrapped to a high voltage, and also node C 3  goes to V 1 , resulting in turning off the OLED  92 . During the third operating cycle X 33 , the voltage at node A 3  is discharged through the switch TFT  100  and the drive TFT  98  and settles to V 2 +V T  where V T  is the threshold voltage of the drive TFT  98 , and V 2  is, for example, 16 V. VSS goes to zero before the current-regulation cycle, and node A 3  goes to V T . A programming voltage V PG  is added to the generated V T  by bootstrapping during the fourth operating cycle X 34 . The current regulation occurs in the fourth operating cycle X 34  during which node B 3  is charged to the programming voltage V PG  (for example, V PG =6V). Thus the voltage at node A 3  changes to V PG +V T  resulting in an overdrive voltage independent of V T . The current of the pixel circuit during the fifth cycle X 35  (driving cycle) becomes independent of V T  shift. Here, the first storage capacitor  94  is used to store the V T  during the V T -generation interval. 
         [0069]      FIG. 12  illustrates the pixel current stability of the pixel circuit  90  of  FIG. 10 . In  FIG. 12 , “ΔV T ” represents the shift in the threshold voltage of the drive TFT (e.g.,  98  of  FIG. 10 ), and “Error in 1 pixel (%)” represents the change in the pixel current causing by ΔV T  As shown in  FIG. 12 , the pixel circuit  90  of  FIG. 10  provides a highly stable current even after a 2-V shift in the V T  of the drive TFT. 
         [0070]      FIG. 13  illustrates another example of a pixel circuit to which the shared signaling addressing scheme is applicable. The pixel circuit  110  of  FIG. 13  is similar to the pixel circuit  90  of  FIG. 10 , and, however, includes two switch TFTs. The pixel circuit  110  includes an OLED  112 , storage capacitors  114  and  116 , a drive TFT  118 , and switch TFTs  120  and  122 . The drive TFT  118 , the switch TFT  120 , and the first storage capacitor  114  are connected at node A 4 . The switch TFTs  122  and the first and second storage capacitors  114  and  116  are connected at node B 4 . The cathode of the OLED  112 , the drive TFT  118  and the switch TFT  120  are connected to node C 4 . The second storage capacitor  116  and the drive TFT  118  are connected to a controllable voltage supply VSS. 
         [0071]      FIG. 14  illustrates an example of a timing schedule applied to the pixel circuit  110 . In  FIG. 15 , “X 41 ”, “X 42 ”, “X 43 ”, “X 44 ”, and “X 44 ” represent operating cycles. X 41 , X 42 , and X 43  correspond to compensation cycles (e.g.  301  of  FIG. 9 ), X 44  correspond to “P” of  FIG. 9 , and X 45  correspond to “D” of  FIG. 9 . 
         [0072]    Referring to  FIGS. 13 and 14 , the pixel circuit  110  employs a bootstrapping effect to add the programming voltage to the generated V T . The compensation cycles (e.g.  301  of  FIG. 9 ) include the first three cycles X 41 , X 42 , and X 43 . During the first operating cycle X 41 , node A 4  is charged to a compensation voltage, VDD-V OLED . The timing of the first operating cycle X 41  is small to control the effect of unwanted emission. During the second operating cycle X 42 , VSS goes to a high positive voltage V 1  (for example, V 1 =20 V), and so node A 4  is bootstrapped to a high voltage, and also node C 4  goes to V 1 , resulting in turning off the OLED  112 . During the third operating cycle X 43 , the voltage at node A 4  is discharged through the switch TFT  120  and the drive TFT  118  and settles to V 2 +V T  where V T  is the threshold voltage of the drive TFT  118  and V 2  is, for example, 16 V. VSS goes to zero before the current-regulation cycle, and thus node A 4  goes to V T . A programming voltage V PG  is added to the generated V T  by bootstrapping during the fourth operating cycle X 44 . The current regulation occurs in the fourth operating cycle X 44  during which node B 4  is charged to the programming voltage V PG  (for example, V PG =6 V). Thus the voltage at node A 4  changes to V PG +V T  resulting in an overdrive voltage independent of V T . The current of the pixel circuit during the fifth cycle X 45  (driving cycle) becomes independent of V T  shift. Here, the first storage capacitor  114  is used to store the V T  during the V T -generation interval. 
         [0073]      FIG. 15  illustrates an example of an AMOLED display structure for the pixel circuit of  FIG. 10 . In  FIG. 15 , GSEL[a] (a=1, . . . , k) corresponds to SEL 2  of  FIG. 10 , SEL 1 [ b ] (b=1, . . . , m) corresponds to SEL 1  of  FIG. 10 , GVSS[c] (c=1, . . . , k) corresponds to VSS of  FIG. 10 , VDATA[d] (d=1, . . . , n) corresponds to VDATA of  FIG. 10 . The AMOLED display  200  of  FIG. 15  includes a plurality of pixel circuits  90  which are arranged in row and column, an address driver  204  for controlling GSEL[a], SEL 1 [ b ] and GVSS[c], and a data driver  206  for controlling VDATA[s]. The rows of the pixel circuits  90  are segmented as described above. In  FIG. 15 , segment [ 1 ] and segment [k] are shown as examples. 
         [0074]    Referring to  FIGS. 10 and 15 , SEL 2  and VSS signals of the rows in one segment are connected together and form GSEL and GVSS signals. 
         [0075]      FIG. 16  illustrates an example of an AMOLED display structure for the pixel circuit of  FIG. 14 . In  FIG. 17 , GSEL[a] (a=1, . . . , k) corresponds to SEL 2  of  FIG. 14 , SEL 1 [ b ] (b=1, . . . , m) corresponds to SEL 1  of  FIG. 14 , GVSS[c] (c=1, . . . , k) corresponds to VSS of  FIG. 14 , VDATA[d] (d=1, . . . , n) corresponds to VDATA of  FIG. 14 . The AMOLED display  210  of  FIG. 16  includes a plurality of pixel circuits  110  which are arranged in row and column, an address driver  214  for controlling GSEL[a], SEL 1 [ b ] and GVSS[c], and a data driver  216  for controlling VDATA[s]. The rows of the pixel circuits  110  are segmented as described above. In  FIG. 15 , segment [ 1 ] and segment [k] are shown as examples. 
         [0076]    Referring to  FIGS. 14 and 16 , SEL 2  and VSS signals of the rows in one segment are connected together and form GSEL and GVSS signals. 
         [0077]    Referring to  FIGS. 15 and 16 , the display arrays can diminish its area by sharing VSS and GSEL signals between physically adjacent rows. Moreover, GVSS and GSEL in the same segment are merged together and form the segment GVSS and GSEL lines. Thus, the controlling signals are reduced. Further, the number of blocks driving the signals is also reduced resulting in lower power consumption and lower implementation cost. 
         [0078]      FIG. 17  illustrates a further example of a pixel circuit to which the shared signaling addressing scheme is applicable. The pixel circuit of  FIG. 17  includes an OLED  132 , storage capacitors  134  and  136 , a drive TFT  138 , and switch TFTs  140 ,  142  and  144 . A first select line SEL is connected to the gate terminal of the switch TFT  142 . A second select line GSEL is connected to the gate terminal of the switch TFT  144 . A GCOMP signal line is connected to the gate terminal of the switch TFT  140 . The first terminal of the switch TFT  140  is connected to node A 5 , and the second terminal of the switch TFT  140  is connected to node C 5 . The first terminal of the drive TFT  138  is connected to node C 5  and the second terminal of the drive TFT  138  is connected to the anode of the OLED  132 . The first terminal of the switch TFT  142  is connected to a data line VDATA, and the second terminal of the switch TFT  142  is connected to node B 5 . The first terminal of the switch TFT  144  is connected to a voltage supply VDD, and the second terminal of the switch TFT  144  is connected to node C 5 . The first terminal of the first storage capacitor  134  is connected to node A 5 , and the second terminal of the first storage capacitor  134  is connected to node B 5 . The first terminal of the second storage capacitor  136  is connected to node B 5 , and the second terminal of the second storage capacitor  136  is connected to VDD. 
         [0079]      FIG. 18  illustrates an example of a timing schedule applied to the pixel circuit  130 . In  FIG. 18 , operating cycles X 51 , X 52 , X 53 , and X 54  form a generating frame cycle (e.g.,  302  of  FIG. 9 ), the second operating cycles X 53  and X 54  form a post-compensation frame cycle (e.g.,  304  of  FIGS. 9 ). X 53  and X 54  are the normal operation cycles whereas the rest are the compensation cycles. 
         [0080]    Referring to  FIGS. 17 and 18 , the pixel circuit  130  employs bootstrapping effect to add a programming voltage to the generated V T  where V T  is the threshold voltage of the drive TFT  138 . The compensation cycles (e.g.  301  of  FIG. 9 ) include the first two cycles X 51  and X 52 . During the first operating cycle X 51 , node A 5  is charged to a compensation voltage, and node B 5  is charged to V REF  through the switch TFT  142  and VDATA. The timing of the first operating cycle X 51  is small to control the effect of unwanted emission. During the second operating cycle X 52 , GSEL goes to zero and thus it turns off the switch TFT  144 . The voltage at node A 5  is discharged through the switch TFT  140  and the drive TFT  138  and settles to V OLED +V T  where V OLED  is the voltage of the OLED  132 , and V T  is the threshold voltage of the drive TFT  138 . During the programming cycle, i.e., the third operating cycle X 53 , node B 5  is charged to V P +V REF  where V P  is a programming voltage. Thus the gate voltage of the drive TFT  138  becomes V OLED +V T +V P . Here, the first storage capacitor  134  is used to store the V T +V OLED  during the compensation interval. 
         [0081]      FIG. 19  illustrates an example of an AMOLED display array structure for the pixel circuit  130  of  FIG. 17 . In  FIG. 19 , GSEL[a] (a=1, . . . , k) corresponds to GSEL of  FIG. 17 , SEL[b] (b=1, . . . , m) corresponds to SEL 1  of  FIG. 17 , GCMP[c] (c=1, . . . , k) corresponds to GCOMP of  FIG. 17 , VDATA[d] (d=1, . . . , n) corresponds to VDATA of  FIG. 17 . The AMOLED display  220  of  FIG. 19  includes a plurality of pixel circuits  130  which are arranged in row and column, an address driver  224  for controlling SEL[a], GSEL[b], and GCOMP[c], and a data driver  226  for controlling VDATA[c]. The rows of the pixel circuits  130  are segmented (e.g., segment [ 1 ] and segment [k]) as described above. 
         [0082]    As shown in  FIGS. 17 and 19 , GSEL and GCOMP signals of the rows in one segment are connected together and form GSEL and GCOMP lines. GSEL and GCOMP signals are shared in the segment. Moreover, GVSS and GSEL in the same segment are merged together and form the segment GVSS and GSEL lines. Thus, the controlling signals are reduced. Further, the number of blocks driving the signals is also reduced resulting in lower power consumption and lower implementation cost. 
         [0083]      FIG. 20  illustrates a further example of a pixel circuit to which the shared addressing scheme is applicable. The pixel circuit  150  of  FIG. 20  is similar to the pixel circuit  130  of  FIG. 17 . The pixel circuit  150  includes an OLED  152 , storage capacitors  154  and  156 , a drive TFT  158 , and switch TFTs  160 ,  162 , and  164 . The gate terminal of the switch TFT  164  is connected to a controllable voltage supply VDD, rather than GSEL. The drive TFT  158 , the switch TFT  162  and the first storage capacitor  154  are connected at node A 6 . The switch TFT  162  and the first and second storage capacitors  154  and  156  are connected at node B 6 . The drive TFT  158  and the switch TFTs  160  and  164  are connected to node C 6 . 
         [0084]      FIG. 21  illustrates an example of a timing schedule applied to the pixel circuit  150 . In  FIG. 21 , operating cycles X 61 , X 62 , X 63 , and X 64  form a generating frame cycle (e.g.,  302  of  FIG. 9 ), the second operating cycles X 63  and X 64  form a post-compensation frame cycle (e.g.,  304  of  FIG. 9 ). 
         [0085]    Referring to  FIGS. 20 and 21 , the pixel circuit  150  employs bootstrapping effect to add a programming voltage to the generated V T  where V T  is the threshold voltage of the drive TFT  158 . The compensation cycles (e.g.  301  of  FIG. 9 ) include the first two cycles X 61  and X 62 . During the first operating cycle X 61 , node A 6  is charged to a compensation voltage, and node B 6  is charged to V REF  through the switch TFT  162  and VDATA. The timing of the first operating cycle x 61  is small to control the effect of unwanted emission. During the second operating cycle x 62 , VDD goes to zero and thus it turns off the switch TFT  164 . The voltage at node A 6  is discharged through the switch TFT  160  and the drive fn.  158  and settles to V OLED +V T  where V OLED  is the voltage of the OLED  152 , and V T  is the threshold voltage of the drive TFT  158 . During the programming cycle, i.e., the third operating cycle x 63 , node B 6  is charged to V P +V REF  where V P  is a programming voltage. It has been identified Thus the gate voltage of the drive TFT  158  becomes V OLED +V T +V P . Here, the first storage capacitor  154  is used to store the V T +V OLED  during the compensation interval. 
         [0086]      FIG. 22  illustrates an example of an AMOLED display array structure for the pixel circuit  150  of  FIG. 20 . In  FIG. 22 , SEL[a] (a=1, . . . , m) corresponds to SEL of  FIG. 22 , GCMP[b] (b=1, . . . , K) corresponds to GCOMP of  FIG. 22 , GVDD[c] (c=1, . . . , k) corresponds to VDD of  FIG. 22 , and VDATA[d] (d=1, . . . , n) corresponds to VDATA of  FIG. 22 . The AMOLED display  230  of  FIG. 22  includes a plurality of pixel circuits  150  which are arranged in row and column, an address driver  234  for controlling SEL[a], GCOMP[b], and GVDD[c], and a data driver  236  for controlling VDATA[c]. The rows of the pixel circuits  230  are segmented (e.g., segment [ 1 ] and segment [k]) as described above. 
         [0087]    Referring to  FIGS. 20 and 22 , VDD and GCOMP signals of the rows in one segment are connected together and form GVDD and GCOMP lines. GVDD and GCOMP signals are shared in the segment. Moreover, GVDD and GCOMP in the same segment are merged together and form the segment GVDD and GCOMP lines. Thus, the controlling signals are reduced. Further, the number of blocks driving the signals is also reduced resulting in lower power consumption and lower implementation cost. 
         [0088]    According to the embodiments of the present invention, the operating cycles are shared in a segment to generate an accurate threshold voltage of the drive TFT. It reduces the power consumption and signals, resulting in lower implementation cost. The operating cycles of a row in the segment are overlapped with the operating cycles of another row in the segment. Thus, they can maintain high display speed, regardless of the size of the display. 
         [0089]    The accuracy of the generated VT depends on the time allocated to the V T -generation cycle. The generated V T  is a function of the storage capacitance and drive TFT parameters, as a result, the special mismatch affects the generated VT associated within the mismatch in the storage capacitor for a given threshold voltage of the drive transistor. Increasing the time of the V T -generation cycle reduces the effect of special mismatch on the generated V T . According to the embodiments of the present invention, the timing assigned to V T  is extendable without either affecting the frame rate or reducing the number of rows, thus, it is capable of reducing the imperfect compensation and spatial mismatch effect, regardless of the size of the panel. 
         [0090]    The V T -generation time is increased to enable high-precision recovery of the threshold voltage V T  of the drive TFT across its gate-source terminals. As a result, the uniformity over the panel is improved. In addition, the pixel circuits for the addressing schemes have the capability of providing a predictably higher current as the pixel ages and so as to compensate for the OLED luminance degradation. 
         [0091]    According to the embodiments of the present invention, the addressing schemes improve the backplane stability, and also compensate for the OLED luminance degradation. The overhead in power consumption and implementation cost is reduced by over 90% compared to the existing compensation driving schemes. 
         [0092]    Since the shared addressing scheme ensures the low power consumption, it is suitable for low power applications, such as mobile applications. The mobile applications may be, but not limited to, Personal Digital Assistants (PDAs), cell phones, etc. 
         [0093]    All citations are hereby incorporated by reference. 
         [0094]    The present invention has been described with regard to one or more embodiments. However, it will be apparent to persons skilled in the art that a number of variations and modifications can be made without departing from the scope of the invention as defined in the claims.

Technology Category: g