Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a clock monitoring circuit for detecting that the period of a clock signal has become shorter than a predetermined permissible range. 
     2. Description of the Related Art 
     Processors that operate in synchronization with a clock signal generated by a clock generating circuit and that execute various types of processing are currently implemented, for example, in the form of MPUs (Micro Processing Units). Processors such as MPUs are designed to operate in synchronization with a clock signal of a predetermined period and are therefore subject to overrunning when the period of this clock signal has become shorter than the predetermined period. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a clock monitoring circuit that can easily and accurately detect that the period of a clock signal has become shorter than a predetermined period. 
     It is another object of the present invention to provide a data processing device that is equipped with the above-described clock monitoring circuit and that can prevent overrunning of a processing circuit when the period of the clock signal has become shorter than the predetermined period. 
     In order to achieve the above-described objects, the clock monitoring circuit of the present invention comprises first and second flip-flop circuits, a delay means, and a gate circuit. The first and second flip-flop circuits are D-type flip-flops that latch input signals in synchronization with the rising edge or falling edge of a clock signal. 
     The second flip-flop circuit receives as an input signal the output signal of the first flip-flop circuit. The output signal of the second flip-flop circuit is delayed a fixed time period by the delay means and then supplied as an input signal to the first flip-flop circuit. The delay time of the delay means is set to be equal to the previously described predetermined period. 
     The gate circuit is constructed such that it receives the output signals of the first and second flip-flop circuits and provides an output signal whose logic level depends on whether the period of the input clock signals is the predetermined period or not. A shortening of the period of the clock signal can thus be detected according to the logic level of the output signal of the clock monitoring circuit. 
     A data processing device according to the present invention includes the aforementioned clock monitoring circuit. When an abnormality in the clock signal is detected by the clock monitoring circuit, this abnormality is communicated to an operation control circuit that controls the operation of the processor, halting the operation of the processor. 
     Overrunning in the processing circuit due to abnormalities of the clock signal can thus be stopped. 
     The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings, which illustrate examples of the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention; 
     FIG. 2 is a circuit diagram showing the construction of the clock monitoring circuit shown in FIG. 1; 
     FIG. 3 is a timing chart showing the operation of the clock monitoring circuit shown in FIG. 2; and 
     FIG. 4 is a block diagram showing the construction of a data processing system as an application of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 1, there is shown a data processing device according to an embodiment of the present invention that includes reset input terminal  102 , a plurality of data input/output terminals  103 , clock generating circuit  104 , MPU  105  which executes data processing, clock monitoring circuit  106 , and operation control circuit  107 . 
     Reset input terminal  102  is connected to MPU  105  and clock monitoring circuit  106 . Data input/output terminal  103  is connected to MPU  105 . MPU  105  is further connected to clock generating circuit  104  and operation control circuit  107 . Clock monitoring circuit  106  is also connected to clock generating circuit  104  and operation control circuit  107 . 
     Clock generating circuit  104  is provided with, for example, a crystal oscillator (not shown), and generates a clock signal of a predetermined period T. A computer program for executing processing, i.e., software or firmware, is installed in MPU  105 , and MPU  105  executes processing in synchronization with the clock signal generated by clock generating circuit  104 . 
     In other words, MPU  105  executes processing in accordance with the various types of data that are supplied from data input/output terminals  103 , and outputs the data resulting from this processing from data input/output terminals  103 . Accordingly, the data processor can communicate with an outside apparatus (not shown) by way of data input/output terminals  103 , and can execute various types of data processing in accordance with this communication. 
     When a reset signal is applied as input to reset input terminal  102 , the reset signal is applied to MPU  105  and clock monitoring circuit  106 , whereby MPU  105  and clock monitoring circuit  106  are reset. 
     Clock monitoring circuit  106  monitors the period of the clock signal generated by clock generating circuit  104 . When the period of the clock signal becomes shorter than a predetermined reference time interval, clock monitoring circuit  106  provides a clock abnormality signal to operation control circuit  107 . When operation control circuit  107  receives the clock abnormality signal from clock monitoring circuit  106 , it forcibly halts the processing performed by MPU  105 . 
     Referring now to FIG. 2, the clock monitoring circuit of this embodiment comprises reset input terminal  111 , clock input terminal  112 , signal output terminal  113 , flip-flop(hereinafter abbreviated to FF) circuit  114 , signal delay circuit  115 , FF circuit  116 , exclusive-OR circuit  117 , inverter element  118 , inverter element  119 , and FF circuit  120 . 
     Reset input terminal  111  is connected to the reset terminal of FF circuit  114 , the set terminal of FF circuit  116 , and the reset terminal of FF circuit  120 . Clock input terminal  112  is connected to the clock terminals of FF circuit  114  and FF circuit  116 , and to the clock terminal of FF circuit  120  by way of inverter element  119 . The signal input terminal of FF circuit  114  and the signal output terminal of FF circuit  116  are connected each other through feedback signal  121 . In addition, the signal output terminal of FF circuit  114  and the signal input terminal of FF circuit  116  are connected by way of signal delay circuit  115 . 
     The signal output terminals of FF circuit  114  and FF circuit  116  are each connected to a respective signal input terminal of exclusive-OR circuit  117 . The signal output terminal of exclusive-OR circuit  117  is connected to the signal input terminal of FF circuit  120  by way of inverter element  118 . The signal output terminal of FF circuit  120  is connected to signal output terminal  113 , and signal output terminal  113  is connected to operation control circuit  107  (FIG.  1 ). 
     FF circuit  114  is reset by the reset signal. FF circuit  114  receives output signal Q 2  of FF circuit  116  as input signal D 1 , latches input signal D 1  at the rising edge of input clock signal CLK, and provides output signal Q 1  as input to signal delay circuit  115 . 
     Signal delay circuit  115  is made up of two inverter elements that are connected in series. Signal delay circuit  115  delays output signal Q 1  of FF circuit  114  by a predetermined time interval, and provides as input signal D 2  to FF circuit  116 . This delay time must be set shorter than the period of the normal clock signal and longer than the minimum period of the clock signal at which MPU  105  can operate normally. 
     FF circuit  116  is set by the reset signal, receives input signal D 2 , latches input signal D 2  at the rising edge of received clock signal CLK, and provides output signal Q 2  as output. Output signal Q 2  is supplied as input signal D 1  to FF circuit  114 . Exclusive-OR circuit  117  exclusively ORs output signal Q 1  of FF circuit  114  with output signal Q 2  of FF circuit  116  and provides the resultant signal as an output. Inverter element  118  inverts the output signal of exclusive-OR circuit  117  and provides the resultant signal as input signal D 3  to FF circuit  120 . 
     FF circuit  120  is reset by the reset signal, receives input signal D 3  that is output from inverter  118 , latches input signal D 3  at the rising edge of clock signal CLK that was inverted by inverter element  119 , and provides output signal Q 3  as an output. Output signal Q 3  of FF circuit  120  is supplied to operation control circuit  107  by way of signal output terminal  113 . 
     The operation of this embodiment will next be described with reference to FIG.  3 . Upon receipt of a clock signal of a predetermined period T at clock input terminal  112  at time t 1 , output signal Q 2  (input signal D 1 ) of FF circuit  116  is latched by FF circuit  114  at the rising edge of clock signal CLK and generated as output signal Q 1 . 
     Output signal Q 1  of FF circuit  114  is delayed a predetermined time interval by signal delay circuit  115 . FF circuit  116  receives the delayed signal, i.e., input signal D 2 , latches input signal D 2  at the rising edge of clock signal CLK, and provides the signal as output signal Q 2 . 
     If the period of clock signal CLK is longer than the delay time of signal delay circuit  115 , output signal Q 1  of FF circuit  114  becomes a signal that is the inverted logic of output signal Q 2  of FF circuit  116 , and output signal Q 2  of FF circuit  116  becomes a signal that is the inverted logic of output signal Q 1  of FF circuit  114 . Accordingly, the output signal of exclusive OR circuit  117  maintained at low logical level. 
     If the operation of FF circuit  114  and the operation of FF circuit  116  are not synchronized with complete accuracy, however, spike noise occurs in output signal D 3  of exclusive-OR circuit  117  even if the period of clock signal CLK is longer than the delay time of signal delay circuit  115 . In the clock monitoring circuit of the embodiment, however, FF circuit  120  receives, as input signal D 3 , the output signal of exclusive-OR circuit  117  that has been inverted by inverter element  118 , and by matching the logic level of output signal Q 3  with the logic level of input signal D 3  at the rising edge of clock signal CLK that is inverted by inverter element  119 , the spike noise that occurs in output signal D 3  of exclusive-OR circuit  117  due to the timing error between FF circuit  114  and FF circuit  116  is eliminated. 
     If the period of clock signal CLK is shorter than the delay time of signal delay circuit  115  at time t 2 , output signal Q 1  of FF circuit  114  and output signal Q 2  of FF circuit  116  both go low between time t 2  and time t 3 . Input signal D 3  of FF circuit  120  goes accordingly high. Output signal Q 3  also goes high, and a clock abnormality signal is transmitted as output from output terminal  113  to operation control circuit  107 . Operation control circuit  107  receives the clock abnormality signal and forcibly halts the operation of MPU  105 , thereby reliably preventing overrunning of MPU  105 . 
     When the period of clock signal CLK returns to T at time t 4 , clock monitoring circuit  106  operates as previously described. 
     In clock monitoring circuit  106  of the present embodiment, moreover, since signal delay circuit  115  is constituted by logic circuits, the delay time of signal delay circuit  115  does not vary in analog fashion, and since the clock monitoring circuit itself is constituted by digital circuits, clock monitoring circuit  106  is capable of stable operation. 
     The present invention is not limited to the above-described embodiment, and allows various modifications within the scope of the invention. Although signal delay circuit  115  is constituted by logic circuits and clock monitoring circuit  106  is constituted entirely by digital circuits in the above-described embodiment, an analog signal delay circuit composed of, for example, resistors and capacitors or a signal delay circuit made up of a long wiring may also be used. 
     Furthermore, although a case has been described in the present embodiment in which a data processor incorporates a clock generating circuit, data processing system  200  may be constructed which includes data processor  201  that does not incorporate a clock generating circuit, as shown in FIG.  4 . 
     Data processing system  200  comprises parent device  202  which can be equipped with data processor  201  as a subordinate device, and parent device  202  comprises clock generating circuit  104  and clock output terminal  203 . Data processor  201  is equipped with clock input terminal  204 , and clock input terminal  204  and clock output terminal  203  are connected when data processor  201  is equipped with parent device  202 . 
     The clock signal generated by clock generating circuit  104  of parent device  202  is supplied from clock output terminal  203  to clock input terminal  204  of data processor  201 , and each of portions  105 - 107  of data processing device  201  operate in synchronization with the clock signal. 
     As described previously, a clock signal is supplied from parent device  202  to data processor  201  in data processing system  200 . With such configuration, however, data processor  201  can accept parent devices of a variety of standards, and a clock signal having a period that is shorter than the predetermined period may be supplied to data processor  201 . To avoid this, data processing device  201  comprises clock monitoring circuit  106  and operation control circuit  107 , thereby preventing overrunning of MPU  105 . 
     Although FF circuit  114  and FF circuit  116  are designed to operate at the rising edge of clock signal CLK and FF circuit  120  is designed to operate at the falling edge of clock signal CLK in clock monitoring circuit  106  of this embodiment, FF circuit  114  and FF circuit  116  may be designd to operate at the falling edge of clock signal CLK and FF circuit  120  may be designed to operate at the rising edge of clock signal CLK. In addition, inverted output signals {overscore (Q)} may be used as the output signals of FF circuit  114 , FF circuit  116 , and FF circuit  120 , respectively, instead of output signals Q 1 , Q 2 , and Q 3 . 
     While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.

Technology Category: g