Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a Divisional of U.S. patent application Ser. No. 10/867,845, filed on Jun. 14, 2004, now pending, which claims priority from Korean Patent Application No. 2003-39164, filed on Jun. 17, 2003, the contents of which are hereby incorporated by reference for all purposes. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Technical Field Of The Invention  
         [0003]     This disclosure relates to transistor manufacturing for a semiconductor memory, and more particularly, to a transistor having a recess channel and a method for forming the same.  
         [0004]     2. Description of the Related Art  
         [0005]     A MOS transistor is generally constructed of gate, drain and source regions. A gradually increasing integration density in semiconductor devices requires the continued miniaturization of transistors, but there is a limitation in that a junction depth of a source and drain region can&#39;t become exceedingly shallow. That is, the gradual reduction of the length of channel causes the depletion region of the source and drain to invade the interior of channel, reducing the effective length of the channel along with the threshold voltage. A short channel effect is thus generated, and gate control function in the MOS transistor is lost. The shortened channel length causes a high electric field in the semiconductor device, which generates a hot carrier. The hot carrier brings about collision ionization and the hot carrier thus invades an oxide film. The oxide film is thus degraded.  
         [0006]     In order to prevent these short channel effects, a thickness of a gate insulation film should be reduced, and a channel between the source and drain, namely, a maximum width of the depletion region provided under the gate should be reduced, and a density of dopant in the semiconductor substrate should be reduced.  
         [0007]     In order to prevent the short channel effect, conventional methods have attempted to ion implant a dopant of opposite conductivity type into a lower part of the channel region, together with the shallow junction. Furthermore, in order to prevent the hot carrier effect, most conventional transistor manufacturing processes employ a lightly doped drain (LDD) structure, which forms a buffering region of a low density implantation between the gate region and the drain region, which have a high density implantation. However, since the channel length is continuously shortened by tendency to increase the integration density of the semiconductor device, the transistor of the LDD structure has the short channel and hot carrier phenomena, too. Furthermore, the dopants in the source and drain regions are diffused to a side thereof, by a punchthrough effect, during operation of the transistor.  
         [0008]     In order to solve these problems, a transistor structure has been proposed that has a gate formed in a recess channel that is formed in the semiconductor substrate. The recess is formed in a region where a channel of the transistor would be formed, increasing an effective channel length and improving the punchthrough resistance of the source and the drain regions. The recess actually widens a distance between the source and the drain, enhancing a high-integration density of the semiconductor device.  
         [0009]     FIGS.  1  to  7  are cross-sectional views illustrating a sequential manufacturing process for a transistor having a recess channel according to the conventional art.  
         [0010]     With reference to  FIG. 1 , a low density doping layer  18  is formed through an ion implantation on a semiconductor substrate  12  on which a device separation film  14  is formed, and a channel adjusting dopant layer  16  is formed to prevent punchthrough. On the semiconductor substrate  12  on which the low density doping layer  18  and the channel adjusting dopant layer  16  were formed, an oxide film  20  and a mask film  22  are formed.  
         [0011]     In  FIG. 2 , an opening  23  having a predetermined pattern is formed in the mask film  22 .  
         [0012]     An open critical dimension (CD) in an upper part of the opening  23  is about 90 nm, and a CD in a lower part of the opening  23  is about 50 nm.  
         [0013]     In  FIG. 3 , the semiconductor substrate  12  and the oxide film  20  exposed in the lower part of the opening  23  are etched by using the mask film  22  as an etch mask, to thus form a recess  24 .  
         [0014]     A process of forming the recess  24  includes a break-through (BT) process of removing the oxide film  20  and a process of forming the recess  24 .  
         [0015]      FIG. 4  illustrates the semiconductor substrate  12  having the recess  24  formed after a chemical dry etching (CDE) process is performed to remove the mask film  22 .  
         [0016]     The recess  24  has a generally large open CD and the upper edge of the recess  24  is formed as a pointed shape.  
         [0017]     In  FIG. 5 , the oxide film  20  remaining on the semiconductor substrate  12  is removed and this is passed through a thermal oxide process, then a gate oxide film  26  is formed on an overall face of the semiconductor substrate  12  including the recess  24 .  
         [0018]     In  FIG. 6 , a gate stack  33  containing a gate electrode  28  formed of polysilicon, a metal silicide layer  30 , and a gate insulation film  32 , is formed on the semiconductor substrate  12  having the gate oxide film  26 .  
         [0019]     The CD of the gate stack  33  is about 60 nm, smaller than the upper open CD of the recess, to be entered inside the recess  24 .  
         [0020]     In  FIG. 7 , gate spacers  34  are formed on either side of the gate stacks  33 .  
         [0021]     Source and drain regions are formed by implanting a high-density doping ion into the semiconductor substrate  12  having the gate spacer. A series of these processes completes the conventional transistor having the recess channel.  
         [0022]     This method of forming the transistor according to the conventional art exhibits the following problems.  
         [0023]     First, since the recess has a structure where an open CD of the recess  24  is greater than a CD of a gate stack  33 , polysilicon on the sides of the gate electrode collapses toward an interior lower side of the recess  24  during a necessary etching process for forming the gate stack. According to conventional methods, there is difficulty in controlling the level of collapse. Furthermore, if a deposited thickness of the gate electrode is thin, an aspect ratio becomes large, and reducing a process margin and other issues concerning a profile become problematic.  
         [0024]     Secondly, when the upper CD of the recess is large, there is a problem that a bottom CD of a self aligned contact (SAC) that is formed as a bitline contact or a storage node contact in a subsequent process should be formed relatively small.  
         [0025]     Thirdly, in etching a polysilicon used as material for use of the mask in order to form an etch mask pattern on a semiconductor substrate, the surface of the oxide film is not uniform because the oxide film exposed in the lower part is also partially etched. Thus, a difference in an etching depth is caused in the BT process as the process of etching the oxide film among processes of forming the recess. This causes a difference from a depth of the recess.  
         [0026]     Fourthly, in forming the gate oxide film on the semiconductor substrate, an upper part of the recess is formed as a pointed shape, thus causing a thinned effect of the gate oxide film and a concentrated phenomenon of electric field onto an edge portion of the upper part of the recess. Furthermore, a leakage current increases and a degradation of the gate oxide film may occur.  
         [0027]     Embodiments of the invention address these and other disadvantages of the conventional art.  
       SUMMARY OF THE INVENTION  
       [0028]     Some embodiments of the invention provide a method of forming a transistor having a recess channel and a structure thereof, in which an open CD of a recess is formed small to prevent a side face of a gate electrode from collapsing in forming the gate electrode and to small form an aspect ratio of the gate electrode, thus provide a process margin largely and improve problems concerning a profile, caused due to a large open CD of the recess.  
         [0029]     Some embodiments provide a method of forming a transistor having a recess channel and a structure thereof, which is capable of improving a small bottom CD of a SAC, etc. Some embodiments of the invention also provide a method of forming a transistor having a recess channel and a structure thereof, which is capable of preventing a difference in the recess channel depth and of forming the recess uniformly.  
         [0030]     Further embodiments of the invention provide a method of forming a transistor having a recess channel and a structure thereof, an upper edge of the recess being formed with a rounded shape to prevent a gate oxide film from being thinned and the upper edge of the recess from being concentrated by an electric field, thus preventing an increase of leakage current and a degradation of the gate oxide film. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0031]     The above and other features of the invention will become readily apparent from the description of the exemplary embodiments that follows, with reference to the attached drawing.  
         [0032]     FIGS.  1  to  7  are cross-sectional diagrams illustrating a sequential manufacturing process for a transistor having a recess channel according to the conventional art.  
         [0033]     FIGS.  8  to  15  are cross-sectional diagrams illustrating a sequential manufacturing process for a transistor having a recess channel according to some embodiments of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0034]     According to some embodiments of the invention, a method of forming a transistor having a recess channel and a structure thereof will be described with reference to FIGS.  8  to  15 . It will be understood by those skilled in the art that the invention may be practiced in numerous different ways and is not limited to the following described embodiments. Rather, the embodiments described below are exemplary in nature.  
         [0035]     FIGS.  8  to  15  are cross-sectional diagrams illustrating a sequential manufacturing process for a transistor having a recess channel according to some embodiments of the invention, and the resulting structure.  
         [0036]     Referring to  FIG. 8 , a low density doping layer  118  is formed through an ion implantation on a semiconductor substrate  112  on which a device separation film  114  was formed, and a channel adjusting dopant layer  116  is formed to prevent punchthrough. On the semiconductor substrate  112  on which the low density doping layer  118  and the channel adjusting dopant layer  116  were formed, a pad oxide film  120  and a mask film  122  are formed.  
         [0037]     The low density doping layer  118  is formed near the surface of the semiconductor substrate  112 . The channel adjusting dopant layer  116  is formed to prevent a short channel effect, and is formed by doping with a dopant having conductivity opposite to the dopant of the low density doping layer  118 .  
         [0038]     The pad oxide film  120  may be desirably formed of a medium temperature oxide (MTO) film, and its thickness is about 100 Å. The mask film  122  may be desirably formed of polysilicon, and its thickness has about 1000 Å.  
         [0039]     With reference to  FIG. 9 , a mask pattern in which an opening  123  having a predetermined pattern is formed by etching the mask film  122 .  
         [0040]     The opening  123  is formed to expose the pad oxide film  120 , and the pad oxide film  120  serves as an etch stop film. An open CD of the opening  123  is about 50 nm to 100 nm.  
         [0041]     Referring to  FIG. 10 , an undercut region  123   a  is formed by selectively etching the pad oxide film  120  exposed in the opening  123 . The undercut region is formed in such a way that the pad oxide film  120  provided underneath the mask film is partially removed. The etching of the pad oxide film  120  is performed through a wet etching method as an isotropic etching method. The undercut region  123   a  preferably undercuts the edges of the mask film by about 100 Å.  
         [0042]     The pad oxide film  120  is removed through the wet etching method, thus the pad oxide film removal process can be omitted from the recess forming process described below in order to prevent a nonuniformity of the recess depth caused by the pad oxide film removal process.  
         [0043]     In  FIG. 11 , a sidewall spacer  125  is formed in the mask film  122  involving the undercut region  123   a , in which the opening  123  was formed.  
         [0044]     The sidewall spacer  125  is formed by depositing polysilicon to a thickness of about 200 Å. Furthermore, the polysilicon of the sidewall spacer  125  completely fills the undercut region  123   a  formed in the pad oxide film  120 .  
         [0045]     The process of forming the sidewall spacer  125  includes forming a material film for use as a sidewall spacer on the semiconductor substrate including the undercut region, then anisotropically etching the sidewall spacer material film. The anisotropic etching is preferably performed by a reactive ion etching method or a plasma etching method.  
         [0046]     In  FIG. 12 , a recess  124  is formed by etching the semiconductor substrate  112  using the sidewall spacer  125  and the mask film  122  as a mask.  
         [0047]     When the recess  124  is formed, the sidewall spacer  125  and the mask film  122  are etched at the same time. Thus, differently from the prior art, a BT process of etching the oxide film  120  is omitted. Consequently, a non-uniformity of the recess depth is prevented by the etching process of the oxide film  120 , to uniformly form the depth of the recess  124 . Furthermore, since the sidewall spacer  125  is used as an etching mask to form the recess  124 , an open CD of the recess  124  is minimized.  
         [0048]     A tint of the sidewall spacer  125 , and the undercut region  123   a  formed by wet-etching the pad oxide film  120 , resulting in a convexly rounded edge portion of the upper part of the recess  124 . A depth of the recess  124  is preferably about 1000 Å to 1500 Å.  
         [0049]      FIG. 13  shows the resulting structure on the semiconductor substrate  112  after removing the pad oxide film  120 .  
         [0050]     In alternative embodiments of the invention, an isotropic etching process is additionally performed before removing the pad oxide film  120 . To additionally perform the isotropic etching process is to remove an unetched portion of the recess  124  and to roundly form an interior shape of the recess  124 .  
         [0051]     The isotropic etching employs a CDE method. After the CDE process, the pad oxide film  120  remaining on the semiconductor substrate  112  is removed. An open CD of the upper part of the recess is about 65 nm.  
         [0052]     Since the semiconductor substrate  112  is damaged by the etching process used to form the recess  124 , a thermal oxide process may be additionally formed to remove the damage. Also, a process for removing the oxide film generated by the thermal oxide process may be performed.  
         [0053]     Forming a channel adjusting dopant doping region in a lower part of the recess  124  may also be added to prevent punchthrough.  
         [0054]     In  FIG. 14 , a gate oxide film  126  is formed on the semiconductor substrate  112  having the recess  124 , and a gate stack  133  involving a gate electrode  128 , a metal silicide film  130 , and a gate insulation film  132  is formed on an upper part of the recess  124  on which the gate oxide film  126  was formed.  
         [0055]     The gate stack  133  is formed by sequentially depositing a gate electrode material, a metal silicide material, and a gate insulation material on the semiconductor substrate  112  having the recess  124  and by performing a photolithography and etching process.  
         [0056]     The gate electrode  128  is formed by depositing polysilicon, and the metal silicide film  130  can be formed additionally thereto in order to reduce a contact resistance. The metal silicide film  130  can be formed of WSi x  , TaSi 2 , or MoSi 2 .  
         [0057]     The gate insulation film can be formed of a silicon oxide film, a silicon nitride film SiN, or a silicon oxynitride film SiON, etc. The gate electrode  128  is formed in the interior of the recess  124 , and is overlapped with the roundly formed edge portion of the upper part of the recess  124 , which is higher than the semiconductor substrate. A CD of the gate electrode  128  is about 60 nm.  
         [0058]     A low density doping layer may also be added onto the semiconductor substrate having the gate stack.  
         [0059]     In  FIG. 15 , a gate spacer  134  is formed on the semiconductor substrate having the gate stack  133 .  
         [0060]     The gate spacer  134  can be desirably formed of a silicon oxide film, or a family of a silicon nitride film SiN or silicon oxynitride film SiON, etc.  
         [0061]     On the semiconductor substrate having the gate stack  133  and the gate spacer  134 , a source region  136   s  and a drain region  136   d  doped by a high density are formed, to thus form a transistor having a recess channel. A method of forming the a source region  136   s  and the drain region  136   d  doped by the high density employs an ion implantation method.  
         [0062]     The inventive method of forming the transistor having the recess channel type gate, and the structure thereof, are applicable not only to an NMOS (N-type Metal Oxide Semiconductor) transistor, but also to a PMOS (P-type Metal Oxide Semiconductor) transistor, and also applicable to others such as a CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor).  
         [0063]     As described above, a transistor having a recess channel has the following advantages as compared with the conventional art, for example.  
         [0064]     Differently from the method of forming a transistor having a recess channel according to the conventional art, embodiments of the invention form a small open CD of the recess through an etching process using a sidewall spacer. Thus, a collapse phenomenon of a gate electrode does not occur in an etching process of forming a gate stack. In addition, the problems of a relatively large aspect ratio of the gate electrode or a relatively large open CD of the recess can be solved. Thus, process margins can become larger.  
         [0065]     Also, a transistor having a recess channel formed by embodiments of the invention can solve a problem where a bottom CD becomes small in a self aligned contact (SAC) formation since the open CD of the recess is formed small.  
         [0066]     Further in the process of forming the recess according to embodiments of the invention, an oxide film is removed previously through a wet etching method, differently from a recess forming procedure of the prior art, thus a BT process can be omitted in the recess forming process. Thus, the problem of different depth recesses do not occur in the recess forming procedure, and the recesses may be formed uniformly.  
         [0067]     Additionally, in forming the recess to form a gate electrode according to embodiments of the invention, since an upper edge portion thereof is formed roundly and convexly, a thinned phenomenon of a gate oxide film is prevented and an electric field concentrated phenomenon onto the upper edge portion of the recess can be prevented, and an increase of leakage current and a degradation of the gate oxide film can be prevented.  
         [0068]     The invention may be practiced in many ways. What follows are exemplary, non-limiting descriptions of some embodiments of the invention.  
         [0069]     According to some embodiments of the invention, a method of forming a transistor having a recess channel includes sequentially forming a pad oxide film and a mask film on a semiconductor substrate having a device separation film, and then forming an opening for partially exposing the pad oxide film by performing a photolithography and etching process on the mask film. Next, forming an undercut region using an etching process is performed by using the mask film as an etch mask, to simultaneously etch the pad oxide film exposed in the opening and the pad oxide film provided in an edge lower part of the mask film, thus exposing a partial surface of the semiconductor substrate that extends under an edge of the lower part of the mask film to form the undercut region. Subsequently, a sidewall spacer is formed that extends from the undercut region and that surrounds both sidewalls of the mask film, and an etching process using the mask film as the etch mask is performed to form a recess in the semiconductor substrate. Subsequently, a gate oxide film is formed on the semiconductor substrate inside the recess, then a gate electrode is formed in the recess over the gate oxide film. The gate electrode overlaps with an upper edge portion of the recess and is positioned higher than an upper part of the recess. Next, a gate insulation film is formed on the gate electrode. Then, a gate spacer is formed on the semiconductor substrate where the gate electrode and the gate insulation film were formed. Finally, a source region and a drain region doped with a high density dopant are formed.  
         [0070]     The method may further include forming a low density doping layer on the semiconductor substrate, and preferably further includes forming a channel adjusting dopant doping region for preventing a punchthrough in a lower part of the recess. The method can further include performing a thermal oxide process after the etching process of the semiconductor substrate to form the recess, and may further include removing a silicon oxide film formed through the thermal oxide process.  
         [0071]     In performing the etching process to form the recess, the mask film used as the etch mask and the sidewall spacer can be etched simultaneously. After forming the recess, an isotropic etching process using a CDE method may be further performed in the recess interior to form the transistor that has a recessed channel. The etching process using the CDE method is performed desirably in a range from 100 Å to 200 Å. The gate electrode is formed, further including a metal silicide film.  
         [0072]     According to other embodiments of the invention, a structure of a transistor having a recess channel includes a semiconductor substrate having a recess, an edge portion of the upper part of the recess being rounded convexly, a corner portion of the interior of the recess being rounded concavely. This structure also includes a gate oxide film formed on an inner face of the recess, and a gate electrode that overlaps with the rounded edge portion of the upper part of the recess. The gate electrode is formed higher than the semiconductor substrate, and is also formed being buried into the interior of the recess on the gate oxide film.  
         [0073]     It will be apparent to those skilled in the art that modifications and variations can be made in the present invention without deviating from the spirit or scope of the invention. Thus, it is intended that the present invention cover any such modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. For instance, a shape of a gate stack, a shape of a recess, or a configuration of film material, etc. can be changed through a transistor forming procedure, or steps in a manufacturing process can be added or omitted. Accordingly, these and other changes and modifications are seen to be within the true spirit and scope of the invention as defined by the appended claims.

Technology Category: h