Patent Document

BACKGROUND OF THE INVENTION 
     I. Field of the Invention 
     The invention presented relates to pseudonoise (PN) sequence generators. More particularly, the present invention relates to a method and an apparatus for generating PN sequence with each clock pulse by computing their bits in parallel. 
     II. Description of the Related Art 
     The Telecommunications Industry Association has standardized a method for code division multiple access (CDMA) communications in the IS-95 family of interim standards, entitled “Mobile Station-Base Station Compatibility Standard for Dual Mode Wideband Spread Spectrum Cellular System.” In addition, the Telecommunications Industry Association in its submission to the International Telecommunications Union, entitled “The cdma2000 ITU-R RTT Candidate Submission,” describes proposed CDMA system that would be able to support higher data rates and higher capacity. Both in the IS-95 standard and in the cdma2000 proposal, the transmitted waveform is modulated in accordance with a pseudonoise spreading sequence. 
     The use of a pseudonoise sequence with appropriate autocorrelation characteristics is essential to the operation of a CDMA system in which multipath components are present. The generation and employment of pseudonoise sequences are described in detail in U.S. Pat. No. 4,901,307, entitled “SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM USING SATELLITE OR TERRESTRIAL REPEATERS,” assigned to the assignee of the present invention, and incorporated by reference herein. The use of CDMA techniques in a multiple access communication system is further disclosed in U.S. Pat. No. 5,103,459, entitled “SYSTEM AND METHOD FOR GENERATING SIGNAL WAVEFORMS IN A CDMA CELLULAR TELEPHONE SYSTEM,” assigned to the assignee of the present invention, and incorporated by reference herein. 
     The aforementioned U.S. Pat. Nos. 4,901,307 and 5,103,459 describe the use of a pilot signal used for acquisition. The use of a pilot signal enables the remote user to acquire local base station communication system in a timely manner. The remote user gets synchronization information and relative signal power information from the received pilot signal. U.S. Pat. Nos. 5,644,591 and 5,805,648, both entitled “METHOD AND APPARATUS FOR PERFORMING SEARCH ACQUISITION IN A CDMA COMMUNICATION SYSTEM,” describe a novel and improved method and apparatus that reduces the remote user forward link acquisition time. Both patents are assigned to the assignee of the present invention and are incorporated by reference herein. 
     Space or path diversity is obtained by providing multiple signal paths through simultaneous links from a remote user through two or more cell-sites. Furthermore, path diversity may be obtained by exploiting the multipath environment through spread spectrum processing by allowing a signal arriving with different propagation delays to be received and processed separately. Examples of path diversity are illustrated in U.S. Pat. No. 5,101,501, entitled “SOFT HANDOFF IN A CDMA CELLULAR TELEPHONE SYSTEM,” and U.S. Pat. No. 5,109,390, entitled “DIVERSITY RECEIVER IN A CDMA CELLULAR TELEPHONE SYSTEM,” both assigned to the assignee of the present invention, and incorporated by reference herein. 
     In CDMA communications systems, a pilot signal is transmitted that allows a receiver to coherently demodulate the received signal. Within demodulator of such receivers is a channel estimate generator, which estimates the channel characteristics based on the pilot signal transmitted with values known to both the transmitter and the receiver. The pilot signal is demodulated and the phase ambiguities in the received signal are resolved by taking the dot product of the received signal and the pilot signal channel estimate. An exemplary embodiment of a circuit for performing the dot product operation is disclosed in U.S. Pat. No. 5,506,865, entitled “PILOT CARRIER DOT PRODUCT CIRCUIT,” assigned to the assignee of the present invention, and incorporated by reference herein. 
     SUMMARY OF THE INVENTION 
     The invention presented is a novel method and apparatus for generating a PN sequences with an arbitrary number of bits, where the number of bits is provided in parallel with each clock pulse. This allows the sequences to be generated at high speed when needed, and allows parallel processing in the acquisition and demodulation processes. The invention describes in detail generation of PN sequences as standardized for the IS-95 communications systems. As proposed in the IS-95 standards, the pseudonoise spreading sequences are maximal length sequences that are capable of being generated using linear feedback shift-registers (LSFRs). Using a linear feedback shift-register, the PN sequences are computed one bit with each clock pulse. 
     In the invention, the initial PN states are loaded into registers of a parallel PN generator, which immediately generates the next n bits of the PN sequence, where n is an arbitrary number dependent on performance required. In addition, the present invention provides a method of determining the register states of the parallel PN generator an arbitrary number of cycles in the future. Thus, the present invention takes the present state of the registers of the PN generator and outputs the next n bits of the generator. In addition, the PN generator of the present invention receives the present state of the PN generator and outputs the state of the PN generator n bits in the future. In this fashion, the entire PN sequence can be continuously generated. 
     It will be understood by one skilled in the art that although the present invention is directed toward the generation of a psuedonoise sequences compliant with systems standardized by the Telecommunications Industry Association, the teachings of the present invention are equally applicable to the generation of other psuedonoise sequences such as, the orthogonal Gold code sequences proposed for use in the W-CDMA, proposals to the International Telecommunications Industry Association, proposals by the European Telecommunications Standards Institute (ETSI), and the Association of Radio Industries and Business (ARIB). 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features, objects, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein: 
     FIGS. 1 a - 1   d  illustrate prior art embodiments of pseudonoise (PN) generators employing linear feedback shift-registers; 
     FIG. 2 depicts prior art of pseudonoise generators employed to generate parallel groups of PN sequence; 
     FIG. 3 is a block diagram illustrating the generalized operation of the present invention apparatus for generating the PN sequences; 
     FIG. 4 shows one embodiment of the invention; 
     FIG. 5 is a simplified block diagram of an exemplary receiver chain using PN generators in accordance with the invention; and 
     FIG. 6 is a block diagram of a part of an exemplary single demodulation chain using PN generators in accordance with the invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 a  illustrates a traditional apparatus employing a linear feedback shift-register for generating pseudonoise sequences. The generalized shift-register  100  from FIG. 1 a  comprises memory elements  102   a ,  102   b , . . . ,  102   n , holding state values S 0 (n), S 1 (n), . . . , SN N (n). The last value S N  constitutes an output of the shift-register, and also a feedback to modulo-2 adders  104   a , . . . ,  104   m . Before the value S N  is provided to a particular modulo-2 adder  104   a , . . . ,  104   m , it is multiplied by an associated coefficient g 0 , g 1 , . . . , g N . A coefficient will take a value of ‘1’ if a feedback is desired, and a value of ‘0’ otherwise. 
     Short-code pseudonoise sequences are used to modulate and demodulate the in-phase (I) and quadrature-phase (Q) components of the CDMA waveform. The I and Q short-code PN sequences are periodic with a period of 2 15 −1 with a bit stuffed at the preamble of sequence to make the sequence periodic with an even factor of 2. 
     The short-code PN I  sequence satisfies a linear recursion specified by the following generator polynomial (P I ): 
     
       
           P   I ( x )= x   15   +x   13   +x   9   +x   8   +x   7   +x   5 +1.  (1) 
       
     
     FIG. 1 b  depicts a shift-register implementation for generating the PN I  sequence. Note that in accordance with FIG. 1 a , only the ‘1’ valued coefficients g 15 , g 13 , g 9 , g 8 , g 7 , g 5 , g 0 , are present. 
     The short-code PN Q  sequence satisfies a linear recursion specified by the following generator polynomial (P Q ): 
     
       
           P   Q ( x )= x   15   +x   12   +x   11   +x   10   +x   6   +x   5   +x   4   +x   3 +1.  (2) 
       
     
     FIG. 1 c  depicts a shift-register implementation for generating the PN Q  sequence. 
     FIG. 1 d  shows a shift-register implementation of a long-code PN generator with a mask. The long-code is periodic, with period 2 42 −1 chips and satisfies a linear recursion specified by the following characteristic polynomial (P): 
       P ( x )= x   42   +x   35   +x   33   +x   31   +x   27   +x   26   +x   25   +x   22   +x   21   +x   19   +x   18   +x   17   +x   16   ++x   10   +x   7   +x   6   +x   5   +x   3   +x   2   +x +1.  (3) 
     The mask used for the long-code is channel type dependent, and can be found along with further details about the implementation of the PN generators in a document entitled “Physical Layer Standard for cdma2000 Spread Spectrum Systems.” 
     It is sometimes desired to obtain an output of a shift-register as a parallel combination of output state values S N (n), S N (n+1), . . . , S N (n+K). FIG. 2 shows a block diagram of a parallel PN generator  200  according to the prior art. The PN generator comprises a shift-register  100  in accordance with a description for FIG. 1 a , followed by a serial-to-parallel converter  202 . The PN generator outputs K values of S N (n) for shift instances n, n+1, . . . ,n+K. However, there are K clock cycles required for generating the set of K output values. In the prior art understanding, in order to generate the parallel PN generator outputs, the outputs of the linear feedback shift-registers illustrated in FIGS. 1 a  and  1   b  are provided to the serial to parallel converter. 
     FIG. 3 shows a block diagram of inventive alternative to the implementation of FIG.  2 . In general, a relationship between values of shift register in a state (n) and next state (n+1) can be expressed as a system of equations: 
     
       
           S   N ( n +1)= g   11   ·S   N ( n )+ . . . + g   1N−1   ·S   2 ( n )+ g   1N   ·S   1 ( n )  (4a) 
       
     
     
       
           S   2 ( n +1)= g   N−11   ·S   N ( n )+ . . . + g   N−1N−1   ·S   2 ( n )+ g   2N   ·S   1 ( n )  (4n-1) 
       
     
     
       
           S   1 ( n +1)= g   N1   ·S   N ( n )+ . . . + g   NN−1   ·S   2N−1 ( n )+ g   NN   ·S   1 ( n )  (4n) 
       
     
     Such a system of equations can be re-written in a matrix form as: 
     
       
           S ( n +1)= G*S ( n ),  (5) 
       
     
     where: 
     S(n+1) is a column matrix containing the state values of the state after a shift, 
     G is a coefficient matrix comprising the g values indicated in equations 4a-4n, and 
     S(n) is a column vector of present states. 
     Once a state after a shift has been determined, the next state can be calculated using equation (5): 
     
       
           S ( n +2)= G*S ( n +1).  (6) 
       
     
     Substituting equation (5) into equation (10) then results into an equation: 
     
       
           S ( n +2)= G*G*S ( n )= G   2   *S ( n ).  (7) 
       
     
     Further generalization of equation (11) yields an equation: 
     
       
           S ( n+k )= G   k   *S ( n ).  (8) 
       
     
     where k is a number expressing a state, in which an output is to be computed. 
     Applying these principles to FIG. 1, it is obvious that a value of a certain register in next state S 1 (n+1) is a function of a value of the preceding register in current state S 1-1 (n), and—if a feedback exists—a value of the output register in current state S N (n). Consequently, the system of equations (4) will have at most two non-zero coefficients in each of the equations (4a) through (4n). 
     As an example, the G matrix for a PN I  shift-register in accordance with FIG. 1 b  will be developed as follows: 
     Observing, that there is a connection between stages S 15  and S 14  and no feedback from stage S 15 , it follows that the next state value of S 15  is equal to previous state value of S 14 . Thus, equation (4a) will take a form: 
     
       
           S   15 ( n +1)=0 ·S   15 ( n )+1 ·S   14 ( n )  (9) 
       
     
     Consequently, the first row of matrix G will contain a non-zero element only in a position g 12 : 
     
       
         G 1 =[010000000000000]  (10) 
       
     
     Equivalent relation will hold for all stages an input of which is an output of another stage. 
     Turning to the next stage S 14 , one can observe that its next state value is equal to previous state value of stage S 13  summed with a previous state value of stage S 15 . Thus, the equation (4b) will take a form: 
     
       
           S   14 ( n +1)=1 ·S   15 ( n )+1 ·S   13 ( n )  (11) 
       
     
     Consequently, the second row of matrix G will contain a non-zero (unity) element in a position g 21 , and g 23 : 
     
       
         G 2 =[010000000000000]  (10) 
       
     
     Equivalent relation will hold between all stages an input of which is a sum of outputs of two stages. 
     Reference back to FIG. 3 will expand on these concepts. State memory  212  is initialized to an initial set of states S 1 (n), S 2 (n), . . . , S N (n). These states are then provided to an output generator  214 , and a next state generator  216 . Next state generator  216  contains a coefficient matrix G NS  formed in accordance with the principles outlined in description of equations (4) and (5). In the exemplary embodiment, the generator polynomial has relatively few feedback taps and, consequently, the resultant matrix G is sparse. This sparseness permits a relatively simple implementation of the matrix operation to be performed using fixed Boolean operator programmed into a field programmable gate array or designed into an application specific integrated circuit (ASIC). 
     Next state generator  216  accepts the set of states S 1 (n), S 2 (n), . . . , S N (n) from state memory  212  to compute a set of new states S 1 (n+K), S 2 (n+K), . . . , S N (n+K) in accordance with equation (12), and provides the set of new states back to the state memory  212 . 
     The output generator  214  performs a matrix operation on the current states in accordance with a matrix G OS  formed as follows. As explained in description to FIG. 1 a , the output of a shift-register is the state S N (n). From equation (8) follows that: 
     
       
           S ( n +0)= G   0   *S ( n ).  (13) 
       
     
     where G 0  is a matrix having non-zero elements only in the main diagonal. Inspecting the system of equations (4), it is obvious that value S N (n) can be calculated using equation (4a). This equation is equivalent to forming a row matrix G R  by taking the first row of a matrix G NS   0  and multiplying it by a column matrix of states S formed from values S 1 (n), S 2 (n), . . . , S N (n). Therefore, the first row of a matrix G NS  becomes the last row of matrix G OS . Similarly, from equation (8), the value S N (n+1) can be calculated by forming a row matrix G R  by taking the first row of a matrix G NS   2 , and multiplying it by a column matrix of states S. Thus, the last row of a matrix G NS  becomes the last but one row of matrix G OS . This process of forming the matrix G OS  continues until all K rows are filled. In mathematical terms:                  G   OS     =     [           G   NS   K             ⋮             G   NS   1               G   NS   0           ]       ,           (   14   )                                
     where G NS   k  is last row of matrix G NS   k . 
     Once matrix G OS  has been formed, the output generator  214  computes the values S N (n+1), S N (n+2), . . . , S N (n+K) by multiplying the matrix G OS  by a column matrix of states S: 
     
       
           S   N ( n+K )= G   OS   ·S ( n )  (15) 
       
     
     A long-code output generator  214  differs from the structure of short-code output generator. The reason is that the long-code generator contains a mask, which can be different for each long-code generator, see, “The cdma2000 ITU-R RTT Candidate Submission” and FIG. 1 d . The PN output bit of the long code is a modulo-2 addition of values of the shift registers multiplied by the mask. The output bit can be expressed in matrix notation as follows: 
     
       
           pn   OUT ( n )= M*S ( n ),  (16) 
       
     
     where: 
     pn OUT (n) is an output bit in a state n, and 
     M is a column mask matrix. 
     Substituting equation (8) into equation (16) results in: 
     
       
           pn   OUT ( n+k )= M*G   k   *S ( n ),  (17) 
       
     
     From equation (10) follows that desired output of K+1 parallel bits can be achieved by forming matrix G OSL                   G   OSL     =     [           M   *     G   NSL   K               ⋮             M   *     G   NSL   1                 M   *     G   NSL   0             ]       ,           (   18   )                                
     and, once matrix G OSL  has been formed, the output generator  214  computes the values pn(n), pn(n+1), . . . , pn(n+K) by multiplying the matrix G OSL  by a column matrix of states S: 
     
       
           pn ( n+K )= G   OSL   ·S ( n ),  (19) 
       
     
     At this point of the process the set of states, S 1 (n+K), S 2 (n+K), . . . , S N (n+K) is provided to an output generator  214 , a next state generator  216 , and the whole cycle is repeated. 
     In particular, let us consider the G matrix for a PN I  shift-register to be the basic next state generator matrix G NSI :          G   NSl1     =     [         010000000000000           101000000000000           000100000000000           000010000000000           000001000000000           100000100000000           100000010000000           100000001000000           000000000100000           100000000010000           000000000001000           000000000000100           000000000000010           000000000000001           100000000000000                    ]                            
     Matrix G NSl   0  is as follows:          G   NSl0     =     [                    100000000000000           010000000000000           001000000000000           000100000000000           000010000000000           000001000000000           000000100000000           000000010000000           000000001000000           000000000100000           000000000010000           000000000001000           000000000000100           000000000000010           000000000000001                    ]                            
     Taking the first row of matrix G NSl   0  and last row of matrix G NSI , the matrix G OSI2  is formed as follows:          G   OSl2     =     [         010000000000000           100000000000000                    ]                            
     One ordinarily skilled in the art will recognize that matrix G OS  can be modified according to desired PN generator output, without departing from the scope of the invention. For example, if a parallel output S N (n), S N (n+2), S N (n+4), and S N (n+6) is desired, matrix G OS  will comprise in accordance with equation (14) first row of G NS   6  in row one, first row of G NS   4  in row two, first row of G NS   2  in row three, and first row of G NS   0  in row four. 
     FIG. 4 depicts a block diagram of a preferred embodiment of the parallel PN generator. In addition to the state memory  212 , the output generator  214 , and a next state generator  216 , it contains a jump generator  218  and a control processor  220 . The function of the jump generator  218  is to advance the state by predetermined number of shifts. Such a function is desirable e.g., for forward link acquisition as described in aforementioned U.S. Pat. Nos. 5,644,591 and 5,805,648. In the exemplary embodiment, the PN generator is employed in a receiver in accordance to an IS-95 standard. The systems designed in accordance with an IS-95 standard comprise base stations utilizing a common PN generator, with a phase offset in increments of 64 chips for a particular pilot signal. Consequently, the jump generator  218  is functionally equivalent to next state generator  216  in that it comprises a coefficient matrix G JS  formed in accordance with the principles outlined in description of FIG. 1 a , and raised to the power of 64. 
     Next state generator  216  receives the set of states S 1 (n), S 2 (n), . . . , S N (n) from state memory  212  and generates a set of new states S 1 (n+64), S 2 (n+64), . . . , S N (n+64) in accordance with equation (8), and provides the set of new states back to state memory  212 . The reason for having a separate next state generator  216  and a jump generator  218  is that in general K≠L, and, consequently, the matrices G OS  and G JS  are different. As described above, the present invention is preferably implemented in hardware adapted to the specific operation and designed to perform a specific task. 
     The function of the control processor  220  is to coordinate cooperation between the different subsystems, and to control bit stuffing. As described, the short-code PN sequences have a period of 2 15  generating polynomials, and from them derived matrices, generate only sequences with period 2 15 −1. The control processor  200  monitors the output of the next state generator  216  for the state preceding the state corresponding to a period 2 15 −1, for which a computation of next state according to equation (8) would exceed the state corresponding to a period 2 15 −1. Once the control processor  200  detects such state it performs two operations. It will cause the output generator  214  to compute the output state values, and overwrites the last output state value with ‘0’. It will then avoid writing the output of the next state generator  216  into state memory  212 , and will initialize the state memory  212  to initial set of states S 1 (n), S 2 (n), . . . , S N (n). 
     FIG. 5 depicts a simplified block diagram of an exemplary receiver chain using PN generators in accordance with the invention. The RF signal arriving at the antenna  400  is provided to the receiver (RCVR)  402 , which downconverts the received signal to a baseband frequency, producing I and Q components of the signal. These components are simultaneously provided to a searcher  404  and demodulators  406   a , . . . ,  406   c . The task of the searcher  404  is to perform searches in code space to identify candidate signals to be added to the Active Set of the remote station in order to maximize the quality of the received signal. To accomplish this task, searcher  404  will control parameters of the PN sequences generators, devised in accordance with the principles outlined in present invention. An exemplary method for performing acquisition and searching in a CDMA communication system is described in detail in aforementioned U.S. Pat. Nos. 5,644,591 and 5,805,648 
     In order to be effective, a receiver must be able to operate in a multipath environment and must be able to adapt to changes in physical location. In the aforementioned U.S. Pat. Nos. 5,101,501 and 5,109,390, a method for exploiting the reception of multiple version of a signal is described. Demodulators  406   a ,  406   b  and  406   c  demodulate redundant versions of the same signal. This redundant version either correspond to multipath propagations of a signal from a single source or from multiple transmissions of the same information from multiple base stations in a soft handoff condition. 
     The demodulated signals from demodulators  406   a , . . . ,  406   c  are provided to combiner  410 , which combines the signals and provides them for further processing to a de-interleaver  412  and decoder  414 . 
     FIG. 6 illustrates the exemplary embodiment of the receiver structure of the present invention. The signal is received at antenna  400  and provided to receiver (RCVR)  402 . Receiver  402  downconverts, amplifies, filters, and samples the received signal, and provides digital samples to buffer  404 . In response to signals from control processor  403 , a selected set of samples from buffer  404  is provided to despreader  408 . In addition, in response to a signal from control processor  403 , PN generator  406  provides a portion of a PN sequence to depreader  408 . 
     Despreader  408  despreads the signal in accordance with the portion of the PN sequence provided by PN generator  406  which operates in accordance with the present invention. Within despreader  408  the PN sequence is provided to pilot despreader  412 , which despreads the received signal in accordance with the portion of the short PN sequence provided by PN generator  406  and the Walsh covering sequence for the pilot signal. In the exemplary embodiment, the pilot signal is covered with the Walsh zero sequence and as such does not effect the despreading operation performed by pilot despreader  412 . In addition, the portion of the short PN sequence is provided to traffic despreader  414 , which despreads the signal in accordance with the short PN sequence and the Walsh traffic covering sequence W T . 
     The result of the despreading operation performed by pilot despreader  412  and the result of the despreading operation performed by traffic despreader  414  are provided to dot product circuit  416 . The pilot signal has known symbols and can be used to remove the phase ambiguities introduced by the propagation path as described in the aforementioned U.S. Pat. No. 5,506,865. The result of the dot product operation is provided to combiner  410 . Combiner  410  combines redundantly despread version of the same symbols whether transmitted by different base stations in a soft handoff environment or by the same base station traversing different propagation paths in a multipath environment. 
     In accordance with an exemplary demodulation chain embodiment, and previous discussion follows that a first set of matrices is required for the short-code PN generator for the I component, a second set for the short-code PN generator for the Q component, and a third set for the long-code PN generator. 
     1. Acquisition Mode. 
     In the exemplary embodiment, the receiver is able to rapidly determine jump 64 chips ahead in the PN sequence in order to perform a correlation process to determine the correlation energy of between the received signal and a portion of the PN sequence. 
     In the generation of the short PN I  sequence, state memory  212  provides the current state of the PN sequence S(n) to next state generator  216 . Next state generator  216  generates the state of the PN sequence S(n+2) two cycles in advance by left-multiplying the PN sequence S(n) by the matrix G NSI2 :          G     NSI2                  =     [         101000000000000           010100000000000           000010000000000           000001000000000           100000100000000           110000010000000           110000001000000           010000000100000           100000000010000           010000000001000           000000000000100           000000000000010           000000000000001           100000000000000           010000000000000         ]                            
     In the generation of the short PN I  sequence, state memory  212  provides the current state of the PN sequence S(n) to jump generator  218 . Jump generator  218  generates the state of the PN sequence S(n+2) sixty-four (64) cycles in advance by left-multiplying the PN sequence S(n) by the matrix G JSI64 :          G   JSI64     =     [         101011010100101           010101101010010           000001100001100           000000110000110           000000011000011           000000001100001           101011010010101           011110111101111           000100001010010           000010000101001           101010010110001           110101001011000           011010100101100           101101010010110           010110101001011         ]                            
     In the generation of the short PN I  sequence, the next state generator  216  or the jump generator  218  provides the current state of the PN sequence S(n) to output generator  214 . Output generator  214  computes the values S N (n+1), S N (n+2), . . . , S N (n+K) left-multiplying a column matrix of states S(n) by the matrix G OSI2 :          G   OSI2     =     [         010000000000000           100000000000000         ]                            
     The short-code PN generator for the Q component  518  uses an algorithm for PN sequence generation, identical to the one for the acquisition mode. Consequently, the set of matrices as well as their application is identical.          G   NSQ2     =     [         001000000000000           100100000000000           110010000000000           110001000000000           010000100000000           000000010000000           000000001000000           100000000100000           110000000010000           110000000001000           110000000000100           010000000000010           000000000000001           100000000000000           010000000000000         ]               G   JSQ64     =     [         100011001011100           010001100101110           001000110010111           000111010010111           100000100010111           110011011010111           011001101101011           101100110110101           110110011011010           011000000110001           101111001000100           110100101111110           011001011100011           001100101110001           000110010111000         ]               G   OSQ2     =     [         010000000000000           100000000000000         ]                            
     In the generation of the long-code PN sequence, state memory  212  provides the current state of the PN sequence S(n) to next state generator  216 . Next state generator  216  generates the state of the PN sequence S(n+2) two cycles in advance by left-multiplying the PN sequence S(n) by the matrix G NSL2 :                           
     In the generation of the long-code PN sequence, state memory  212  provides the current state of the PN sequence S(n) to jump generator  218 . Jump generator  218  generates the state of the PN sequence S(n+64) sixty-four (64) cycles in advance by left-multiplying the PN sequence S(n) by the matrix G JSL64 :                           
     In the generation of the long-code PN sequence, the next state generator  216  or the jump generator  218  provides the current state of the PN sequence S(n) to output generator  214 . Output generator  214  first computes the output state matrix G OSL  by left-multiplying matrix M by matrices G NSL0 :                           
     ,and by matrix G NS1 :                           
     , and then computes the output bits pn OUT (n+k) by multiplying the resulting matrix G OSL  by a column matrix of states S. 
     2. Demodulation Mode: 
     The demodulation mode uses algorithm for PN sequence generation, identical to the one for the acquisition mode. Consequently, the set of matrices as well as their application is identical. 
     The short-code PN generator for the I component  516  comprises the following matrices:          G   NSI8     =     [         010010101000000           001001010100000           110110000010000           111011000001000           011101100000100           101110110000010           000101110000001           010000010000000           011010100000000           001101010000000           010100000000000           101010000000000           010101000000000           001010100000000           100101010000000         ]               G   JSI64     =     [         101011010100101           010101101010010           000001100001100           000000110000110           000000011000011           000000001100001           101011010010101           011110111101111           000100001010010           000010000101001           101010010110001           110101001011000           011010100101100           101101010010110           010110101001011         ]               G   OSI8     =     [         100101010000000           001010100000000           010101000000000           101010000000000           010100000000000           101000000000000           010000000000000           100000000000000         ]                            
     The short-code PN generator for the Q component  518  comprises the following matrices:          G   NSQ8     =     [         101111001000000           010111100100000           101011110010000           011010110001000           000010010000100           001110000000010           100111000000001           110011100000000           111001110000000           010011110000000           000110110000000           101100010000000           111001000000000           111100100000000           011110010000000         ]               G   JSQ64     =     [         100011001011100           010001100101110           001000110010111           000111010010111           100000100010111           110011011010111           011001101101011           101100110110101           110110011011010           011000000110001           101111001000100           110100101111110           011001011100011           001100101110001           000110010111000         ]               G   OSQ8     =     [         011110010000000           111100100000000           111001000000000           110010000000000           100100000000000           001000000000000           010000000000000           100000000000000         ]                            
     The long-code PN generator for  518  comprises the following matrices:                                                                                                                                                                                                                                                                     
     The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. The various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Technology Category: g