Patent Document

FIELD OF INVENTION 
   This invention relates generally to multiplexer circuits, and more particularly to multiplexer circuits capable of level-shifting logic signals. 
   DESCRIPTION OF RELATED ART 
   Multiplexer circuits are very common in integrated circuits (ICs) and other electronic circuits. For example, multiplexer circuits are used throughout many programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), to programmably select one of several different input signals to pass to a logic destination, or to select one of several stored values to provide as the output signal from a lookup table (LUT). Therefore, multiplexers can form a significant portion of the logic circuitry in a PLD. 
     FIG. 1  illustrates a well-known 8-to-1 binary multiplexer (MUX) circuit  100 . A similar MUX architecture is commonly used to implement look-up tables (LUT) that form function generators in the configurable logic blocks of an FPGA. The choice of eight input signals for the various MUX circuits illustrated herein is purely exemplary. MUX circuits often have fewer or more than eight input signals. The drawings herein are standardized on 8-to-1 MUX circuits simply to simplify the drawings and to provide a common standard for comparison purposes. MUX circuits having different numbers of input signals are easily extrapolated from the illustrated examples by those of skill in the relevant arts. 
   MUX architecture  100  is shown to include a MUX circuit  110  and a keeper circuit  120 . MUX circuit  110 , which includes inputs to receive input signals IN 0 -IN 7  and select terminals to receive select signals SA-SC, is implemented using three hierarchical levels of 2:1 MUXes formed by pairs of NMOS transistors, as depicted in  FIG. 1 . More specifically, the first-level MUXes formed by transistor pairs MA 0 -MA 1 , MA 2 -MA 3 , MA 4 -MA 5 , and MA 6 -MA 7  receive input signal pairs IN 0 -IN 1 , IN 2 -IN 3 , IN 4 -IN 5 , and IN 6 -IN 7 , respectively, where transistors MA 0 , MA 2 , MA 4 , and MA 6  have gates responsive to SA, and transistors MA 1 , MA 3 , MA 5 , and MA 7  have gates responsive to  SA , which is the logical complement of SA provided by inverter INVA. The second-level MUXes formed by transistor pairs MB 0 -MB 1  and MB 2 -MB 3  receive input signals from corresponding pairs of the first-level MUXes, where transistors MB 0  and MB 2  have gates responsive to SB, and transistors MB 1  and MB 3  have gates responsive to  SB , which is the logical complement of SB provided by inverter INVB. The third-level MUX formed by transistor pair MC 0 -MC 1  receives input signals from corresponding pairs of the second-level MUXes and includes an output terminal at node N 1 , where transistor MC 0  has a gate responsive to SC, and transistor MC 1  has gate responsive to  SC , which is the logical complement of SC provided by inverter INVC. 
   Keeper circuit  120  includes CMOS inverter INV 1  and a PMOS pull-up transistor MP 1 . Inverter INV 1  is coupled between node N 1  and the MUX architecture&#39;s output terminal OUT, and has power terminals coupled to ground potential and to VDD. Although not shown for simplicity, inverter INV 1  is formed in a well-known manner by a PMOS and an NMOS transistor pair coupled in series between VDD and ground potential. PMOS transistor MP 1  is coupled between VDD and node N 1 , and has a gate coupled to OUT. 
   When MUX architecture  100  is used to implement a LUT in an FPGA, the input signals IN 0 -IN 7  are typically stored in SRAM configuration cells (not shown for simplicity) and the select signals SA-SC are used as LUT input signals to select one of signals IN 0 -IN 7  to output as OUT in a well-known manner. For example, to select IN 0  for output as OUT, SA-SC are all driven to a logic high state of VDD, thereby turning on transistors MA 0 , MB 0 , and MC 0  so that IN 0  propagates through transistors MA 0 , MB 0 , and MC 0  to node N 1  as IN_N 1 . The logic high value of IN_N 1  is logically inverted by INV 1  to drive OUT to logic low. For applications in which the logic “1” values of IN 0 -IN 7  and the logic “1” values of SA-SC are approximately equal to VDD, the input signal IN 0  experiences a voltage drop as it propagates through NMOS pass gates MA 0 , MB 0 , and MC 0  such that the logic “1” value of IN_N 1  is approximately equal to VDD−Vth, where Vth is the total voltage drop across transistors MA 0 , MB 0 , and MC 0 . Keeper circuit  120  compensates for this voltage drop by turning on PMOS transistor MP 1  when OUT is driven to logic low, thereby pulling the voltage of IN_N 1  to approximately VDD. 
   The MUX architecture of  FIG. 1  works well with sufficiently high values of VDD. For example, as long as the voltage level VDD−Vth is high enough to flip inverter INV 1  and turn on PMOS pull-up transistor MP 1 , the circuit functions properly. However, power voltage levels (VDD) are much lower in today&#39;s ICs than was previously the case. For example, when VDD=1.2 volts and Vth=0.5 volts, a voltage level of VDD−Vth=0.7 volts cannot be relied upon to flip inverter INV 1 . 
   Various methods have been used to resolve this problem. One known method is to use a gate voltage higher than VDD when driving a logic “1” high value onto the gates of the NMOS pass transistors, for example, by implementing select signals SA-SC and inverters INVA-INVC using a “pumped” high voltage greater than VDD. For example, if the NMOS gate voltage is higher than VDD by one threshold voltage Vth, the resulting voltage of IN_N 1  at node N 1  is VDD+Vth−Vth, or simply VDD. However, this solution complicates the fabrication of the circuit, especially at very short gate lengths. 
   Perhaps more importantly, many newer FPGA architectures utilize multiple voltage domains to balance the desire for high performance with the desire for low power consumption. For example, in some FPGAs, resources such as configurable logic blocks (CLB) are powered by a relatively high supply voltage (VDDH), and resources such as the programmable interconnect are powered by a relatively low supply voltage (VDDL). Thus, when MUX architecture  100  is used to implement a LUT in a CLB, the input signals IN 0 -IN 7  are typically stored in configuration memory cells (not shown for simplicity) powered by VDDH, and the select signals SA-SC are received from a low-voltage domain powered by a relatively low supply voltage VDDL, where for purposes of discussion herein VDDH is equal to approximately 1.2 volts and VDDL is equal to approximately 0.8 volts. For such FPGAs, because the logic “1” values of IN 0 -IN 7  are approximately equal to VDDH and the logic “1” values of select signals SA-SC are approximately equal to VDDL, level-shifter circuits are typically required to increase the peak voltage level of select signals SA-SC from VDDL to VDDH so that MUX architecture  100  operates properly. Unfortunately, using level-shifters for select signals SA-SC not only increases circuit area but also introduces circuit delays for select signals SA-SC. 
   Thus, there is a need to incorporate level-shifting functions within the MUX architectures that implement LUTs in the CLBs of FPGA devices. 
   SUMMARY 
   The present invention incorporates level-shifting functions within a multiplexer circuit that may be implemented in IC devices such as an FPGA having two-different voltage domains, e.g., a low-voltage domain and a high-voltage domain. The multiplexer circuit utilizes pseudo-differential multiplexing architectures and employs level-shifting techniques to convert low-voltage signals received from the low-voltage domain into high-voltage signals more suitable for the high-voltage domain. In this manner, multiplexer circuits of the present invention may reduce propagation delay and/or may minimize voltage drops of signals selected to be propagated through the multiplexer circuit. 
   For some embodiments, the multiplexer circuit includes a level-shifting decoder circuit, two multiplexers, a signal inversion circuit, and an output circuit. The level-shifting decoder circuit has inputs to receive two or more of the low-voltage select signals and is configured to generate a number of high-voltage decoded select signals. The first multiplexer has inputs to receive the high-voltage input signals, has select terminals responsive to a combination of the low-voltage select signals and the high-voltage decoded select signals, and has an output. The signal inversion circuit generates logical complements of the high-voltage input signals. The second multiplexer has, inputs to receive the high-voltage complemented input signals, has select terminals responsive to the combination of the low-voltage select signals and the high-voltage decoded select signals, and has an output. The output circuit has inputs coupled to the outputs of the first and second multiplexers, and has first and second output terminals to generate a differential output signal for the multiplexer circuit. 
   For some embodiments, the first and second multiplexers are organized as hierarchical levels of pass transistors, for example, where the pass transistors in the first level are organized in pairs and are coupled to receive the input signals, and the transistors in the second level are coupled between corresponding transistor pairs in the first level and output terminals in the second level. For one embodiment, the gates of the transistors in the first level are responsive to the low-voltage select signals, and the gates of the transistors in the second level are responsive to the high-voltage decoded select signals. By driving the pass gates in the second hierarchical level with high-voltage select signals, as opposed to low-voltage select signals, propagation delays across the pass gates are reduced. In addition, by utilizing decoded select signals to control the second hierarchical level, the third hierarchical level of previous MUX architectures may be eliminated, thereby reducing circuit area and reducing the number of gate delays. 
   For other embodiments, the first and second multiplexers are organized as hierarchical levels of pass transistors, for example, where the pass transistors in the first hierarchical level receive the input signals and are responsive to the low-voltage encoded select signals, and the transistors in the second hierarchical level are arranged in pairs and are responsive to the high-voltage decoded select signals. By driving the pass gates in the first hierarchical level with high-voltage select signals, as opposed to low-voltage select signals, propagation delays across the pass gates are reduced. In addition, by utilizing decoded select signals to control the first hierarchical level, the third hierarchical level of previous MUX architectures may be eliminated, thereby reducing circuit area and reducing the number of gate delays. 
   In addition, the output circuit restores the voltage levels of signals propagated through the multiplexer circuit to their maximum values, thereby ensuring that the output inverters trigger properly and also maintaining an acceptable drive strength for the output signals. 
   Further, the invention enables the use of multiplexers that include only N-channel transistors in the signal paths between the data input and output terminals, even at very low operating voltages. Power dissipation and leakage current are also lower than is normally achieved using traditional multiplexer circuits. Additionally, the layout area required to implement the resulting structures is less than is required for traditional CMOS implementations. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention are illustrated by way of example and are by no means intended to limit the scope of the present invention to the particular embodiments shown, and in which: 
       FIG. 1  is a circuit diagram of a well-known multiplexer circuit that may be used to implement look-up tables in an FPGA device; 
       FIG. 2  is a simplified functional block diagram of an IC device including a level-shifting multiplexer circuit in accordance with first embodiments of the present invention; 
       FIG. 3  is a circuit diagram of one embodiment of the level-shifting multiplexer circuit of  FIG. 2 ; 
       FIG. 4  is a simplified functional block diagram of an IC device including a level-shifting multiplexer circuit in accordance with second embodiments of the present invention; 
       FIG. 5  is a circuit diagram of one embodiment of the level-shifting multiplexer circuit of  FIG. 4 ; 
       FIG. 6  is a block diagram of one embodiment of the level-shifting decoder circuit of  FIG. 5 ; 
       FIG. 7  is a circuit diagram of one embodiment of the AND gate of  FIG. 6 ; 
       FIG. 8  is a circuit diagram of another embodiment of the level-shifting multiplexer circuit of  FIG. 4 ; and 
       FIG. 9  is a circuit diagram of one embodiment of the level-shifting multiplexer circuit of  FIG. 2  that may be used to implement signal routing functions. 
   

   Like reference numerals refer to corresponding parts throughout the drawing figures. 
   DETAILED DESCRIPTION 
   In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present invention. In other instances, well-known circuits and devices are shown in block diagram form to avoid obscuring the present invention unnecessarily. Further, the logic states of various signals described herein are exemplary and therefore may be reversed or otherwise modified as generally known in the art. Accordingly, the present invention is not to be construed as limited to specific examples described herein but rather includes within its scope all embodiments defined by the appended claims. 
     FIG. 2  shows an IC device  140  including a pseudo-differential multiplexer circuit  200  in accordance with first embodiments of the present invention. IC device  140 , which may be any suitable IC device, includes a low-voltage domain  150  and a high-voltage domain  160 . Low-voltage domain  150  is powered by a relatively low supply voltage VDDL, and includes a well-known interconnect structure  151  having a power terminal coupled to VDDL and having outputs to generate low-voltage select signals SA-SC. High-voltage domain  160  includes multiplexer (MUX) circuit  200  and a plurality of memory cells  161  having power terminals coupled to VDDH. Memory cells  161 , which may be any suitable type of memory cell such as DRAM or SRAM cells, provide high-voltage input signals IN 0 -IN 7  to MUX circuit  200 , which in response to select signals SA-SC outputs one of IN 0 -IN 7  as a high-voltage output signal OUT. For some embodiments, memory cells  161  and MUX circuit  200  may form a look-up table (LUT) that generates OUT as a predetermined logic function of select signals SA-SC. 
   For other embodiments, the configuration memory cells that store IN 0 -IN 7  may be powered by a regulated voltage (Vgg), where Vgg=VDDH+Vth. For such embodiments, input signals IN 0 -IN 7  have a logic “1” voltage of approximately Vgg. 
   For some embodiments, IC device  140  is an FPGA device having different voltage domains  150  and  160 , where interconnect structure  151  forms part of the switch fabric of the FPGA device and the LUT formed by memory cells  161  and MUX circuit  200  implements a function generator in a configurable logic block (CLB) of the FPGA device. Of course, for other embodiments, IC device  140  may be another programmable logic device such as a complex PLD, or may be a dedicated logic device such as an ASIC device. 
   For purposes of discussion herein, the low-voltage select signals SA-SC have voltage swings approximately between 0 volts and VDDL, and input signals IN 0 -IN 7  have voltage swings approximately between 0 volts and VDDH. VDDL and VDDH may be any suitable supply voltages. For one embodiment, VDDL is approximately 0.8 volts and VDDH is approximately 1.2 volts, although other voltage levels may be used for VDDL and VDDH. 
   MUX circuit  200  includes two MUXes  210  and  220 , an inversion circuit  230  coupled between the input terminals of the two MUXes  210  and  220 , and an output circuit  240  coupled to the output terminals of the two MUXes  210  and  220 . More specifically, the first MUX  210  includes a plurality of inputs to receive input signals IN 0 -IN 7  from memory cells  161 , select terminals to receive select signals SA-SC from interconnect structure  151 , and an output coupled to a first input of output circuit  240  at node A. Inversion circuit  230  includes inputs to receive IN 0 -IN 7 , and is configured to generate complementary input signals  IN 0   -  IN 7    at its output terminals. The second MUX  220  includes a plurality of inputs to receive complementary input signals  IN 0   -  IN 7    from inversion circuit  230 , select terminals to receive select signals SA-SC, and an output coupled to a second input of output circuit  240  at node B. 
   MUxes  210  and  220  may be any suitable multiplexers such as, for example, binary multiplexers or one-hot multiplexers. For some embodiments, MUXes  210  and  220  include only NMOS transistors on each signal path between the input terminals and the output terminal of each multiplexer. Further, the select terminals of the two MUXes  210  and  220  are coupled such that the two MUXes  210  and  220  are configured to select a corresponding one of their respective input signals IN 0 -IN 7  and  IN 0   -  IN 7   , respectively, in response to equivalent signals received at their respective select input terminals. 
   Inversion circuit  230  may be implemented using any suitable circuitry. For one embodiment, inversion circuit  230  may include a plurality of inverters (e.g., CMOS inverters) each coupled between a corresponding pair of inputs of MUXes  210  and  220 . For another embodiment, inversion circuit  230  may be part of a memory cell providing true and complement logic signals to MUXes  210  and  220 , respectively. For yet another embodiment, inversion circuit  230  may be implemented using pull-down transistors gated by corresponding input signals, as known in the art. Further, although not shown for simplicity, for some embodiments, inversion circuit  230  includes power terminal coupled to VDDH and ground potential. 
   Output circuit  240 , which includes power terminals coupled to VDDH and ground potential, is configured to generate the output signal OUT in response to the voltage differential between its two input terminals at nodes A and B, thereby allowing a relatively low voltage value of a logic “1” input signal IN 0 -IN 7  to drive OUT to its proper logic state, as described in more detail below. For some embodiments, output circuit  240  may be configured to level-shift the signals IN and  IN  received from MUXes  210  and  220 , respectively, when generating OUT. 
     FIG. 3  shows a MUX circuit  300  that is one embodiment of MUX circuit  200  of  FIG. 2 . Circuit  300  is shown to include a first MUX  310 , a second MUX  320 , an input signal inversion circuit  330 , and an output circuit  340 . Further,  FIG. 3  shows a select signal inversion circuit  350  having inverters INVA-INVC that logically complement select signals SA-SC to generate complementary select signals  SA -  SC , respectively. Although not shown for simplicity, inverters INVA-INVC include power terminals coupled to VDDL and ground potential, and therefore signals  SA -  SC  have logic “1” values equal to VDDL. Thus, although depicted in the exemplary embodiment of  FIG. 3  as part of MUX circuit  300 , for actual embodiments, inversion circuit  350  may be formed within the low-voltage domain  150  of IC device  140 . 
   MUX  310 , which is one embodiment of MUX  210  of  FIG. 2 , is implemented as a standard binary multiplexer that selectively provides one of input signals IN 0 -IN 7  as IN to node A in response to select signals SA-SC. Inversion circuit  330 , which is one embodiment of inversion circuit  230  of  FIG. 2 , is shown to include eight inverters that logically complement IN 0 -IN 7  to generate  IN 0   -  IN 7   , respectively, although other well-known circuitry may be used to implement inversion circuit  330 . MUX  320 , which is one embodiment of MUX  220  of  FIG. 2 , is implemented as a standard binary multiplexer that selectively provides one of complemented input signals  IN 0   -  IN 7    as  IN  to node B in response to select signals SA-SC. Because the architecture and operation of MUXes  310  and  320  are similar to the well-known MUX circuit  110  of  FIG. 1 , a detailed description thereof is not repeated herein for brevity. 
   Output circuit  340 , which is one embodiment of output circuit  240  of  FIG. 2 , includes cross-coupled PMOS pull-up transistors  341 - 342  and inverters  343 - 344 . More specifically, pull-up transistor  341  is coupled between VDDH and node A, and has a gate coupled to node B. Pull-up transistor  342  is coupled between VDDH and node B, and has a gate coupled to node A. Inverter  343 , which has power terminals coupled to VDDH and ground potential and may be a CMOS inverter, includes an input coupled to node A and includes an output to generate an output signal OUT. Inverter  344 , which has power terminals coupled to VDDH and ground potential and may be a CMOS inverter, includes an input coupled to node B and includes an output to generate a complementary output signal  OUT . For other embodiments, pull-up transistors  341  and  343  may be eliminated from output circuit  340 . 
   In operation, select signals SA-SC select one of input signals IN 0 -IN 7  to be propagated through MUX  310  as IN to node A, and also select a corresponding one of complemented input signals  IN 0   -  IN 7    to be propagated through MUX  320  as  IN  to node B. For example, if SA-SC are all driven to logic high (e.g., to VDDL), and IN 0  has a logic “1” value of VDDH, the logic high states of SA-SC turn on NMOS pass transistors MA 0 , MB 0 , and MC 0 , respectively, thereby propagating the logic “1” value of IN 0  through pass transistors MA 0 , MB 0 , and MC 0  as IN to node A. Because the gates of pass transistors are driven by logic “1” voltages of VDDL, the resultant logic high state of IN at node A is approximately VDDL−Vth. The logic high voltages of SA-SC also turn on NMOS pass transistors MA 8 , MB 4 , and MC 2 , thereby propagating the logic “0” value of  IN 0    through pass transistors MA 8 , MB 4 , and MC 2  as  IN  to node B. The logic low state of  IN  at node B triggers inverter  344 , which drives  OUT  high to VDDH. The logic low state of  IN  at node B also turns on pull-up transistor  341 , which pulls the voltage of IN at node A from VDDL−Vth to VDDH. In response thereto, inverter  343  drives OUT low to ground potential. The logic high state of IN at node A also turns off pull-up transistor  342 , thereby isolating node B from VDDH. 
   The differential operation of circuit  300  is advantageous for several reasons. First, because a selected input signal and its complement are always selected by SA-SC to propagate through MUXes  310  and  320  to reach nodes A and B, the logic “0” of the selected signal pair will propagate through the NMOS pass gates in the multiplexer circuit without any voltage drop, thereby triggering its output inverter to drive the output signal high to VDDH and turning on the PMOS pull-up transistor in the complementary signal path to restore the logic “1” of the complemented signal to VDDH to trigger that output inverter to drive its output signal low to ground potential. In this manner, the low-voltage select signals SA-SC may be used to select one of the high-voltage input signals IN 0 -IN 7  to be output from circuit  300  as a high-voltage complementary pair OUT and  OUT . Further, by restoring the voltage of a logic “1” signal at an input of output circuit  340  from VDDL−Vth to VDDH, the PMOS pull-up transistor (not shown for simplicity) in the corresponding CMOS inverter  343 / 344  is completely turned off, thereby eliminating short circuits between VDDH and ground potential through the corresponding inverter  343 / 344 . 
   For other embodiments, a first gain stage similar to output circuit  340  may be added between the second and third hierarchical levels of MUX  310 , and a second gain stage similar to output circuit  340  may be added between the second and third hierarchical levels of MUX  320 , thereby increasing the strength of the signals provided to transistors MC 0 -MC 1  and increasing the strength of the complementary signals provided to transistors MC 2 -MC 3 . 
     FIG. 4  shows IC device  140  including a pseudo-differential multiplexer circuit  400  in accordance with second embodiments of the present invention. MUX circuit  400  includes all the elements of circuit  200  of  FIG. 2 , with the addition of a level-shifting decoder circuit  450 . Decoder circuit  450 , which has power terminals coupled to VDDH and ground potential, includes an input to receive low-voltage select signals SA-SC and includes an output to generate high-voltage decoded select signals SEL_DEC. In this manner, the decoded signals SEL_DEC are high-voltage signals that have logic “1” values of approximately VDDH. Therefore, because the gates of the NMOS pass transistors within MUXes  210  and  220  are driven by logic “1” values of VDDH, rather than VDDL, the propagation delay of logic high signals IN 0 -IN 7  through MUX  210  and the propagation delay of logic high signals  IN 0   -  IN 7    through MUX  220  may be reduced, for example, as compared to the exemplary embodiments of MUX circuit  200  of  FIG. 2 . Further, driving the NMOS pass gates within MUXes  210  and  220  with logic “1” values of VDDH (e.g., instead of VDDL) increases the resultant voltage of logic “1” states of IN and  IN , which in turn may reduce the charging times of nodes A and B. In addition, decoding the encoded select signals SA-SC to generate SEL_DEC may reduce the number of transistors needed to implement MUXes  210  and  220  of MUX circuit  400 , for example, as compared to MUX circuit  200  of  FIG. 2 , thereby conserving valuable circuit area and reducing the number of gate delays in the MUX circuit. 
     FIG. 5  shows a MUX circuit  500  that is one embodiment of MUX circuit  400  of  FIG. 4 . Circuit  500  is shown to include a first MUX  510  having a first portion  510   a  and a second portion  510   b , a second MUX  520  having a first portion  520   a  and a second portion  520   b , input signal inversion circuit  330 , output circuit  340 , and a level-shifting decoder circuit  550 . As mentioned above with respect to  FIG. 2 , select signals SA-SC are received from low-voltage domain  150  and thus have logic “1” values equal to VDDL. Although not shown for simplicity, inverter INVA has power terminals coupled to VDDL and ground potential, and therefore  SA  has a logic “1” value equal to VDDL. Thus, although depicted in  FIG. 5  as part of MUX circuit  500 , for actual embodiments, INVA may be provided within the low-voltage domain  150  of the IC device. 
   Level-shifting decoder circuit  550  includes inputs to receive encoded select signals SB-SC, and includes outputs to generate level-shifted decoded select signals LS 0 -LS 3 . Together, LS 0 -LS 3 , SA, and  SA  form the decoded signals SEL_EN. Thus, although not shown in  FIG. 5  for simplicity, decoder circuit  550  has power terminals coupled to VDDH and ground potential, and therefore the logic “1” values of decoded select signals LS 0 -LS 3  output from decoder circuit  550  are equal to approximately VDDH. In this manner, decoder circuit  550  level-shifts low-voltage signals SB-SC received from the low-voltage domain  150  to generate high-voltage decoded select signals LS 0 -LS 3 . For other embodiments, level-shifting decoder circuit  550  may be modified to receive low-voltage select signal SA and configured to generate a high-voltage select signal SA and a high-voltage complementary signal  SA , for example, so that signals SA,  SA , and LS 0 -LS 3  all have logic “1” values of approximately VDDH. 
   MUXes  510   a - 510   b , which together form another embodiment of MUX  210  of  FIGS. 2 and 4 , selectively provide one of input signals IN 0 -IN 7  as IN to node A in response to select signals SA-  SA  and decoded select signals LS 0 -LS 3 . MUX  510   a  is similar in architecture and operation to the first hierarchical level of MUX  310  of  FIG. 3 , for example, in that NMOS transistor pairs MA 0 -MA 1 , MA 2 -MA 3 , MA 4 -MA 5 , and MA 6 -MA 7  receive input signal pairs IN 0 -IN 1 , IN 2 -IN 3 , IN 4 -IN 5 , and IN 6 -IN 7 , respectively, and are coupled to internal MUX terminals T 0 -T 3 , respectively. Further, within each transistor pair in the first hierarchical level  510   a , the gate of one transistor is controlled by SA and the gate of the other transistor is controlled by  SA . Thus, for the exemplary embodiment of  FIG. 5 , transistors MA 0 , MA 2 , MA 4 , and MA 6  are controlled by SA, and transistors MA 1 , MA 3 , MA 5 , and MA 7  are controlled by  SA . MUX  510   b  includes a single hierarchical level of four NMOS transistors MB 0 -MB 3 , each of which is coupled between a corresponding pair of transistors in first-level MUX  510   a  and node A and has a gate to receive a corresponding one of level-shifted decoded select signals LS 0 -LS 3 . Thus, for the exemplary embodiment of  FIG. 5 , pass transistor MB 0  is coupled between internal terminal T 0  and node A, and has a gate to receive LS 0 ; pass transistor MB 1  is coupled between internal terminal T 1  and node A, and has a gate to receive LS 1 ; pass transistor MB 2  is coupled between internal terminal T 2  and node A, and has a gate to receive LS 2 ; and pass transistor MB 3  is coupled between internal terminal T 3  and node A, and has a gate to receive LS 3 . 
   MUXes  520   a - 520   b , which together form another embodiment of MUX  220  of  FIGS. 2 and 4 , selectively provide one of complemented input signals  IN 0   -  IN 7    as  IN  to node B in response to select signals SA-  SA  and decoded select signals LS 0 -LS 3 . MUX  520   a  is similar in architecture and operation to the first hierarchical level of MUX  320  of  FIG. 3 , for example, in that NMOS transistor pairs MA 8 -MA 9 , MA 10 -MA 11 , MA 12 -MA 13 , and MA 14 -MA 15  receive input signal pairs  IN 0   -  IN 1   ,  IN 2   -  IN 3   ,  IV 4   -  IN 5   , and  IN 6   -  IN 7   , respectively, and are coupled to internal MUX terminals T 4 -T 7 , respectively. Further, within each transistor pair in the first hierarchical level  520   a , the gate of one transistor is controlled by SA and the gate of the other transistor is controlled by  SA . Thus, for the exemplary embodiment of  FIG. 5 , transistors MA 8 , MA 10 , MA 12 , and MA 14  are controlled by SA, and transistors MA 9 , MA 11 , MA 13 , and MA 15  are controlled by  SA . MUX  520   b  includes a single hierarchical level of four NMOS transistors MB 4 -MB 7 , each of which is coupled between a corresponding pair of transistors in first-level MUX  520   a  and node B and has a gate to receive a corresponding one of level-shifted decoded select signals LS 0 -LS 3 . Thus, for the exemplary embodiment of  FIG. 5 , pass transistor MB 4  is coupled between internal terminal T 4  and node B, and has a gate to receive LS 0 ; pass transistor MB 5  is coupled between internal terminal T 5  and node B, and has a gate to receive LS 1 ; pass transistor MB 6  is coupled between internal terminal T 6  and node B, and has a gate to receive LS 2 ; and pass transistor MB 7  is coupled between internal terminal T 7  and node B, and has a gate to receive LS 3 . 
   As mentioned above, level-shifting decoder circuit  550  receives low-voltage encoded select signals SB-SC (e.g., having logic “1” values of VDDL) and in response thereto generates four high-voltage decoded select signals LS 0 -LS 3  (e.g., having logic “1” values of VDDH) that select one of the four possible intermediate signals in each of second-level MUX circuits  510   b  and  520   b . Decoder circuit  550  may employ any suitable combinational logic circuitry to generate LS 0 -LS 3  in response to SB-SC. For some embodiments, the logical relationship between SB-SC and LS 0 -LS 3  is as shown below in Table 1, although other relationships between SB-SC and LS 0 -LS 3  may be employed for other embodiments. 
   
     
       
             
             
             
             
             
             
             
           
         
             
                 
               TABLE 1 
             
             
                 
                 
             
             
                 
               SB 
               SC 
               LS0 
               LS1 
               LS2 
               LS3 
             
             
                 
                 
             
           
           
             
                 
               0 
               0 
               1 
               0 
               0 
               0 
             
             
                 
               0 
               1 
               0 
               1 
               0 
               0 
             
             
                 
               1 
               0 
               0 
               0 
               1 
               0 
             
             
                 
               1 
               1 
               0 
               0 
               0 
               1 
             
             
                 
                 
             
           
        
       
     
   
   For example, referring again to  FIG. 5 , if SA is driven to “1,” SB is driven to “1,” and SC is driven to “0,” input signals IN 4  and  IN 4    are provided as IN and  IN  to nodes A and B, respectively. More specifically, the logic “1” state of SA turns on pass transistors MA 0 , MA 2 , MA 4 , MA 6 , MA 8 , MA 10 , MA 12 , and MA 14 . Driving SB to logic “1” and driving SC to logic “0” causes decoder circuit  550  to drive LS 0 , LS 1 , and LS 3  to logic “0” and to drive LS 2  to logic “1.” The logic high state of LS 2  turns on NMOS pass transistors MB 2  and MB 6 , which in turn propagate IN 4  as IN to node A and propagate  IN 4    as  IN  to node B. Assuming that IN 4  is logic high and that  IN 4    is logic low, the voltage at node A should be equal to VDDH−Vth, and the voltage at node B should be approximately 0 volts. The logic low voltage at node B causes inverter  344  to drive  OUT  high to VDDH, and also turns on pull-up transistor  341 , which pulls node A higher to VDDH (e.g., from VDDH−Vth). The high voltage at node A causes inverter  343  to drive OUT low to ground potential, and also turns off pull-up transistor  342  to isolate node B from VDDH. For other embodiments, pull-up transistors  341  and  343  may be eliminated from output circuit  340  of  FIG. 5 . 
   As mentioned above, to select one of input signals IN 0 -IN 7 , decoder circuit  550  asserts only one of LS 0 -LS 3  to logic “1” and de-asserts the remaining decoded select signals to logic “0,” thereby enabling only one of the four paths in each of MUX circuits  510   b  and  520   b . The remaining three paths in both MUX circuits  510   b  and  520   b  are cut-off by applying a zero voltage to the corresponding NMOS pass gates, thereby advantageously preventing leakage current in circuit  500 . Further, by encoding select signals SB-SC to generate decoded select signals LS 0 -LS 3  that control the NMOS transistors MB 0  and MB 4 , MB 1  and MB 5 , MB 2  and MB 6 , and MB 3  and MB 7 , respectively, the circuit  500  of  FIG. 5  may operate using only two hierarchical levels of pass gates, for example, as compared to MUX circuit  300  of  FIG. 3 , which requires three hierarchical levels of pass gates, thereby reducing the number of gate delays through MUX circuit  500 . Further, because the selected paths in MUXes  510   b  and  520   b  are driven by a logic high value of VDDH, voltage drops and propagation delays through MUXes  510   b  and  520   b  are minimized. 
     FIG. 6  is a functional block diagram of an exemplary embodiment  600  of level-shifting decoder circuit  500  that implements the logic functions summarized in Table 1 above. Circuit  600  includes four logical AND gates  610 - 613 , where AND gate  610  includes inputs to receive  SB  and  SC  and includes an output to generate LS 0 , AND gate  611  includes inputs to receive  SB  and SC and includes an output to generate LS 1 , AND gate  612  includes inputs to receive SB and  SC  and includes an output to generate LS 2 , and AND gate  613  includes inputs to receive SB and SC and includes an output to generate LS 3 . Thus, AND gate  610  asserts LS 0  to logic “1” only if both  SB  and  SC  are logic “1”, AND gate  611  asserts LS 1  to logic “1” only if both  SB  and SC are logic “1,” AND gate  612  asserts LS 2  to logic “1” only if both SB and  SC  are logic “1”, and AND gate  613  asserts LS 3  to logic “1” only if both SB and SC are logic “1.” 
   Of course, for other embodiments, the AND gates  610 - 613  of circuit  600  may receive other SB/SC signal pairs to implement logic functions of LS 0 -LS 3  from SB-SC that are different from the exemplary logic function depicted in Table 1, as will be apparent to one skilled in the art after reading this disclosure. Further, for other embodiments, logic gates other than AND gates may be used to generate LS 0 -LS 3  in response to SB-SC. 
     FIG. 7  shows an exemplary differential level-shifting AND gate  700  that may be used to implement AND gates  610 - 613  of  FIG. 6 . AND gate  700 , which is configured to generate an AND function of its input signals while performing a level-shifting function, includes cross-coupled PMOS transistors  701 - 702  and NMOS pull-down transistors  703 - 706 . PMOS transistor  701  is connected between VDDH and OUT and has a gate coupled to  OUT , and PMOS transistor  702  is connected between VDDH and  OUT , and has a gate coupled to OUT. NMOS transistor  703  is coupled between OUT and ground potential, and has a gate to receive the complement of a first select signal (  S 1   ). NMOS transistor  704  is coupled between OUT and ground potential, and has a gate to receive the complement of a second select signal (  S 2   ). NMOS transistors  705 - 706  are coupled in series between  OUT  and ground potential, with the gate of transistor  705  receiving the first select signal (S 1 ) and the gate of transistor  706  receiving the second select signal (S 2 ). The differential input signals S 1 -  S 1    and S 2 -  S 2    are low-voltage signals having logic “1” values equal to VDDL, and the differential output signal OUT-  OUT  is a high-voltage signal having a logic “1” value equal to VDDH. 
   Circuit  700  is advantageous because it is capable of level-shifting low-voltage select signals S 1 -S 2  to generate high-voltage differential output signals OUT and  OUT  while preventing short circuits between VDDH and ground potential, regardless of the voltage of VDDL. For one example, if S 1  is logic “1” and S 2  is logic “0,” NMOS pull-down transistor  706  completely turns off, thereby preventing a current path from VDDH to ground potential through transistors  705 - 706 . The resultant logic “1” value of  S 2    turns on NMOS transistor  704 , which pulls OUT low towards ground potential. The resultant logic low state of OUT turns on PMOS transistor  702 , which pulls  OUT  high towards VDDH. The high voltage at  OUT  completely turns off PMOS transistor  701 , thereby isolating OUT from VDDH and preventing a short circuit between VDDH and ground potential through transistor  701 . For another example, if S 1  and S 2  are both logic “1,” NMOS pull-down transistors  705 - 706  turn on, thereby pulling  OUT  low to ground potential. The resultant logic low state of  OUT  turns on PMOS transistor  701 , which pulls OUT high towards VDDH. The resultant logic high state of OUT completely turns off PMOS transistor  702 , thereby isolating  OUT  from VDDH and preventing a short circuit path between VDDH and ground potential through transistor  702 . The resultant logic “0” values of  S 1    and  S 2    turn off NMOS transistors  703  and  704 , respectively, thereby preventing a short circuit between VDDH and ground potential through transistor  701 . 
   As mentioned above, circuit  700  may be used to implement any of AND gates  610 - 613  of  FIG. 6 . For one example, circuit  700  may be used to implement the first AND gate  610  of  FIG. 6  by coupling SB to the gate of transistor  703 , coupling SC to the gate of transistor  704 , coupling  SB  to the gate of transistor  705 , and coupling  SC  to the gate of transistor  706 , wherein OUT provides LS 0 . Thus, if  SB  and  SC  are logic “0,” the resultant logic “1” states of SB and SC turn on NMOS pull-down transistors  703 - 704  and pull OUT low to ground potential, thereby driving LS 0  to logic “0.” However, if  SB  and  SC  are logic “1,” NMOS pull-down transistors  705 - 706  turn on and pull  OUT  low to ground potential, which turns on pull-up transistor  701  and pulls OUT high to VDDH, thereby driving LS 0  to logic “1,” as summarized in Table 1. 
     FIG. 8  shows a MUX circuit  800  that is another embodiment of MUX circuit  400  of  FIG. 4 . Circuit  800  is shown to include a first MUX  810  having a first portion  810   a  and a second portion  810   b , a second MUX  820  having a first portion  820   a  and a second portion  820   b , inversion circuit  330 , output circuit  340 , and level-shifting decoder circuit  550 . As mentioned above with respect to  FIG. 2 , select signals SA-SC are received from a low-voltage domain, and thus SA-SC have logic “1” values equal to VDDL. Although not shown for simplicity, inverter INVC has power terminals coupled to VDDL and ground potential, and therefore  SC  has a logic “1” value equal to VDDL. Thus, although depicted in  FIG. 8  as part of MUX circuit  800 , for actual embodiments, INVC may be provided within the low-voltage domain  150  of the IC device. 
   Level-shifting decoder circuit  550  includes inputs to receive SA-SB, and includes outputs to generate level-shifted decoded select signals LS 0 -LS 3 , which together form SEL_DEC. Thus, although not shown in  FIG. 8  for simplicity, decoder circuit  550  has power terminals coupled to VDDH and ground potential, and therefore the logic “1” values of select signals LS 0 -LS 3  output from decoder circuit  550  are equal to approximately VDDH. In this manner, decoder circuit  550  level-shifts low-voltage signals SA-SB received from the low-voltage domain  150  to generate high-voltage decoded select signals LS 0 -LS 3 . For other embodiments, level-shifting decoder circuit  550  may be modified to receive low-voltage select signal SC and configured to generate a high-voltage select signal SC and a high-voltage complementary signal  SC , for example, so that signals SC,  SC , and LS 0 -LS 3  all have logic “1” values of approximately VDDH. 
   MUXes  810   a - 810   b , which together form another embodiment of MUX  210  of  FIGS. 2 and 4 , selectively provide one of input signals IN 0 -IN 7  to node A in response to select signals SC,  SC , and LS 0 -LS 3 . MUX  810   a  includes a single hierarchical level of eight NMOS transistors MA 0 -MA 7  that receive input signals IN 0 -IN 7 , respectively, where the gates of pass transistors MA 0  and MA 4  receive LS 0 , the gates of pass transistors MA 1  and MA 5  receive LS 1 , the gates of pass transistors MA 2  and MA 6  receive LS 2 , and the gates of pass transistors MA 3  and MA 7  receive LS 3 . MUX  810   b  is similar in architecture and operation to the third hierarchical level of MUX  310  of  FIG. 3  in that for the NMOS transistor pair MC 0 -MC 1 , transistor MC 0  receives one of IN 0 -IN 3  from internal terminal T 0  as an intermediate signal and is controlled by SC, and transistor MC 1  receives one of IN 4 -IN 7  from internal terminal T 1  as an intermediate signal and is controlled by  SC . 
   MUXes  820   a - 820   b , which together form another embodiment of MUX  220  of  FIGS. 2 and 4 , selectively provide one of input signals  IN 0   -  IN 7    to node B in response to select signals SC,  SC , and LS 0 -LS 3 . MUX  820   a  includes a single hierarchical level of eight NMOS transistors MA 8 -MA 15  that receive complemented input signals  IN 0   -  IN 7   , respectively, where the gates of pass transistors MA 8  and MA 12  receive LS 0 , the gates of pass transistors MA 9  and MA 13  receive LS 1 , the gates of pass transistors MA 10  and MA 14  receive LS 2 , and the gates of pass transistors MA 11  and MA 15  receive LS 3 . MUX  820   b  is similar in architecture and operation to the third hierarchical level of MUX  320  of  FIG. 3  in that for the NMOS transistor pair, transistor MC 2  receives one of  IN 0   -  IN 3    as an intermediate signal from internal terminal T 2  and is controlled by SC, and transistor MC 3  receives one of  IN 4   -  IN 7    as an intermediate signal from internal terminal T 3  and is controlled by  SC . 
   As mentioned above, level-shifting decoder circuit  550  receives low-voltage encoded select signals SA-SB (e.g., having logic “1” values of VDDL) and in response thereto generates four high-voltage decoded select signals LS 0 -LS 3  (e.g., having logic “1” values of VDDH) that select two of the eight possible signal paths in each of first-level MUX circuits  810   a  and  820   a . In this manner, voltage drops and propagation delays through MUXes  810   a  and  820   b  are minimized. The encoded select signal pair SC and  SC  select one of the intermediate signals from each MUX  810   a  and  810   b  for output to output circuit  340 . Further, by encoding select signals SA-SB to generate decoded select signals LS 0 -LS 3  that control the NMOS transistors MA 0 -MA 15 , the circuit  800  of  FIG. 8  may operate using only two hierarchical levels of pass gates, thereby reducing the number of gate delays through the multiplexer circuit, for example, as compared to the MUX circuit  300  of  FIG. 3 , which requires three hierarchical levels of pass gates, thereby reducing the number of gate delays through MUX circuit  800 . 
   The embodiment of  FIG. 8  is advantageous over the embodiment of  FIG. 5  for applications in which select signal SC involves a critical timing path. 
   Decoder circuit  550  may employ any suitable combinational logic circuitry to generate LS 0 -LS 3  in response to SA-SB. For some embodiments, the logical relationship between SA-SB and LS 0 -LS 3  is as shown below in Table 2, although other relationships between SA-SB and LS 0 -LS 3  may be employed for other embodiments. 
   
     
       
             
             
             
             
             
             
             
           
         
             
                 
               TABLE 2 
             
             
                 
                 
             
             
                 
               SA 
               SB 
               LS0 
               LS1 
               LS2 
               LS3 
             
             
                 
                 
             
           
           
             
                 
               0 
               0 
               1 
               0 
               0 
               0 
             
             
                 
               0 
               1 
               0 
               1 
               0 
               0 
             
             
                 
               1 
               0 
               0 
               0 
               1 
               0 
             
             
                 
               1 
               1 
               0 
               0 
               0 
               1 
             
             
                 
                 
             
           
        
       
     
   
   The logic states of LS 0 -LS 3  may be generated in response to SA-SB using well-known combinational logic circuitry. For some embodiments, the decoder circuit  600  of  FIG. 6  and level-shifting AND gate  700  of  FIG. 7  may be used to generate LS 0 -LS 3  in response to SA-SB. For other embodiments, other circuitry may be used. 
   As described above, embodiments of the present invention may be used to implement LUTs, for example, in the CLBs of an FPGA device. Embodiments of the present invention may also be used to implement signal routing functions, for example, in the switch fabric of FPGA devices. For example,  FIG. 9  shows a MUX circuit  900  that may be used to selectively route input signals IN 0 -IN 7  as OUT and  OUT  in response to SA-SC. MUX circuit  900  is similar in architecture and operation to MUX circuit  300  of  FIG. 3 , except that inverters INVA-INVC of  FIG. 3  are replaced by memory cells  901 - 903 , respectively, in  FIG. 9 . Memory cells  901 - 903 , which may be any suitable memory cells such as, for example, DRAM or SRAM cells, provide select signals SA-SC and their complements  SA -  SC  to MUXes  310  and  320 . For some embodiments, memory cells  901 - 903  are configuration memory cells that control signal routing functions in an FPGA. 
   Memory cells  901 - 903  may be powered by any suitable supply voltage. For an exemplary embodiment, memory cells  901 - 903  are powered by VDDH, and input signals IN 0 -IN 7  are provided by interconnect structure  151  (see also  FIG. 2 ), which is powered by VDDL. 
   While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects, and therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention. For example, although the exemplary embodiments are described above with respect to an 8:1 MUX structure responsive to 3 select signals, it will be apparent to those skilled in the art after reading this disclosure that the teachings of the present invention may be readily applied to MUX architectures having more or fewer than 8 inputs and more or fewer than 3 select terminals.

Technology Category: 5