Patent Document

BACKGROUND OF THE INVENTION 
     This invention relates to inter-level isolation of interconnects in semiconductor devices and more particularly to integration processes for producing very low-k isolation of copper interconnects. 
     Copper interconnects are formed using a dual damascene process. The incorporation of low-k insulator material may be accomplished by depositing a first layer of low-k dielectric material over a copper interconnect. This may be followed by an optional etch stop barrier insulator and then a second layer of low-k material. A via is then etched through the second layer of low-k material, any etch stop barrier insulator, and the first layer of low-k dielectric material to reach the copper interconnect. A trench is then etched into the second layer of low-k material to aid in forming another layer of copper interconnects. Barrier metal and copper are deposited by sputtering, CVD, electrochemical deposition, or a combination of these methods. The deposited copper, and possibly the barrier metal, will then be planarized using CMP to form copper interconnects. 
     Materials having very low dielectric constants, less than approximately 2, tend to have poor mechanical strength. Due to this poor mechanical strength, these materials may not support CMP processes necessary for copper damascene interconnect fabrication. 
     SUMMARY OF THE INVENTION 
     Accordingly, a method of fabricating copper interconnects with very low-k inter-level insulators is provided. A method of forming a low-k inter-level insulator structure is provided comprising the steps of: providing a first metal layer; depositing a sacrificial insulator layer overlying the first metal layer; producing a second metal layer; removing the sacrificial insulator layer; and depositing a low-k inter-level insulator, whereby low-k material replaces the sacrificial insulator. 
     An intermediate insulator layer structure is also provided comprising a sacrificial insulator layer overlying a low-k insulator layer, such that the sacrificial insulator layer may be subjected to processes, including CMP, which may be incompatible with low-k insulator materials. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross sectional view of a low-k inter-level insulator structure after initial processing. 
     FIG. 2 is a cross sectional view of a low-k inter-level insulator structure following photoresist patterning. 
     FIG. 3 is a cross sectional view of a low-k inter-level insulator structure following via and trench formation. 
     FIG. 4 is a cross sectional view of a low-k inter-level insulator structure following metal deposition and polishing. 
     FIG. 5 is a cross sectional view of a low-k inter-level insulator structure following removal of a sacrificial layer and replacement with a low-k insulator material. 
     FIG. 6 is a cross sectional view of a low-k inter-level insulator structure following patterning, and trench/via formation, for an additional metal layer. 
     FIG. 7 is a cross sectional view of a low-k inter-level insulator structure following deposition and polishing of an additional metal layer. 
     FIG. 8 is a cross sectional view of a low-k inter-level insulator structure following removal of another sacrificial layer and replacement 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is shows an interconnect structure  10  following some initial processing. The interconnect structure  10  comprises a substrate  12  following planarization and formation of a first metal layer  14 , which is preferably copper. Although barrier metal is not shown, throughout the figures, for ease of illustration, a barrier metal, such as TiN, TaN, Ti x Ta y N z , or WN, is deposited prior to deposition of copper as necessary, or desired. A passivation insulator  16  is deposited overlying the first metal layer  14  to reduce, or eliminate, copper out diffusion. The passivation layer  16  is preferably SiC, Si x N y , or BN. A first layer of low-k material  18  is deposited overlying the passivation insulator  16 . The first layer of low-k material  18  is preferably a very low-k material such as porous silicon oxide, xergel, or Hydrogensilsesquioxane Resin (HSQ). The first layer of low-k material  18  is preferably deposited by a spin-on process or by CVD to a thickness approximately equal to the desired distance between two metal layers. 
     Preferably, an etch stop insulator  20  is deposited overlying the first layer of low-k material  18 . The etch stop insulator  20  is preferably a material such as SiO 2 , Si 3 N 4 , SiC, or BN. In another embodiment, no etch stop insulator is deposited. 
     A first sacrificial insulator layer  22  is deposited overlying the etch stop insulator  20 . The first sacrificial insulator layer  22  is a material with sufficient mechanical strength to be suitable for CMP and other processes, and generally has a higher dielectric constant than desired for very low-k insulator applications. The first sacrificial insulator layer  22  is preferably silicon nitride (Si 3 N 4 ) or silicon dioxide (SiO 2 ). The first sacrificial insulator layer  22  will preferably have a thickness approximately equal to a desired thickness of a second metal layer, which is to be formed subsequently. For example, the first sacrificial insulator layer  22  may be on the order of approximately 500 nm thick. A hard mask  24  is deposited over the first sacrificial insulator layer  22 . 
     In a preferred embodiment in which no etch stop insulator is deposited, the first sacrificial insulator layer  22  and low-k material are selected to complement each other to provide the ability to selectively etch one versus the other. For example, silicon nitride (Si 3 N 4 ) may be used for the first sacrificial insulator layer  22 , when porous silicon oxide is the low-k material, since they can be selectively etched. Alternatively, if xergel, or HSQ is used for the low-k material either silicon nitride (Si 3 N 4 ) or silicon dioxide may be used as the first sacrificial insulator layer  22 . 
     Referring now to FIG. 2, one or more via openings  26  is etched into the hard mask  24  by applying photoresist and etching. The photoresist is then removed. A second photoresist mask  28  is deposited and patterned. The first sacrificial insulator layer  22  is etched to form a via at the via openings  26 . The etch stop insulator  20  is removed from the bottom of the via formed in the first sacrificial insulator layer. The hard mask  24  is removed from the areas not protected by the second photoresist mask  28 . Preferably, both the etch stop insulator  20  and the hard mask  24  are removed simultaneously. 
     Referring now to FIG. 3, the first sacrificial layer  22  is etched where it is not protected by the second photoresist mask  28  down to the etch stop insulator  20  to form a trench  30 . The first layer of low-k material  18  is also etched, preferably until the passivation insulator  16  is also removed to form a via  32 . Alternatively the passivation insulator  16  can be removed in a separate etch step. Preferably, a single anisotropic etch process can be used to etch the first layer of low-k material  18  and the first sacrificial layer  22  at the same time. After etching the trench  30 , the second photoresist mask  28  can be stripped. Since the etch stop insulator  20  has a higher dielectric constant than the first layer of low-k material, it may be preferable to remove the etch stop insulator  20  from the bottom of the trench  30 . Note that if the etch stop insulator  20  is to be removed, that must be accounted for in terms of the desired distance between metal layers. 
     Following formation of the trenches and vias, barrier metal and copper is deposited. Copper, and possibly barrier metal, is planarized to the level of the first sacrificial layer  22  using CMP to form a second metal layer  34 , as shown in FIG.  4 . The first sacrificial layer  22 , as discussed above, is a material that is chosen because it has the mechanical strength compatible with the CMP process. In addition, the copper lines and vias assist in supporting the first layer of low-k material  18 . The hard mask  24  is also removed before or during the CMP process. 
     The first sacrificial layer  22  is removed. The first sacrificial layer  22  can be removed by either a selective wet etch or selective dry etch process. Since copper will not be etched during oxide or nitride plasma etching, the selective dry etch of the sacrificial insulator  22  can be readily accomplished. It is preferable, to remove any remaining etch stop insulator  20  remaining over the first layer of low-k material  18 , since it has a dielectric constant higher than the low-k material. A second low-k layer  36  is deposited, preferably by a spin-on process, and etched back to expose the second metal layer  34 , as is shown in FIG.  5 . The interconnect structure  10  has an upper surface, at this stage, which is not as flat as would be achieved if CMP were possible with low-k materials. A second passivation insulator  38  is deposited. 
     Referring now to FIG. 6, a third low-k layer  40  is deposited, preferably by spin coating. The third low-k layer  40  is deposited to a thickness equal to, or greater than, the desired distance between the second metal layer  34  and the next metal layer to be formed. The thickness is preferably between approximately 500 nm and 1000 nm. After depositing the third low-k layer  40 , the interconnect structure  10  has an upper surface that is almost as flat as can be achieved by CMP. A second etch stop insulator  42  is deposited followed by a second sacrificial insulator  44 . The second sacrificial insulator  44  is equal to, or slightly thicker than, the desired thickness of the next metal layer to be formed. If it is considered desirable at this stage for the interconnect structure  10  to have a flatter upper surface, a CMP process can be used to polish the second sacrificial insulator  44 . The second sacrificial insulator  44  is capped with a second hard mask  46 . Using a process similar to the one discussed above, a photoresist mask can be used to form via openings in the second hard mask  46  to allow for formation of a second set of vias  48 . An additional photoresist mask can be patterned to allow for formation of a second set of trenches  50 . Following etching, or removal, of the second sacrificial insulator  44 , the third low-k layer  40 , the second etch stop insulator  42 , the second barrier layer  38  and stripping of any remaining photoresist, the interconnection structure  10  similar to that shown in FIG. 6 is achieved. 
     Again barrier metal and copper are deposited, and planarized to form a third metal layer  52 , as shown in FIG.  7 . It may be desirable to leave the second sacrificial insulator  44 , which in this case corresponds to the final sacrificial insulator, with its higher mechanical strength, as the final insulator if desirable to support the interconnect structure  10  during subsequent packaging processes. It may also be preferable to leave a sacrificial insulator between some of the low-k layers to provide additional mechanical support for devices with larger numbers of metal layers. 
     Alternatively, as shown in FIG. 8, the second sacrificial layer could be removed and replaced by a fourth low-k layer  54 . It would also be possible to remove any remaining portion of the second etch stop insulator  42  or the second barrier layer  38 . A third barrier layer  56  could then be formed and the process repeated as desired to form additional metal layers with low-k insulating material. 
     Although preferred embodiments along with some alternatives have been described, the invention is not limited to any specific embodiment. Rather, the scope of the invention is determined based upon the following claims.

Technology Category: 5