Patent Document

CROSS REFERENCES TO RELATED APPLICATIONS  
       [0001]     This application claims priority to and the benefit of Korean Patent Application Nos. 10-2004-0050669, 10-2004-0050670 and 10-2004-0050671 filed in the Korean Intellectual Property Office on the same day of Jun. 30, 2004, the entire contents of all of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a light emitting display. More specifically, the present invention relates to an organic light emitting diode (OLED) display including a test pad.  
         [0004]     2. Discussion of the Related Art  
         [0005]     In general, a flat panel display (FPD) is a display device in which walls are provided between two substrates to manufacture an airtight device, and appropriate elements are arranged in the airtight device to display desired images. The importance of the FPD has been emphasized following the development of multimedia technologies. In response to this trend, various flat displays such as the liquid crystal display (LCD), the organic light emitting diode (OLED) display, and the field emission display (FED) have been put to practical use. In particular, the OLED display including an organic light emitting diode has been developed.  
         [0006]     Generally, OLED displays emit light by electrically exciting an organic compound. An OLED display includes N×M organic light emitting cells arranged in the form of a matrix, and displays an image by driving the organic light emitting cells, using voltage or current. Such organic light emitting cells are also referred to as “organic light emitting diodes (OLEDs)” because they have diode characteristics. As shown in  FIG. 15 , an organic light emitting cell (or OLED) has a structure including an anode electrode layer (e.g., indium tin oxide: ITO), an organic layer, and a cathode electrode (e.g., metal) layer. To achieve an improved balance between electrons and holes, and thus, an enhancement in light emitting efficiency, the organic layer has a multi-layer structure including an emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL). The organic layer also includes an electron injecting layer (EIL) and a hole injecting layer (HIL). Several organic light emitting cells are arranged in the form of an M×N matrix to form an OLED display panel.  
         [0007]     Methods for driving an OLED display panel include a passive matrix type driving method and an active matrix type driving method using thin film transistors (TFTs). In the passive matrix type driving method, anodes and cathodes are arranged to be orthogonal to each other so that a desired line to be driven can be selected. In the active matrix type driving method, thin film transistors are coupled to respective indium tin oxide (ITO) pixel electrodes in an OLED display panel so that the OLED display panel is driven by a voltage maintained by the capacitance of a capacitor coupled to the gate of each thin film transistor.  
         [0008]      FIG. 1  shows a pixel circuit of an OLED display to be driven by the passive matrix type driving method.  
         [0009]     The pixel circuit of the OLED display includes an organic light emitting cell OLED, two transistors SM and DM, and a capacitor Cst. A power voltage VDD is coupled to a source of the driving transistor DM, and a capacitor is coupled between the source and a gate of the transistor DM. The capacitor Cst maintains a gate-source voltage V GS  of the driving transistor DM for a predetermined period. The switching transistor SM transmits a data voltage from a data line D m  to the gate of the transistor DM with response to a selection signal from a present scan line S n . A cathode of the cell OLED is coupled to a reference voltage Vss, and the cell OLED emits a light corresponding to a current applied through the driving transistor DM.  
         [0010]     The conventional OLED display has a configuration in which a high density integrated circuit is coupled to an array substrate in which pixels are arranged using a tape automated bonding (TAB) method. In the conventional OLED display in which the driving circuit is coupled to the array substrate using the TAB method, multiple leads for coupling the array substrate to the driving circuit are required; therefore, it is difficult to manufacture the conventional OLED display, and reliability of the display may be reduced. In addition, the cost of the conventional OLED display is high because of the high cost of the high-density integrated circuit.  
         [0011]     Accordingly, an OLED display including a driving circuit directly accumulated on a pixel array substrate in which a pixel circuit is arranged has been developed. The OLED display manufactured by directly accumulating the driving circuit to the pixel array substrate is referred to as a chip on glass (COG) type OLED display or a system on panel (SOP) type OLED display. The reliability of the product is increased in the COG or SOP type OLED display because the additional process of coupling the driving circuit to the pixel array substrate is not necessary.  
         [0012]     Typically, it is not difficult to test an operation of a driving circuit when the driving circuit uses an additional high-density integrated circuit. However, it is difficult to test an operation of a driving circuit when the driving circuit is accumulated on the substrate of a COG or SOP type OLED display.  
       SUMMARY OF THE INVENTION  
       [0013]     An embodiment of the present invention provides a chip on glass (COG) type light emitting or OLED display with a test pad coupled to an output terminal of a driving circuit of the display in order to test the driving circuit.  
         [0014]     One embodiment of the present invention provides a light emitting display. The light emitting display includes: a display area including a plurality of scan lines for transmitting selection signals, a plurality of data lines for transmitting data signals, and a plurality of pixels arranged in a matrix format and respectively coupled to the scan lines and the data lines, the display area being formed on a same substrate; a scan driver for generating the selection signals and respectively applying the selection signals to the scan lines, the scan driver being formed on the same substrate; and a data driver for generating the data signals and for respectively applying the data signals to the data lines, the scan driver being formed on the same substrate.  
         [0015]     In this embodiment, the data driver includes: a shift register for generating shift signals shifted to sequentially have a first level and for outputting the shift signals through a plurality output terminals; a plurality of test pads respectively coupled to the plurality of output terminals of the shift register; and a demultiplexer for selectively applying the data signals input through a plurality of data buses to the data lines in response to the first level of the shift signals.  
         [0016]     One embodiment of the present invention provides a light emitting display. The light emitting display includes: a plurality of scan lines for transmitting selection signals; a plurality of data lines for transmitting data signals; a plurality of pixels respectively coupled to the scan lines and the data lines, and arranged in a matrix format; and a data driver for generating the data signals and for respectively applying the data signals to the data lines.  
         [0017]     In this embodiment, the data driver includes: a shift register for generating shift signals shifted to sequentially have a first level and for outputting the shift signals; a buffering unit for buffering the shift signals output from the shift register, the buffering unit comprising a plurality of output terminals for outputting the buffered shift signals; and a test pad coupled to each of the output terminals of the buffering unit.  
         [0018]     One embodiment of the present invention provides a data driver for forming on a pixel array substrate in which a pixel displaying an image data with reference to a data signal applied through a data line is arranged in a matrix format with a plurality of other pixels. The data driver includes: a shift register for generating a plurality of shift signals shifted to sequentially have a first level and for outputting the shift signals; a buffering unit including a plurality of buffering circuits for receiving the plurality of shift signals output from the shift register, the buffering unit being for buffering the shift signals and for outputting the shift signals, the plurality of buffering circuits comprising a plurality of output terminals; a test pad formed to be coupled to each of the output terminals of the plurality of buffering circuits; and a demultiplexer for selectively applying the data signal input through at least one of a plurality of data buses to the data line in response to the first level of at least one of the plurality of shift signals output from the buffering unit.  
         [0019]     One embodiment of the present invention provides a light emitting display. The light emitting display includes: a display area including a plurality of scan lines for transmitting selection signals, a plurality of data lines for transmitting data signals, and a plurality of pixels arranged in a matrix format and respectively coupled to the scan lines and the data lines, the display area being formed on a same substrate; a scan driver for generating the selection signals and for respectively applying the selection signals to the scan lines, the scan driver being formed on the same substrate; and a data driver for generating the data signals and for respectively applying the data signals to the data lines, the scan driver being formed on the substrate.  
         [0020]     In this embodiment, the data driver includes: a shift register for generating a plurality of shift signals shifted to sequentially have a first level and for respectively outputting the shift signals through a plurality of output terminals of the shift register; a demultiplexer for selectively applying the data signal input through a plurality of data buses to the data lines through a plurality of output terminals of the demultiplexer in response to the first level of the shift signal; and a plurality of test pads formed to be coupled between the output terminals of the demultiplexer and the data lines.  
         [0021]     One embodiment of the present invention provides a data driver for forming on a pixel array substrate in which a pixel displaying an image data with reference to a data signal applied through a data line is arranged in a matrix format with a plurality of other pixels. The data driver includes: a shift register for generating a plurality of shift signals shifted to sequentially have a first level and for respectively outputting the shift signals; a buffering unit including a plurality of buffering circuits for receiving the plurality of shift signals output from the shift register, the buffering unit being for buffering the shift signals and for outputting the shift signals; a demultiplexer for selectively applying the data signal input through at least one of a plurality of data buses to the data line through at least one of a plurality of output terminals of the demultiplexer in response to the first level of the shift signal output from the buffering unit; and a test pad formed to be coupled to the output terminals of the demultiplexer.  
         [0022]     One embodiment of the present invention provides a light emitting display. The light emitting display includes: a display area including a plurality of scan lines for transmitting selection signals, a plurality of data lines for transmitting data signals, and a plurality of pixels arranged in a matrix format and respectively coupled to the scan lines and the data lines, the display area being formed on a substrate; a scan driver for generating the selection signals and for respectively applying the selection signals to the scan lines, the scan driver being formed on the substrate; and a data driver for generating the data signals and for applying the data signals to the data lines, the scan driver being formed on the substrate.  
         [0023]     In this embodiment, the scan driver includes: a shift register for generating the selection signals shifted to sequentially have a first level and for respectively outputting the selection signals through a plurality of output terminals; and a plurality of test pads formed to be coupled to the plurality of output terminals of the shift register.  
         [0024]     One embodiment of the present invention provides a light emitting display. The light emitting display includes: a plurality of scan lines for transmitting selection signals; a plurality of data lines for transmitting data signals; a plurality of pixels respectively coupled to the scan lines and the data lines, and arranged in a matrix format; and a scan driver for generating the selection signals and for applying the selection signals to the scan lines.  
         [0025]     In this embodiment, the scan driver includes: a shift register for generating the selection signals shifted to sequentially have a first level and for respectively outputting the selection signals through a plurality of output terminals; and a plurality of test pads formed to be respectively coupled to the plurality of output terminals of the shift register. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]     The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the invention.  
         [0027]      FIG. 1  shows a pixel circuit driven by a passive matrix type driving method.  
         [0028]      FIG. 2  shows a configuration of an OLED display according to an exemplary embodiment of the present invention.  
         [0029]      FIG. 3  shows a configuration of the data driver of  FIG. 2 .  
         [0030]      FIG. 4  shows a detailed diagram for representing the configuration of the data driver of  FIG. 3  according to a first exemplary embodiment of the present invention.  
         [0031]      FIG. 5  shows a detailed diagram for representing the buffering circuit, and the test pad provided to the output terminal of the buffering circuit of  FIG. 4 .  
         [0032]      FIG. 6  shows a configuration in which an area A (shown in  FIG. 5 ) of the test pad and the buffering unit of  FIG. 5  is arranged on a substrate.  
         [0033]      FIG. 7  shows a cross-sectional view of the test pad taken along the line I-I′ of  FIG. 6 .  
         [0034]      FIG. 8  shows a detailed diagram for representing the switching circuit, and a test pad provided to the output terminal of the switching circuit of  FIG. 4  according to a second exemplary embodiment of the present invention.  
         [0035]      FIG. 9  shows a configuration in which an area A′ of the test pad and the buffering unit of  FIG. 8  is arranged on the substrate.  
         [0036]      FIG. 10  shows a cross-sectional view of the test pad taken along the line II-II′ of  FIG. 9 .  
         [0037]      FIG. 11  schematically shows a configuration of the scan driver according to a third exemplary embodiment of the present invention.  
         [0038]      FIG. 12  shows a configuration of the shift register of  FIG. 11 .  
         [0039]      FIG. 13  shows a configuration in which an area A″ of  FIG. 12  is arranged.  
         [0040]      FIG. 14  shows a cross-sectional view of a part taken along the line III-III′ of  FIG. 13 .  
         [0041]      FIG. 15  schematically shows a structure of an organic light emitting cell. 
     
    
     DETAILED DESCRIPTION  
       [0042]     In the following detailed description, exemplary embodiments of the present invention are shown and described, by way of illustration. As those skilled in the art would recognize, the described exemplary embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, rather than restrictive. There may be parts shown in the drawings, or parts not shown in the drawings, that are not discussed in the specification, as they are not essential to a complete understanding of the invention. Like reference numerals designate like elements.  
         [0043]      FIG. 2  shows a configuration of an OLED display according to an exemplary embodiment of the present invention. The OLED display includes a data driver  200 , a scan driver  300 , and a display area  400  that are all formed on a glass substrate  100 .  
         [0044]     The display area  400  includes a plurality of data lines D 1  to Dm arranged in a column direction, a plurality of scan lines S 1  to Sn arranged in a row direction, and a plurality of pixel circuits  410 . The data lines D 1  to Dm are used for transmitting data signals for representing image signals to the pixel circuits  410 , and the scan lines S 1  to Sn are used for transmitting selection signals to the pixel circuits  410 . A pixel circuit  410  is formed in a pixel area which is defined by two neighboring data lines D 1  to Dm and two neighboring scan lines S 1  to Sn.  
         [0045]     The data driver  200  applies data signals corresponding to red, green, and blue image signals to the data lines D 1  to Dm in the display area  400 . The scan driver  300  sequentially generates the selection signals and applies the signals to the scan lines S 1  to Sn in the display area  400 .  
         [0046]     As shown, the OLED or light emitting display according to the present invention is a chip on glass (COG) type OLED or light emitting display in which the display area  400  and the driving circuits (e.g., drivers  200  and  300 ) are formed on the substrate  100 .  
         [0047]      FIG. 3  shows a configuration of the data driver  200  of  FIG. 2 . As shown, the data driver  200  includes a shift register  210 , a buffering unit  220 , and a demultiplexer  230 . The shift register  210  receives a clock signal CLK and a start signal SP and sequentially generates signals SR 1  to SRk shifted at a predetermined interval. The buffering unit  220  buffers the signals sequentially shifted and output from the shift register  210  in order to transmit signals without distortion, and outputs signals BF 1  to BFk. The demultiplexer  230  receives red, green, and blue data signals A_R, A_G, and A_B converted into analog data (from digital data), and sequentially applies the data signals to corresponding data lines D 1 , D 1 , . . . Dm- 1 , Dm with reference to the signals BF 1  to BFk sequentially output from the buffering unit  220 .  
         [0048]      FIG. 4  shows a detailed diagram for representing the configuration of the data driver  200  of  FIG. 3  according to a first exemplary embodiment of the present invention.  
         [0049]     As shown in  FIG. 4 , the shift register  210  includes a plurality of flip-flops  211   1  to  211   k , and the buffering unit  220  includes a plurality of buffering circuits  221   1  to  221   k . The demultiplexer  230  includes a plurality of switching circuits  231   1  to  231   k .  
         [0050]     The flip-flop  211   1  receives a clock signal CLK and a start signal SP, and generates a signal SR 1  having a low level for a predetermined period. The flip-flop  211   2  receives the clock signal CLK and the signal SR 1  output from the flip-flop  211   1 , and outputs a signal SR 2  which is generated by shifting of the signal SR 1  having the low level. In the like manner, the flip-flop  211   k  receives the clock signal CLK and a signal SRk- 1 , and outputs a signal SRk which is generated by the shifting of the signal SRk- 1 .  
         [0051]     The buffering circuits  221   1  to  221   k  receive the signals SR 1  to SRk output from the respective flip-flops  211   1  to  211   k , respectively buffer the signals, and respectively output the signals BF 1  to BFk.  
         [0052]     The demultiplexer  230  includes the plurality of switching circuits  231   1  to  231   k . The switching circuit  231   1  is turned on when the signal BF 1  is received, and respectively outputs twenty-four data signals received through respective eight red, green, and blue data buses (total of twenty-four bus lines) to data lines D 1  to D 24 . In the like manner, the switching circuit  231   2  is turned on when the signal BF 2  is received, and respectively outputs the twenty-four data signals received through the respective eight red, green, and blue data buses (total of twenty-four bus line) to data lines D 25  to D 48 .  
         [0053]     In the data driver according to the exemplary embodiment of the present invention, a test pad  250  is provided at each of the respective output terminals of the buffering circuits  221   1  to  221   k  in order to test any delay(s) or any distortion(s) of the signals SR 1  to SRk output from the shift register  210 .  
         [0054]      FIG. 5  shows a detailed diagram for representing the buffering circuit  221  (e.g., the buffering circuit  221   1 ), and the test pad  250  (e.g., the test paid  250   1 ) provided at the output terminal of the buffering circuit  221 .  
         [0055]     As shown in  FIG. 5 , the buffering circuit  221  includes two n-transistors T 11  and T 12 , and two p-transistors T 21  and T 22 .  
         [0056]     When the signal SR 1  is at the low level, the transistor T 11  is turned off, the transistor T 21  is turned on, and a voltage of VDD is applied to a node a. The voltage of VDD, which is a high level potential of the node a, is applied to gates of the transistor T 12  and the transistor T 22 . The transistor T 12  is turned on, the transistor T 22  is turned off, a voltage of VSS, which is a low level potential, is applied to a node b, and therefore the output terminal of the buffering circuit  221  is at the low level VSS. Accordingly, the test pad  250  is provided to the node b for the purpose of testing the operation of the buffering circuit  221 .  
         [0057]      FIG. 6  shows a configuration in which an area A (shown in  FIG. 5 ) of the test pad  250  and the buffering unit  221  is arranged on the substrate  100 .  
         [0058]     As shown in  FIG. 6 , based on an electrode line  261  forming the node a, the transistor T 12  is extended and arranged in the row direction to the left of the electrode line  261 , and the transistor T 22  is extended and arranged in the row direction to the right of the electrode line  261 . The electrode  261  is coupled to gate lines  268   a  and  268   b  of the transistor T 12 . The electrode  261  is also coupled to gate lines  267   a  and  267   b  through an electrode line  267  and an electrode line  261   a . That is, a signal applied to the node a is transmitted to the gate lines  268   a  and  268   b  of the transistor T 12  and the gate lines  267   a  and  267   b  of the transistor T 22 .  
         [0059]     The power voltage VSS which is the low level potential is applied to an electrode line  262  corresponding to a source of the transistor T 12 , and the power voltage VDD which is high level potential is applied to electrode lines  263   a  and  263   b  corresponding to a source of the transistor T 22 . Electrode lines  264   a  and  264   b  corresponding to a drain of the transistor T 12 , and an electrode line  264  corresponding to a drain of the transistor T 22  which are output terminals output the signal BF 1 .  
         [0060]     A test pad  250  is formed at a terminal of the electrode line  264   a  forming an output terminal. The electrode line  264   a  forming an output terminal as the drain of the transistor T 12  is extended and formed in a rectangular shape and the test pad  250  is formed to be coupled to the electrode line  264   a.    
         [0061]      FIG. 7  shows a cross-sectional view of the test pad  250  taken along the line I-I′ of  FIG. 6 .  
         [0062]     As shown in  FIG. 7 , a blocking layer  110  is formed on the substrate  100 , semiconductor layers including a source and a drain of a transistor, and a channel area are formed on the blocking layer  110 , and a gate insulator film  130  is formed on the semiconductor layer. A gate layer including electrode lines including a gate of the transistor is formed on the gate insulator film  130 . An insulator film between layers  150  is formed on the gate layer. The semiconductor layer and the gate layer are not provided where the test pad  250  is arranged, and therefore are not illustrated.  
         [0063]     A source-drain layer including connection electrodes and data lines coupling sources and drains of transistors is formed on the insulator film between layers  150 . In  FIG. 7 , the electrode  264   a  of  FIG. 6  can be represented as the source-drain layer. An electrode  251  is formed being coupled to the electrode line  264   a . A flattening film  170  is formed on the electrode  251 . A test pad electrode  255  is formed to be coupled to the electrode  251  through a plurality of contact holes  253 . Accordingly, the test pad  250  coupled to the output terminal of the buffering circuit  221  is completed.  
         [0064]     Because of the embodiment of  FIGS. 4, 5 ,  6 , and  7 , the operation of the COG type light emitting display can be tested before its completion because the output power of the shift register  210  may be tested by the test pad  250  coupled to the output terminal of the buffering circuit  221 . Accordingly, a wasteful manufacturing cost caused by completing a defective display is reduced.  
         [0065]     A second exemplary embodiment of the present invention will be described with reference to  FIG. 8  to  FIG. 10 .  
         [0066]     The second exemplary embodiment of the present invention corresponds to the first exemplary embodiment of the present invention except that a test pad  260  is provided to each of the respective output terminals of the switching circuits  231   1  to  231   k .  
         [0067]      FIG. 8  shows a detailed diagram for representing the switching circuit  231   1 , and a test pad  260  provided to an output terminal of the switching circuit  231   1 .  
         [0068]     As shown in  FIG. 8 , the switching circuit  231   1  includes switching elements corresponding to a number of data buses R 1 , G 1 , B 1  through R 8 , G 8 , and B 8 . That is, in the switching circuit  231   1 , a source is coupled to the respective data buses R 1 , G 1 , B 1  through R 8 , G 8 , and B 8  when the red, green, and blue data signals A_R (e.g., A_R 1 , A_R 2 , A_R 8 , etc.), A_G (e.g., A_G 1 , A_G 2 , A_G 8 , etc.), and A_B (e.g., A_B, A_B 2 , A_B 8 , etc.) are input through the twenty-four data buses R 1 , G 1 , B 1  through R 8 , G 8 , and B 8  that are eight data buses for the respective red, green, and blue. The switching circuit  2311  includes twenty-four transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8 . The signal BF 1  output from the buffering circuit  221   1  is applied to respective gates of the transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8 . In this exemplary embodiment of the present invention, the twenty-four transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8  are p-type transistors.  
         [0069]     In operation, the respective buffering circuits  221   1  to  221   k  sequentially output the signals BF 1  to BFk having the low level. The twenty-four transistors (e.g., the transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8 ) of each of the switching circuits  231   1  to  231   k  are turned on, and the data signals transmitted through the data buses (e.g., the data buses R 1 , G 1 , B 1  through R 8 , G 8 , and B 8 ) are applied to the data lines D 1  to Dm.  
         [0070]     In more detail, the low level signal BF 1  is output from the buffering circuit  221   1 , the low level is applied to the gates of the transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8  of the switching circuit  231   1 , and the transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8  are turned on. Accordingly, the data signals A_R (e.g., A_R 1 , A_R 2 , A_R 8 , etc.), A_G (e.g., A_G 1 , A_G 2 , A_G 8 , etc.), and A_B (e.g., A_B 1 , A_B 2 , A_B 8 , etc.) transmitted through the data buses R 1 , G 1 , B 1  through R 8 , G 8 , and B 8  are respectively applied to the data lines D 1  to D 24 . The low level signal BF 2  is output from the buffering circuit  221   2 , and the low level is applied to the gates of the transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8  of the switching circuit  231   2 . Accordingly, the transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8  are turned on, and the data signals A_R, A_G, and A_B transmitted through the data buses R 1 , G 1 , B 1  through R 8 , G 8 , and B 8  are respectively applied to the data lines D 25  to D 48 . In a like manner, the low level signal BFk is output from the buffering circuit  221   k , the low level is applied to the gates of the transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8  of the switching circuit  231   k , the transistors TR 1 , TG 1 , TB 1  through TR 8 , TG 8 , and TB 8  are turned on, and the data signals A_R, A_G, and A_B transmitted through the data buses R 1 , G 1 , B 1  through R 8 , G 8 , and B 8  are respectively applied to the data lines Dm- 23  to Dm. As described, demultiplexer  230  applies a corresponding data signal to 24×k=m data lines D 1  to Dm by using twenty-four data buses R 1 , G 1 , B 1  through R 8 , G 8 , and B 8 .  
         [0071]     Also, in this exemplary embodiment of the present invention, the test pad  260  provided to each of the output terminals of the switching circuits  231   1  to  231   k  is for the purpose of testing the data signal output from the demultiplexer  230 .  
         [0072]      FIG. 9  shows a configuration in which an area A′ of the test pads  260  and the switching circuit  231   1  of  FIG. 8  is arranged on the substrate.  
         [0073]     An electrode line coupled to a source of the transistor TR 1  is formed being coupled to a data bus A_R 1 . An electrode line  263  coupled to a drain of the transistor TR 1  is formed being coupled to a data line D 1 , and a data line for transmitting the signal BF 1  is formed being coupled to a gate of the transistor TR 1 . Accordingly, the transistor TR 1  is turned on with response to the low level signal BF 1  transmitted by the electrode line  140 , and transmits the data signal applied from the data bus A_R 1  to the data line D 1 . Also, an electrode  261  is extended and formed by being coupled to the electrode line  263  coupled to the drain of the transistor TR 1 . The test pad  260  of the transistor TR 1  coupled to the electrode  261  through a plurality of contact holes is formed while being insulated and overlapped with the electrode  261 .  
         [0074]     In a manner similar to above, the test pads  260  of the transistors TG 1 , TB 1 , and TR 2  are formed.  
         [0075]      FIG. 10  shows a cross-sectional view of the test pad  260  taken along the line II-II′ of  FIG. 9 .  
         [0076]     As shown in  FIG. 10 , a blocking layer  110  is formed on the substrate  100 , semiconductor layers including a source and a drain of a transistor, and a channel area are formed on the blocking layer  110 , and a gate insulator film  130  is formed on the semiconductor layer. A gate layer including electrode lines including a gate of the transistor is formed on the gate insulator film  130 . An insulator film between layers  150  is formed on the gate layer. The semiconductor layer and the gate layer are not provided where the test pad  260  is arranged, and therefore are not illustrated.  
         [0077]     A source-drain layer including connection electrodes and data lines coupling sources and drains of transistors is formed on the insulator film between layers  150 . In  FIG. 10 , the electrode line  263  of  FIG. 9  can be represented as the source-drain layer. An electrode  261  is formed being coupled to the electrode line  263 . A flattening film  170  is formed on the electrode  261 . A test pad electrode  265  is formed to be coupled to the electrode  261  through a plurality of contact holes  273 . Accordingly, the test pad  260  coupled to the output terminal of the switching circuit  231  is completed.  
         [0078]     Because of the embodiment of  FIGS. 8, 9 , and  10 , the operation of the COG type light emitting display can be tested before its completion because the output power of the shift register  210  may be tested by forming the test pad  260  coupled to the output terminal of the switching circuit  231 . Accordingly, a wasteful manufacturing cost caused by completing a defective display is reduced.  
         [0079]     A third exemplary embodiment of the present invention will now be described with reference to  FIG. 11  to  FIG. 14 .  
         [0080]     In the third exemplary embodiment of the present invention, the test pad is provided to an output terminal of the flip-flop.  
         [0081]      FIG. 11  schematically shows a configuration of the scan driver  300  according to the third exemplary embodiment of the present invention.  
         [0082]     The scan driver  300  shows a shift register  500 , a level shifter  320 , and a buffer or buffering unit  330 .  
         [0083]     The shift register  500  is a bi-directional shift register for a bi-directional scanning operation. The shift register  500  receives a start signal STV, a clock signal CLK′, and a direction signal CTS from a controller (not illustrated); generates selection signals to be applied to respective scan lines S 1  to Sn; and outputs the selection signals to the level shifter  320 . The shift register  500  sequentially shifts the start signal STV, sequentially generates the selection signals to the respective scan lines S 1  to Sn, and outputs the selection signals according to the input clock signal when the direction signal CTS is a forward signal. The shift register  500  shifts the start signal STV in a reverse direction, sequentially generates the selection signals to the respective scan lines Sn to S 1 , and outputs the selection signals according to the clock signal CLK when the direction signal CTS is a reverse signal.  
         [0084]     The level shifter  320  receives power at voltage levels of Vdd and Vss from one or more power suppliers (not illustrated), and shifts the selection signals to the respective scan lines S 1  to Sn input from the shift register  500  to a predetermined voltage level.  
         [0085]     The buffer  330  buffers the selection signals to the respective scan lines S 1  to Sn shifted to the predetermined voltage level, and applies them to the corresponding scan lines S 1  to Sn of the display area  400 .  
         [0086]      FIG. 12  shows a configuration of the shift register  500 .  
         [0087]     In  FIG. 12 , an inversion signal for a signal that is inversed, is represented by using ‘/’. For example, an inversion signal of the start signal STV is represented by ‘/STV.’ 
         [0088]     The bi-directional shift register  500  includes a plurality of flip-flops  510  to  540 , each including an input terminal and an output terminal; a plurality of forward NAND gates RN 1  to RN 4 ; a plurality of reverse NAND gates LN 1  to LN 4 ; and a plurality of NAND gates N 1  to N 4 .  
         [0089]     While the shift register used in the scan driver  300  and the data driver  200  of  FIG. 2  can each respectively include as many flip-flops as the number of the scan lines and the data lines, it will be described such that the shift register includes four flip-flops in this exemplary embodiment of the present invention for convenience of description. The forward direction will be referred to when a signal is transmitted from the flip-flop  510  to the flip-flop  540  through the flip-flops  520  and  530 , and the reverse direction will be referred to when a signal is transmitted from the flip-flop  540  to the flip-flop  510  through the flip-flops  520  and  530 .  
         [0090]     The forward NAND gate RN 1  receives a start signal STV and a control signal, and the reverse NAND gate LN 1  receives an inversion signal /CTS of the control signal CTS and an output signal of the flip-flop  520 . The NAND gate N 1  receives outputs of the forward NAND gate RN 1  and the reverse NAND gate LN 1 . The flip-flop  510  receives an output of the NAND gate N 1  through an input terminal  511 .  
         [0091]     The forward NAND gate RN 2  receives an output signal of the flip-flop  510  through an output terminal  512 . That is, the forward NAND gate RN 2  receives the output signal of the flip-flop  510  and the control signal CTS. The reverse NAND gate LN 2  receives the inversion signal /CTS of the control signal CTS and an output signal of the flip-flop  530 . The NAND gate N 2  receives outputs of the forward NAND gate RN 2  and the reverse NAND gate LN 2 , and the flip-flop  520  receives an output of the NAND gate N 2  through an input terminal  521 .  
         [0092]     The forward NAND gate RN 3  receives an output signal of the flip-flop  520  through an output terminal  522 . That is, the forward NAND gate RN 3  receives the output signal of the flip-flop  520  and the control signal CTS. The reverse NAND gate LN 3  receives the inversion signal /CTS of the control signal CTS and an output signal of the flip-flop  540 . The NAND gate N 3  receives outputs of the forward NAND gate RN 3  and the reverse NAND gate LN 3 , and the flip-flop  530  receives an output of the NAND gate N 3  through an input terminal  531 .  
         [0093]     The forward NAND gate RN 4  receives an output signal of the flip-flop  530  through an output terminal  532 . That is, the forward NAND gate RN 4  receives the output signal of the flip-flop  530  and the control signal CTS. The reverse NAND gate LN 4  receives the inversion signal /CTS of the control signal CTS and the start signal STV. The NAND gate N 4  receives outputs of the forward NAND gate RN 4  and the reverse NAND gate LN 4 , and the flip-flop  540  receives an output of the NAND gate N 4  through an input terminal  541 .  
         [0094]     When a signal is output in the forward direction, the start signal STV is sequentially transmitted from the flip-flop  510  to the flip-flop  540  through the flip-flops  520  and  530 , and the respective flip-flops  510  to  540  output a delayed signal with reference to the clock signal.  
         [0095]     When a signal is output in the reverse direction, the start signal STV is sequentially transmitted from the flip-flop  540  to the flip-flop  510  through the flip-flops  530  and  520  in the reverse direction, and the respective flip-flops  540  to  510  output a delayed signal with reference to the clock signal.  
         [0096]     Test pads  512   a ,  522   a ,  532   a , and  542   a  for testing an output signal are provided in the respective output terminals  512 ,  522 ,  532 , and  542  of the shift register  500 .  
         [0097]      FIG. 13  shows a configuration in an area A″ of  FIG. 12 , and  FIG. 14  shows a cross-sectional view of a part taken along the line III-III′ of  FIG. 13 .  
         [0098]     As shown in  FIG. 13 , the output terminal  512  of the flip-flop  510  is extended and formed, and the test pad  512   a  is formed in a center of the output terminal  512  in a rectangular form.  
         [0099]     As shown in  FIG. 14 , a blocking layer  110  is formed on the substrate  100 ; semiconductor layers including a source and a drain of a transistor, and a channel area are formed on the blocking layer  110 ; and a gate insulator film  130  is formed on the semiconductor layer. The semiconductor layer and the gate layer are not provided where the test pad  512   a  is arranged, and therefore are not illustrated. A gate layer including electrode lines including a gate of the transistor is formed on the gate insulator film  130 . An insulator film between layers  150  is formed on the gate layer.  
         [0100]     A source-drain layer including connection electrodes and data lines coupling sources and drains of transistors is formed on the insulator film between layers  150 . In  FIG. 14 , the electrode line  512  is formed as the source-drain layer. A flattening film  170  is formed on the electrode  512 . A test pad electrode  512   a  is formed to be coupled to the electrode  512  through a plurality of contact holes C. Accordingly, the test pad  512   a  coupled to the output terminal  512  of the flip-flop  510  is completed.  
         [0101]     Because of the embodiment of  FIGS. 11, 12 ,  13 , and  14 , the operation of the COG type light emitting display may be tested before its completion because the output power of the shift register may be tested by forming the test pad  512   a  coupled to the output terminal of the buffering circuit  221 . Accordingly, a wasteful manufacturing cost caused by completing a defective display is reduced  
         [0102]     According to the present invention, an output of a shift register may be tested by providing a test circuit to an output terminal of a buffering circuit for buffering the signal of the shift register of a data driver. Accordingly, the operation of the data driver may be tested before its completion in the COG type or SOP type light emitting display. Accordingly, a wasteful manufacturing cost caused by completing a defective display is reduced.  
         [0103]     While the invention has been described in connection with certain exemplary embodiments, it is to be understood by those skilled in the art that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications included within the spirit and scope of the appended claims and equivalents thereof.

Technology Category: g