Patent Document

[0001]     This application claims the benefit of U.S. Provisional Patent Application No. 60/616,718 filed on Oct. 6, 2004. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates generally to a hard disk drive data storage system, and more particularly to a method for turning on current mirrors within the hard disk drive data storage system and an apparatus comprising current mirrors for the hard disk drive storage system.  
       BACKGROUND OF THE INVENTION  
       [0003]     Disk drives are a cost effective data storage system for use with a computer or other data processing devices. As shown in  FIG. 1 , a disk drive  10  comprises a magnetic recording medium, in the form of a disk or platter  12  having a hub  13  and a magnetic read/write transducer  14 , commonly referred to as a read/write head. The read/write head  14  is attached to, or formed integrally with, a suspension arm  15  suspended over the disk  12  and affixed to a rotary actuator arm  16 . A structural arm  18 , fixed to a platform  20  of the disk drive  10 , is pivotably connected to the actuator arm  16  at a pivot joint  22 . A voice coil motor  24  drives the actuator arm  16  to position the head  14  over a selected position on the disk  12 .  
         [0004]     As the disk  12  is rotated by a spindle motor (not shown) at an operating speed, the moving air generated by the rotating disk, in conjunction with the physical features of the suspension arm  15 , lifts the read/write head  14  away from the platter  12 , allowing the head to glide or fly on a cushion of air slightly above a surface of the disk  12 . The flying height of the read/write head over the disk surface is typically less than a micron.  
         [0005]     An arm electronics module  30  may include circuits that switch the head function between read and write operations and write drivers for supplying write current to the head  14  during write operations. The write current alters magnetic domains within the disk  12  to store data thereon. The arm electronics module  30  may also include a preamplifier electrically connected to the head  14  by flexible conductive leads  32 . During read operations the preamplifier amplifies the read signals produced by the head  14  to increase the read signal signal-to-noise ratio. In the write mode, the preamplifier scales up the relatively low voltage levels representing the data bits to be written to the disk to a voltage range of about ±6 to ±10V. The preamplifier also shapes the write signal to optimize the data writing process.  
         [0006]     The configuration and components of the electronics module  30  may vary according to the disk drive design, as will be understood by persons familiar with such technology. Although the module  30  may be mounted anywhere in the disk drive  10 , a location proximate the head  14  minimizes signal losses and induced noise in the head signals during a read operation. A preferred mounting location for the module  30  comprises a side surface of the structural arm  18  as shown in  FIG. 1 .  
         [0007]     As shown in  FIG. 2 , the disk  12  comprises a substrate  50  and a thin film  52  disposed thereover. During write operations current through a write head  14 A alters magnetic domains of ferromagnetic material in the thin film  52  for storing the data bits as magnetic transitions. During read operations a read head  14 B senses the magnetic transitions to determine the data bits stored on the disk  12 .  
         [0008]     In other data storage systems the head  14  operates with different types of storage media (not shown in the Figures) comprising, for example, a rigid magnetic disk, a flexible magnetic disk, magnetic tape and a magneto-optical disk.  
         [0009]     The disk drive read head  14 B comprises either a magneto-resistive (MR) sensor or an inductive sensor. The former produces a higher magnitude output signal in response to the magnetic transitions, and thus the output signal exhibits a greater signal-to-noise ratio than an output signal produced by the inductive sensor. The MR sensor is thus preferred, especially when a higher areal data storage density in the disk drive  10  is desired.  
         [0010]     A DC (direct current) voltage of about 0.04V to 0.2V is supplied by the preamplifier to the read head terminals  54 A and  545 B via the conductive leads  32  for biasing the read head  14 B. Magnetic domains in the thin film  52  passing under the read head  14 B alter a resistance of the magneto-resistive material, imposing an AC (alternating current) component on the DC bias voltage, wherein the AC component represents the read data bits. The AC component is detected in the preamplifier, but has a relatively small magnitude (e.g., several millivolts) with respect to the DC bias voltage.  
         [0011]     Operation of the preamplifier read circuits is not required during those times when data is not being read from the disk  12 . Since power consumption is not typically an operational limitation for a desktop computer, the read circuits in the desktop computer disk drive system are maintained in an on state when data is not being read from the disk  12 . This feature minimizes a turn-on time for the read circuits (specifically the turn-on time for preamplifier current mirrors operative when reading data) and ensures that the preamplifier processes the magnetic transitions from the beginning of the data read interval.  
         [0012]     The desktop preamplifier may be switched to a semi-active state (idle mode) if the computer does not access the disk drive  10  for an extended length of time, and may be shut down to a very low power level (sleep mode) when the computer switches to a sleep state. The disk drive system  10  permits a relatively long (i.e., several microseconds to milliseconds) power-up time for the preamplifier to transition from the sleep or idle mode to one of the fully active modes (e.g., the read or the write mode).  
         [0013]     In contrast to a desktop computer system, battery power conservation is a crucial design objective for mobile and portable computing devices and data processing systems, for stored music players and for other battery-operated devices that include a mass data storage system operative with a preamplifier. To minimize preamplifier power consumption and thereby conserve battery power, the preamplifier read circuits are turned off when data is not being read from the hard disk drive. For example, the read circuits are turned off during data writing. But to avoid data losses during a read operation and to provide high-speed data access, it is desired that the preamplifier read circuits turn-on and reach a desired steady state condition in less than about 100 ns.  
         [0014]     Returning to  FIG. 2 , the output signal from the read head  14 B, representing data bits read from the disk drive  10  and having an amplitude in a range of several millivolts, is input to a signal processing stage  102  followed by an output or buffer stage  104 . Typically, both the signal processing stage  102  and the output stage  104  are included within the preamplifier. The output stage  104  scales up the head signal voltage to a peak voltage value in a range of several hundred millivolts and supplies the scaled-up signal to channel circuits of a channel chip  106 . The channel chip  106  detects the read data bits from the voltage pulses, while applying error detection and correction processes to the voltage pulses.  
         [0015]      FIG. 3  illustrates a conventional prior art output stage  104  of  FIG. 2 . A PMOSFET M 2  is gated on to supply a reference current Iref 0  (25 microamps in one embodiment) that is directed to a collector C of a bipolar junction transistor (BJT) Q 1  (operating as a current mirror master) and to a gate G of an n-channel metal oxide semiconductor field effect transistor NMOSFET) M 0  to turn on the NMOSFET M 0 . A source S of the PMOSFET M 2  and a drain D of the NMOSFET M 0  are connected to a positive power supply voltage VP (in one embodiment about 3.3 V) and a source S of M 2  is connected to a base B of the transistor Q 1 . When the NMOSFET M 0  is on, the BJT Q 1  is gated on and the current Iref 0  flows through the BJT Q 1  and a resistor R 11  to ground. As is known, the base current of a BJT can change over a five to one range due to the BJT fabrication process variations and due to temperature variations during operation. A resistor R 7  operates as a pull down resistor for the NMOSFET M 0  to ensure M 0  supplies sufficient bias current for proper operation of the current mirror transistors Q 1 , Q 2 , Q 3 , Q 4  and Q 5  over all expected process, temperature and operating conditions. In those applications where battery power conservation is advisable, the current Iref 0  is terminated when data is not being read from the disk  12 , i.e., when data is being written to the disk  12  and during idle periods when data is neither being written nor read.  
         [0016]     The BJTS Q 2 , Q 3 , Q 4  and Q 5  are also gated on by the on-state of the NMOSFET M 0 . Assuming that the BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5  are matched, have substantially identical base-emitter voltages and operate with properly-scaled emitter resistors R 11 , R 10 , R 13 , R 14  and R 15 , then the BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5  operate as scaled current mirrors. By properly scaled emitter resistors is meant that each resistor R 11 , R 10 , R 13 , R 14  and R 15  is scaled based on the BJT with which the resistor is associated, i.e., R 10 =R 11 /k 1 , R 13 =R 11 /k 2 , R 14 =R 11 /k 3  and R 15 =R 11 /k 4 , where k 1 -k 4  represent an emitter area ratio for each of the BJT&#39;s Q 2 -Q 5  relative to the emitter area of Q 1 , that is, Q 2 =Q 1 *k 1 , Q 3 =Q 11 *k 2 , Q 4 =Q 1 *k 3  and Q 5 =Q 1 *k 4 ). The BJTS Q 2 , Q 3 , Q 4  and Q 5  function as constant current sources for their associated BJTS Q 7 , Q 6 , Q 12  and Q 9 . The current Iref 0  through the BJT Q 1  is mirrored and scaled (according to the associated scaling value k) through the BJTS Q 2 , Q 3 , Q 4  and Q 5 .  
         [0017]     A collector C of a BJT Q 7  is connected to the power supply VP through a resistor R 17 , and a base B of Q 7  is driven by a bias voltage (not shown) and voltage pulses from the signal processing stage  102 . When an amplifier comprising BJTS Q 6  and BJT Q 7  is active, the BJT Q 7  is driven to an on state or on condition and the current Iref through the BJT Q 1  is mirrored as a current I 2  through resistors R 10  and R 17  and the BJTS Q 7  and Q 2 . Since the BJTS Q 1  and Q 2  form a current mirror, then I 2 =k 1 *Iref, where k 1  is the ratio of the emitter area of BJT Q 2  to the emitter area of BJT Q 1 . Typically such area ratioed BJTS are formed from a plurality of unit transistors, that is, the BJT Q 2  comprises k 1  times the number of unit transistors comprising the BJT Q 1 .  
         [0018]     The negative feedback action of the emitter resistors R 10  and R 11  increases the impedance seen looking into the collector of the BJT Q 1  and the BJT Q 2  enough such that the ratio of I 2  to Iref is a very weak function of Q 2 &#39;s collector-emitter voltage, as long as Q 2 &#39;s collector-emitter voltage is greater than approximately 0.5V. Thus as can be appreciated by those skilled in the art, the variation of I 2  with the collector-emitter voltage of BJT Q 2  is neglected herein.  
         [0019]     A state of the current mirror BJT Q 3  is controlled by the NMOSFET M 0 . The BJT Q 6  is biased by the signal processing stage  102 , which supplies both the signal and DC bias to the base B of the BJT Q 6 . When the BJTS Q 3  and Q 6  are both gated on, a current I 3  flows through resistors R 19  and R 13  and the BJTS Q 3  and Q 6 , where I 3 =k 2 *Iref, since the BJTS Q 1  and Q 3  are current mirrors and Q 3 =Q 1 *k 2 .  
         [0020]     The BJTS Q 6  and Q 7  form a differential amplifier with a degeneration resistor R 20  connected between the emitter of the BJT Q 6  and the emitter of the BJT Q 7  to linearize the amplification and stabilize the gain. The signal from signal processing stage  102  biases the amplifier inputs (the base of each one of the BJTS Q 6  and Q 7 ) and presents the processed data signal that is amplified (i.e., scaled-up) and buffered by the output stage  104  before driving an interconnect to the channel chip  106 , i.e., terminals RDP and RDN.  
         [0021]     The BJTS Q 9  and Q 12  buffer collector loads R 17  and R 19  to drive the interconnect to the channel chip  106  from a low impedance thereby maintaining a wide bandwidth, typically up to about 700 MHz.  
         [0022]     In  FIG. 3  the NMOSFET M 0  supplies the base drive current for each of the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5 . In one embodiment each BJT base current is about 16 microamps, for a total of about 80 microamps. The current Iref is substantially equivalent to the collector current of the BJT Q 1 , since substantially no current flows to the gate G of the NMOSFET M 0 .  
         [0023]     A circuit loop comprising the base/collector path of the BJT Q 1  and the gate/source path of the NMOSFET M 0  forms a feedback loop that, like all feedback loops, tends to oscillate. The oscillations are limited or controlled by a capacitor C 0  connected between the collector of the BJT Q 1  and ground. The loop bandwidth is controlled by the current through the NMOSFET M 0 , as determined by the resistor R 7  and is increased by the base current supplied to the BJTS Q 1 , Q 2 , Q 3 , Q 4 , and Q 5 .  
         [0024]     Although the capacitor C 0  advantageously prevents feedback loop oscillation, it also disadvantageously extends the turn-on time of the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5  as the current mirrors do not turn on until the capacitor C 0  has charged. The output signal does not appear at the terminals RDP and RDN until the current mirrors have turned on. Thus the output signal is delayed by the charging time of the capacitor C 0 . In certain embodiments of the output stage  104  the output signal delay exceeds the objective of about 100 nanoseconds.  
       SUMMARY OF THE INVENTION  
       [0025]     According to one embodiment, the present invention comprises a current mirror controller for controlling current mirrors, comprising: a control node having a reference current therethrough; a current mirror master connected to the control node and receiving the reference current, the current mirror master connected to the current mirrors; a first switching device connected to a power supply controlling a state of the current mirror master; a circuit module configured to control a voltage at the control node to a first voltage during a first operational mode; and the circuit module configured to control the voltage at the control node to a second voltage during a second operational mode, wherein the first switching device controls the current mirror master to an on state during the second operational mode during which the current mirrors mirror the reference current.  
         [0026]     According to another embodiment, the invention comprises a method for controlling current mirrors, comprising: controlling a voltage at a control node to a first voltage during a first operational mode and to a second voltage during a second operational mode, wherein a capacitor is connected to the control node; supplying a reference current through the control node to a current mirror master, wherein during the second operational mode the reference current is mirrored and scaled by the current mirrors; and charging the capacitor from the first voltage to the second voltage at an onset of the second operational mode such that after the capacitor is charged to the second voltage the current mirrors are turned on to mirror the reference current. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]     The present invention can be more easily understood and the advantages and uses thereof more readily apparent when the following detailed description of the present invention is read in conjunction with the figures wherein:  
         [0028]      FIG. 1  illustrates a prior art disk drive to which the teachings of the present invention can be applied.  
         [0029]      FIG. 2  is a schematic diagram of a prior art head and related components of the disk drive of  FIG. 1 .  
         [0030]      FIG. 3  is a schematic diagram of a prior art output stage of  FIG. 2 .  
         [0031]      FIGS. 4 and 5  are schematic diagrams of certain elements for use in conjunction with the output stage of  FIG. 3   
         [0032]      FIG. 5  is a schematic diagram of certain elements for use in conjunction with the output stage of  FIG. 3  according to the present invention  
         [0033]      FIG. 7  illustrates timing diagrams of current magnitudes as a function of time for the three embodiments of  FIGS. 4-6 .  
     
    
       [0034]     In accordance with common practice, the various described device features are not drawn to scale, but are drawn to emphasize specific features relevant to the invention. Reference characters denote like elements throughout the figures and text.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0035]     Before describing in detail the particular method and apparatus related to an output stage of a preamplifier for a disk drive system, it should be observed that the present invention resides primarily in a novel and non-obvious combination of elements and process steps. So as not to obscure the disclosure with details that will be readily apparent to those skilled in the art, certain conventional elements and steps have been presented with lesser detail, while the drawings and the specification describe in greater detail other elements and steps pertinent to understanding the invention.  
         [0036]      FIG. 4  illustrates a current mirror controller  112  for use with the output stage  104  of  FIG. 3  (replacing a current mirror controller  110  thereof) that limits the turn on time of the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5  by maintaining a charge on the capacitor C 0  during non-read intervals such as during data writing and during an idle mode state. As described above, when data is read from the disk  12 , the current mirrors are turned on to activate the amplifier comprising the BJTS Q 6 , Q 7 , Q 9  and Q 12 . The amplifier scales up and buffers the voltage from the signal processing stage  102  for subsequent processing and data detection in the channel chip  106 .  
         [0037]     In the  FIG. 4  circuit, a PMOSFET M 2  is on during the non-read intervals (such as during data writing and during an idle mode) to supply a reference current Irefl that maintains a charge on the capacitor C 0 . Since the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5  do not turn on until the capacitor C 0  is charged, maintaining the capacitor C 0  in a charged state avoids a time delay that would otherwise be required to charge the capacitor C 0  before the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5  turn on at the beginning of a read operation. The PMOSFET M 2  is on at all times except when the disk drive is operating in the sleep mode.  
         [0038]     To conserve battery power, it is desired to turn off the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5  during data writing and idle periods. This is accomplished by turning off the PMOSFET M 4  to open the current path through the NMOSFET M 0  that supplies base current drive to the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5 . The PMOSFET M 4  is turned off by applying an inverse read signal, which is high during the write and idle modes, to a gate G.  
         [0039]     With the BJT Q 1  off, the PMOSFET M 2  pulls a node  120  and the capacitor C 0  to the power supply voltage VP as desired during non-read intervals. Note that when the current mirrors BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5  are active, the NMOSFET M 0 , the BJT Q 1 , the resistor R 11  and the current Iref determine the voltage at the node  120 .  
         [0040]     During a read operation, the inverse read signal goes low, gating the PMOSFET M 4  on, permitting the NMOSFET M 0  to supply base current to turn on the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5 . Since the capacitor C 0  had been charged to the power supply VP, at the beginning of read mode operation the capacitor C 0  must discharge to an operating voltage of Vgs M0 +Vbe Q1 +Iref 1 *R 11 . During this discharging interval the current I 2 , the collector current of the BJT Q 7  (see  FIG. 3 ) overshoots its intended value for approximately 20 ns. The current overshoot causes the output common mode voltage at the output terminals RDP and RDN in  FIG. 3  to fall then slowly recover as the capacitor C 0  reaches its operating voltage. During the overshoot period a common mode transient is supplied to the channel chip  106  through Q 12  and Q 9  of  FIG. 3 . Obviously, this is not an acceptable condition as it may adversely impact reading of the first several data bits from the disk  12 .  
         [0041]      FIG. 5  illustrates a current mirror controller  122  for limiting the turn on time of the current mirrors. In the  FIG. 5  embodiment, an NMOSFET M 6  is turned on during data writing and idle operation (by a high logic state of the inverse read signal applied to a gate G of the NMOSFET M 6 ), shunting the reference current Iref 2  to ground and shorting the capacitor C 0  and the node  120  to ground. As a result, the gate G of the NMOSFET M 0  is at ground potential and the NMOSFET M 0  is off. No current flows through the NMOSFET M 0  to supply base current to drive the current mirrors so the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5  are off.  
         [0042]     During data reading the NMOSFET M 6  is turned off, permitting the capacitor C 0  to charge to the power supply voltage and gating the NMOSFET M 0  on to supply the base current for the current mirror BJTS Q 1 , Q 2 , Q 3 , Q 4  and Q 5 . However, an extended mirror turn-on time (as long as 40 ns in one embodiment) is required to charge the capacitor C 0  from ground to Vgs M0 +Vbe Q3 +Iref 2 *R 11 . Such a long turn on time may be unacceptable as the first several data bits read from the disk  12  may not be properly processed through the output stage  104 .  
         [0043]      FIG. 6  illustrates a schematic diagram of yet another current mirror controller  130  having a relatively fast settling time when compared with the current mirror controller  122  of  FIG. 5  and avoiding the overshoot period associated with the current mirror controller  112  of  FIG. 4 . The current mirror controller  130  is can be used in place of the controller  110  of  FIG. 3 .  
         [0044]     To minimize current mirror turn-on time at the start of each read cycle, during non-read intervals (e.g., during idle/write mode operation) the current mirror controller  130  clamps the voltage at the node  120  to a voltage that approximates the nodal voltage during the read mode. Preferably according to one embodiment, the idle/write mode bias voltage at the node  120  is set slightly below the nodal read mode voltage so that the current I 2  does not overshoot the intended bias level at the start of a read operation.  
         [0045]     The NMOSFET M 0  provides the same functionality in the current mirror controller  130  as in the embodiments of  FIGS. 3-5 .  
         [0046]     An inverse read signal having a high logic state during the idle and write modes gates a PMOSFET M 30 . During the idle and write modes, the inverse read signal controls the PMOSFET M 30  to an open state, thereby shutting down the current mirrors by removing the current bias to the base of the mirror master BJT Q 1  and each current mirror BJT Q 2 , Q 3 , Q 4  and Q 5 . Turning off the current mirrors during idle and write modes conserves power, an especially important advantage for battery powered devices.  
         [0047]     Current Iref 3  supplied from the power supply VP under control of the PMOSFET M 2  causes an NMOSFET M 31  to turn on. The PMOSFET M 2  is on during the idle, write and read modes. According to a preferred embodiment, Iref 3  is turned off during a sleep mode of the disk drive  10  and anytime power is removed from the disk drive  10 , by turning off M 2 . 25 μA is an exemplary value for Iref 3 , which is similar to Iref 2  and Iref 1  in the other embodiments. A resistor R 22  operates as a pull down resistor for the NMOSFET M 31 .  
         [0048]     A PMOSFET M 32  is gated on by a low logic state of the read signal applied to a gate G. Thus when the read signal is low (during idle and write operations) the PMOSFET M 32  is on and the transistor Q 10  is on, permitting Iref 3  current through the node  120 , the collector-emitter path of the BJT Q 10  and the resistor R 20 . The node voltage equals the collector-emitter voltage drop across the BJT Q 10  plus a voltage drop across the resistor R 20 . The capacitor C 0  is charged to the node voltage during the idle and write modes. Note the capacitance of the capacitor C 0  can be the same in the embodiments of  FIGS. 3-6 .  
         [0049]     To control the node voltage to approximately the same value in the read mode as in the write/idle modes, R 20 =R 11  and Q 10  has the same performance parameters as Q 1 . To ensure that the voltage at the node  120  is slightly lower during write/idle operation than the voltage during read operation, R 22 =40 kΩ while R 7 =10 kΩ, and M 31  is 5 um wide while M 0  is 10 um wide, permitting Vgs M31  in the idle/write modes to be slightly lower than Vgs M0  in the read mode.  
         [0050]     Those skilled in the art recognize that these values are merely exemplary and other values can be used to achieve a Vgs M31  voltage in the idle and write modes lower than Vgs M0  in the read mode. For example, the devices sizes specified above control the voltage at the node  120  to approximately 1.9 V in the read mode and 1.8 V in the write/idle modes. The voltage difference of about 0.1 V was selected according to one embodiment based on expected performance variations (e.g., due to variations in component values) and the desired amount of undershoot and overshoot.  
         [0051]     During the read mode the PMOSFET M 30  is on and current is supplied from the power supply VP to the feedback loop comprising the MOSFET M 0  and the BJT Q 1 , which supplies he base current to the BJT current mirrors Q 2 , Q 3 , Q 4  and Q 5 .  
         [0052]     Further during the read mode, the read signal supplied to the gate of the PMOSFET M 32  and to a gate of an NMOSFET M 34  turns the PMOSFET M 32  off and the NMOSFET M 34  on. When the PMOSFET M 32  is off, the base drive for the BJT Q 10  is removed. Further, when the NMOSFET M 34  is on the base of the BJT Q 10  is shorted to ground, turning Q 10  off Thus the Iref 3  current charges the capacitor C 0  to its normal operating voltage, but because it had been charged to the voltage at the node  120  during write/idle operation, the charging time is significantly reduced from that of the  FIG. 5  embodiment.  
         [0053]     By maintaining the node  120  at about the same voltage during both read and idle/write operations, the charge time of the capacitor C 0  is reduced and the turn-on time of the current mirrors is also reduced.  
         [0054]     In another embodiment, one or more of the MOSFETS and BJTS as described herein is replaced by an opposite polarity MOSFET or BJT. The associated gate drive signals and power supply voltages are modified to accommodate the doping characteristics of the opposite polarity MOSFET or BJT, while providing the functionality of the present invention. Further, throughout the description of the present invention, the phrase, ‘high’ signal value is used interchangeably with a ‘true’ or an ‘asserted’ state. Those skilled in the art recognize that other signal values can also be associated with a ‘true’ or an ‘asserted’ logic state with a corresponding change in the device responsive to the logic state.  
         [0055]      FIG. 7  shows three timing diagrams illustrating the current I 2  (one of the mirrored currents) as a function of time for the three embodiments of the present invention. The “overshoo” curve is associated with the embodiment of  FIG. 4 , the “slow” curve is associated with the embodiment of  FIG. 5  and the “fast” curve is associated with the embodiment of  FIG. 6 . The substantial improvement provided by the  FIG. 6  embodiment is evident.  
         [0056]     While the present invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalent elements may be substituted for the elements thereof without departing from the scope of the invention. The scope of the present invention further includes any combination of elements from the various embodiments set forth herein. In addition, modifications may be made to adapt a particular situation to the teachings of the present invention without departing from its essential scope. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Technology Category: g