Patent Document

RELATED APPLICATIONS  
       [0001]     This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/626,801, filed Nov. 10, 2004, the disclosure of which is incorporated herein by reference in its entirety. 
     
    
     TECHNICAL FIELD  
       [0002]     The subject matter described herein relates to managing electronic-circuit cards residing in electronic equipment enclosures. More particularly, the subject matter described herein relates to methods and systems for providing management communications between electronic circuit cards in a telecommunications equipment shelf assembly and an off-shelf management entity.  
       BACKGROUND ART  
       [0003]     It is well known to arrange telecommunications equipment in shelf assemblies. In some shelf assemblies, circuit cards are removably connected to a backplane or midplane. The circuit cards may be arranged in parallel to one another and may be guided to be perpendicular to the backplane or midplane. Electrical connections are established between connectors on the backplane or midplane and complementary connectors on the back edge of each circuit card. Typically, the connectors include multiple pins and sockets arranged in one or more rows along part or all of the back edge of the circuit card. When a circuit card is inserted into the equipment shelf, the shelf guides provide an approximate alignment for the pins and sockets, and a precise alignment is achieved by the mating portions of the connectors.  
         [0004]     The backplane or midplane typically provides power to each circuit card, as well as electrical interconnections between circuit cards. The electrical signal assigned to each connector pin is left to the designer of the card and chassis to decide. Thus, various connector pin-outs have been developed, both industry standard and proprietary. The PCI Industrial Computer Manufacturers Group (PICMG) 3.0 specification defines an open architecture whereby circuit cards from different manufacturers can interoperate within a shelf assembly. The PICMG specification defines the pinout and function of the various connectors used to connect a circuit card to the midplane of a shelf assembly.  
         [0005]      FIG. 1  is a perspective view of the basic elements of a PICMG 3.0 compliant card assembly platform. In  FIG. 1 , front board  101  contains the electrical components required to perform a desired function or application and has connectors required to interface with a shelf midplane  103 . The PICMG standard defines three connector zones on front board  101 . Zone  1  provides power connection and shelf management, Zone  2  provides the data transport interface, and Zone  3  permits a user defined input/output interconnect. Midplane  103  has connector interfaces for the Zone  1  and Zone  2  connectors on the front board  101 , as well as mechanical alignment and support. Rear transition module  105  provides user defined input and output connectivity between the Zone  3  connector on the front board  101  and external systems or devices.  
         [0006]     Shelf assemblies permit the deployment of several application cards in a comparatively small space. In many shelf architectures, a shelf management interface card is provided to monitor shelf status and provide the ability to manage cards within the shelf, for example by relaying network management queries and responses between a system manager and an application card. A common network management protocol is Simple Network Management Protocol (SNMP), which typically uses TCP/IP for transport. Thus, in order for the application card to receive and respond to SNMP queries, the application card must be functioning at a level that permits communication at a higher-level protocol. For example, the operating system on an application card must generally be operational to implement SNMP or another application level management protocol. When a card fails on booting up, the operating system may not be available. As a result, application level management functions are typically not available.  
         [0007]     In order to provide diagnostic and management connectivity when application level management capabilities are not available, application cards have typically included a dedicated serial port to permit configuring and debugging the application card when the application card is not capable of supporting a higher level protocol. This dedicated serial port is referred to as a console port. The console port is generally accessible through rear transition module  105  using a suitable connector. Requiring a dedicated console port on each card increases the cost of electronic equipment assemblies when the assemblies have multiple cards. In addition, the time and equipment required to diagnose card failures is increased since the console port on each card must be accessed in order to monitor data being sent from each card.  
         [0008]     Accordingly, there exists a need for improved methods and systems for providing diagnostic and management connectivity to application cards in electronic equipment assemblies having multiple application cards.  
       DISCLOSURE OF THE INVENTION  
       [0009]     In accordance with one aspect of the subject matter described herein, a method for connecting an externally accessible shared serial port to one of a plurality of target serial ports is provided. The target serial ports are associated with a plurality of different application cards within a shelf assembly. The method includes receiving, from an external device connected to an externally accessible shared serial port, a request for a connection between the externally accessible shared serial port and one of a plurality of target serial ports within a shelf assembly associated with a plurality of different application cards, and determining whether shelf resources are available to connect the externally accessible shared serial port to the requested target serial port. In response to determining that shelf resources are available, the externally accessible shared serial port is connected to the requested target serial port.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIG. 1  is a perspective view of the basic elements of a PICMG 3.0 compliant platform;  
         [0011]      FIG. 2  is a block diagram of a shelf assembly having a shared serial management interface in accordance with an aspect of the subject matter described herein;  
         [0012]      FIG. 3  is a block diagram of an exemplary interface for a shared serial bus in accordance with an embodiment of the subject matter described herein; and  
         [0013]      FIG. 4  is a block diagram of a midplane of a PICMG 3.0 compatible shelf assembly in accordance with an embodiment of the subject matter described herein. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]     The subject matter described herein provides improved methods and systems for providing diagnostic card management connectivity to a plurality of application cards in a shelf assembly using a shared serial management interface. The shared serial management interface may be provided on a shelf management card and may be accessible to an external manager. The shelf management card interacts with an application card at a level that does not require the operating system on the card to be operational. For example, the management card may provide diagnostic and management connectivity to the application cards during boot up and during or after an operating system failure.  
         [0015]      FIG. 2  is a block diagram of a shelf assembly having a shared serial management interface in accordance with an aspect of the subject matter described herein. Shelf management card  200  includes one or more external management ports  202 A,  202 B, and  202 C that may be used to interface with an external manager, a corresponding number of universal asynchronous receiver transmitters (UARTs)  204 A,  204 B, and  204 C, a shelf management control processor  206 , a shelf management interface  208 , multiplexer and selector logic  210 , a rack control interface  212 , and a shared serial bus interface  214 .  
         [0016]     In  FIG. 2 , three external management ports  202 A,  202 B, and  202 C are shown. External management ports  202 A and  202 C may provide a direct terminal interface, while external management port  202 B may provide connectivity through a dedicated modem. Each external management port  202 A,  202 B, and  202 C may interface with a respective UART  204 A,  204 B, and  204 C and may include circuitry needed to convert the interface signals to a format and level compatible with the UARTs  204 A,  204 B, and  204 C. For example, external management ports  202 A and  202 C may include circuitry to convert the terminal interface signals from one voltage level, such as that used by serial interface standards such as EIA/TIA-232, to a voltage level compatible with the corresponding UART  204 A and  204 C. Similarly, external management port  202 B may include circuitry, such as a modulator/demodulator, to convert encoded data received from the public switched telephone network (PSTN) to a serial bit stream.  
         [0017]     UARTs  204 A,  204 B, and  204 C interface with the shelf management processor  206 . As is known to the art, a UART receives data from a host processor and converts the data into a serial bit stream having a format that is compatible with a target serial device, such as a terminal. For example, the UART may add start, stop, and parity bits to each character and transmit the character to the terminal at a specified serial data rate. Likewise, serial data that is received at a specified serial data rate from the terminal is converted by the UART into a suitable format by removing the start, stop, and parity bits. The UART may employ common flow control techniques and an internal data buffer to provide efficient communication between the shelf management control processor  206  and the external manager. As shown in  FIG. 2 , UARTs  204 A,  204 B, and  204 C may be integral to shelf management processor  206  or may be peripheral to shelf management processor  206  and interface with shelf management processor  206  using conventional techniques, such as connection by an address and data bus.  
         [0018]     Shelf management processor  206  provides a communication and control interface between an external manager and application cards in the shelf. Shelf management processor  206  may receive a request from an external manager to connect to a particular application card in the shelf assembly. A connection menu generated by shelf management processor  206  may be viewed by the external manager and the connection request may be transmitted to shelf management processor  206  as a menu option selection. The connection menu may include a list of available ports that may be used to establish a connection and may be presented in a source-target format. For example, external management port  202 A,  202 B, or  202 C may be designated as a source port and either rack control interface  212  or shared serial bus interface  214  may be designated as a target port. The connection menu may list each possible source-target combination, or may utilize a two-step approach, with a source port identified in one step and a target port identified in another step. Shelf management processor  206  may also be capable of receiving connection requests from a command line using a predetermined command format.  
         [0019]     After receiving a connection request, shelf management processor  206  may determine if the shelf resources needed to complete the connection (i.e., the designated source port and the designated target port) are available. If shelf management processor  206  determines that connection resources are available, shelf management processor  206  may instruct the appropriate application card to attach to a shared serial bus  402 , for example by sending a connection command over shelf management interface  208 . Shelf management interface  208  may be adapted to connect to management channel  404 . Shelf management interface  208  may be implemented using a commercially available chip set, such as Intel&#39;s Intelligent Platform Management Interface (IPMI). IPMI, which is based on the inter-integrated circuit (I 2 C) bus developed by Philips Semiconductors, uses a serial data line and a serial clock line to support communication on management channel  404 . Shelf management processor  206  may complete the connection between the appropriate external management port  202 A,  202 B, or  202 C and shared serial bus interface  214  using multiplexer and selector logic  210 .  
         [0020]     In addition to connecting to a local application card via shared serial bus interface  214 , a connection to a shelf manager controller  200  on an adjacent shelf may be established using rack control interface  212 . Rack control interface  212  may be connected to a management port  202 A,  202 C on a shelf management controller  200  residing on an adjacent shelf using an external cable.  
         [0021]     Once the connection between external management port  202 A,  202 B, or  202 C, and the target interface (i.e., serial bus interface  214  or rack control interface  212 ) is established, shelf management processor  206  monitors communications from the external manager to determine when to terminate the connection between the external manager and the target interface. The external manager may initiate the termination of the connection using an in-band command, such as a predetermined escape sequence, by changing the status of one or more hardware interface signals, or both.  
         [0022]      FIG. 2  illustrates two application cards  300 , each of which may be identically configured to busses  402  and  404 . For simplicity, the internal components of one of the application cards are omitted from  FIG. 2 . In  FIG. 2 , application card  300  may include an application processor  302 , a shelf management interface  304 , a UART  306 , a shared serial bus interface  308 , and control logic  310 . Application processor  302  may perform predetermined application functions, such as providing connection and management functions in a telecommunications network. Application processor  302  may also respond to queries through shelf management interface  304 , which performs functions complementary to shelf management interface  208 . Shelf management interface  304  may communicate with shelf management interface  208  on shelf manager controller  200 , including receiving and responding to various status messages. Shelf management interface  304  may be implemented using a commercially available chip set, such as Intel&#39;s Intelligent Platform Management Interface (IPMI), and may include a dedicated management controller and interface logic. By using a dedicated management interface, such as IPMI, application processor  302  may be freed from responding to shelf-level management messages. In addition, in the event that application processor  302  ceases to function properly, access to the management functions of application card  300  may still be provided through shelf management interface  304 .  
         [0023]     UART  306  and shared serial bus interface  308  provide communication capability between application processor  302  and shared serial bus  402 . Control logic  310  receives appropriate instructions from shelf management interface  304  to engage or disengage shared serial bus interface  308  from shared serial bus  402 . Data received from shared serial bus  402  is reformatted by UART  306  and read by application processor  302  in due course.  
         [0024]     In accordance with one embodiment of the subject matter described herein, shelf management card  200  communicates with an application card  300  using a shared serial bus  402 . Each application card  300  in a shelf may be connected to shared serial bus  402 . Shelf management card  200  and application cards  300  may be configured in a master-slave configuration, with shelf management card  200  acting as the serial bus master.  
         [0025]      FIG. 3  is a block diagram of an exemplary interface for a shared serial bus in accordance with an embodiment of the subject matter described herein. In  FIG. 3 , each redundant shared serial bus  402 A and  402 B may be implemented as a balanced, multi-drop transmission line, such as that defined by EIA RS-422 or RS-485. Shelf management card  200 A or  200 B and each application card  300 A and  300 B may have a differential transceiver circuit  308  to interface to shared serial bus  402 A and  402 B. The receiver portion of transceiver circuit  308  of each application card  300 A and  300 B is connected to the transmitter portion of transceiver circuit  214  of shelf management card  200 A and  200 B. Likewise, the transmitter portion of transceiver circuit  308  of each application card  300 A and  300 B is connected to the receiver portion of transceiver circuit  214  of the respective shelf management card  200 A and  200 B. Each application card  300 A and  300 B may include provisions to ensure that only one application card is transmitting at a time to prevent bus contention.  
         [0026]     Each application card  300 A and  300 B may include two serial ports for low-level diagnostics, with each serial part being supported by a UART  306 . One port may be a diagnostics port and the other may be a console port. The diagnostics port may provide access to diagnostics that are typically used during manufacturing test and may include the ability to access chip-level registers. The console port may provide access to higher-level functions and may be used to set initialization parameters. It is generally not necessary for the operating system to be functioning in order to utilize the console port. The application card  300 A and  300 B may access the diagnostic port and console port using separate transceivers, or a multiplexer may be used to select the port being connected to the bus  402 A and  402 B. Each port may support diagnostic and console port functions, thereby providing dual functionality.  
         [0027]     As previously noted, only one application card  300 A or  300 B should transmit on each shared serial bus  402 A and  402 B at a time. Shelf management card  200 A or  200 B may instruct the appropriate application card  300 A or  300 B to transmit on the bus by transmitting a command that includes the identity the target application card  300 A or  300 B. The command may be transmitted on shared serial bus  402 A or  402 B and the application card identity may be based on the slot location of the application card  300 A or  300 B. For example, a unique slot ID may be hard-coded into a midplane connector at each slot location, thereby permitting application card  300 A or  300 B to determine its slot location in the shelf, even if application card  300 A or  300 B has limited functionality. Since the receiver portion of transceiver  308  of each application card  300 A and  300 B can simultaneously access each shared serial bus  402 A and  402 B, a command sent by the shelf manager card  200 A or  200 B may be received by each application card  300 A and  300 B. Each application card  300 A and  300 B may process the command to determine the intended destination address and ignore the command if it is addressed to another card.  
         [0028]     The shelf assembly may also provide a separate management channel  404 A and  404 B for routing command messages and performing other management functions. Management channel  404 A and  404 B may be implemented using an IPMI architecture. The IPMI architecture includes a serial data signal and a serial clock signal. A bus master provides the clock signal, although IPMI supports multiple bus masters. Thus, any IPMI interface on an IPMI bus may act as a master to initiate communication with another IPMI interface.  
         [0029]     The IPMI architecture may also include a dedicated controller  304  for receiving and processing management commands. Using a dedicated controller  304  to process management commands rather than routing the management commands to application processor  302  provides increased reliability, since management commands can be received and processed even if application processor  302  is not functioning properly. Moreover, the IPMI controller may provide additional services, such as reporting an application processor failure to shelf manager  200 A or  200 B using management channel  404 A and  404 B.  
         [0030]      FIG. 4  is a block diagram of a midplane of a PICMG 3.0 compatible shelf assembly including a shared serial bus for external diagnostics and console connections in accordance with an embodiment of the subject matter described herein. While the invention is described with reference to a PICMG 3.0 compatible shelf, it should be appreciated that the description of the invention as set forth herein may be applied to other equipment shelf systems. Accordingly, the invention should not be limited to any particular shelf architecture.  
         [0031]     Referring to  FIG. 4 , the shelf assembly provides seventeen card slots arranged in parallel along the midplane. Shelf assemblies typically provide a card slot for a shelf controller and the remaining sixteen slots are available for user devices. The PICMG standard provides for redundant shelf management controller (ShMC) cards  200 A and  200 B having a management interface to each card slot in the shelf. The ShMC card defined by PICMG is a half-height card, thus both ShMC cards may reside in portions of the same physical slot thereby providing redundancy without reducing the number of available application card slots.  
         [0032]     As previously noted, the midplane supports the connectivity for Zone  1  and Zone  2 . Zone  1  provides access to a power bus  503  and supports an interface to a management channel  505  from the ShMC to each slot. The power bus  503  may provide access from each slot to at least one power supply. The management channel  404  may be used by various cards in a shelf to obtain initialization information and to conduct management functions, such as card diagnostics. Each card in the shelf may include an intelligent platform management controller (IPMC) that communicates with the ShMC. Zone  1  may also provide a shelf address  507 , which may be used in conjunction with other information to identify and/or assign a unique address to each application card in a multi-shelf system.  
         [0033]     Zone  2  supports clock and/or data transport across four separate interfaces. These interfaces include a base interface  509 , a fabric interface  511 , an update channel interface  513 , and a synchronization clock interface  515 . Base interface  509  may support 10/100/1000Base-T Ethernet connections between application cards in a shelf. Each application node slot may have a single, point-to-point base channel connection to each of two base hub slots  517 A and  517 B. Base interface  509  may also support other Ethernet-based services, such as Tekelec&#39;s proprietary IMT management bus supported by IMT hub cards  519 A and  519 B.  
         [0034]     Fabric interface  511  supports non-Ethernet-based communication between cards. Redundant fabric interface cards  521 A and  521 B may be provided in the shelf assembly. Each fabric interface card may include configuration information for application cards residing in the remaining card slots, and facilitate non-Ethernet-based communication between application cards. As shown in  FIG. 4 , redundant fabric interface cards  521 A and  521 B reside in slot  7  and slot  8 . It should be appreciated that non-PICMG compatible shelf architectures may not require the use of fabric interface cards, thus making these slots available for use by application cards.  
         [0035]     Update channel interface  513  provides differential signal pairs for communication between slots. The signal pairs may be configured for point-to-point communication between two slots, with a card in one slot transmitting on a first signal pair and the other card transmitting on a second signal pair. In embodiments of the subject matter described herein, one card, such as the ShMC, may be designated as the bus master and the signal pairs may be designated as a transmit pair and a receive pair with respect to the bus master. It should be appreciated that a card other than the ShMC may act as the bus master. For example, if two application cards are communicating using update channel interface  513 , one card may be designated the master and an externally accessible console port on the master application card may be used to interface with the other application card. The ShMC may communicate this designation to the application card using management channel  404 .  
         [0036]     It will be understood that various details of the invention may be changed without departing from the scope of the invention. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the invention is defined by the claims as set forth hereinafter.

Technology Category: 3