Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to semiconductor devices, and more specifically to power management of semiconductor devices. 
         [0003]    2. Background Art 
         [0004]    With the increasing performance and attendant thermal dissipation requirements of modern semiconductor devices, effective power management emerges as a growing concern. In particular, for applications running continuously around the clock, such as heavily loaded data center applications where many processes may run in parallel, even small optimizations in power consumption can lead to large savings in operating costs. Besides practical cost considerations, providing “green” solutions is also desirable to demonstrate corporate responsibility and generate customer goodwill. 
         [0005]    Conventionally, power management algorithms have focused on short term or immediate workloads. However, using this narrow focus may lead to constantly fluctuating voltage adjustments and inefficiencies resulting from overestimating or underestimating long-term workloads. For example, voltage and frequency may be unnecessarily ramped up beyond a performance level necessary to meet long-term deadlines, resulting in wasted power consumption. 
         [0006]    Accordingly, there is a need in the art to provide power management for semiconductor devices that can provide higher efficiency than conventional methods of power management. 
       SUMMARY OF THE INVENTION 
       [0007]    There is provided a method of scheduler assisted power management for semiconductor devices, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    The features and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, wherein: 
           [0009]      FIG. 1  shows a diagram of an exemplary semiconductor processing system using scheduler assisted power management, according to one embodiment of the present invention; 
           [0010]      FIG. 2  shows a diagram of an exemplary semiconductor processing system using scheduler assisted power management, according to another embodiment of the present invention; and 
           [0011]      FIG. 3  is a flowchart presenting a method of scheduler assisted power management for semiconductor devices, according to one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0012]    Although the invention is described with respect to specific embodiments, the principles of the invention, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the invention described herein. Moreover, in the description of the present invention, certain details have been left out in order to not obscure the inventive aspects of the invention. The details left out are within the knowledge of a person of ordinary skill in the art. The drawings in the present application and their accompanying detailed description are directed to merely example embodiments of the invention. To maintain brevity, other embodiments of the invention which use the principles of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings. It should be borne in mind that, unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. 
         [0013]      FIG. 1  shows a diagram of an exemplary semiconductor processing system using scheduler assisted power management, according to one embodiment of the present invention. Network traffic routing system  100  of  FIG. 1  includes Ethernet MAC  110 , scheduler block  120 , shaper  125 , power management block  130 , CPU block  140 , auxiliary block  145 , and bus  150 . Scheduler block  120  includes processor  121  and Ethernet MAC  110  includes queues  115   a - 115   h.    
         [0014]    Scheduler block  120  may use processor  121  to provide scheduling services for queues  115   a - 115   h  of Ethernet MAC  110 , which may be supported by a DMA (Direct Memory Access) engine for queuing outgoing Tx (transmit) data packet workloads. While eight queues are depicted in  FIG. 1 , alternative embodiments may support different numbers of queues. Scheduler block  120  may prioritize particular queues based on data packet content type, such as voice, data, or video content, or perform other QoS (Quality of Service) adjustments, for example to conform with the Home Gateway Initiative (HGI) version 1.0. In this manner, scheduling rules can be formulated to service real-time media streams, teleconferencing, video gaming, or other latency sensitive applications with a higher priority class, whereas normal data transfers or other latency insensitive streams may be serviced with a lower priority class. Alternatively or additionally, priority classes may be determined based on the severity of resulting packet loss. For example, if a few packets of real-time audio streams are not serviced, jarring audio dropouts or artifacts may result. On the other hand, if a few packets of real-time video streams are not serviced, then minor visual artifacting or missing pixels may occur, which may be less distracting to users than audio defects. Thus, audio packets might be placed in a higher priority class than video packets. 
         [0015]    As shown in  FIG. 1 , several processing blocks are included in network traffic routing system  100  to process queues  115   a - 115   h . Shaper  125  may be directed to specify queue processing delays to moderate the flow of queues  115   a - 115   h  and enforce the above QoS rules. CPU block  140  may comprise a plurality of processing cores configured to read network packets from Ethernet MAC  110  for processing into queues  115   a - 115   h  over bus  150 . Auxiliary block  145  may perform additional services such as supporting IPsec (Internet Protocol Security) for encryption and authentication of network packets. 
         [0016]    Scheduler block  120  may then interface with power management block  130  to manage the above processing blocks in the most power efficient manner. In order to process queues  115   a - 115   h  in a timely fashion, voltages and operating frequencies of shaper  125 , CPU block  140 , and auxiliary block  145  may be adjusted up or down by power management block  130  as necessary. However, to avoid unnecessary power usage, voltages and frequencies may be ramped up only as much as necessary to safely meet queue processing completion deadlines, thus optimizing power usage. For idle periods when queues  115   a - 115   h  are mostly empty, some cores of CPU block  140  may also be turned off completely or provided with zeroed voltage for extra power savings. In this manner, the components of network traffic routing system  100  are intelligently power optimized based on the dynamic workloads presented by queues  115   a - 115   h.    
         [0017]    While the scheduler assisted power management of the present invention has been illustrated using a network traffic routing system, the present invention is not limited to this particular embodiment and is generally applicable to all kinds of processing blocks requiring power management. For example,  FIG. 2  shows a diagram of an exemplary semiconductor processing system using scheduler assisted power management, according to another embodiment of the present invention. 
         [0018]    Computing system  200  of  FIG. 2  includes processor  240  and operating system  260 . Processor  240  includes power management block  230  and cores  245   a - 245   b . Operating system  260  includes threads  265   a - 265   b  and scheduler  220 . 
         [0019]    As shown in  FIG. 2 , processor  240  uses conventional on-die power management to control voltages for cores  245   a - 245   b . Operating system  260  executes on processor  240  and includes a software scheduler  220 , which is currently executing threads  265   a - 265   b . As shown in  FIG. 2 , thread  265   a  is assigned to core  245   a  and thread  265   b  is assigned to core  245   b . While processor  240  is shown as a dual-core processor, alternative embodiments may include additional cores. 
         [0020]    One example application for  FIG. 2  might be real-time video encoding for streaming broadcast. Thread  265   a  may then comprise a real-time video encoding thread, whereas thread  265   b  may comprise a communications thread to transfer the resulting encoded video over a network. Scheduler  220  thus has detailed completion deadline data for the workloads represented by threads  265   a - 265   b , and may direct power management to block  230  to adjust voltages for cores  245   a - 245   b  accordingly. For example, depending on task parameters such as video encoding bit-rate, resolution, and other factors affecting processing workload, the voltage and frequency for core  245   a  may be adjusted upwards to meet a minimum performance threshold for encoding in real-time without buffer underruns. Similarly, since thread  265   b  only needs to transfer a small amount of network data compared to the processor intensive task of video encoding, voltage and frequency for core  245   b  may be adjusted downwards until just enough performance is provided to service the network connection. In this manner, performance and power consumption is best optimized to meet application requirements. 
         [0021]      FIG. 3  is a flowchart presenting a method of scheduler assisted power management for semiconductor devices, according to one embodiment of the present invention. Certain details and features have been left out of flowchart  300  of  FIG. 3  that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more sub-steps or may involve specialized equipment, as known in the art. While steps  310  through  330  shown in flowchart  300  are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown in flowchart  300 . 
         [0022]    Referring to step  310  of flowchart  300  in  FIG. 3  and network traffic routing system  100  of  FIG. 1 , step  310  of flowchart  300  comprises processor  121  of scheduler block  120  accessing queues  115   a - 115   h  describing Tx network packets to be processed by shaper  125 , CPU block  140 , and auxiliary block  145 . This workload data provides scheduler block  120  with the information necessary to make power management to decisions. 
         [0023]    Referring to step  320  of flowchart  300  in  FIG. 3  and network traffic routing system  100  of  FIG. 1 , step  320  of flowchart  300  comprises processor  121  of scheduler block  120  analyzing queues  115   a - 115   h  to determine a power management policy. As previously described, queues  115   a - 115   h  may be optimized according to particular QoS rules to prioritize real-time latency sensitive traffic groups above latency tolerant data groups. In addition, the power management policy may be configured to provide only as much performance as necessary to expedite queues  115   a - 115   h  according to said QoS rules, providing optimal power efficiency. 
         [0024]    Referring to step  330  of flowchart  300  in  FIG. 3  and network traffic routing system  100  of  FIG. 1 , step  330  of flowchart  300  comprises processor  121  of scheduler block  120  applying the power management policy from step  320  to shaper  125 , CPU block  140 , and auxiliary block  145 . As previously described, the power management policy may specify increasing or decreasing voltages and operating frequencies of the above processing blocks, or may even completely turn off particular processing blocks such as processor cores of CPU block  140 . In this manner, the above processing blocks are optimized to provide sufficient application performance with finely tuned power consumption, which provides greater power savings compared to conventional methods of power management that do not integrate workload data from a scheduler. 
         [0025]    From the above description of the embodiments of the present invention, it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the present invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.

Technology Category: 4