Patent Document

BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates generally to amplifier circuits, and more particularly to improving amplifier performance by overcoming difficulties caused by capacitance associated with the bulk electrodes of the input field effect transistors.  
         [0002]     Bulk electrode capacitance associated with input stages of high-speed operational amplifiers reduces the amplifier slew rates and also causes unsymmetrical operational amplifier responses to the positive-going and negative-going edges of large-magnitude input step signals. Prior Art  FIG. 1  illustrates an operational amplifier including a differential input transconductance stage  2  including input transistors  6 A and  6 B having their sources connected by conductor  8  to a tail current source  7 . The bulk electrodes of input transistors  6 A and  6 B are connected by conductor  10  to the positive supply voltage VDD. The drains of input transistors  6 A and  6 B are connected to inputs of a prior art folded cascode stage  3 , the outputs of which are connected to the inputs of a conventional class AB stage  4 .  
         [0003]     In the circuit of Prior Art  FIG. 1 , the bulk electrode capacitance Cb of the bulk electrodes of the input transistors does not significantly affect the signal path of the input signal (Vin=Vin+−Vin−) through the operational amplifier. However, the CMRR (common mode rejection ratio) of the operational amplifier is degraded due to mismatching between input transistors  6 A and  6 B, since the CMRR is a function of the source-drain voltages of the input transistors  6 A and  6 B.  
         [0004]     Prior Art  FIG. 2  shows another configuration of a similar transconductance input stage  2 A in which the bulk electrodes of its of input transistors  6 A and  6 B are connected by conductor  10 A to the common source conductor  8 , rather than to VDD as in  FIG. 1 . A cascode transistor  11 A is coupled between the drain of input transistor  6 A and output conductor  9 A, with its gate also connected to Vin−, and a cascode transistor  11 B is coupled between the drain of input transistor  6 B and output conductor  9 B, with its gate connected to Vin+. Cascode transistors  11 A and  11 B provide improved CMRR of the operational amplifier by providing a relatively constant drain-source voltage across input transistors  6 A and  6 B. However, the circuit configuration of Prior Art  FIG. 2  causes the bulk electrode capacitance Cb to be coupled so as to directly load the amplifier signal path, thereby degrading the large signal response of the amplifier by causing slower settling times and unsymmetrical slew rates.  
         [0005]     Specifically, if the bulk electrodes of the input transistors are connected directly to their sources as shown in  FIG. 2 , the total bulk electrode capacitance Cb can be considered to be added directly to the signal path capacitance. This causes the above-mentioned unsymmetrical slewing operation wherein the rising edge of Vout is slower than the falling edge. For most operational amplifiers, the slew rate is determined by the total input stage tail current divided by the Miller compensation capacitance C M . If all of the input stage tail current flows to the Miller compensation capacitance C M , it does not matter whether that occurs in response to a rising edge or falling edge of the operational amplifier step input pulse. However, if the bulk electrode capacitance Cb of the input transistors  6 A and  6 B is connected directly to their sources, the total increased capacitance associated with the bulk electrodes of the input transistors  6 A and  6 B must be charged or discharged during slewing operation and therefore causes slower slewing rates.  
         [0006]     During the rising edge of the amplifier input voltage, some of the tail current will go to the source capacitance of input transistors  6 A and  6 B, so less of the tail current is available to charge the Miller compensation capacitance C M  of the operational amplifier output stage  4 , resulting in a decreased slew rate.  
         [0007]     During the falling edge of the input step pulse, the voltage of the common source conductor  8  of input transistors  6 A and  6 B will decrease. The total capacitance on common source conductor  8 , including source capacitances of input transistors  6 A and  6 B and the total bulk electrode capacitance Cb, will be discharged through input transistors  6 A and  6 B and conductors  9 A and  9 B and through the signal path of the folded cascode stage  3  to the Miller compensation capacitances C M  and will produce a current that is substantially greater in magnitude than the tail current I 1  of input stage  2 A. This causes a substantially faster slew rate than for the rising edge of the input step voltage pulse. Thus, the slewing rates in response to the rising and falling edges of a step voltage input pulse are unsymmetrical.  
         [0008]     Conventional buffer circuits may have been previously used to drive the bulk electrodes of operational amplifier input stage field effect transistors, but if so, it would have been found that this approach has significant difficulties because some of the tail current of the conventional buffer circuit would have been leaked to the integrated circuit substrate or ground, i.e., wasted, and therefore resulting in less of the tail current being available to drive the bulk electrode capacitance Cb. This would have resulted in excessive power consumption if the tail current had been substantially increased to drive the bulk electrode capacitance in order to increase output slew rates.  
         [0009]     Thus, there is an unmet need for an amplifier input stage that provides symmetrical slew rates.  
         [0010]     There also is an unmet need for an amplifier input stage that provides symmetrical slew rates and fast signal settling times.  
         [0011]     There also is an unmet need for an amplifier input stage that provides symmetrical slew rates and fast signal settling times without unacceptably increasing power consumption.  
       SUMMARY OF THE INVENTION  
       [0012]     It is an object of the invention to provide an amplifier input stage that provides symmetrical slew rates.  
         [0013]     It is another object of the invention to provide an operational amplifier including a transconductance input stage that provides symmetrical amplifier slew rates and fast signal settling times.  
         [0014]     It is another object of the invention to provide an operational amplifier including an input stage that provides symmetrical amplifier slew rates and fast signal settling times without unacceptably increasing power consumption.  
         [0015]     Briefly described, and in accordance with one embodiment, the present invention provides amplifier circuitry ( 100 ) having an input stage ( 2 B) which includes a transconductance stage ( 2 C) including first ( 6 A) and second ( 6 B) input transistors each having a source, a drain, a gate, and a bulk electrode, and a first tail current source (I 1 ) coupled to the sources of the first ( 6 A) and second ( 6 B) input transistors, the gates of the first ( 6 A) and second ( 6 B) input transistors being coupled to first (Vin−) and second (Vin+) input voltage signals, respectively. The input stage ( 2 B) also includes a bulk electrode capacitance driver circuit ( 15 ) including third ( 60 A) and fourth ( 60 B) input transistors and first ( 111 A) and second ( 111 B) cascode transistors each having a source, a drain, a gate, and a bulk electrode, and a second tail current source (I 2 ) coupled to the sources and bulk electrodes of the third ( 60 A) and fourth ( 60 B) input transistors and also to the bulk electrodes of the first ( 6 A) and second ( 6 B) input transistors. The gates of the third ( 60 A) and fourth ( 60 B) input transistors are coupled to the first (Vin−) and second (Vin+) input voltage signals, respectively. The gates of the first ( 111 A) and second ( 111 B) cascode transistors are cross-coupled to the second (Vin+) and first (Vin−) input voltage signals, respectively. The source and drain of the first cascode transistor ( 111 A) are coupled to the drain of the third input transistor ( 60 A) and a reference voltage conductor (GND), respectively, and the source and drain of the second cascode transistor ( 111 B) are coupled to the drain of the fourth input transistor ( 60 B) and the reference voltage conductor (GND), respectively. A first output conductor ( 9 A) is coupled to the drain of the first input transistor ( 6 A) and a second output conductor ( 9 B) is coupled to the drain of the second input transistor ( 6 B).  
         [0016]     In the described embodiment, the transconductance stage ( 2 C) includes third ( 11 A) and fourth ( 11 B) cascode transistors, wherein a source and drain of the third cascode transistor ( 11 A) are coupled to the drain of the first input transistor ( 6 A) and the first output conductor ( 9 A), respectively. A source and drain of the fourth cascode transistor ( 11 B) are coupled to the drain of the second input transistor ( 6 B) and the second output conductor ( 9 B), respectively. Gates of the third ( 11 A) and fourth ( 11 B) cascode transistors are coupled to the first (Vin−) and second (Vin+) input voltage signals, respectively. The first ( 9 A) and second ( 9 B) output conductors are coupled to inputs of a folded cascode stage ( 3 ), the output of which is coupled to the input of a class AB output stage ( 4 ).  
         [0017]     In one embodiment, the invention provides a method of operating an amplifying circuit to improve speed and symmetry of slewing operation, including providing a transconductance stage ( 2 C) including first ( 6 A) and second ( 6 B) input transistors and a first tail current source (I 1 ) coupled to sources of the first ( 6 A) and second ( 6 B) input transistors, drains of the first ( 6 A) and second ( 6 B) input transistors being coupled to first ( 9 A) and second ( 9 B) output conductors, respectively, of the transconductance stage, and providing a bulk electrode capacitance driver circuit ( 15 ) including third ( 60 A) and fourth ( 60 B) input transistors and first ( 111 A) and second ( 111 B) cascode transistors and a second tail current source (I 2 ) coupled to the sources and bulk electrodes of the third ( 60 A) and fourth ( 60 B) input transistors and also to bulk electrodes of the first ( 6 A) and second ( 6 B) input transistors, drains of the first ( 111 A) and second ( 111 B) cascode transistors being coupled to a reference voltage conductor (GND), sources of the first ( 111 A) and second ( 111 B) cascode transistors being coupled to drains of the third ( 60 A) and fourth ( 60 B) input transistors, respectively. This embodiment of the invention also includes applying first (Vin−) and second (Vin+) signals which constitute a differential input signal (Vin) of at least a predetermined magnitude between various gates of the first ( 6 A), second ( 6 B), third ( 60 A) and fourth ( 60 B) input transistors and the first ( 111 A) and second ( 111 B) cascode transistors to either (1) simultaneously turn on the first ( 6 A) and third ( 60 A) input transistors and the second ( 111 B) cascode transistor and turn off the second ( 6 B) and fourth ( 60 B) input transistors and the first ( 111 A) cascode transistor, or (2) simultaneously turn the first ( 6 A) and third ( 60 A) input transistors and the second ( 111 B) cascode transistor off and turn on the second ( 6 B) and fourth ( 60 B) input transistors and the first ( 111 A) cascode transistor, depending on the polarity of the differential input signal (Vin), so as to prevent tail current from the second tail current source (I 2 ) from flowing into the reference voltage conductor (GND) and being wasted while the magnitude of the input signal (Vin) exceeds the predetermined magnitude.  
         [0018]     In one embodiment, the invention provides circuitry ( 100 ) including a transconductance stage ( 2 C) which includes first ( 6 A) and second ( 6 B) input transistors and a first tail current source (I) coupled to sources of the first ( 6 A) and second ( 6 B) input transistors, drains of the first ( 6 A) and second ( 6 B) input transistors being coupled to first ( 9 A) and second ( 9 B) output conductors, respectively, of the transconductance stage. A bulk electrode capacitance driver circuit ( 15 ) includes third ( 60 A) and fourth ( 60 B) input transistors and first ( 111 A) and second ( 111 B) cascode transistors and a second tail current source (I 2 ) coupled to the sources and bulk electrodes of the third ( 60 A) and fourth ( 60 B) input transistors and also to bulk electrodes of the first ( 6 A) and second ( 6 B) input transistors, drains of the first ( 11 A) and second ( 111 B) cascode transistors being coupled to a reference voltage conductor (GND), sources of the first ( 111 A) and second ( 111 B) cascode transistors being coupled to drains of the third ( 60 A) and fourth ( 60 B) input transistors, respectively. This embodiment of the invention also includes means for applying first (Vin−) and second (Vin+) signals which constitute a differential input signal (Vin) of at least a predetermined magnitude between various gates of the first ( 6 A), second ( 6 B), third ( 60 A) and fourth ( 60 B) input transistors and the first ( 111 A) and second ( 111 B) cascode transistors to either (1) simultaneously turn on the first ( 6 A) and third ( 60 A) input transistors and the second ( 111 B) cascode transistor and turn off the second ( 6 B) and fourth ( 60 B) input transistors and the first ( 111 A) cascode transistor, or (2) simultaneously turn the first ( 6 A) and third ( 60 A) input transistors and the second ( 111 B) cascode transistor off and turn on the second ( 6 B) and fourth ( 60 B) input transistor and the first ( 111 A) cascode transistors, depending on the polarity of the differential input signal (Vin), so as to prevent tail current from the second tail current source (I 2 ) from flowing into the reference voltage conductor (GND) and being wasted while the magnitude of the input signal (Vin) exceeds the predetermined magnitude.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]      FIG. 1  is a schematic diagram of a prior art operational amplifier in which the bulk electrodes of the input stage transistors are connected to the positive supply voltage.  
         [0020]      FIG. 2  is a schematic diagram of a prior art operational amplifier in which the bulk electrodes of the input stage transistors are connected to their source electrodes.  
         [0021]      FIG. 3  is a schematic diagram of an operational amplifier including a bulk electrode driver circuit in accordance with the present invention.  
         [0022]      FIG. 4  is an enlarged schematic diagram of the input stage and bulk driver circuit shown in  FIG. 3 .  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]     The present invention provides a low-power bulk electrode driver circuit for driving the bulk electrodes of the input transistors of an amplifier circuit. When the capacitance Cb associated with the bulk electrodes is driven by the bulk electrode driver circuit, the bulk electrode capacitance has minimal effect on the main signal path through the amplifier. This results in substantial improvements in the slew rates and settling times of the amplifier, and also results in more symmetrical slew rates of the amplifier circuit.  
         [0024]      FIG. 3  shows an amplifier  100  including an input stage  2 B which drives a known prior art folded cascode stage  3  that is followed by a conventional class AB output stage  4 . Input stage  2 B includes a transconductance input stage  2 C which receives input signals Vin+ and Vin- and, in response thereto, produces output currents in conductors  9 A and  9 B. In accordance with the present invention, input stage  2 B also includes bulk capacitance driver circuit  15 , which also receives input signals Vin+ and Vin−, and, in response thereto, produces a signal on conductor  16 , which is connected to the bulk electrodes of, and drives the bulk capacitance Cb associated with, the bulk electrodes of the input transistors of both transconductance input stage  2 C and bulk capacitance driver circuit  15 . The details of transconductance input stage  2 C and bulk capacitance driver  15  are shown in  FIG. 4 .  
         [0025]     Referring to  FIG. 4 , transconductance input stage  2 C includes tail current source  7  coupled between VDD and a common source conductor  8  that is connected to the source electrodes of P-channel input transistors  6 A and  6 B. Tail current source  7  supplies a constant tail current I 1  to the sources of input transistors  6 A and  6 B. The gates of input transistors  6 A and  6 B are connected to Vin− and Vin+, respectively. The bulk electrodes of input transistors  6 A and  6 B, which have an associated bulk capacitance Cb 1 , are connected to bulk capacitance driver output conductor  16 . The drain of input transistor  6 A is connected to the source and bulk electrodes of a P-channel cascode transistor  11 A. The gate of cascode transistor  11 A is connected to Vin− and its drain is connected to conductor  9 A. The drain of input transistor  6 B is connected to the source and bulk electrodes of a P-channel cascode transistor  11 B, and the gate of cascode transistor  11 B is connected to Vin+ and its drain is connected to conductor  9 B. (Note that use of cascode transistors  11 A and  11 B substantially improves the CMRR of operational amplifier  100 , but these transistors can be omitted if CMRR is acceptable without them.)  
         [0026]     Bulk capacitance driver circuit  15  includes tail current source  7 A coupled between VDD and bulk driver circuit output conductor  16 , which is also connected to the source and bulk electrodes of P-channel input transistors  60 A and  60 B of bulk capacitance driver circuit  15 . Tail current source  7 A produces a constant tail current I 2  which is scaled relative to tail current I 1  of transconductance input stage  2 C. A parasitic bulk capacitance Cb 2  is associated with the bulk electrodes of input transistors  60 A and  60 B. The gate electrode of input transistor  60 A is connected to Vin− and the gate electrode of input transistor  60 B is connected to Vin+, where a differential input signal Vin to be amplified by operational amplifier  100  is given by the expression Vin=Vin+−Vin−. The source and bulk electrodes of a P-channel cascode transistor  111 A are connected to the drain of input transistor  60 A, and the gate of cascode transistor  111 A is connected to Vin+. The source and bulk electrodes of a P-channel cascode transistor  111 B are connected to the drain of input transistor  60 B, and the gate of cascode transistor  111 B is connected to Vin−. The drains of cascode transistors  111 A and  111 B are connected to ground.  
         [0027]     Thus, the gates of cascode transistors  111 A and  111 B can be considered to be “cross-coupled” to Vin+ and Vin− relative to the way the gates of input transistors  60 A and  60 B are coupled to Vin− and Vin+.  
         [0028]     The various transistor geometries are selected such that the current densities in input transistors  60 A and  60 B of bulk electrode driver circuit  15  are essentially the same as in the corresponding input transistors  6 A and  6 B of transconductance input stage  2 C. Consequently, the VGS (gate-to-source) voltages and the bulk-to-source voltages of input transistors  6 A and  6 B of transconductance input stage  2 C are very close to the corresponding VGS voltages of input transistors  60 A and  60 B of bulk capacitance driver  15 . Therefore, the voltage on common source conductor  8  in transconductance input stage  2 C is very close to the voltage produced on bulk capacitance driver output conductor  16 . However, it should be noted that the main advantages of this invention, including faster, more symmetrical slewing are achieved, without substantially increased power dissipation, even if the current densities in  6 A,  6 B,  60 A and  60 B and their VGS voltages are somewhat unequal.  
         [0029]     Under “large signal transient” conditions wherein the difference between Vin+ and Vin− and the “cross-coupled” connection of cascode transistors  111 A and  111 B to Vin+ and Vin−, respectively, prevents any of the tail current I 2  of bulk capacitance driver circuit  15  from flowing into ground. (See the earlier discussion of problems of using a conventional buffer to drive bulk electrodes of field effect input transistors.) For example, if the transient difference between Vin+ and Vin− causes input transistor  60 B to be turned off, then cascode transistor  111 A will also be turned off. Therefore, even though input transistor  60 A is turned on hard, cascode transistor  111 A will be turned off. Consequently, even though input transistor  60 A is turned on hard, cascode transistor  111 A blocks any of the tail current I 2  from flowing through input transistor  60 A to ground. Since both input transistor  60 B and cascode transistor  111 A are off during the transient, all of the tail current I 2  flows into the parasitic bulk capacitances Cb 1  and Cb 2 , which is the ideal situation because none of tail current I 2  is “wasted” by flowing into ground. Power consumption of bulk capacitance driver  15  therefore is minimized, because only a minimal amount of tail current I 2  is used to drive the bulk capacitances Cb 1  and Cb 2 .  
         [0030]     The above operation is in direct contrast to operation which would be achieved if an ordinary buffer were to be used to drive the bulk capacitance Cb 1  of transconductance input stage  2 C. For example, without the cross-coupling of the gates of cascode transistors  111 A and  111 B shown in bulk driver circuit  15  of  FIG. 4  (that is, if the gates of cascode transistors  11 A and  111 B are connected to Vin− and Vin+ instead of as shown in  FIG. 4 ), a large positive transient swing of Vin+ relative to Vin− would turn input transistor  60 B and cascode transistor  111 B off and would cause input transistor  60 A and cascode transistor  111 A to be turned on. Initially, all of the tail current  7 A would flow through conductor  16  toward transistor  60 A, causing the voltage of conductor  16  to rise during the transient. Without the cross-coupling of the present invention, some of the constant tail current I 2  would flow through input transistor  60 A and cascode transistor  111 A (both of which would be turned on) to ground during the transient and the rest would flow into bulk electrode capacitances Cb 1  and Cb 2  as the source voltage on conductor  16  would continue to rise until the end of the transient, after which the tail current  7 A all would flow through input transistor  60 A and cascode transistor  111 A to ground. More specifically, as transistors  60 B and  111 B are turned off, a current equal to one half of tail current I 2  begins immediately to charge the bulk electrode capacitances Cb 1  and Cb 2 . Then the voltage on conductor  16  starts to rise faster than the voltage on the gate of transistor  60 A, turning it on harder. That causes more of the tail current I 2  to flow through transistor  60 A to ground and therefore be wasted, and also causes less of the tail current I 2  to be available to continue charging bulk electrode capacitances Cb 1  and Cb 2 .  
         [0031]     Thus, the maximum current available to charge the bulk electrodes of the input transistors would be one half of the tail current I 2 , and it would diminish as the voltage on conductor  16  changes. By the end of this process, there would be no current charging the bulk electrode capacitances Cb 1  and Cb 2 , as all of the tail current I 2  would flow through transistor  60 A. All of the current which would flow to ground during the transient would have been wasted, resulting in substantially slower charging of the bulk electrode capacitances.  
         [0032]     In contrast, in the cross-coupled configuration shown in bulk electrode driver circuit  15  of  FIG. 4 , all of the parasitic bulk capacitance Cb 1  and Cb 2  of input transistors  6 A,  6 B,  60 A, and  60 B are driven by the constant tail current I 2 , so the bulk electrode capacitances Cb 1  and Cb 2  have relatively little effect on the large signal transient response of operational amplifier  100  of  FIGS. 3 and 4 . Symmetrical slewing and fast settling times of operational amplifier  100  therefore are achieved with use of a relatively small amount of additional integrated circuit chip area and with a relatively low additional amount of current compared to the additional amount that would be required if the connections between input transistors  60 A and  60 B and Vin+ and Vin− were to be reversed so that the connections were not “cross-coupled”.  
         [0033]     It should be noted that if a conventional buffer is used instead of bulk capacitance driver  15 , it is likely to be more complex than the four-transistor bulk capacitance driver circuit  15  of  FIG. 4 , and it may have to be biased by a greater tail current (and hence have greater power dissipation) to make up for the current that would be wasted without the cross-coupled transistors  111 A and  111 B, in order for the operational amplifier to have the same slewing performance as operational amplifier  100  of  FIG. 3 .  
         [0034]     The circuit configuration of bulk capacitance driver  15  is very simple compared to a conventional buffer circuit that one skilled in the art might consider using to drive the bulk electrodes of input transistors  6 A and  6 B, and may use substantially less current than would be required by a conventional buffer circuit. Furthermore, bulk electrode driver circuit  15  has rail-to-rail voltage swing capability.  
         [0035]     Referring again to  FIG. 3 , known folded cascode circuit  3  includes an N-channel current mirror which includes a diode-connected current mirror control transistor  32 , the drain and gate of which are connected to current source  33 , and also includes N-channel current mirror output transistors  20  and  24 , the sources of which are connected to ground. The drain of transistor  20  is connected by conductor  9 A to the source of N-channel cascode transistor  21 , the drain of which is connected to the drain of P-channel cascode transistor  22  and to the gates of P-channel current mirror transistors  23 ,  30  and  31 , the sources of which are connected to VDD. The drain of transistor  24  is connected by conductor  9 B to the sources of N-channel cascode transistors  25  and  26 , which split the current through transistor  24 . Current mirror output transistors  20  and  24  can be considered to be active load devices of transconductance input stage  2 C which converts the signal currents in conductors  9 A and  9 B to corresponding voltages on the drain of cascode transistor  21  and on the drains of N-channel cascode transistors  25  and  26 .  
         [0036]     The drain of cascode transistor  25  is connected by conductor  27 A to the drain of P-channel cascode transistor  28 , the source of which is connected to the drain of current mirror output transistor  30 . The drain of cascode transistor  26  is connected by conductor  27 B to the drain of P-channel cascode transistor  29 , the source of which is connected to the drain of current mirror transistor  31 . The gates of cascode transistors  21  and  25  are biased by a reference voltage produced on conductor  43  by a reference voltage circuit including current source  37  coupled by conductor  43  to the gate and drain of N-channel transistor  35 , the source of which is connected to ground. The gate of cascode transistor  26  is biased by a reference voltage produced on conductor  44  by a reference circuit including current source  36  which is also coupled by conductor  44  to the drain and gate of N-channel transistor  34 , the source of which is connected to ground. The gates of P-channel cascode transistors  22 ,  28  and  29  are biased by a reference voltage on conductor  42  produced by a reference voltage circuit including a current source  39  coupled by conductor  42  to the drain and gate of a P-channel transistor  38  having its source connected to VDD.  
         [0037]     Class AB stage  4  includes P-channel output transistor  45  having its source connected to VDD, its gate connected to conductor  27 A, and its drain connected to Vout. A Miller compensation capacitor C M  is coupled in series with a low-value resistor  40  between the gate and drain of output transistor  45 . A N-channel transistor  46  has its source connected to ground, its drain connected to Vout, and its gate connected to conductor  27 B. A Miller compensation capacitor C M  is coupled in series with a low-value resistor  41  between the gate and drain of output transistor  46 . Low value resistors  40  and  41  are provided in series with the Miller gate-drain capacitances C M  associated with class AB output transistors  45  and  46  to ensure amplifier stability. Transistors  24 ,  25 ,  26 ,  28 ,  29 ,  30  and  31  operate to split the current through current mirror output transistor, 24 causing the signal on conductor  27 A to drive P-channel output transistor  45  and causing the signal on conductor  27 B to drive N-channel output transistor  46 . The currents through current mirror output transistors  20  and  24  can be considered to be DC currents, and the AC signal current in conductor  9 A can be considered to flow through cascode transistor  21 , and the AC signal currents in conductor  9 B can be considered to be split through cascode transistors  25  and  26 , respectively. The currents of current sources  36  and  37  are selected so that the voltages on the gates of transistors  25  and  26  cause the gate voltage of the P-channel output transistor  45  to be higher than the gate voltage of N-channel output transistor  46  so as to prevent overly large currents from flowing through both of output transistors  45  and  46 , to thereby provide ordinary class AB output stage control.  
         [0038]     It should be appreciated that input stage  2 B of  FIGS. 3 and 4  may be used in conjunction with a variety of other kinds of output stages.  
         [0039]     Preferably, the tail current source  7 A, input transistors  60 A and  60 B, and cascode transistors  111 A and  111 B of bulk capacitance driver  15  are substantially smaller than, and scaled by a suitable ratio to, tail current source  7 , input transistors  6 A and  6 B, and cascode transistors  11 A and  11 B, respectively, of transconductance input circuit  2 C. Specifically, tail current source  7 A, input transistors  60 A and  60 B, and cascode transistors  111 A and  111 B preferably are scaled relative to current source  7 , input transistors  6 A and  6 B, and cascode transistors  11 A and  11 B, respectively, by a ratio such that the VGS voltages of input transistors  6 A and  6 B of transconductance input stage  2 A are equal to the corresponding VGS voltages of input transistors  60 A and  60 B of bulk driver circuit  15 , respectively, so that the bulk voltage of input transistors  6 A and  6 B on conductor  16  is essentially equal to the source voltage on common source conductor  8 .  
         [0040]     After a large voltage transient is over, input transistors  60 A and  60 B and input transistors  6 A and  6 B are turned on equally, and cascode transistors  111 A and  111 B also are turned on equally. Under these conditions, the “cross coupling” of cascode transistors  111 A and  111 B is of no effect. Therefore, the cross coupling is very advantageous during transitions, and has no disadvantages during stable, i.e. non-transient, conditions.  
         [0041]     Thus, the bulk electrode driver of the present invention has the advantages that it does not cause loading of the signal path of an amplifier, allows use of a small value of tail current I 2  to accomplish driving the bulk terminals of the input transistors of the amplifier, thereby reducing power dissipation, and provides faster signal settling times and faster and more symmetrical slewing operation of the operational amplifier.  
         [0042]     While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from its true spirit and scope. It is intended that all elements or steps which are insubstantially different from those recited in the claims but perform substantially the same functions, respectively, in substantially the same way to achieve the same result as what is claimed are within the scope of the invention.

Technology Category: 5