Patent Document

BACKGROUND OF THE INVENTION  
       [0001]     1. Technical Field  
         [0002]     The present invention relates to semiconductor transistors, and more specifically, to semiconductor transistors having embedded strained source/drain regions.  
         [0003]     2. Related Art  
         [0004]     The mobility of holes and electrons created in doped regions (e.g., channel and source/drain regions) of a transistor affects the switching speed of that transistor. Higher mobility of holes and electrons will result in higher switching speed for the transistor. Therefore, there is a need for a semiconductor transistor structure (and a method for forming the same) that has a high mobility for electrons and holes created in doped regions of the transistor.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention provides a semiconductor structure, comprising (a) a substrate having a top substrate surface; (b) a channel region on the top substrate surface; (c) a gate dielectric region on the top substrate surface; (d) a gate electrode region on the top substrate surface, wherein the channel region is electrically insulated from the gate electrode region by the gate dielectric region; and (e) first and second source/drain regions on the top substrate surface, wherein the channel region is disposed between the first and second source/drain regions, wherein the channel region and the gate dielectric region are in direct physical contact with each other via an interfacing surface which is essentially perpendicular to the top substrate surface, wherein each of the first and second source/drain regions comprises both first and second semiconductor materials, and wherein the first and second semiconductor materials are different from each other.  
         [0006]     The present invention also provides a semiconductor structure, comprising (a) a substrate having a top substrate surface; (b) a channel region on the top substrate surface; (c) a gate dielectric region on the top substrate surface; (d) a gate electrode region on the top substrate surface, wherein the channel region is electrically insulated from the gate electrode region by the gate dielectric region; and (e) first and second source/drain regions on the top substrate surface, wherein the channel region is disposed between the first and second source/drain regions, wherein the channel region and the gate dielectric region are in direct physical contact with each other via an interfacing surface which is essentially perpendicular to the top substrate surface, wherein each of the first and second source/drain regions comprises both first and second semiconductor materials, wherein the first and second semiconductor materials are different from each other, wherein the first and second source/drain regions comprise first and second surfaces, respectively, wherein the first and second surfaces are essentially aligned with the interfacing surface between the channel region and the gate dielectric region, and wherein each of the first and second source/drain regions comprises a mixture of Si and Ge atoms.  
         [0007]     The present invention also provides a semiconductor structure fabrication method, comprising providing a structure which includes (a) a substrate having a top substrate surface, (b) a semiconductor region on the top substrate surface, the semiconductor region comprising a channel region, (c) a gate dielectric region on the substrate, wherein the channel region and the gate dielectric region are in direct physical contact with each other via an interfacing surface which is essentially perpendicular to the top substrate surface, and (d) a gate electrode region on the top substrate surface, wherein the channel region is electrically insulated from the gate electrode region by the gate dielectric region; and replacing first and second portions of the semiconductor region with third and fourth portions, respectively, wherein each of the third and fourth portions comprises dopants and a mixture of first and second semiconductor materials, wherein the channel region is disposed between the first and second portions, and wherein the first and second semiconductor materials are different from each other.  
         [0008]     The present invention provides a structure (and a method for forming the same) in which, the mobility of electron and hole is enhanced. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIGS. 1-16D  show the fabrication process for forming a structure, in accordance with embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0010]      FIGS. 1-16D  show the fabrication process for forming a structure  100 , in accordance with embodiments of the present invention.  
         [0011]     With reference to  FIG. 1  (cross-section view), in one embodiment, the fabrication process starts out with an SOI (silicon on insulator) substrate  105  comprising (i) a buried oxide (BOX) layer  110 , and (ii) a silicon layer  120  on the BOX layer  110 . In an alternative embodiment, the fabrication process can start out with a bulk silicon wafer (not shown) instead of with the SOI substrate  105 .  
         [0012]     Next, with reference to  FIG. 2  (cross-section view), in one embodiment, an oxide layer  130  is formed on top of the silicon layer  120 . Illustratively, the oxide layer  130  comprises an oxide material such as silicon dioxide. In one embodiment, the silicon dioxide layer  130  is formed by chemical vapor deposition (CVD) of SiO2 on top of the SOI substrate  105 .  
         [0013]     Next, in one embodiment, a nitride layer  140  is formed on top of the oxide layer  130 . Illustratively, the nitride layer  140  is formed by CVD.  
         [0014]     Next, with reference to  FIG. 3  (top-down view), in one embodiment, a patterned photoresist layer  150  is formed on top of the nitride layer  140 . Illustratively, the patterned photoresist layer  150  is formed by a conventional lithographic process.  FIG. 3A  shows a cross-section view of the structure  100  of  FIG. 3  along a line  3 A- 3 A.  
         [0015]     Next, in one embodiment, the patterned photoresist layer  150  is used as a blocking mask to etch the nitride layer  140 , the oxide layer  130 , and the silicon layer  120  in that order, stopping at the BOX layer  110 , resulting in the structure  100  of  FIG. 4  (top-down view).  FIG. 4A  shows a cross-section view of the structure  100  of  FIG. 4  along a line  4 A- 4 A. With reference to  FIG. 4A , as a result of the etching, what remain of the nitride layer  140 , the oxide layer  130 , and the silicon layer  120  ( FIG. 3A ) are a nitride region  141 , an oxide region  131 , and a silicon region  121 , respectively. In one embodiment, the etching of the nitride layer  140 , the oxide layer  130 , and the silicon layer  120  ( FIG. 3A ) is anisostropic such as reactive ion etching (RIE).  
         [0016]     Next, with reference to  FIG. 4  (top-down view) and  FIG. 4A  (cross-section view), in one embodiment, the patterned photoresist layer  150  is removed using wet etching.  
         [0017]     Next, with reference to  FIG. 5  (cross-section view), in one embodiment, a dielectric region  124  is formed on side walls of the silicon region  121 . Illustratively, the dielectric region  124  comprises an oxide material such as silicon dioxide. In one embodiment, the dielectric region  124  is formed by thermal oxidation.  
         [0018]     Next, in one embodiment, a poly silicon layer  160  is formed on top the entire structure  100  right after the formation of the dielectric region  124 . Illustratively, the poly silicon layer  160  is formed using CVD of poly silicon.  
         [0019]     Next, in one embodiment, the poly silicon layer  160  is planarized using a chemical mechanical polishing (CMP) step, until the nitride region  141  is exposed to the surrounding ambient, resulting in the structure  100  of  FIG. 6  (top-down view). What remains of the poly silicon layer  160  after the CMP step is a poly silicon region  161  ( FIG. 6 ).  FIG. 6A  illustrates a cross-section view of the structure  100  of  FIG. 6  along a line  6 A- 6 A.  
         [0020]     Next, with reference to  FIG. 7  (top-down view), in one embodiment, a patterned photoresist layer  170  is formed on top of the nitride layer  141  and the poly silicon region  161 . Illustratively, the patterned photoresist layer  170  is formed by a conventional lithographic process.  FIGS. 7A-7B  show cross-section views of the structure  100  of  FIG. 7  along lines  7 A- 7 A and  7 B- 7 B, respectively.  
         [0021]     Next, in one embodiment, the patterned photoresist layer  170  is used as a blocking mask to directionally etch (a) the nitride region  141 , stopping at the oxide layer  131  and (b) the poly silicon layer  161 , stopping at the BOX layer  110 , resulting in the structure  100  of  FIG. 8  (top-down view). In one embodiment, the etching of the nitride region  141  and the poly silicon layer  161  is reactive ion etch (RIE).  FIGS. 8A, 8B , and  8 C show cross-section views of the structure  100  of  FIG. 8  along lines  8 A- 8 A,  8 B- 8 B, and  8 C- 8 C. As can be seen in  FIG. 8C , what remain of the poly silicon layer  161  of  FIG. 7  after the etching of the nitride region  141  and the poly silicon layer  161  of  FIG. 7  are poly silicon regions  161 . 1  and  161 . 2 . Also, what remains of the nitride region  141  of  FIG. 7  is a nitride region  142 .  
         [0022]     Next, in one embodiment, the patterned photoresist layer  170  is removed using dry and/or wet etching, resulting in the structure  100  of  FIG. 9  (top-down view).  FIGS. 9A, 9B , and  9 C show cross-section views of the structure  100  of  FIG. 9  along lines  9 A- 9 A,  9 B- 9 B, and  9 C- 9 C.  
         [0023]     Next, with reference to  FIG. 9A  (cross-section view), in one embodiment, extension regions and halo regions (not shown, but can be seen in  FIG. 16D  as the halo regions  129  and extension regions  128 ) are formed in the silicon region  121  by ion-implantation whose directions of ion bombardment are indicated by the arrows  910 . More specifically, in one embodiment, regarding extension ion-implantation, n-type dopants (As and P) are used for nMOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors with n-type channel), whereas p-type dopants (B and In) are used for pMOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors with p-type channel). In contrast, regarding halo ion-implantation, n-type dopants (As and P) are used for pMOSFETs, whereas p-type dopants (B and In) are used for nMOSFETs.  
         [0024]     Next, with reference to  FIG. 10  (top-down view), in one embodiment, a patterned photoresist layer  180  is formed on top of the structure  100  of  FIG. 9  so as to cover the poly silicon region  161 . 2 . Illustratively, the patterned photoresist layer  180  is formed by a conventional lithographic process.  FIG. 10A  shows a cross-section view of the structure  100  of  FIG. 10  along a line  10 A- 10 A whereas  FIG. 10C  shows a cross-section view of the structure  100  of  FIG. 10  along a line  10 C- 10 C.  
         [0025]     Next, in one embodiment, the patterned photoresist layer  180  is used as a blocking mask to etch the poly silicon region  161 . 1  so as to remove the poly silicon region  161 . 1 . Next, in one embodiment, the patterned photoresist layer  180  is removed using wet etching, resulting in the structure  100  of  FIG. 11  (top-down view).  FIG. 11A  shows a cross-section view of the structure  100  of  FIG. 11  along a line  11 A- 11 A whereas  FIG. 11C  shows a cross-section view of the structure  100  of  FIG. 11  along a line  11 C- 11 C.  
         [0026]     Next, with reference to  FIG. 12A  and  FIG. 12C , in one embodiment, a nitride layer  190  is formed on top of the entire structure  100  of  FIG. 11 . It should be noted that  FIG. 12A  and  FIG. 12C  show cross-section views of the structure  100  of  FIG. 11  along lines  11 A- 11 A and  11 C- 11 C after the nitride layer  190  is formed. Illustratively, the nitride layer  190  is formed by CVD or PECVD (Plasma-enhanced CVD).  
         [0027]     Next, in one embodiment, Ge atoms are implanted in the silicon region  121  ( FIG. 12A ) and the poly silicon region  161 . 2  ( FIG. 12C ) by ion implantation so as to form two Ge-doped silicon regions  125  in the silicon region  121  (only one of which is shown in  FIG. 12A ) and a Ge-doped poly silicon region  165  ( FIG. 12C ).  
         [0028]     Next, in one embodiment, the nitride layer  190  is directionally etched (illustratively, by reactive ion etching, i.e., RIE etch) so as to form nitride spacers  163  ( FIG. 13 ). It should be noted that, the etching of the nitride layer  190  does not stop until the nitride region  142  ( FIG. 12C ) and all portions of the nitride layer  190  on side walls of the silicon region  121  are completely removed, resulting in the structure  100  of  FIG. 13 . As the result of the etching of the nitride layer  190 , what remain of the nitride layer  190  are the nitride spacers  163  ( FIG. 13 ) on side walls of the poly silicon region  161 . 2  and a residual nitride spacer  163 ′( FIG. 13 ).  FIGS. 13A, 13B , and  13 C show cross-section views of the structure  100  of  FIG. 13  along lines  13 A- 13 A,  13 B- 13 B, and  13 C- 13 C.  
         [0029]     Next, with reference to  FIG. 13A , in one embodiment, the dielectric region  124  is etched by wet etching. As the result of the etching of the dielectric region  124 , what remains of the dielectric region  124  is a gate dielectric region  126  ( FIG. 14C ). Next, in one embodiment, after the etching of the dielectric region  124 , the two Ge-doped silicon regions  125  and the Ge-doped poly silicon region  165  are removed by wet etching selective to Ge undoped Si (i.e., Si that is not doped with Ge).  FIG. 14A  shows the structure  100  of  FIG. 13A  after the dielectric region  124  is etched and the two Ge-doped silicon regions  125  are removed.  FIG. 14B  and  FIG. 14C  show the structure  100  of  FIG. 13B  and  FIG. 13C , respectively after the Ge-doped poly silicon region  165  is removed.  
         [0030]     Next, with reference to FIGS.  14 A-C, in one embodiment, a mixture of Si and Ge (or in short, SiGe) is epitaxially grown on the silicon region  121  and the poly silicon region  161 . 2 , resulting in the structure  100  of  FIG. 15 . It should be noted that materials used in the above epitaxial growth step for pMOSFETs and nMOSFETs are SiGe and Si:C, respectively (wherein Si:C indicates a mixture of Si and C atoms).  FIGS. 15A, 15B , and  15 C show cross-section views of the structure  100  of  FIG. 15  along lines  15 A- 15 A,  15 B- 15 B, and  15 C- 15 C. As a result of the epitaxial growth of SiGe on the silicon region  121  and the poly silicon region  161 . 2 , SiGe region  122  is formed on side walls of the silicon region  121  ( FIG. 15A ), and a poly SiGe region  172  is formed on top of the poly silicon region  161 . 2  ( FIG. 15B  and  FIG. 15C ).  
         [0031]     In one embodiment, p-type dopants are added into the mixture of Si and Ge during the epitaxial growth so that the SiGe region  122  and the poly SiGe region  172  are doped with the p-type dopants.  
         [0032]     Next, in one embodiment, the structure  100  of  FIG. 15  is annealed so as to (i) activate the dopants in the SiGe region  122  and (ii) diffuse dopants implanted in the poly SiGe region  172  into the poly silicon region  161 . 2 . As a result of the annealing step, the poly silicon region  161 . 2  becomes a doped poly silicon region  164  ( FIG. 16 ).  
         [0033]     Next, in one embodiment, the oxide region  131  is used as a blocking mask to directionally etch the SiGe region  122  stopping at the BOX layer  110 , resulting in two SiGe source/drain (S/D) regions  123  ( FIG. 16D ). Illustratively, the SiGe region  122  is directionally etched using RIE etch selective to Si. Next, in one embodiment, the etching of the SiGe region  122  to create the two SiGe S/D regions  123  also removes the poly SiGe region  172 , resulting in the structure  100  of  FIG. 16 . FIGS.  16 A-C show cross-section views of the structure  100  of  FIG. 16  along lines  16 A- 16 A,  16 B- 16 B, and  16 C- 16 C.  FIG. 16D  shows a top-down view of the structure  100  of  FIG. 16C  along a line  16 D- 16 D. As can be seen in  FIG. 16D , as a result of the etching of the SiGe region  122  ( FIG. 15 ), SiGe side surfaces  151  of the SiGe S/D regions  123  are essentially aligned with a channel surface  152 .  
         [0034]     In summary, with reference to  FIG. 16D , the transistor structure  100  includes a channel region  127  disposed between the extension regions  128  and the halo regions  129 . The channel region  127  is electrically insulated from the doped poly silicon region  164  by the gate dielectric region  126 . The structure  100  also includes the first and second SiGe S/D regions  123 . Because the S/D regions  123  comprise silicon and germanium atoms, there exists stress in the lattice of the first and second S/D regions  123  resulting in high mobility of electrons and holes created in the first and second S/D regions  123 . As a result, the transistor structure  100  operates at a higher speed than in the prior art. In one embodiment, in the case the first and second S/D regions  123  comprise single crystal SiGe, the average lattice constant (or in short, lattice constant) of the single crystal SiGe is at least 0.2% larger than the lattice constant of single crystal Si in the channel region  127 . In one embodiment, in the case the first and second S/D regions  123  comprise single crystal Si:C, the average lattice constant (or in short, lattice constant) of the single crystal SiGe is at least 0.2% smaller than the lattice constant of single crystal Si in the channel region  127 .  
         [0035]     While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.

Technology Category: 5