Patent Document

BACKGROUND 
       [0001]    A modern application specific integrated circuit (ASIC) must meet very stringent design and performance specifications. One of the factors that influence the design and performance of an ASIC is inductance. Typically, it is desirable to minimize the inductance in the power supply network as well as in the signal distribution network. Minimizing inductance improves signal isolation and reduces cross talk between signal paths. A modern ASIC is typically assembled into a package, which is then mounted to a structure, such as a printed circuit board, using one of a number of known mounting techniques. The ASIC package frequently includes a laminate structure that includes a laminate core and one or more material layers on opposing sides of the core that include conductive traces and that are used to distribute power, to route signals and to provide ground connections for both power and signal connections. The laminate structure is typically located between the ASIC chip and the PCB to distribute power and signals between the ASIC and the PCB. Due to the many power and signal connections in a modern ASIC, inductance between power supply and ground connections, and inductance between signal and ground connections and between signal lines can easily become so large that it negatively affects the performance of the ASIC. 
         [0002]    Therefore, it would be desirable to have a way of minimizing power supply inductance and signal inductance in an ASIC. 
       SUMMARY 
       [0003]    In an embodiment, a laminate interconnect structure includes a core material and at least one additional layer adjacent the core material, a first electrically conductive via formed in the core material, and a second electrically conductive via formed in the core material, coaxial with the first electrically conductive via and separated from the first electrically conductive via by a non-conductive material. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    The invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0005]      FIG. 1  is a schematic diagram illustrating a portion of an application specific integrated circuit (ASIC) assembly including a laminate structure having one or more coaxial via structures. 
           [0006]      FIG. 2  is a schematic diagram illustrating a portion of the assembly of  FIG. 1 . 
           [0007]      FIG. 3  is a schematic view illustrating a cross-section the coaxial via of  FIG. 2 . 
           [0008]      FIGS. 4A through 4D  are a series of schematic drawings showing an example of a process or method that can be used to form a coaxial via in a laminate structure. 
           [0009]      FIG. 5  is a schematic diagram illustrating an alternative embodiment of a coaxial via structure. 
           [0010]      FIG. 6  is a plan view illustrating the coaxial via shown in  FIG. 4 . 
           [0011]      FIG. 7  is a plan view illustrating the coaxial via shown in  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    A laminate interconnect having a coaxial via structure can be used in any application specific integrated circuit (ASIC) in which it is desirable to reduce loop inductance between power and ground connections, reduce loop inductance between signal and ground connections, and reduce inductive coupling between signal connections. Minimizing inductance and inductive coupling improves signal isolation and reduces cross talk between signal paths. The laminate interconnect having a coaxial via structure can be implemented in circuits having single-ended signals, or in circuits having differential signals. The laminate interconnect having a coaxial via structure will be described below as being implemented in an ASIC package. However, the laminate interconnect having a coaxial via structure can be implemented in any laminate structure such as a printed circuit (PC) board interconnect. 
         [0013]      FIG. 1  is a schematic diagram illustrating a portion of an application specific integrated circuit (ASIC) assembly  100  including a laminate structure having one or more coaxial via structures. The assembly  100  comprises a printed circuit (PC) board  102  over which a circuit package  105  is located and attached to the PC board  102  using solder balls  122 . An example of a circuit package  105  can be a DRAM package or another circuit package. Further, the circuit package  105  can be a flip-chip package, or another circuit package as known to those skilled in the art. The PC board  102  can be any single-layer or multi-layer structure used to mount a circuit package, such as the circuit package  105  as known in the art. The solder balls  122  are an example of an attachment structure that can be used to electrically and mechanically attach the circuit package  105  to the PC board  102 , and are known to those skilled in the art. 
         [0014]    The circuit package  105  comprises a circuit element, also referred to as a “chip”  106  located and attached to a laminate structure  104  using solder bumps  124 . The chip  106  generally comprises the active circuit elements of the ASIC circuitry. The solder bumps  124  are an example of an attachment structure that can be used to electrically and mechanically attach the chip  106  to the laminate structure  104 , and are known to those skilled in the art. A lid  112  is attached to the circuit package  105  using an adhesive  108  as known to those skilled in the art. 
         [0015]    The laminate structure  104  generally comprises a laminate core and one or more layers formed on one or both sides of the laminate core. The laminate core and the layers formed thereon will be shown in greater detail below. The laminate structure  104  generally comprises a power distribution network and signal distribution connections, sometimes referred to as circuit traces, which transfer power and signal connections between the PC board  102  and the chip  106 . Generally, the form factor and the array of solder bumps  124  of the chip  106  dictate that connection to the PC board  102  and the array of solder balls  122  occur through an adaptive connection. The laminate structure  104  serves this adaptive connection function of coupling the chip  106  to the PC board  102 , and distributing the connections between the chip  106  and the PC board  102 . The laminate structure  104  generally comprises one or more power layers, ground plane layers, and wiring interconnects. The laminate structure  104  may also include one or more passages, referred to as “vias” that provide electrical connectivity between and among the various layers of the laminate structure  104 . In an embodiment, the laminate structure  104  may include a coaxial via structure, an example one of which is illustrated using reference numeral  150 . The coaxial via structure  150  will be described in greater detail below. 
         [0016]    In the embodiment shown, the chip  106  is located over the laminate structure  104  and a periphery of the chip  106  is generally contained within the periphery of the laminate structure  104 . Further, the laminate structure  104  is located over the PC board  102 , and a periphery of the laminate structure  104  is generally contained within a periphery of the PC board  102 . 
         [0017]      FIG. 2  is a schematic diagram illustrating a portion  200  of the assembly of 
         [0018]      FIG. 1 . The portion  200  generally comprises portions of the circuit package  105 , chip  106  and laminate structure  104 . 
         [0019]    The laminate structure  104  generally comprises a laminate core  202  and layers  204  and  206 . For example purposes only, the laminate core  202  can be fabricated from a glass fiber material, or another suitable material known to those skilled in the art. For example purposes only, the layers  204  comprise individual layers  208  and  212 , and the layers  206  comprise individual layers  214  and  216 . The layers  204  and  206  are illustrated as each comprising two layers, sometimes referred to as “build-up” layers, but those skilled in the art will recognize that layers  204  and  206  may comprise more or fewer layers, and may each comprise a different number of layers. The layers  204  and  206  generally include a combination of non-conductive high density build-up material and material used to construct electrical interconnects including, but not limited to, copper, or other conductive material circuit traces, or other conductive material circuit pads, and other conductive elements and structures. 
         [0020]    The laminate structure  104  also comprises an embodiment of a coaxial via structure  150 . In the embodiment shown, the coaxial via structure  150  comprises a central via  220  and a peripheral via  225 , which in this embodiment, can be constructed as a through hole electrically conductive plated via or an electrically conductive filled via. In the example shown in  FIG. 2 , the peripheral via  225  is constructed as a through hole electrically conductive plated via, whereby the peripheral via  225  comprises a vertical portion  227  and layer portions  228  and  229 , each of which is formed by plating, or another process by which electrically conductive material is applied or formed. The coaxial via structure  150  also comprises non-conductive fill material  226 , which can be, for example purposes only, a non-conductive resin or another structurally stable non-conductive dielectric material. 
         [0021]    In the embodiment shown in  FIG. 2 , the coaxial via structure  150  electrically connects the solder bump  231  to the central via  220 , through the conductive elements  232  and  234 , and electrically connects the solder bump  236  to the peripheral via  225 , through the conductive elements  237  and  238 . On the opposing side of the laminate structure  104 , the coaxial via structure  150  electrically connects the solder ball  251  to the central via  220 , through conductive elements  252 ,  254  and  255 , and electrically connects the solder ball  256  to the peripheral via  225 , through the conductive elements  257  and  258 . The conductive elements  232 ,  234 ,  237  and  238  are formed in the laminate layers  206 , as known in the art. Similarly, the conductive elements  252 ,  254 ,  255 ,  257  and  258  are formed in the laminate layers  204 , as known in the art. In this manner, a coaxial via structure  150  provides two electrical paths of connectivity between the chip  106  and the PC board  102  (not shown in  FIG. 2 ), while minimizing inductance and while minimizing the amount of area consumed on the laminate structure  104 . This arrangement improves signal isolation and minimizes the likelihood of cross talk for signals carried through the coaxial via  150 . 
         [0022]      FIG. 3  is a schematic view illustrating a cross-section of an example coaxial via  300 , which is similar to the coaxial via  150  of  FIG. 2 . The elements in  FIG. 3  and in the subsequent figures to follow are numbered using the convention XX, where “XX” refers to a similar element in  FIG. 2 . 
         [0023]    A coaxial via  300  is formed in a laminate core  302 . The coaxial via  300  comprises a peripheral via  325  and a central via  320 . The peripheral via  325  is formed from a conductive material and comprises a vertical portion  327  and layer portions  328  and  329 . In an embodiment, the peripheral via  325  is formed by drilling, etching, boring, or otherwise forming a hole in the laminate core  302  and then plating or otherwise covering the exposed surface of the laminate core  302  with a conductive material to form the vertical portion  327  and the layer portions  328  and  329 . Subsequently, conductive elements  351  are formed as generally indicated, but are generally not part of the peripheral via  325 . 
         [0024]    A non-conductive fill material  326 , such as a glass fiber resin or other suitable non-conductive material fills the space within the interior portion of the peripheral via  325 . The fill material  326  is then drilled, etched, bored, or otherwise processed to form an opening within which to form the central via  320 . The central via  320  can be a plated or filled via, depending upon application. The conductive elements  354  and  334  are formed subsequently as described above in the laminate layers  204  and  206  (not shown in  FIG. 3 ), as described with respect to  FIG. 2 . 
         [0025]      FIGS. 4A through 4D  are a series of schematic drawings showing an example of a process or method that can be used to form a coaxial via in a laminate structure.  FIG. 4A  shows a schematic diagram  400  including a laminate core  402  having an opening  407  formed therein. The opening  407  can be formed by drilling, boring, etching, eroding, or another known process for creating an opening in a laminate core. In an embodiment, the opening  407  has an initial diameter “a.” The diameter “a” as sometimes referred to as the “drill diameter.” The peripheral via  425  is formed by plating, or otherwise applying a conductive material to the portions of the laminate core  402  exposed when forming the opening  407 . The conductive material forms the vertical portion  427  and the layer portions  428  and  429  of the peripheral via  425 . A circuit pad  405  is also formed by portions of the vertical portion  427  and the layer portion  428 . The dimension “d” refers to a diameter of the circuit pad to  405 . A circuit pad  411  can be similarly formed on the opposing side of the laminate core  402  and may have a dimension that is the same or different than the dimension “d.” In the embodiment shown in  FIG. 4A , the thickness of the vertical portion  427  is illustrated using dimension “b” and the width of the opening after plating is shown by dimension “c.” The thickness of the layer portions  428  and  429  can be the same or different than the dimension “b.” 
         [0026]      FIG. 4B  is a schematic diagram  415  illustrating the peripheral via  425  after being filled with a non-conductive material  426 . In an embodiment, the non-conductive material  426  can be a glass resin or other structurally sound material. The dimension “e” refers to the diameter of the resin film material  426 . 
         [0027]      FIG. 4C  is a schematic diagram  430  illustrating the formation of an opening  409  through the fill material  426 . The diameter of the opening  409  corresponds to dimension “f′ and allows for the formation of the central via therein. The dimension “g” refers to the thickness of the resin material  426  on either side of the opening  409 . 
         [0028]      FIG. 4D  is a schematic diagram  435  showing a central via  420  formed within the opening  409 . The central via  420  can be a solid filled conductive structure, or can be a cylindrical plated hole, so long as the central via  420  is formed using a conductive material. Conductive elements  451  are formed as described above on the pads  405  and  411  of the peripheral via  425  while conductive elements  434  and  454  are formed on opposing ends of the central via  420 . 
         [0029]      FIG. 5  is a schematic diagram  500  illustrating an alternative embodiment of a coaxial via structure. The coaxial via structure shown in  FIG. 3  is generally suitable for power and ground connections and for circuit paths having what is referred to as a “single-ended” signal conductor and a single ground path (or power path). The coaxial via structure shown in  FIG. 5  is suitable for circumstances in which there may be multiple signal paths and a single ground path, or in applications referred to as a “differential-signal.” For example, the coaxial via structure shown in  FIG. 5  is suitable for a differential signal path where two signals of opposing polarity and a ground plane (or power plane) are carried. 
         [0030]      FIG. 5  illustrates a laminate core  502  within which a peripheral via  525  is formed as described above. The peripheral via  525  is one of three vias shown in  FIG. 5 . A fill material  526  is used to create a non-conductive solid structure within the peripheral via  525 . In the embodiment shown in  FIG. 5 , two central vias  520  and  523  are formed in and electrically isolated from each other and from the peripheral via  525  by the fill material  526  as described above. 
         [0031]    Conductive elements  551  are formed in contact with the peripheral via  525 , conductive elements  552  are formed in contact with the central via  520 , and conductive elements  553  are formed in contact to the central via  523 , as described above. The embodiment shown in  FIG. 5  can be used for differential signals in which the opposing polarity signals are carried by the central vias  520  and  523  and a ground connection is carried by the peripheral via  525 . 
         [0032]      FIG. 6  is a plan view  600  illustrating the coaxial via shown in  FIG. 4 . The central via  420  is located in the approximate center of the fill material  426 . The peripheral via  425  surrounds the fill material  426  and the central via  420 . The pad  405  is shown as comprising portions of the peripheral via  425  and layer portion  428 , but typically, the material that forms the pad  405  and the peripheral via  425  is a single continuous material. The laminate core  402  is shown for reference. 
         [0033]      FIG. 7  is a plan view  700  illustrating the coaxial via shown in  FIG. 5 . The central via  520  and central via  523  are located approximately as shown within and electrically isolated from each other and from the peripheral via  525  by the fill material  526 . The peripheral via  525  surrounds the fill material  526  and the central vias  520  and  523 . A pad  505  is shown as comprising portions of the peripheral via  525  and layer portion  528 , but typically, the material that forms the pad  505  and the peripheral via  525  is a single continuous material. The laminate core  502  is shown for reference. 
         [0034]    This disclosure describes the invention in detail using illustrative embodiments. However, it is to be understood that the invention defined by the appended claims is not limited to the precise embodiments described.

Technology Category: 5