Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to integrated circuits (ICs) that have a hysteresis capability, and more specifically to a circuit for programming an IC&#39;s hysteresis level by adjusting a programmable hysteresis signal. 
     2. Description of the Related Art 
     It would be desirable to provide an IC such as a temperature controller, an A/D converter, a comparator or a controller with the capability of having externally programmable hysteresis levels. These types of ICs typically compare an input signal to a set point to generate an output signal. Hysteresis prevents the output signal from jittering when the input signal is hovering near the set point, and also holds the output signal for a longer period of time. The output signal may be used, for example, in a temperature controller to trigger a cooling fan, produce a warning signal or shut down a system. In this type of application it is clearly advantageous to have a signal that does not turn on and off rapidly. However, the amount of hysteresis required for different temperature sensing applications, for example, may vary substantially, with a typical range being 0.5°-10° C. 
     The TMP-01 programmable temperature controller by Analog Devices, Inc., the assignee of the present invention, described in U.S. Pat. No. 5,225,811, &#34;Temperature Limit Circuit With Dual Hysteresis&#34;, provides over- and under-temperature signals that incorporate an adjustable level of hysteresis. In the TMP-01 both the high and low temperature set points and the hysteresis levels are set by a common impedance circuit. The impedance circuit is a voltage divider that is connected between an external reference voltage pin provided by the TMP-01 and ground. The set points are determined by the ratios of the resistors in the voltage divider, and the hysteresis current is set by the divider&#39;s total resistance. 
     By using a common circuit to establish both the set points and the hysteresis, the TMP-01 can be offered in an 8-pin package. However, in this configuration the values of the resistors in the voltage divider are a function of both the desired set points and the desired hysteresis level. Users have had trouble computing the resistor values to obtain both the correct set points and hysteresis. Furthermore, adjusting the set points affects the hysteresis and vice versa. 
     Another problem occurs when the reference voltage pin is used to bias another circuit. If the circuit loads the reference voltage pin, the hysteresis current will be affected. The loading effects can be reduced by using a high impedance buffer between the external pin and the circuit, but this adds components which occupy valuable board space. 
     A programmable hysteresis circuit that provides a number of predetermined hysteresis levels and easily computable intermediate levels that are not dependent on the set points or affected by loading the IC&#39;s reference voltage is needed. 
     SUMMARY OF THE INVENTION 
     The present invention seeks to provide a circuit having independent set point and hysteresis circuits, with the hysteresis circuit producing a hysteresis that can be adjusted between preset and intermediate levels through a programmable hysteresis input. 
     This is accomplished with comparators that produce output signals when an input signal crosses respective set points and a hysteresis circuit that establishes a hysteresis in the output signals. When a comparator&#39;s output signal is &#34;on&#34;, the input signal is shifted by a hysteresis differential. The output signal is terminated when the shifted input signal returns to the set point. The hysteresis circuit includes a programmable hysteresis input for adjusting the hysteresis differential to different preset and intermediate hysteresis levels. 
    
    
     For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a programmable temperature controller IC and its external set point biasing circuitry; 
     FIG. 2 is a hysteresis diagram for four over temperature outputs of the temperature controller of FIG. 1; and 
     FIG. 3 is a schematic diagram of a hysteresis circuit for producing a hysteresis current and controlling the application of a hysteresis differential to a temperature signal. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The programmable hysteresis circuit of the present invention can be used with a wide range of ICs, including sensors, controllers, analog-to-digital converters and comparators, to adjust the amount of hysteresis in the IC. In this way a standard chip can be used for a variety of applications, such as temperature sensing, that require different amounts of hysteresis. The invention will be described in conjunction with a programmable temperature controller, but it is generally applicable to many other ICs and electrical circuits. The temperature controller is provided with a hysteresis circuit for establishing a hysteresis, and an input pin for receiving a signal to adjust the magnitude of the hysteresis. The hysteresis is programmable between a number of preset and intermediate levels. 
     As shown in FIG. 1, a programmable temperature controller IC 10 produces a voltage proportional to absolute temperature, and compares it to four set point voltages. When the temperature voltage exceeds a set point, the controller produces an &#34;on&#34; binary output voltage. For example, the controller may be used to monitor and control a power supply&#39;s temperature. When the first (lowest) set point is exceeded, the associated binary output voltage trips a fan that is used to cool the power supply. When the second set point is surpassed, the fan&#39;s speed is increased and a compressor is turned on to provide additional cooling. If the temperature rises higher than the third set point a warning signal is produced, and if the fourth and highest set point is traversed the power supply is shut down. 
     Hysteresis is built into the system to prevent the outputs from jittering on and off when the temperature voltage hovers close to one of the set points. Once the temperature voltage exceeds a set point it must fall back at least a hysteresis differential below the set point to switch the output &#34;off&#34;. It would be very inefficient to turn the fan, compressor or entire system on and off every few seconds. 
     The temperature controller IC 10 includes a bandgap reference and temperature sensor 12 that is typically referred to as a &#34;Brokaw&#34; cell, and is disclosed in U.S. Pat. No. 5,225,811, &#34;Temperature Limit Circuit With Dual Hysteresis.&#34; Separate sensing and reference voltage circuits could be used. The Brokaw cell outputs a reference voltage V ref , suitably 2.5 volts, and a voltage proportional to absolute temperature V PTAT . V PTAT  is amplified by amplifier 14, typically having a gain of 2.5, to give the controller a sensitivity of approximately 5 mV/°C. Since the output of amplifier 14 is also proportional to absolute temperature, it is also designated V PTAT . The 16-pin IC package 15 includes a V S  supply voltage pin 16 and a GND pin 17 for biasing the IC&#39;s internal circuitry. The supply voltage, suitably 5 volts, and ground are provided externally. For clarity the IC&#39;s internal supply voltage and ground connections are not shown. The IC includes a V ref  pin 18 and a V PTAT  pin 20 that are connected to the reference voltage V ref  and amplified temperature voltage V PTAT , respectively. To conserve power a shutdown feature is included for the temperature sensor. A shutdown pin 22 is connected internally to the temperature sensor and receives an externally applied signal. 
     The set point voltages are established externally so that they can be adjusted to the needs of the particular application. A voltage divider 24 consisting of five series resistors R1 through R5 is connected between the V ref  pin and ground. The four set point voltages are tapped off of the voltage divider between each successive pair of resistors, and are connected to input pins IN1 (26) through IN4 (32), respectively. The ratio of the resistance between each tap and ground to the total resistance of the divider determines the value of the set point voltage for that tap. The voltage divider is preferably added by the user to establish the desired set points. Alternatively, programmable digital-to-analog converters (DACs) could be used to establish the set point voltages from digital inputs or the voltage divider could be internal to the IC. 
     The IC includes four comparators C1-C4 for comparing V PTAT  to the respective set point voltages. The comparators&#39; inverting inputs 34a-34d are connected to the input pins IN1-IN4, respectively. The amplified V PTAT  is connected through resistors R6-R9 to the comparators&#39; non-inverting inputs 36a-36d, respectively. 
     A hysteresis circuit 38 produces hysteresis currents I HC1 , I HC2 , I HC3  and I HC4  that can be applied through switches S1-S4 to the comparators&#39; non-inverting inputs, respectively, to shift the input signal, V PTAT . A hysteresis pin H pin  40 is connected to the hysteresis circuit 38 and can be used to sink or source current to adjust the magnitude of the hysteresis currents. The preferred external connections for the hysteresis pin are shown in FIG. 3. 
     Because the input impedances to the comparators are very large, when the switches are open the voltages at the non-inverting comparator inputs substantially equal V PTAT . When the switches are closed, the hysteresis I HC1  -I HC2  currents flow through the respective resistors R6-R9, thus increasing the voltages at the non-inverting comparator inputs by a hysteresis differential. The switches are independently controlled by the voltage levels at the output terminals T1-T4 of the respective comparators. 
     If V PTAT  rises above a particular set point voltage, the corresponding comparator&#39;s output goes high and closes its associated switch, allowing the associated hysteresis current to flow. V PTAT  must then fall below the set point by at least the hysteresis differential before the comparator will switch low. In terms of the previous example, if the lowest set point is 373° K. and the hysteresis differential is 4° K., the first comparator will transition high at 373° K., turning on the fan, and will remain high until the temperature falls below 369° K. The same principle can be applied to sensing temperatures below set points by reversing the direction of the hysteresis current, switching the polarities of the comparators&#39; inputs and closing the switch when the comparator output is low. When V PTAT  falls below the set point, the comparator output turns &#34;on&#34; and stays &#34;on&#34; until V PTAT  exceeds the set point by the hysteresis differential. 
     The circuit produces a corresponding output signal when any of the comparators turns &#34;on&#34;. The output signals are preferably low voltages because it is typically more efficient to drive external circuitry from a low voltage. To invert the signals at the comparator output terminals T1-T4, the terminals are connected to the bases of npn transistors Q1-Q4, respectively. The transistors&#39; collectors are connected to output pins OUT1-OUT4 (42, 44, 46 and 48), respectively, and their emitters are grounded. Therefore, if V PTAT  exceeds a set point the corresponding output pin will assume a low voltage level. 
     FIG. 2 is a plot of the voltage levels V 01  -V 04  at the respective output pins OUT1-OUT4 versus V PTAT . The voltages at the output pins remain high until V PTAT  surpasses their corresponding set points SP1-SP4. When this happens the output voltage switches low, and stays low until V PTAT  falls to at least a hysteresis differential 50 below the set point. The magnitudes of the hysteresis differentials are proportional to the respective hysteresis currents I HC1 , I HC2 , I HC3  and I HC4 , and can be adjusted by sinking or sourcing current through the H pin  40. 
     As shown in FIG. 3 the hysteresis circuit 38 produces a hysteresis current I H  that is mirrored to each comparator circuit. For purposes of explanation only the first comparator circuit C1 is shown, but similar circuitry is provided for the other comparators C2-C4. In the preferred embodiment a current source IS is connected to the emitter of an npn transistor QS. The current source establishes the reference hysteresis current I H , for example 15 μA, flowing through the transistor&#39;s collector. Q5&#39;s emitter is also connected through a resistor R10 to the hysteresis pin H pin . Connecting the H pin  to different voltages increases or reduces the amount of emitter current, and hence changes the hysteresis current I H . The transistor&#39;s base is biased so that the voltage at the emitter is insensitive to fluctuations in temperature, and lies between ground and V ref . For example, a suitable base voltage would be V b  +V be  volts, where V be  is the base-emitter voltage drop and V b  =2.011 volts, so that the emitter voltage is also 2.011 volts. 
     The hysteresis current I H  flowing through Q5&#39;s collector is reflected through a current mirror 51 to the comparator C1 to supply the comparator&#39;s hysteresis current I HC1 . The current mirror comprises a pair of pnp transistors Q6 and Q7a having a common base connection, and emitter degeneration resistors R11 and R12a connected between their respective emitters and the supply voltage V S . The collector of Q6 is connected to the collector of Q5 to supply the hysteresis current I H , and the collector of Q7a mirrors the hysteresis current to comparator C1. The emitter and base of a transistor Q8 are connected to Q6&#39;s base and collector, respectively. The emitter degeneration resistors and transistor Q8 reduce the error between collector currents on either side of the current mirror that would otherwise result from mismatches between Q6 and Q7a. Alternatively, the current mirror could be a Wilson, cascode or base current mirror. 
     The hysteresis current I HC1  supplied by Q7a will be equal to the current I H  in Q6 if the transistors have equal emitter areas and the degeneration resistors have equal values. In general the current applied to the comparator can be a multiple or fraction of I H . For example, if the emitter area of Q6 is n times greater than the emitter area of Q7a and the value of the degeneration resistor R12a is n times the value of R11, I HC1  =I H  /(n). This property allows the hysteresis currents and hence the hysteresis differentials to be different for each set point. However, the magnitudes of the hysteresis differentials relative to each other are fixed for a given IC design, and cannot be altered via the hysteresis pin. Typically the hysteresis differentials for the different set points are all the same. 
     The switch S1 (shown in FIG. 1) is preferably implemented as a switch S1a and a diode D1. The switch S1a may be implemented by one or more transistors, which could be bipolar, MOSFETs, or JFETs. Similarly, the diode D1 may be replaced by one or more transistors, or anything which implements the diodes functionality as a cutoff valve. When the V PTAT  voltage is lower than the voltage at IN1, C1&#39;s output is low. This closes switch S1a and shunts the hysteresis current I HC1  to ground. Conversely, when the V PTAT  voltage is higher than the voltage at IN1, C1&#39;s output switches high. This opens switch S1a, thus allowing the hysteresis current I HC1  to forward bias and conduct current through diode D1. As the current flows through R6 it shifts the input signal (V PTAT ) by the hysteresis differential. 
     The reference hysteresis current I H , and hence I HC1  and the hysteresis differential, are adjustable by connecting the hysteresis pin H pin  to different voltage levels. For example, I H  can have three preset levels: low, medium and high. These levels correspond to connecting H pin  to the V ref  pin, leaving it unconnected and connecting it to the GND pin, respectively. An important aspect of the invention is that the user can select one of the three preset levels without providing any additional external biasing circuitry. In general, the number of preset levels would be limited only by the availability of reference voltages. 
     Leaving H pin  unconnected has no effect on Q5&#39;s emitter current, and hence the medium level is determined by the reference hysteresis current provided by the current source IS. Tying H pin  to V ref , which is greater than the voltage at Q5&#39;s emitter, causes the pin to source current. Hence the current source IS draws less current through Q5, which reduces I H . Conversely, tying H pin  to ground causes it to sink current such that both IS and H pin  draw current from Q5. The exact values for the high and low levels are determined by the selected voltage levels, such as 2.5 V for V ref  and 0 V for ground, and by the value of R10. Intermediate hysteresis levels can be selected by tying H pin  through a resistor R13 to V ref  or GND. The H pin  setting for a desired hysteresis differential is described in Table 1 below. 
     
                       TABLE 1______________________________________Desired HysteresisDifferential (°C.)          H.sub.pin setting______________________________________H = H.sub.low  Tie to V.sub.refH.sub.low &lt; H &lt; H.sub.med          Tie to V.sub.ref Through           ##STR1##H = H.sub.med  Leave UnconnectedH.sub.med &lt; H &lt; H.sub.high          Tie to Ground Through           ##STR2##H = H.sub.high Tie to Ground______________________________________ 
    
     For example, under the following conditions: IS=15 μA, Q5&#39;s emitter voltage=2.011 V, R10=57.5 KΩ, R6=2Ω, I HC1  /I H  = 1/4 and V ref  =2.5 V, the preset hysteresis levels would be H low  =0.5° C., H med  =1.5° C. and H high  =5° C. An intermediate hysteresis of 1° C. would be achieved by connecting a 40.3 KΩ resistor between the hysteresis pin and V ref , and a hysteresis of 3° C. would result from connecting a 76.6 KΩ resistor between the pin and ground. 
     By providing a separate external hysteresis pin that is independent of the reference voltage pin, the hysteresis differential can be set without affecting the set point voltages and vice versa. The calculations for the voltage divider resistors for the desired set points and the calculations for the hysteresis resistor R13 are independent, and thus much simpler. Furthermore, the reference voltage pin can be used to bias other circuits without requiring a high impedance buffer to avoid loading the pin. 
     While several illustrative embodiments of the invention have been shown and described, numerous variations and alternate embodiment will occur to those skilled in the art. For example, while the invention has been described in terms of shifting the input signal to produce hysteresis, it may also be possible to produce hysteresis by shifting a set point, and making the set point shift programmable. Such variations and alternate embodiments are contemplated, and can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Technology Category: h