Patent Document

TECHNICAL FIELD  
       [0001]     This patent relates to a repair I/O fuse circuit of a semiconductor memory device, and more specifically, to a repair I/O fuse circuit in which the number of fuses is reduced.  
       Discussion of Related Art  
       [0002]     A semiconductor memory device includes redundancy cells capable of repairing fail cells. To control the redundancy cells, an address fuse and an I/O fuse are used.  
         [0003]      FIG. 1  is a circuit diagram of a repair I/O fuse circuit in the related art.  
         [0004]     Referring to  FIG. 1 , a PMOS transistor P 1  is always turned on according to a TRED signal always having logic low. If a repair signal REPb becomes logic low and thus indicates that an address to be replaced has been detected, PMOS transistors P 1  to P 5  and N 1 t oN 4  are all turned on. At this time, one of I/O fuses F 1  and F 2  is cut to output a repair I/O information signal IOBUS&lt; 0 &gt; as logic high or logic low, one of I/O fuses F 3  and F 4  is cut to output a repair I/O information signal IOBUS&lt; 1 &gt; as logic high or logic low, one of fuses F 5  and F 6  is cut to output a repair I/O information signal IOBUS&lt; 2 &gt; as logic high or logic low, and one of fuses F 7  and F 8  is cut to output a repair I/O information signal IOBUS&lt; 3 &gt; as logic high or logic low.  
         [0005]     In the above-described repair I/O fuse circuit, however, two I/O fuses (e.g., F 1 , F 2 ) that store repair I/O information represent one repair I/O information signal IOBUS&lt; 0 &gt;. These I/O fuses occupy a greater amount of a layout area than that of a MOS transistor. Therefore, an increase in the number of I/O fuses results an increased die size.  
       SUMMARY OF THE INVENTION  
       [0006]     A repair I/O fuse circuit of a semiconductor memory device incorporates a reduced by as much as half by replacing what one repair I/O information is represented by existing two I/O fuses with what one repair I/O information is represented by one I/O fuse.  
         [0007]     A repair I/O fuse circuit of a semiconductor memory device may include a plurality of I/O fuse circuits that output repair I/O information signals depending on whether a fuse has been cut, respectively, in response to a repair signal and a chip enable signal. Each of the plurality of I/O fuse circuits includes one fuse, wherein the repair signal indicates that there is an address to be replaced, and if the chip enable signal is activated, each of the plurality of I/O fuse circuits outputs the repair I/O information signal depending on whether the fuse has been cut.  
         [0008]     A repair I/O fuse circuit of a semiconductor memory device may include a plurality of I/O fuse circuits that output repair I/O information signals depending on whether a fuse has been cut, respectively, in response to a repair signal and a chip enable signal. Each of the plurality of fuse circuits includes a feedback unit that combines one of the plurality of repair I/O information signals and the chip enable signal to output a feedback signal, a fuse unit that includes one fuse, outputs an output signal depending on whether the fuse has been cut and operates in response to the repair signal and the feedback signal, and a buffer unit that outputs one of the plurality of repair I/O information signals in response to the output signal of the fuse unit and the repair signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a circuit diagram of a repair I/O fuse circuit in the related art; and  
         [0010]      FIG. 2  is a circuit diagram of a repair I/O fuse circuit according to a herein described embodiment. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0011]      FIG. 2  is a circuit diagram of a repair I/O fuse circuit.  
         [0012]     Referring to  FIG. 2 , the repair I/O fuse circuit may include a plurality of I/O fuse circuits, four being illustrated as fuse circuits  100 - 0  to  100 - 3 . It has been shown in  FIG. 2  that the number of the I/O fuses is four. It is, however, to be understood that the number of the I/O fuses is not limited to the above.  
         [0013]     The I/O fuse circuit  100 - 0  may include a fuse unit  110 , a 3-state buffer unit  120  and a feedback unit  130 . The fuse unit  110  receives a repair signal RED_Enb and a feedback signal FD and outputs a signal having a voltage level depending on whether a fuse has been cut. The 3-state buffer unit  120  receives the feedback signal FD, the output signal of the fuse unit  110  and an inverting signal of the repair signal RED_Enb, inverts the output signal of the fuse unit  110 , and outputs a repair I/O information signal IOBUS&lt; 0 &gt;. The repair I/O information signal is loaded on an I/O bus (not shown). The feedback unit  130  logically combines the chip enable signal ENb and the output signal of the 3-state buffer unit  120  and outputs the feedback signal FD.  
         [0014]     The fuse unit  110  may include an inverter IV 11 , a PMOS transistor P 11 , a NMOS transistor P 12  and a fuse F 11 . The inverter IV 11  inverts the repair signal RED_ENb. The PMOS transistor P 11  is connected between a power supply voltage VCC and a node NA and has the gate to which the feedback signal FD is input. The PMOS transistor P 11  is a weak transistor, which is weakly (i.e., very small) is turned on according to the feedback signal FD. A NMOS transistor N 11  and the fuse F 11  is connected in series between the node NA and a ground voltage VSS. The NMOS transistor N 11  has the gate to which the output signal of the inverter IV 11  is input.  
         [0015]     The 3-state buffer unit  120  may include PMOS transistors P 12 , P 13  and NMOS transistors N 12 , N 13 . The PMOS transistors P 12 , P 13  are connected in series between the power supply voltage VCC and an output terminal. The PMOS transistor P 12  receives the repair signal RED_ENb through its gate. The PMOS transistor P 13  receives a signal of the node NA through its gate. The NMOS transistors N 12 , N 13  are connected between the output terminal and the ground voltage VSS. The NMOS transistor N 12  receives a signal of the node NA through its gate. The NMOS transistor N 13  receives the output signal of the inverter IV 11  through its gate.  
         [0016]     The feedback unit  130  may include a NAND gate ND 1  and an inverter IV 2 . The NAND gate N 1  performs a NAND operation on a chip enable signal ENb and the output signal of the 3-state buffer  120 . The inverter IV 12  inverts the output signal of the NAND gate ND 1  and outputs the feedback signal FD.  
         [0017]     The remaining I/O fuse circuits  100 - 1  to  100 - 3  have the same construction as that of the aforementioned I/O fuse circuit  100 - 0  and operate according to the same input signal. Description thereof will be omitted.  
         [0018]     Hereinafter, the operation of the repair I/O fuse circuit according to a preferred embodiment of the present invention will be described with reference to  FIG. 2 .  
         [0019]     If the repair signal RED_ENb is applied as logic low and the chip enable signal ENb is applied as logic low, the PMOS transistors P 11 , P 12  and the NMOS transistors N 11 , N 13  are all turned on. At this time, if the fuse F 11  within the I/O fuse circuit  100 - 1  has not been cut, the node NA has the level of the ground voltage VSS level since the PMOS transistor P 11  is a weak transistor. That is, although the current by the power supply voltage VCC collides against the current by the ground voltage VSS, the amount of current by the ground voltage VSS becomes greater than those by the power supply voltage VCC, so that the node NA has the level of the ground voltage VSS.  
         [0020]     Meanwhile, if the fuse F 11  within the I/O fuse circuit  100 - 1  has been cut, the current by the ground voltage VSS is cut and the node NA has the level of the power supply voltage VCC. If the node NA has the level of the ground voltage VSS since the fuse F 11  is not cut, the PMOS transistors P 12 , P 13  are turned on. Therefore, the repair I/O information signal IOBUS&lt; 0 &gt; becomes logic high and thus loaded on a corresponding I/O bus (not shown). If the node NA has the level of the power supply voltage VCC since the fuse F 11  is cut, the NMOS transistors N 12 , N 13  are cut. Therefore, the repair I/O information signal IOBUS&lt; 0 &gt; becomes logic low and thus loaded on a corresponding I/O bus (not shown).  
         [0021]     If the chip enable signal ENb becomes logic high with the repair signal RED_ENb becoming logic low, i.e., a chip is in standby mode, the PMOS transistor P 11  is turned on and an active current is not generated accordingly. The PMOS transistor P 12  and the NMOS transistors N 11 , N 13  are turned on according to the repair signal RED_ENb. At this time, if the fuse F 11  has not been cut, the node NA becomes the level of the ground voltage VSS and both the PMOS transistors P 12 , P 13  are turned on. Therefore, the repair I/O information signal IOBUS&lt; 0 &gt; becomes logic high and thus has repair I/O information. Meanwhile, if the fuse F 11  has been cut, the repair I/O information signal IOBUS&lt; 0 &gt; is floated since the current does not flow through the node NA.  
         [0022]     If the repair signal RED_ENb becomes logic high and the chip enable signal ENb is logic low, the PMOS transistor P 11  is turned on and the NMOS transistors N 11 , N 13  are turned off. Therefore, the node NA becomes the level of the power supply voltage VCC regardless of whether the fuse F 11  has been cut. In this case, since the PMOS transistors P 12 , P 13  are turned on and the NMOS transistor N 13  is turned off, the repair I/O information signal IOBUS&lt; 0 &gt; becomes floated. If the chip enable signal ENb becomes logic high with the repair signal RED_ENb becoming logic high, i.e., a chip is in standby mode, both the PMOS transistor P 11  and the NMOS transistor N 11  are turned on and the repair I/O information signal IOBUS&lt; 0 &gt; becomes floated regardless of whether the fuse F 11  has been cut.  
         [0023]     The remaining I/O fuse circuits  100 - 1  to  100 - 3  have the same operation as that of the aforementioned I/O fuse circuit  100 - 0 . Description thereof will be omitted in order to avoid redundancy.  
         [0024]     As described above, in the case where the repair signal RED_ENb becomes logic low top indicate that an address to be replaced has been detected and the chip enable signal ENb is enabled as logic low, if the fuse F 11  has been cut, the repair I/O information signal IOBUS&lt;i&gt; becomes logic low, and if the fuse F 11  has not been cut, the repair I/O information signal IOBUS&lt;i&gt; becomes logic high. Meanwhile, if the repair signal RED_ENb becomes logic high, it means that there is no address to be replaced. Therefore, the repair I/O information signal IOBUS&lt;i&gt; becomes floated regardless of a logic state of the chip enable signal ENb.  
         [0025]     An I/O fuse circuit uses one fuse in order to represent one repair I/O information (i.e., in order to output one repair I/O information signal). The I/O fuse circuit has a large number of MOS transistors, but a small number of fuses in comparison with the prior art. That is, since MOS transistors do not occupy a large layout area, the layout area can be significantly reduced by reducing the number of fuses that occupy lots of the layout area.  
         [0026]     As described above, the number of fuses can be reduced approximately by half in comparison with the related art. Therefore, it is possible to reduce a layout area, i.e., a chip area by half compared with the prior art.  
         [0027]     Although the foregoing description has been made with reference to various embodiments, it is to be understood that changes and modifications of the present invention may be made by the person of ordinary skill in the art without departing from the spirit and scope of the present invention defined by the appended claims.

Technology Category: 3