Patent Document

CLAIM OF PRIORITY 
       [0001]    This application claims the benefit of the earlier filing date, pursuant to 35 USC 119(a), to that patent application entitled “Method for Interpolating Chrominance Signal in Video Encoder and Decoder,” filed with the Korean Intellectual Property Office on Oct. 20, 2006 and assigned Serial No. 2006-102539, the contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to image signal processing and to a method for interpolating chrominance signals in a video encoder and a decoder based on optimized computation and memory access so that interpolation can be performed efficiently with little power consumption. 
         [0004]    2. Description of the Related Art 
         [0005]    As generally known in the art, image compression is based on a number of compression standards, including MPEG and H.26x, and such image compression techniques are widely used for video players, VODs, video telephones, DMB, etc. In addition, development of wireless communication (e.g. 2.5G/3G) has resulted in commercialized image transmission on a wireless mobile basis. 
         [0006]    Most moving image compression standards, including MPEG- or H.26x-series moving image codecs, adopt a compression scheme based on motion estimation/compensation and transformation. In the case of encoding based on such motion estimation/compensation, information regarding the motion vector of each block must be encoded and transmitted. In addition, how the motion vector is encoded may greatly affect the compression efficiency. 
         [0007]    Recently, ITU-T and ISO has jointly established H.264 as the next-generation moving image compression standard, which has progressed remarkably from conventional technical standards (e.g. MPEG-2, MPEG-4 (Part 2)) in terms of flexible adaptation to various network environments and efficient encoding of moving images. 
         [0008]    Images are generally encoded in the following manner: a digital image signal is subjected to DCT (Discrete Cosine Transform); a DCT coefficient is quantized so as to perform VLC (Variable Length Coding); the quantized DCT coefficient is inversely quantized and subjected to inverse DCT so that the image is restored and stored in a memory; the stored image and the next frame image are used to obtain a motion vector; and the motion vector is subjected to VLC so as to constitute a bit stream together with the encoded image information and transmit it. Decoding of images follows the opposite order. 
         [0009]    Methods for compressing and encoding images are based on spatial redundancy and/or temporal redundancy. In the case of a moving image codec based on temporal redundancy, the temporal redundancy with regard to the previous frame can be efficiently eliminated by using the motion vector of macro blocks. For example, the codec searches for a macro block most similar to the macro block of the current frame from a previous frame (reference frame). As a standard for determining similarity between the macro block of the current frame and that of the previous frame, the codec calculates the square of distance between two vectors and searches for a macro block having the smallest square. In this manner, the redundancy between frames is efficiently eliminated so as to improve the compression efficiency. 
         [0010]      FIG. 1  shows a conventional H.264 compression codec interpolating chrominance signals. 
         [0011]    Referring to  FIG. 1 , the chrominance signal sub-pixel interpolation method based on H.264 uses ⅛ interpolation. That is, it simply uses integer pixel values adjacent to a location indicated by a motion vector. Particularly, the interpolation is based on four adjacent integer pixel values as defined by equation (1). 
         [0000]    
       
         
           
             
               
                 
                   
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             wherein, “&gt;&gt;” refers to rightward bit-shift 
           
         
       
     
         [0013]    This method has the advantage of high interpolation performance by using adjacent integer pixels. However, the sub-pixel value of ⅛ location cannot be obtained but from a single formula. 
         [0014]    Basically, a luma signal interpolation method based on H.264 performs ¼ sub-pixel computation, and the resulting chrominance signal interpolation method is based on ⅛ interpolation. This chrominance signal interpolation method, which uses ⅛ sub-pixels, has been developed to obtain higher accuracy by using four adjacent integer pixels only. However, this interpolation method has a problem in that, since the formula requires many multiplication steps and inefficient memory access, the overall amount of computation increases. Therefore, an alternative computation method is necessary with regard to the chrominance signal interpolation method based on H.264. Particularly, a method for reducing the memory access frequency is requested. To this end, the calculation characteristics of H.264 video encoders and decoders must be analyzed for more efficient computation with a smaller size. 
       SUMMARY OF THE INVENTION 
       [0015]    Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an aspect of the present invention is to provide a new chrominance signal interpolation method exhibiting optimized computation and memory access so that a codec can function efficiently with little power consumption. 
         [0016]    In one embodiment, there is provided a method for interpolating chrominance signals in a video encoder and a decoder, the method including the steps of accessing a memory unit so as to load an integer pixel value with regard to a plurality of motion compensation blocks, searching for a location of a motion vector so as to perform sub-pixel interpolation of chrominance signals regarding the blocks and performing ¼ sub-pixel interpolation by means of row-based and column-based shifting when the motion vector indicates a ¼ location pixel with regard to the blocks. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    The above features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0018]      FIG. 1  shows a conventional H.264 compression codec interpolating chrominance signals; 
           [0019]      FIG. 2  is a block diagram of an MPEG decoder according to one embodiment of the present invention; 
           [0020]      FIG. 3  is a block diagram of an MPEG encoder according to one embodiment of the present invention; 
           [0021]      FIG. 4  shows examples of motion compensation blocks acting as a unit of motion compensation according to an embodiment of the present invention; 
           [0022]      FIG. 5  is a flowchart showing an interpolation process according to an exemplary embodiment of the present invention; 
           [0023]      FIG. 6  partially illustrates pixels constituting a motion compensation block according to an exemplary embodiment of the present invention; 
           [0024]      FIG. 7  shows an interpolation process according to an exemplary embodiment of the present invention; 
           [0025]      FIG. 8  shows an interpolation process according to another exemplary embodiment of the present invention; and 
           [0026]      FIG. 9  shows another interpolation process according to another exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0027]    Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein is omitted to avoid making the subject matter of the present invention unclear. 
         [0028]      FIG. 2  is a block diagram of an MPEG decoder  200  according to a first exemplary embodiment of the present invention, and  FIG. 3  is a block diagram of an MPEG encoder  300  according the embodiment of the present invention. 
         [0029]    As shown in  FIGS. 2 and 3 , the MPEG decoder and encoder  200  and  300  have a circuit based on H.264 standards, and the same components are given the same reference numerals. In particular, the region labeled  100  is included in both the decoder  200  and the encoder  300  according to H.264 standards. For brevity, the circuit configuration of the MPEG decoder  200  will solely be described. However, it would be recognized that the circuit configuration description is also applicable to an encoder. 
         [0030]    Referring to  FIG. 2 , the MPEG decoder  200  includes a entropy decoding unit  10  for receiving an NAL (Network Abstraction Layer), which is a compressed bit stream, and performing entropy decoding, a reordering unit  20  for reordering the data into groups, an inverse quantization unit  30  for inversely quantizing data outputted by the reordering unit  20 , an inverse discrete cosine transform (hereinafter, referred to as IDCT) unit  40  for subjecting the inversely quantized data to IDCT, an intra/inter-screen data prediction unit  50  for performing intra-screen prediction or inter-screen prediction and compensation and an in-loop deblocking filter  90  for eliminating errors which have occurred during the inverse quantization process. The intra/inter-screen data prediction unit  50  includes an intra-screen prediction unit  60  for performing intra-screen prediction and a motion compensation unit  70  for performing inter-screen prediction. The motion compensation unit  70  includes an interpolation unit  500  for interpolating images so that motion compensation becomes more precise. 
         [0031]    The decoder  200  and encoder  300  respectively shown in  FIGS. 2 and 3  follow H.264 standards, and the interpolation unit  500  performs ¼ interpolation. 
         [0032]    More particularly, the interpolation unit  500  selectively conducts a ¼ interpolation process in response to a motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10 . During the interpolation process of the interpolation unit  500 , data stored in the register (not shown) of an external memory unit is obtained by simply shifting it row by row and column by column. This guarantees fast calculations. In addition, the interpolation unit  500  has a simple overall structure, because it has a minimum register applicable to all sub-macro blocks with various sizes. Prior to description of the detailed construction of the interpolation unit  500 , the operation and result of interpolation of decoded images will now be described. 
         [0033]      FIG. 4  shows examples of motion compensation blocks acting as a unit of motion compensation according to a preferred embodiment of the present invention. 
         [0034]    Referring to  FIG. 4 , the memory unit consists of a number of motion compensation blocks, including not only 16×16 macro blocks according to the present embodiment, but also 16×8 reference blocks obtained by bisecting a macro block in the horizontal direction, 8×16 blocks obtained by bisecting a macro block in the vertical direction, 8×8 blocks obtained by bisecting a macro block in the horizontal and vertical directions, 8×4 or 4×8 blocks obtained by bisecting a 8×8 block in the horizontal or vertical direction, and 4×4 blocks obtained by bisecting a 8×8 block in the horizontal and vertical directions. 
         [0035]      FIG. 5  is a flowchart shows an interpolation process according to an exemplary embodiment of the present invention. 
         [0036]    With regard to a plurality of motion compensation blocks having various sizes, the interpolation unit needs an integer pixel value of a corresponding block, which has accessed the memory unit, and a pixel value adjacent to a region indicated by a motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10 . That is, for the purpose of sub-pixel interpolation regarding the corresponding block, access to the memory unit is necessary to load an integer pixel value related to the chrominance signal of the corresponding block (S 500 ). 
         [0037]    In order to perform sub-pixel interpolation of the chrominance signal concerning the corresponding block, the interpolation unit searches for the location of the motion vector (X_Frac, Y_Frac) provided by the decoding unit  10  (S 510 ). When the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10  indicates a ¼ location pixel value itself, the ¼ interpolation unit  580  outputs ¼ interpolation results as they are. When the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10  indicates a ⅛ location pixel, the interpolation unit, which follows H.264 standards, divides the ⅛ location pixel value by 2 and rounds it off so that it is converted into a ¼ location pixel (S 520 ), as defined by equation (2). 
         [0000]      ¼ MV= (⅛ MV+ 1)&gt;&gt;1   (2)       wherein, “&gt;&gt;” refers to rightward bit-shift.         
         [0039]    In order to perform ¼ interpolation with regard to the corresponding block, the interpolation unit must create a pixel value of a sub-pixel location and uses a separate calculation formula, which has been optimized for each sub-pixel location, to obtain the sub-pixel value of the interpolated chrominance signal. 
         [0040]      FIG. 6  partially illustrates pixels constituting a motion compensation block according to an exemplary embodiment of the present invention. 
         [0041]    Referring to  FIG. 6 , pixels locations due for ¼ sub-pixel interpolation by the interpolation unit are a, b, c, d, e, f, g, h, i, j, k, n, p, q, and r. In  FIGS. 6 , A, B, C, and D refer to integer location pixel values. That is, interpolation is performed based on these pixel values A, B, C, and D to obtain sub-pixel values for respective locations a to r. 
         [0042]    Particularly, sub-pixels of respective locations due for interpolation are calculated continuously, and intermediate result values used to calculate adjacent sub-pixels are used again. This means that six adjacent integer pixels are used to calculate two sub-pixel values (a 1 , a 2 ˜r 1 , r 2 ) (see  FIG. 7 ). 
         [0043]    The ¼ sub-pixel interpolation according to the present invention can be performed in one of the following schemes, depending on the location of the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10  with regard to a plurality of motion compensation blocks (S 530 ). 
         [0044]      FIG. 7  shows interpolation process according to an exemplary embodiment of the present invention. 
         [0045]    Scheme 1 
         [0046]    Referring to  FIG. 7 , the interpolation unit calculates sub-pixel values of locations a, b, c, d, h, and n by means of row-based shifting according to the location of the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10  with regard to a plurality of motion compensation blocks. Particularly, the interpolation unit calculates the sub-pixel value of the location indicated by the motion vector (X_Frac, Y_Frac) by using integer pixel values adjacent to the corresponding block (S 540 ). In this case, b 1  and b 2  refer to sub-pixel values of existing location b, and h 1  and h 2  refer to sub-pixel values of existing location h. 
         [0047]    In addition, calculation is made by using sub-pixel values adjacent to the location indicated by the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10 , as well as integer location pixel values adjacent to the corresponding block. In this case, a 1  and a 2  correspond to location a shown in  FIG. 6 , i.e. they refer to sub-pixel values of existing location a. Similarly, c 1  and c 2  refer to sub-pixel values of existing location c; d 1  and d 2  refer to sub-pixel values of existing location d; and n 1  and n 2  refer to sub-pixel values of existing location n. Respective sub-pixel values are obtained as defined by equation (3) below. 
         [0000]        b 1=( A+B+ 1)&gt;&gt;1,  b 2=( B+C+ 1)&gt;&gt;1 
         [0000]        h 1=( A+D+ 1)&gt;&gt;1,  h 2=( B+E+ 1)&gt;&gt;1 
         [0000]        a 1=( A+b 1+1)&gt;&gt;1,  a 2=( B+b 2+1)&gt;&gt;1 
         [0000]        c 1=( B+b 1+1)&gt;&gt;1,  c 2=( C+b 2+1)&gt;&gt;1 
         [0000]        d 1=( A+h 1+1)&gt;&gt;1,  d 2=( B+h 2+1)&gt;&gt;1 
         [0000]        n 1=( D+h 1+1)&gt;&gt;1,  n 2=( E+h 2+1)&gt;&gt;1   (3) 
         [0048]    wherein, “&gt;&gt;” refers to rightward bit-shift. 
         [0049]    Scheme 2 
         [0050]    The interpolation unit calculates sub-pixel values of locations f, j, and q based on the location of the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10 . Particularly, the calculation is based on sub-pixel values adjacent to the location indicated by the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10 , as well as integer pixel values adjacent to the corresponding block (S 550 ). In this case, f 1  and f 2  refer to sub-pixel values of existing location f; j 1  and j 2  refer to sub-pixel values of existing location j; and q 1  and q 2  refer to sub-pixel values of existing location q. Respective sub-pixel values are obtained as defined by equation (4). 
         [0000]        f 1=( A+h 2+1)&gt;&gt;1,  f 2=( C+h 2+1)&gt;&gt;1 
         [0000]        q 1=( D+h 2+1)&gt;&gt;1,  q 2=( F+h 2+1)&gt;&gt;1 
         [0000]        j 1=( A+E+ 1)&gt;&gt;1,  j 2=( C+E+ 1)&gt;&gt;1   (4) 
         [0051]    wherein, “&gt;&gt;” refers to rightward bit-shift. 
         [0052]      FIG. 8  shows an interpolation process according to another exemplary embodiment of the present invention. 
         [0053]    Scheme 3 
         [0054]    Referring to  FIG. 8 , the interpolation unit calculates sub-pixel values of locations i and k by means of column-based shifting according to the location of the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10  with regard to a plurality of motion compensation blocks. Particularly, the calculation is based on sub-pixel values adjacent to the location indicated by the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10 , as well as integer pixel values adjacent to the corresponding block (S 560 ). In this case, i 1  and i 2  refer to sub-pixel values of existing location i, and k 1  and k 2  refer to sub-pixel values of existing location k. Respective sub-pixel values are obtained as defined by equation (5). 
         [0000]        i 1=( A+b 2+1)&gt;&gt;1,  i 2=( E+b 2+1)&gt;&gt;1 
         [0000]        k 1=( B+b 2+1)&gt;&gt;1,  k 2=( F+b 2+1)&gt;&gt;1   (5) 
         [0055]    wherein, “&gt;&gt;” refers to rightward bit-shift. 
         [0056]      FIG. 9  shows an interpolation process according to another exemplary embodiment of the present invention. 
         [0057]    Scheme 4 
         [0058]    Referring to  FIG. 9 , the interpolation unit calculates sub-pixel values of locations e, g, p and r by means of row-based shifting according to the location of the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10  with regard to a plurality of motion compensation blocks. Particularly, the calculation is based on sub-pixel values adjacent to the location indicated by the motion vector (X_Frac, Y_Frac) provided by the entropy decoding unit  10 , as well as integer pixel values adjacent to the corresponding block (S 570 ). In this case, e 1  and e 2  refer to sub-pixel values of existing location e; g 1  and g 2  refer to sub-pixel values of existing location g; p 1  and p 2  refer to sub-pixel values of existing location p; and r 1  and r 2  refer to sub-pixel values of existing location r. Respective sub-pixel values are obtained as defined by equation (6). 
         [0000]        e 1=( A+j 1+1)&gt;&gt;1, wherein  j 1=( B+D+ 1)&gt;&gt;1 
         [0000]        e 2=( B+j 2+1)&gt;&gt;1, wherein  j 2=( C+E+ 1)&gt;&gt;1 
         [0000]        g 1=( B+j 1+1)&gt;&gt;1, wherein  j 1=( A+E+ 1)&gt;&gt;1 
         [0000]        g 2=( C+j 2+1)&gt;&gt;1, wherein  j 2=( B+F+ 1)&gt;&gt;1 
         [0000]        p 1=( D+j 1+1)&gt;&gt;1, wherein  j 1=( A+E+ 1)&gt;&gt;1 
         [0000]        p 2=( E+j 2+1)&gt;&gt;1, wherein  j 2=( B+F+ 1)&gt;&gt;1 
         [0000]        r 1=( E+j 1+1)&gt;&gt;1, wherein  j 1=( B+D+ 1)&gt;&gt;1 
         [0000]        r 2=( F+j 2+1)&gt;&gt;1, wherein  j 2=( C+E+ 1)&gt;&gt;1   (6) 
         [0059]    wherein, “&gt;&gt;” refers to rightward bit-shift. 
         [0060]    It is to be noted with regard to the above equation that the value of j 1  and j 2 , which are used to created sub-pixel values for respective locations, are obtained in different methods. 
         [0061]    As mentioned above, the interpolation unit  500  according to the present invention does not perform ⅛ interpolation, which requires a large amount of calculation, but performs ¼ interpolation in a discrete and gradual manner. 
         [0062]    The ¼ interpolation process is selectively performed with reference to the motion vector, and ¼ interpolation computation is performed fast by simply shifting data, which is stored in the register, row by row and column by column. Compared with conventional chrominance signal interpolation methods based on H.264, the inventive process has the advantages of fast computation because it involves no multiplication and undergoes infrequent memory access. In addition, the fact that all sizes of variable macro blocks are supported for the sake of interpolation, which is performed in the direction of motion of all pixels, simplifies the structure. 
         [0063]    The above-described methods according to the present invention can be realized in hardware or as software or computer code that can be stored in a recording medium such as a CD ROM, an RAM, a floppy disk, a hard disk, or a magneto-optical disk or downloaded over a network, so that the methods described herein can be rendered in such software using a general purpose computer, or a special processor or in programmable or dedicated hardware, such as an ASIC or FPGA. As would be understood in the art, the computer, the processor or the programmable hardware include memory components, e.g., RAM, ROM, Flash, etc. that may store or receive software or computer code that when accessed and executed by the computer, processor or hardware implement the processing methods described herein. 
         [0064]    While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Category: h