Patent Document

FIELD OF THE INVENTION 
     The invention relates to high power semiconductor switches, and more particularly to FET switch layouts and biasing thereof. 
     BACKGROUND OF THE INVENTION 
     In modern RF communication systems, a semiconductor-based transmit-receive switch is often the last/first component encountered by a transmitted/received signal before/after encountering an antenna. 
     Many of the main advances in semiconductor-based transmit-receive switches have been with respect to isolation and insertion loss. Groups of FETs are arranged in the switch along with judiciously chosen resistors and capacitors to ensure low insertion loss along the signal path and high isolation from the off paths. One general approach utilizes, instead of a single FET switch along each alternative path, a group of FET switches in series. This general approach moreover does not simply turn the FETs on and off by utilizing only a voltage at the gate, but instead biases both the gate and the source/drain in a forward and reverse manner to turn the FETs full-on and full-off respectively. Two general approaches have been used to enable this, namely, the use of negative voltage sources, and the use of DC blocking capacitors. 
     In both known approaches n-FETs are used due to their lower insertion loss and low harmonics while p-FETs are avoided due to their higher insertion loss caused in part by the relative low mobility of holes in a p-FET compared with the relatively higher electron mobility in an n-FET. The FETs described herein are MOSFETs which include a gate, a source, a drain and a backgate. For n-FETs which are nMOSFETs as depicted in  FIGS. 1A and 1B , in order for the transistor to be fully on, the voltage applied to the backgate should be the substantially similar to that applied to the source and the drain, while the voltage at the gate must be higher, in the case of silicon on insulator (SOI), than the voltage at the source or drain by 2.5V. In order for the SOI n-FET to be properly off, the voltage at the backgate should be less than the voltage at the drain and the source, and the voltage at the gate should be less than the voltage at the drain or the source. Harmonic generation occurs when the depletion region of the parasitic diodes associated with the n-FET devices are modulated by a signal when it passes through the n-FET. 
     An example of a known series-shunt switch  100  according to a prior art approach utilizing negative voltage sources for biasing is presented in  FIG. 1A . An RF terminal  101  is coupled along a signal or series path  111  through a series FET group switch  110  to an antenna  102 , and is connected along a shunt path  121  through a shunt FET group switch  120  to ground  103 . Each FET group switch  110 ,  120  has a group of n-FET transistors connected in series with the respective path from the RF terminal  101  to the antenna  102  or from the RF terminal  101  to ground  103 . Each FET group switch  110 ,  120  also has a respective associated group of source/drain resistors  115 ,  125 , each resistor of which is coupled to a sources and drain of a respective FET of the group switch it is associated with. 
     The gates of the FETs of the series FET group switch  110  are biased by a series gate biasing terminal  112  with a voltage V gSERIES , while gates of the FETs of the shunt FET group switch  120  are biased by a shunt gate biasing terminal  122  with a voltage V gSHUNT . The backgates of the FETs of the series FET group switch  110  are biased by a series backgate biasing terminal  114  with a voltage V bSERIES , while backgates of the FETs of the shunt FET group switch  120  are biased by a shunt backgate biasing terminal  124  with a voltage V bSHUNT . All of the sources and drains of the series FET group switch are effectively biased at the same DC voltage level of the RF terminal  101 , ground  103 , and the antenna  102  which is 0.0V. 
     To connect the RF terminal  101  to the antenna  102  and put the switch  100  into series mode, the series gate biasing terminal  112  is set to V gSERIES =2.5V, while the series backgate biasing terminal  114  is set to V bSERIES =0.0V, and while the shunt gate bias terminal  122  and the shunt backgate bias terminal  124  are each set to V gSHUNT =V bSHUNT =−2.5V with use of a negative voltage source (not shown) which typically would be an on-chip negative voltage generator. Setting the biases in this manner ensures that the FETs of the series FET group switch  110  are fully on while the FETs of the shunt FET group switch  120  are properly off, within the reliability/breakdown limits of operation. 
     To connect the RF terminal  101  to ground  103  and put the switch  100  into shunt mode, the series gate biasing terminal  112  and the series backgate biasing terminal  114  are set to V gSERIES =V bSERIES =−2.5V with use of the negative voltage source, while the shunt gate biasing terminal  122  is set to V gSHUNT =2.5V, and while the shunt backgate bias terminal  124  is set to V bSHUNT =0.0V. Setting the biases in this manner ensures that the FETs of the series FET group switch  110  are properly off while the FETs of the shunt FET group switch  120  are fully on, within the reliability/breakdown limits of operation. 
     This configuration biases each FET group switch in the forward or the reverse direction ensuring respectively low insertion loss and high isolation which are very important when dealing with high-power signal transmission. 
     Some of the drawbacks of the series shunt switch  100  of  FIG. 1A  are that it requires oscillators, charge pump circuitry, positive and negative voltage regulators, supply filtering including a negative supply filter which usually occupies a much larger area than a positive supply filter, and a pseudo-random bit sequence (PRBS) generator. The additional components can create noise, spurious tones, and spurious spectral emissions and tend to occupy a large percentage of IC (integrated chip) die area, and consume extra DC power. 
     Another example of a known series-shunt switch  150 , this one according to a prior art approach utilizing DC blocking capacitors is presented in  FIG. 1B . An RF terminal  151  is coupled along a series path  161  to a first blocking capacitor  181  coupled in series with a series FET group switch  160  in turn coupled in series with a second blocking capacitor  182  to an antenna  152 , and is connected along a shunt path  171  to a third blocking capacitor  183  coupled in series with a shunt FET group switch  170  in turn coupled in series with a fourth blocking capacitor  184  to ground  153 . Each FET group switch  160 ,  170  has a group of n-FET transistors connected in series with the respective path from the RF terminal  151  to the antenna  152  or from the RF terminal  151  to ground  153 . Each FET group switch  160 ,  170  also has a respective associated group of source/drain resistors  165 ,  175 . Each FET of the series and shunt FET group switches  160 ,  170  has a respective resistor of its associated group of source/drain resistors  165  coupled across its source and drain. All of the sources and drains of the FETs of the series FET group switch  160  are supplied with a series source/drain bias V s/dSERIES  from a series source/drain biasing terminal  166 . All of the sources and drains of the FETs of the shunt FET group switch  170  are supplied with a shunt source/drain bias V s/dSHUNT  from a shunt source/drain biasing terminal  176 . The actual mechanism for providing the biasing to the source/drains may be chosen from any number of known methods for providing biasing voltage. For the purposes of the switching function described herein, the chosen level of the biasing applied at each of the source/drains is the important factor. 
     The gates of the FETs of the series FET group switch  160  are biased by a series gate biasing terminal  162  with a voltage V gSERIES , while gates of the FETs of the shunt FET group switch  170  are biased by a shunt gate biasing terminal  172  with a voltage V gSHUNT . The backgates of the FETs of the series FET group switch  160  are biased by a series backgate biasing terminal  164  with a voltage V bSERIES , while backgates of the FETs of the shunt FET group switch  170  are biased by a shunt backgate biasing terminal  174  with a voltage V bSHUNT . 
     To connect the RF terminal  151  to the antenna  152  and put the switch  150  into series mode, the series gate biasing terminal  162  and the shunt source/drain bias terminal  176  are set to V gSERIES =V s/dSHUNT =2.5V, while the series backgate biasing terminal  164 , the shunt backgate biasing terminal  174 , the series source/drain bias terminal  166  and the shunt gate bias terminal  172  are set to V bSERIES =V bSHUNT =V s/dSERIES =V gSHUNT =0.0V. Setting the biases in this manner ensures that the FETs of the series FET group switch  160  are fully on while the FETs of the shunt FET group switch  170  are properly off, within the reliability/breakdown limits of operation. In this mode of the series-shunt switch&#39;s  150  operation, the third blocking capacitor  183  blocks the RF terminal  151  from the 2.5 V DC shunt source/drain biasing, while the fourth blocking capacitor  184  blocks the 2.5 V DC shunt source/drain biasing from ground  153 . 
     To connect the RF terminal  151  to ground  153 , and put the switch  150  into shunt mode, the shunt gate biasing terminal  172  and the series source/drain bias terminal  166  are set to V gSHUNT =V s/dSERIES =2.5V, while the shunt backgate biasing terminal  174 , the series backgate biasing terminal  164 , the shunt source/drain bias terminal  176  and the series gate bias terminal  162  are set to V bSHUNT =V bSERIES =V s/dSHUNT =V gSERIES =0.0V. Setting the biases in this manner ensures that the FETs of the shunt FET group switch  170  are fully on while the FETs of the series FET group switch  160  are fully off, within the reliability/breakdown limits of operation. In this mode of the series-shunt switch&#39;s  150  operation, the first blocking capacitor  181  blocks the RF terminal  151  from the 2.5 V DC series source/drain biasing, while the second blocking capacitor  182  blocks the 2.5 V DC series source/drain biasing from the antenna  102 . 
     As with the circuit depicted in  FIG. 1A , this configuration biases each FET group switch in the forward or the reverse direction ensuring respectively low insertion loss and high isolation without the use of negative voltage generators. 
     Some of the drawbacks of the series-shunt switch  150  of  FIG. 1B  are that it often requires a DC-DC boost converter circuit (not shown), and requires that all terminals be blocked with an appropriately sized blocking capacitor in order to ensure flexible voltage settings. Integrated DC blocking capacitor&#39;s take up significant IC die area and may easily be damaged during ESD (ElectroStatic Discharge) events hampering the reliability and robustness of the circuit. Use of off chip capacitors also occupies a significant board area and can add significant cost. Although the blocking capacitors  181 ,  182 ,  183 ,  184 , are effective in allowing all of the bias voltages to be positive and present a tolerable insertion loss, their use does, however, cause the switch  150  of  FIG. 1B  to exhibit more insertion loss than the switch  100  of  FIG. 1A . 
     SUMMARY OF THE INVENTION 
     According to one aspect, the invention provides for a high power switch comprising: a first transistor group switch comprising a plurality of first transistors of a first type, the first transistor group switch coupled along a signal path formed between a first end and a second end; and a second transistor group switch comprising a plurality of second transistors of a second type, the second transistor group switch coupled along a shunt path formed between a shunt end and at least one of the first and second ends of the signal path, wherein a drain and a source of at least one of the first transistors is held at a substantially similar biasing voltage as that applied to a drain and a source of at least one of the second transistors when the switch is in a series mode and when the switch is in a shunt mode. 
     According to another aspect the invention provides for a method of high power switching, the method comprising: providing a first transistor group switch comprising a plurality of first transistors of a first type, the first transistor group switch coupled along a signal path formed between a first end and a second end; and providing a second transistor group switch comprising a plurality of second transistors of a second type, the second transistor group switch coupled along a shunt path formed between a shunt end and at least one of the first and second ends of the signal path, biasing a drain and a source of at least one of the first transistors at a substantially similar biasing voltage as that applied to a drain and a source of at least one of the second transistors when the switch is in a series mode and when the switch is in a shunt mode. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features and advantages of the invention will become more apparent from the following detailed description of the preferred embodiment(s) with reference to the attached figures, wherein: 
         FIG. 1A  is a circuit diagram illustrating a prior art implementation of a series-shunt switch utilizing negative biasing; 
         FIG. 1B  is a circuit diagram illustrating a second prior art implementation of a series-shunt switch utilizing blocking capacitors; and 
         FIG. 2  is a circuit diagram illustrating a series-shunt switch according to an embodiment of the invention. 
     
    
    
     It is noted that in the attached figures, like features bear similar labels. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to  FIG. 2 , a series-shunt switch  200  in accordance with a first embodiment of the invention will now be discussed in terms of its structure. 
     An RF terminal  201  is coupled along a series path  211  through a series n-FET group switch  210  to an antenna  202 , and is connected along a shunt path  221  through a first blocking capacitor  241  in series with a shunt p-FET group switch  220  to an AC ground or shunt terminal  203 . The series n-FET group switch  210  is made up of a plurality of n-type FET transistors, while the shunt p-FET group switch  220  is made up of a plurality of p-type FET transistors. Each FET group switch  210 ,  220  is connected in series with the respective path from the RF terminal  201  to the antenna  202  or from the RF terminal  201  to the shunt terminal  203 . Each FET group switch  210 ,  220  also has a respective associated group of source/drain resistors  215 ,  225 . Each n-FET of the series n-FET group switch  210 , except for the last n-FET on the RF end of the series n-FET group switch  210  and the last n-FET on the antenna end of the n-FET group switch  210  has a respective resistor of the associated source/drain resistors  215  coupled across its source and drain. Each p-FET a the shunt p-FET group switch  220 , except for the last p-FET on the shunt end of the p-FET group switch  220  has a respective resistor of the associated source/drain resistors to 25 coupled across its source and drain. 
     The gates of the n-FETs of the series n-FET group switch  210  are biased by a series gate biasing terminal  212  with a voltage V g , and the gates of the p-FETs of the shunt p-FET group switch  220  are biased by a shunt gate biasing terminal  222  with a voltage V g ′ which is set equal to the voltage applied to the series gate biasing terminal  212 , namely, V g . Although the value of V g  will change as the switch  200  changes mode, the same value V g  or voltage values substantially similar to V g  will always be simultaneously applied to both the series gate biasing terminal  212  and the shunt gate biasing terminal  222  i.e. either V g =V g ′ or V g ≈V g ′. At all times and in any mode of the switch&#39;s  200  operation, the backgates of the n-FETs of the series n-FET group switch  210  are biased by a series backgate biasing terminal  214  with a voltage V LO =0.0V, while backgates of the p-FETs of the shunt p-FET group switch  220  are biased by a shunt backgate biasing terminal  224  with a voltage V HI =2.5V. In the embodiment depicted in  FIG. 2 , the antenna  202  and RF terminal  201  are both pulled to 0.0V. The shunt terminal  203  is set to a voltage of V SHUNT  which is set to V HI =2.5V and serves as AC ground. 
     To connect the RF terminal  201  to the antenna  202  and put the switch  200  into series mode, the series gate biasing terminal  212  and the shunt gate biasing terminal  222  are both set to V g =V g ′=2.5V. Setting V g =V g ′ to this value ensures that the n-FETs of the series n-FET group switch  210  are fully on while the p-FETs of the shunt p-FET group switch  220  are fully off, within the reliability/breakdown limits of operation. It is noted that as a result of this biasing configuration, all of the sources/drains of the n-FETs and of the p-FETs of the FET group switches  210   220  are biased at 0.0 V, with only the exception of the source/drain of the shunt p-FET group switch  220  adjacent the shunt terminal  203 . 
     To connect the RF terminal  201  to the shunt terminal  203  and put the switch  200  into shunt mode, the series gate biasing terminal  212  and the shunt gate biasing terminal  222  are both set to V g =V g ′=0.0V. Setting V g =V g ′ to this value ensures that the n-FETs of the series n-FET group switch  210  are fully off while the p-FETs of the shunt p-FET group switch  220  are fully on, within the reliability/breakdown limits of operation. It is noted that as a result of this biasing configuration, all sources/drains of the n-FETs and of the p-FETs of the FET group switches  210   220  are biased at 2.5 V, with only the exception of the source/drain of the series n-FET group switch  210  adjacent the RF terminal  201  and the source/drain of the series n-FET group switch  210  adjacent the antenna  202 . 
     As with the configurations of the prior art, this embodiment according to the invention fully biases each FET group switch in the forward or the reverse direction ensuring respectively low insertion loss and high isolation which are very important when dealing with high-power signal transmission. Moreover, the drawbacks of negative voltage generation and blocking capacitors along the series path are mitigated. 
     Unlike the series-shunt switch  100  of  FIG. 1A  which utilizes a negative power supply, the series-shunt switch  200  of  FIG. 2  utilizes only positive voltage supplied at 2.5V or 0.0V. The drawbacks of the series shunt switch  100  of  FIG. 1A , namely that it requires oscillators, charge pump circuitry, a negative voltage regulator, large area occupying negative supply filtering, and pseudo-random bit sequence (PRBS) generator are avoidable. The absence of additional components means that noise, spurious tones, and spurious spectral emissions that they create, the large percentage of IC (integrated chip) die area they tend to occupy, and the extra DC power they would consume are also avoided. 
     Unlike the series-shunt switch  150  of  FIG. 1B , which utilizes blocking capacitors along the series path  181 , the series shunt switch  200  of  FIG. 2  utilizes blocking capacitors only to isolate RF terminal  201  and the antenna  202  from the nonzero effective biasing of the source/drains of the n-FETs of the series n-FET group switch  210  and the p-FETs of the shunt p-FET group switch  220  which occurs in shunt mode. Since a signal traversing the series path  211  does not encounter a blocking capacitor, the insertion loss along the series path  211  of the series-shunt switch  200  of  FIG. 2  is less than that of the series path  161  of the known series-shunt switch  150  of  FIG. 1B . The absence of blocking capacitors along the series path typically also improves switching times. The blocking capacitors  241 ,  243  of the switch  200  of  FIG. 2  also do not bear the full brunt of any ESD event since the source/drain breakdown of the n-FETs at the ends of the series n-FET group switch  210  clamps the voltage of the blocking capacitors  241 ,  243  so as to protect them. As such, the switch  200  is much more robust to forms of ESD event damage. The switch  200  also does not require a DC-DC boost converter circuit as required by prior art configurations. In addition to requiring fewer blocking capacitors, the switch  200  of  FIG. 2  may use blocking capacitors  241 ,  243  which are not as large as those  181 ,  182 ,  183 ,  184  of the known switch  150  of  FIG. 1B . Reduction in both the size and number of blocking capacitors translates to reduction in IC die area usage for integrated blocking capacitors and/or reduction in board area and cost imposed by the use of off-chip capacitors. 
     The switch  200  in addition to reducing or avoiding altogether the various drawbacks of known switch architectures described above also is controllable in an elegant and uncomplicated manner, namely, by control of the gate biasing voltage V g =V g ′. When it is desired that the switch  200  function in series mode, V g =V g ′ is set to 2.5V and when it is desired that the switch  200  function in shunt mode, V g =V g ′ is set to 0.0V. Since isolation along the shunt path  221  is not as important as that along series path  211 , the p-FETs may be used along the shunt path without any serious detriment to the circuit&#39;s  200  performance. As long as the p-FET transistors are situated along the insertion loss insensitive paths, and as long as they provide a relatively low impedance to an AC ground, they may be advantageously used to allow biasing voltages on the drain and source of the various FET group switches to move between supply and ground. 
     Although each embodiment has been described as utilizing FET group switches comprising n-type and p-type MOSFETs it should be understood that other implementations may utilize any suitable number and combination of complementary n-type and p-type transistor switches, including unipolar devices such as standard CMOS, SOI CMOS, MOS with depletion mode devices, pHEMT, MESFET, JFET, etc. 
     Although in the embodiment of  FIG. 2 , the same voltage V g  is shown as being applied to all the gates of the FETs of the various FET group switches, in some embodiments the bias voltage applied to the gates of the p-FETs of the shunt p-FET group switch  220 , namely, V g ′ may only be substantially similar or approximately equal to the voltage applied to the gates of the n-FETs of the series n-FET group switch  210 , namely, V g , i.e. V g ′≈V g . 
     Although in embodiments described above the high voltage level for biasing has been chosen to be 2.5V, other values of positive voltage for V HI  and the gate biasing voltages may be appropriate in specific instances. 
     The embodiments presented are exemplary only and persons skilled in the art would appreciate that variations to the embodiments described above may be made without departing from the spirit of the invention. The scope of the invention is solely defined by the appended claims.

Technology Category: 5