Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to the fabrication of circuit boards. More particularly, the present invention relates to a solder pad structure for printed circuit boards and fabrication method thereof. 
     2. Description of the Prior Art 
     Rapid changes in the semiconductor industry will continue toward higher functionality that leads to higher I/O counts, pushing packaging towards new, smaller, and higher density architectures. The semiconductor industry has developed features of 30 nm for high performance microprocessors. However, the feature size that the packaging industry can produce is about 15˜20 μm. A huge technical gap exists between semiconductor and packaging. In order to keep pace with semiconductor process development, a process for finer pitch wiring substrate is necessary. 
       FIG. 1  to  FIG. 5  demonstrate a conventional solder resist process and the solder paste printing process after the solder resist process. As shown in  FIG. 1 , a surface wiring structure  1   a  is formed on a surface of the circuit board  1 . The surface wiring structure  1   a  includes a plurality of solder pad structures  2  and fine trace  3 . For the sake of simplicity, the conductive via holes or other inner layer interconnection are not shown in the figures. 
     As shown in  FIG. 2 , after the formation of the surface wiring structure  1   a , a solder resist layer  4  is formed to cover the surface of the circuit board  1 . Typically, the solder resist layer  4  is composed of photo-sensitive polymers or inks, and the solder resist layer  4  may be liquid type or solid film type. It is well known that the solder resist layer  4  is used to protect the circuit wires that are not covered with tin and prevent solder from bridging between conductive traces, thereby preventing short circuits. 
     As shown in  FIG. 3 , after coating the solder resist layer  4 , a conventional photolithographic process including exposure and development is carried out to form a plurality of solder resist openings  4   a  in the solder resist layer  4 . Each of the solder resist openings  4   a  exposes a portion of each of the underlying solder pad structures  2 . 
     As shown in  FIG. 4 , prior to the formation of electroless nickel/immersion gold (ENIG), a chemical micro-etching and cleaning process is performed to remove the oxide residuals formed on the exposed surface of the solder pad structures  2  from the solder resist openings  4   a . However, this cleaning process results in undercut defects  4   b  at the bottom of the solder resist openings  4   a.    
     Subsequently, as shown in  FIG. 5 , a conventional electroless nickel/immersion gold (ENIG) process is carried out to form an ENIG surface finish layer  5  having a thickness of about 0.5-1.5 micrometers on the exposed top surface of the solder pad structures  2  within the solder resist openings  4   a . A conventional solder paste printing process is then performed to fill the solder resist openings  4   a  with solder paste  6 . Thereafter, the circuit board  1  is subjected to reflow and pressing processes. 
     However, the above-described prior art method has several drawbacks. First, the yield of the solder paste printing process reduces as the pitch between the solder pad structures  2  on the flip-chip side of the circuit board becomes smaller and smaller. Second, the adhesion of solder paste  6  to the solder resist layer  4  is poor. Third, the undercut defects  4   b  formed during the chemical micro-etching and cleaning process create high stress points in the subsequent processes leading to reliability problems of the circuit board. In light of the above, there is a strong need in this industry to provide an improved method for fabricating a circuit board that is capable of solving the shortcomings and problems of the prior art. 
     SUMMARY OF THE INVENTION 
     It is one object of the present invention to provide an improved solder pad structure for printed circuit boards and fabrication method thereof in order to solve the above-described prior art problems. 
     According to one preferred embodiment of this invention, a method for fabricating a solder pad structure of a circuit board includes: providing a circuit board having thereon at least one copper pad structure; forming a solder resist layer on a surface of the circuit board; subjecting the solder resist layer to a laser to thereby form a solder resist opening exposing a portion of the copper pad structure, the laser simultaneously forming a laser-activated layer on sidewall of the solder resist opening; and growing copper from the laser-activated layer on sidewall of the solder resist opening and from the exposed portion of the copper pad structure. 
     According to another preferred embodiment of this invention, a method for fabricating a solder pad structure of a circuit board includes: providing a circuit board having thereon at least one copper pad structure; forming a solder resist layer on a surface of the circuit board; forming a peelable film on the solder resist layer; subjecting the peelable film and the solder resist layer to a laser to thereby form a solder resist opening exposing a portion of the copper pad structure; forming a seed layer on interior sidewall of the solder resist opening; peeling off the peelable film from the solder resist layer; and filling the solder resist opening with copper. 
     According to still another preferred embodiment of this invention, a method for fabricating a solder pad structure of a circuit board includes: providing a circuit board having thereon at least one copper pad structure; forming a solder resist layer on a surface of the circuit board; forming a protective layer on the solder resist layer; forming a solder resist opening in the protective layer and the solder resist layer to expose a portion of the copper pad structure; selectively forming a seed layer on interior surface of the solder resist opening; and filling the solder resist opening with copper. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  to  FIG. 5  demonstrate a conventional solder resist process and the solder paste printing process after the solder resist process. 
         FIG. 6  to  FIG. 9  are schematic, cross-sectional diagrams showing a method for fabricating a solder pad structure on a circuit board in accordance with one preferred embodiment of this invention. 
         FIG. 10  to  FIG. 15  are schematic, cross-sectional diagrams showing a method for fabricating a solder pad structure on a circuit board in accordance with another preferred embodiment of this invention. 
         FIG. 16  to  FIG. 19  are schematic, cross-sectional diagrams showing a method for fabricating a solder pad structure on a circuit board in accordance with still another preferred embodiment of this invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 6  to  FIG. 9  are schematic, cross-sectional diagrams showing a method for fabricating a solder pad structure on a circuit board in accordance with one preferred embodiment of this invention. First, as shown in  FIG. 6 , a surface wiring structure  10   a  is provided on the surface of the circuit board  10 . The surface wiring structure  10   a  may include but not limited to a plurality of copper pad structure  20  and fine traces  30 . It is to be understood that the circuit board  10  may be a single wiring layer circuit board, double wiring layer circuit board or multiple wiring layer circuit board. For the sake of simplicity, the conductive via holes or other inner layer interconnection inside the circuit board  10  are not shown in the figures. 
     After the formation of the surface wiring structure  10   a , a non-conductive material layer  120  is coated on the surface of the circuit board  10 . The non-conductive material layer  120  comprises a dielectric matrix and laser-activable catalytic particles. The catalytic particles are evenly dispersed in the dielectric matrix. The aforesaid catalytic particles may be activated by laser energy and a conductive layer may be selectively deposited on the laser-activated traces on the non-conductive material layer  120 . 
     According to the preferred embodiment of this invention, the dielectric matrix comprises polymer material such as epoxy resins, modified epoxy resins, polyesters, acrylate, fluoro-containing polymer, (PPO) polyphenylene oxide (PPO), polyimide, phenolic resins, polysulfone (PSF), Si-containing polymer, BT resins, polycyanate, polyethylene, polycarbonate, acrylonitrile-butadiene-styrene copolymer, polyethylene terephthalate (PET), polybutylene terephthalate (PBT), liquid crystal polymers (LCP), polyamide (PA), Nylon 6, nylonpolyoxymethylene (POM) polyphenylene sulfide (PPS), COC or a combination thereof. 
     According to the preferred embodiment of this invention, the catalytic particles described above may be nano-particles of metals or metal coordination compounds. For example, suitable metal coordination compounds may include metal oxides, metal nitrides, metal complexes and/or metal chelating compounds. In one embodiment of the present invention, the aforesaid metal may include but not limited to zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, aluminum, chromium, tungsten, vanadium, tantalum, and/or titanium. 
     As shown in  FIG. 7 , a specific laser beam such as UV laser is directed to the top surface of the non-conductive material layer  120  to etch openings  120   a  into the non-conductive material layer  120 . Each of the opening  120   a  exposes a portion of each of the copper pads  20 . Optionally, a desmear process may be carried out to ensure removal of epoxy-smear or residuals from the exposed surface of the copper pad  20 . Suitable desmear process may include but not limited to plasma or oxidation methods. For example, permanganate may be used as an oxidant in the desmear process. At this point, the catalytic particles inside the opening  120   a  are activated by laser, thereby forming a laser activated layer  120   b  on sidewall of each of the openings  120   a.    
     As shown in  FIG. 8 , a chemical copper deposition or plating process is carried out to grow chemical copper  60  from the laser activated layer  120   b  and from the exposed top surface of the copper pad  20  at the same time. Since the chemical copper  60  is directly grown from the laser activated layer  120   b  on the sidewall of the opening  120   a , a tight bonding between the chemical copper  60  and the non-conductive material layer  120  is created. Optionally, the chemical copper  60  may continue to grow until it protrudes from the top surface of the non-conductive material layer  120  to thereby form a bump structure  70 , as shown in  FIG. 9 . The bump structure  70  and the copper pad structure  20  together constitute a solder pad structure  80 . 
     The present invention comprises at least the following advantages. First, the laser method for forming the opening  120   a  provides higher accuracy compared to the conventional photolithographic process. Second, the production throughput is improved because the chemical copper  60  grows simultaneously from the laser activated layer  120   b  on the sidewall of the opening  120   a  and from the exposed top surface of the copper pad  20 . Third, since the bump structure  70  is grown on the copper pad  20 , the poor yield due to conventional solder paste printing can be avoided. In addition, direct bonding between the chemical copper  60  or the bump structure  70  and the sidewall laser-activated layer  120   b  improves the reliability of the solder pad structure  80 . 
       FIG. 10  to  FIG. 15  are schematic, cross-sectional diagrams showing a method for fabricating a solder pad structure on a circuit board in accordance with another preferred embodiment of this invention. As shown in  FIG. 10 , likewise, a surface wiring structure  10   a  is provided on the surface of the circuit board  10 . The surface wiring structure  10   a  may include but not limited to a plurality of copper pad structure  20  and fine traces  30 . For the sake of simplicity, the conductive via holes or other inner layer interconnection inside the circuit board  10  are not shown in the figures. 
     After the formation of the surface wiring structure  10   a , a solder resist layer  220  is coated on the surface of the circuit board  10 . The solder resist layer  220  comprises a dielectric matrix and laser-activable catalytic particles. The catalytic particles are evenly dispersed in the dielectric matrix. The aforesaid catalytic particles may be activated by laser energy and a conductive layer may be selectively deposited on the laser-activated traces on the non-conductive material layer  120 . However, the solder resist layer  220  may be composed of photo-sensitive polymers or inks. 
     The aforesaid dielectric matrix may comprise polymer material such as epoxy resins, modified epoxy resins, polyesters, acrylate, fluoro-containing polymer, (PPO) polyphenylene oxide (PPO), polyimide, phenolic resins, polysulfone (PSF), Si-containing polymer, BT resins, polycyanate, polyethylene, polycarbonate, acrylonitrile-butadiene-styrene copolymer, polyethylene terephthalate (PET), polybutylene terephthalate (PBT), liquid crystal polymers (LCP), polyamide (PA), Nylon 6, nylonpolyoxymethylene (POM) polyphenylene sulfide (PPS), COC or a combination thereof. 
     The aforesaid catalytic particles described above may be nano-particles of metals or metal coordination compounds. For example, suitable metal coordination compounds may include metal oxides, metal nitrides, metal complexes and/or metal chelating compounds. In one embodiment of the present invention, the aforesaid metal may include but not limited to zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, iridium, indium, iron, manganese, aluminum, chromium, tungsten, vanadium, tantalum, and/or titanium. 
     As shown in  FIG. 11 , a peelable film  230  is formed on the solder resist layer  220 . For example, the peelable film  230  may be a polymer release film such as polyester film or the like. Preferably, the peelable film  230  has a thickness of about 1-2 micrometers, but not limited thereto. 
     As shown in  FIG. 12 , a specific laser beam such as UV laser is directed to the top surface of the peelable film  230  to etch openings  220   a  into the peelable film  230  and the solder resist layer  220 . Each of the opening  220   a  exposes a portion of each of the copper pads  20 . Optionally, a desmear process may be carried out to ensure removal of epoxy-smear or residuals from the exposed surface of the copper pad  20 . Suitable desmear process may include but not limited to plasma or oxidation methods. For example, permanganate may be used as an oxidant in the desmear process. 
     As shown in  FIG. 13 , a seed layer  240 , for example, Pd, Ti, W or the like, is conformally deposited on the interior sidewall of the openings  220   a , the exposed surface of the copper pad  20  and on the top surface of the peelable film  230 . Notably, the seed layer  240  is conformally deposited on the circuit board  10  and does not fill up the openings  220   a . According to the preferred embodiment of this invention, the seed layer  240  may be an organic seed layer or an inorganic seed layer. 
     As shown in  FIG. 14 , after the conformal deposition of the seed layer  240 , the peelable film  230  is peeled off from the surface of the solder resist layer  220 . A portion of the seed layer  240  that is situated on the peelable film  230  is also removed, thereby leaving the other portion of the seed layer  240  on the interior sidewall of the openings  220   a  intact. 
     As shown in  FIG. 15 , a chemical copper deposition or plating process is then carried out to fill the openings  220   a  with chemical copper  260 . A top surface of the chemical copper  260  may be lower than the top surface of the solder resist layer  220 . In another case, the top surface of the chemical copper  260  may be higher than the top surface of the solder resist layer  220 . The production throughput is improved since the chemical copper  260  is grown from the seed layer  240  in different directions, for example, from the sidewall directions and from the top of the pad  20  at the same time. 
       FIG. 16  to  FIG. 19  are schematic, cross-sectional diagrams showing a method for fabricating a solder pad structure on a circuit board in accordance with still another preferred embodiment of this invention. As shown in  FIG. 16 , likewise, a surface wiring structure  10   a  is provided on the surface of the circuit board  10 . The surface wiring structure  10   a  may include but not limited to a plurality of copper pad structure  20  and fine traces  30 . For the sake of simplicity, the conductive via holes or other inner layer interconnection inside the circuit board  10  are not shown in the figures. 
     After the formation of the surface wiring structure  10   a , a solder resist layer  320  is coated on the surface of the circuit board  10 . The solder resist layer  320  may be composed of photo-sensitive polymers or inks. Subsequently, a protective layer  330  is coated on the surface of the solder resist layer  320 . The protective layer  330  may be coated by printing or spraying methods. Preferably, the protective layer  330  has a thickness that is less than 2 micrometers. Preferably, the protective layer  330  is composed of nano-coating or nano-paint comprising nano-scale particles. 
     As shown in  FIG. 17 , a specific laser beam such as UV laser is directed to the top surface of the protective layer  330  to etch openings  320   a  into the protective layer  330  and the solder resist layer  320 . Each of the opening  320   a  exposes a portion of each of the copper pads  20 . Optionally, a desmear process may be carried out to ensure removal of epoxy-smear or residuals from the exposed surface of the copper pad  20 . Suitable desmear process may include but not limited to plasma or oxidation methods. For example, permanganate may be used as an oxidant in the desmear process. 
     As shown in  FIG. 18 , after the formation of the openings  320   a , a seed layer  340 , for example, Pd, Ti, W or the like, is selectively deposited on the interior sidewall of the openings  320   a , the exposed surface of the copper pad  20  but not deposited on the top surface of the protective layer  330 . The seed layer  340  is conformally deposited on the interior sidewall of the openings  320   a  and does not fill up the openings  320   a . According to the preferred embodiment of this invention, the seed layer  340  may be an organic seed layer or an inorganic seed layer. 
     As shown in  FIG. 19 , a chemical copper deposition or plating process is then carried out to fill the openings  320   a  with chemical copper  360 . A top surface of the chemical copper  360  may be lower than the top surface of the protective layer  330 . In another case, the top surface of the chemical copper  360  may be higher than the top surface of the protective layer  330 . The production throughput is improved since the chemical copper  360  is grown from the seed layer  340  in different directions within the openings  320   a  at the same time. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Technology Category: 7