Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims benefit of U.S. Provisional Application No. 60/079,046, filed on Mar. 23, 1998, which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to CMOS image sensors, and more particularly to methods and associated architectures for reading out data, from such a sensor.  
       BACKGROUND  
       [0003]     The advent of HDTV and other high-end digital imaging systems is increasing demand for large format high speed sensors. CMOS active pixel image sensors which have low power dissipation, are low cost and highly reliable, and which can typically be configured in a single chip solution, are increasingly being developed for large format high speed imaging applications. Large format sensors usually require an image pixel array of at least 1024×1024 pixels in size. Unfortunately, as the image array is made larger, it becomes difficult to increase pixel readout rate without also increasing frame rate because of parasitic capacitance limitations in current architectures.  
       SUMMARY  
       [0004]     The present disclosure describes a method and associated architecture for dividing column readout circuitry in an image sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided with block signaling. Accordingly, only column readout circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines at any point in time. Block signaling was found to increase pixel readout rate while maintaining a constant frame rate for utility in large format high-speed imaging applications.  
         [0005]     In accordance with a preferred embodiment, by mathematically modeling the load capacitance and the effective RC constant seen by any column output stage at a particular time and by using a differentiated derived equation, a desirable optimum number of connections per block as well as a desired number of blocks for a given size of column readout circuits can be easily determined.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]      FIG. 1  shows a pixel and corresponding column readout circuit in an active pixel sensor.  
         [0007]      FIG. 2  shows the timing for a photodiode pixel readout operation.  
         [0008]      FIG. 3  shows a block diagram of a CMOS active pixel sensor including an array of pixels and corresponding column readout circuits, all coupled to a pair of shared readout lines.  
         [0009]      FIG. 4  shows a simplified schematic diagram of a portion of an output stage for each of plural column readout circuits and the parasitic capacitance effects contributed thereby.  
         [0010]      FIG. 5  shows a tree-style column decoder and multiplexer.  
         [0011]      FIG. 6  shows the grouping of column readout circuits in blocks of k across an m-pixel linear array.  
         [0012]      FIG. 7  shows the timing for column readout and column group selection in accordance with a preferred implementation of the present disclosure.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0013]     A schematic diagram of a conventional CMOS active pixel  100  and associated column readout circuit  101  is shown in  FIG. 1 . Incident photons on the pixel  101  generate electrons that are collected in the floating diffusion area  102 . The charge is buffered by an in-pixel source follover  105 . A number of pixels are typically arranged horizontally to form a row of pixels and also vertically to define a column of pixels. Row selection transistor  103  is enabled to allow charge from a given row of pixels to be selectable for readout.  
         [0014]     A more detailed discussion of the general principles of pixel readout is provided in U.S. Pat. No. 5,841,126.  
         [0015]     While the illustrative implementation shows a photodiode pixel, it should be understood that a photogate, phototransistor or the like could be used instead.  
         [0016]     During imaging, the photodiode floating diffusion area  102  is first reset. This is achieved by pulsing a gate of reset transistor  104  to a high voltage, for example VDD. After a period of time, the voltage of the floating diffusion area  102  drops to reflect the number of electrons accumulated in the Floating diffusion area  102 . The voltage V S  of the floating diffusion area is then read out from the pixel  100  into the column readout circuit  101  using source follower  105  within pixel  100 . Voltage V S  is then sampled onto storage capacitor C S    106  by enabling the sample-hold signal (SHS) transistor  107 .  
         [0017]     After the signal charge V S  is read out, the pixel  100  is then reset and the gate of reset transistor  104  is again pulsed to a high voltage. The resultant voltage V R  of Floating diffusion area  102  is then read out to the column readout circuit  101  as before. This time the voltage V R  is sampled onto storage capacitor C R    108  by enabling the sample-hold reset (SHR) transistor  109 .  FIG. 2  shows the timing for the above photodiode operation.  
         [0018]     The voltage difference between the voltages stored in the two capacitors, C s    106  and C R    108  is indicative of the charge collected in the floating diffusion area  102 . Typically, all the pixels  100  in a same row are processed simultaneously. The signals are sampled onto capacitors C S  and C R  in their respective column readout circuits collectively arranged beneath the row (or multiple rows: array  10 ) of pixels. After a row sampling process is complete, voltage signal Vout_S, Vout_R in each column is read out successively by successively enabling the associated n-channel column selection transistors  110 ,  111 . A high level block diagram of an array of pixels  10  and associated linear array  10 ′ of corresponding column readout circuits  101 , arranged in parallel fashion, is shown in  FIG. 3 . The outputs of Vout_R and Vout_S of column readout circuits  101  each share a common readout line.  
         [0019]      FIG. 4  is a simplified partial schematic diagram of the respective output stages of the column readout circuits  101  in a linear array of pixels  10 ′. Each column output stage contributes a parasitic capacitance resulting in an effective load capacitance of Cp, represented by capacitor  401 . Assuming Ci to be the parasitic capacitance contributed by each column circuitry, total parasitic capacitance and total RC time constant (charge and discharge) turn-on/off settling time, may then be represented as follows: 
   Cp 1= mCi   eq. (1)    RCp 1= mRCi   eq. (2),  
 where R is the built-in resistance associated with each of column select transistors  110 ,  111  in the ON state, and m is the total number of column readout circuits  101  in a column-addressable row. 
 
         [0020]     As explained above, column readout circuit  101  output signals (Vout_S and Vout_R) are each connected to a pair of corresponding shared column readout lines. An image sensor with a horizontal resolution of 1000 pixels could theoretically result in the column output stage of a selected column readout circuit  101  having to drive the load capacitance associated with the other 999 columns. The parasitic capacitance in such a case could effectively be in the tens or even hundreds of picofarads.  
         [0021]     A larger capacitance requires longer time to charge the capacitance to a desired voltage value, and results in a greater RC time constant which translates into greater settling time. To increase pixel readout rate at a predetermined maximum frame rate necessarily involves minimizing the effective load capacitance seen by a selected column output buffer (transistor  110 ,  111 ).  
         [0022]     Settling time may be improved by increasing the biasing current on the column output buffer. The time to charge up a capacitance to a certain voltage is well known and may be represented by the following equation:  
         I   avg     =     C   ⁢       ⅆ   V       ⅆ   t             
       dt   =       C     I   avg       ⁢   dV         
 
         [0023]     Increasing the current would mean more power dissipation since P diss =V*I. For portable video systems, power dissipation is a key issue because higher power dissipation would reduce the lifetime of the battery. The present inventor has determined this not a desirable or optimum solution.  
         [0024]     Settling time may also be reduced by reducing the effective load capacitance on the column output buffer. A technique for reducing effective load capacitance for faster readout is called tree-style column decoding. An example of a RAM tree-style column decoder and multiplexer is shown in  FIG. 5 . Data bit lines are coupled to a pool of switches (transistors  401 ) which are selectively enabled to drive only a desired data bit through to a shared bit line  402 . In the configuration shown, a selected bit line receives a parasitic capacitance contribution from at least four transistors. With such a scheme, however, the overall effective capacitance seen on the shared bit line  402  can be reduced by as much as half that which might be imparted were all eight bit lines to be directly coupled to shared bit line  402  by only a single parallel bank of eight transistors.  
         [0025]     Tree-style column decoding reduces the effective capacitance seen by each bit output line.  
         [0026]     The present inventor has discovered that by splitting the column circuitry into different blocks, as will be explained in greater detail below, the readout bus capacitance seen by a currently selected column output stage could be significantly reduced beyond that possible by known techniques.  
         [0027]     In accordance with a preferred embodiment, the load capacitance is mathematically modeled. The effective RC constant seen by any column output stage at a particular time is determined. By using a differentiated derived equation, a desirable optimum number of connections per block as well as a desired number of blocks for a given size of column readout circuits can be easily determined from this equation.  
         [0028]     An improved configuration for coupling the column output stages resulting in reduced parasitic capacitance effects is illustrated in  FIG. 6 .  FIG. 6  shows the column readout circuits  101 . Only one portion of the respective column out put stage is shown. These are logically divided up into blocks  200 , each comprised of k contiguous column readout circuits. A set of block switches (n channel transistors)  601  are used to select among the blocks  200 . Each switch  601  functions as a block select switch allowing the column readout circuits  101  in a given block to become actively coupled to the shared column readout line  500 . Block switches  601  are used to select among the blocks  200  every time an associated column readout circuit  101  is to be turned ON. Once a column readout circuit  101  is selected for readout, its corresponding block switch  601  is also selected, but none of the other block switches are selected. Those blocks  200  which are not selected prevent or block associated column readout circuits from imparting a parasitic capacitance on the shared readout line  500 , and/or on the column output stage of the currently active column readout circuit.  
         [0029]     Block switches  601  also collectively impart a proportionate parasitic capacitance on the currently active column readout circuit, regardless of whether or not they are connected. Thus, in an arrangement of 64-wide block column readout circuits servicing a 1024-pixel wide row, there would be a total 1024/64=8 blocks. Each of the eight block switch transistors  601  would impart a parasitic capacitance of its own. This capacitance of eight transistors, however, is much less than the collective capacitance of 1024 non-blocked column select transistors. In this regard, it might be said that block select switches  601  function as parasitic capacitance blockers.  
         [0030]     The present inventor has determined that the optimum number of column readout circuits  101  per block  200  (i.e., the optimum value of k) for a given size pixel configuration may be calculated from the following mathematical quadratic relation, 
 
 C   p2 =( k+ 2 +m/k ) C   i ,  eq. (3) 
 
 for k (n-channel) column select transistors ( 110  or  111 ) and m/k groups, where m is the total number of column readout circuits  101 . The numeral 2 constant is derived from the parasitic capacitance of the group selection (nmos) transistor of the particular block being selected. This is based on a previous assumption that Ci is the parasitic capacitance of the source/drain diffusion of the nmos selection transistor. 
 
         [0031]     Minimizing C p2  in eq. (3) by differentiating C p2  with respect to k and equating it to zero, we get: 
 
(1 −m/k   2 ) C   i =0,  eq. (4) 
 
 solving for k, 
 
k=m 1/2 , 
 
 then substituting the value of k back into eq. (3), we get: 
 
 C   p2 =(2 m   1/2 +2) C   i .  eq. (5) 
 
         [0032]     Now, since each block switch transistor  601  is in series with a selected column output buffer (transistors  110  or  111 ), the result is a doubling in the effective resistance R imparted on each associated Vout_S, Vout_R column readout line  500 . The doubled resistance impacts doubly on the RC time constant settling time. This doubled resistance may be mathematically represented in terms of a relevant time constant from equations (2) and (3) as: 
 
 RC   p2 =2×(2 m   1/2 +2)* RC   I .  eq. (6) 
 
         [0033]     From the above, a parasitic capacitance improvement (or reduction) between C p1  (without block switching) and C p2  (with block switching) may be expressed as a ratio C p1 :C p2  as 
 
m:2m 1/2 +2,  eq. (7) 
        for large m, 2m 1/2 +2, approximates to 2m 1/2 , substituting back in eq. (7), we get a ratio of     m:2m 1/2 , which equates to a ratio of M 1/2 :2.        
 
         [0036]     Thus, for large m (e.g, 512, 1024, or greater), parasitic capacitance is effectively reduced by a factor of about m 1/2 /2. In a 1024-row architecture having block switching and an optimum block size of 32 (k=m 1/2 ), a parasitic capacitance reduction of 16 (=m 1/2 /2=32/2) may be realized over the case where no block switching is utilized.  
         [0037]     A similar analysis may be used to determine RC time constant improvement (or reduction) in the cases where there is no block switching (RC 1 ) versus the case where block switching (RC 2 ) is provided.  
         [0038]     Representing the two cases by RC p1 :RC p2 , from equations (6) and (7), we get 
 
m: 2 ×(2m 1/2 +2).  eq. (8). 
 
         [0039]     Here again, for large m, 
        2m 1/2 +2, approximates to 2m 1/2 , 
 
 substituting back in eq. (8), the ratio can be expressed as 
    m:4m 1/2 , 
 
 which equates to a ratio of m 1/2 :4. 
       
 
         [0042]     Thus it is shown that block switching can reduce the effective RC constant by a factor of about m 1/2 /4. Accordingly, for a pixel array of 1024×1024, the parasitic capacitance may be reduced by a factor of 8×2 (=10241/2/4×2), while the RC time constant is reduced by a factor of 8, by utilizing block switching. In a 32 (1024 1/2 ) block orientation, each column output stage is imparted an effective loading equivalent to having 1024/16=64 columns connected together.  
         [0043]      FIG. 7  shows the timing for effecting column selection in block group fashion in accordance with a preferred implementation in which it is contemplated that the column read out circuits  101  in a given block will be readout first. After all the columns in the block have been read out, the associated block switch is disabled, and the block switch associated with the next column readout circuit to be read out is enabled (turned ON).  
         [0044]     The present implementation has been described having only one level of block switches. Another embodiment uses multiple levels of cascaded stages of block switching to further reduce the effective parasitic capacitance seen by a selected column output stage.  
         [0045]     In summary, the present solution provides a way for reducing the effective load capacitance thereby allowing for an increase in pixel readout rate without any increase in power dissipation. It is contemplated however that the present solution also allows for a way to improve (reduce) power dissipation in applications where a low pixel readout is desirable.  
         [0046]     As should be readily apparent from the above discussion of the preferred embodiments, block switching provides additional advantages beyond those in conventional tree-style decoding. A typical tree-style single stage implementation decoding method reduces the effective load capacitance by a factor of 2. For n cascaded stages, the load capacitance is reduced by a factor of 2 n  at the expense of very high circuit complexity. The non-cascaded system of  FIG. 6  with a large image array with a horizontal resolution of 1024 could have its effective capacitance reduced by a factor of 16.  
         [0047]     This system can also increase the pixel readout rate (due to faster settling time) without any increase in the biasing current of the column output stages, and without introducing substantial circuit complexity to the overall active pixel sensor column readout architecture.  
         [0048]     Although only a few embodiments have been described in detail, those having ordinary skill in the art would certainly understand that many modifications are possible in the preferred embodiment without departing from the teachings thereof. For example, although the block switching is described in terms of “rows”, the blocks could be columns or any other shape of blocks.  
         [0049]     All such modifications are intended to be encompassed by the following claims.

Technology Category: h