Patent Document

CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims the benefit of Korean Patent Application No. 2005-6402, filed Jan. 24, 2005, the disclosure of which is hereby incorporated herein by reference in its entirety. 
   BACKGROUND OF THE INVENTION 
   The present invention relates to voltage generating circuits and methods, and more particularly, to circuits and methods for generating a voltage greater than a power supply voltage of a semiconductor memory device. 
   A conventional semiconductor memory device typically includes a plurality of memory cells, with each cell including a capacitor and an NMOS transistor. A gate of the NMOS transistor typically is connected to a word line. When a power supply voltage is applied to the gate of the NMOS transistor, the NMOS transistor is turned on, so that a ground voltage is transmitted without a loss in threshold voltage, while a power supply voltage is transmitted with a loss in threshold voltage. To transmit a power supply voltage without a loss in threshold voltage, a voltage higher than the power supply voltage typically is applied to the gate. In general, the high voltage is set to be greater than a threshold voltage of the NMOS transistor, added to a power supply voltage. The semiconductor memory device typically includes a high voltage generating circuit for generating the high voltage. 
     FIG. 1  is a diagram showing a conventional high voltage generating circuit. The high voltage generating circuit includes a high-voltage level detector  10 , a control signal generator  12 , and a high voltage generator  14 . The high voltage generator  14  is composed of capacitors C 1 -C 4  and switches SW 1 -SW 8 . Operations of the respective components shown in  FIG. 1  will now be described. 
   The high-voltage level detector  10  detects a high voltage VPP and generates a high-voltage level detection signal VPPEN when the high voltage VPP is lower than a target level. The control signal generator  12  drives the precharge signal P 1  and pump signals P 2 -P 4  in response to the high-voltage level detection signal VPPEN. The switches SW 1 , SW 2 , SW 3 , and SW 6  precharge each of nodes n 1 , n 2 , n 3 , and n 4  to a voltage VDD in response to the precharge signal P 1 . The capacitors C 1  and C 2  pump the nodes n 1  and n 2 , respectively, in response to the pump signal P 2 . The capacitor C 3  pumps the node n 3  in response to the pump signal P 3 , and the capacitor C 4  pumps the node  4  in response to the pump signal P 4 . The switch SW 4  is turned on in response to the pump signal P 2  and allows charge to be shared between the nodes n 2  and n 3 , and the switch SW 5  is turned on in response to the pump signal P 2  and allows charge to be shared between the nodes n 1  and n 4 . The switch SW 7  is turned on in response to the pump signal P 3  and allows charge to be shared between the nodes n 3  and n 4 . The switch SW 8  is turned on in response to the pump signal P 4  and allows charge to be shared between the node n 4  and a high voltage generating terminal n 5 . 
     FIG. 2  is a timing diagram illustrating operations of the high voltage generating circuit shown in  FIG. 1 . When the control signal generator  12  drives the precharge signal P 1  to a high level for a precharge period T 1 , the switches SW 1 , SW 2 , SW 3 , and SW 6  are turned on so that the nodes n 1  to n 4  are precharged to a power supply voltage VDD. 
   When the control signal generator  12  drives the pump signal P 2  to a high level during a first pumping period T 2 , the capacitors C 1  and C 2  pump the nodes n 1  and n 2  to a voltage 2 VDD. The switch SW 4  and SW 5  are turned on in response to the high level of the pump signal P 2 , so that charge is shared between the nodes n 1  and n 4  and between the nodes n 2  and n 3 , respectively. Thus, the nodes n 1 -n 4  reach a voltage 1.5 VDD. 
   When the control signal generator  12  drives the pump signal P 3  to a high level during a second pumping period T 3 , the capacitor C 3  pumps the node n 3  to a voltage 2.5 VDD. The switch SW 7  is turned on in response to the high level of the pump signal P 3 , so that charge is shared between the nodes n 3  and n 4 . Thus, the nodes n 3  and n 4  reach a voltage 2 VDD. 
   When the control signal generator  12  drives the pump signal P 4  to a high level during a third pumping period T 4 , the capacitor C 4  pumps the node n 4  to a voltage 3 VDD. The switch SW 8  is turned on in response to the high level of the pump signal P 4 , so that charge is shared between the node n 4  and the high voltage generating terminal n 5 . Thus, the node n 4  and the high voltage generating terminal n 5  are pumped to a voltage α. In this manner, the high voltage generating terminal n 5  can reach a maximum voltage 3 VDD. The high voltage generating circuit shown in  FIG. 1  includes four pumping capacitors C 1 -C 4  and performs a three-stage pumping operation to produce a maximum voltage 3 VDD. 
     FIG. 3  is a diagram showing another conventional high voltage generating circuit. The high voltage generating circuit includes a high-voltage level detector  20 , a control signal generator  22 , and a high voltage generator  24 . The high voltage generator  24  includes capacitors C 5  and C 6  and switches SW 10 -SW 15 . Functions of the respective components shown in  FIG. 3  will now be described. 
   The high-voltage level detector  20  detects a high voltage VPP and generates a high-voltage level detection signal VPPEN when the high voltage VPP is lower than a target level. The control signal generator  22  drives the precharge signal P 1  and a pump signal P 2  in response to the high-voltage level detection signal. The switches SW 10 , SW 11 , SW 13 , and SW 14  precharge nodes n 5  and n 7  to a ground voltage in response to the precharge signal P 1  and precharge nodes n 6  and n 8  to a power supply voltage VDD. The switch SW 12  connects the nodes n 6  and n 7  in response to the pump signal P 2 , and the switch SW 15  connects the node n 8  and a high voltage generating terminal n 9  in response to the pump signal P 2 . 
     FIG. 4  is a timing diagram illustrating operations of the high voltage generating circuit shown in  FIG. 3 . When the control signal generator  22  drives the precharge signal P 1  to a high level during a precharge period T 1 , all the switches SW 10 , SW 11 , SW 13 , and SW 14  are turned on so that the nodes n 5  and n 7  are precharged to a ground voltage and the nodes n 6  and n 8  are precharged to a power supply voltage VDD. When the control signal generator  22  drives the pump signal P 2  to a high level during a pumping period T 2 , the node n 5  reaches a power supply voltage VDD, and the capacitor C 5  pumps the node n 6  to a voltage 2 VDD. Because the switch SW 12  is turned on, the node n 7  reaches a voltage 2 VDD like the node n 6 , and the capacitor C 6  pumps the node n 8  to a voltage 3 VDD. Because the switch SW 15  is turned on, charge is shared between the node n 8  and a high voltage generating terminal n 9 , so that the node n 8  and the high voltage generating terminal n 9  are pumped to a voltage α. In this manner, the high voltage generating terminal n 9  may reach a maximum voltage 3 VDD. That is, the high voltage generating circuit shown in  FIG. 3  includes two pumping capacitors C 5  and C 6  and performs a single pumping operation to produce a maximum voltage 3 VDD. Accordingly, the high voltage generating circuit shown in  FIG. 3  includes fewer pumping capacitors than the high voltage generating circuit shown in  FIG. 1  and may generate a target high voltage with a single pumping operation. 
   However, semiconductor memory devices generally are being designed with increasingly lower power supply voltage and faster operation as semiconductor manufacturing technologies progress. If a target level for a high voltage decreases, a conventional high voltage generating circuit may be used to generate the target high voltage. However, as power supply voltage decreases, decreases in high voltage may be limited, because the threshold voltage of an NMOS transistor generally cannot be decreased below a certain value. Also, because the period of a high-voltage level detection signal is shortened due to high-speed operation, it is desirable to reduce the number of pumping operations needed to generate a high voltage. Therefore, it is desirable to provide a high voltage generating circuit having excellent pumping capability without an undue number of pumping operations. 
   SUMMARY OF THE INVENTION 
   In some embodiments of the present invention, a high voltage generating circuit includes a high-voltage level detector for detecting a level of high voltage to generate a high-voltage level detection signal. The high voltage generating circuit also includes a control signal generator for generating a precharge control signal and first and second pumping control signals in response to the high-voltage level detection signal. The high voltage generating circuit further includes a high voltage generator including a first pumper and a second pumper, the first pumper including first and second capacitors, pumping a first output node by serially connecting the first and second capacitors in response to the first pumping control signal, and allowing charges to be shared between the first output node and a second output node, the second pumper including third and fourth capacitors, pumping the second output node by serially connecting the third and fourth capacitors in response to the second pumping control signal, and allowing charges to be shared between the second output node and a high voltage generating terminal, the high voltage generator for connecting the first, second, third, and fourth capacitors between a first precharge voltage level and a second precharge voltage level in response to the precharge control signal. 
   In some embodiments, the first pumper comprises a first precharge circuit for precharging a first node to the first precharge voltage level in response to the precharge control signal, a second precharge circuit for precharging a second node to the second precharge voltage level in response to the precharge control signal, a third precharge circuit for precharging the first output node to the first precharge voltage level in response to the precharge control signal, a first switch for connecting the first and second nodes in response to the first pumping control signal, and a second switch for allowing charges to be shared between the first and second output nodes in response to the first pumping control signal, wherein the first capacitor is connected between the first pumping control signal and the first node, and the second capacitor is connected between the second node and the first output node. The first precharge voltage level is a power supply voltage level, and the second precharge voltage level is a ground voltage level. The second pumper comprises a fourth precharge circuit for precharging a third node to the first precharge voltage level in response to the precharge control signal, a fifth precharge circuit for precharging a fourth node to the second precharge voltage level in response to a phase-inverted signal of the second pumping control signal, a sixth precharge circuit for precharging the second output node to the first precharge voltage level in response to the precharge control signal, a third switch for connecting the third to and the fourth node in response to the second pumping control signal, and a fourth switch for allowing charges to be shared between the second output node and the high voltage generating terminal in response to the second pumping control signal, wherein the third capacitor is connected between the second pumping control signal and the third node, and the fourth capacitor is connected between the fourth node and the second output node. The first precharge voltage level is a power supply voltage level, and the second precharge voltage level is a ground voltage level. 
   In additional embodiments of the present invention, a high voltage generating circuit includes a high-voltage level detector for detecting a level of high voltage to generate a high-voltage level detection signal. The high voltage generating circuit also includes a control signal generator for generating a precharge control signal and first and second pumping control signals in response to the high-voltage level detection signal. The high voltage generating circuit further includes a high voltage generator including a first pumper and a second pumper, the first pumper including a first capacitor, pumping a first output node in response to the first pumping control signal, and allowing charges to be shared between the first output node and a second output node, the second pumper including second and third capacitors, pumping the second output node by serially connecting the second and third capacitors in response to the second pumping control signal, and allowing charges to be shared between the second output node and a high voltage generating terminal, the high voltage generator for connecting the first, second, and third capacitors between a first precharge voltage level and a second precharge voltage level in response to the precharge control signal. 
   In some embodiments, the first pumper comprises a first precharge circuit for precharging the first output node to the first precharge voltage level in response to the precharge control signal, and a first switch for allowing charges to be shared between the first and second output nodes in response to the first pumping control signal, wherein the first capacitor is connected between the first pumping control signal and the first output node. The first precharge voltage level is a power supply voltage level, and the second precharge voltage level is a ground voltage level. The second pumper comprises a second precharge circuit for precharging a first node to the first precharge voltage level in response to the precharge control signal, a third precharge circuit for precharging a second node to the second precharge voltage level in response to a phase-inverted signal of the second pumping control signal, a fourth precharge circuit for precharging the second output node to the first precharge voltage level in response to the precharge control signal, a second switch for connecting the first and second nodes in response to the second pumping control signal, and a third switch for allowing charges to be shared between the second output node and the high voltage generating terminal in response to the second pumping control signal, wherein the second capacitor is connected between the second pumping control signal and the first node, and the third capacitor is connected between the second node and the second output node. The first precharge voltage level is a power supply voltage level, and the second precharge voltage level is a ground voltage level. 
   In some method embodiments, a method for generating a high voltage includes generating a high-voltage level detection signal by detecting a high voltage level, generating a precharge control signal and first and second pumping control signals in response to the high-voltage level detection signal, precharging a first node, a third node, a first output node, and a second output node to a first precharge voltage level and precharging a second node and a fourth node to a second precharge voltage level in response to the precharge control signal, pumping the first node by a first capacitor in response to the first pumping control signal, connecting the first and second nodes, pumping the first output node by a second capacitor in response to a level of the second node, and sharing charges between the first and second output nodes, and pumping the third node by a third capacitor in response to the second pumping control signal, connecting the third node and the fourth node, pumping the second output node by a fourth capacitor in response to a level of the fourth node, and sharing charges between the second output node and a high voltage generating terminal. 
   In further embodiments, a high voltage generating method includes detecting a high voltage level to generate a high-voltage level detection signal, generating a precharge control signal and first and second pumping control signals in response to the high-voltage level detection signal, precharging first and second output nodes and a first node to a first precharge voltage level and precharging a second node to a second precharge voltage level in response to the precharge control signal, pumping the first output node by a first capacitor in response to the first pumping control signal and sharing charges between the first and second output nodes, and pumping the first node by a second capacitor in response to the second pumping control signal, connecting the first and second nodes, pumping the second output node by a third capacitor in response to a level of the second node, and sharing charges between the second output node and a high voltage generating terminal. 
   In further embodiments, a semiconductor memory device includes: a high voltage generating circuit, which includes a high-voltage level detector for detecting a high voltage level to generate a high-voltage level detection signal, a control signal generator for generating a precharge control signal and first and second pumping control signals in response to the high-voltage level detection signal, and a high voltage generator including a first pumper and a second pumper, the first pumper including first and second capacitors, pumping a first output node by serially connecting the first and second capacitors in response to the first pumping control signal, and allowing charges to be shared between the first output node and a second output node, the second pumper including third and fourth capacitors, pumping the second output node by serially connecting the third and fourth capacitors in response to the second pumping control signal, and allowing charges to be shared between the second output node and a high voltage generating terminal, the high voltage generator for connecting the first, second, third, and fourth capacitors between a first precharge voltage level and a second precharge voltage level in response to the precharge control signal. 
   In still further embodiments, a semiconductor memory device includes: a high voltage generating circuit, which includes a high-voltage level detector for detecting a high voltage level to generate a high-voltage level detection signal, a control signal generator for generating a precharge control signal and first and second pumping control signals in response to the high-voltage level detection signal, and a high voltage generator including a first pumper and a second pumper, the first pumper including a first capacitor, pumping a first output node in response to the first pumping control signal, and allowing charges to be shared between the first output node and a second output node, the second pumper including second and third capacitors, pumping the second output node by serially connecting the second and third capacitors in response to the second pumping control signal, and allowing charges to be shared between the second output node and a high voltage generating terminal, the high voltage generator for connecting the first, second, and third capacitors between a first precharge voltage level and a second precharge voltage level in response to the precharge control signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram showing a conventional high voltage generating circuit; 
       FIG. 2  is a timing diagram illustrating operations of the high voltage generating circuit shown in  FIG. 1 ; 
       FIG. 3  is a diagram showing another conventional high voltage generating circuit; 
       FIG. 4  is a timing diagram illustrating operations of the high voltage generating circuit shown in  FIG. 3 ; 
       FIG. 5  is a diagram showing a high voltage generating circuit according to some embodiments of the present invention; 
       FIG. 6  is a timing diagram illustrating operations of the high voltage generating circuit shown in  FIG. 5 ; 
       FIG. 7  is a diagram showing a high voltage generating circuit according to further embodiments of the present invention; and 
       FIG. 8  is a timing diagram illustrating operations of the high voltage generating circuit shown in  FIG. 7 . 
   

   DETAILED DESCRIPTION 
   The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the sizes or configurations of elements may be idealized or exaggerated for clarity. 
   It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected to” or “directly coupled to” another element, there are no intervening elements present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
   It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components and/or sections, these elements, components and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, or section from another element, region or section. Thus, a first element, component or section discussed below could be termed a second element, component or section without departing from the teachings of the present invention. 
   The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
   Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
   As described herein, operations according to some embodiments of the present invention involve driving or transitioning signal lines, e.g., “pump signal lines”, to a predetermined voltage, e.g., a power supply voltage or a ground voltage. As used herein, driving a signal line “to” a particular voltage includes driving the signal line “toward” the voltage in question. For example, driving a signal line “to a power supply voltage” includes driving the line to the point at which it actually achieves that voltage and/or driving the signal line substantially toward such voltage. Thus, for example, a driving operation that drives a signal line through a device, such as a transistor, such that it approaches the power supply voltage, but does not fully reach the power supply voltage because of a threshold voltage or diode drop associated with the transistor, nonetheless falls within the scope of driving the line “to” the power supply voltage. 
     FIG. 5  is a diagram showing a high voltage generating circuit  500  according to some embodiments of the present invention. The high voltage generating circuit  500  includes a high-voltage level detector  30 , a control signal generator  32 , and a high voltage generator  34 . The high voltage generator  34  includes a first pump circuit  34 - 1  and a second pump circuit  34 - 2 . The first pump circuit  34 - 1  includes capacitors C 7  and C 8  and switches SW 20 -SW 23  and SW 28 . The second pump circuit  34 - 2  includes capacitors C 9  and C 10  and switches SW 24 -SW 27  and SW 29 . Functions of the circuit  500  shown in  FIG. 5  will now be described. 
   The high-voltage level detector  30  detects a high voltage VPP and generates a high-voltage level detection signal VPPEN when the high voltage VPP is lower than a target level. The control signal generator  32  generates the precharge signal P 1  and pump signals P 2  and P 3  in response to the high-voltage level detection signal VPPEN. The switches SW 20 , SW 23 , SW 24 , and SW 27  precharge nodes n 10 , n 12 , n 13 , and n 15  to a power supply voltage VDD in response to the precharge signal P 1 . The switch SW 22  precharges node n 11  to a ground voltage in response to the precharge signal P 1 . The switch SW 21  connects the nodes n 10  and n 11  in response to the pump signal P 2 , and the switch SW 22  connects the nodes n 12  and n 15  in response to the pump signal P 2 . The switch SW 25  connects the node n 13  and a node  14  in response to the pump signal P 3 , and the switch SW 29  connects the node n 15  and a high voltage generating terminal n 16  in response to the pump signal P 3 . The switch SW 26  precharges the node n 14  to a ground voltage in response to an inverted pump signal P 3 B. The capacitors C 7  and C 8  perform pumping operations in response to the pump signal P 2 , and the capacitors C 9  and C 10  perform pumping operations in response to the pump signal P 3 . 
     FIG. 6  is a timing diagram illustrating operations of the high voltage generating circuit  500  shown in  FIG. 5 . When the control signal generator  32  drives the precharge signal P 1  to a high level during a precharge period T 1 , the switches SW 20 , SW 22 , SW 23 , SW 24 , and SW 27  are turned on so that the nodes n 10 , n 12 , n 13 , and n 15  are precharged to a power supply voltage VDD, and the switch SW 22  is turned on so that the node n 11  is precharged to a ground voltage. The inverted pump signal P 3 B is at a high level, such that the switch SW 26  is turned on so that the node n 14  is precharged to the ground voltage. 
   When the control signal generator  32  drives the pump signal P 2  to a high level during a first pumping period T 2 , the switch SW 2  is turned on, so that the nodes n 10  and n 11  are connected to each other and the capacitor C 7  pumps the nodes n 10  and n 11  to a voltage 2 VDD. Once the node n 11  reaches the voltage 2 VDD, the capacitor C 8  pumps the node n 12  to a voltage 3 VDD. The switch SW 28  is turned on in response to the high level of the pump signal P 2 , so that charge is shared between the nodes n 12  and n 15 . Thus, each of the nodes n 12  and n 15  reaches a voltage 2 VDD. Because the inverted pump signal P 3 B is at a high level, the switch SW 26  is turned on so that the node n 14  is maintained at the ground voltage. 
   The circuit may be designed such that the capacitances of the capacitors C 7  and C 8  are equal to the capacitance of the capacitor C 10 . In other words, if the capacitance of each of the capacitors C 7  and C 8  is C, because the total capacitance of the serially connected capacitors C 7  and C 8  is C/2, the capacitance of the capacitor C 10  may be C/2. Also, because the capacitance of the capacitor C 9  may be equal to the capacitance of the capacitor C 10  that is serially connected to the capacitor C 9 , the capacitance of the capacitor C 9  may be C/2. 
   When the control signal generator  32  drives a pump signal P 3  to a high level during a second pumping period T 3 , the switches SW 25  and SW 29  are turned on and the switch SW 26  is turned off, so that the node n 13  is connected to the node  14  and the node n 15  is connected to the high voltage generating terminal. The capacitor C 9  pumps the nodes n 13  and n 14  to a voltage 2 VDD in response to the high level of the pump signal P 3  to a high level. Once the node n 14  reaches the voltage 2 VDD, the capacitor C 10  pumps the node n 15  to a voltage 4 VDD. Because the switch SW 29  remains turned on, charge is shared between the node n 15  and the high voltage generating terminal n 16 , so that the node n 15  and the high voltage generating terminal n 16  reach a voltage β. In this manner, the high voltage generating circuit  500  may generate a high voltage VPP to a voltage 4 VDD. 
   The high voltage generating circuit shown in  FIG. 5  performs a two-stage pumping operation so that a maximum voltage 4 VDD may be obtained. Accordingly, even if the period of the high-voltage level detection signal VPPEN is shortened, the high voltage VPP may be maintained, and even if a power supply voltage is lowered, a highest pumping voltage may be elevated, thus a target high voltage VPP may be generated. 
     FIG. 7  is a diagram showing a high voltage generating circuit  700  according to further embodiments of the present invention. The high voltage generating circuit  700  includes a high-voltage level detector  40 , a control signal generator  42 , and a high voltage generator  44 . The high voltage generator  44  includes a first pump circuit  44 - 1  and a second pump circuit  44 - 2 . The first pump circuit  44 - 1  includes a capacitor C 11  and switches SW 30  and SW 35 , and the second pump circuit  44 - 2  includes capacitors C 12  and C 13  and switches SW 31 -SW 34  and SW 36 . Operations of the circuit  700  shown in  FIG. 7  will now be described. 
   The high-voltage level detector  40  detects a high voltage VPP and generates a high-voltage level detection signal VPPEN when the high voltage VPP is lower than a target level. The control signal generator  42  generates the precharge signal P 1  and pump signals P 2  and P 3  in response to the high-voltage level detection signal VPPEN. The switches SW 30 , SW 31 , and SW 34  precharge nodes n 20 , n 21 , and n 23  to a power supply voltage VDD in response to the pump signal P 1 . The switch SW 35  allows charge to be shared between the nodes n 20  and n 23  in response to the pump signal P 2 . The switch SW 32  connects the node n 21  and a node n 22  in response to the pump signal P 3 , and the switch SW 36  allows charge to be shared between the node n 23  and a high voltage generating terminal n 24  in response to the pump signal P 3 . The switch SW 33  precharges the node n 22  to a ground voltage in response to an inverted pump signal P 3 B. 
     FIG. 8  is a timing diagram illustrating the operation of the high voltage generating circuit shown in  FIG. 7 . When the control signal generator  42  drives the precharge signal P 1  to a high level during a precharge period T 1 , the switches SW 30 , SW 31 , and SW 34  are turned on, so that the nodes n 20 , n 21 , and n 23  are precharged to a power supply voltage VDD. When the control signal generator  42  drives the inverted pump signal P 3 B to a high level during the period T 1 , the switch SW 33  is turned on, so that the node n 22  is precharged to a ground voltage. 
   When the control signal generator  42  drives a pump signal P 2  to a high level during a first pumping period T 2 , the capacitor C 11  pumps the node n 20  to a voltage 2 VDD, and the switch SW 35  is turned on in response to the high level of the pump signal P 2  so that charge is shared between the nodes n 20  and n 23 . Thus, the nodes n 20  and n 23  reach a voltage 1.5 VDD. Because the control signal generator  42  continues to drive the inverted pump signal P 3 B to a high level, the switch SW 33  is turned on so that the node n 22  is maintained at the ground voltage. In some embodiments, the capacitance of the capacitor C 11  is equal to the capacitance of the capacitor C 13 , i.e., if the capacitance of the capacitor C 11  is C, the capacitance of the capacitor C 13  may be C. The capacitance of the capacitor C 12  may be equal to the capacitance of the capacitor C 13  that is serially connected to the capacitor C 12 , e.g., the capacitance of the capacitor C 12  may also be C. 
   When the control signal generator  42  drives the pump signal P 3  to a high level during a second pumping period T 3 , the switches SW 32  and SW 36  are turned on and the switch SW 33  is turned off, so that the node n 21  is connected to the node  22  and the node n 23  is connected to the high voltage generating terminal n 24 . The capacitor C 12  pumps the nodes n 21  and n 22  to a voltage 2 VDD in response to the high level of the pump signal P 3 . Once the node n 22  reaches the voltage 2 VDD, the capacitor C 13  pumps the node n 23  to a voltage 3.5 VDD. Because the switch SW 36  remains turned on, charge is shared between the node n 23  and the high voltage generating terminal n 24 , so that the node n 23  and the high voltage generating terminal n 24  reach a voltage. In this manner, the high voltage generating circuit  700  may generate a high voltage VPP to a maximum voltage 3.5 VDD. 
   The high voltage generating circuit  700  shown in  FIG. 7  performs a two-stage pumping operation so that a maximum voltage 3.5 VDD may be obtained. Although the highest pumping voltage is lower than that of the high voltage generating circuit  500  shown in  FIG. 5 , the number of capacitors may be reduced in comparison to the high voltage generating circuit  500  shown in  FIG. 5 . Like the high voltage generating circuit shown in  FIG. 5 , even if the period of the high-voltage level detection signal VPPEN is shortened, the high voltage VPP may be maintained. Also, even if a power supply voltage is lowered, a highest pumping voltage may be elevated, thus a target high voltage VPP may be generated. 
   In the above-described exemplary embodiments, precharge nodes are precharged at the same time during the precharge period T 1 . However, directly after the first pumping period T 2  comes to an end, each of the precharge nodes n 10 , n 11 , and n 12  of  FIG. 5  or the precharge node n 20  of  FIG. 7  may be precharged to a precharge voltage. 
   In the above-described exemplary embodiments, high voltage generating circuits and methods may be applied to semiconductor memory devices with low power supply voltage and high-speed operations. High voltage generating circuits and methods according to some embodiments of the present invention may stably generate a target high voltage even if a power supply voltage is lowered and the period of a high-voltage level detection signal is shortened. Consequently, high voltage generating circuits and methods according to embodiments of the present invention may be applied to a semiconductor memory device to increase reliability of the device. 
   The foregoing is illustrative of the present invention and is not to be construed as limiting thereof. Although a few exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.

Technology Category: h