Patent Document

BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a conductive landing pad of a semiconductor device which connects a lower plug with an upper interconnection, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device in which a contact area between a lower plug and a landing pad is increased, so that detachment of the landing pad from the lower plug or a wafer can be prevented.  
           [0003]    2. Description of the Related Art  
           [0004]    Semiconductor devices have a multi-layered structure, in which upper interconnections are connected to lower plugs by landing pads formed in the interlevel dielectric (ILD) film between the upper interconnection and the lower plug. In general, the landing pad is formed of tungsten having a low resistivity. Unfortunately, tungsten also has strong tensile strength, so it has poor adhesiveness with respect to the ILD film made of silicon oxide, in which the landing pad is located. As a result, the landing pad made of tungsten is liable to be detached from the ILD film or a wafer. This detachment problem is inevitable when the landing pad is formed of a material having poor adhesiveness to the ILD film.  
           [0005]    In particular, an ILD film is deposited over lower plugs and etched to form grooves for landing pads. Following this, a conductive material, for example, tungsten, is deposited over the ILD film to fill the grooves, and subjected to mechanical and chemical polishing using a slurry until the ILD film is exposed, thereby resulting in completed landing pads. The slurry used in the mechanical and chemical polishing aggregates by heat generated as the wafer is turned, so that it cannot be easily removed from the wafer. When the mechanical and chemical polishing is continued, the surface of the wafer is scratched and the landing pad formed of tungsten is separated from the ILD film and the lower plugs.  
           [0006]    When the formation of the landing pad is completed, the wafer with the landing pad is subjected to washing and drying processes. The drying process is performed by spin drying. “Spin drying” refers to removing water used in the washing process from the wafer surface by centrifugal force generated as the water is turned. Although the landing pads remain in the ILD film through the mechanical and chemical polishing process, it is more likely that the landing pads passed through the mechanical and chemical polishing process are liable to be detached from the wafer surface during the spin drying processes. The separation of the landing pads causes poor electrical connections in the resultant semiconductor device. Furthermore, the detachment of the landing pads becomes serious with an increase in the integration density of semiconductor devices.  
           [0007]    To account for the detachment of landing pads, a technique of placing an adhesive layer formed of TiN or TaN, which has excellent adhesiveness to an ILD film, between the ILD film and landing pads formed of tungsten has been suggested. Although the adhesive layer is interposed between the ILD film and the landing pads, the landing pads cannot remain intact in the ILD film through subsequent mechanical and chemical polishing, washing and drying processes, which are carried out after filling grooves for landing pads in the ILD. On the other hand, in order to ensure strong adhesiveness between the landing pads and the ILD film with the adhesive layer, the landing pads must be larger than a predetermined dimension, which restricts the integration density of semiconductor devices.  
           [0008]    Another approach used to overcome the detachment of landing pads is to increase the contact area between landing pads and lower plugs by etching a lower insulating layer, in which the lower plugs are to be formed, as well as the ILD film to form grooves for the landing pads. However, this overetching technique needs a lower insulating layer having increased thickness to ensure a sufficient processing margin for deep grooves, so that the aspect ratio of openings for the lower plugs formed in the lower insulating layer increases. In this way, because the grooves for the landing pads are formed over the ILD film and the lower insulating layer, the aspect ratio of the grooves also increases. Such increased aspect ratios cause difficulties in etching the ILD film and the lower insulating layer. In addition, the openings for the lower plugs and the grooves for the landing pads are filled with conductive materials, voids more likely occur within the openings and the grooves. With the increase in the integration density of semiconductor devices, these problems become serious.  
         SUMMARY OF THE INVENTION  
         [0009]    To solve the above problems, it is an objective of the present invention to provide a semiconductor device having a combination of lower plugs and a conductive layer, and a method for manufacturing the semiconductor device, in which separation of the conductive layer from an interlevel dielectric film (ILD) and the lower plugs can be suppressed even when a fine pattern is adopted to increase the integration density of semiconductor devices.  
           [0010]    It is another objective of the present invention to provide a semiconductor device having a combination of lower plugs and a conductive layer, and a method for manufacturing the semiconductor device, in which less consideration is needed in etching openings for the lower plugs and grooves for the conductive layer, and prevents occurrence of voids in the lower plugs and the conductive layer.  
           [0011]    According to an aspect of the present invention, there is provided a semiconductor device including a first interlevel dielectric (ILD) film having an opening. A diffusion barrier layer is formed along the first ILD film having the opening. A lower plug having a recession is formed in the opening coated with the diffusion barrier layer. The semiconductor device also includes a second ILD film having a groove through which at least the recession of the lower plug is exposed, the second ILD film being formed over the first ILD film. An adhesive layer is formed on the groove of the second ILD film and the recession of the lower plug. A conductive layer is deposited on the adhesive layer to fill the groove of the second ILD film and the recession of the lower plug.  
           [0012]    The adhesive layer may be formed on a portion of the recession of the lower plug, or over the recession of the lower plug according to the processing conditions. It is preferable that the diameter of the recession is ¼-½ of the diameter of the opening of the first ILD film.  
           [0013]    The lower plug may be formed of a metal, preferably, aluminum, copper or tungsten. The conductive layer may be formed of a metal such as tungsten, copper, aluminum, refractory metal and refractory metal silicide.  
           [0014]    According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device. In accordance with the method, a first interlevel dielectric (ILD) film is formed with an opening over a semiconductor substrate. A diffusion barrier layer is formed along the first ILD film having the opening. A first conductive layer having a recession is formed in the opening of the first ILD film coated with diffusion barrier layer, and a second ILD film having a groove, through which at least the recession of the lower plug is exposed, is formed over the first ILD film. A metal is deposited over the second ILD film having the groove to form an adhesive layer on the groove of the second ILD film and the recession of the lower plug. A conductive layer is formed over the adhesive layer such that the conductive layer fills the groove of the second ILD film and the recession of the lower plug. In the manufacture of the semiconductor device, the first conductive layer is a lower plug, and the second conductive layer is a landing pad.  
           [0015]    In another embodiment, the semiconductor device manufacturing method according to the present invention comprises preparing a semiconductor substrate in which an active region is defined. A first interlevel dielectric (ILD) film with an opening, through which the active region is exposed, is formed over the semiconductor substrate. A diffusion barrier layer is formed along the first ILD film having the opening. A first conductive layer is deposited over semiconductor substrate having the diffusion barrier layer, such that the opening of the first ILD film is not completely filled. The first conductive layer and the diffusion barrier layer are etched until the surface of the first ILD film is exposed, thereby resulting in a lower plug having a recession. A second ILD film having a groove, through which at least the recession of the lower plug is exposed, is formed over the first ILD film. A metal is deposited over the second ILD film having the groove to form an adhesive layer on the groove of the second ILD film and the recession of the lower plug. A second conductive layer is formed over the adhesive layer such that the second conductive layer fills the groove of the second ILD film and the recession of the lower plug. The adhesive layer and the second ILD film are etched until the surface of the second ILD film is exposed, so that a landing pad filling the groove and the recession is formed.  
           [0016]    The adhesive layer may be formed on a portion of the recession of the lower plug, or over the recession of the lower plug according to the processing conditions. It is preferable that the diameter of the recession is ¼-½ of the diameter of the opening of the first ILD film.  
           [0017]    In one embodiment, forming the lower plug includes forming a conductive material layer over the first ILD film having the opening coated with the diffusion barrier layer, such that the opening of the first ILD film is not completely filled. The conductive material layer is etched until the top of the first ILD film is exposed. The conductive material layer can be etched by mechanical and chemical polishing.  
           [0018]    In one embodiment, forming the conductive layer includes forming a conductive material layer over the second ILD film coated with the adhesive layer such that the groove of the second ILD film and the recession of the lower plug are completely filled. The conductive material layer is etched until the top of the second ILD film is exposed. The conductive material layer can be etched by either mechanical and chemical polishing or dry etching. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]    The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.  
         [0020]    [0020]FIG. 1 is a sectional view of an embodiment of a semiconductor device having landing pads, which connect lower plugs and upper interconnection, according to the present invention.  
         [0021]    [0021]FIG. 2 is a sectional view of another embodiment of a semiconductor device having landing pads, which connect lower plugs and upper interconnection, according to the present invention.  
         [0022]    [0022]FIGS. 3 through 6 illustrate an embodiment of a method of forming landing pads of a semiconductor device according to the present invention.  
         [0023]    [0023]FIGS. 7 and 8 illustrate another embodiment of a method of forming landing pads of a semiconductor device according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]    A preferred embodiment of a semiconductor device according to the present invention is shown in FIG. 1. Referring to FIG. 1, a source region  308   a  and a drain region  308   b  are defined in a semiconductor substrate  300 , and a gate electrode assembly G 3  is formed on the semiconductor substrate  300 . The gate electrode assembly G 3  includes a gate insulating layer  302  formed on the semiconductor substrate  300 , a gate electrode  304  made of a conductive material, and a spacer  306  formed on the sidewalls of the gate electrode  304 . A first interlevel dielectric (ILD) film  310  is formed over the semiconductor substrate  300  having the gate electrode assembly G 3 . Openings, which partially expose the source region  308   a  and the drain region  308   b , are formed in the first ILD film  310 . A diffusion barrier layer  314   a  is formed along the inner walls and bottom of the openings. The diffusion barrier layer  314   a  may be formed of a titanium layer, a titanium nitride layer, a tantalum nitride layer, or a titanium/titanium nitride layer. A lower plug  316   a  having a recession, as a first conductive layer, is formed in each of the openings coated with the diffusion barrier layer  314   a . The diameter C of the recession is ¼-½ of the diameter R of the opening. The first conductive layer, i.e., the lower plug  316   a,  is formed of a metal, preferably, tungsten, copper or aluminum.  
         [0025]    A second ILD film  318  having grooves  319   a  and  319   b,  through which at least the recession  317  (see FIG. 4) of the lower plug  316   a  is exposed, is formed on the first ILD film  310 . In particular, one groove  319   a  of the second ILD film  318 , which is located on the left side of FIG. 1, exposes the diffusion barrier layer  314   a  and the lower plugs  316   a,  while the other groove  319   b  of the second ILD film  318 , which is located on the right side of FIG. 1, exposes a portion of the first ILD film  310  as well as the diffusion barrier layer  314   a  and the lower plug  316   a.  An adhesive layer  320  is coated along the insides of the grooves. In particular, as shown in FIG. 1, as for the groove  319   a  of the second ILD film  318 , the inner sidewalls of the groove  319   a,  the top of the lower plug  316   a,  and a portion of the recession  317  (see FIG. 4) are coated with the adhesive layer  320 . As for the groove  319   b  of the second ILD film  318 , the inner sidewalls of the groove  319   b,  the top of the lower plug  316   a,  and the exposed top of the first ILD film  310  and a portion of the recession  317  (see FIG. 4) are coated with the adhesive layer  320 . The adhesive layer  320 , which serves to improve adhesiveness between the second IDL film made of an oxide and a second conductive layer, i.e., a landing pad  211   a  and a lower interconnection  322   b,  to be formed in a subsequent step, is formed of a titanium nitride layer or a tantalum nitride layer. The grooves  319   a  and  319   b  coated with the adhesive layer  320  and the recessions of the lower plugs  316   a  are filled with a conductive material, thereby resulting in the landing pad  322   a  and the lower interconnection  322   b  each of which has a projection protruding into the lower plugs  216   b.  The second conductive layer including the landing pad  322   a  and the lower interconnection  322   b  is formed of metal, preferably, tungsten, copper, aluminum, refractory metal or refractory metal silicide.  
         [0026]    Over the second ILD film  318  with the landing pad  322   a  and the lower interconnection  322   b , a third ILD film  324  having an opening, through which the top of the landing pad  322  is exposed, is deposited. An upper interconnection  328  is formed on the third ILD film  324 , filling the opening.  
         [0027]    Another embodiment of a semiconductor device according to the present invention is shown in FIG. 2. The semiconductor device shown in FIG. 2 is the same as the semiconductor device shown in FIG. 1, except that an adhesive layer  420  is formed to cover the entire recessions of lower plugs  416   b . As shown in FIG. 1, the adhesive layer can be formed on a portion of the recessions of the lower plugs  316   b,  or on the entire of the recessions of the lower plugs  416   b , as in the present embodiment, which depend on the material selected and the technique applied to form the adhesive layer  420 . In FIG. 2, reference numeral  400  represents a semiconductor substrate, reference character G 4  represents a gate electrode assembly including a gate electrode  404 , a gate insulating layer  402  and a spacer  406 , reference numeral  408   a  represents a source region, reference numeral  408   b  represents a drain region, reference numeral  410  represents a first ILD film, reference numeral  414   a  represents a diffusion barrier layer, reference numeral  416   b  represents a first conductive layer, i.e., the lower plugs having recessions, reference numeral  418  represents a second ILD film, reference numerals  419   a  and  419   b  represent grooves in the second ILD film  418 , reference numeral  420  represents the adhesive layer, reference numerals  421   a  and  421   b  represent projections corresponding to the recessions, reference numerals  422   a  and  422   b  represent a second conductive layer, i.e., landing pads having the projections  421   a  and  421   b,  reference numeral  424  represents a third ILD film, and reference numeral  428  represents an upper interconnection.  
         [0028]    An embodiment of a method for manufacturing a semiconductor device according to the present invention is illustrated in FIGS. 3 through 6. Referring to FIG. 1, an insulating layer (not shown) and a conductive material layer (not shown) are deposited over a semiconductor substrate  300  in succession, and patterned into a gate insulating layer  302  and a gate electrode  304 , respectively. An insulating layer (not shown) is deposited over the semiconductor substrate  300  having the gate electrode  304 , and etched back to form a spacer  306  on each sidewall of the gate electrode  304 , thereby resulting in a gate electrode assembly G 3 . Following this, a source region  308   a  and a drain region  308   b  are formed in the semiconductor substrate  100  by ion implantation. Alternatively, after the formation of the gate electrode  304  and before the formation of the spacer  306 , the semiconductor substrate  300  having the gate electrode  304  may be lightly doped with impurities. A first ILD film  310  is formed over the semiconductor substrate  300  having the gate electrode assembly G 3 . A portion of the first ILD film is etched using CF 4  and O 2  gases to form openings through which the source region  308   a  and the drain region  308   b  are exposed.  
         [0029]    A conductive material is deposited over the first ILD film  310  having the openings by chemical vapor deposition or physical vapor deposition to form a diffusion barrier layer  314  with a thickness of 100-1000 Å. The diffusion barrier layer  314  may be formed of a tantalum nitride layer, a titanium nitride layer or a titanium/ titanium nitride layer. A first conductive layer  316  is formed along the diffusion barrier layer  314  by chemical vapor deposition or physical vapor deposition, such that a recession  317  remains in the opening, as shown in FIG. 3. Preferably, the diameter C of the recession  317  is ¼-½ of the diameter R of the opening. The first conductive layer  316  is formed of metal, preferably, tungsten, aluminum or copper.  
         [0030]    Referring to FIG. 4, the semiconductor substrate  300  with the first conductive layer  316  is subjected to mechanical and chemical polishing until the surface of the ILD film  310  is exposed, so that the lower plugs  316   a  with the recessions  317  are formed. If an etching back technique is applied, instead of the mechanical and chemical polishing technique, to expose the surface of the ILD film  310 , the diffusion barrier layer  314  and the first conductive layer  316  formed on the bottom of the opening are also removed during the etching back process, so that a conductive material such as metal filling the recessions  317  may migrate into the semiconductor substrate  300 , thereby causing sparking in the junction near the source region  308   a  and the drain region  308   b . As a result, there arises a problem of leakage current.  
         [0031]    Referring to FIG. 5, a second ILD film  318  is formed over the first ILD film  310  having the lower plugs  316   a , and a portion of the second ILD film  318  is removed by photolithography, thereby resulting in grooves  319   a  and  319   b  in the second ILD film  318 . Following this, an adhesiveness enhancing layer (not shown) is deposited along the second ILD film  318  having the grooves by low-pressure chemical vapor deposition or ionization physical deposition to have a thickness of 100-700 Å. The adhesiveness enhancing layer acts to improve the adhesiveness between the second ILD film  318  and a second conductive layer (not shown) to be formed in a subsequent step. The adhesiveness enhancing layer may be formed of a titanium nitride layer, a tantalum nitride layer or a titanium/titanium nitride layer. When the ionization physical deposition method is applied to form the adhesive enhancement layer, metal such as titanium or tantalum is ionized by plasma, and the resultant metal ions adhere to a wafer installed in an etching apparatus by electric field generated with application of alternating current (AC).  
         [0032]    Next, a second conductive layer having a thickness of 3000-6000 Å is deposited over the adhesiveness enhancing layer. The second conductive layer, which fills the grooves of the second ILD  318  and the recessions  317  of the lower plugs  316   a , is formed of metal such as tungsten, copper, aluminum, refractory metal or refractory metal silicide. When tungsten is selected as the material of the second conductive layer, SiH 4  and W 6  gases are used as reaction source gases and the temperature is adjusted in the range of 400-450° C. When aluminum is selected as the material of the second conductive layer, aluminum containing 0.1-0.5% by weight silicon is deposited and heated at a temperature of 450° C. or more. As a result, the recessions  317  and the grooves  319   a  and  319   b  of the second ILD film  318  are filled with tungsten or aluminum.  
         [0033]    Following this, the second conductive layer and the adhesiveness enhancing layer are removed by dry etching or mechanical and chemical polishing until the top of the second ILD  318  is exposed, thereby resulting in an adhesiveness layer  320 , a landing pad  322   a  and a lower interconnection  322   b . The landing pad  322   a  and the lower interconnection  322   b  include projections  321   a  and  321   b  corresponding to the recessions of the lower plugs  316   a.    
         [0034]    As shown in FIG. 6, a third ILD film  324  is deposited over the second ILD film  318  having the adhesiveness layer  320 , the landing pad  322   a  and the lower interconnection  322   b . A portion of the third ILD film  320  is etched to form openings to be an upper metal interconnection. A conductive material such as metal is deposited over the third ILD film  324 , filling the openings, and patterned to form an upper metal interconnection  328 .  
         [0035]    Another embodiment of a method for manufacturing a semiconductor device according to the present invention is illustrated in FIGS. 7 and 8. A gate electrode assembly G 4 , a source region  408   a,  a drain region  408   b,  a diffusion barrier layer  414   a,  a lower plug  416   a,  a landing pad  422   a,  a lower interconnection  422   b,  first, second and third ILD films  410 ,  418  and  424 , and an upper interconnection  428  are formed through the same processes as those illustrated with reference to FIGS. 3 through 6. Although the same deposition technique is applied to form both the adhesive layers  320  and  420 , if the openings of the first ILD film  410 , in which the lower plugs  416   a  are to be formed, are designed to be larger than those for the lower plugs  316   a  shown in FIGS. 5 and 6, the adhesive layer  420  can be formed over the recessions of the lower plugs  416 , unlike the adhesive layer  320  coated on a portion of the recessions of the lower plugs  316   a . In this way, the deposition conditions applied to form the adhesive layer  320  shown in FIGS. 5 and 6 can be varied such that the adhesive layer  420  can be formed over the recessions of the lower plugs  416 .  
         [0036]    As previously mentioned in the above two embodiments, the lower plugs  316   a  and  416   a  have recessions, and the landing pads  322  and  422 , or the lower interconnections  322   b  and  422   b  have projections fitted into the recessions of the lower plugs  316  and  416   a,  so that the contact area between the lower plugs  316   a  and  416   a,  and the landing pads  322   a  and  422   a  or the lower interconnections  322   b  and  422   b  increases, thereby strengthening the combination of the landing pads  322  and  422  or the lower interconnections  322   b  and  422   b,  and the lower plugs  316   a  and  416   a . For this reason, after a conductive material filling the openings of the second ILD films  318  and  418 , and the recessions of the lower plugs  316   a  and  416   a  is polished or etched back to form the landing pads  322  and  422  or the lower interconnections  322   b  and  422   b,  or even when the semiconductor substrate having the landing pads  322  and  422  or the lower interconnections  322   b  and  422   b  are subjected to subsequent integration processes, such as washing and drying processes, detachment of the landing pads  322  and  422 , or the lower interconnections  322   b  and  422   b  from the lower plugs  316   a  and  416   a,  or the semiconductor substrates  300  and  400  can be suppressed.  
         [0037]    Although the lower plugs  316   a  and  416  have recessions, the recessions are filled with the landing pads  322  and  422 , or the lower interconnections  322   b  and  422   b,  so that there is no increase in contact resistance between the lower plugs  316   a  and  416   b , and the landing pads  322  and  422  or the lower interconnections  322   b  and  422   b.    
         [0038]    In addition, the openings formed in the first ILD films  310  and  410  are completely filled with conductive material through two stages, i.e., by the lower plugs  316   a  and  416   a,  and then by the landing pads  322  and  422 , or the lower interconnections  322   b  and  422   b,  so that occurrence of voids in filling the openings of the first ILD films  310  and  410  can be prevented.  
         [0039]    While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made to the described embodiments without departing from the spirit and scope of the invention as defined by the appended claims.

Technology Category: 5