Patent Document

BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present invention relates to noise reduction in digital systems, and more specifically, to noise reduction by asserting clock signals at different times. 
   2. Related Art 
   In the normal operation of a conventional digital system, simultaneous clocking of registers of the conventional digital system can cause signal noise. Therefore, there is a need for a digital system (and a method for operating the same) in which the noise due to the simultaneous clocking of data registers can be reduced compared to prior art. 
   SUMMARY OF THE INVENTION 
   The present invention provides a digital system, comprising (a) a first logic circuit and a second logic circuit; (b) a first register electrically coupled to the first logic circuit; (c) a second register electrically coupled to the first logic circuit and the second logic circuit; (d) a third register electrically coupled to the second logic circuit; (e) a clock generator circuit electrically coupled to the first, second, and third registers; and (f) a controller circuit electrically coupled to the clock generator circuit, wherein the first logic circuit is capable of obtaining first data from the first register, processing the obtained first data into second data, and sending the second data to the second register, wherein the second logic circuit is capable of obtaining the second data from the second register, processing the obtained second data into third data, and sending the third data to the third register, wherein the clock generator circuit is capable of asserting a first register clock signal at a first time point to the first register resulting in the first logic circuit obtaining the first data from the first register, wherein the clock generator circuit is further capable of asserting a second register clock signal at a second time point to the second register resulting in the second logic circuit obtaining the second data from the second register, wherein the clock generator circuit is further capable of asserting a third register clock signal at a third time point to the third register, wherein the controller circuit is capable of (i) determining a first processing time for the first logic circuit to obtain the first data, process the obtained first data into the second data, and send the second data to the second register, (ii) determining a second processing time for the second logic circuit to obtain the second data, process the obtained second data into the third data, and send the third data to the third register, (iii) determining a fourth time point after the first time point such that a first time duration between the first time point and the fourth time point is at least the first processing time, (iv) determining a fifth time point before the third time point and after the fourth time point such that a second time duration between the fifth time point and the third time point is at least the second processing time, wherein the fourth time point and the fifth time point define a first clock window, and (v) controlling the clock generator circuit to assert the second register clock signal such that the second time point is within the first clock window. 
   The present invention provides a digital system operation method, which comprises providing a digital system which includes (a) a first logic circuit and a second logic circuit, (b) a first register electrically coupled to the first logic circuit, (c) a second register electrically coupled to the first logic circuit and the second logic circuit, (d) a third register electrically coupled to the second logic circuit, (e) a clock generator circuit electrically coupled to the first, second, and third registers, and (f) a controller circuit electrically coupled to the clock generator circuit; using the clock generator circuit to assert a first register clock signal at a first time point to the first register; using the clock generator circuit further to assert a second register clock signal at a second time point to the second register; using the clock generator circuit to further assert a third register clock signal at a third time point to the third register; in response to the clock generator circuit asserting the first register clock signal at the first time point to the first register, using the first logic circuit to obtain first data from the first register, process the obtained first data into second data, and send the second data to the second register; in response to the clock generator circuit further asserting the second register clock signal at the second time point to the second register, using the second logic circuit to obtain the second data from the second register, process the obtained second data into third data, and send the third data to the third register; using the controller circuit to (i) determine a first processing time for the first logic circuit to obtain the first data, process the obtained first data into the second data, and send the second data to the second register; (ii) determine a second processing time for the second logic circuit to obtain the second data, process the obtained second data into the third data, and send the third data to the third register; (iii) determine a fourth time point after the first time point such that a first time duration between the first time point and the fourth time point is at least the first processing time; (iv) determine a fifth time point before the third time point and after the fourth time point such that a second time duration between the fifth time point and the third time point is at least the second processing time; wherein the fourth time point and the fifth time point define a first clock window, and (vi) control the clock generator circuit to assert the second register clock signal such that the second time point is within the first clock window. 
   The present invention provides a digital system, comprising (a) a first logic circuit and a second logic circuit; (b) a first register electrically coupled to the first logic circuit; (c) a second register electrically coupled to the first logic circuit and the second logic circuit; (d) a third register electrically coupled to the second logic circuit; (e) a clock generator circuit electrically coupled to the first, second, and third registers; and (f) a controller circuit electrically coupled to the clock generator circuit, wherein the first logic circuit comprises a fast logic circuit and a slow logic circuit, wherein the fast logic circuit and the slow logic circuit are capable of performing a same function, wherein the first logic circuit is capable of obtaining first data from the first register, processing the obtained first data into second data, and sending the second data to the second register, wherein the second logic circuit is capable of obtaining the second data from the second register, processing the obtained second data into third data, and sending the third data to the third register, wherein the clock generator circuit is capable of asserting a first register clock signal at a first time point to the first register resulting in the first logic circuit obtaining the first data from the first register, wherein the clock generator circuit is further capable of asserting a second register clock signal at a second time point to the second register resulting in the second logic circuit obtaining the second data from the second register, wherein the clock generator circuit is further capable of asserting a third register clock signal at a third time point to the third register, wherein a first plurality of registers receive as input the second register clock signal, wherein a second plurality of registers receive as input the third register clock signal, wherein the controller circuit is capable of (i) determining a first processing time for the first logic circuit to obtain the first data, process the obtained first data into the second data, and send the second data to the second register, (ii) determining a second processing time for the second logic circuit to obtain the second data, process the obtained second data into the third data, and send the third data to the third register, (iii) determining a fourth time point after the first time point such that a first time duration between the first time point and the fourth time point is at least the first processing time, (iv) determining a fifth time point before the third time point and after the fourth time point such that a second time duration between the fifth time point and the third time point is at least the second processing time, wherein the fourth time point and the fifth time point define a first clock window, and (v) controlling the clock generator circuit to assert the second register clock signal such that the second time point is within the first clock window. 
   The present invention provides a novel digital system (and a method for operating the same) in which the noise due to the simultaneous clocking of data registers can be reduced compared to prior art. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a digital system, in accordance with embodiments of the present invention. 
       FIG. 2  shows a detail configuration of a logic circuit of the digital system of  FIG. 1 , in accordance with embodiments of the present invention. 
       FIG. 3  shows a detail configuration of a clock generator circuit of the digital system of  FIG. 1 , in accordance with embodiments of the present invention. 
       FIG. 4  shows a detail configuration of another embodiment of the logic circuit of the digital system of  FIG. 1 , in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1  shows a digital system  100 , in accordance with embodiments of the present invention. More specifically, in one embodiment, the digital system  100  comprises multiple register banks (e.g., register banks  110 ,  120 , and  130 ). Although the digital system  100  has many register banks, only the three register banks  110 ,  120 , and  130  of the digital system  100  are shown in  FIG. 1 . Illustratively, the register bank  110  comprises multiple registers (e.g., registers  111 ,  112 ,  113 ,  114 ,  115 , and  116 ). It should be noted that the register bank  110  comprises many registers but only the six registers  111  through  116  are shown in  FIG. 1 . Similarly, the register banks  120  and  130  comprise multiple registers (e.g., registers  121 ,  122  of the register bank  120  and registers  131 ,  132  of the register bank  130 ). In one embodiment, similarly, the other register banks in the digital system  100  comprise multiple registers. In one embodiment, the digital system  100  further comprises multiple logic circuits electrically coupled between the register banks  110  and  120  (e.g., logic circuits  142 ,  144 , and  146 ). In one embodiment, the digital system  100  further comprises multiple logic circuits electrically coupled between the register banks  120  and  130  (e.g., logic circuits  152 ,  154 , and  156 ). In one embodiment, the digital system  100  further comprises a clock generator circuit  170  electrically coupled to the register banks  110 ,  120  and  130 . In one embodiment, each register of each register bank of the digital system  100  receives one clock signal from the clock generator circuit  170 . More specifically, in one embodiment, for illustration, the registers  121 ,  122 ,  131 , and  132  receive clock signals CLK 121 , CLK 122 , CLK 131 , and CLK 132 , respectively, from the clock generator circuit  170 . Although the clock generator circuit  170  generates many clock signals, only the four clock signals CLK 121 , CLK 122 , CLK 131 , and CLK 132  are shown in  FIG. 1 . In one embodiment, the digital system  100  further comprises a controller circuit  160  electrically coupled to the clock generator circuit  170 . 
     FIG. 2  shows a detail configuration of the logic circuit  142  of  FIG. 1 , in accordance with embodiments of the present invention. More specifically, in one embodiment, the logic circuit  142  comprises inverters  205 ,  240 ,  245 , and  250 . In one embodiment, the logic circuit  142  further comprises NAND gates  210 ,  215 ,  230 ,  235  and OR gates  220  and  225 . In one embodiment, the inverters, NAND gates, and OR gates of the logic circuit  142  are electrically coupled together as shown. As can be seen in  FIG. 2 , the logic circuit  142  has six inputs IN 1 , IN 2 , IN 3 , IN 4 , IN  5 , IN  6  and two outputs OUT 1  and OUT 2 . In one embodiment, the six input signals IN 1 , IN 2 , IN 3 , IN 4 , IN  5 , and IN  6  come from the six registers  111  through  116  of the register bank  110  of  FIG. 1 , respectively, and the two output signals OUT 1  and OUT 2  go to the two registers  121  and  122  of the register bank  120  of  FIG. 1 , respectively. In one embodiment, similar to the logic circuit  142 , each of the other logic circuits of the digital system  100  of  FIG. 1  can comprise logic elements (e.g., inverters, NAND gates, and OR gates, etc.) which are electrically coupled together and can have multiple inputs and multiple outputs. 
     FIG. 3  shows a detail configuration of the clock generator circuit  170  of  FIG. 1 , in accordance with embodiments of the present invention. More specifically, in one embodiment, the clock generator circuit  170  comprises multiple delay circuits (e.g., delay circuits  310 ,  320 , and  330 ) electrically coupled together in a chain. It should be noted that the clock generator circuit  170  may have many delay circuits but only the three delay circuits  310 ,  320 , and  330  are shown in  FIG. 3 . In one embodiment, the delay circuit  310  receives a master clock signal and generates a clock signal CLK 1  to the delay circuit  320 . In one embodiment, the delay circuit  320  receives the clock signal CLK 1  from the delay circuit  310  and generates a clock signal CLK 2  to the delay circuits  330 . Similarly, the delay circuit  330  receives the clock signal CLK 2  from the delay circuit  320  and generates a clock signal CLK 3 . In one embodiment, similarly, the other delay circuits in the chain of the clock generator circuit  170  are coupled in a similar manner. In one embodiment, the clock generator circuit  170  further comprises multiple multiplexer (MUX) circuits (e.g., MUX circuits  341  and  342 ). Although the clock generator circuit  170  may have many MUX circuits, only the MUX circuits  341  and  342  are shown in  FIG. 3  for illustration. The way the other MUX circuits are coupled to the delay circuits of the clock generator circuit  170  will be described later. In one embodiment, the MUX circuits  341  and  342  receive the three clock signals: master clock, CLK 1 , and CLK 2 . In one embodiment, the MUX circuits  341  and  342  also receive control signals  161  and  162 , respectively, from the controller circuit  160 . In one embodiment, the MUX circuits  341  and  342  also generate clock signals CLK 121  and CLK 122  to the registers  121  and  122  of the register bank  120  of  FIG. 1 , respectively. It should be noted that the clock signal CLK 121  comes from one of the master clock, clock signal CLK 1 , and clock signal CLK 2  depending on the control signal  161 . Similarly, the clock signal CLK 122  comes from one of the master clock, clock signal CLK 1 , and clock signal CLK 2  depending on the control signal  162 . In one embodiment, the remaining MUX circuits of clock generator circuit  170  will generate multiple clock signals one to one to the other registers of  FIG. 1 . 
   In one embodiment, with reference to  FIGS. 1 ,  2 , and  3 , the operation of the digital system  100  is as follows. In one embodiment, to simplify the description of the present invention, assume that one clock cycle of the digital system  100  is one hour. In one embodiment, assume further that in a first clock cycle starting at 8:00 AM, the controller circuit  160  controls the clock generator circuit  170  such that all clock signals going to the registers in  FIG. 1  are asserted at a same time (e.g., at 8:00 AM). In response, each of the logic circuits in the digital system  100  obtains data from registers of the register bank on the left, processes the obtained data, and sends the processed data to registers of the register bank on the right. More specifically, for instance, at 8:00 AM the logic circuit  142  obtains data from registers  111  through  116  of the register bank  110 , processes the obtained data, and sends the processed data to the registers  121  and  122  of the register bank  120 . Assume further that in a second clock cycle starting around 9:00 AM, the logic circuit  152  will obtain the data from the register  121 , process the obtained data, and send the processed data to the register  131 . Assume further that in the second clock cycle, the logic circuit  154  will obtain the data from the register  122 , process the obtained data, and send the processed data to the register  132 . Assume further that in a third clock cycle, the clock signals CLK 131  and CLK 132  will be asserted at 10:00 AM. In one embodiment, the processed data from the logic circuits  152  and  154  will be ready in the registers  131  and  132 , respectively, before the clock signals CLK 131  and CLK 132  are asserted at 10:00 AM. One recognizes that each group of registers is clocked every cycle. For the purpose of this example, data proprogating thru the pipeline is being illustrated. 
   Assume that the controller circuit  160  determines that the logic circuit  142  takes only 40 minutes to have the processed data ready in the registers  121  and  122 . In other words, a first processing time of the logic circuit  142  is 40 minutes. This means that the processed data is ready in the registers  121  and  122  at 8:40 AM. Assume further that the controller circuit  160  determines that the logic circuit  152  and  154  take 45 minutes and 50 minutes to have processed data ready in the registers  131  and  132  of register bank  130 , respectively. In other words, a second processing time and a third processing time of the logic circuits  152  and  154  are 45 and 50 minutes, respectively. As a result, the controller circuit  160  determines that a first clock window for the clock signal CLK 121  is from 8:40 AM to 9:15 AM (the first clock window is a window in which the clock signal CLK 121  can be asserted such that the register  121  has processed data from the logic circuit  142  and the register  131  has processed data before the clock signal CLK 131  is asserted at 10:00 AM). Similarly, the controller circuit  160  determines that a second clock window for the clock signal CLK 122  is from 8:40 AM to 9:10 AM (the second clock window is a window in which the clock signal CLK 122  can be asserted such that the register  122  has processed data from the logic circuit  142  and the register  132  has processed data before the clock signal CLK 132  is asserted at 10:00 AM). Therefore, in one embodiment, the controller circuit  160  controls the clock generator circuit  170  to assert the clock signals CLK 121  and CLK 122  in the first and second clock windows, respectively. This ensures that the processed data from the logic circuits  152  and  154  will be ready in the registers  131  and  132 , respectively, before the clock signals CLK 131  and CLK 132  are asserted at 10:00 AM. 
   In one embodiment, the controller circuit  160  determines that the clock signal CLK 121  will be asserted at 9:00 AM (which is within the first clock window) and the clock signal CLK 122  will be asserted at 9:05 AM (which is within the second clock window). Assume that the master clock is asserted at 8:00 AM, 9:00 AM, 10:00 AM, etc. Assume further that each delay circuit (e.g., delay circuit  310 ,  320 , and  330 ) delays 5 minutes. As a result, the clock signal CLK 1  is asserted at 8:05 AM, 9:05 AM, 10:05 AM, etc; the clock signal CLK 2  is asserted at 8:10 AM, 9:10 AM, 10:10 AM, etc; and the clock signal CLK 3  is asserted at 8:15 AM, 9:15 AM, 10:15 AM, etc. 
   In one embodiment, for instance, in order to assert the clock signal CLK 121  at 9:00 AM, the controller circuit  160  controls the clock generator  170  to generate the control signal  161  so as to cause the MUX circuit  341  to pass the master clock through it as the clock signal CLK 121  to the register  131 . As a result, the clock signal CLK 121  will be asserted at 9:00 AM which is in the first clock window. This ensures that the processed data from the logic circuit  152  will be ready in the register  131  of the register bank  130  before the clock signal CLK 131  is asserted at 10:00 AM. 
   In one embodiment, similarly, in order to assert the clock signal CLK 122  at 9:05 AM, the controller circuit  160  controls the clock generator  170  to generate a control signal  162  so as to cause the MUX circuit  342  to pass the clock signal CLK 1  through it as the clock signal CLK 122  to the register  132 . As a result, the clock signal CLK 122  will be asserted at 9:05 AM which is in the second clock window. This ensures that the processed data from the logic circuit  154  will be ready in the register  132  of the register bank  130  before the clock signal CLK 132  is asserted at 10:00 AM. 
   In summary, the clock signals CLK 121  and CLK 122  are asserted at different times for the second clock cycle (9:00 AM and 9:05 AM, respectively). As a result, noise is reduced. 
   In one embodiment, the controller circuit  160  of  FIG. 1  is a state machine. In an alternative embodiment, the controller circuit  160  of  FIG. 1  contains a microcode that helps the controller circuit  160  perform its functions described above. 
   In the embodiment described above, it is assumed that the process data is ready in the registers  121  and  122  at the same time. In an alternative embodiment, it takes different processing times to have processed data ready in the registers  121  and  122 . 
   In the embodiment described above, with reference to  FIG. 3 , each of the MUX circuit  341  and  342  receive the three clock signals: master clock, CLK 1 , and CLK 2 . Alternatively, each of the MUX circuit  341  and  342  can receive N clock signals, N being positive integer. For example, the MUX circuit  341  can receive clock signals CLK 1 , CLK 2 , CLK 3 , and CLK 4 ; and the MUX circuit  342  can receive clock signals CLK 1 , CLK 3 , CLK 6 , and CLK 11 . As a result, the clock signal CLK 121  can be asserted at either 9:05 AM, 9:10 AM, 9:15 AM or 9:20 AM for the second clock cycle around the start of the second clock cycle. Similarly, the clock signal CLK 122  can be asserted at either 9:05 AM, 9:15 AM, 9:30 AM or 9:55 AM for the second clock cycle around the start of the second clock cycle. 
   In the embodiments described above, each register of digital system  100  of  FIG. 1  receives a clock signal from the clock generator circuit  170 . In an alternative embodiment, the registers of one register bank of the digital system  100  are divided into group, wherein each group receives one clock signal from the clock generator circuit  170 . For example, the registers  111  through  116  can be grouped together, and receive the same clock signal from the clock generator circuit  170 . 
     FIG. 4  shows a detail configuration of another embodiment of the logic circuit  142  of  FIG. 1 , in accordance with embodiments of the present invention. More specifically, in one embodiment, the logic circuit  142  comprises a fast logic circuit  142   a , a slow logic circuit  142   b , a MUX circuit  142   c , and a MUX circuit  142   d , which are electrically coupled together as shown. It should be noted that the MUX circuits  142   c  and  142   d  receive control signals (not shown) from the controller circuit  160 . In one embodiment, the fast logic circuit  142   a  and the slow logic circuit  142   b  perform the same function, but the fast logic circuit  142   a  is faster than the slow logic circuit  142   b  in performing the function. However, the fast logic circuit  142   a  consumes more energy than the slow logic circuit  142   b . In one embodiment, the other logic circuits of the digital system  100  have similar structure as the logic circuit  142  of  FIG. 4 . In one embodiment, in each particular clock cycle, one of the fast logic circuit  142   a  and the slow logic circuit  142   b  is selected by the controller circuit  160  to obtain data from the registers  111  through  116  of register bank  110  via the MUX circuit  142   c , processes the obtained data, and sends the processed data to the registers  121  and  122  of register bank  120  via the MUX circuit  142   d . The non-selected circuit of the fast logic circuit  142   a  and the slow logic circuit  142   b  does not operate (does not consume energy). 
   In the embodiments described above, with reference to  FIGS. 1 ,  3 , and  4 , in the first clock cycle, the controller circuit  160  can select the fast logic circuit  142   a  to operate (the slow logic circuit  142   b  does not operate). As a result, the first and the second clock window are wider than the case in which the controller circuit  160  selects the slow logic circuit  142   b  to operate. 
   In summary, in operation processing of the digital system  100  of  FIG. 1 , the times at which the clock signals CLK 121  and CLK 122  are asserted can be spread out. As a result, noise is reduced. 
   In the embodiments described above, for simplicity, it is assumed that the controller circuit  160  causes the clock generator circuit  170  to simultaneously assert the clock signals to all the registers of the digital system  100  at 8:00 AM and again at 10:00 AM. Only at around 9:00 AM, the clock signals to the registers are asserted at different times. More specifically, the clock signal CLK 121  to the register  121  is asserted at 9:00 AM and the clock signal CLK 122  to the register  122  is asserted at 9:05 AM. In an alternative embodiment, the clock signals to the registers of the digital system  100  are asserted at different times around any clock cycle boundary including around 8:00 AM and 10:00 AM. 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.

Technology Category: 3