Patent Document

BACKGROUND OF THE INVENTION 
       [0001]    This relates to N-well or P-well strap structures for use in integrated circuits. 
         [0002]    N-well or P-well strap structures are typically used in integrated circuits to tie a source line to a well region so as to assure that the voltage in the well region is the same as the voltage at the source line. 
         [0003]      FIGS. 1 and 2  depict a top view and a cross-section along lines  2 - 2  of  FIG. 1  of a typical integrated circuit structure  100  that includes an active device and a well strap formed in a well in a semiconductor substrate  105  It will be understood that this structure may be replicated multiple times in the integrated circuit. Structure  100  includes source and drain regions  110 ,  120  formed in a well  130  with a polysilicon gate finger  140  formed on a dielectric layer (not shown) on the surface of well  130 . These elements will be recognized as forming a MOS transistor; but it is to be understood that the MOS transistor is only illustrative of any active device. Following industry practice, the length L of gate  140  is its shorter dimension. 
         [0004]    Structure  100  further includes diffusion region  160  that makes ohmic contact with well  130  and ohmic contacts (or taps)  115  to source region  110 , ohmic contacts  125  to drain region  120 , and ohmic contacts  165  to diffusion region  160 . The diffusion region  160  and its contacts or taps  165  constitute the well strap. A shallow trench isolation (STI) region  150  surrounds the active device and well strap. 
         [0005]    Illustratively, the transistor is a PMOS transistor, source and drain regions are P-type, well  130  is an N-type well, and diffusion region  160  is N-type. Alternatively, the transistor is an NMOS transistor, source and drain regions  110 ,  120  are N-type, and well  130  and diffusion region  160  are P-type. 
         [0006]    In certain prior art integrated circuits, the N-well or P-well strap is placed so that it is directly abutting an active device such as the MOS transistor as shown in  FIGS. 1 and 2 . Further details concerning such an implementation of a N-well strap may be found in U.S. Pat. No. 7,586,147 B2 for “Butted Source Contact and Well Strap,” which is incorporated herein by reference. In alternative structures, the well strap may form a ring around the active device or group of active devices. 
         [0007]    In certain other prior art integrated circuits, dummy polysilicon is placed next to the device gates so as to control uniformity of critical dimensions. In this case, the well strap is spaced apart from the active device.  FIG. 3  is a top view of such a prior art integrated circuit structure  300  including an active device and a well strap. Illustratively, structure  300  includes source and drain regions  310 ,  320  formed in a well  330  with a polysilicon gate finger  340  formed on a dielectric layer (not shown) on the surface of well  330 . These elements will be recognized as forming a MOS transistor; but it is to be understood that the MOS transistor is only illustrative of any active device. A substrate (not shown) similar to substrate  105  of  FIG. 2  underlies well  330 . 
         [0008]    Structure  300  further includes diffusion region  360  that makes ohmic contact with well  330  and ohmic contacts (or taps)  315  to source region  310 , ohmic contacts  325  to drain region  320 , and ohmic contacts  365  to diffusion region  360 . The diffusion region  360  and its contacts or taps  365  constitute the well strap. A STI region  350  surrounds the active device and the well strap. Again, the transistor can be a PMOS transistor with P-type source and drain regions  310 ,  320  and N-type well  330  and diffusion region  360 ; or the transistor can be a NMOS transistor with N-type source and drain regions  310 ,  320  and P-type well  330  and diffusion region  360 . 
         [0009]    Structure  300  further comprises dummy polysilicon gate fingers  371 ,  372  located on opposite sides of the active device above portions of the STI region  350 . As a result, the well strap is separated from the active device by at least one length of the dummy polysilicon finger. 
         [0010]    In certain other prior art integrated circuits, double dummy polysilicon is placed next to active devices.  FIG. 4  is a top view of such a prior art integrated circuit structure  400  including an active device and a well strap. Illustratively, structure  400  includes on the left-hand side source and drain regions  410 ,  420  formed in a well  430  with a polysilicon gate finger  440  formed on a dielectric layer (not shown) on the surface of well  430 . These elements will be recognized as forming a first MOS transistor; but it will be understood that the MOS transistor is only illustrative of any active device. A second MOS transistor is formed on the right-hand side of  FIG. 4  and includes the same elements bearing the same numbers followed by the suffix A. Again, a substrate (not shown) similar to substrate  105  of  FIG. 2  underlies well  430 . 
         [0011]    Structure  400  further includes diffusion region  460  that makes ohmic contact with well  430  and ohmic contacts (or taps)  415  to source region  410 , ohmic contacts  425  to drain region  420 , and ohmic contacts  465  to diffusion region  460 . The diffusion region  460  and its contacts or taps  465  constitute the well strap. A STI region  450  surrounds the active devices and the well strap. Again, the transistor can be a PMOS transistor with P-type source and drain regions  410 ,  420  and N-type well  430  and diffusion region  460 ; or the transistor can be a NMOS transistor with N-type source and drain regions  410 ,  420  and P-type well  430  and diffusion region  460 . 
         [0012]    Structure  400  further comprises dummy polysilicon gate fingers  471 ,  472 ,  473 ,  474  with the first two fingers  471 ,  472  located above portions of STI region  450  between the well strap and the first transistor and the second two fingers  473 ,  474  being located above other portions of STI regions  450  between the well strap and the second transistor. As a result, the well strap is separated from the active device by at least two lengths of the dummy polysilicon fingers. 
       SUMMARY OF THE INVENTION 
       [0013]    The use of increasing numbers of dummy polysilicon gate fingers to separate the active device(s) from the well strap takes up considerable amount of space on the semiconductor substrate. The present invention is improved N-well or P-well strap structures with lower space requirements. In illustrative embodiments, reduced space requirements are achieved by forming the strap on both sides of one or more floating polysilicon gate fingers. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    These and other objects and advantages of the present invention will be apparent to those of ordinary skill in the art in view of the following Detailed Description in which: 
           [0015]      FIGS. 1 and 2  are a top view and a cross-sectional view of a first well strap structure of the prior art; 
           [0016]      FIG. 3  is a top view of a second prior art well strap structure; 
           [0017]      FIG. 4  is a top view of a third prior art well strap structure; 
           [0018]      FIGS. 5 and 6  are a top view and a cross-sectional view of a first illustrative embodiment of the invention; 
           [0019]      FIG. 7  is a top view of a second illustrative embodiment of the invention; 
           [0020]      FIG. 8  is a top view of a third illustrative embodiment of the invention; and 
           [0021]      FIG. 9  is a top view of a fourth illustrative embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]      FIGS. 5 and 6  are a top view and a cross-sectional view of a first illustrative embodiment of the invention. Structure  500  includes source and drain regions  510 ,  520  formed in a well  530  with a polysilicon gate finger  540  formed on a dielectric layer (not shown) on the surface of well  530 . These elements will be recognized as forming a MOS transistor; but it will be understood that the MOS transistor is only illustrative of any active device that may be used in the practice of the invention. A second MOS transistor is formed on the right-hand side of  FIG. 5  and includes the same elements bearing the same numbers followed by the suffix A. As shown in  FIG. 6 , a semiconductor substrate  605  underlies well  530 . 
         [0023]    Structure  500  further includes diffusion regions  560 ,  562  that make ohmic contact with well  530 , a floating polysilicon gate finger  580  between diffusion regions  560 ,  562 , and ohmic contacts (or taps)  515  to source region  510 , ohmic contacts  525  to drain region  520 , and ohmic contacts  565 ,  567  to diffusion regions  560 ,  562 . The diffusion regions  560 ,  562 , and contacts or taps  565 ,  567  constitute the well strap. A STI region  550  surrounds the active devices and the well strap. As shown in  FIG. 5 , taps  565  and taps  567  are on opposite sides of floating gate finger  580 . While two taps  565  and two taps  567  are shown, a single tap  565  or  567  or more than two taps  565  or  567  may be used. 
         [0024]    Structure  500  further comprises dummy polysilicon gate fingers  575 ,  576  located on opposite sides of diffusion regions  560 ,  562  and above portions of STI region  550 . As a result, the well strap is separated from the active device by only one length of the dummy polysilicon gate finger, thereby reducing the distance between the active device and the diffusion region  560  compared with the distance between the active device and the diffusion region  460  in the prior art structure of  FIG. 4 . 
         [0025]    To form structure  500 , dopants of a first conductivity-type, illustratively N-type, are first implanted in a substrate  602  of a second conductivity type, illustratively P-type, to form an N-type well  530 . STI region  550  is then formed in well  530 . An insulating layer is then formed on the surface of the well; and polysilicon gate fingers  540 ,  540 A,  575 ,  576 ,  580  are formed on the insulating layer. Lightly doped drain regions are then formed in the well on each side of gates  540 ,  540 A; and sidewalls  542 ,  542 A are then formed on the sides of gates  540 ,  540 A. The gates and sidewalls are then used as masks to control the implantation of dopants during formation of the source and drain regions and the diffusion regions. Illustratively P-type dopants are implanted on both sides of gates  540 ,  540 A and sidewalls  542 ,  542 A to form source regions  510 ,  510 A and drain regions  520 ,  520 A of the PMOS transistors; and N-type dopants are implanted on both sides of gate finger  580  to form diffusion regions  560 ,  562 . Because the gates and sidewalls shield the well regions directly underneath them, these well regions are not doped during the implantation process with the result that separate source and drain regions and separate diffusion regions  560 ,  562  are formed. Holes are then made in the insulating layer and contacts are formed to the source and drain regions  510 ,  510 A,  520 ,  520 A and the diffusion regions  560 ,  562 . Advantageously, the N-type diffusion regions  560 ,  562  may be formed at the same time as the same process is used to form other N-type regions, such as source and drain regions, elsewhere on the integrated circuit; and similarly, the P-type process used to form the P-type source and drain regions  510 ,  510 A,  520 ,  520 A may be used to form P-type diffusion regions elsewhere on the integrated circuit. 
         [0026]      FIG. 7  is a top view of a second illustrative embodiment of the invention. Structure  700  includes source and drain regions  710 ,  720  formed in a well (not shown) with a polysilicon gate finger  740  formed on a dielectric layer (not shown) on the surface of the well. These elements will be recognized as forming a MOS transistor; but it will be understood that the MOS transistor is only illustrative of any active device that may be used in the practice of the invention. A second MOS transistor is formed on the right-hand side of  FIG. 7  and includes the same elements bearing the same numbers followed by the suffix A. The well is formed in a semiconductor substrate (not shown); and the cross-section of the active device, well and substrate of the embodiment of  FIG. 7  is similar to the cross-section of the active device, well  630  and substrate  605  of  FIG. 6 . 
         [0027]    Structure  700  further includes diffusion regions  760 ,  762 ,  764  that make ohmic contact with well  730 , at least two floating polysilicon gate fingers  782 ,  784  between diffusion regions  760 ,  762  and ohmic contacts (or taps)  715  to source region  710 , ohmic contacts  725  to drain region  720 , and ohmic contacts  765 ,  767  to diffusion regions  760 ,  762 . No contacts are made to diffusion region  764  with the result that region  764  is left floating. The diffusion regions  760 ,  762 , and contacts or taps  765 ,  767  constitute the well strap. A STI region  750  surrounds the active devices and the well strap. As shown in  FIG. 7 , taps  765  and taps  767  are on opposite sides of floating gate fingers  782 ,  784 . 
         [0028]    Structure  700  further comprises dummy polysilicon gate fingers  775 ,  777  located on opposite sides of the active device and above portions of the STI region  750 . As a result, the well strap is separated from the active device by only one length of the dummy polysilicon gate finger, thereby reducing the distance between the active device and the diffusion region compared to prior art structures. 
         [0029]    The process for forming structure  700  and the resulting structural cross-section are substantially the same as those of structure  500  except that two floating polysilicon gate fingers  782 ,  784  are used instead of a single polysilicon gate finger  580  with the result that three diffusion regions  760 ,  762 ,  764  are formed instead of two. 
         [0030]      FIG. 8  is a top view of a third illustrative embodiment of the invention. Structure  800  includes source and drain regions  810 ,  820  formed in a well (not shown) with a polysilicon gate finger  840  formed on a dielectric layer (not shown) on the surface of the well. These elements will be recognized as forming a MOS transistor; but it will be understood that the transistor is only illustrative of any active device that may be used in the practice of the invention. A second MOS transistor is formed on the right-hand side of  FIG. 8  and includes the same elements bearing the same numbers followed by the suffix A. Again, the well is formed in a semiconductor substrate (not shown); and the cross-section of the active device, well and substrate of the embodiment of  FIG. 8  is similar to the cross-section of the active device, well  630  and substrate  605  of  FIG. 6 . 
         [0031]    Structure  800  further includes diffusion regions  860 ,  862  that make ohmic contact with well  830 , a floating polysilicon gate finger  880  between diffusion regions  860 ,  862  and ohmic contacts (or taps)  815  to source region  810 , ohmic contacts  825  to drain region  820 , and ohmic contacts  865  to diffusion region  860 . As shown in  FIG. 8 , the contacts  865  to diffusion region are located on only one side of the floating polysilicon gate finger  880  with the result that diffusion region  862  is left floating. The diffusion region  860  and contacts or taps  865  constitute the well strap. A STI region  850  surrounds the active devices and the diffusion regions. 
         [0032]    Structure  800  further comprises dummy polysilicon gate fingers  871 ,  872  located on opposite sides of the active device and above the diffusion regions. As a result, the well strap is separated from the active device by only one length of the dummy polysilicon gate finger; and the size of diffusion region  862  is reduced by eliminating the taps on one side of the floating gate finger. 
         [0033]    The process for forming structure  800  and the resulting structural cross-section are substantially the same as those of structure  500  except that contacts to the diffusion region are formed on only one side of the floating polysilicon gate finger  880 . 
         [0034]      FIG. 9  is a top view of a fourth illustrative embodiment of the invention. Structure  900  includes source and drain regions  910 ,  920  formed in a well (not shown) with a polysilicon gate finger  940  formed on a dielectric layer (not shown) on the surface of the well. These elements will be recognized as forming a MOS transistor; but it will be understood that the MOS transistor is only illustrative of any active device that may be used in the practice of the invention. A second MOS transistor is formed on the right-hand side of  FIG. 9  and includes the same elements bearing the same numbers followed by the suffix A. Again, the well is formed in a semiconductor substrate (not shown); and the cross-section of the active device, well and substrate of the embodiment of  FIG. 9  is similar to the cross-section of the active device, well  630  and substrate  605  of  FIG. 6 . 
         [0035]    Structure  900  further includes diffusion regions  960 ,  962 ,  964  that make ohmic contact with well  930 , at least two floating polysilicon gate fingers  982 ,  984  between diffusion regions  960 ,  962 ,  964 , and ohmic contacts (or taps)  915  to source region  910 , ohmic contacts  925  to drain region  920 , and ohmic contacts  965  to diffusion region  960 . As shown in  FIG. 9 , the contacts  965  to diffusion region  960  are located on only one side of the floating polysilicon gate fingers  982 ,  984  with the result that diffusion regions  962 ,  964  are left floating. The diffusion region  960  and contacts or taps  965  constitute the well strap. A STI region  950  surrounds the active devices and the well strap. 
         [0036]    Structure  900  further comprises dummy polysilicon gate fingers  971 ,  972  located on opposite sides of the active device and above portions of the STI regions. As a result, the well strap is separated from the active device by only one length of the dummy polysilicon gate finger; and the size of the diffusion region is reduced by eliminating the contacts on one side. 
         [0037]    The process for forming structure  900  and the resulting structural cross-section are substantially the same as those of structure  700  except that contacts to the diffusion region are made on only one side of the floating polysilicon gate fingers  982 ,  984 . 
         [0038]    As will be apparent to those skilled in the art, numerous variations may be practiced within the spirit and scope of the present invention. For example, the well and diffusion region can be either a P-type well and diffusion region or an N-type well and diffusion region. If the active device is a transistor, it can be an NMOS transistor in a P-well or a PMOS transistor in an N-well. Other active devices may also be used in the practice of the invention. For purposes of illustration, the contacts or taps have been depicted as a pair of contacts; but the invention may be practiced with a single contact or with more than two contacts. Other modifications will be apparent to those skilled in the art.

Technology Category: 5