Patent Document

BACKGROUND 
     Three dimensional (3D) integrated circuits (IC) structures have multiple layers. Communication between the multiple layers is typically performed by “pins” comprising one of interlayer vias or through silicon vias. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 2  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 3  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 4  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 5  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 6  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 7  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 8  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 9  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 10  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 11  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 12  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 13  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 14  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 15  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 16  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 17  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 18  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 19  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 20  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 21  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 22  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 23  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 24  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 25  is an illustration of a semiconductor arrangement, according to some embodiments. 
         FIG. 26  is a flow diagram illustrating a method of forming a semiconductor arrangement, according to some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The claimed subject matter is now described with reference to the drawings, wherein like reference numerals are generally used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide an understanding of the claimed subject matter. It is evident, however, that the claimed subject matter may be practiced without these specific details. In other instances, structures and devices are illustrated in block diagram form in order to facilitate describing the claimed subject matter. 
     According to some embodiments, a semiconductor arrangement comprises a three dimensional (3D) integrated circuit (IC) structure comprising a first layer comprising a first optical transmitter and a second layer comprising a second optical transmitter, the second layer over the first layer. In some embodiments, the first optical transmitter is configured to transmit data from the first layer to the second layer and the second optical transmitter is configured to transmit data from the second layer to the first layer. In some embodiments, the first layer comprises at least one of a first optical receiver or a first optical transceiver, the first optical transceiver comprising the first optical transmitter and the first optical receiver. In some embodiments, the second layer comprises at least one of a second optical receiver or a second optical transceiver, the second optical transceiver comprising the second optical transmitter and the second optical receiver. In some embodiments, the first layer comprises at least one of a first serializer connected to the first optical transmitter or a first deserializer connected to the first optical receiver. In some embodiments, the second layer comprises at least one of a second serializer connected to the second optical transmitter or a second deserializer connected to the second optical receiver. In some embodiments, transmitted signals are in a serialized format comprising a first serial data output and a second serial data output, such as through the use of the first serializer or the second serializer. In some embodiment, a first serializer/deserializer (SerDes) comprising the first serializer and the first deserializer is connected to the first optical transceiver, which converts electrical signals, such as the first serial data output, into modulated light signals at an optical wavelength between 0.9-6.0 μm. In some embodiments, optical wavelengths between 0.9-6.0 μm are transparent or semi-transparent on a silicon substrate. In some embodiments, a number of pins required for the semiconductor arrangement to function is reduced compared to an arraignment without an optical transmitter and an optical receiver, or a serializer and a deserializer. In some embodiments, communication in a 3D IC structure is achieved through coupling optical signals to transmit data from at least one of the first layer of the 3D IC structure to the second layer of the 3D IC structure or the second layer of the 3D IC structure to the first layer of the 3D IC structure. In some embodiments, the semiconductor arrangement comprising the 3D IC structure does not require an interlayer via (ILV) or through silicon via (TSV) to facilitate communication between the first layer of the 3D IC structure and the second layer of the 3D IC structure. In some embodiments, a semiconductor arrangement without an optical transmitter and an optical receiver, or a serializer and a deserializer has ILV misalignment between a first layer and a second layer, due to the ILV having a small size between about 1 μm to about 10 μm. In some embodiments, a semiconductor arrangement without an optical transmitter and an optical receiver, or a serializer and a deserializer has a TSV. In some embodiments, the TSV has a size between about 75 μm to about 150 μm, which is a greater size than the ILV and thus has a greater area penalty than the ILV. In some embodiments, the semiconductor arrangement comprising the first optical transmitter connected to the first serializer on the first layer and the second optical receiver connected to the second deserializer on the second layer, has a smaller area than the TSV and achieves alignment through aligning the data transmission, comprising an alignment signal, of the first optical transmitter to the second optical receiver, and thus lacks the misalignment of the ILV. 
       FIG. 1  illustrates a semiconductor arrangement  100 , according to some embodiments. In some embodiments, the semiconductor arrangement  100  comprises a three dimensional (3D) integrated circuit (IC) structure  103  comprising a first layer  102   a  and a second layer  102   b . In some embodiments, the first layer  102   a  comprises first memory macros  122   a  connected to a first serializer/deserializer (SerDes)  112   a . In some embodiments, the first SerDes  112   a  comprises a first serializer  116   a  and a first deserializer  114   a . In some embodiments, the first SerDes  112   a  is connected to a first optical transceiver  106   a . In some embodiments, the first optical transceiver  106   a  comprises a first optical receiver  110   a  and a first optical transmitter  108   a . In some embodiments, the first serializer  116   a  converts a first parallel data input  126   a  from the first memory macros  122   a  into a first serial data output  118   a . In some embodiments, the first deserializer  114   a  converts a first serial data input  120   a  from the first optical receiver  110   a  into a first parallel data output  128   a . In some embodiments, the first deserializer  114   a  sends the first parallel data output  128   a  to the first memory macros  122   a . In some embodiments, the first serializer  116   a  sends the serial data output  118   a  to the first optical transmitter  108   a . In some embodiments, the first optical transmitter  108   a  transmits data  124   a  from the first layer  102   a  to the second optical transceiver  106   b  on the second layer  102   b . In some embodiments, at least one of the first serial data input  120   a , the first serial data output  118   a , the first parallel data input  126   a , the first parallel data output  128   a  or the data  124   a  comprise a clock signal. In some embodiments, the second optical transceiver  106   b  is connected to a second SerDes  112   b . In some embodiments, the second SerDes  112   b  comprises a second serializer  116   b  and a second deserializer  114   b . In some embodiments, the second optical transceiver  106   b  comprises a second optical transmitter  108   b  and a second optical receiver  110   b . In some embodiments, the second optical receiver  110   b  is connected to the second deserializer  114   b . In some embodiments, the second optical receiver  110   b  sends a second serial data input  120   b  to the second deserializer  114   b . In some embodiments, the second deserializer  114   b  converts the second serial data input  120   b  to a second parallel data output  128   b . In some embodiments, the second deserializer  114   b  is connected to second memory macros  122   b . In some embodiments, the second deserializer  114   b  sends the second parallel data output  128   b  to the second memory macros  122   b  on the second layer  102   b . In some embodiments, the second memory macros  122   b  is connected to the second serializer  116   b . In some embodiments, the second memory macros  122   b  sends a second parallel input  126   b  to the second serializer  116   b . In some embodiments, the second serializer  116   b  converts the second parallel data input  126   b  into a second serial output  118   b . In some embodiments, the second serializer  116   b  is connected to the second optical transmitter  108   b . In some embodiments, the second serializer  116   b  sends a second serial data output  118   b  to the second optical transmitter  108   b . In some embodiments, the second optical transmitter  108   b  transmits data  124   b  from the second layer  102   b  to the first optical transceiver  106   a  on the first layer  102   a . In some embodiments, at least one of the second serial data input  120   b , the second serial data output  118   b , the second parallel data input  126   b , the second parallel data output  128   b  or the data  124   b  comprise a clock signal. Although two layers are shown, multiple layers with multiple optical transceivers connected to multiple SerDes are contemplated. Although optical transmitters and optical receivers that are part of optical transceivers are shown, separate components are contemplated such that a layer has at least one of an optical transmitter or an optical receiver that is or is not part of an optical transceiver. 
     According to some embodiments, the first optical transmitter  108   a  comprises at least one of a first internal optical source or a first external optical source. According to some embodiments, the second optical transmitter  108   b  comprises at least one of a second internal optical source or a second external optical source. According to some embodiments, a first optical transmitter  108   a  with the first internal optical source or the second optical transmitter  108   b  with the second internal optical source are illustrated in  FIGS. 2-7 . According to some embodiments, the first optical transmitter  108   a  with the first external optical source or the second optical transmitter  108   b  with the second external optical source are illustrated in  FIGS. 8-13 . 
     Turning to  FIG. 2 , a passivation layer  310  is illustrated over a substrate  302 , where the substrate  302  comprises a first active area  304  and a second active area  306 , and a first doped area  308 , according to some embodiments. In some embodiments, the substrate  302  comprises at least one of silicon, polysilicon, or germanium. In some embodiments, the substrate  302  comprises a compound group of at least one of group 3 elements, such as aluminum, indium, or gallium, or group 5 elements, such as arsenic, phosphorous, antimony. According to some embodiments, the substrate  302  comprises at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the first active area  304 , the second active area  306  and the first doped area  308  are formed by implantation of a first dopant, such as boron. In some embodiments, the first active area  304  and the second active area  306  comprise at least one of a source or a drain. In some embodiments, the first doped area  308  comprises a seed layer. In some embodiments, the passivation layer  310  comprises at least one of SiO 2  or silicon nitride (Si 3 N 4 ). In some embodiments, the passivation layer  310  comprises a thickness of between about 2 μm to about 50 μm. 
     Turning to  FIG. 3 , a gate  312  is illustrated between the first active area  304  and the second active area  306  and an optical transmitter  108  is illustrated in the passivation layer  310 , according to some embodiments. In some embodiments, the gate  312  is formed by forming a first opening in the passivation layer  310  between the first active area  304  and the second active area  306 , and forming the gate  312 , such that the gate  312 , the first active area  304  and the second active area  306  comprise a transistor. In some embodiments, the gate  312  comprises at least one of a polysilicon or a metal. In some embodiments, the gate  312  comprises a high dielectric constant material in contact with the substrate  302 . In some embodiments, the first optical transmitter  108   a  as shown in  FIG. 1  comprises a first internal optical source and the second optical transmitter  108   b  shown in  FIG. 1  comprises a second internal optical source. In some embodiments, the first internal optical source comprises a first vertical cavity laser  317 . In some embodiments, the first vertical cavity laser  317  comprises a top mirror  314 , a gain region  318  and a bottom mirror  316 , such that the gain region  318  is between the top mirror  314  and the bottom mirror  316 . In some embodiments, the top mirror  314  and the bottom mirror  316  comprise alternating mirror layers, such that even mirror layers have the same composition and odd mirror layers have the same composition, such that a first mirror layer has the same composition as a third mirror layer, and a second mirror layer has the same composition as a fourth mirror layer. In some embodiments, the first vertical cavity laser  317  is grown, such as by epitaxial growth. In some embodiments, the first vertical cavity laser  317  is formed by high vacuum chemical vapor deposition (HVCVD). In some embodiments, at least one of the top mirror  314  or the bottom mirror  316  are formed by alternating different gasses in a chamber during HVCVD. In some embodiments, the even mirror layers comprise at least one of a first optical material or a second optical material, such that the first optical material has different optical properties than the second optical material. In some embodiments, the odd mirror layers comprise a first optical material or a second optical material, such that the odd mirror layers comprise the first optical material when the even mirror layer comprise the second optical material and the odd mirror layers comprise the second optical material when the even layers comprise the first optical material. In some embodiments, the first vertical cavity laser  317  comprises at least one of silicon, germanium, tin, or at least one of group 3 elements, such as aluminum, indium, or gallium, or group 5 elements, such as arsenic, phosphorous, antimony. In some embodiments, the gain region  218  comprises at least one of quantum wells, quantum dots, or nano-crystals. 
     Turning to  FIG. 4 , a first connect  322  connected to the first active area  304 , a second connect  320  connected to the second active area  306 , and a third connect  311  connected to the first doped area  308  are illustrated, according to some embodiments. In some embodiments, the first connect  322 , the second connect  320 , and the third connect  311  comprise a conductive material, such as metal. In some embodiments at least one of the first connect  322 , the second connect  320 , or the third connect  311  comprise different conductive materials. In some embodiments, the transistor acts as switch to activate the first vertical cavity laser  317 . In some embodiments, the serializer  116  sends a serial data output  118  to the first vertical cavity laser  317  comprising the data  124 . In some embodiments, the first connect  322  supplies a current to the first active area  304  and the second connect  320  supplies an activation current to the first vertical cavity laser  317 . In some embodiments, the third connect  311  is connected to ground, such that the current flowing through the first vertical cavity laser  317  goes to ground. In some embodiments, the first vertical cavity laser  317  transmits modulated light signals  324 , where the arrows indicate the propagation direction of the data transmitted as modulated light signals  324 . In some embodiments, the data  124  is converted into modulated light signals  324  that transmit the data  124  to an optical receiver on a different layer than the layer that the first vertical cavity laser  317  occupies. In some embodiments, the first optical transmitter  108   a , such as illustrated in  FIG. 1 , comprises the first vertical cavity laser  317  on the first layer  102   a , such as illustrated in  FIG. 4 . In some embodiments, the second optical transmitter  108   b , such as illustrated in  FIG. 1 , comprises a second vertical cavity laser on the second layer  102   b , such as illustrated in  FIG. 4 . 
     Turning to  FIG. 5 , the substrate  302 , the first active area  304 , the second active area  306 , the first doped area  308  and the passivation layer  310  are illustrated, which are formed as described above with regards to  FIG. 2 , according to some embodiments. 
     In  FIG. 6 , a gate  312  between the first active area  304  and the second active area  306  in the passivation layer  310 , which forms a transistor, and an optical transmitter  108  in the passivation layer  310  are illustrated, according to some embodiments. In some embodiments, the gate  312  is formed as described above with regards to the gate  312 , as illustrated in  FIG. 3 . In some embodiments, the optical transmitter  108  comprises an internal optical source. In some embodiments, the internal optical source comprises a first laser  417 , where the first laser  417  comprises at least one of a SiGe laser or a hybrid laser. In some embodiments, the first laser  417  comprises at least one of quantum wells, quantum dots, or nano-crystals. In some embodiments, the first laser  417  comprises at least one of silicon, germanium, tin, or at least one of group 3 elements, such as aluminum, indium, or gallium, or group 5 elements, such as arsenic, phosphorous, antimony. In some embodiments, the first laser  417  is formed by at least one of epitaxial growth or wafer-level bonding. In some embodiments, the first laser  417  is formed in a second opening in the passivation layer  310 . In some embodiments, the first laser  417  has a first junction  414 , a second junction  418  and a first contact  416 . In some embodiments, the first junction  414  is at least one of a positive type junction or a negative type junction. In some embodiments, the second junction  418  is a positive type junction when the first junction  414  is a negative type junction. In some embodiments, the second junction  418  is a negative type junction when the first junction  414  is a positive type junction. In some embodiments, the first contact  416  is a low resistance contact, such as a metal. 
     In  FIG. 7 , the first laser  417  in contact with a waveguide  420  and a grating coupler  440  in contact with the waveguide  420  is illustrated, according to some embodiments. In some embodiments, the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are formed as described above with regard to the first metal connect  322 , the second metal connect  320  and the third metal connect  311  as illustrated in  FIG. 4 . In some embodiments, the second connect  320  is connected to the second active area  306  and the first contact  416  of the first laser  417 . In some embodiments, the waveguide  420  comprises an SOI waveguide, a dielectric waveguide, or a plasmonic waveguide. In some embodiments, the dielectric waveguide comprises at least one of patterned silicon nitride, amorphous silicon, or high dielectric material surrounded by a low dielectric constant material, such as silicon oxide. In some embodiments, the plasmonic waveguide comprises patterned metal nano-wires surrounded by a dielectric material. In some embodiments, the grating coupler  440  comprises one of a metal or a high dielectric material. In some embodiments, the grating coupler  440  comprises several segments with a distance between each segment. In some embodiments, the first laser  417  generates a laser signal comprising data  124 , such as a serial data output  118  from the serializer  116 , which passes through the waveguide  420  to the grated coupler  440 . In some embodiments, the grated coupler  440  transforms the laser signal into the modulated light signal  324 . In some embodiment, the grating coupler  440  transmits the modulated the light signals  324 , where the arrows indicate the propagation direction of the data  124  transmitted as the modulated light signal  324 . In some embodiments, the first optical transmitter  108   a , such as illustrated in  FIG. 1 , comprises the first laser  417  in contact with the first waveguide  420  and the first grating coupler  440  on the first layer  102   a , such as illustrated in  FIG. 7 . In some embodiments, the second optical transmitter  108   b , such as illustrated in  FIG. 1 , comprises a second laser  417  in contact with the second waveguide  420  and the second grating coupler  440  on the second layer  102   b , such as illustrated in  FIG. 7 . 
     Turning to  FIG. 8 , the substrate  302 , the first active area  304 , the second active area  306 , the first doped area  308  and the passivation layer  310  are illustrated, which are formed as described above with regards to  FIG. 2 , according to some embodiments. 
     In  FIG. 9 , a gate  312  between the first active area  304  and the second active area  306  in the passivation layer, which forms a transistor, and an optical transmitter  108  comprising an external laser  530  and an electro-absorption modulator  517  are illustrated, according to some embodiments. In some embodiments, the gate  312  is formed as described above with regards to the gate  312 , as illustrated in  FIG. 3 . In some embodiments, the external laser  530  comprises a laser, such as a vertical cavity laser or a fiber array with lens coupler. In some embodiments, the electro-absorption modulator  517  is formed in a third opening in the passivation layer over the first doped area  308 . In some embodiments, the electro-absorption modulator  517  comprises even modulator layers  516  and odd modulator layers  514 , where the even modulator layers  516  have a different composition having different optical properties than the odd modulator layers  514 . In some embodiments, the electro-absorption modulator  517  comprises at least one of silicon, germanium, tin, or at least one of group 3 elements, such as aluminum, indium, or gallium, or group 5 elements, such as arsenic, phosphorous, antimony. In some embodiments, the electro-absorption modulator  517  is formed by at least one of epitaxial growth or wafer-level bonding. 
     In  FIG. 10 , the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are illustrated, according to some embodiments. In some embodiments, the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are formed as described above with regard to the first metal connect  322 , the second metal connect  320  and the third metal connect  311  as illustrated in  FIG. 4 . In some embodiments, the second connect  320  is in connected to the second active area  306  and the electro-absorption modulator  517 . According to some embodiments, the external laser  530  generates a laser signal  524 , where the arrows indicate the propagation direction of the laser signal  524 . In some embodiments, the laser signal  524  is applied to the electro-absorption modulator  517 . In some embodiments, the serializer  116  sends a serial data output  118  to the electro-absorption modulator  517  comprising the data  124 . In some embodiments, the laser signal  524  activates the electro-absorption modulator  517  to transform the laser signal  524  into a modulated light signal  324  comprising the serial data output  118 , where the arrows indicate the propagation direction of the data  124  transmitted as the modulated light signal  324 . In some embodiments, the first optical transmitter  108   a , such as illustrated in  FIG. 1 , comprises the first external laser  530  in contact with the electro-absorption modulator  517  on the first layer  102   a , such as illustrated in  FIG. 10 . In some embodiments, the first optical transmitter  108   a , such as illustrated in  FIG. 1 , comprises a first external optical source, the first external optical source comprising a first vertical cavity laser array or a first fiber array with a lens coupler. In some embodiments, the second optical transmitter  108   b , such as illustrated in  FIG. 1 , comprises a second external laser  530  in contact with the electro-absorption modulator  530  on the second layer  102   b , such as illustrated in  FIG. 10 . In some embodiments, the second optical transmitter  108   b , such as illustrated in  FIG. 1 , comprises a second external optical source, the second external optical source comprising a second vertical cavity laser array or a second fiber array with a lens coupler. 
     Turning to  FIG. 11 , the substrate  302 , the first active area  304 , the second active area  306 , the passivation layer  310  and a waveguide modulator  620  in the passivation layer  310  are illustrated, according to some embodiments. In some embodiments, the substrate  302 , the first active area  304 , the second active area  306  and the passivation layer  310 , are formed as described above with regards to  FIG. 2 . In some embodiments, the waveguide modulator  620  comprises a first waveguide grating coupler  621   a  and a second waveguide grating coupler  261   b . In some embodiments, the first waveguide grating coupler  621   a  comprises several segments with a distance between each segment. In some embodiments, the second waveguide grating coupler  621   b  comprises several segments with a distance between each segment. In some embodiments, the waveguide modulator  620  comprises at least one of silicon, germanium, tin, or at least one of group 3 elements, such as aluminum, indium, or gallium, or group 5 elements, such as arsenic, phosphorous, antimony. In some embodiments, the waveguide modulator  620  is formed by at least one of epitaxial growth or wafer-level bonding. In some embodiments, the waveguide modulator  620  comprises a first waveguide contact  608   a  and a second waveguide contact  608   b , where at least one of the first waveguide contact  608   a  or the second waveguide contact  608   b  is a low resistance contact, such as a metal. 
     In  FIG. 12 , a gate  312  between the first active area  304  and the second active area  306  in the passivation layer, which forms a transistor, and an optical transmitter  108  comprising the external laser  530  and the waveguide modulator  517  are illustrated, according to some embodiments. In some embodiments, the gate  312  is formed as described above with regards to the gate  312 , as illustrated in  FIG. 3 . In some embodiments, the external laser  530  comprises a laser, such as a vertical cavity laser or a fiber array with lens coupler. 
     In  FIG. 13 , the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are illustrated, according to some embodiments. In some embodiments, the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are formed as described above with regard to the first metal connect  322 , the second metal connect  320  and the third metal connect  311  as illustrated in  FIG. 4 . In some embodiments, the second connect  320  is connected to the second active area  306  and the first waveguide contact  608   a , and the third connect  311  is connected to the second waveguide contact  608   b . According to some embodiments, the external laser  530  generates a laser signal  524 , where the arrows indicate the propagation direction of the laser signal  524 . In some embodiments, the serializer  116  sends a serial data output  118  to the waveguide modulator  630  comprising the data  124 . In some embodiments, the laser signal  524  is applied to the first waveguide grating coupler  621   a . In some embodiments, the laser signal  524  activates the waveguide modulator  620  to transform the laser signal  524  into a modulated light signal  324  comprising the serial data output  118 . In some embodiments, the modulated light signal  324  is transmitted from the second waveguide grating coupler  621   b , where the arrows indicate the propagation direction of the data  124  transmitted as the modulated light signal  324 . In some embodiments, the first optical transmitter  108   a , such as illustrated in  FIG. 1 , comprises the first external laser  530  in contact with the waveguide modulator  620  on the first layer  102   a , such as illustrated in  FIG. 13 . In some embodiments, the first optical transmitter  108   a , such as illustrated in  FIG. 1 , comprises a first external optical source, the first external optical source comprising a first vertical cavity laser array or a first fiber array with a lens coupler. In some embodiments, the second optical transmitter  108   b , such as illustrated in  FIG. 1 , comprises a second external laser  530  in contact with the waveguide modulator  620  on the second layer  102   b , such as illustrated in  FIG. 13 . In some embodiments, the second optical transmitter  108   b , such as illustrated in  FIG. 1 , comprises a second external optical source, the second external optical source comprising a second vertical cavity laser array or a second fiber array with a lens coupler. 
     According to some embodiments, the first optical receiver  110   a  comprises at least one of a first photodiode or a first photo-transistor. According to some embodiments, the second optical receiver  110   b  comprises at least one of a second photodiode or a second photo-transistor. According to some embodiments, the first optical receiver  110   a  comprising the first photodiode or the second optical receiver  110   b  comprising the second photodiode is illustrated in  FIGS. 14-19 . According to some embodiments, the first optical receiver  110   a  comprising the first photo-transistor or the second optical receiver  110   b  comprising the second photo-transistor is illustrated in  FIGS. 20-25 . 
     Turning to  FIG. 14 , the substrate  302 , the first active area  304 , the second active area  306 , the first doped area  308  and the passivation layer  310 , which are formed as described above with regards to  FIG. 2  are illustrated, according to some embodiments. 
     In  FIG. 15 , a gate  312  between the first active area  304  and the second active area  306  in the passivation layer, which forms a transistor, and a photodiode  717  in the passivation layer  310  are illustrated, according to some embodiments. In some embodiments, the gate  312  is formed as described above with regards to the gate  312 , as illustrated in  FIG. 3 . In some embodiments, the optical receiver  110  comprises the photodiode  717 . In some embodiments, the photodiode  717  comprises a p-i-n junction comprising a first photodiode junction  716 , a second photodiode junction  714  and an intrinsic area  718 . In some embodiments, the first photodiode junction  716  comprises at least one of a positive type junction or negative type junction. In some embodiments, the second photodiode junction  714  comprises a positive type junction when the first photodiode junction  716  comprises a negative type junction. In some embodiments, the second photodiode junction  714  comprises a negative type junction when the first photodiode junction  716  comprises a positive type junction. In some embodiments, the photodiode  717  comprises at least one of silicon, germanium, tin, or at least one of group 3 elements, such as aluminum, indium, or gallium, or group 5 elements, such as arsenic, phosphorous, antimony. In some embodiments, the photodiode  717  is formed by at least one of epitaxial growth or wafer-level bonding. 
     In  FIG. 16 , the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are illustrated, according to some embodiments. In some embodiments, the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are formed as described above with regard to the first metal connect  322 , the second metal connect  320  and the third metal connect  311  as illustrated in  FIG. 4 . In some embodiments, the second metal connect is connected to the second active area  306  and the photodiode  717 . In some embodiments, the transistor acts a switch to activate conduction from the photodiode  717  to the memory macros  122 . In some embodiments, the photodiode  717  receives modulated light signals  324 , where the arrows indicate the propagation direction of the data  124  received as modulated light signals  324 . In some embodiments, the data  124  is converted from modulated light signals  324  that transmit the data  124 , to an electrical data signal that comprises a serial data input  120 . In some embodiments, the deserializer  114  converts the serial data input  120  received from the optical receiver  110  into a parallel data output  128 . In some embodiments, the first optical receiver  110   a , such as illustrated in  FIG. 1 , comprises a first photodiode  717  on the first layer  102   a , as illustrated in  FIG. 16 . In some embodiments, the second optical receiver  110   b , such as illustrated in  FIG. 1  comprises a second photodiode  717  on the second layer  102   b , such as illustrated in  FIG. 16 . 
     Turning to  FIG. 17 , the substrate  302 , the first active area  304 , the second active area  306 , the first doped area  308  and the passivation layer  310  are illustrated, which are formed as described above with regards to  FIG. 2 , according to some embodiments. 
     In  FIG. 18 , a gate  312  is illustrated between the first active area  304  and the second active area  306  in the passivation layer, which forms a transistor, and a photodiode  717  in the passivation layer  310  are illustrated, according to some embodiments. In some embodiments, the gate  312  is formed as described above with regards to the gate  312 , as illustrated in  FIG. 3 . In some embodiments, the photodiode is formed as described above with regards to the photodiode  717 , as illustrated in  FIG. 15 . 
     In  FIG. 19 , the first metal connect  322 , the second metal connect  320 , the third metal connect  311 , a plasmonic waveguide  820  and a grating coupler  440  connected to the photodiode  717  are illustrated, according to some embodiments. In some embodiments, the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are formed as described above with regard to the first metal connect  322 , the second metal connect  320  and the third metal connect  311  as illustrated in  FIG. 16 . In some embodiments, the plasmonic waveguide  820  comprises patterned metal nano-wires surrounded by a dielectric material. In some embodiments, the grating coupler  440  comprises one of a metal or a high dielectric material. In some embodiments, the grating coupler  440  comprises several segments with a distance between each segment. In some embodiments, the modulated light signals  324  are input into the grating coupler  440 . In some embodiments, the modulated light signal  324  passes though the grating coupler  440  and the plasmonic waveguide  820  and are applied onto the photodiode  717 . In some embodiments, the photodiode  717  transforms the modulated light single  324  into electrical data signals comprising a serial data input  120 . In some embodiments, the serial data input  120  is sent to the deserializer  114 . In some embodiments, the first optical receiver  110   a , such as illustrated in  FIG. 1  comprises a first photodiode  717  connected to a first plasmonic waveguide  820  and a first grating coupler  420  on the first layer  102   a , such as illustrated in  FIG. 19 . In some embodiments, the second optical receiver  110   b , such as illustrated in  FIG. 1 , comprises a second photodiode  717  connected to a second plasmonic waveguide  820  and a second grating coupler  420  on the second layer  102   b , as illustrated in  FIG. 19 . 
     Turning to  FIG. 20 , the substrate  302 , the first active area  304 , the second active area  306 , the first doped area  308  and the passivation layer  310  are illustrated, which are formed as described above with regards to  FIG. 2 , according to some embodiments. 
     In  FIG. 21 , a gate  312  between the first active area  304  and the second active area  306  in the passivation layer, which forms a transistor and an optical receiver  110  comprising a photo-transistor  917  in the passivation layer  310  are illustrated, according to some embodiments. In some embodiments, the gate  312  is formed as described above with regards to the gate  312 , as illustrated in  FIG. 3 . In some embodiments, the photo-transistor  917  comprises a first transistor layer  914 , a second transistor layer  918 , and a third transistor layer  916 . In some embodiments, the first transistor layer  914  and the third transistor layer  916  comprise at least one of a positive type junction or a negative type junction. In some embodiments, the second transistor layer  918  comprises a positive type junction if the first transistor layer  914  and the third transistor layer  916  comprise a negative type junction. In some embodiments, the second transistor layer  918  comprises a negative type junction if the first transistor layer  914  and the third transistor layer  916  comprise a positive type junction. In some embodiments, the phototransistor  917  comprises at least one of silicon, germanium, tin, or at least one of group 3 elements, such as aluminum, indium, or gallium, or group 5 elements, such as arsenic, phosphorous, antimony. In some embodiments, the phototransistor  917  is formed by at least one of epitaxial growth or wafer-level bonding. 
     In  FIG. 22 , the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are illustrated, according to some embodiments. In some embodiments, the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are formed as described above with regard to the first metal connect  322 , the second metal connect  320  and the third metal connect  311  as illustrated in  FIG. 4 . In some embodiments, the second metal connect  320  is connected to the second active area  306  and the third transistor layer  916 . In some embodiments, the third metal connect  311  is connected to the first transistor layer  914 . In some embodiments, the transistor acts as a switch to activate conduction from the photo-transistor  917  to the memory macros  122 . In some embodiments, the photo-transistor  917  receives modulated light signals  324 , where the arrows indicate the propagation direction of the data  124  received as modulated light signals  324 . In some embodiments, the data  124  is converted from the modulated light signals  324  that transmit the data  124 , to an electrical data signal that comprises a serial data input  120 . In some embodiments, the deserializer  114  converts the serial data input  120  received from the optical receiver  110  into a parallel data output  128 . In some embodiments, the first optical receiver  110   a , such as illustrated in  FIG. 1 , comprises a photo-transistor  917  on the first layer  102   a , such as illustrated in  FIG. 22 . In some embodiments, the second optical receiver  110   b , such as illustrated in  FIG. 1 , comprises a second photo-transistor  917  on the second layer  102   b , such as illustrated in  FIG. 22 . 
     Turning to  FIG. 23 , the substrate  302 , the first active area  304 , the second active area  306 , the first doped area  308  and the passivation layer  310  are illustrated, which are formed as described above with regards to  FIG. 2 , according to some embodiments. 
     In  FIG. 24 , a gate  312  is between the first active area  304  and the second active area  306  in the passivation layer, which forms a transistor, and the photo-transistor  917  in the passivation layer  310  are illustrated, according to some embodiments. In some embodiments, the gate  312  is formed as described above with regards to the gate  312 , as illustrated in  FIG. 3 . In some embodiments, the photo-transistor  917  is formed as described above with regards to the photo-transistor  917 , as illustrated in  FIG. 21 . 
     In  FIG. 25 , the first metal connect  322 , the second metal connect  320 , the third metal connect  311  and a plasmonic waveguide  1020  and a grating coupler  420  are illustrated, according to some embodiments. In some embodiments, the first metal connect  322 , the second metal connect  320  and the third metal connect  311  are formed as described above with regard to the first metal connect  322 , the second metal connect  320  and the third metal connect  311  as illustrated in  FIG. 22 . In some embodiments, the transistor acts as a switch to activate conduction from the photo-transistor  917  to the memory macros  122 . In some embodiments, the modulated light signal  324  is input into the grating coupler  440  where the arrows indicate the propagation direction of the data  124  received as modulated light signals  324 . In some embodiments, the modulated light signal  324  passes though the plasmonic waveguide  1020  and is applied onto the photo-transistor  917 . In some embodiments, the photo-transistor  917  transforms the modulated light signal  324  into electrical data signals that comprise a serial data input  120 . In some embodiments, the deserializer  114  converts the serial data input  120  received from the optical receiver  110  into a parallel data output  128 . In some embodiments, the first optical receiver  110   a , such as illustrated in  FIG. 1 , comprises a first photo-transistor  917  connected to a first plasmonic waveguide  1020  and a first grating coupler  420  on the first layer  102   a , as illustrated in  FIG. 25 . In some embodiments, the second optical receiver  110   b , such as illustrated in  FIG. 1 , comprises a second photo-transistor  917  connected to a second plasmonic waveguide  1020  and a second grating coupler  420  on the second layer  102   b , such as illustrated in  FIG. 25 . 
     An example method  1100  of forming a semiconductor arrangement, such as semiconductor arrangement  100  according to some embodiments, is illustrated in  FIG. 26 . 
     At  1102 , according to some embodiments, a first layer  102   a  comprising at least one of a first optical transmitter  108   a , a first optical receiver  110   a  or a first optical transceiver  106   a  is formed, as illustrated in  FIG. 1 . In some embodiments, the first optical transceiver  106   a  comprises at least one of the first optical transmitter  108   a  or the first optical receiver  110   a.    
     At  1104 , according to some embodiments, a second layer  102   b  comprising at least one of a second optical transmitter  108   b , a second optical receiver or a second optical transceiver  106   b  is formed, as illustrated in  FIG. 1 . In some embodiments, the second optical transceiver  106   a  comprises at least one of the second optical transmitter  108   a  or the second optical receiver  110   a.    
     At  1106 , according to some embodiments, at least one of a first serializer  116   a  connected to the first optical transmitter  108   a , a first deserializer  114   a  connected to the first optical receiver  110   a , a second serializer  116   b  connected to the second optical transmitter  108   b , or a second deserializer  114   a  connected to the second optical receiver  110   b  are formed, as illustrated in  FIG. 1 . 
     At  1108 , the first optical transmitter  108   a  is aligned with the second optical receiver  110   b , such that the first optical transmitter  108   a  transmits data  124   a  to the second optical receiver  110   b . In some embodiment, the first optical transmitter  108   a  transmits alignment data to the second optical receiver  110   a  to determine an amount of alignment data received. In some embodiments, the first layer  102   a  position or the second layer  102   b  position is adjusted until the amount of alignment data received by the second optical receiver  110   b  meets an alignment threshold. In some embodiments, the alignment threshold is met when the second optical receiver  110   b  receives greater than 50% of the alignment signal transmitted by the first optical transmitter  108   a.    
     According to some embodiments, a semiconductor arrangement comprises a three dimensional (3D) integrated circuit (IC) structure. In some embodiments, the 3D IC structure comprises a first layer comprising a first optical transmitter and a second layer comprising a second optical transmitter over the first layer. In some embodiments, the first optical transmitter is configured to transmit data from the first layer to the second layer and the second optical transmitter is configured to transmit data from the second layer to the first layer. 
     According to some embodiments, a method of making a semiconductor arrangement comprises forming a three dimensional (3D) integrated circuit (IC) structure. The forming the 3D IC structure comprising forming a first layer comprising a first optical transmitter, forming a second layer comprising a second optical receiver and aligning the first optical transmitter with the a second optical receiver, such that the first optical transmitter transmits data to the first optical receiver. 
     According to some embodiments, a semiconductor arrangement comprises a three dimensional (3D) integrated circuit (IC) structure. In some embodiments, the 3D IC structure comprises a first layer comprising a first optical transmitter and a second layer comprising a second optical receiver. In some embodiments, the second layer is over the first layer. In some embodiments, the first optical transmitter is configured to transmit data to the second optical receiver, the data comprising a clock signal. 
     Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as embodiment forms of implementing at least some of the claims. 
     Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed to imply that these operations are necessarily order dependent. Alternative ordering will be appreciated having the benefit of this description. Further, it will be understood that not all operations are necessarily present in each embodiment provided herein. Also, it will be understood that not all operations are necessary in some embodiments. 
     It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions relative to one another, such as structural dimensions or orientations, for example, for purposes of simplicity and ease of understanding and that actual dimensions of the same differ substantially from that illustrated herein, in some embodiments. Additionally, a variety of techniques exist for forming the layers features, elements, etc. mentioned herein, such as etching techniques, implanting techniques, doping techniques, spin-on techniques, sputtering techniques such as magnetron or ion beam sputtering, growth techniques, such as thermal growth or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), for example. 
     Moreover, “exemplary” is used herein to mean serving as an example, instance, illustration, etc., and not necessarily as advantageous. As used in this application, “or” is intended to mean an inclusive “or” rather than an exclusive “or”. In addition, “a” and “an” as used in this application and the appended claims are generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Also, at least one of A and B and/or the like generally means A or B or both A and B. Furthermore, to the extent that “includes”, “having”, “has”, “with”, or variants thereof are used, such terms are intended to be inclusive in a manner similar to the term “comprising”. Also, unless specified otherwise, “first,” “second,” or the like are not intended to imply a temporal aspect, a spatial aspect, an ordering, etc. Rather, such terms are merely used as identifiers, names, etc. for features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or the same element. 
     Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure comprises all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

Technology Category: h