Patent Document

BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to clock-data recovery. 
     2. Description of Related Art 
     Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “signal,” “clock,” “square wave,” “edge (of clock),” “binary data,” “vertical eye opening,” “binary phase detector,” “loop filter,” “voltage-controlled oscillator,” “ADC (analog-to-digital converter),” “inverter,” “delay-lock loop,” and “clock recovery.” Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus will not be explained in detail here. 
     A clock-data recovery circuit is a circuit that receives a received signal, which carries a stream of serial binary data, and establishes a recovered clock that is aligned with a timing of the received signal. An exemplary waveform of a prior art clock-data recovery circuit, as observed by using an oscilloscope, is shown in  FIG. 1A . The received signal, when observed using an oscilloscope, exhibits an “eye pattern”. The recovered clock is represented as a square wave with a first edge (i.e., rising edge) aligned with a data transition of the received signal (e.g., edges  101 ,  103 ,  105 ,  107 , and  109 ) and a second edge (i.e., falling edge) aligned with a center of the serial binary data carried by the received signal (e.g., edges  102 ,  104 ,  106 , and  108 ). Once the recovered clock is properly established, the serial binary data can be detected by sampling the received signal using the second edge of the recovered clock. A principal of clock-data recovery is well known in prior art and thus not described in detail here. 
     The prior art clock-data recovery circuit works well if the received signal exhibits a symmetrical eye pattern. However, sometimes, the received signal exhibits a nonsymmetrical eye pattern, as shown in  FIG. 1B . In such a situation, the second edge  112  will not be perfectly aligned with the optimal sampling instant  113  where the received signal has the maximum “vertical eye opening” when the first edge  111  is aligned with the transition of the data carried by the received signal. 
     What is desired is a clock-data recovery circuit that establishes a clock with an edge that is aligned with the optimal timing where the received signal has a maximum “vertical eye opening.” 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is a circuit for data clock recovery and uses a method for estimating timing of a vertical eye opening of a received signal at maximum height. 
     The present invention improves performance of a clock-recovery circuit by adjusting a phase of a recovered clock in accordance with an estimate of a vertical eye opening of a received signal. 
     The present invention adjusts a phase of a recovered clock to align with an optimal timing where a vertical eye opening of the received signal is maximum. 
     In an exemplary embodiment, a circuit comprises: a variable delay circuit receiving a recovered clock and outputting a calibrated clock in accordance with a control code; a two-bit ADC (analog-to-digital converter) converting a received signal into two-bit data in accordance with a timing of the calibrated clock; and a vertical eye monitor circuit receiving the two-bit data and outputting the control code, wherein a timing of the recovered clock is approximately aligned with a transition portion of serial binary data carried by the received signal. In an embodiment, the vertical eye monitor circuit establishes an estimate of a vertical eye opening of the received signal based on statistics of the two-bit data, and adjusts the control code in accordance with a sign of a change of the estimate of the vertical eye opening of the received signal in response to a previous change of the control code. 
     In an exemplary embodiment, a method comprises: receiving a received signal; receiving a recovered clock, wherein a timing of the recovered clock is aligned with a transition of a binary data stream carried by the received signal; establishing a calibrated clock by delaying the recovered clock by a delay controlled by a control code; converting the received signal using a two-bit analog-to-digital converter into two-bit data in accordance with a timing of the calibrated clock; estimating timing of a maximum of a vertical eye opening of the received signal based on statistics of the two-bit data; and adjusting the control code in accordance with a direction of a change of the estimate of the vertical eye opening of the received signal in response to a previous change of the control code. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  shows an exemplary waveform of a prior art clock-data recovery circuit. 
         FIG. 1B  shows another exemplary waveform of a prior art clock-data recovery circuit. 
         FIG. 2  shows a schematic diagram of a clock-data recovery circuit in accordance with an embodiment of the present invention. 
         FIG. 3  shows an exemplary waveform of the clock-data recovery circuit of  FIG. 2 . 
         FIG. 4  shows a flow diagram of a vertical eye monitor circuit within the clock-data recovery circuit of  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention relates to clock-data recovery. While the specification describes several example embodiments of the invention considered as favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention. 
     A schematic diagram of a clock-data recovery circuit  200  in accordance with an embodiment of the present invention is shown in  FIG. 2 . Clock-data recovery circuit  200  receives a received signal S and a recovered clock CK 0 , wherein an edge (e.g., rising edge) of the recovered clock CK 0  is aligned with a transition of a serial binary data stream carried by the received signal S. Clock-data recovery circuit  200  comprises: a variable-delay circuit  220  receiving the recovered clock CK 0  and outputting a calibrated clock CK 1 . The calibrated clock CK 1  comprises the recovered clock CK 0  delayed by a timing controlled by a control code CTL. A 2-bit ADC (analog-to-digital converter)  230  receives the received signal S and outputs 2-bit data D, in accordance with a timing of the calibrated clock CK 1 . A vertical eye monitor circuit  240  receives the 2-bit data D and outputs the control code CTL. The control code CTL is established in a closed-loop manner so that the timing of the calibrated clock CK 1  is aligned with an optimal timing for sampling the received signal S where a vertical eye opening of the received signal S is greatest. The operation of an exemplary embodiment of the present invention is described in paragraphs that follow. 
     An exemplary waveform for the 2-bit ADC  230  of  FIG. 2  is shown in  FIG. 3 . The 2-bit ADC  230  outputs the 2-bit data D by comparing the received signal S with three approximately evenly spaced levels: VR 1 , VR 2 , and VR 3 , in comparators  231 ,  232  and  233 , respectively. VR 2  is approximately equal to a mean of the received signal S, VR 1  is lower than VR 2 , VR 3  is higher than VR 2 , and a difference between VR 2  and VR 1  is approximately equal to a difference between VR 3  and VR 2 . If S is found to be lower than VR 1 , D is set to 0 (00); if S is found to be higher than VR 1  but lower than VR 2 , D is set to 1 (01); if S is found to be higher than VR 2  but lower than VR 3 , D is set to 2 (10); otherwise, D is set to 3 (11). One skilled in the art would understand how to employ a logical processor and/or logic gates to implement the input and outputs described. VR 2  is a level that is known a priori, while the difference between VR 2  and VR 1  (which is approximately equal to the difference between VR 3  and VR 2 ) is set so that a majority of samples of D will be either 0 or 3 when the timing of the calibrated clock CK 1  is close to being optimal. When the timing of the calibrated clock CK 1  is aligned with the optimal timing instant  302  where the vertical eye opening of the received signal S is greatest, the probability of D being 0 or 3 will be maximum. When the timing of the calibrated clock CK 1  is displaced from the optimal timing instant  302 , either pulled earlier (e.g., at timing instant  301 ) or pushed later (e.g., at timing instant  303 ), the probability of D being 0 or 3 will be reduced. Therefore, the probability of D being 0 or 3 can serve as an estimate of the timing of the vertical eye opening at its maximum. The vertical eye monitor circuit  240  uses statistics of D to estimate the vertical eye opening of the received signal S, and adapts the control code CTL accordingly to align the timing of the calibrated clock CK 1  with the optimal timing where the vertical eye opening of the received signal S is maximum and the 2-bit data D is most likely to be assigned a value of either 0 or 3. 
     In an embodiment, the vertical eye monitor circuit  240  is a finite state machine illustrated by the flow diagram  400  of  FIG. 4 . The vertical eye monitor circuit  240  comprises an initialization state  410  and an adaptation state  420 . In the initialization state  410 , the vertical eye monitor circuit  240  goes through the following steps: set CTL to a default value (step  411 ); monitor N samples of the 2-bit data D (where N is an integer that is sufficiently large for a reliable statistics; e.g., N=2 20 ) (step  412 ); record the number of samples of D that are either 0 or 3 to a first internal variable H 1  (step  413 ); and set an internal flag C to 1 (step  414 ). In the adaptation state  420 , the vertical eye monitor circuit  240  goes through the following steps: update the control code CTL in accordance with the internal flag C—increment CTL if C is 1 or else decrement CTL (step  421 ); monitor N samples of the 2-bit data D (step  422 ); record the number of samples of D that are either 0 or 3 to a second internal variable H 2  (step  423 ); update the internal flag C in accordance with a comparison between H 1  and H 2 —keep the internal flag C unchanged if H 2  is greater than H 1  or else reverse the internal flag C (step  424 ); save the value of H 2  into H 1  (step  424 ); and loop back to step  421 . In step  424 , if H 2  is greater than H 1 , it indicates that the previous change of CTL leads to a greater vertical eye opening, and thus the previous change of CTL is in the correct direction and the next change of CTL needs to be in the same direction. Otherwise, if H 2  is not greater than H 1 , this indicates that the previous change of CTL does not lead to a greater vertical eye opening, and thus the previous change of CTL is not in the correct direction and the next change of CTL needs to be in the opposite direction. In this manner, CTL is updated in a closed-loop manner to maximize the number of samples of D that are either 0 or 3, and thus maximize the vertical eye opening. 
     Referring back to  FIG. 2 . The 2-bit ADC  230  comprises: three comparators  231 ,  232 , and  233 , for outputting three binary data D 1 , D 2 , and D 3 , by comparing the received signal S with the three levels VR 1 , VR 2 , and VR 3 , respectively, in accordance with a timing of the calibrated clock CK 1 . An adder  234  outputs the 2-bit data D by adding the three binary data D 1 , D 2 , and D 3 . The 2-bit ADC  230  is often referred to as a two-bit “flash ADC” which is conventionally known to those of ordinary skill in the art and thus not described in detail here. Comparators  231 ,  232 , and  233  can be embodied by comparator circuits that are conventionally known to those of ordinary skill in the art and thus not described in detail here. After the calibrated clock CK 1  is properly established, the binary data D 2  is the recovered data for the serial binary data stream carried by the receive signal. 
     An optional inverter can be placed prior to the input of the delay circuit  220 , embodied by inverter circuits that are conventionally known to those of ordinary skill in the art and thus not described in detail here. 
     The variable delay circuit  220  can be embodied by variable delay circuits that are conventionally known to those of ordinary skill in the art (for instance, a multi-phase delay lock loop, wherein the control code CTL specifies a phase to be tapped), and thus not described in detail here. In an embodiment, an increment of the control code CTL leads to an increase of a delay of the calibrated clock CK 1 , and a decrement of the control code CTL leads to a decrease of the delay of the calibrated clock CK 1 . 
     Note that the timing of the recovered clock CK 0  is approximately aligned with a transition of the serial binary data stream carried by the received signal S; the recovered clock CK 0  can be established by using clock recovery methods that are conventionally known to those of ordinary skill in the art (e.g., using a clock recovery circuit comprising: a binary phase detector, a loop filter, and a voltage-controlled oscillator). As far as the present invention is concerned, the condition is a given and not part of the present invention. 
     In practice, an optimal value of the control code CTL does not change very often during operation. Therefore, the control code CTL does not need to be updated very often. In an embodiment not shown in  FIG. 4  but will be clear to those of ordinary skill in the art simply using written descriptions, the vertical eye monitor circuit  240  can work in an intermittent manner, wherein the vertical eye monitor  240  enters a low-power standby state for a period of time after it exits step  425  and before it loops back to step  421 . During the standby state, the control code CTL is frozen, and the vertical eye monitor circuit  240  is idle to save power. The vertical eye monitor circuit  240  returns to the adaptation state  420  after the period of time expires. In one embodiment, during the period of time when the vertical eye monitor  240  is in the low-power standby state, the 2-bit ADC  230  is also powered down to save power. In another embodiment, during the period of time where the vertical eye monitor circuit  240  is in the low-power standby state, the 2-bit ADC  230  is used for other purposes, for instance, for adapting an equalizer circuit (including a variable gain amplifier) that outputs the received signal S. Using a 2-bit ADC to adapt an adaptive equalizer circuit (including the variable gain amplifier) is known to those of ordinary skill in the art and thus not described in detail here. It is workable to let the adaptive equalizer circuit and the vertical eye monitor circuit  240  take turns using a common 2-bit ADC (i.e. 2-bit ADC  230 ) because neither the adaptive equalizer nor the variable delay circuit  220  needs to be adapted very often. However, it must be noted that, when using the 2-bit ADC  230  for the adaptation of the adaptive equalizer (including the variable gain amplifier), VR 1  needs to be set to a target level of the received signal S for the case when the binary data stream that the received signal S carries is “0” and VR 3  needs to be set to a target level of the received signal S for the case when the binary data stream that the received signal carries is “1.” In other words, the level of VR 1  when the 2-bit ADC  230  is used for the adaptation of the adaptive equalizer is different from the level of VR 1  when the 2-bit ADC  230  is used by the vertical eye monitor circuit  240  for adjusting the timing of the calibrated clock CK 1 . The level of VR 3  when the 2-bit ADC  230  is used for the adaptation of the adaptive equalizer is different from the level of VR 3  when the 2-bit ADC  230  is used by the vertical eye monitor circuit  240  for adjusting the timing of the calibrated clock CK 1 . By way of example but not limitation, VR 1  is set to −200 mV, VR 2  is set to 0V, and VR 3  is set to 200 mV when the 2-bit ADC  230  is used by the vertical eye monitor circuit  240  for adjusting the timing of the calibrated clock CK 1 . VR 1  is set to −300 mV, VR 2  is set to 0V, and VR 3  is set to 300 mV when the 2-bit ADC  230  is used for the adaptation of the adaptive equalizer. Using these settings, the received signal S can be equalized to approximately either −300 mV or 300 mV (depending on whether the serial data stream carried by the received signal is “0” or “1”), and a majority of samples of the received signal S are either below −250 mV or above 250 mV. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the invention should be construed according to the appended claims.

Technology Category: 5