Patent Document

FIELD OF THE INVENTION 
     Summary of the Invention 
     The present invention relates to a method for processing digital signals and to a transmission/reception system that implements said method. 
     The invention is intended mainly, but not exclusively, for receiving and transmitting digital audio and video signals, in particular those involved in the broadcasting of second-generation digital television signals over cable networks. 
     In order to protect the signals from the distortions of the transmission channel, the second-generation system for broadband satellite broadcasting (DVB-S2) utilizes the LDPC (Low Density Parity Check) encoding associated with the QPSK, 8PSK, 16APSK and 32APSK modulations, respectively shown in sequence in  FIG. 1  from top to bottom and from left to right, which are suitable for transmission over a non-linear channel such as the satellite one. A description of the DVB-S2 standard and LDPC codes can be found, for example, in A. Morello, V. Mignone, “DVB-S2: The Second Generation Standard for Satellite Broad-band Services”, Proceedings of the IEEE, Volume 94, Issue 1, Jan. 2006, pages 210-227. 
     For the purpose of better exploiting the potentiality of the codes, the DVB-S2 standard provides that an interleaver is interposed between the LDPC encoder and the 8PSK, 16APSK and 32APSK constellation mapper in order to achieve an improved association between the bits of the encoded word and the bits carried by the constellation points. 
     In the interleaver defined in the DVB-S2 standard, shown in  FIG. 2 , the encoded packet outputted by the LDPC encoder (formed by a number of bits equal to 16,200 or 64,800, which number is generally referred to with the symbol “N FRAME ”) is written by columns in a matrix having N columns, where N is the number of bits carried by the constellation (N is 3 for 8PSK, 4 for 16APSK, 5 for 32APSK), and N FRAME /N rows, and is read by rows; reading takes place from left to right for all code rates provided by the standard, with the exception of the ⅗ rate, where reading takes place from right to left in the case of 8PSK modulation. The association with the constellation points or coordinates takes place as shown in  FIG. 1 . 
     Following the current trend in the broadcasting of second-generation digital terrestrial television signals, it has recently been thought of using the same encoding scheme as that employed in the DVB-S2 standard, i.e. the same LDPC codes, also for the reception and transmission of numerical audio and video signals involved in the broadcasting of second-generation digital television signals over cable networks, however associated with QAM (Quadrature Amplitude Modulation) modulations; in particular, cable network broadcasting utilizes the 1024QAM and 4096QAM modulations ( FIG. 3   b ). 
     The Applicant has realised that, with QAM modulations, the performance offered by the LDPC codes of the DVB-S2 standard are good but not wholly satisfactory as to the signal-to-noise ratio (SNR) required for reaching the QEF (Quasi Error Free) condition; as known, such a condition corresponds to the case wherein less than one error is received per hour of received program. 
     The general object of the present invention is to solve the above-mentioned problem and, in particular, to improve the association between the bits outputted by the LDPC encoder and the constellation coordinates of QAM modulations; more in particular, the present invention deals with the LDPC encoding according to the DVB-S2 standard and with the 1024QAM and 4096QAM modulations. 
     Said objects are achieved through the method for processing digital signals and the transmission/reception system having the features set out in the appended claims, which are intended as an integral part of the present description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will now be described in detail in some of its preferred embodiments, which are provided herein by way of non-limiting example, by referring to the annexed drawings, wherein: 
         FIG. 1  is a schematic representation of the QPSK, 8PSK, 16APSK and 32APSK constellations included, among others, in the DVB-S2 standard; 
         FIG. 2  is an explanatory diagram of an interleaver provided by the DVB-S2 standard, with reference to 8PSK modulation; 
         FIG. 3   a  is a schematic representation of the QPSK, 16QAM, 64QAM and 256QAM constellations applicable to the reception and transmission of audio and video signals involved in the broadcasting of second-generation digital television signals over cable networks; 
         FIG. 3   b  is a schematic representation of the 1024QAM and 4096QAM constellations applicable to the reception and transmission of audio and video signals involved in the broadcasting of second-generation digital television signals over cable networks; 
         FIG. 4  is a much simplified block diagram of a system for processing a modulating digital signal according to the present invention; 
         FIG. 5  is an explanatory general diagram of the interleaver of  FIG. 4 ; 
         FIGS. 6   a  to  6   d  schematically show the function carried out by the “Demux” block of  FIG. 4  according to four preferred embodiments of the present invention relating to 1024QAM modulation; 
         FIGS. 7   a  to  7   d  schematically show the function carried out by the “Demux” block of  FIG. 4  according to four preferred embodiments of the present invention relating to 4096QAM modulation; 
         FIGS. 8   a  to  8   d  show the method used for obtaining the function carried out by the “Demux” block of  FIG. 4  according to the diagram shown in  FIG. 6   a;    
         FIGS. 9   a  to  9   d  show the method used for obtaining the function carried out by the “Demux” block of  FIG. 4  according to the diagram shown in  FIG. 7   a;    
         FIGS. 10   a  to  10   m  show the mapping of the real and imaginary portions of the points of the QPSK, 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM constellations applicable to the reception and transmission of audio and video signals involved in the broadcasting of second-generation digital television signals over cable networks, wherein z q  designates the vector that identifies the constellation point in the complex plane, with a real portion Re(z q ) and an imaginary portion Im(z q ), whereas y i,q  designates the i th  bit of the group of N bits which is mapped to the constellation point identified by z q  (for 4096QAM, for example, N=12 and i=0, 1, 2, . . . , 10, 11). 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to  FIG. 4 , there is shown a much simplified block diagram of a system for processing a modulating digital signal, wherein an “Encoder” block receives a modulating information stream and outputs an encoded information stream organised in packets consisting of N FRAME  bits, which may be either 64,800 or 16,200; the code employed is the LDPC code of the DVB-S2 standard. 
     In an “Interleaver” block, said packets are written into an interleaving matrix having a total size N FRAME ; said matrix is constituted by m×N columns and N FRAME /m×N rows. 
     A “Demux” block carries out a permutation of the bits received from the “Interleaver” block; such bits are received by the interleaving matrix in groups of m×N bits at a time, where N is the number of bits carried by the constellation (N=10 for 1024QAM, N=12 for 4096QAM), and “m” is an integer greater than or equal to 1. The “Demux” block associates them in m groups of N bits and permutes them according to predetermined schemes by taking into account the type of modulation (i.e. the QAM level), the code and the type of transmission channel, and then it outputs them. 
     A “Mapper” block associates the N-ples of bits outputted by the “Demux” block with the points or coordinates of the constellation, e.g. as shown in  FIGS. 3   a  and  3   b  and in  FIGS. 10   a  to  10   m  for QAM modulations. 
     It is worth pointing out that the blocks shown in  FIG. 4  are only those which are essential for understanding the present invention; it should not therefore be excluded the presence of intermediate blocks, e.g. located between the “Demux” block and the “Mapper” block, adapted to perform specific signal processing functions. 
     The present invention proposes particular permutation schemes which may be adopted for the QAM modulations and LDPC codes having different code rates provided, for example, by the DVB-S2 standard in association with different types of interleaving. 
     The preferred embodiment of the present invention refers to the 1024QAM and 4096QAM modulations and to the LDPC code of the DVB-S2 standard. 
     The preferred embodiment of the present invention employs an interleaver which is equal or similar to the one of the DVB-S2 standard as shown in  FIG. 2 , with a number of bits/columns dependent on the QAM modulation level type. 
     The present invention provides for using a matrix interleaver in the form of a matrix having 2×N columns and N FRAME /(2×N) rows, written by columns from top to bottom and read by rows from left to right. In this case, the “Demux” block operates with m equal to 2. 
     For 1024QAM modulation, the 2×N bits inputted to the “Demux” block are permuted as specified in any of  FIGS. 6   a  to  6   d , and are associated with 2 consecutive symbols of 1024QAM modulation. 
     Given the 2×N bits b 0  to b 19 , the 2×N bits carried by the 1024QAM constellation y 0  to y 19  are determined by applying the method described in detail below. 
     A first symbol consists of the bits b 0 , b 2 , b 4 , b 6 , b 8 , b 10 , b 12 , b 14 , b 16 , b 18 , and a second symbol consists of the bits b 1 , b 3 , b 5 , b 7 , b 9 , b 11 , b 13 , b 15 , b 17 , b 19 . Each symbol is mapped individually by arranging the bits first on the in-phase portion (I) from the least significant bit (LSB) to the most significant bit (MSB), and subsequently on the quadrature portion (Q) from the MSB to the LSB, as shown in  FIG. 8   a . I b,1  and Q b,1  respectively designate the arrays of bits associated with the bits I y1  carried by the in-phase component and with the bits Q y1  carried by the quadrature component of the first symbol; I b2 , Q b2 , I y2 , Q y2  have the same meaning for the second symbol. 
     As an alternative, the bits may be associated with the QAM symbols as follows: I y,1 =I b,2 , Q y,1 =Q b,2 , I y,2 =I b,1 , Q y,2 =Q b,1.    
     The bits belonging to the pairs (b 1 ,b 3 ) and (b 11 ,b 19 ) are then exchanged;  FIG. 8   b  will thus be obtained from the example shown in  FIG. 8   a.    
     The two symbols are then interlaced in terms of in-phase and quadrature portions, e.g. as shown in  FIG. 8   c , which is obtained from the example of  FIG. 8   b.    
     As an alternative, the bits may be associated with the QAM symbols as follows: I y,1 =I b,2 , Q y,1 =Q b,1 , I y,2 =I b,1 , Q y,2 =Q b,2 . 
     Afterwards, the bits associated with the even locations y 2 , y 6 , y 10 , y 14 , y 18  or odd locations y 0 , y 4 , y 8 , y 12 , y 16  on the in-phase portion are respectively exchanged with those associated with the even locations y 3 , y 7 , y 11 , y 15 , y 19  or odd locations y 1 , y 5 , y 9 , y 13 , y 17  on the quadrature portion.  FIG. 8   d  will thus be obtained from the example shown in  FIG. 8   c.    
     A first preferred embodiment relating to the 1024QAM constellation is the one listed in  FIG. 8   d  and illustrated in  FIG. 6   a , according to which, given the 2×N bits b 0  to b 19 , the 2×N bits carried by the 1024QAM constellation y 0  to y 19  are determined as follows:
     y 0 =b 8 , y 1 =b 19 , y 2 =b 13 , y 3 =b 6 , y 4 =b 4 , y 5 =b 15 , y 6 =b 17 , y 7 =b 2 , y 8 =b 0 , y 9 =b 11 , y 10 =b 10 , y 11 =b 9 , y 12 =b 7 , y 13 =b 12 , y 14 =b 14 , y 15 =b 5 , y 16 =b 1 , y 17 =b 16 , y 18 =b 18 , y 19 =b 3     where b 0  and y 0  are the most significant bits [MSB], and b 19  and y 19  are the least significant bits [LSB].   

     In particular, the “Mapper” block receives the bits y 0  to y 9  first, followed by the bits y 10  to y 19 . 
     By using the above-mentioned alternatives, three more preferred embodiments can be obtained. 
     The second preferred embodiment is the one shown in  FIG. 6   b , wherein the bits y 0  to y 19  are determined as follows:
     y 0 =b 19 , y 1 =b 8 , y 2 =b 6 , y 3 =b 13 , y 4 =b 15 , y 5 =b 4 , y 6 =b 2 , y 7 =b 17 , y 8 =b 11 , y 9 =b 0 , y 10 =b 9 , y 11 =b 10 , y 12 =b 12 , y 13 =b 7 , y 14 =b 5 , y 15 =b 14 , y 16 =b 16 , y 17 =b 1 , y 18 =b 3 , y 19 =b 18 .   

     The third preferred embodiment is the one shown in  FIG. 6   c , wherein the bits y 0  to y 19  are determined as follows:
     y 0 =b 9 , y 1 =b 10 , y 2 =b 12 , y 3 =b 7 , y 4 =b 5 , y 5 =b 14 , y 6 =b 16 , y 7 =b 1 , y 8 =b 3 , y 9 =b 18 , y 10 =b 19 , y 11 =b 8 , y 12 =b 6 , y 13 =b 13 , y 14 =b 15 , y 15 =b 4 , y 16 =b 2 , y 17 =b 17 , y 18 =b 11 , y 19 =b 0 .   

     The fourth preferred embodiment is the one shown in  FIG. 6   d , wherein the bits y 0  to y 19  are determined as follows:
     y 0 =b 10 , y 1 =b 9 , y 2 =b 7 , y 3 =b 12 , y 4 =b 14 , y 5 =b 5 , y 6 =b 1 , y 7 =b 16 , y 8 =b 18 , y 9 =b 3 , y 10 =b 8 , y 11 =b 19 , y 12 =b 13 , y 13 =b 6 , y 14 =b 4 , y 15 =b 15 , y 16 =b 17 , y 17 =b 2 , y 18 =b 0 , y 19 =b 11 .   

     Still referring to the case wherein the “Demux” block operates with m equal to 2, there are some permutations which have proven to be advantageous for the 4096QAM constellation; the 2×N bits inputted to the “Demux” block are permuted as specified in any of  FIGS. 7   a  to  7   d , for 4096QAM modulation encoded according to the LDPC code of the DVB-S2 standard, and are associated with two consecutive symbols of 4096QAM modulation. The method for obtaining the configurations shown in  FIGS. 7   a  to  7   d  will now be described in detail. 
     Given the 2×N bits b 0  to b 23 , a first symbol consists of the bits b 0 , b 2 , b 4 , b 6 , b 8 , b 10 , b 12 , b 14 , b 16 , b 18 , b 20 , b 22 , and a second symbol consists of the bits b 1 , b 3 , b 5 , b 7 , b 9 , b 11 , b 13 , b 15 , b 17 , b 19 , b 21 , b 23 . Each symbol is mapped individually by arranging the bits first on the in-phase portion (I) from the LSB to the MSB, and subsequently on the quadrature portion (Q) from the MSB to the LSB, as shown in  FIG. 9   a.    
     As an alternative, the bits may be associated with the QAM symbols as follows: I y,1 =I b,2 , Q y,1 =Q b,2 , I y,2 =I b,1 , Q y,2 =Q b,1.    
     The bits belonging to the pairs b 1 , b 3  and b 13 , b 23  are then exchanged;  FIG. 9   b  will thus be obtained from the example shown in  FIG. 9   a.    
     The two symbols are then interlaced in terms of in-phase and quadrature portions; for example, the table of  FIG. 9   c  will thus be obtained from  FIG. 9   b.    
     As an alternative, the bits may be associated with the QAM symbols as follows:
     I y,1 =I b,2 , Q y,1 =Q b,1 , I y,2 =I b,1 , Q y,2 =Q b,2 .   

     Afterwards, the bits associated with the even locations y 2 , y 6 , y 10 , y 14 , y 18 , y 22  or odd locations y 0 , y 4 , y 8 , y 12 , y 16 , y 20  on the in-phase portion are respectively exchanged with those associated with the even locations y 3 , y 7 , y 11 , y 15 , y 19 , y 23  or odd locations y 1 , y 5 , y 9 , y 13 , y 17 , y 21  on the quadrature portion. For example, the table of  FIG. 9   d  will thus be obtained from  FIG. 9   c.    
     A first preferred embodiment relating to the 4096QAM constellation is the one listed in  FIG. 9   d  and illustrated in  FIG. 7   a , according to which, given the 2×N bits b 0  to b 23 , the 2×N bits carried by the 4096QAM constellation y 0  to y 23  are determined as follows:
     y 0 =b 10 , y 1 =b 23 , y 2 =b 15 , y 3 =b 8 , y 4 =b 6 , y 5 =b 17 , y 6 =b 19 , y 7 =b 4 , y 8 =b 2 , y 9 =b 21 , y 10 =b 13 , y 11 =b 0 , y 12 =b 11 , y 13 =b 12 , y 14 =b 14 , y 15 =b 9 , y 16 =b 7 , y 17 =b 16 , y 18 =b 18 , y 19 =b 5 , y 20 =b 1 , y 21 =b 20 , y 22 =b 22 , y 23 =b 3     

     By using the above-mentioned alternatives, three more preferred embodiments can be obtained. The second preferred embodiment is the one shown in  FIG. 7   b , wherein the bits y 0  to y 23  are determined as follows:
     y 0 =b 23 , y 1 =b 10 , y 2 =b 8 , y 3 =b 15 , y 4 =b 17 , y 5 =b 6 , y 6 =b 4 , y 7 =b 19 , y 8 =b 21 , y 9 =b 2 , y 10 =b 0 , y 11 =b 13 , y 12 =b 12 , y 13 =b 11 , y 14 =b 9 , y 15 =b 14 , y 16 =b 16 , y 17 =b 7 , y 18 =b 5 , y 19 =b 18 , y 20 =b 20 , y 21 =b 1 , y 22 =b 3 , y 23 =b 22     

     The third preferred embodiment is the one shown in  FIG. 7   c , wherein the bits y 0  to y 23  are determined as follows:
     y 0 =b 11 , y 1 =b 12 , y 2 =b 14 , y 3 =b 9 , y 4 =b 7 , y 5 =b 16 , y 6 =b 18 , y 7 =b 5 , y 8 =b 1 , y 9 =b 20 , y 10 =b 22 , y 11 =b 3 , y 12 =b 10 , y 13 =b 23 , y 14 =b 15 , y 15 =b 8 , y 16 =b 6 , y 17 =b 17 , y 18 =b 19 , y 19 =b 4 , y 20 =b 2 , y 21 =b 21 , y 22 =b 13 , y 23 =b 0     

     The fourth preferred embodiment is the one shown in  FIG. 7   d , wherein the bits y 0  to y 23  are determined as follows:
     y 0 =b 12 , y 1 =b 11 , y 2 =b 9 , y 3 =b 14 , y 4 =b 16 , y 5 =b 7 , y 6 =b 5 , y 7 =b 18 , y 8 =b 20 , y 9 =b 1 , y 10 =b 3 , y 11 =b 22 , y 12 =b 23 , y 13 =b 10 , y 14 =b 8 , y 15 =b 15 , y 16 =b 17 , y 17 =b 6 , y 18 =b 4 , y 19 =b 19 , y 20 =b 21 , y 21 =b 2 , y 22 =b 0 , y 23 =b 13     

     The above-described methods may be used to advantage in a system for transmitting digital signals based on a 1024QAM or 4096QAM modulator, and particularly in an audio/video digital signal transmitter for broadcasting digital television signals over cable networks. 
     As is apparent to those skilled in the art, if the above-described method is applied in transmission, a reverse method will have to be applied in reception. 
     As known, the transmission of television signals is carried out by radio frequency transmitters, while the reception of television signals occurs through television receivers typically installed in the television service users&#39; homes.

Technology Category: h