Patent Document

BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a circuit for controlling a plurality of devices to boot sequentially. 
         [0003]    2. Description of Related Art 
         [0004]    A reference current of a server system with several devices usually satisfies a working current of each device. However, when the server system is operating, the fact working current is usually less than the reference current, which causes waste of the current. 
         [0005]    Therefore, there is need for improvement in the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views. 
           [0007]      FIG. 1  is a block diagram of an embodiment of a control circuit, wherein the control circuit includes a first switch circuit, a first delay circuit, a second switch circuit, a second delay circuit, and a third switch circuit. 
           [0008]      FIG. 2  is a circuit diagram of the first switch circuit of the control circuit of  FIG. 1 . 
           [0009]      FIG. 3  is circuit diagrams of the first delay circuit and the second switch circuit control circuit of  FIG. 1 . 
           [0010]      FIG. 4  is circuit diagrams of the second delay circuit and the third switch circuit control circuit of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0011]      FIG. 1  is a block diagram of an embodiment of a control circuit  100 . The control circuit  100  is used in a server. The server includes a power supply unit (PSU)  1 , a first device  2 , a second device  3 , and a third device  5 . The PSU  1  provides power to the devices  2 - 5 . The control circuit  100  can be used to boot the devices  2 - 5  in an orderly manner. 
         [0012]    The control circuit  100  includes a first switch circuit  10 , a second switch circuit  12 , a third switch circuit  15 , a first delay circuit  16 , and a second delay circuit  18 . In the embodiment, the first device  2  is a fan, the second device  3  is a hard disk drive, and the third device  5  is a video card with a peripheral component interconnect express (PCIe) interface, but the disclosure is not limited thereto. 
         [0013]    The first switch circuit  10  is connected between the PSU  1  and the first device  2 , and receives a power good signal PWRGD_PS and a first voltage P 12 V from the PSU  1 , and the first voltage P 12 V is transmitted to the first device  2  after receiving the power good signal PWRGD_PS. 
         [0014]    The first delay circuit  16  is connected between the PSU  1  and the second switch circuit  12  and receives the power good signal PWRGD_PS, and a first delay signal PWRGD_PS_DLY is output to the second switch circuit  12 . The second switch circuit  12  is connected between the PSU  1  and the second device  3  and receives the first voltage P 12 V from the PSU  1 , and outputting the first voltage P 12 V to the second device  3  after receiving the first delay signal PWRGD_PS_DLY. 
         [0015]    The second delay circuit  18  is connected between the first delay circuit  16  and the third switch circuit  15 , and receives the first delay signal PWRGD_PS_DLY, and outputs a second delay signal PWRGD_PS_DLY  1  to the third switch circuit  15 . The third switch circuit  15  is connected between the PSU  1  and the third device  5  and receives the first voltage P 12 V from the PSU  1 , and the first voltage P 12 V is output to the third device  5  after receiving the second delay signal PWRGD_PS_DLY  1 . 
         [0016]    In  FIG. 2 , the first switch circuit  10  includes two electronic switches Q 1  and Q 2 , three resistors R 1 -R 3 , and four capacitors C 1 -C 4 . A first end of the electronic switch Q 1  is connected to the PSU  1  through the resistor R 1 , and receives the power good signal PWRGD_PS. The first end of the electronic switch Q 1  is further grounded through the capacitor C 1 . A second end of the electronic switch Q 1  is connected to a first power terminal P 12 V of the PSU  1  through the resistor R 2 , and receives the first voltage P 12 V. A third end of the electronic switch Q 1  is grounded. 
         [0017]    A first end of the electronic switch Q 2  is connected to the second end of the electronic switch Q 1  through the resistor R 3 , and is connected to the first power terminal P 12 V of the PSU  1  through the capacitor C 3 . A second end of the electronic switch Q 2  is connected to the first power terminal P 12 V of the PSU  1 , and receives the first voltage P 12 V, and is grounded through the capacitor C 2 . A third end of the electronic switch Q 2  is connected to the first device  2  and is grounded through the capacitor C 4 . The capacitors C 1 -C 4  filter noise from the first switch circuit  10 . 
         [0018]    In  FIG. 3 , the first delay circuit  16  includes a first delay chip U 1 , six resistors R 10 -R 15 , and three capacitors C 13 -C 15 . A reset pin RESET of the first delay chip U 1  is connected to the second switch circuit  12  through the resistor R 10 , and outputs the first delay signal PWRGD_PS_DLY to the second switch circuit  12 . The reset pin RESET of the first delay chip U 1  is also connected to a second power terminal P 3 V 3  of the PSU  1  through the resistor R 13 , and is grounded through the resistor R 13  and the capacitor C 13  in series. A ground pin GND of the first delay chip U 1  is grounded. A manual reset pin MR of the first delay chip U 1  is connected to the PSU  1  through the resistor R 11 , and receives the power good signal PWRGD_PS. The manual reset pin MR of the first delay chip U 1  is also connected to the second power terminal P 3 V 3  of the PSU  1  through the resistor R 12 , and receives a second voltage P 3 V 3 . A set pin CT of the first delay chip U 1  is grounded through the capacitor C 14 . A sense pin SENSE of the first delay chip U 1  is grounded through the capacitor C 15 . The second power terminal P 3 V 3  of the PSU  1  is grounded through the resistors R 14  and R 15  in series. A node between the resistors R 14  and R 15  is connected to the sense pin SENSE of the first delay chip U 1 . 
         [0019]    The second switch circuit  12  includes two electronic switches Q 3  and Q 4 , three resistors R 4 -R 6 , and four capacitors C 5 -C 8 . A first end of the electronic switch Q 3  is connected to the first delay circuit  16  through the resistor R 4  and receives the first delay signal PWRGD_PS_DLY. The first end of the electronic switch Q 3  is also grounded through the capacitor C 5 . A second end of the electronic switch Q 3  is connected to the first power terminal P 12 V of the PSU  1  through the resistor R 5 , and receives the first voltage P 12 V. A third end of the electronic switch Q 3  is grounded. 
         [0020]    A first end of the electronic switch Q 4  is connected to the second end of the electronic switch Q 3  through the resistor R 6 , and is connected to the first power terminal P 12 V of the PSU  1  through the capacitor C 7 . A second end of the electronic switch Q 4  is connected to the first power terminal P 12 V of the PSU  1 , and receives the first voltage P 12 V, and is grounded through the capacitor C 6 . A third end of the electronic switch Q 4  is connected to the second device  3  and is grounded through the capacitor C 8 . The capacitors C 5 -C 8  filter noise from the second switch circuit  12 . 
         [0021]    In  FIG. 4 , the second delay circuit  18  includes a second delay chip U 2 , six resistors R 16 -R 21 , and three capacitors C 16 -C 18 . A reset pin RESET of the second delay chip U 2  is connected to the third switch circuit  15  through the resistor R 16 , and outputs the second delay signal PWRGD_PS_DLY 1  to the third switch circuit  15 . The reset pin RESET of the second delay chip U 2  is also connected to the second power terminal P 3 V 3  of the PSU  1  through the resistor R 19 , and is grounded through the resistor R 19  and the capacitor C 16  in series. A ground pin GND of the second delay chip U 2  is grounded. A manual reset pin MR of the second delay chip U 2  is connected to the first delay circuit  16  through the resistor R 17 , and receives the first delay signal PWRGD_PS_DLY. The manual reset pin MR of the second delay chip U 2  is also connected to the second power terminal P 3 V 3  of the PSU  1  through the resistor R 18 , and receives the second voltage P 3 V 3 . A set pin CT of the second delay chip U 2  is grounded through the capacitor C 17 . A sense pin SENSE of the second delay chip U 2  is grounded through the capacitor C 18 . The second power terminal P 3 V 3  of the PSU  1  is grounded through the resistors R 20  and R 21  in series. A node between the resistors R 20  and R 21  is connected to the sense pin SENSE of the second delay chip U 2 . 
         [0022]    The third switch circuit  15  includes two electronic switches Q 5  and Q 6 , three resistors R 7 -R 9 , and four capacitors C 9 -C 12 . A first end of the electronic switch Q 5  is connected to the second delay circuit  18  through the resistor R 7 , and receives the second delay signal PWRGD_PS_DLY 1 . The first end of the electronic switch Q 5  is also grounded through the capacitor C 9 . A second end of the electronic switch Q 5  is connected to the first power terminal P 12 V of the PSU  1  through the resistor R 8 , and receives the first voltage P 12 V. A third end of the electronic switch Q 5  is grounded. 
         [0023]    A first end of the electronic switch Q 6  is connected to the second end of the electronic switch Q 5  through the resistor R 9 , and is connected to the first power terminal P 12 V of the PSU  1  through the capacitor C 11 . A second end of the electronic switch Q 6  is connected to the first power terminal P 12 V of the PSU  1 , and receives the first voltage P 12 V, and is grounded through the capacitor C 10 . A third end of the electronic switch Q 6  is connected to the third device  5 , and is grounded through the capacitor C 12 . The capacitors C 9 -C 12  filter noise from the third switch circuit  15 . 
         [0024]    In use, the PSU  1  outputs the power good signal PWRGD_PS to the first switch circuit  10  and the first delay circuit  16 . When the first switch circuit  10  receives the power good signal PWRGD_PS, the electronic switches Q 1  and Q 2  are turned on. Therefore, the first voltage P 12 V of the PSU  1  is outputted to the first device  2  for booting the first device  2 . 
         [0025]    When the first delay circuit  16  receives the power good signal PWRGD P_S, the reset pin RESET of the first delay chip U 1  outputs the first delay signal PWRGD_PS_DLY to the second switch circuit  12  and the second delay circuit  18  after a first delay time set beforehand in the first delay chip U 1 . When the second switch circuit  12  receives the first delay signal PWRGD_PS_DLY, the electronic switches Q 3  and Q 4  are turned on. Therefore, the first voltage P 12 V of the PSU  1  is outputted to the second device  3  for booting the second device  3 . 
         [0026]    When the second delay circuit  18  receives the first delay signal PWRGD_PS_DLY, the reset pin RESET of the second delay chip U 2  outputs the second delay signal PWRGD_PS_DLY  1  to the third switch circuit  15  after a second delay time set beforehand in the second delay chip U 2 . 
         [0027]    The electronic switches Q 5  and Q 6  are turned on. The first voltage P 12 V of the PSU  1  is outputted to the third device  5  for booting the third device  5 . 
         [0028]    In the embodiment, the electronic switches Q 1 -Q 6  are metal oxide semiconductor field-effect transistors (MOSFETs). The electronic switches Q 1 , Q 3 , and Q 5  are n-channel MOSFETs. The electronic switches Q 2 , Q 4 , and Q 6  are p-channel MOSFETs. The first, second, and third ends of each electronic switch respectively correspond to a gate, a drain, and a source of each MOSFET. 
         [0029]    While the disclosure has been described by way of example and in terms of preferred embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Technology Category: 4