Patent Document

BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a current output circuit in which an amount of current is adjusted through zapping.  
           [0003]    2. Description of the Related Art  
           [0004]    In many cases, the manufacture of various circuits requires a final adjustment process. In particular, in semiconductor integrated circuits or the like, variations among elements cannot be completely eliminated, and thus, a product requires adjustment of characteristics after the completion of manufacture.  
           [0005]    Various methods are employed for this final adjustment, including adjustment of an amount of current within an internal circuit through zapping. In this zapping process, for example, a zapping terminal to which a zapping diode is connected is provided and a predetermined voltage is applied to the zapping terminal to induce breakdown of the zapping diode. Provision of a transistor which is switched on and off by the zapping diode enables adjustment of an amount of current of a constant current source or the like within an internal circuit.  
           [0006]    A zapping circuit described above is embodied by various circuits, including a structure disclosed in Japanese Patent Laid-Open Publication No. 2002-261243.  
           [0007]    In many transistors which are switched on and off through zapping, an amount of current flowing through the transistor when the transistor is switched on is an adjustment current that is added to or reduced from a reference current. For example, in the above-identified Japanese Patent Laid-Open Publication No. 2002-261243, ON/OFF states of a plurality of adjustment current transistors are controlled in order to control the overall amount of current. Therefore, the amount of current flowing through the adjustment current transistor when the transistor is ON is an important parameter.  
           [0008]    In conventional devices, the transistor for inducing flow of the adjustment current is generally connected in series to a resistance, and the magnitude of the adjustment current flowing through the transistor is set by the magnitude of the resistance. However, because the adjustment current transistor is generally switched fully on, Vce becomes small and the transistor becomes saturated. Therefore, the magnitude of the adjustment current is affected not only by the resistance of the resistor, but also by the ON-resistance (emitter resistance) of the adjustment current transistor. The ON-resistances of saturated transistors are significantly affected by variations among transistors, raising a problem that the adjustment currents vary. In addition, the ON-resistance of a transistor has temperature characteristics, and compensation of these characteristics has been difficult.  
         SUMMARY OF THE INVENTION  
         [0009]    According to one aspect of the present invention, a transistor for determining the magnitude of current (hereinafter called a “current-determining transistor”) is diode-connected. Therefore, when current flows through the current-determining transistor, the voltage drop at the transistor is Vbe. Therefore, a constant current can flow stably without dependence on the ON-resistance of the transistor.  
           [0010]    According to another aspect of the present invention, the temperature characteristics of the current-determining transistor can be easily compensated by inserting a diode in a reference power supply for supplying a reference voltage. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is a diagram showing a circuit according to a preferred embodiment of the present invention.  
         [0012]    [0012]FIG. 2 is a diagram showing a circuit according to another preferred embodiment of the present invention. 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0013]    Preferred embodiments of the present invention (hereinafter may be referred to as simply “embodiments”) will now be described with reference to the drawings.  
         [0014]    [0014]FIG. 1 is a circuit diagram showing a structure of a preferred embodiment of the present invention.  
         [0015]    In the present specification, the words “zapping diode” mean “Zener diode for use of zapping.” A resistance of a zapping diode (=Zener diode) becomes 0 by zapping and function of the Zener diode will not be recovered.  
         [0016]    A reference power supply  10  is a circuit which outputs a reference voltage. In the preferred embodiment, the reference power supply  10  comprises a serially connected structure consisting of a resistor R 01 , a diode D 1 , and a resistor R 02 , arranged between a predetermined power supply Vreg and the ground. A voltage at the upper side (anode side) of the diode D 1  is determined from the voltage of the power supply Vreg, a voltage drop at the diode D 1  (1Vbe), and resistance values of the resistors R 01  and R 02 . The determined anode-side voltage is output as a reference voltage. Therefore, the temperature characteristics of 1Vbe at the diode D 1  are imparted to the reference voltage.  
         [0017]    The reference voltage is input to a positive input terminal of an operational amplifier OP 1 . This operational amplifier OP 1  is a buffer amplifier in which an output terminal is connected (or short-circuited) to a negative input terminal. Therefore, a reference voltage is stably output on the output of the operational amplifier OP 1 .  
         [0018]    Collectors of two NPN-type transistors Q 1  and Q 2  each having an emitter connected to the ground are connected to the output of the operational amplifier OP 1  via a resistor R 1 . A base and a collector of transistor Q 2  are connected (diode connection) to each other, and a base of an NPN-type transistor Q 3  having an emitter connected to the ground is connected to the base of the transistor Q 2 . Therefore, the transistors Q 2  and Q 3  form a current mirror. An adjustment current  11  having a magnitude of a voltage which is reduced by 1Vbe from the reference voltage divided by the resistance of the resistor R 1  flows through the transistor Q 2 , and a current having the same magnitude flows through the transistor Q 3 .  
         [0019]    In the illustrated structure, two circuits having the same structure as the circuit comprising the resistor R 1  and the transistors Q 1 , Q 2 , and Q 3  are additionally provided on the output of the operational amplifier OP 1 . That is, a circuit comprising a resistor R 2  and transistors Q 4 , Q 5 , and Q 6 , and a circuit comprising a resistor R 3  and transistors Q 7 , Q 8 , and Q 9  are provided. Similar to the case of the first circuit, an adjustment current  12  which is determined by the resistor R 2  flows through the transistor Q 6 , and an adjustment current  13  which is determined by the resistor R 3  flows through the transistor Q 9 .  
         [0020]    The collectors of the transistors Q 3 , Q 6 , and Q 9  are commonly connected to a collector of a PNP-type transistor Q 10 , which has an emitter connected to the power supply Vreg via a resistance, and a base and a collector which are mutually connected. Therefore, a current which is obtained by adding the adjustment currents flowing through the transistors Q 3 , Q 6 , and Q 9  flows through the transistor Q 10 . A base of a PNP-type transistor Q 11  which has an emitter connected to the power supply Vreg via a resistor is connected to a base of the transistor Q 10 . A collector of the transistor Q 11  constitutes a current output terminal.  
         [0021]    Thus, the transistors Q 10  and Q 11  form a current mirror, and a reference current identical with a reference current flowing through the reference transistor, the transistor Q 10 , flows through the transistor Q 11  and is output. Provision of a plurality of transistors which are connected to the transistor Q 10  to form current mirrors enables these transistors to also output reference currents. By changing the area of the emitter of the output transistor, the magnitude of the current to be output can be changed to various different values.  
         [0022]    A connection point between resistors R 12  and R 13  among three serially connected resistors R 11 , R 12 , and R 13  connected between the power supply Vreg and the ground is connected to the base of the transistor Q 1 . The resistance values of the resistors R 11 , R 12 , and R 13  are set so that the voltage of the connection point between the resistors R 12  and R 13  is sufficient to allow the transistor Q 1  to be switched on. In addition, a cathode of a zapping diode ZD 1  having an anode connected to the ground and a zapping terminal PD 1  are connected to a connection point between the resistors R 11  and R 12  among the three serially connected resistors R 11 , R 12 , and R 13 .  
         [0023]    Similarly, circuits identical with that connected to the base of the transistor Q 1  are respectively connected to the bases of the transistors Q 4  and Q 7 . That is, a resistance divider circuit comprising resistors R 21 , R 22 , and R 23 , and a zapping diode ZD 2  and a zapping terminal PD 2  which are connected to the resistance divider circuit are connected to the base of the transistor Q 4 , and a resistance divider circuit comprising resistors R 31 , R 32 , and R 33 , and a zapping diode ZD 3  and a zapping terminal PD 3  which are connected to the resistance divider circuit are connected to the base of the transistor Q 7 .  
         [0024]    Before zapping by the zapping terminals PD 1 , PD 2 , and PD 3  occurs, the zapping diodes (Zener diode) ZD 1 , ZD 2 , and ZD 3  are functioning and the voltage on the cathode side is maintained. Thus, the transistors Q 1 , Q 4 , and Q 7  are in an ON state. These transistors Q 1 , Q 4 , and Q 7  are configured such that when these transistors are ON, current flows through these transistors in place of the transistors Q 2 , Q 5 , and Q 8 , and no current flows through the transistors Q 2 , Q 5 , and Q 8 . Therefore, no current flows through the transistors Q 2 , Q 3 , Q 5 , Q 6 , Q 8 , and Q 9 , and adjustment currents become I 1 =I 2 =I 3 =0. Thus, total adjustment current is 0 and no current flows through the transistors Q 10  and Q 11 . Therefore, the output current from the zapping circuit is 0.  
         [0025]    In this circuit, by individually applying, to the zapping terminals PD 1 , PD 2 , and PD 3 , a voltage which is sufficient for the zapping diodes ZD 1 , ZD 2 , and ZD 3  to attain destructive breakdown (break), the zapping diodes ZD 1 , ZD 2 , and ZD 3  can attain break independently. When the zapping diode ZD 1 , ZD 2 , or ZD 3  is broken, the zapping terminal PD 1 , PD 2 , or PD 3  is connected to the ground.  
         [0026]    For example, when a predetermined voltage is applied to the zapping terminal PD 1  to induce break of the zapping diode ZD 1 , the base of the transistor Q 1  is connected to the ground and the transistor Q 1  is switched off. When the transistor Q 1  is switched off, adjustment current I 1  flows through the transistor Q 2 , causing the adjustment current I 1  to also flow through the transistors Q 3 , Q 10 , and Q 11 .  
         [0027]    Similarly, when zapping is performed by the zapping terminal PD 2 , the adjustment current  12  flows through the transistors Q 5 , Q 6 , Q 10 , and Q 11 , and when zapping is performed by the zapping terminal PD 3 , the adjustment current  13  flows through the transistors Q 8 , Q 9 , Q 10 , and Q 11 . Therefore, through zapping, the current in the transistor Q 11  can be set to 8 different values: 0, I 1 , I 2 , I 3 , I 1 +I 2 , I 2 +I 3 , I 3 +I 1 , and I 1 +I 2 +I 3 . By setting, for example, the adjustment currents I 1 ,  12 , and I 3  at a ratio of 1:2:4, 8 different currents from 0 to 7 can be obtained.  
         [0028]    By changing an emitter area ratio in each of pairs of transistors (Q 1 , Q 2 ), (Q 4 , Q 5 ), and (Q 7 , Q 8 ) forming a current mirror, the adjustment currents I 1 , I 2 , and I 3  can be changed independently. In addition, by changing the resistance values of the resistors R 1 , R 2 , and R 3 , the adjustment currents I 1 ,  12 , and  13  can be changed independently.  
         [0029]    In this configuration, when the transistor Q 1 , Q 4 , or Q 7  is ON, no corresponding adjustment current flows. Therefore, the adjustment current can be set without consideration of the ON-resistances of these transistors Q 1 , Q 4 , and Q 7 . On the other hand, when the transistor Q 1 , Q 4 , or Q 7  is OFF, current flows through the transistor Q 2 , Q 5 , or Q 8 . However, as described above, in each of the transistors Q 2 , Q 5 , and Q 8 , the collector and base are mutually connected, and, thus, the voltage drop is constant, at 1Vbe. Therefore, the adjustment currents I 1 , I 2 , and I 3  when zapping is performed depend respectively on resistors R 1 , R 2 , and R 3 , but do not depend on the ON-resistances of the transistors Q 2 , Q 5 , and Q 8 . The adjustment currents I 1 , I 2 , and I 3  are therefore less affected by variations in the transistors. In addition, although the adjustment currents I 1 , I 2 , and I 3  are affected respectively by the temperature characteristics of Vbe of the transistors Q 1 , Q 4 , and Q 7 , the reference voltage from the reference power supply  10  is also affected by the temperature characteristics of Vbe of the diode D 1 , in such a manner that the temperature characteristics are cancelled out. Therefore, the present embodiment has an advantage in that the adjustment currents I 1 , I 2 , and I 3  are basically unaffected by the temperature characteristics of transistors.  
         [0030]    In the above-described embodiment, the transistors for adjustment current, Q 2 , Q 3 , Q 5 , Q 6 , Q 8 , and Q 9 , are described as being NPN transistors. However, PNP transistors can be employed in place of the NPN transistors. FIG. 2 shows an example circuit structure in this case.  
         [0031]    The structures of zapping terminals PD 1 , PD 2 , and PD 3 , zapping diodes ZD 1 , ZD 2 , and ZD 3  connected to the zapping terminals, and resistors R 1 , R 12 , R 13 , R 21 , R 22 , R 23 , R 31 , R 32 , and R 33  are identical with those in the above-described case. The circuits for switching on and off three adjustment currents are identical with each other, and thus, only one of these circuits will be described.  
         [0032]    A connection point between the resistors R 12  and R 13  is connected to a base of an NPN-type transistor Q 21 . An emitter of the transistor Q 21  is connected to the ground, and a collector of the transistor Q 21  is connected to a power supply Vreg via two resistors. A connection point between the two resistors is connected to a base of a PNP-type transistor Q 22 . An emitter of the transistor Q 22  is connected to the power supply Vreg, and a collector of the transistor Q 22  is connected to a collector of a PNP-type transistor Q 23 , which has an emitter connected to the power supply Vreg. The collector and a base of the transistor Q 23  are mutually connected, and the base of the transistor Q 23  is connected to a base of a transistor Q 24 . An emitter of the transistor Q 24  is connected to the power supply Vreg, and the transistors Q 23  and Q 24  form a current mirror.  
         [0033]    An output of an operational amplifier OP 1  having its output terminal and its negative input terminal mutually connected is connected to the collectors of the transistors Q 22  and Q 23  via a resistor R 1 . A reference power supply  12  is connected to a positive input terminal of the operational amplifier OP 1 . The reference power supply  12  is similar to the reference power supply  10 , in that the reference power supply  12  comprises a serial connection consisting of a resistor R 01 , a diode D 1 , and a resistor R 02  between the power supply Vreg and the ground. The reference power supply  12  differs from the reference power supply  10  in that the cathode (lower side) of the diode D 1  is connected to the positive input terminal of the operational amplifier OP 1 .  
         [0034]    A collector of the transistor Q 24  is connected to a collector of an NPN-type transistor Q 25 , which has its emitter connected to the ground and its collector and base mutually connected. A base of a transistor Q 26  having its emitter connected to the ground is connected to the base of the transistor Q 25 .  
         [0035]    As illustrated in FIG. 4, resistors are preferably inserted between emitters of transistors Q 25  and Q 26  and the ground.  
         [0036]    Therefore, when zapping is not performed, the transistor Q 21  is switched on and the transistor Q 22  is switched on, causing the transistors Q 23  and Q 24  to be switched off, and no adjustment current flows. When, on the other hand, zapping is performed, the transistor Q 21  is switched off and the transistor Q 22  is switched off, causing the transistors Q 23  and Q 24  to be switched on and the adjustment current to flow. In this structure also, when the transistor Q 23  is ON, Vce is fixed to Vce=Vbe, and thus, this circuit is not affected by the ON-resistance of the transistor Q 23 . The temperature characteristics of the transistor Q 22  are compensated by the temperature characteristics of the diode D 1 .  
         [0037]    In this manner, in this circuit, adjustment current having a stable current value can be adjusted. A current adjusted by zapping can be used in various circuits. For example, the adjusted current maybe used as a current for adjusting a center frequency in a band-pass filter.

Technology Category: g