Patent Document

CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation application of U.S. patent application Ser. No. 13/052,115, filed on Mar. 21, 2011, and all benefits of such earlier application are hereby claimed for this new continuation application. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a semiconductor device, and more particularly, to a semiconductor device with metal gate and method for fabricating the same. 
     2. Description of the Prior Art 
     With a trend towards scaling down size of the semiconductor device, conventional methods, which are used to achieve optimization, such as reducing thickness of the gate dielectric layer, for example the thickness of silicon dioxide layer, have faced problems such as leakage current due to tunneling effect. In order to keep progression to next generation, high-K materials are used to replace the conventional silicon oxide to be the gate dielectric layer because it decreases physical limit thickness effectively, reduces leakage current, and obtains equivalent capacitor in an identical equivalent oxide thickness (EOT). 
     On the other hand, the conventional polysilicon gate also has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Thus work function metals are developed to replace the conventional polysilicon gate to be the control electrode that competent to the high-K gate dielectric layer. 
     However, there is always a continuing need in the semiconductor processing art to develop semiconductor device renders superior performance and reliability even though the conventional silicon dioxide or silicon oxynitride gate dielectric layer is replaced by the high-K gate dielectric layer and the conventional polysilicon gate is replaced by the metal gate. 
     SUMMARY OF THE INVENTION 
     It is an objective of the present invention to provide a semiconductor device with metal gate and method for fabricating the same. 
     According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer; and a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer. 
     According to another aspect of the present invention, a method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate, wherein the gate structure comprises a high-k dielectric layer; forming a first seal layer on a sidewall of the gate structure; and forming a lightly doped drain in the substrate adjacent to two sides of the gate structure. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-6  illustrate a method for fabricating a semiconductor device having metal gate. 
         FIGS. 7-12  illustrate a method for fabricating a semiconductor device having metal gate according to another embodiment of the present invention. 
         FIG. 13  illustrates a semiconductor device having metal gate according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIGS. 1-6 ,  FIGS. 1-6  illustrate a method for fabricating a semiconductor device having metal gate, in which the method preferably conducts a gate-first approach accompanying a high-k first fabrication. As shown in  FIG. 1 , a substrate  100 , such as a silicon substrate or a silicon-in-insulator (SOI) substrate is provided. A plurality of shallow trench isolations (STI)  102  used for electrical isolation is also formed in the substrate  100 . 
     Next, a gate insulating layer  104  composed of oxide or nitride is formed on the surface of the substrate  100 , in which the gate insulating layer  104  is preferably used as an interfacial layer. Next, a stacked film composed of a high-k dielectric layer  106 , a polysilicon layer  108 , and a hard mask  110  is formed on the gate insulating layer  104 . The polysilicon layer  108  is preferably used as a sacrificial layer, which could be composed of undoped polysilicon, polysilicon having n+ dopants, or amorphous polysilicon material. 
     The high-k dielectric layer  106  could be a single-layer or a multi-layer structure containing metal oxide layer such as rare earth metal oxide, in which the dielectric constant of the high-k dielectric layer  106  is substantially greater than  20 . For example, the high-k dielectric layer  106  could be selected from a group consisting of hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO), tantalum oxide, Ta 2 O 3 , zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), strontium bismuth tantalite (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), and barium strontium titanate (Ba x Sr 1-x TiO 3 , BST). The hard mask  110  could be composed of SiO 2 , SiN, SiC, or SiON. 
     Next, as shown in  FIG. 2 , a patterned photoresist (not shown) is formed on the hard mask  110 , and a pattern transfer is performed by using the patterned photoresist as mask to partially remove the hard mask  110 , the polysilicon layer  108 , the high-k dielectric layer  106 , and the gate insulating layer  104  through single or multiple etching processes. After stripping the patterned photoresist, a gate structure  112  is formed on the substrate  100 . 
     Next, a first seal layer  114  composed of silicon nitride is formed on the sidewall surface of the gate structure  112  and the surface of the substrate  100 , and a lightly doped ion implantation is carried out to implant n-type or p-type dopants into the substrate  100  adjacent to two sides of the gate structure  112  for forming a lightly doped drain  116 . 
     As shown in  FIG. 3 , a second seal layer  118  composed of silicon oxide and a third seal layer  120  composed of silicon nitride are sequentially formed on the substrate  100  and covering the gate structure  112  and the first seal layer  114 . In this embodiment, the second seal layer  118  is preferably composed of silicon oxide and thus having a different etching rate with respect to the first seal layer  114  underneath. 
     Next, as shown in  FIG. 4 , a dry etching process is performed to partially remove the third seal layer  120  and stop on the surface of the second seal layer  118 , another dry etching is carried out to partially remove the second seal layer  118  and the first seal layer  114 , and a wet etching process is performed to remove remaining polymers from the above etching process for forming a first spacer  122  composed of L-shaped first seal layer, an L-shaped second seal layer  118 , and a second spacer  124  composed of the remaining third seal layer  120  on the sidewall of the gate structure  112 . 
     In an alternative approach to the above steps, another embodiment of the present invention could also perform a dry etching process to partially remove the third seal layer  120  and stop on the surface of the second seal layer  118 , perform another dry etching process to partially remove the third seal layer  118 , and perform a wet etching process to partially remove the first seal layer  114  for forming the above L-shaped first spacer  122 , the L-shaped second seal layer  118 , and the second spacer  124 . 
     Next, an ion implantation process is performed to implant n-type or p-type dopants into the substrate  100  adjacent to two sides of the aforementioned spacer for forming a source/drain region  126 . In this embodiment, a selective strain scheme (SSS) can be used for forming the source/drain region  126 . For example, a selective epitaxial growth (SEG) can be used to form the source/drain region  126 , such that when the source/drain region  126  is a p-type source/drain, epitaxial silicon layers with silicon germanium (SiGe) can be used to form the p-type source/drain region  126 , whereas when the source/drain region  126  is an n-type source/drain region  126 , epitaxial silicon layers with silicon carbide (SiC) can be used to form the n-type source/drain region  126 . Additionally, silicides (not shown) are formed on the surface of the source/drain region  126 . Thereafter, a contact etch stop layer (CESL)  128  and an inter-layer dielectric (ILD)  130  layer are sequentially formed on the substrate  100 . Since the steps of forming the above mentioned elements are well-known to those skilled in the art, the details of which are omitted herein for the sake of brevity. 
     As shown in  FIG. 5 , a planarizing process, such as a chemical mechanical polishing (CMP) is conducted to partially remove the ILD layer  130 , the CESL  128 , and the patterned hard mask  110  until exposing the polysilicon layer  108 . Another adequate etching process could then be carried to remove the polysilicon layer  108  to form a trench  132 . During this step, the high-k dielectric layer  106  could be used as an etching stop layer to protect the gate insulating layer  104  underneath from the etching process conducted previously. As the aforementioned planarizing process and etching process are well known to those skilled in the art, the details of which are omitted herein for the sake of brevity. 
     Next, as shown in  FIG. 6 , a work function metal layer  134 , a barrier layer  136 , and a low resistance metal layer  138  are formed sequentially to fill the trench  132 , in which the work functional metal layer  134  could include a p-type work function metal or an n-type work functional metal. A planarizing process is conducted thereafter to partially remove the low resistance metal layer  138 , the barrier layer  136 , and work function metal layer  134  for completing the fabrication of a semiconductor device having metal gate  140 . 
     Referring to  FIGS. 7-12 ,  FIGS. 7-12  illustrate a method for fabricating a semiconductor device having metal gate according to another embodiment of the present invention, in which this embodiment also employs a gate-first fabrication with a high-k first process. 
     As shown in  FIG. 7 , a substrate  200 , such as a silicon substrate or a silicon-in-insulator (SOI) substrate is provided. A plurality of shallow trench isolations (STI)  202  used for electrical isolation is also formed in the substrate  200 . 
     Next, a gate insulating layer  204  composed of oxide or nitride is formed on the surface of the substrate  200 , in which the gate insulating layer  204  is preferably used as an interfacial layer. Next, a stacked film composed of a high-k dielectric layer  206 , a polysilicon layer  208 , and a hard mask  210  is formed on the gate insulating layer  204 . The polysilicon layer  208  is preferably used as a sacrificial layer, which could be composed of undoped polysilicon, polysilicon having n+ dopants, or amorphous polysilicon material. 
     Next, as shown in  FIG. 8 , a patterned photoresist (not shown) is formed on the hard mask  210 , and a pattern transfer is performed by using the patterned photoresist as mask to partially remove the hard mask  210 , the polysilicon layer  208 , the high-k dielectric layer  206 , and the gate insulating layer  204  through single or multiple etching processes. After stripping the patterned photoresist, a gate structure  212  is formed on the substrate  200 . 
     Next, a first seal layer (not shown) composed of silicon nitride is formed on the sidewall surface of the gate structure  212  and the surface of the substrate  200 , and an etching back process performed to partially remove the first seal layer on the substrate  200  for forming a first spacer  214  on the sidewall of the gate structure  212 . Next, a lightly doped ion implantation is carried out to implant n-type or p-type dopants into the substrate  200  adjacent to two sides of the gate structure  212  for forming a lightly doped drain  216 . A second seal layer  218  composed of silicon oxide is then covered on the gate structure  212 , the first spacer  214 , and the surface of the substrate  200 . 
     As shown in  FIG. 9 , a third seal layer  220  composed of silicon nitride is formed on the substrate  200  and covering the gate structure  212  and the second seal layer  218 . In this embodiment, the second seal layer  218  is preferably composed of silicon oxide and thus having a different etching rate with respect to the third seal layer  220  above. 
     As shown in  FIG. 10 , a dry etching process is performed to partially remove the third seal layer  220  and stop on the surface of the second seal layer  218 , and a wet etching process is performed to partially remove the second seal layer  218  for forming a first spacer  214 , an L-shaped second seal layer  218 , and a second spacer  222  on the sidewall of the gate structure  212 . 
     Next, an ion implantation process is performed to implant n-type or p-type dopants into the substrate  200  adjacent to two sides of the aforementioned spacer for forming a source/drain region  226 . In this embodiment, a selective strain scheme (SSS) can be employed for forming the source/drain region  226 . For example, a selective epitaxial growth (SEG) can be used to form the source/drain region  226 , such that when the source/drain region  226  is a p-type source/drain, epitaxial silicon layers with silicon germanium (SiGe) can be used to form the p-type source/drain region  226 , whereas when the source/drain region  226  is an n-type source/drain region  226 , epitaxial silicon layers with silicon carbide (SiC) can be used to form the n-type source/drain region  226 . Additionally, silicides (not shown) are formed on the surface of the source/drain region  226 . Thereafter, a contact etch stop layer (CESL)  228  and an inter-layer dielectric (ILD)  230  layer are sequentially formed on the substrate  200 . Since the steps of forming the above mentioned elements are well-known to those skilled in the art, the details of which are omitted herein for the sake of brevity. 
     As shown in  FIG. 11 , a planarizing process, such as a chemical mechanical polishing (CMP) is conducted to partially remove the ILD layer  230 , the CESL  228 , and the hard mask  210  until exposing the polysilicon layer  208 . Another adequate etching process could then be carried to remove the polysilicon layer  208  to form a trench  232 . In this step, the high-k dielectric layer  206  could be served as an etching stop layer to protect the gate insulating layer  204  underneath from the etching process conducted previously. As the aforementioned planarizing process and etching process are well known to those skilled in the art, the details of which are omitted herein for the sake of brevity. 
     Next, as shown in  FIG. 12 , a work function metal layer  234 , a barrier layer  236 , and a low resistance metal layer  238  are formed sequentially to fill the trench  232 , in which the work functional metal layer  234  could include a p-type work function metal or an n-type work functional metal. A planarizing process is conducted thereafter to partially remove the low resistance metal layer  238 , the barrier layer  236 , and work function metal layer  234  for completing the fabrication of a semiconductor device having metal gate  240 . 
     Overall, the present invention preferably forms an oxygen-free seal layer on the sidewall of the gate structure to protect the high-k dielectric layer in the gate structure before a lightly doped drain is formed. According to a preferred embodiment of the present invention, the oxygen-free seal layer is preferably composed of silicon nitride, and is adhered and contacting the hard mask, the polysilicon layer, the high-k dielectric layer, and gate insulating layer of the gate structure. As no material layer is formed on the sidewall of the gate structure for protecting the high-k dielectric layer before the formation of lightly doped drain in conventional art, the high-k dielectric layer is often damaged or removed during later processes including the wet cleaning conducted for lightly doped drain, oxide stripping, or spacer removal. By forming an oxygen-free seal layer on the sidewall of the gate structure before forming the lightly doped drain, the present invention could avoid the aforementioned problem found in conventional art and prevent the high-k dielectric layer from damage effectively. 
     It should be noted that despite the aforementioned embodiment employs a gate-first and h-k first approach, the fabrication process of the present invention could also be applied to gate-first fabrication and high-k last fabrication, which are all within the scope of the present invention. For instance, the gate structure of the gate-first process preferably includes a gate insulating layer, a high-k dielectric layer disposed on the gate insulating layer and a polysilicon gate disposed on the high-k dielectric layer, in which the high-k dielectric layer preferably to be a linear high-k dielectric layer. The gate structure of a high-k last fabrication on the other hand, as shown in  FIG. 13 , includes a gate insulating layer  204 , a high-k dielectric layer  206  disposed on the gate insulating layer  204 , and a metal gate  240  disposed on the high-k dielectric layer  206 , in which the high-k dielectric layer  206  is a U-shaped high-k dielectric layer. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Technology Category: 5