Patent Document

This is a continuation of application Ser. No. 07/954,631 filed Sep. 30, 1992. 
    
    
     TECHNICAL FIELD OF THE INVENTION 
     This invention relates to personal computers, and more particularly to the random access memory (RAM) in personal computers. 
     BACKGROUND OF THE INVENTION 
     Memory modules allow easy upgrades of computer systems by relatively untrained personnel. However, installation of the memory modules themselves is only a portion of the upgrade task. Often a number of system parameters must be altered as well. Upgrading often involves changing jumpers, switches, or other indicators so that the computer system correctly recognizes the newly installed memory. This additional setting of indicators is frequently the source of errors when the memory is installed by untrained personnel. Additionally, the number of parameters which need to be configured has increased as the system memory controllers attempt to use memory modules in more sophisticated ways to extract the highest performance from the memory module. Changing up to 20 parameters is not likely to be successful, even for trained personnel. 
     One solution to this problem is self-identification of a memory board, such as that disclosed in UK Patent Application 2,226,667A. In that application a decoder electrically coupled with memory slots and with the central processing unit receives at the time the computer system is first powered on memory size identifying information from each of the memory boards coupled with the slots. The decoder assigns system address space to each of the individual memories. UK Patent Application 2,226,666A discloses a request/response protocol, in which a processor asserts a request signal onto a system bus. A memory module corresponding to the address of the request responds with information regarding the module&#39;s characteristics. Those characteristics include whether the module can communicate in a deterministic mode, memory size, memory speed, memory type, and whether the memory is cachable to a processor. 
     U.S. Pat. No. 4,589,063 to Shah et al. discloses a method and apparatus for automatic configuration of a computer system. The Shah et al. system is similarly limited to self-identification of an input/output device. The patent gives examples of such input/output devices, such as graphics controllers, analog-to-digital interfaces, and computer network interface equipment. 
     These identification solutions do not help the user who wishes to add some RAM, less than a full board, to his computer. What is needed is self-identification for individual memory modules, rather than identification of just an entire board of devices. 
     SUMMARY OF THE INVENTION 
     A computer includes a processor for processing data, memory modules for storing the data, first communication lines coupling the processor and the memory modules, for communicating the data between the processor and the memory modules and for communicating the memory module characteristic information from the modules to the processor, and second communication lines coupling the processor and the memory modules, for use by the processor to request the memory module characteristic information from the modules. Each module includes a read-write memory and a read-only memory. The read-only memory contains memory module characteristic information. Each module is connected to only two second communication lines. In other features of the invention, the memory module characteristic information includes an identification code for the manufacturer of the memory module, a part number for the memory module, the depth of the memory, access times to read full and page, and delay times to read and write full and page. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above-noted and other aspects of the present invention will become more apparent from a description of the preferred embodiment when read in conjunction with the accompanying drawings. The drawings illustrate the preferred embodiment of the invention. In the drawings the same members have the same reference numerals. 
     FIG. 1 depicts in a block diagram a computer built according to the present invention, containing three self-identifying memory modules. 
     FIG. 2 is a block diagram of four self-identifying memory modules built according to the present invention. 
     FIG. 3 is a block diagram of one self-identifying memory module built according to the present invention. 
     FIG. 4 is a block diagram depicting a read-only configuration memory. 
     FIGS. 5a and 5b are flow charts showing the method of the memory module self-identification of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 depicts a computer 10 built according to the present invention. The computer 10 has three memory modules 12, 14, and 16. Each memory module has four random access memories (RAM) 18. The memory modules 12, 14, and 16 also have read-only configuration memories (ROCM) 20, 22, and 24 respectively. Each ROCM could also be a ROM, a PROM, an EPROM, an EEPROM, or any other memory device that can not be modified merely by commands from the computer 10. Each ROM stores the self-identification information for its respective module, also known as the memory module characteristic information. The memory module 12 is coupled to a processor 26 by two communication lines 28, 30. The memory module 14 is coupled to the processor 26 by two communication lines 32, 34. The memory module 16 is coupled to the processor 26 by two communication lines 36, 38. The processor requests self-identification information from memory module 12 via lines 28, 30, from memory module 14 via lines 32, 34, and from memory module 16 via lines 36, 38. In the preferred embodiment, lines 30, 34, and 38 are just one line, which carries a  CONFIG signal from the processor to each module. Communication lines 40 also couple the modules to the processor. The communication lines 40 carry data between the modules and the processor, and carry the memory module characteristic information from each module to the processor. 
     FIG. 2 depicts four self-identifying memory modules 12, 14, 16, and 17, built according to the present invention. The  CONFIG signal is carried on a line 42 which connects to all four modules. A select (&#34;SEL&#34;) signal is carried on SEL lines 44, each of which connects an address (&#34;ADDR&#34;) line 46 to a memory module. Thus, for example, the SEL signal is carried on line 44a from lines 46 to memory module 17. The line 46 in FIGS. 2 and 3 represents multiple ADDR signal lines. Thus, each memory module is connected to a different ADDR line, 46a, 46b, 46c, and 46d. The SEL signal lines 44 serve the function of lines 28, 32, and 36 in FIG. 1. The SEL signal is used to select only one of the memory modules to respond with configuration information. The ADDR lines 46 connect to all four modules and carry address signals &#34;ADDR&#34; used for the row and column addresses of DRAM locations for normal, non-configuration access. Data in (&#34;D&#34;), data out (&#34;Q&#34;) lines DQ 48 connect to all four modules and carry data into and out of each module. The DQ line 48 in FIGS. 2 and 3 represents multiple DQ signal lines. A row access strobe (&#34; RAS&#34;) signal line 50 and a column access strobe (&#34; CAS&#34;) signal line 52 connect to each module. The RAS and CAS signals mark the row and column addresses as with standard DRAMs. A write enable line (&#34; WE&#34;) line 54 connects to all four modules and carries the signal WE, which is used, as in standard, normal DRAMs, to mark when an access to a DRAM is a &#34;write&#34;, instead of a &#34;read&#34;. 
     The  CONFIG and SEL signals work together to request self-identification information individually from each module, as shown below in Table 1. 
     
                       TABLE 1______________________________________    SEL     SEL     SEL   SEL   MODULE CONFIG  44a     44b     44c   44d   SELECTED______________________________________High Level    X       X       X     X     NONESignalLow Level    0       0       0     0     NONESignalLow Level    0       0       0     1     12SignalLow Level    0       0       1     0     14SignalLow Level    0       1       0     0     16SignalLow Level    1       0       0     0     17SignalLow Level    X       X       1     1     INVALIDSignal______________________________________ Where X is either zero or one, and the bottom row is only one example of an invalid combination of SEL signals, because such combination would select more than one module. 
    
     TABLE 1 
     FIG. 3 is a block diagram of the self-identifying memory module 12 built according to the present invention. The module 12 includes four DRAM&#39;s 18. Each DRAM 18 is connected to four data in, data out (DQ) lines 48. The DRAM 18a is also connected to the  RAS 50,  CAS 52,  WE 54, and ADDR 46 lines. One of the DQ lines 48 connected to the DRAM 18d is also connected to a data out line 60 of the ROCM 20. The SEL signal and the inversion of the  CONFIG signal are connected to the ROCM 20. 
     FIG. 4 depicts the ROCM 20 in block diagram form. A voltage supply point V cc  70 is connected to approximately five volts DC. A low voltage point V ss  72 is connected to ground. The ROCM 20 is controlled by a NEXT signal on line 52 from a  CAS signal, a  CONFIG signal on line 42, and a SEL signal on the SEL line 44d, according to Table 2 shown below. In the memory module 12, the  NEXT signal is the same as the  CAS signal. 
     
                                           TABLE 2__________________________________________________________________________         INTERNAL        INTERNAL         CURRENT         NEXTINPUTS        STATES     OUT- STATES         STATE STATE                    PUTS NEXT                             NEXT NEXT    SEL  CONFIG         N     E    Q    N   E__________________________________________________________________________X   L   ↓         X     X    Hi Z --  LH   H   ↓         X     X    Hi Z L   HL   H   ↓         X     X    Q.sub.0                         L   H↑    X   L     N     H    Q.sub.N                         N + 1                             HH   X   X     N     E    Hi Z N   EX   X   H     N     E    Hi Z N   LL   X   L     N     H    Q.sub.N                         N   HX   X   L     N     L    Hi Z N   L__________________________________________________________________________ Where: the output at T state = the input at T + 1 state; N = current place; E = enabled; H = high signal level; L = low signal level; ↑ = transition from a low level signal to a high level signal; and ↓ = transition from a high level signal to a low signal level signal. 
    
     The signal line  CONFIG connects to every module in the memory system. The signal line SEL connects to an address line. Each module connects to a different address line. The ROCM is selected by (1) asserting an address on the ADDR lines, which only assert SEL to a single module, (2) asserting  CAS, and (3) asserting  CONFIG. SEL is only sampled when  CONFIG is asserted. When  CONFIG is first asserted, the ROCM resets to its initial state. Thereafter, each time  NEXT is asserted, Q is driven with the next bit in sequence. Q is always held in the high impedance state unless CONFIG and  NEXT are both asserted and the module is selected by having SEL asserted when  CONFIG was first asserted. 
     Referring now to FIG. 5a, there is shown a flow chart depicting the process of the present invention, the self-identification of the configuration memory module. The process begins with an initialize step 80. Both  RAS and  CAS are initialized to high. The address is set to be an address that selects the first module, one with all zeros except for the lower order address bit equal to one.  CONFIG is initialized to low. This sets the first module into a configuration mode. In step 82, for each parameter in the parameter list as stored in configuration RAM, the parameter is set to &#34;Collect 1&#34; which is a subroutine shown in FIG. 5b. In step 84, the memory controller (not shown in the figures) is programmed for the memory module, such as a SIMM, to respond to those parameters. In step 86, the address in the next module is selected by shifting the address left one position, which can also be done by multiplying the address by two. In step 88, a count of the modules COUNT is incremented. In step 90, a configuration controller (not shown) checks to see whether it is beyond the last possible memory configuration address, or memory SIMM position, for the system. If not, the configuration controller goes back for each parameter stage and collects parameters for the next module or SIMM. If the configuration controller has finished, it is ready to enter normal operation (step 92); it is finished with the configuration operation. 
     Referring now to FIG. 5b, the &#34;Collect 1&#34; flow chart, in step 94 the accumulator is set to zero, (A cc  =0), and an internal counter is set to zero. The counter counts the number of data bits that the configuration controller reads out of the configuration memory. In step 96, the configuration controller sets  CAS equal to low. This selects the memory and causes the ROCM to drive out its first data. Step 98 is the accumulate step, which sets the value of &#34;Collect 1&#34;. In step 98, the configuration controller takes the bit on DQ o  and adds it into the previously accumulated bits, shifted up by multiplying the previously accumulated bits by two. (Accumulator ×2+DQ o ). Thus, the configuration controller shifts the accumulator and adds in a lower order bit, taken from the memory module&#39;s configuration memory. In step 100, the configuration controller returns  CAS to high. This causes the ROCM memory to increment to the next location. In step 102, the configuration controller sets Count=Count+1 in order to keep track of how many data bits have been taken in from the ROCM. In step 104, the configuration controller tests whether the count is less than the parameter size. If the count is less than the parameter size then the configuration controller goes back to step 96, sets CAS =1, to accumulate more of the data bits. If the Count is greater than or equal to the parameter size, then the configuration controller has collected enough bits, and thus it returns, in step 106, the contents of A cc  as the value of &#34;Collect 1&#34; to step 82 of FIG. 5A. 
     The fields in the ROM&#39;s 20, 22, and 24 are allocated to key parameters as shown below in Table 3. The full names of the key parameters are shown in Table 4. Other key parameters which could be included are shown on page 6-5 in &#34;MOS Memory Data Book&#34;, #SMYD091, published in 1991 by Texas Instruments. 
     
                       TABLE 3______________________________________CODE      DESCRIPTION    SPACE IN MEMORY______________________________________Manufacturer:     JDEC Code      8 bitsPart Number:     ASCII128 bits  (16 bytes)Depth:    binary value to                    8 bits     the base log2     of the number of     words in the memoryTarf:     Nanoseconds in 8 bits     binaryTarp:     Nanoseconds in 8 bits     binaryTdrf-rf:  Nanoseconds in 8 bits     binaryTdrf-rp:  Nanoseconds in 8 bits     binaryTdrp-rp:  Nanoseconds in 8 bits     binaryTdrf-wf:  Nanoseconds in 8 bits     binaryTdrp-wf:  Nanoseconds in 8 bits     binaryTdrp-wp:  Nanoseconds in 8 bits     binaryTdrf-wp:  Nanoseconds in 8 bits     binaryTddwf:    Nanoseconds in 8 bits     binaryTddwp:    Nanoseconds in 8 bits     binaryTdwf-rf:  Nanoseconds in 8 bits     binaryTdwf-rp:  Nanoseconds in 8 bits     binaryTdwp-rf:  Nanoseconds in 8 bits     binaryTdwp-rp:  Nanoseconds in 8 bits     binary______________________________________ 
    
     TABLE 3 
     
                       TABLE 4______________________________________ABBREVIATION:  MEANING:______________________________________Tarf:          Time access read fullTarp:          Time access read pageTdrf-rf:       Time delay read full to read fullTdrf-rp:       Time delay read full to read pageTdrp-rp:       Time delay read page to read pageTdrf-wf:       Time delay read full to write fullTdrp-wf:       Time delay read page to write fullTdrp-wp:       Time delay read page to write pageTdrf-wp:       Time delay read full to write pageTddwf:         Time delay data write fullTddwp:         Time delay data write pageTdwf-rf:       Time delay write full to read fullTdwf-rp:       Time delay write full to read pageTdwp-rf:       Time delay write page to read fullTdwp-rp:       Time delay write page to read page______________________________________ 
    
     In order to keep connections to a minimum, most of the control lines and all the data lines needed are shared with signals normally present on the memory module. For example, shown below in Table 4 are the signal lines which are used for two different signals. 
     
                       TABLE 5______________________________________                         SignalSignal                        SharedLine         Description      With______________________________________ CONFIG      configuration ROM                         none        enableQ            1 bit data line  DQOSEL          select this module                         none NEXT        step to next serial                          CAS        bit______________________________________ 
    
     This scheme requires only  CONFIG and SEL as additional connections to the module. 
     The principles, preferred embodiments and modes of operation of the present invention have been described in the foregoing specification. The invention is not to be construed as limited to the particular forms disclosed, since these are regarded as illustrative rather than restrictive. Moreover, variations and changes may be made by those skilled in the art without departing from the spirit of the invention.

Technology Category: 3