content
stringlengths 0
23.8k
| Book
stringclasses 10
values | segment
stringlengths 8
10
| image_urls
sequencelengths 0
11
| section
stringlengths 4
3.25k
| url
stringlengths 22
24
| timestamp
stringlengths 19
19
|
|---|---|---|---|---|---|---|
introduction riscv pronounced riskfive new instructionset architecture isa originally designed support computer architecture research education hope also become standard free open architecture industry implementations goals defining riscv include completely open isa freely available academia industry real isa suitable direct native hardware implementation simulation binary translation isa avoids overarchitecting particular microarchitecture style eg mi crocoded inorder decoupled outoforder implementation technology eg fullcustom asic fpga allows efficient implementation isa separated small base integer isa usable base customized accelerators educational purposes optional standard extensions support general purpose software development support revised 2008 ieee754 floatingpoint standard 7 isa supporting extensive isa extensions specialized variants 32bit 64bit address space variants applications operating system kernels hardware implementations isa support highlyparallel multicore manycore implementations including heterogeneous multiprocessors optional variablelength instructions expand available instruction encoding space support optional dense instruction encoding improved performance static code size energy efficiency fully virtualizable isa ease hypervisor development isa simplifies experiments new privileged architecture designs commentary design decisions formatted paragraph nonnormative text skipped reader interested specification name riscv chosen represent fifth major risc isa design uc berkeley risci 15 riscii 8 soar 21 spur 11 first four also pun use roman numeral v signify variations vectors support range architecture research including various dataparallel accelerators explicit goal isa design riscv isa defined avoiding implementation details much possible although com mentary included implementationdriven decisions read softwarevisible interface wide variety implementations rather design particular hardware artifact riscv manual structured two volumes volume covers design base unprivileged instructions including optional unprivileged isa extensions unprivileged instructions generally usable privilege modes privileged architectures though behavior might vary depending privilege mode privilege architecture second volume provides design first classic privileged architecture manuals use iec 80000132008 conventions byte 8 bits unprivileged isa design tried remove dependence particular microarchi tectural features cache line size privileged architecture details page translation simplicity allow maximum flexibility alternative microar chitectures alternative privileged architectures | riscv-spec-20191213 | segment0 | [] | Chapter 1 | RV32ISPEC.pdf#segment0 | 2023-09-18 14:50:12 |
riscv hardware platform contain one riscvcompatible processing cores to gether nonriscvcompatible cores fixedfunction accelerators various physical mem ory structures io devices interconnect structure allow components communicate component termed core contains independent instruction fetch unit riscv compatible core might support multiple riscvcompatible hardware threads harts multithreading riscv core might additional specialized instructionset extensions added coprocessor use term coprocessor refer unit attached riscv core mostly sequenced riscv instruction stream contains additional architectural state instructionset extensions possibly limited autonomy relative primary riscv instruction stream use term accelerator refer either nonprogrammable fixedfunction unit core operate autonomously specialized certain tasks riscv systems expect many programmable accelerators riscvbased cores specialized instructionset extensions andor customized coprocessors important class riscv accelerators io accelerators offload io processing tasks main application cores systemlevel organization riscv hardware platform range singlecore micro controller manythousandnode cluster sharedmemory manycore server nodes even small systemsonachip might structured hierarchy multicomputers andor multiprocessors modularize development effort provide secure isolation subsystems | riscv-spec-20191213 | segment1 | [] | 1.1 RISC-V Hardware Platform Terminology | RV32ISPEC.pdf#segment1 | 2023-09-18 14:50:12 |
behavior riscv program depends execution environment runs riscv execution environment interface eei defines initial state program number type harts environment including privilege modes supported harts accessibility attributes memory io regions behavior legal instructions exe cuted hart ie isa one component eei handling interrupts exceptions raised execution including environment calls examples eeis include linux application binary interface abi riscv supervisor binary interface sbi implementation riscv execution environment pure hardware pure software combination hardware software example opcode traps software emulation used implement functionality provided hardware examples execution environment implementations include bare metal hardware platforms harts directly implemented physical processor threads instructions full access physical address space hardware platform defines execution environment begins poweron reset riscv operating systems provide multiple userlevel execution environments mul tiplexing userlevel harts onto available physical processor threads controlling access memory via virtual memory riscv hypervisors provide multiple supervisorlevel execution environments guest operating systems riscv emulators spike qemu rv8 emulate riscv harts under lying x86 system provide either userlevel supervisorlevel execution environment bare hardware platform considered define eei accessible harts memory devices populate environment initial state poweron reset generally software designed use abstract interface hardware abstract eeis provide greater portability across different hardware platforms often eeis layered top one another one higherlevel eei uses another lowerlevel eei perspective software running given execution environment hart resource autonomously fetches executes riscv instructions within execution environment respect hart behaves like hardware thread resource even timemultiplexed onto real hardware execution environment eeis support creation destruction additional harts example via environment calls fork new harts execution environment responsible ensuring eventual forward progress harts given hart responsibility suspended hart exercising mechanism explicitly waits event waitforinterrupt instruction defined volume ii specification responsibility ends hart terminated following events constitute forward progress retirement instruction trap defined section 16 event defined extension constitute forward progress term hart introduced work lithe 13 14 provide term represent abstract execution resource opposed software thread programming abstraction important distinction hardware thread hart software thread context software running inside execution environment responsible causing progress harts responsibility outer execution environment environment harts operate like hardware threads perspective software inside execution environment execution environment implementation might timemultiplex set guest harts onto fewer host harts provided execution environment must way guest harts operate like independent hardware threads particular guest harts host harts execution environment must able preempt guest harts must wait indefinitely guest software guest hart yield control guest hart | riscv-spec-20191213 | segment2 | [] | 1.2 RISC-V Software Execution Environments and Harts | RV32ISPEC.pdf#segment2 | 2023-09-18 14:50:12 |
riscv isa defined base integer isa must present implementation plus optional extensions base isa base integer isas similar early risc processors except branch delay slots support optional variablelength instruction encodings base carefully restricted minimal set instructions sufficient provide reasonable target compilers assemblers linkers operating systems addi tional privileged operations provides convenient isa software toolchain skeleton around customized processor isas built although convenient speak riscv isa riscv actually family related isas currently four base isas base integer instruction set characterized width integer registers corresponding size address space number integer registers two primary base integer variants rv32i rv64i described chapters 2 5 provide 32bit 64bit address spaces respectively use term xlen refer width integer register bits either 32 64 chapter 4 describes rv32e subset variant rv32i base instruction set added support small microcontrollers half number integer registers chapter 6 sketches future rv128i variant base integer instruction set supporting flat 128bit address space xlen128 base integer instruction sets use two scomplement representation signed integer values although 64bit address spaces requirement larger systems believe 32bit address spaces remain adequate many embedded client devices decades come desirable lower memory traffic energy consumption addition 32bit address spaces sufficient educational purposes larger flat 128bit address space might eventually required ensured could accommodated within riscv isa framework four base isas riscv treated distinct base isas common question single isa particular rv32i strict subset rv64i earlier isa designs sparc mips adopted strict superset policy increasing address space size support running existing 32bit binaries new 64bit hardware main advantage explicitly separating base isas base isa opti mized needs without requiring support operations needed base isas example rv64i omit instructions csrs needed cope nar rower registers rv32i rv32i variants use encoding space otherwise reserved instructions required wider addressspace variants main disadvantage treating design single isa complicates hardware needed emulate one base isa another eg rv32i rv64i however differences addressing illegal instruction traps generally mean mode switch would required hardware case even full superset instruction encodings different riscv base isas similar enough supporting multiple versions relatively low cost although proposed strict superset design would allow legacy 32bit libraries linked 64bit code impractical practice even compatible encodings due differences software calling conventions systemcall interfaces riscv privileged architecture provides fields misa control unprivileged isa level support emulating different base isas hardware note newer sparc mips isa revisions deprecated support running 32bit code unchanged 64bit systems related question different encoding 32bit adds rv32i add rv64i addw addw opcode could used 32bit adds rv32i addd 64bit adds rv64i instead existing design uses opcode add 32 bit adds rv32i 64bit adds rv64i different opcode addw 32bit adds rv64i would also consistent use lw opcode 32bit load rv32i rv64i first versions riscv isa variant alternate design riscv design changed current choice january 2011 focus supporting 32bit integers 64bit isa providing compatibility 32bit isa motivation remove asymmetry arose opcodes rv32i w suffix eg addw andw hindsight perhaps welljustified consequence designing isas time opposed adding one later sit top another also belief fold platform requirements isa spec would imply rv32i instructions would required rv64i late change encoding also little practical consequence reasons stated noted could enable w variants extension rv32i systems provide common encoding across rv64i future rv32 variant riscv designed support extensive customization specialization base integer isa extended one optional instructionset extensions divide risc v instructionset encoding space related encoding spaces csrs three disjoint categories standard reserved custom standard encodings defined foundation shall conflict standard extensions base isa reserved encodings currently defined saved future standard extensions use term non standard describe extension defined foundation custom encodings shall never used standard extensions made available vendorspecific nonstandard extensions use term nonconforming describe nonstandard extension uses either standard reserved encoding ie custom extensions nonconforming instructionset extensions generally shared may provide slightly different functionality depending base isa chapter 26 describes various ways extending riscv isa also developed naming convention riscv base instructions instructionset extensions described detail chapter 27 support general software development set standard extensions defined provide integer multiplydivide atomic operations single doubleprecision floatingpoint arith metic base integer isa named prefixed rv32 rv64 depending integer register width contains integer computational instructions integer loads integer stores control flow instructions standard integer multiplication division extension named adds instructions multiply divide values held integer registers standard atomic instruction extension denoted adds instructions atomically read modify write memory interprocessor synchronization standard singleprecision floatingpoint exten sion denoted f adds floatingpoint registers singleprecision computational instructions singleprecision loads stores standard doubleprecision floatingpoint extension denoted expands floatingpoint registers adds doubleprecision computational instruc tions loads stores standard c compressed instruction extension provides narrower 16bit forms common instructions beyond base integer isa standard gc extensions believe rare new instruction provide significant benefit applications although may beneficial certain domain energy efficiency concerns forcing greater specialization believe important simplify required portion isa specification whereas architectures usually treat isa single entity changes new version instructions added time riscv endeavor keep base standard extension constant time instead layer new instructions optional extensions example base integer isas continue fully supported standalone isas regardless subsequent extensions | riscv-spec-20191213 | segment3 | [] | 1.3 RISC-V ISA Overview | RV32ISPEC.pdf#segment3 | 2023-09-18 14:50:13 |
riscv hart single byteaddressable address space 2xlen bytes memory accesses word memory defined 32 bits 4 bytes correspondingly halfword 16 bits 2 bytes doubleword 64 bits 8 bytes quadword 128 bits 16 bytes memory address space circular byte address 2xlen 1 adjacent byte address zero accordingly memory address computations done hardware ignore overflow instead wrap around modulo 2xlen execution environment determines mapping hardware resources hart address space different address ranges hart address space may 1 vacant 2 contain main memory 3 contain one io devices reads writes io devices may visible side effects accesses main memory although possible execution environment call everything hart address space io device usually expected portion specified main memory riscv platform multiple harts address spaces two harts may entirely entirely different may partly different sharing subset resources mapped different address ranges purely bare metal environment harts may see identical address space accessed entirely physical addresses however execution environment includes operating system employing address translation common hart given virtual address space largely entirely executing riscv machine instruction entails one memory accesses subdivided implicit explicit accesses instruction executed implicit memory read instruction fetch done obtain encoded instruction execute many riscv instructions perform memory accesses beyond instruction fetch specific load store instructions perform explicit read write memory address determined instruction execution environment may dictate instruction execution performs implicit memory accesses implement address translation beyond documented unprivileged isa execution environment determines portions nonvacant address space accessible kind memory access example set locations implicitly read instruction fetch may may overlap set locations explicitly read load instruction set locations explicitly written store instruction may subset locations read ordinarily instruction attempts access memory inaccessible address exception raised instruction vacant locations address space never accessible except specified otherwise implicit reads raise exception side effects may occur arbitrarily early speculatively even machine could possibly prove read needed instance valid implementation could attempt read main memory earliest opportunity cache many fetchable executable bytes possible later instruction fetches avoid reading main memory instruction fetches ever ensure certain implicit reads ordered writes memory locations software must execute specific fence cachecontrol instructions defined purpose fencei instruction defined chapter 3 memory accesses implicit explicit made hart may appear occur different order perceived another hart agent access memory perceived reordering memory accesses always constrained however applicable memory consistency model default memory consistency model riscv riscv weak memory ordering rvwmo defined chapter 14 appendices optionally implementation may adopt stronger model total store ordering defined chapter 23 execution environment may also add constraints limit perceived reordering memory accesses since rvwmo model weakest model allowed riscv implementation software written model compatible actual memory consistency rules riscv implementations implicit reads software must execute fence cachecontrol instructions ensure specific ordering memory accesses beyond requirements assumed memory consistency model execution environment | riscv-spec-20191213 | segment4 | [] | 1.4 Memory | RV32ISPEC.pdf#segment4 | 2023-09-18 14:50:13 |
base riscv isa fixedlength 32bit instructions must naturally aligned 32bit boundaries however standard riscv encoding scheme designed support isa extensions variablelength instructions instruction number 16bit instruction parcels length parcels naturally aligned 16bit boundaries standard compressed isa extension described chapter 16 reduces code size providing compressed 16bit instructions relaxes alignment constraints allow instructions 16 bit 32 bit aligned 16bit boundary improve code density use term ialign measured bits refer instructionaddress alignment constraint implementation enforces ialign 32 bits base isa isa extensions including compressed isa extension relax ialign 16 bits ialign may take value 16 32 use term ilen measured bits refer maximum instruction length supported implementation always multiple ialign implementations supporting base instruction set ilen 32 bits implementations supporting longer instructions larger values ilen figure 11 illustrates standard riscv instructionlength encoding convention 32bit instructions base isa lowest two bits set 11 optional compressed 16bit instructionset extensions lowest two bits equal 00 01 10 expanded instructionlength encoding portion 32bit instructionencoding space tentatively allocated instructions longer 32 bits entirety space reserved time following proposal encoding instructions longer 32 bits considered frozen standard instructionset extensions encoded 32 bits additional loworder bits set 1 conventions 48bit 64bit lengths shown figure 11 instruction lengths 80 bits 176 bits encoded using 3bit field bits 1412 giving number 16bit words addition first 516bit words encoding bits 1412 set 111 reserved future longer instruction encodings given code size energy savings compressed format wanted build support compressed format isa encoding scheme rather adding afterthought allow simpler implementations want make compressed format mandatory also wanted optionally allow longer instructions support experimentation larger instructionset extensions although encoding convention required tighter encoding core riscv isa several beneficial effects implementation standard imafd isa need hold mostsignificant 30 bits instruction caches 625 saving instruction cache refills instructions encountered either low bit clear recoded illegal 30bit instructions storing cache preserve illegal instruction exception behavior perhaps importantly condensing base isa subset 32bit instruction word leave space available nonstandard custom extensions particular base rv32i isa uses less 18 encoding space 32bit instruction word described chapter 26 implementation require support standard compressed instruction extension map 3 additional nonconforming 30bit instruction spaces 32bit fixedwidth format preserving support standard 32bit instructionset extensions implementation also need instructions 32bits length recover four major opcodes nonconforming extensions encodings bits 150 zeros defined illegal instructions instructions con sidered minimal length 16 bits 16bit instructionset extension present otherwise 32 bits encoding bits ilen10 ones also illegal instruction considered ilen bits long consider feature length instruction containing zero bits legal quickly traps erroneous jumps zeroed memory regions similarly also reserve instruction encoding containing ones illegal instruction catch common pattern observed unprogrammed nonvolatile memory devices disconnected memory buses broken memory devices software rely naturally aligned 32bit word containing zero act illegal instruction riscv implementations used software illegal instruction explicitly desired defining corresponding known illegal value ones difficult due variablelength encoding software generally use illegal value ilen bits 1s software might know ilen eventual target machine eg software compiled standard binary library used many different machines defining 32bit word ones illegal also considered machines must support 32bit instruction size requires instructionfetch unit machines ilen 32 report illegal instruction exception rather access fault instruction borders protection boundary complicating variableinstructionlength fetch decode riscv base isas either littleendian bigendian memory systems privileged architecture defining biendian operation instructions stored memory sequence 16bit littleendian parcels regardless memory system endianness parcels forming one in struction stored increasing halfword addresses lowestaddressed parcel holding lowestnumbered bits instruction specification originally chose littleendian byte ordering riscv memory system little endian systems currently dominant commercially x86 systems ios android win dows arm minor point also found littleendian memory systems natural hardware designers however certain application areas ip networking operate bigendian data structures certain legacy code bases built assuming bigendian processors defined bigendian biendian variants riscv fix order instruction parcels stored memory independent memory system endianness ensure lengthencoding bits always appear first halfword address order allows length variablelength instruction quickly determined instructionfetch unit examining first bits first 16bit instruction parcel make instruction parcels littleendian decouple instruction encoding memory system endianness altogether design benefits software tooling biendian hardware otherwise instance riscv assembler disassembler would always need know intended active endianness despite biendian systems endianness mode might change dynamically execution contrast giving instructions fixed endianness sometimes possible carefully written software endianness agnostic even binary form much like positionindependent code choice instructions littleendian consequences however riscv software encodes decodes machine instructions bigendian jit compilers example must swap byte order storing instruction memory decided fix littleendian instruction encoding naturally led placing lengthencoding bits lsb positions instruction format avoid breaking opcode fields | riscv-spec-20191213 | segment5 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%201.1.jpg?raw=true"
] | 1.5 Base Instruction-Length Encoding | RV32ISPEC.pdf#segment5 | 2023-09-18 14:50:14 |
use term exception refer unusual condition occurring run time associated instruction current riscv hart use term interrupt refer external asynchronous event may cause riscv hart experience unexpected transfer control use term trap refer transfer control trap handler caused either exception interrupt instruction descriptions following chapters describe conditions raise exception execution general behavior riscv eeis trap handler occurs exception signaled instruction except floatingpoint exceptions standard floatingpoint extensions cause traps manner interrupts generated routed enabled hart depends eei use exception trap compatible ieee754 floatingpoint stan dard traps handled made visible software running hart depends enclosing execution environment perspective software running inside execution environment traps encountered hart runtime four different effects contained trap trap visible handled software running inside execution environment example eei providing supervisor user mode harts ecall usermode hart generally result transfer control supervisor mode handler running hart similarly environment hart interrupted interrupt handler run supervisor mode hart requested trap trap synchronous exception explicit call execution environment requesting action behalf software inside execution environment example system call case execution may may resume hart requested action taken execution environment example system call could remove hart cause orderly termination entire execution environment invisible trap trap handled transparently execution environment execution resumes normally trap handled examples include emulating missing instructions handling nonresident page faults demandpaged virtualmemory system handling device interrupts different job multiprogrammed machine cases software running inside execution environment aware trap ignore timing effects definitions fatal trap trap represents fatal failure causes execution environment terminate execution examples include failing virtualmemory pageprotection check allowing watchdog timer expire eei define execution terminated reported external environment eei defines trap whether handled precisely though recommendation maintain preciseness possible contained requested traps observed imprecise software inside execution environment invisible traps definition observed precise imprecise software running inside execution environment fatal traps observed imprecise software running inside execution environment knownerrorful instructions cause immediate termination document describes unprivileged instructions traps rarely mentioned architec tural means handle contained traps defined privileged architecture manual along features support richer eeis unprivileged instructions defined solely cause requested traps documented invisible traps nature scope document instruction encodings defined defined means may cause fatal trap | riscv-spec-20191213 | segment6 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%201.1.jpg?raw=true"
] | 1.6 Exceptions, Traps, and Interrupts | RV32ISPEC.pdf#segment6 | 2023-09-18 14:50:14 |
architecture fully describes implementations must constraints may cases architecture intentionally constrain implementations term unspecified explicitly used term unspecified refers behavior value intentionally unconstrained definition behaviors values open extensions platform standards implementations extensions platform standards implementation documentation may provide normative content constrain cases base architecture defines unspecified like base architecture extensions fully describe allowable behavior values use term unspecified cases intentionally unconstrained cases may constrained defined extensions platform standards implementations | riscv-spec-20191213 | segment7 | [] | 1.7 UNSPECIFIED Behaviors and Values | RV32ISPEC.pdf#segment7 | 2023-09-18 14:50:14 |
rv32i base integer instruction set version 21 chapter describes version 20 rv32i base integer instruction set rv32i designed sufficient form compiler target support modern operating system environments isa also designed reduce hardware required minimal implementation rv32i contains 40 unique instructions though simple implementation might cover ecallebreak instructions single system hardware instruction al ways traps might able implement fence instruction nop reducing base instruction count 38 total rv32i emulate almost isa extension except extension requires additional hardware support atomicity practice hardware implementation including machinemode privileged architecture also require 6 csr instructions subsets base integer isa might useful pedagogical purposes base defined little incentive subset real hardware implementation beyond omitting support misaligned memory accesses treating system instructions single trap commentary rv32i also applies rv64i base | riscv-spec-20191213 | segment8 | [] | Chapter 2 | RV32ISPEC.pdf#segment8 | 2023-09-18 14:50:14 |
figure 21 shows unprivileged state base integer isa rv32i 32 x registers 32 bits wide ie xlen32 register x0 hardwired bits equal 0 general purpose registers x1x31 hold values various instructions interpret collection boolean values two complement signed binary integers unsigned binary integers one additional unprivileged register program counter pc holds address current instruction dedicated stack pointer subroutine return address link register base integer isa instruction encoding allows x register used purposes however standard software calling convention uses register x1 hold return address call register x5 available alternate link register standard calling convention uses register x2 stack pointer hardware might choose accelerate function calls returns use x1 x5 see descriptions jal jalr instructions optional compressed 16bit instruction format designed around assumption x1 return address register x2 stack pointer software using conventions operate correctly may greater code size number available architectural registers large impacts code size performance energy consumption although 16 registers would arguably sufficient integer isa running compiled code impossible encode complete isa 16 registers 16bit instructions using 3address format although 2address format would possible would increase instruction count lower efficiency wanted avoid intermediate instruction sizes xtensa 24bit instructions simplify base hardware implementations 32bit instruction size adopted straightforward support 32 integer registers larger number integer registers also helps performance highperformance code extensive use loop unrolling software pipelining cache tiling reasons chose conventional size 32 integer registers base isa dy namic register usage tends dominated frequently accessed registers regfile im plementations optimized reduce access energy frequently accessed registers 20 optional compressed 16bit instruction format mostly accesses 8 registers hence provide dense instruction encoding additional instructionset extensions could support much larger register space either flat hierarchical desired resourceconstrained embedded applications defined rv32e subset 16 registers chapter 4 | riscv-spec-20191213 | segment9 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%202.1.jpg?raw=true"
] | 2.1 Programmers’ Model for Base Integer ISA | RV32ISPEC.pdf#segment9 | 2023-09-18 14:50:14 |
base rv32i isa four core instruction formats risu shown figure 22 fixed 32 bits length must aligned fourbyte boundary memory instructionaddressmisaligned exception generated taken branch unconditional jump target address fourbyte aligned exception reported branch jump instruction target instruction instructionaddressmisaligned exception generated conditional branch taken alignment constraint base isa instructions relaxed twobyte boundary instruction extensions 16bit lengths odd multiples 16bit lengths added ie ialign16 instructionaddressmisaligned exceptions reported branch jump would cause instruction misalignment help debugging simplify hardware design systems ialign32 places misalignment occur behavior upon decoding reserved instruction unspecified platforms may require opcodes reserved standard use raise illegalinstruction exception platforms may permit reserved opcode space used nonconforming exten sions riscv isa keeps source rs1 rs2 destination rd registers position formats simplify decoding except 5bit immediates used csr instructions chapter 9 immediates always signextended generally packed towards leftmost available bits instruction allocated reduce hardware complexity partic ular sign bit immediates always bit 31 instruction speed signextension circuitry decoding register specifiers usually critical paths implementations in struction format chosen keep register specifiers position formats expense move immediate bits across formats property shared risciv aka spur 11 practice immediates either small require xlen bits chose asym metric immediate split 12 bits regular instructions plus special loadupperimmediate in struction 20 bits increase opcode space available regular instructions immediates signextended observe benefit using zeroextension immediates mips isa wanted keep isa simple possible | riscv-spec-20191213 | segment10 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%202.2.jpg?raw=true"
] | 2.2 Base Instruction Formats | RV32ISPEC.pdf#segment10 | 2023-09-18 14:50:14 |
two variants instruction formats bj based handling imme diates shown figure 23 difference b formats 12bit immediate field used encode branch offsets multiples 2 b f ormat instead shifting bits instructionencoded immediate left one hardware conventionally done middle bits imm 101 sign bit stay fixed p ositions lowest bit format inst 7 encodes highorder bit b format similarly difference u j formats 20bit immediate shifted left 12 bits form u immediates 1 bit form j immediates location instruction bits u j format immediates chosen maximize overlap formats figure 24 shows immediates produced base instruction formats labeled show instruction bit inst produces bit immediate value signextension one critical operations immediates particularly xlen 32 riscv sign bit immediates always held bit 31 instruction allow signextension proceed parallel instruction decoding although complex implementations might separate adders branch jump calculations would benefit keeping location immediate bits constant across types instruction wanted reduce hardware cost simplest implementations rotating bits instruction encoding b j immediates instead using dynamic hard ware muxes multiply immediate 2 reduce instruction signal fanout immediate mux costs around factor 2 scrambled immediate encoding add negligible time static aheadoftime compilation dynamic generation instructions small additional overhead common short forward branches straightforward immediate encodings | riscv-spec-20191213 | segment11 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%202.3.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%202.4.jpg?raw=true"
] | 2.3 Immediate Encoding Variants | RV32ISPEC.pdf#segment11 | 2023-09-18 14:50:14 |
integer computational instructions operate xlen bits values held integer register file integer computational instructions either encoded registerimmediate operations using itype format registerregister operations using rtype format destination register rd registerimmediate registerregister instructions integer computational instructions cause arithmetic exceptions include special instructionset support overflow checks integer arithmetic operations base instruction set many overflow checks cheaply implemented using riscv branches overflow checking unsigned addition requires single additional branch instruction addition add t0 t1 t2 bltu t0 t1 overflow signed addition one operand sign known overflow checking requires single branch addition addi t0 t1 imm blt t0 t1 overflow covers common case addition immediate operand general signed addition three additional instructions addition required leveraging observation sum less one operands operand negative add t0 t1 t2 slti t3 t2 0 slt t4 t0 t1 bne t3 t4 overflow rv64i checks 32bit signed additions optimized comparing results add addw operands integer registerimmediate instructions addi adds signextended 12bit immediate register rs1 arithmetic overflow ignored result simply low xlen bits result addi rd rs1 0 used implement mv rd rs1 assembler pseudoinstruction slti set less immediate places value 1 register rd register rs1 less sign extended immediate treated signed numbers else 0 written rd sltiu similar compares values unsigned numbers ie immediate first signextended xlen bits treated unsigned number note sltiu rd rs1 1 sets rd 1 rs1 equals zero otherwise sets rd 0 assembler pseudoinstruction seqz rd rs andi ori xori logical operations perform bitwise xor register rs1 signextended 12bit immediate place result rd note xori rd rs1 1 performs bitwise logical inversion register rs1 assembler pseudoinstruction rd rs shifts constant encoded specialization itype format operand shifted rs1 shift amount encoded lower 5 bits iimmediate field right shift type encoded bit 30 slli logical left shift zeros shifted lower bits srli logical right shift zeros shifted upper bits srai arithmetic right shift original sign bit copied vacated upper bits lui load upper immediate used build 32bit constants uses utype format lui places uimmediate value top 20 bits destination register rd filling lowest 12 bits zeros auipc add upper immediate pc used build pcrelative addresses uses utype format auipc forms 32bit offset 20bit uimmediate filling lowest 12 bits zeros adds offset address auipc instruction places result register rd auipc instruction supports twoinstruction sequences access arbitrary offsets pc controlflow transfers data accesses combination auipc 12bit immediate jalr transfer control 32bit pcrelative address auipc plus 12bit immediate offset regular load store instructions access 32bit pcrelative data address current pc obtained setting uimmediate 0 although jal 4 instruction could also used obtain local pc instruction following jal might cause pipeline breaks simpler microarchitectures pollute btb structures complex microarchitectures integer registerregister operations rv32i defines several arithmetic rtype operations operations read rs1 rs2 registers source operands write result register rd funct7 funct3 fields select type operation add performs addition rs1 rs2 sub performs subtraction rs2 rs1 overflows ignored low xlen bits results written destination rd slt sltu perform signed unsigned compares respectively writing 1 rd rs1 rs2 0 otherwise note sltu rd x0 rs2 sets rd 1 rs2 equal zero otherwise sets rd zero assembler pseudoinstruction snez rd rs xor perform bitwise logical operations sll srl sra perform logical left logical right arithmetic right shifts value register rs1 shift amount held lower 5 bits register rs2 nop instruction nop instruction change architecturally visible state except advancing pc incrementing applicable performance counters nop encoded addi x0 x0 0 nops used align code segments microarchitecturally significant address boundaries leave space inline code modifications although many possible ways encode nop define canonical nop encoding allow microarchitectural optimizations well readable disassembly output nop encodings made available hint instructions section 29 addi chosen nop encoding likely take fewest resources execute across range systems optimized away decode particular instruction reads one register also addi functional unit likely available superscalar design adds common operation particular addressgeneration functional units execute addi using hardware needed baseoffset address calculations registerregister add logicalshift operations require additional hardware | riscv-spec-20191213 | segment12 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(2.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(2.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra4(2.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra5(2.4).jpg?raw=true"
] | 2.4 Integer Computational Instructions | RV32ISPEC.pdf#segment12 | 2023-09-18 14:50:15 |
rv32i provides two types control transfer instructions unconditional jumps conditional branches control transfer instructions rv32i architecturally visible delay slots unconditional jumps jump link jal instruction uses jtype format jimmediate encodes signed offset multiples 2 bytes offset signextended added address jump instruction form jump target address jumps therefore target 1 mib range jal stores address instruction following jump pc4 register rd standard software calling convention uses x1 return address register x5 alternate link register alternate link register supports calling millicode routines eg save restore registers compressed code preserving regular return address register register x5 chosen alternate link register maps temporary standard calling convention encoding one bit different regular link register plain unconditional jumps assembler pseudoinstruction j encoded jal rdx0 indirect jump instruction jalr jump link register uses itype encoding target address obtained adding signextended 12bit iimmediate register rs1 setting leastsignificant bit result zero address instruction following jump pc4 written register rd register x0 used destination result required unconditional jump instructions use pcrelative addressing help support position independent code jalr instruction defined enable twoinstruction sequence jump anywhere 32bit absolute address range lui instruction first load rs1 upper 20 bits target address jalr add lower bits similarly auipc jalr jump anywhere 32bit pcrelative address range note jalr instruction treat 12bit immediate multiples 2 bytes unlike conditional branch instructions avoids one immediate format hardware practice uses jalr either zero immediate paired lui auipc slight reduction range significant clearing leastsignificant bit calculating jalr target address simplifies hardware slightly allows low bit function pointers used store auxiliary information although potentially slight loss error checking case practice jumps incorrect instruction address usually quickly raise exception used base rs1x0 jalr used implement single instruction subrou tine call lowest 2 kib highest 2 kib address region anywhere address space could used implement fast calls small runtime library alternatively abi could dedicate generalpurpose register point library elsewhere address space jal jalr instructions generate instructionaddressmisaligned exception target address aligned fourbyte boundary instructionaddressmisaligned exceptions possible machines support extensions 16bit aligned instructions compressed instructionset extension c returnaddress prediction stacks common feature highperformance instructionfetch units require accurate detection instructions used procedure calls returns effective riscv hints instructions usage encoded implicitly via register numbers used jal instruction push return address onto returnaddress stack ras rdx1x5 jalr instructions pushpop ras shown table 21 isas added explicit hint bits indirectjump instructions guide return address stack manipulation use implicit hinting tied register numbers calling convention reduce encoding space used hints two different link registers x1 x5 given rs1 rd ras popped pushed support coroutines rs1 rd link regis ter either x1 x5 ras pushed enable macroop fusion sequences lui ra imm20 jalr ra imm12 ra auipc ra imm20 jalr ra imm12 ra conditional branches branch instructions use btype instruction format 12bit bimmediate encodes signed offsets multiples 2 bytes offset signextended added address branch instruction give target address conditional branch range 4 kib branch instructions compare two registers beq bne take branch registers rs1 rs2 equal unequal respectively blt bltu take branch rs1 less rs2 using signed unsigned comparison respectively bge bgeu take branch rs1 greater equal rs2 using signed unsigned comparison respectively note bgt bgtu ble bleu synthesized reversing operands blt bltu bge bgeu respectively signed array bounds may checked single bltu instruction since negative index compare greater nonnegative bound software optimized sequential code path common path lessfrequently taken code paths placed line software also assume backward branches predicted taken forward branches taken least first time encountered dynamic predictors quickly learn predictable branch behavior unlike architectures riscv jump jal rdx0 instruction always used unconditional branches instead conditional branch instruction always true condition riscv jumps also pcrelative support much wider offset range branches pollute conditionalbranch prediction tables conditional branches designed include arithmetic comparison operations two registers also done parisc xtensa mips r6 rather use condition codes x86 arm sparc powerpc compare one register zero alpha mips two registers equality mips design motivated observation combined compareandbranch instruction fits regular pipeline avoids additional condition code state use temporary register reduces static code size dynamic instruction fetch traffic another point comparisons zero require nontrivial circuit delay especially move static logic advanced processes almost expensive arithmetic magnitude compares another advantage fused compareandbranch instruction branches observed earlier frontend instruction stream predicted earlier perhaps advantage design condition codes case multiple branches taken based condition codes believe case relatively rare considered include static branch hints instruction encoding reduce pressure dynamic predictors require instruction encoding space software profiling best results result poor performance production runs match profiling runs considered include conditional moves predicated instructions effectively replace unpredictable short forward branches conditional moves simpler two difficult use conditional code might cause exceptions memory accesses floatingpoint operations predication adds additional flag state system addi tional instructions set clear flags additional encoding overhead every instruction conditional move predicated instructions add complexity outoforder microarchitec tures adding implicit third source operand due need copy original value destination architectural register renamed destination physical register predicate false also static compiletime decisions use predication instead branches result lower performance inputs included compiler training set especially given unpredictable branches rare becoming rarer branch prediction techniques improve note various microarchitectural techniques exist dynamically convert unpredictable short forward branches internally predicated code avoid cost flushing pipelines branch mispredict 6 10 9 implemented commercial processors 17 simplest techniques reduce penalty recovering mispredicted short forward branch flushing instructions branch shadow instead entire fetch pipeline fetching instructions sides using wide instruction fetch idle instruction fetch slots complex techniques outoforder cores add internal predicates instructions branch shadow internal predicate value written branch instruction allowing branch following instructions executed speculatively outoforder respect code 17 conditional branch instructions generate instructionaddressmisaligned exception target address aligned fourbyte boundary branch condition evaluates true branch condition evaluates false instructionaddressmisaligned exception raised instructionaddressmisaligned exceptions possible machines support extensions 16bit aligned instructions compressed instructionset extension c | riscv-spec-20191213 | segment13 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(2.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%202.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(2.5).jpg?raw=true"
] | 2.5 Control Transfer Instructions | RV32ISPEC.pdf#segment13 | 2023-09-18 14:50:15 |
rv32i loadstore architecture load store instructions access memory arithmetic instructions operate cpu registers rv32i provides 32bit address space byteaddressed eei define portions address space legal access instructions eg addresses might read support word access loads destination x0 must still raise exceptions cause side effects even though load value discarded eei define whether memory system littleendian bigendian riscv endian ness byteaddress invariant system endianness byteaddress invariant following property holds byte stored memory address endianness bytesized load address endianness returns stored value littleendian configuration multibyte stores write leastsignificant register byte lowest memory byte address followed register bytes ascending order significance loads similarly transfer contents lesser memory byte addresses lesssignificant register bytes bigendian configuration multibyte stores write mostsignificant register byte lowest memory byte address followed register bytes descending order significance loads similarly transfer contents greater memory byte addresses lesssignificant register bytes load store instructions transfer value registers memory loads encoded itype format stores stype effective address obtained adding register rs1 signextended 12bit offset loads copy value memory register rd stores copy value register rs2 memory lw instruction loads 32bit value memory rd lh loads 16bit value memory signextends 32bits storing rd lhu loads 16bit value memory zero extends 32bits storing rd lb lbu defined analogously 8bit values sw sh sb instructions store 32bit 16bit 8bit values low bits register rs2 memory regardless eei loads stores whose effective addresses naturally aligned shall raise addressmisaligned exception loads stores effective address naturally aligned referenced datatype ie fourbyte boundary 32bit accesses twobyte boundary 16bit accesses behavior dependent eei eei may guarantee misaligned loads stores fully supported software run ning inside execution environment never experience contained fatal addressmisaligned trap case misaligned loads stores handled hardware via invisible trap execution environment implementation possibly combination hardware invisible trap depending address eei may guarantee misaligned loads stores handled invisibly case loads stores naturally aligned may either complete execution successfully raise exception exception raised either addressmisaligned exception accessfault exception memory access would otherwise able complete except misalign ment access exception raised instead addressmisaligned exception misaligned access emulated eg accesses memory region side effects eei guarantee misaligned loads stores handled invisibly eei must define exceptions caused address misalignment result contained trap allowing software running inside execution environment handle trap fatal trap terminating execution misaligned accesses occasionally required porting legacy code help performance applications using form packedsimd extension handling externally packed data structures rationale allowing eeis choose support misaligned accesses via regular load store instructions simplify addition misaligned hardware support one option would disallow misaligned accesses base isa provide separate isa support misaligned accesses either special instructions help software handle misaligned accesses new hardware addressing mode misaligned accesses special instructions difficult use complicate isa often add new processor state eg sparc vis align address offset register complicate access existing processor state eg mips lwllwr partial register writes addition looporiented packedsimd code extra overhead operands misaligned motivates software provide multiple forms loop depending operand alignment complicates code generation adds loop startup overhead new misaligned hardware addressing modes take considerable space instruction encoding require simplified addressing modes eg register indirect even misaligned loads stores complete successfully accesses might run extremely slowly depending implementation eg implemented via invisible trap further whereas naturally aligned loads stores guaranteed execute atomically misaligned loads stores might hence require additional synchronization ensure atomicity mandate atomicity misaligned accesses execution environment implementa tions use invisible machine trap software handler handle misaligned accesses hardware misaligned support provided software exploit simply using regular load store instructions hardware automatically optimize accesses depend ing whether runtime addresses aligned | riscv-spec-20191213 | segment14 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.6).jpg?raw=true"
] | 2.6 Load and Store Instructions | RV32ISPEC.pdf#segment14 | 2023-09-18 14:50:16 |
fence instruction used order device io memory accesses viewed risc v harts external devices coprocessors combination device input device output memory reads r memory writes w may ordered respect combination informally riscv hart external device observe operation successor set following fence operation predecessor set preceding fence chapter 14 provides precise description riscv memory consistency model eei define io operations possible particular memory addresses accessed load store instructions treated ordered device input device output operations respectively rather memory reads writes example memory mapped io devices typically accessed uncached loads stores ordered using bits rather r w bits instructionset extensions might also describe new io instructions also ordered using bits fence fence mode field fm defines semantics fence fence fm0000 orders memory operations predecessor set memory operations successor set optional fencetso instruction encoded fence instruction fm1000 predeces sorrw successorrw fencetso orders load operations predecessor set memory operations successor set store operations predecessor set store operations successor set leaves nonamo store operations fencetso predecessor set unordered nonamo loads successor set fencetso encoding added optional extension original base fence instruction encoding base definition requires implementations ignore set bits treat fence global backwardscompatible extension unused fields fence instructionsrs1 rdare reserved finergrain fences future extensions forward compatibility base implementations shall ignore fields standard software shall zero fields likewise many fm predecessorsuccessor set settings table 22 also reserved future use base implementations shall treat reserved configurations normal fences fm0000 standard software shall use nonreserved configurations chose relaxed memory model allow high performance simple machine implementa tions likely future coprocessor accelerator extensions separate io ordering memory rw ordering avoid unnecessary serialization within devicedriver hart also support alternative nonmemory paths control added coprocessors io devices simple implementations may additionally ignore predecessor successor fields always execute conservative fence operations | riscv-spec-20191213 | segment15 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.7).jpg?raw=true"
] | 2.7 Memory Ordering Instructions | RV32ISPEC.pdf#segment15 | 2023-09-18 14:50:16 |
system instructions used access system functionality might require privileged ac cess encoded using itype instruction format divided two main classes atomically readmodifywrite control status registers csrs potentially privileged instructions csr instructions described chapter 9 base unprivileged instructions described following section system instructions defined allow simpler implementations always trap single software trap handler sophisticated implementations might execute system instruction hardware two instructions cause precise requested trap supporting execution environment ecall instruction used make service request execution environment eei define parameters service request passed usually defined locations integer register file ebreak instruction used return control debugging environment ecall ebreak previously named scall sbreak instructions functionality encoding renamed reflect used generally call supervisorlevel operating system debugger ebreak primarily designed used debugger cause execution stop fall back debugger ebreak also used standard gcc compiler mark code paths executed another use ebreak support semihosting execution environment in cludes debugger provide services alternate system call interface built around ebreak instruction riscv base isa provide one ebreak instruction riscv semihosting uses special sequence instructions distin guish semihosting ebreak debugger inserted ebreak slli x0 x0 0x1f entry nop ebreak break debugger srai x0 x0 7 nop encoding semihosting call number 7 note three instructions must 32bitwide instructions ie among compressed 16bit instructions described chapter 16 shift nop instructions still considered available use hints semihosting form service call would naturally encoded ecall using existing abi would require debugger able intercept ecalls newer addition debug standard intend move using ecalls standard abi case semihosting share service abi existing standard note arm processors also moved using svc instead bkpt semi hosting calls newer designs | riscv-spec-20191213 | segment16 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.8).jpg?raw=true"
] | 2.8 Environment Call and Breakpoints | RV32ISPEC.pdf#segment16 | 2023-09-18 14:50:16 |
rv32i reserves large encoding space hint instructions usually used commu nicate performance hints microarchitecture hints encoded integer computational instructions rdx0 hence like nop instruction hints change architecturally visible state except advancing pc applicable performance counters implementa tions always allowed ignore encoded hints hint encoding chosen simple implementations ignore hints alto gether instead execute hint regular computational instruction happens mutate architectural state example add hint destination register x0 fivebit rs1 rs2 fields encode arguments hint however simple implementation simply execute hint add rs1 rs2 writes x0 architecturally visible effect table 23 lists rv32i hint code points 91 hint space reserved standard hints none presently defined remainder hint space reserved custom hints standard hints ever defined subspace standard hints presently defined anticipate standard hints eventually include memorysystem spatial temporal locality hints branch prediction hints threadscheduling hints security tags instrumentation flags simulationemulation | riscv-spec-20191213 | segment17 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%202.3.jpg?raw=true"
] | 2.9 HINT Instructions | RV32ISPEC.pdf#segment17 | 2023-09-18 14:50:16 |
zifencei instructionfetch fence version 20 chapter defines zifencei extension includes fencei instruction provides explicit synchronization writes instruction memory instruction fetches hart currently instruction standard mechanism ensure stores visible hart also visible instruction fetches considered include store instruction word instruction majc 19 jit compilers may generate large trace instructions single fencei amortize instruction cache snoopinginvalidation overhead writing translated instructions memory regions known reside icache fencei instruction designed support wide variety implementations sim ple implementation flush local instruction cache instruction pipeline fencei executed complex implementation might snoop instruction data cache every data instruction cache miss use inclusive unified private l2 cache invalidate lines primary instruction cache written local store instruction instruction data caches kept coherent way memory system consists uncached rams fetch pipeline needs flushed fencei fencei instruction previously part base instruction set two main issues driving moving mandatory base although time writing still standard method maintaining instructionfetch coherence first recognized systems fencei expensive implement alternate mechanisms discussed memory model task group particular designs incoherent instruction cache incoherent data cache instruction cache refill snoop coherent data cache caches must completely flushed fencei instruction encountered problem exacerbated multiple levels cache front unified cache outer memory system second instruction powerful enough make available user level unixlike operating system environment fencei synchronizes local hart os reschedule user hart different physical hart fencei would require os execute additional fencei part every context migration reason standard linux abi removed fencei userlevel requires system call maintain instructionfetch coherence allows os minimize number fencei executions required current systems provides forwardcompatibility future improved instructionfetch coherence mechanisms future approaches instructionfetch coherence discussion include providing restricted versions fencei target given address specified rs1 andor allowing software use abi relies machinemode cachemaintenance operations fencei instruction used synchronize instruction data streams riscv guarantee stores instruction memory made visible instruction fetches riscv hart hart executes fencei instruction fencei instruction ensures subsequent instruction fetch riscv hart see previous data stores already visible riscv hart fencei ensure riscv harts instruction fetches observe local hart stores multiprocessor system make store instruction memory visible riscv harts writing hart execute data fence requesting remote riscv harts execute fencei unused fields fencei instruction imm 110 rs1 rd reserved finergrain fences future extensions forward compatibility base implementations shall ignore fields standard software shall zero fields fencei orders stores hart instruction fetches application code rely upon fencei application thread migrated different hart eei provide mechanisms efficient multiprocessor instructionstream synchroniza tion | riscv-spec-20191213 | segment18 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(3).jpg?raw=true"
] | Chapter 3 | RV32ISPEC.pdf#segment18 | 2023-09-18 14:50:16 |
rv32e base integer instruction set version 19 chapter describes draft proposal rv32e base integer instruction set reduced version rv32i designed embedded systems change reduce number integer registers 16 chapter outlines differences rv32e rv32i read chapter 2 rv32e designed provide even smaller base core embedded microcontrollers al though mentioned possibility version 20 document initially resisted defining subset however given demand smallest possible 32bit microcontroller interests preempting fragmentation space defined rv32e fourth standard base isa addition rv32i rv64i rv128i also interest defining rv64e reduce context state highly threaded 64bit processors | riscv-spec-20191213 | segment19 | [] | Chapter 4 | RV32ISPEC.pdf#segment19 | 2023-09-18 14:50:16 |
rv32e reduces integer register count 16 generalpurpose registers x0x15 x0 dedicated zero register found small rv32i core designs upper 16 registers consume around one quarter total area core excluding memories thus removal saves around 25 core area corresponding core power reduction change requires different calling convention abi particular rv32e used softfloat calling convention new embedded abi consideration would work across rv32e rv32i | riscv-spec-20191213 | segment20 | [] | 4.1 RV32E Programmers’ Model | RV32ISPEC.pdf#segment20 | 2023-09-18 14:50:16 |
rv32e uses instructionset encoding rv32i except registers x0x15 provided future standard extensions make use instruction bits freed reduced registerspecifier fields available custom extensions rv32e combined current standard extensions defining f q exten sions 16entry floating point register file combined rv32e considered decided support systems reduced floatingpoint register state intend define zfinx extension makes floatingpoint computations use integer registers removing floatingpoint loads stores moves floating point integer registers | riscv-spec-20191213 | segment21 | [] | 4.2 RV32E Instruction Set | RV32ISPEC.pdf#segment21 | 2023-09-18 14:50:17 |
rv64i base integer instruction set version 21 chapter describes rv64i base integer instruction set builds upon rv32i variant described chapter 2 chapter presents differences rv32i read conjunction earlier chapter | riscv-spec-20191213 | segment22 | [] | Chapter 5 | RV32ISPEC.pdf#segment22 | 2023-09-18 14:50:17 |
rv64i widens integer registers supported user address space 64 bits xlen64 figure 21 | riscv-spec-20191213 | segment23 | [] | 5.1 Register State | RV32ISPEC.pdf#segment23 | 2023-09-18 14:50:17 |
integer computational instructions operate xlenbit values additional instruction vari ants provided manipulate 32bit values rv64i indicated w suffix opcode w instructions ignore upper 32 bits inputs always produce 32bit signed values ie bits xlen1 31 equal compiler calling convention maintain invariant 32bit values held signextended format 64bit registers even 32bit unsigned integers extend bit 31 bits 63 32 consequently conversion unsigned signed 32bit integers noop conversion signed 32bit integer signed 64bit integer existing 64bit wide sltu unsigned branch compares still operate correctly unsigned 32bit integers invariant similarly existing 64bit wide logical operations 32bit signextended integers preserve signextension property new instructions add wsubwsxxw required addition shifts ensure reasonable performance 32bit values integer registerimmediate instructions addiw rv64i instruction adds signextended 12bit immediate register rs1 produces proper signextension 32bit result rd overflows ignored result low 32 bits result signextended 64 bits note addiw rd rs1 0 writes signextension lower 32 bits register rs1 register rd assembler pseudoinstruction sextw shifts constant encoded specialization itype format using instruction opcode rv32i operand shifted rs1 shift amount encoded lower 6 bits iimmediate field rv64i right shift type encoded bit 30 slli logical left shift zeros shifted lower bits srli logical right shift zeros shifted upper bits srai arithmetic right shift original sign bit copied vacated upper bits slliw srliw sraiw rv64ionly instructions analogously defined operate 32bit values produce signed 32bit results slliw srliw sraiw encodings imm 5 0 reserved previously slliw srliw sraiw imm 5 0 defined cause illegal in struction exceptions whereas marked reserved backwardscompatible change lui load upper immediate uses opcode rv32i lui places 20bit uimmediate bits 3112 register rd places zero lowest 12 bits 32bit result signextended 64 bits auipc add upper immediate pc uses opcode rv32i auipc used build pc relative addresses uses utype format auipc appends 12 loworder zero bits 20bit uimmediate signextends result 64 bits adds address auipc instruction places result register rd integer registerregister operations addw subw rv64ionly instructions defined analogously add sub operate 32bit values produce signed 32bit results overflows ignored low 32bits result signextended 64bits written destination register sll srl sra perform logical left logical right arithmetic right shifts value register rs1 shift amount held register rs2 rv64i low 6 bits rs2 considered shift amount sllw srlw sraw rv64ionly instructions analogously defined operate 32bit values produce signed 32bit results shift amount given rs2 40 | riscv-spec-20191213 | segment24 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(5.2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(5.2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(5.2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra4(5.2).jpg?raw=true"
] | 5.2 Integer Computational Instructions | RV32ISPEC.pdf#segment24 | 2023-09-18 14:50:17 |
rv64i extends address space 64 bits execution environment define portions address space legal access ld instruction loads 64bit value memory register rd rv64i lw instruction loads 32bit value memory signextends 64 bits storing register rd rv64i lwu instruction hand zeroextends 32bit value memory rv64i lh lhu defined analogously 16bit values lb lbu 8bit values sd sw sh sb instructions store 64bit 32bit 16bit 8bit values low bits register rs2 memory respectively | riscv-spec-20191213 | segment25 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(5.3).jpg?raw=true"
] | 5.3 Load and Store Instructions | RV32ISPEC.pdf#segment25 | 2023-09-18 14:50:17 |
instructions microarchitectural hints rv32i see section 29 also hints rv64i additional computational instructions rv64i expand standard custom hint encoding spaces table 51 lists rv64i hint code points 91 hint space reserved standard hints none presently defined remainder hint space reserved custom hints standard hints ever defined subspace | riscv-spec-20191213 | segment26 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%205.1.jpg?raw=true"
] | 5.4 HINT Instructions | RV32ISPEC.pdf#segment26 | 2023-09-18 14:50:17 |
rv128i base integer instruction set version 17 one mistake made computer design difficult re cover fromnot enough address bits memory addressing memory man agement bell strecker isca3 1976 chapter describes rv128i variant riscv isa supporting flat 128bit address space variant straightforward extrapolation existing rv32i rv64i designs primary reason extend integer register width support larger address spaces clear flat address space larger 64 bits required time writing fastest supercomputer world measured top500 benchmark 1 pb dram would require 50 bits address space dram resided single address space warehousescale computers already contain even larger quantities dram new dense solidstate nonvolatile memories fast interconnect technologies might drive demand even larger memory spaces exascale systems research targeting 100 pb memory systems occupy 57 bits address space historic rates growth possible greater 64 bits address space might required 2030 history suggests whenever becomes clear 64 bits address space needed architects repeat intensive debates alternatives extending address space including segmentation 96bit address spaces software workarounds finally flat 128 bit address spaces adopted simplest best solution frozen rv128 spec time might need evolve design based actual usage 128bit address spaces rv128i builds upon rv64i way rv64i builds upon rv32i integer registers extended 128 bits ie xlen128 integer computational instructions unchanged defined operate xlen bits rv64i w integer instructions operate 32bit values low bits register retained sign extend results bit 31 bit 127 new set integer instructions added operate 64bit values held low bits 128bit integer registers sign extend results bit 63 bit 127 instructions consume two major opcodes opimm64 op64 standard 32bit encoding improve compatibility rv64 reverse rv32 rv64 handled might change decoding around rename rv64i add 64bit addd add 128bit addq previously op64 major opcode renamed op128 major opcode shifts immediate sllisrlisrai encoded using low 7 bits iimmediate variable shifts sllsrlsra use low 7 bits shift amount source register ldu load double unsigned instruction added using existing load major opcode along new lq sq instructions load store quadword values sq added store major opcode lq added miscmem major opcode floatingpoint instruction set unchanged although 128bit q floatingpoint extension support fmvxq fmvqx instructions together additional fcvt instructions 128bit integer format | riscv-spec-20191213 | segment27 | [] | Chapter 6 | RV32ISPEC.pdf#segment27 | 2023-09-18 14:50:17 |
standard extension integer multiplication division version 20 chapter describes standard integer multiplication division instruction extension named contains instructions multiply divide values held two integer registers separate integer multiply divide base simplify lowend implementations applications integer multiply divide operations either infrequent better handled attached accelerators | riscv-spec-20191213 | segment28 | [] | Chapter 7 | RV32ISPEC.pdf#segment28 | 2023-09-18 14:50:17 |
mul performs xlenbitxlenbit multiplication rs1 rs2 places lower xlen bits destination register mulh mulhu mulhsu perform multiplication re turn upper xlen bits full 2xlenbit product signedsigned unsignedunsigned signed rs1unsigned rs2 multiplication respectively high low bits product required recommended code sequence mulh u rdh rs1 rs2 mul rdl rs1 rs2 source register specifiers must order rdh rs1 rs2 microarchitectures fuse single multiply operation instead performing two separate multiplies mulhsu used multiword signed multiplication multiply mostsignificant word multiplicand contains sign bit lesssignificant words multiplier unsigned mulw rv64 instruction multiplies lower 32 bits source registers placing signextension lower 32 bits result destination register rv64 mul used obtain upper 32 bits 64bit product signed arguments must proper 32bit signed values whereas unsigned arguments must upper 32 bits clear arguments known sign zeroextended alternative shift arguments left 32 bits use mulh u | riscv-spec-20191213 | segment28 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(7.1).jpg?raw=true"
] | 7.1 Multiplication Operations | RV32ISPEC.pdf#segment28 | 2023-09-18 14:50:17 |
div divu perform xlen bits xlen bits signed unsigned integer division rs1 rs2 rounding towards zero rem remu provide remainder corresponding division operation rem sign result equals sign dividend signed unsigned division holds dividend divisor quotient remainder quotient remainder required division recommended code sequence div u rdq rs1 rs2 rem u rdr rs1 rs2 rdq rs1 rs2 microarchitectures fuse single divide operation instead performing two separate divides divw divuw rv64 instructions divide lower 32 bits rs1 lower 32 bits rs2 treating signed unsigned integers respectively placing 32bit quotient rd signextended 64 bits remw remuw rv64 instructions provide corresponding signed unsigned remainder operations respectively remw remuw always signextend 32bit result 64 bits including divide zero semantics division zero division overflow summarized table 71 quotient division zero bits set remainder division zero equals dividend signed division overflow occurs mostnegative integer divided 1 quotient signed division overflow equal dividend remainder zero unsigned division overflow occur considered raising exceptions integer divide zero exceptions causing trap execution environments however would arithmetic trap standard isa floatingpoint exceptions set flags write default values cause traps would require language implementors interact execution environment trap handlers case language standards mandate dividebyzero exception must cause immediate control flow change single branch instruction needs added divide operation branch instruction inserted divide normally predictably taken adding little runtime overhead value bits set returned unsigned signed divide zero simplify divider circuitry value 1s natural value return unsigned divide representing largest unsigned number also natural result simple unsigned divider implementations signed division often implemented using unsigned division circuit specifying overflow result simplifies hardware | riscv-spec-20191213 | segment29 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(7.2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%207.1.jpg?raw=true"
] | 7.2 Division Operations | RV32ISPEC.pdf#segment29 | 2023-09-18 14:50:17 |
standard extension atomic instructions version 21 standard atomicinstruction extension named contains instructions atomically readmodifywrite memory support synchronization multiple riscv harts running memory space two forms atomic instruction provided loadreservedstore conditional instructions atomic fetchandop memory instructions types atomic in struction support various memory consistency orderings including unordered acquire release sequentially consistent semantics instructions allow riscv support rcsc memory consistency model 5 much debate language community architecture community appear finally settled release consistency standard memory consistency model riscv atomic support built around model | riscv-spec-20191213 | segment30 | [] | Chapter 8 | RV32ISPEC.pdf#segment30 | 2023-09-18 14:50:18 |
base riscv isa relaxed memory model fence instruction used impose additional ordering constraints address space divided execution environment memory io domains fence instruction provides options order accesses one two address domains provide efficient support release consistency 5 atomic instruction two bits aq rl used specify additional memory ordering constraints viewed riscv harts bits order accesses one two address domains memory io depending address domain atomic instruction accessing ordering constraint implied accesses domain fence instruction used order across domains bits clear additional ordering constraints imposed atomic memory op eration aq bit set atomic memory operation treated acquire access ie following memory operations riscv hart observed take place acquire memory operation rl bit set atomic memory operation treated release access ie release memory operation observed take place earlier memory operations riscv hart aq rl bits set atomic memory operation sequentially consistent observed happen earlier memory operations later memory operations riscv hart address domain | riscv-spec-20191213 | segment31 | [] | 8.1 Specifying Ordering of Atomic Instructions | RV32ISPEC.pdf#segment31 | 2023-09-18 14:50:18 |
complex atomic memory operations single memory word doubleword performed loadreserved lr storeconditional sc instructions lrw loads word address rs1 places signextended value rd registers reservation seta set bytes subsumes bytes addressed word scw conditionally writes word rs2 address rs1 scw succeeds reservation still valid reservation set contains bytes written scw succeeds instruction writes word rs2 memory writes zero rd scw fails instruction write memory writes nonzero value rd regardless success failure executing scw instruction invalidates reservation held hart lrd scd act analogously doublewords available rv64 rv64 lrw scw signextend value placed rd compareandswap cas lrsc used build lockfree data structures extensive discussion opted lrsc several reasons 1 cas suffers aba problem lrsc avoids monitors accesses address rather checking changes data value 2 cas would also require new integer instruction for mat support three source operands address compare value swap value well different memory system message format would complicate microarchitectures 3 furthermore avoid aba problem systems provide doublewide cas dwcas allow counter tested incremented along data word requires reading five regis ters writing two one instruction also new larger memory system message type complicating implementations 4 lrsc provides efficient implementation many primitives requires one load opposed two cas one load cas instruction obtain value speculative computation second load part cas instruction check value unchanged updating main disadvantage lrsc cas livelock avoid certain cir cumstances architected guarantee eventual forward progress described an concern whether influence current x86 architecture dwcas complicate porting synchronization libraries software assumes dwcas basic machine primitive possible mitigating factor recent addition transactional memory instructions x86 might cause move away dwcas generally multiword atomic primitive desirable still considerable debate form take guaranteeing forward progress adds complexity system current thoughts include small limitedcapacity transactional memory buffer along lines original transactional memory proposals optional standard extension failure code value 1 reserved encode unspecified failure failure codes reserved time portable software assume failure code nonzero reserve failure code 1 mean unspecified simple implementations may return value using existing mux required sltsltu instructions specific failure codes might defined future versions extensions isa lr sc extension requires address held rs1 naturally aligned size operand ie eightbyte aligned 64bit words fourbyte aligned 32bit words address naturally aligned addressmisaligned exception accessfault exception generated accessfault exception generated memory access would otherwise able complete except misalignment misaligned access emulated emulating misaligned lrsc sequences impractical systems misaligned lrsc sequences also raise possibility accessing multiple reservation sets present definitions provide implementation register arbitrarily large reservation set lr provided reser vation set includes bytes addressed data word doubleword sc pair recent lr program order sc may succeed store another hart reservation set observed occurred lr sc sc lr program order sc may succeed write device hart bytes accessed lr instruction observed occurred lr sc note lr might different effective address data size reserved sc address part reservation set following model systems memory translation sc allowed succeed earlier lr reserved location using alias different virtual address also allowed fail virtual address different accommodate legacy devices buses writes devices riscv harts required invalidate reservations overlap bytes accessed lr writes required invalidate reservation access bytes reservation set sc must fail address within reservation set recent lr program order sc must fail store reservation set another hart observed occur lr sc sc must fail write device bytes accessed lr observed occur lr sc device writes reservation set write bytes accessed lr sc may may fail sc must fail another sc address lr sc program order precise statement atomicity requirements successful lrsc sequences defined atomicity axiom section 141 platform provide means determine size shape reservation set platform specification may constrain size shape reservation set example unix platform expected require main memory reservation set fixed size contiguous naturally aligned greater virtual memory page size storeconditional instruction scratch word memory used forcibly invalidate existing load reservation preemptive context switch necessary changing virtual physical address mappings migrating pages might contain active reservation invalidation hart reservation executes lr sc imply hart hold one reservation time sc pair recent lr lr next following sc program order restriction atomicity axiom section 141 ensures software runs correctly expected common implementations operate manner sc instruction never observed another riscv hart lr instruction established reservation lrsc sequence given acquire semantics setting aq bit lr instruction lrsc sequence given release semantics setting rl bit sc instruction setting aq bit lr instruction setting aq rl bit sc instruction makes lrsc sequence sequentially consistent meaning reordered earlier later memory operations hart neither bit set lr sc lrsc sequence observed occur surrounding memory operations riscv hart appropriate lrsc sequence used implement parallel reduction operation software set rl bit lr instruction unless aq bit also set software set aq bit sc instruction unless rl bit also set lrrl scaq instructions guaranteed provide stronger ordering bits clear may result lower performance lrsc used construct lockfree data structures example using lrsc implement compareandswap function shown figure 81 inlined compareandswap functionality need take four instructions | riscv-spec-20191213 | segment32 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(8.2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%208.1.jpg?raw=true"
] | 8.2 Load-Reserved/Store-Conditional Instructions | RV32ISPEC.pdf#segment32 | 2023-09-18 14:50:18 |
standard extension defines constrained lrsc loops following properties loop comprises lrsc sequence code retry sequence case failure must comprise 16 instructions placed sequentially memory lrsc sequence begins lr instruction ends sc instruction dynamic code executed lr sc instructions contain instructions base instruction set excluding loads stores backward jumps taken backward branches jalr fence fencei system instructions c extension supported compressed forms aforementioned instructions also permitted code retry failing lrsc sequence contain backwards jumps andor branches repeat lrsc sequence otherwise constraint code lr sc lr sc addresses must lie within memory region lrsc eventuality property execution environment responsible communicating regions property sc must effective address data size latest lr executed hart lrsc sequences lie within constrained lrsc loops unconstrained unconstrained lrsc sequences might succeed attempts implementations might never succeed implementations restricted length lrsc loops fit within 64 contiguous instruction bytes base isa avoid undue restrictions instruction cache tlb size associativity simi larly disallowed loads stores within loops avoid restrictions datacache associativity simple implementations track reservation within private cache restrictions branches jumps limit time spent sequence floating point operations integer multiplydivide disallowed simplify operating system emulation instructions implementations lacking appropriate hardware support software forbidden using unconstrained lrsc sequences portable software must detect case sequence repeatedly fails fall back alternate code sequence rely unconstrained lrsc sequence implementations permitted unconditionally fail unconstrained lrsc sequence hart h enters constrained lrsc loop execution environment must guarantee one following events eventually occurs h hart executes successful sc reservation set lr instruction h constrained lrsc loops hart executes unconditional store amo instruction reservation set lr instruction h constrained lrsc loop device system writes reservation set h executes branch jump exits constrained lrsc loop h traps note definitions permit implementation fail sc instruction occasionally reason provided aforementioned guarantee violated consequence eventuality guarantee harts execution environment executing constrained lrsc loops harts devices execution environment execute unconditional store amo reservation set least one hart eventually exit constrained lrsc loop contrast harts devices continue write reservation set guaranteed hart exit lrsc loop loads loadreserved instructions impede progress harts lrsc sequences note constraint implies among things loads load reserved instructions executed harts possibly within core impede lrsc progress indefinitely example cache evictions caused another hart sharing cache impede lrsc progress indefinitely typically implies reservations tracked independently evictions shared cache similarly cache misses caused speculative execution within hart impede lrsc progress indefinitely definitions admit possibility sc instructions may spuriously fail imple mentation reasons provided progress eventually made one advantage cas guarantees hart eventually makes progress whereas lrsc atomic sequence could livelock indefinitely systems avoid concern added architectural guarantee livelock freedom certain lrsc sequences earlier versions specification imposed stronger starvationfreedom guarantee how ever weaker livelockfreedom guarantee sufficient implement c11 c11 lan guages substantially easier provide microarchitectural styles | riscv-spec-20191213 | segment33 | [] | 8.3 Eventual Success of Store-Conditional Instructions | RV32ISPEC.pdf#segment33 | 2023-09-18 14:50:19 |
atomic memory operation amo instructions perform readmodifywrite operations mul tiprocessor synchronization encoded rtype instruction format amo in structions atomically load data value address rs1 place value register rd apply binary operator loaded value original value rs2 store result back address rs1 amos either operate 64bit rv64 32bit words memory rv64 32bit amos always signextend value placed rd amos extension requires address held rs1 naturally aligned size operand ie eightbyte aligned 64bit words fourbyte aligned 32bit words address naturally aligned addressmisaligned exception accessfault exception generated accessfault exception generated memory access would otherwise able complete except misalignment misaligned access emulated zam extension described chapter 22 relaxes requirement specifies semantics misaligned amos operations supported swap integer add bitwise bitwise bitwise xor signed unsigned integer maximum minimum without ordering constraints amos used implement parallel reduction operations typically return value would discarded writing x0 provided fetchandop style atomic primitives scale highly parallel systems better lrsc cas simple microarchitecture implement amos using lrsc primi tives provided implementation guarantee amo eventually completes complex implementations might also implement amos memory controllers optimize away fetching original value destination x0 set amos chosen support c11c11 atomic memory operations effi ciently also support parallel reductions memory another use amos provide atomic updates memorymapped device registers eg setting clearing toggling bits io space help implement multiprocessor synchronization amos optionally provide release consis tency semantics aq bit set later memory operations riscv hart observed take place amo conversely rl bit set riscv harts observe amo memory accesses preceding amo riscv hart setting aq rl bit amo makes sequence sequentially consistent meaning reordered earlier later memory operations hart amos designed implement c11 c11 memory models efficiently al though fence r rw instruction suffices implement acquire operation fence rw w suffices implement release imply additional unnecessary ordering compared amos corresponding aq rl bit set example code sequence critical section guarded testandtestandset spinlock shown figure 82 note first amo marked aq order lock acquisition critical section second amo marked rl order critical section lock relinquishment recommend use amo swap idiom shown lock acquire release simplify implementation speculative lock elision 16 instructions extension also used provide sequentially consistent loads stores sequentially consistent load implemented lr aq rl set sequentially consistent store implemented amoswap writes old value x0 aq rl set | riscv-spec-20191213 | segment34 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(8.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%208.2.jpg?raw=true"
] | 8.4 Atomic Memory Operations | RV32ISPEC.pdf#segment34 | 2023-09-18 14:50:19 |
zicsr control status register csr instructions version 20 riscv defines separate address space 4096 control status registers associated hart chapter defines full set csr instructions operate csrs csrs primarily used privileged architecture several uses unprivi leged code including counters timers floatingpoint status counters timers longer considered mandatory parts standard base isas csr instructions required access moved base isa chapter separate chapter | riscv-spec-20191213 | segment35 | [] | Chapter 9 | RV32ISPEC.pdf#segment35 | 2023-09-18 14:50:19 |
csr instructions atomically readmodifywrite single csr whose csr specifier encoded 12bit csr field instruction held bits 3120 immediate forms use 5bit zeroextended immediate encoded rs1 field csrrw atomic readwrite csr instruction atomically swaps values csrs integer registers csrrw reads old value csr zeroextends value xlen bits writes integer register rd initial value rs1 written csr rdx0 instruction shall read csr shall cause side effects might occur csr read csrrs atomic read set bits csr instruction reads value csr zero extends value xlen bits writes integer register rd initial value integer register rs1 treated bit mask specifies bit positions set csr bit high rs1 cause corresponding bit set csr csr bit writable bits csr unaffected though csrs might side effects written csrrc atomic read clear bits csr instruction reads value csr zero extends value xlen bits writes integer register rd initial value integer register rs1 treated bit mask specifies bit positions cleared csr bit high rs1 cause corresponding bit cleared csr csr bit writable bits csr unaffected csrrs csrrc rs1x0 instruction write csr shall cause side effects might otherwise occur csr write raising illegal instruction exceptions accesses readonly csrs csrrs csrrc always read addressed csr cause read side effects regardless rs1 rd fields note rs1 specifies register holding zero value x0 instruction still attempt write unmodified value back csr cause attendant side effects csrrw rs1x0 attempt write zero destination csr csrrwi csrrsi csrrci variants similar csrrw csrrs csrrc re spectively except update csr using xlenbit value obtained zeroextending 5bit unsigned immediate uimm 40 field encoded rs1 field instead value integer register csrrsi csrrci uimm 40 field zero instructions write csr shall cause side effects might otherwise occur csr write csrrwi rdx0 instruction shall read csr shall cause side effects might occur csr read csrrsi csrrci always read csr cause read side effects regardless rd rs1 fields csrs defined far architectural side effects reads beyond raising illegal instruction exceptions disallowed accesses custom extensions might add csrs side effects reads csrs instructionsretired counter instret may modified side effects instruction execution cases csr access instruction reads csr reads value prior execution instruction csr access instruction writes csr write done instead increment particular value written instret one instruction value read following instruction assembler pseudoinstruction read csr csrr rd csr encoded csrrs rd csr x0 assembler pseudoinstruction write csr csrw csr rs1 encoded csrrw x0 csr rs1 csrwi csr uimm encoded csrrwi x0 csr uimm assembler pseudoinstructions defined set clear bits csr old value required csrscsrc csr rs1 csrsicsrci csr uimm csr access ordering given hart explicit implicit csr access performed program order respect instructions whose execution behavior affected state accessed csr particular csr access performed execution prior instructions program order whose behavior modifies modified csr state execution subsequent instructions program order whose behavior modifies modified csr state furthermore csr read access instruction returns accessed csr state execution instruction csr write access instruction updates accessed csr state execution instruction program order hold csr accesses weakly ordered local hart harts may observe csr accesses order different program order addition csr accesses ordered respect explicit memory accesses unless csr access modifies execution behavior instruction performs explicit memory access unless csr access explicit memory access ordered either syntactic dependencies defined memory model ordering requirements defined memoryordering pmas section volume ii manual enforce ordering cases software execute fence instruction relevant accesses purposes fence instruction csr read accesses classified device input csr write accesses classified device output informally csr space acts weakly ordered memorymapped io region defined memoryordering pmas section volume ii manual result order csr accesses respect accesses constrained mechanisms constrain order memorymapped io accesses region csrordering constraints imposed primarily support ordering main memory memorymapped io accesses respect reads time csr exception time cycle mcycle csrs csrs defined thus far volumes ii specification directly accessible harts devices cause side effects visible harts devices thus accesses csrs aforementioned three freely reordered respect fence instructions without violating specification csr accesses cause side effects ordering constraints apply order initiation side effects necessarily apply order completion side effects hardware platform may define accesses certain csrs strongly ordered defined memoryordering pmas section volume ii manual accesses strongly ordered csrs stronger ordering constraints respect accesses weakly ordered csrs accesses memorymapped io regions | riscv-spec-20191213 | segment36 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(9.1).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%209.1.jpg?raw=true"
] | 9.1 CSR Instructions | RV32ISPEC.pdf#segment36 | 2023-09-18 14:50:19 |
counters riscv isas provide set 3264bit performance counters timers accessible via unprivileged xlen readonly csr registers 0xc000xc1f upper 32 bits accessed via csr registers 0xc800xc9f rv32 first three cycle time instret dedicated functions cycle count realtime clock instructionsretired respectively remaining counters implemented provide programmable event counting | riscv-spec-20191213 | segment37 | [] | Chapter 10 | RV32ISPEC.pdf#segment37 | 2023-09-18 14:50:19 |
rv32i provides number 64bit readonly userlevel counters mapped 12 bit csr address space accessed 32bit pieces using csrrs instructions rv64i csr instructions manipulate 64bit csrs particular rdcycle rdtime rdinstret pseudoinstructions read full 64 bits cycle time instret counters hence rdcycleh rdtimeh rdinstreth instructions required rv64i execution environments might prohibit access counters impede timing sidechannel attacks rdcycle pseudoinstruction reads low xlen bits cycle csr holds count number clock cycles executed processor core hart running arbitrary start time past rdcycleh rv32i instruction reads bits 6332 cycle counter underlying 64bit counter never overflow practice rate cycle counter advances depend implementation operating environment execution environment provide means determine current rate cyclessecond cycle counter incrementing rdcycle intended return number cycles executed processor core hart precisely defining core difficult given implementation choices eg amd bulldozer precisely defining clock cycle also difficult given range implementations including software emulations intent rdcycle used performance monitoring along performance counters particular one hartcore one would expect cyclecountinstructionsretired measure cpi hart cores exposed software implementor might choose pretend multiple harts one physical core running separate cores one hartcore provide separate cycle counters hart might make sense simple barrel processor eg cdc 6600 peripheral processors interhart timing interactions non existent minimal one hartcore dynamic multithreading generally possible separate cycles per hart especially smt might possible define separate performance counter tried capture number cycles particular hart running definition would fuzzy cover possible threading implementations example count cycles instruction issued execution hart andor cycles instruction retired include cycles hart occupying machine resources execute due stalls harts went execution likely would needed understandable performance stats complexity defining perhart cycle count also need case total percore cycle count tuning multithreaded code led standardizing percore cycle counter also happens work well common single hartcore case standardizing happens sleep practical given sleep means standardized across execution environments entire core paused entirely clock gated powereddown deep sleep executing clock cycles cycle count increasing per spec many details eg whether clock cycles required reset processor waking powerdown event counted considered executionenvironmentspecific details even though precise definition works platforms still useful facility platforms imprecise common usually correct standard better standard intent rdcycle primarily performance monitoringtuning specification written goal mind rdtime pseudoinstruction reads low xlen bits time csr counts wallclock real time passed arbitrary start time past rdtimeh rv32ionly in struction reads bits 6332 realtime counter underlying 64bit counter never overflow practice execution environment provide means determining period realtime counter secondstick period must constant realtime clocks harts single user application synchronized within one tick realtime clock environment provide means determine accuracy clock simple platforms cycle count might represent valid implementation rdtime case platforms implement rdtime instruction alias rdcycle make code portable rather using rdcycle measure wallclock time rdinstret pseudoinstruction reads low xlen bits instret csr counts number instructions retired hart arbitrary start point past rdinstreth rv32ionly instruction reads bits 6332 instruction counter underlying 64bit counter never overflow practice recommend provision basic counters implementations essential basic performance analysis adaptive dynamic optimization allow application work realtime streams additional counters provided help diagnose performance problems made accessible userlevel application code low overhead required counters 64 bits wide even rv32 otherwise difficult software determine values overflowed lowend implementation upper 32 bits counter implemented using software counters incremented trap handler triggered overflow lower 32 bits sample code described shows full 64bit width value safely read using individual 32bit instructions applications important able read multiple counters instant time run multitasking environment user thread suffer context switch attempting read counters one solution user thread read realtime counter reading counters determine context switch occurred middle sequence case reads retried considered adding output latches allow user thread snapshot counter values atomically would increase size user context especially implementations richer set counters | riscv-spec-20191213 | segment38 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(10.1).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%2010.1.jpg?raw=true"
] | 10.1 Base Counters and Timers | RV32ISPEC.pdf#segment38 | 2023-09-18 14:50:20 |
csr space allocated 29 additional unprivileged 64bit hardware performance coun ters hpmcounter3hpmcounter31 rv32 upper 32 bits performance counters accessible via additional csrs hpmcounter3hhpmcounter31h counters count platform specific events configured via additional privileged registers number width additional counters set events count platformspecific privileged architecture manual describes privileged csrs controlling access coun ters set events counted would useful eventually standardize event settings count isalevel metrics number floatingpoint instructions executed example possibly common microarchitectural metrics l1 instruction cache misses | riscv-spec-20191213 | segment39 | [] | 10.2 Hardware Performance Counters | RV32ISPEC.pdf#segment39 | 2023-09-18 14:50:20 |
f standard extension singleprecision floatingpoint version 22 chapter describes standard instructionset extension singleprecision floatingpoint named f adds singleprecision floatingpoint computational instructions compliant ieee 7542008 arithmetic standard 7 f extension depends zicsr extension control status register access | riscv-spec-20191213 | segment40 | [] | Chapter 11 | RV32ISPEC.pdf#segment40 | 2023-09-18 14:50:20 |
f extension adds 32 floatingpoint registers f0f31 32 bits wide floatingpoint control status register fcsr contains operating mode exception status floatingpoint unit additional state shown figure 111 use term flen describe width floatingpoint registers riscv isa flen32 f singleprecision floatingpoint extension floatingpoint instructions operate values floatingpoint register file floatingpoint load store instructions transfer floatingpoint values registers memory instructions transfer values integer register file also provided considered unified register file integer floatingpoint values simplifies software register allocation calling conventions reduces total user state however split organization increases total number registers accessible given instruction width simplifies provision enough regfile ports wide superscalar issue supports decoupled floatingpointunit architectures simplifies use internal floatingpoint encoding techniques compiler support calling conventions split register file architectures well understood using dirty bits floatingpoint register file state reduce contextswitch overhead | riscv-spec-20191213 | segment41 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%2011.1.jpg?raw=true"
] | 11.1 F Register State | RV32ISPEC.pdf#segment41 | 2023-09-18 14:50:20 |
floatingpoint control status register fcsr riscv control status register csr 32bit readwrite register selects dynamic rounding mode floatingpoint arith metic operations holds accrued exception flags shown figure 112 fcsr register read written frcsr fscsr instructions assembler pseudoinstructions built underlying csr access instructions frcsr reads fcsr copying integer register rd fscsr swaps value fcsr copying original value integer register rd writing new value obtained integer register rs1 fcsr fields within fcsr also accessed individually different csr addresses separate assembler pseudoinstructions defined ccesses frrm instruction reads rounding mode field f rm nd c opies nto l eastsignificant th ree bi ts integer register rd zero bits fsrm swaps value frm copying original value integer register rd writing new value obtained three leastsignificant b integer register rs1 frm frflags fsflags defined nalogously f accrued exception flags field fflags bits 318 fcsr reserved standard extensions including l standard extension decimal floatingpoint f hese e xtensions n ot p resent mplementations shall ignore writes bits supply zero value read standard software preserve contents bits floatingpoint operations use either static rounding mode encoded instruction dynamic rounding mode held frm rounding modes encoded shown table 111 value 111 instruction rm field selects dynamic rounding mode held f rm frm set invalid value 101111 subsequent attempt execute floatingpoint peration w ith dynamic rounding mode raise illegal instruction exception instructions including widening conversions rm field b ut n evertheless u naffected th e ro unding mo de software set rm field rne 000 c99 language standard effectively mandates provision dynamic rounding mode reg ister typical implementations writes dynamic rounding mode csr state serialize pipeline static rounding modes used implement specialized arithmetic operations often switch frequently different rounding modes accrued exception flags indicate exception conditions arisen floatingpoint arithmetic instruction since field last reset software shown table 1 12 base riscv isa support generating trap setting floatingpoint exception flag allowed standard support traps floatingpoint exceptions base isa instead require explicit checks flags software considered adding branches controlled directly contents floatingpoint accrued exception flags ultimately chose omit instructions keep isa simple | riscv-spec-20191213 | segment42 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%2011.2.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.2.jpg?raw=true"
] | 11.2 Floating-Point Control and Status Register | RV32ISPEC.pdf#segment42 | 2023-09-18 14:50:20 |
except otherwise stated result floatingpoint operation nan canonical nan canonical nan positive sign significand bits clear except msb aka quiet bit singleprecision floatingpoint corresponds pattern 0x7fc00000 considered propagating nan payloads recommended standard decision would increased hardware cost moreover since feature optional standard used portable code implementors free provide nan payload propagation scheme nonstandard exten sion enabled nonstandard operating mode however canonical nan scheme described must always supported default mode require implementations return standardmandated default values case ex ceptional conditions without intervention part userlevel software unlike alpha isa floatingpoint trap barriers believe full hardware handling exceptional cases become common wish avoid complicating userlevel isa opti mize approaches implementations always trap machinemode software handlers provide exceptional default values | riscv-spec-20191213 | segment43 | [] | 11.3 NaN Generation and Propagation | RV32ISPEC.pdf#segment43 | 2023-09-18 14:50:20 |
operations subnormal numbers handled accordance ieee 7542008 standard parlance ieee standard tininess detected rounding detecting tininess rounding results fewer spurious underflow signals | riscv-spec-20191213 | segment44 | [] | 11.4 Subnormal Arithmetic | RV32ISPEC.pdf#segment44 | 2023-09-18 14:50:20 |
floatingpoint loads stores use baseoffset addressing mode integer base isa base address register rs1 12bit signed byte offset flw instruction loads singleprecision floatingpoint value memory floatingpoint register rd fsw stores singleprecision value floatingpoint register rs2 memory flw fsw guaranteed execute atomically effective address naturally aligned flw fsw modify bits transferred particular payloads noncanonical nans preserved | riscv-spec-20191213 | segment45 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.5).jpg?raw=true"
] | 11.5 Single-Precision Load and Store Instructions | RV32ISPEC.pdf#segment45 | 2023-09-18 14:50:20 |
floatingpoint arithmetic instructions one two source operands use rtype format opfp major opcode fadds fmuls perform singleprecision floatingpoint addition multiplication respectively rs1 rs2 fsubs performs singleprecision floating point subtraction rs2 rs1 fdivs performs singleprecision floatingpoint division rs1 rs2 fsqrts computes square root rs1 case result written rd 2bit floatingpoint format field fmt encoded shown table 113 set 00 instructions f extension floatingpoint perations hat p erform r ounding c elect r ounding ode u sing rm field encoding shown table 111 floatingpoint minimumnumber maximumnumber instructions fmins fmaxs write respectively smaller larger rs1 rs2 rd purposes instructions value 00 considered less value 00 inputs nans result canonical nan one operand nan result nonnan operand signaling nan inputs set invalid operation exception flag even result nan note version 22 f extension fmins fmaxs instructions amended implement proposed ieee 754201x minimumnumber maximumnumber operations rather ieee 7542008 minnum maxnum operations operations differ handling signaling nans floatingpoint fused multiplyadd instructions require new standard instruction format r4type instructions specify three source registers rs1 rs2 rs3 destination register rd format used floatingpoint fused multiplyadd instructions fmadds multiplies values rs1 rs2 adds value rs3 writes final result rd fmadds computes rs1rs2 rs3 fmsubs multiplies values rs1 rs2 subtracts value rs3 writes final result rd fmsubs computes rs1rs2 rs3 fnmsubs multiplies values rs1 rs2 negates product adds value rs3 writes final result rd fnmsubs computes rs1rs2 rs3 fnmadds multiplies values rs1 rs2 negates product subtracts value rs3 writes final result rd fnmadds computes rs1rs2 rs3 fnmsub fnmadd instructions counterintuitively named owing naming corresponding instructions mipsiv mips instructions defined negate sum rather negating product riscv instructions naming scheme rational time two definitions differ respect signedzero results riscv definition matches behavior x86 arm fused multiplyadd instructions unfortunately riscv fnmsub fnmadd instruction names swapped compared x86 arm fused multiplyadd fma instructions consume large part 32bit instruction en coding space alternatives considered restrict fma use dynamic rounding modes static rounding modes useful code exploits lack product rounding another alternative would use rd provide rs3 would require additional move instructions common sequences current design still leaves large portion 32bit encoding space open avoiding fma nonorthogonal fused multiplyadd instructions must set invalid operation exception flag multi plicands zero even addend quiet nan ieee 7542008 standard permits require raising invalid exception operation 0 qnan | riscv-spec-20191213 | segment46 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.3.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.6).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(11.6).jpg?raw=true"
] | 11.6 Single-Precision Floating-Point Computational Instructions | RV32ISPEC.pdf#segment46 | 2023-09-18 14:50:21 |
floatingpointtointeger integertofloatingpoint conversion instructions encoded opfp major opcode space fcvtws fcvtls converts floatingpoint number floating point register rs1 signed 32bit 64bit integer respectively integer register rd fcvtsw fcvtsl converts 32bit 64bit signed integer respectively integer register rs1 floatingpoint number floatingpoint register rd fcvtwus fcvtlus fcvtswu fcvtslu variants convert unsigned integer values xlen 32 fcvtw u s signextends 32bit result destination register width fcvtl u s fcvtsl u rv64only instructions rounded result representable destination format clipped nearest value invalid flag set table 114 gives range valid inputs fcvtints behavior invalid inputs floatingpoint integer integer floatingpoint conversion instructions round according rm field floatingpoint register initialized floatingpoint positive zero using fcvtsw rd x0 never set exception flags floatingpoint floatingpoint signinjection instructions fsgnjs fsgnjns fsgnjxs produce result takes bits except sign bit rs1 fsgnj result sign bit rs2 sign bit fsgnjn result sign bit opposite rs2 sign bit fsgnjx sign bit xor sign bits rs1 rs2 signinjection instructions set floatingpoint exception flags canonicalize nans note fsgnjs rx ry ry moves ry rx assembler pseudoinstruction fmvs rx ry fsgnjns rx ry ry moves negation ry rx assembler pseudoinstruction fnegs rx ry fsgnjxs rx ry ry moves absolute value ry rx assembler pseudoinstruction fabss rx ry signinjection instructions provide floatingpoint mv abs neg well supporting operations including ieee copysign operation sign manipulation tran scendental math function libraries although mv abs neg need single register operand whereas fsgnj instructions need two unlikely microarchitectures would add optimizations benefit reduced number register reads relatively infrequent instructions even case microarchitecture simply detect source registers fsgnj instructions read single copy instructions provided move bit patterns floatingpoint integer registers fmvxw moves singleprecision value floatingpoint register rs1 represented ieee 754 2008 encoding lower 32 bits integer register rd bits modified transfer particular payloads noncanonical nans preserved rv64 higher 32 bits destination register filled copies floatingpoint number sign bit fmvwx moves singleprecision value encoded ieee 7542008 standard encoding lower 32 bits integer register rs1 floatingpoint register rd bits modified transfer particular payloads noncanonical nans preserved fmvwx fmvxw instructions previously called fmvsx fmvxs use w consistent semantics instruction moves 32 bits without interpreting became clearer defining nanboxing avoid disturbing existing code w versions supported tools base floatingpoint isa defined allow implementations employ internal recoding floatingpoint format registers simplify handling subnormal values possibly reduce functional unit latency end base isa avoids representing integer values floatingpoint registers defining conversion comparison operations read write integer register file directly also removes many common cases explicit moves integer floatingpoint registers required reducing instruction count critical paths common mixedformat code sequences | riscv-spec-20191213 | segment47 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.4.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.7).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(11.7).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.7).jpg?raw=true"
] | 11.7 Single-Precision Floating-Point Conversion and Move Instructions | RV32ISPEC.pdf#segment47 | 2023-09-18 14:50:21 |
floatingpoint compare instructions feqs flts fles perform specified comparison be tween floatingpoint registers rs1 rs2 rs1 rs2 rs1 rs2 writing 1 integer register rd condition holds 0 otherwise flts fles perform ieee 7542008 standard refers signaling comparisons set invalid operation exception flag either input nan feqs performs quiet comparison sets invalid operation exception flag either input signaling nan three instructions result 0 either operand nan f extension provides comparison whereas base isa provides branch comparison synthesized viceversa performance implication inconsistency nevertheless unfortunate incongruity isa | riscv-spec-20191213 | segment48 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.8).jpg?raw=true"
] | 11.8 Single-Precision Floating-Point Compare Instructions | RV32ISPEC.pdf#segment48 | 2023-09-18 14:50:21 |
fclasss instruction examines value floatingpoint register rs1 writes integer register rd 10bit mask indicates class floatingpoint number format mask described table 115 corresponding bit rd set property true clear otherwise bits rd cleared note exactly one bit rd set fclasss set floatingpoint exception flags | riscv-spec-20191213 | segment49 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.9).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.5.jpg?raw=true"
] | 11.9 Single-Precision Floating-Point Classify Instruction | RV32ISPEC.pdf#segment49 | 2023-09-18 14:50:21 |
standard extension doubleprecision floatingpoint version 22 chapter describes standard doubleprecision floatingpoint instructionset extension named adds doubleprecision floatingpoint computational instructions compliant ieee 7542008 arithmetic standard extension depends base singleprecision instruction subset f | riscv-spec-20191213 | segment50 | [] | Chapter 12 | RV32ISPEC.pdf#segment50 | 2023-09-18 14:50:21 |
extension widens 32 floatingpoint registers f0f31 64 bits flen64 fig ure 111 f registers hold either 32bit 64bit floatingpoint values described section 122 flen 32 64 128 depending f q extensions supported four different floatingpoint precisions supported including h f q | riscv-spec-20191213 | segment51 | [] | 12.1 D Register State | RV32ISPEC.pdf#segment51 | 2023-09-18 14:50:21 |
multiple floatingpoint precisions supported valid values narrower nbit types n flen represented lower n bits flenbit nan value process termed nanboxing upper bits valid nanboxed value must 1s valid nanboxed nbit values therefore appear negative quiet nans qnans viewed wider mbit value n flen operation writes narrower result f register must write 1s uppermost flenn bits yield legal nanboxed value software might know current type data stored floatingpoint register able save restore register values hence result using wider operations transfer narrower values defined common case calleesaved registers standard convention also desirable features including varargs userlevel threading libraries virtual machine migration debugging floatingpoint nbit transfer operations move external values held ieee standard formats f registers comprise floatingpoint loads stores flnfsn floating point move instructions fmvnxfmvxn narrower nbit transfer n flen f registers create valid nanboxed value narrower nbit transfer floatingpoint registers transfer lower n bits register ignoring upper flenn bits apart transfer operations described previous paragraph floatingpoint opera tions narrower nbit operations n flen check input operands correctly nanboxed ie upper flenn bits 1 n leastsignificant bits input used input value otherwise input value treated nbit canonical nan earlier versions document define behavior feeding results narrower wider operands operation except require wider saves restores would preserve value narrower operand new definition removes implementationspecific behav ior still accommodating nonrecoded recoded implementations floatingpoint unit new definition also helps catch software errors propagating nans values used incorrectly nonrecoded implementations unpack pack operands ieee standard format input output every floatingpoint operation nanboxing cost nonrecoded implementation primarily checking upper bits narrower operation represent legal nanboxed value writing 1s upper bits result recoded implementations use convenient internal format represent floatingpoint values added exponent bit allow values held normalized cost recoded implementation primarily extra tagging needed track internal types sign bits done without adding new state bits recoding nans internally exponent field small modifications needed pipelines used transfer values recoded format datapath latency costs minimal recoding process handle shifting input subnormal values wide operands case extracting nanboxed value similar process normalization except skipping leading1 bits instead skipping leading0 bits allowing datapath muxing shared | riscv-spec-20191213 | segment52 | [] | 12.2 NaN Boxing of Narrower Values | RV32ISPEC.pdf#segment52 | 2023-09-18 14:50:21 |
fld instruction loads doubleprecision floatingpoint value memory floatingpoint register rd fsd stores doubleprecision value floatingpoint registers memory fld fsd guaranteed execute atomically effective address naturally aligned xlen64 fld fsd modify bits transferred particular payloads noncanonical nans preserved | riscv-spec-20191213 | segment53 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(12.3).jpg?raw=true"
] | 12.3 Double-Precision Load and Store Instructions | RV32ISPEC.pdf#segment53 | 2023-09-18 14:50:21 |
doubleprecision floatingpoint computational instructions defined analogously singleprecision counterparts operate doubleprecision operands produce double precision results | riscv-spec-20191213 | segment54 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.4).jpg?raw=true"
] | 12.4 Double-Precision Floating-Point Computational Instructions | RV32ISPEC.pdf#segment54 | 2023-09-18 14:50:21 |
floatingpointtointeger integertofloatingpoint conversion instructions encoded opfp major opcode space fcvtwd fcvtld converts doubleprecision floatingpoint number floatingpoint register rs1 signed 32bit 64bit integer respectively inte ger register rd fcvtdw fcvtdl converts 32bit 64bit signed integer respec tively integer register rs1 doubleprecision floatingpoint number floatingpoint reg ister rd fcvtwud fcvtlud fcvtdwu fcvtdlu variants convert unsigned integer values rv64 fcvtw u d signextends 32bit result fcvtl u d fcvtdl u rv64only instructions range valid inputs fcvtintd behavior invalid inputs fcvtints floatingpoint integer integer floatingpoint conversion instructions round according rm field note fcvtdw u always produces exact result unaffected rounding mode doubleprecision singleprecision singleprecision doubleprecision conversion instruc tions fcvtsd fcvtds encoded opfp major opcode space source destination floatingpoint registers rs2 field encodes datatype source fmt field encodes datatype destination fcvtsd rounds according rm field fcvtds never round floatingpoint floatingpoint signinjection instructions fsgnjd fsgnjnd fsgnjxd defined analogously singleprecision signinjection instruction xlen64 instructions provided move bit patterns floatingpoint integer registers fmvxd moves doubleprecision value floatingpoint register rs1 representation ieee 7542008 standard encoding integer register rd fmvdx moves doubleprecision value encoded ieee 7542008 standard encoding integer register rs1 floatingpoint register rd fmvxd fmvdx modify bits transferred particular payloads noncanonical nans preserved early versions riscv isa additional instructions allow rv32 systems transfer upper lower portions 64bit floatingpoint register integer register however would instructions partial register writes would add com plexity implementations recoded floatingpoint register renaming requiring pipeline readmodifywrite sequence scaling handling quadprecision rv32 rv64 would also require additional instructions follow pattern isa defined reduce number explicit intfloat register moves conversions comparisons write results appropriate register file expect benefit instructions lower isas note systems implement 64bit floatingpoint unit including fused multiply add support 64bit floatingpoint loads stores marginal hardware cost moving 32bit 64bit integer datapath low software abi supporting 32bit wide address space pointers used avoid growth static data dynamic memory traffic | riscv-spec-20191213 | segment55 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(12.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(12.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra4(12.5).jpg?raw=true"
] | 12.5 Double-Precision Floating-Point Conversion and Move In- structions | RV32ISPEC.pdf#segment55 | 2023-09-18 14:50:21 |
doubleprecision floatingpoint compare instructions defined analogously single precision counterparts operate doubleprecision operands | riscv-spec-20191213 | segment56 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.6).jpg?raw=true"
] | 12.6 Double-Precision Floating-Point Compare Instructions | RV32ISPEC.pdf#segment56 | 2023-09-18 14:50:21 |
doubleprecision floatingpoint classify instruction fclassd defined analogously singleprecision counterpart operates doubleprecision operands | riscv-spec-20191213 | segment57 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.7).jpg?raw=true"
] | 12.7 Double-Precision Floating-Point Classify Instruction | RV32ISPEC.pdf#segment57 | 2023-09-18 14:50:21 |
q standard extension quadprecision floatingpoint version 22 chapter describes q standard extension 128bit quadprecision binary floatingpoint instructions compliant ieee 7542008 arithmetic standard quadprecision binary floatingpoint instructionset extension named q depends doubleprecision floating point extension d floatingpoint registers extended hold either single double quadprecision floatingpoint value flen128 nanboxing scheme described section 122 extended recursively allow singleprecision value nanboxed inside double precision value nanboxed inside quadprecision value | riscv-spec-20191213 | segment58 | [] | Chapter 13 | RV32ISPEC.pdf#segment58 | 2023-09-18 14:50:22 |
new 128bit variants loadfp storefp instructions added encoded new value funct3 width field flq fsq guaranteed execute atomically effective address naturally aligned xlen128 flq fsq modify bits transferred particular payloads noncanonical nans preserved | riscv-spec-20191213 | segment59 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.1).jpg?raw=true"
] | 13.1 Quad-Precision Load and Store Instructions | RV32ISPEC.pdf#segment59 | 2023-09-18 14:50:22 |
new supported format added format field instructions shown table 131 quadprecision floatingpoint c omputational nstructions efined alogously doubleprecision counterparts operate quadprecision operands produce quadprecision results | riscv-spec-20191213 | segment60 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2013.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.2).jpg?raw=true"
] | 13.2 Quad-Precision Computational Instructions | RV32ISPEC.pdf#segment60 | 2023-09-18 14:50:22 |
new floatingpointtointeger integertofloatingpoint conversion instructions added instructions defined analogously doubleprecisiontointeger integertodouble precision conversion instructions fcvtwq fcvtlq converts quadprecision floating point number signed 32bit 64bit integer respectively fcvtqw fcvtql con verts 32bit 64bit signed integer respectively quadprecision floatingpoint number fcvtwuq fcvtluq fcvtqwu fcvtqlu variants convert unsigned integer values fcvtl u q fcvtql u rv64only instructions new floatingpointtofloatingpoint conversion instructions added instructions de fined analogously doubleprecision floatingpointtofloatingpoint conversion instructions fcvtsq fcvtqs converts quadprecision floatingpoint number singleprecision floatingpoint number viceversa respectively fcvtdq fcvtqd converts quad precision floatingpoint number doubleprecision floatingpoint number viceversa respec tively floatingpoint floatingpoint signinjection instructions fsgnjq fsgnjnq fsgnjxq defined analogously doubleprecision signinjection instruction fmvxq fmvqx instructions provided rv32 rv64 quadprecision bit patterns must moved integer registers via memory rv128 support fmvxq fmvqx q extension | riscv-spec-20191213 | segment61 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(13.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(13.3).jpg?raw=true"
] | 13.3 Quad-Precision Convert and Move Instructions | RV32ISPEC.pdf#segment61 | 2023-09-18 14:50:22 |
quadprecision floatingpoint compare instructions defined analogously double precision counterparts operate quadprecision operands | riscv-spec-20191213 | segment62 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.4).jpg?raw=true"
] | 13.4 Quad-Precision Floating-Point Compare Instructions | RV32ISPEC.pdf#segment62 | 2023-09-18 14:50:22 |
quadprecision floatingpoint classify instruction fclassq defined analogously doubleprecision counterpart operates quadprecision operands | riscv-spec-20191213 | segment63 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.5).jpg?raw=true"
] | 13.5 Quad-Precision Floating-Point Classify Instruction | RV32ISPEC.pdf#segment63 | 2023-09-18 14:50:22 |
rvwmo memory consistency model version 01 chapter defines riscv memory consistency model memory consistency model set rules specifying values returned loads memory riscv uses memory model called rvwmo riscv weak memory ordering designed provide flexibility architects build highperformance scalable designs simultaneously supporting tractable programming model rvwmo code running single hart appears execute order perspective memory instructions hart memory instructions another hart may observe memory instructions first hart executed different order there fore multithreaded code may require explicit synchronization guarantee ordering mem ory instructions different harts base riscv isa provides fence instruction purpose described section 27 atomics extension additionally defines load reservedstoreconditional atomic readmodifywrite instructions standard isa extension misaligned atomics zam chapter 22 standard isa extension total store ordering ztso chapter 23 augment rvwmo additional rules specific extensions appendices specification provide axiomatic operational formalizations memory consistency model well additional explanatory material chapter defines memory model regular main memory operations interaction memory model io memory instruction fetches fencei page table walks sfencevma yet formalized may formalized future revision specification rv128 base isa future isa extensions v vector transactional memory j jit extensions need incorporated future revision well memory consistency models supporting overlapping memory accesses different widths si multaneously remain active area academic research yet fully understood specifics memory accesses different sizes interact rvwmo specified best current abilities subject revision new issues uncovered 83 | riscv-spec-20191213 | segment64 | [] | Chapter 14 | RV32ISPEC.pdf#segment64 | 2023-09-18 14:50:22 |
rvwmo memory model defined terms global memory order total ordering memory operations produced harts general multithreaded program many different possible executions execution corresponding global memory order global memory order defined primitive load store operations generated memory instructions subject constraints defined rest chapter execution satisfying memory model constraints legal execution far memory model concerned memory model primitives program order memory operations reflects order instructions generate load store logically laid hart dynamic instruction stream ie order simple inorder processor would execute instructions hart memoryaccessing instructions give rise memory operations memory operation either load operation store operation simultaneously memory operations singlecopy atomic never observed partiallycomplete state among instructions rv32gc rv64gc aligned memory instruction gives rise ex actly one memory operation two exceptions first unsuccessful sc instruction give rise memory operations second fld fsd instructions may give rise multiple memory operations xlen 64 stated section 123 clarified aligned amo gives rise single memory operation load operation store operation simultaneously instructions rv128 base instruction set future isa extensions v vector p simd may give rise multiple memory operations however memory model extensions yet formalized misaligned load store instruction may decomposed set component memory opera tions granularity fld fsd instruction xlen 64 may also decomposed set component memory operations granularity memory operations generated instructions ordered respect program order ordered normally respect memory operations generated preceding subsequent instructions program order atomics extension require execution environments support misaligned atomic instructions however misaligned atomics supported via zam extension lrs scs amos may decomposed subject constraints atomicity axiom misaligned atomics defined chapter 22 decomposition misaligned memory operations byte granularity facilitates emula tion implementations natively support misaligned accesses implementations might example simply iterate bytes misaligned access one one lr instruction sc instruction said paired lr precedes sc program order lr sc instructions corresponding memory operations said paired well except case failed sc store operation generated complete list conditions determining whether sc must succeed may succeed must fail defined section 82 load store operations may also carry one ordering annotations following set acquirercpc acquirercsc releasercpc releasercsc amo lr instruction aq set acquirercsc annotation amo sc instruction rl set release rcsc annotation amo lr sc instruction aq rl set acquirercsc releasercsc annotations convenience use term acquire annotation refer acquirercpc annotation acquirercsc annotation likewise release annotation refers releasercpc annotation releasercsc annotation rcpc annotation refers acquirercpc annotation release rcpc annotation rcsc annotation refers acquirercsc annotation releasercsc annotation memory model literature term rcpc stands release consistency processor consistent synchronization operations term rcsc stands release consistency sequentiallyconsistent synchronization operations 5 many different definitions acquire release annotations litera ture context rvwmo terms concisely completely defined preserved program order rules 57 rcpc annotations currently used implicitly assigned every memory ac cess per standard extension ztso chapter 23 furthermore although isa currently contain native loadacquire storerelease instructions rcpc variants thereof rvwmo model designed forwardscompatible potential addition isa future extension syntactic dependencies definition rvwmo memory model depends part notion syntactic depen dency defined follows context defining dependencies register refers either entire generalpurpose register portion csr entire csr granularity dependencies tracked csrs specific csr defined section 142 syntactic dependencies defined terms instructions source registers instructions desti nation registers way instructions carry dependency source registers destination registers section provides general definition terms however section 143 provides complete listing specifics instruction general register r x0 source register instruction following hold opcode rs1 rs2 rs3 set r csr instruction opcode csr set r unless csrrw csrrwi rd set x0 r csr implicit source register defined section 143 r csr aliases another source register memory instructions also specify source registers address source registers data source registers general register r x0 destination register instruction following hold opcode rd set r csr instruction opcode csr set r unless csrrs csrrc rs1 set x0 csrrsi csrrci uimm 40 set zero r csr implicit destination register defined section 143 r csr aliases another destination register nonmemory instructions carry dependency source registers destination registers however exceptions rule see section 143 instruction j syntactic dependency instruction via destination register source register r j either following hold r instruction programordered j r destination register instruction programordered j following hold 1 j syntactic dependency via destination register q source register r 2 syntactic dependency via destination register source register p 3 carries dependency p q finally definitions follow let b two memory operations let j instructions generate b respectively b syntactic address dependency r address source register j j syntactic dependency via source register r b syntactic data dependency b store operation r data source register j j syntactic dependency via source register r b syntactic control dependency instruction programordered j branch indirect jump syntactic dependency i generally speaking nonamo load instructions data source registers uncondi tional nonamo store instructions destination registers however successful sc instruction considered register specified rd destination register hence possible instruction syntactic dependency successful sc instruction precedes program order preserved program order global memory order given execution program respects hart program order subset program order must respected global memory order known preserved program order complete definition preserved program order follows note amos simul taneously loads stores memory operation precedes memory operation b preserved program order hence also global memory order precedes b program order b access regular main memory rather io regions following hold overlappingaddress orderings 1 b store b access overlapping memory addresses 2 b loads x byte read b store x b program order b return values x written different memory operations 3 generated amo sc instruction b load b returns value written explicit synchronization 4 fence instruction orders b 5 acquire annotation 6 b release annotation 7 b rcsc annotations 8 paired b syntactic dependencies 9 b syntactic address dependency 10 b syntactic data dependency 11 b store b syntactic control dependency pipeline dependencies 12 b load exists store b program order address data dependency b returns value written 13 b store exists instruction b program order address dependency memory model axioms execution riscv program obeys rvwmo memory consistency model exists global memory order conforming preserved program order satisfying load value axiom atomicity axiom progress axiom load value axiom byte load returns value written byte store latest global memory order among following stores 1 stores write byte precede global memory order 2 stores write byte precede program order atomicity axiom r w paired load store operations generated aligned lr sc instructions hart h store byte x r returns value written must precede w global memory order store hart h byte x following preceding w global memory order atomicity axiom theoretically supports lrsc pairs different widths mismatched addresses since implementations permitted allow sc operations succeed cases however practice expect patterns rare use discouraged progress axiom memory operation may preceded global memory order infinite sequence memory operations | riscv-spec-20191213 | segment65 | [] | 14.1 Definition of the RVWMO Memory Model | RV32ISPEC.pdf#segment65 | 2023-09-18 14:50:23 |
note read only csrs listed participate definition syntactic dependencies | riscv-spec-20191213 | segment65 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2014.1.jpg?raw=true"
] | 14.2 CSR Dependency Tracking Granularity | RV32ISPEC.pdf#segment65 | 2023-09-18 14:50:23 |
section provides concrete listing source destination registers instruction listings used definition syntactic dependencies section 141 term accumulating csr used describe csr source destination register carries dependency instructions carry dependency source register source registers column destination register destination registers column source register source registers column csr accumulating csrs column csr accumulating csrs column except annotated otherwise key aaddress source register ddata source register the instruction carry dependency source register destination register the instruction carries dependencies source register destination register specified | riscv-spec-20191213 | segment66 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(14.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(14.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(14.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra4(14.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra5(14.3).jpg?raw=true"
] | 14.3 Source and Destination Register Listings | RV32ISPEC.pdf#segment66 | 2023-09-18 14:50:23 |
l standard extension decimal floatingpoint version 00 chapter draft proposal ratified foundation chapter placeholder specification standard extension named l designed support decimal floatingpoint arithmetic defined ieee 7542008 standard | riscv-spec-20191213 | segment67 | [] | Chapter 15 | RV32ISPEC.pdf#segment67 | 2023-09-18 14:50:23 |
existing floatingpoint registers used hold 64bit 128bit decimal floatingpoint values existing floatingpoint load store instructions used move values memory due large opcode space required fused multiplyadd instructions decimal floating point instruction extension require five 25bit major opcodes 30bit encoding space | riscv-spec-20191213 | segment68 | [] | 15.1 Decimal Floating-Point Registers | RV32ISPEC.pdf#segment68 | 2023-09-18 14:50:23 |
c standard extension compressed instructions version 20 chapter describes current proposal riscv standard compressed instructionset extension named c reduces static dynamic code size adding short 16bit instruction encodings common operations c extension added base isas rv32 rv64 rv128 use generic term rvc cover typically 50 60 riscv instructions program replaced rvc instructions resulting 25 30 codesize reduction | riscv-spec-20191213 | segment69 | [] | Chapter 16 | RV32ISPEC.pdf#segment69 | 2023-09-18 14:50:23 |
rvc uses simple compression scheme offers shorter 16bit versions common 32bit riscv instructions immediate address offset small one registers zero register x0 abi link register x1 abi stack pointer x2 destination register first source register identical registers used 8 popular ones c extension compatible standard instruction extensions c extension allows 16bit instructions freely intermixed 32bit instructions latter able start 16bit boundary ie ialign16 addition c extension instructions raise instructionaddressmisaligned exceptions removing 32bit alignment constraint original 32bit instructions allows significantly greater code density compressed instruction encodings mostly common across rv32c rv64c rv128c shown table 164 opcodes used different purposes depending base isa width example wider addressspace rv64c rv128c variants require additional opcodes compress loads stores 64bit integer values rv32c uses opcodes compress loads stores singleprecision floatingpoint values similarly rv128c requires additional opcodes capture loads stores 128bit integer values opcodes used loads stores doubleprecision floatingpoint values rv32c rv64c c extension implemented appropriate compressed floatingpoint load store instructions must provided whenever relevant standard floatingpoint extension f andor also implemented addition rv32c includes compressed jump link instruction compress shortrange subroutine calls opcode used compress addiw rv64c rv128c doubleprecision loads stores significant fraction static dynamic instructions hence motivation include rv32c rv64c encoding although singleprecision loads stores significant source static dynamic compression benchmarks compiled currently supported abis microcontrollers provide hardware singleprecision floatingpoint units abi sup ports singleprecision floatingpoint numbers singleprecision loads stores used least frequently doubleprecision loads stores measured benchmarks hence motivation provide compressed support rv32c shortrange subroutine calls likely small binaries microcontrollers hence motivation include rv32c although reusing opcodes different purposes different base register widths adds complexity documentation impact implementation complexity small even designs support multiple base isa register widths compressed floatingpoint load store variants use instruction format register specifiers wider integer loads stores rvc designed constraint rvc instruction expands single 32bit instruction either base isa rv32ie rv64i rv128i f standard extensions present adopting constraint two main benefits hardware designs simply expand rvc instructions decode simplifying verification minimizing modifications existing microarchitectures compilers unaware rvc extension leave code compression assembler linker although compressionaware compiler generally able produce better results felt multiple complexity reductions simple oneone mapping c base ifd instructions far outweighed potential gains slightly denser encoding added additional instructions supported c extension allowed encoding multiple ifd instructions one c instruction important note c extension designed standalone isa meant used alongside base isa variablelength instruction sets long used improve code density example ibm stretch 4 developed late 1950s isa 32bit 64bit instructions 32bit instructions compressed versions full 64bit instructions stretch also employed concept limiting set registers addressable shorter instruction formats short branch instructions could refer one index registers later ibm 360 architecture 3 supported simple variablelength instruction encoding 16bit 32bit 48bit instruction formats 1963 cdc introduced craydesigned cdc 6600 18 precursor risc archi tectures introduced registerrich loadstore architecture instructions two lengths 15bits 30bits later cray1 design used similar instruction format 16bit 32bit instruction lengths initial risc isas 1980s picked performance code size reasonable workstation environment embedded systems hence arm mips subsequently made versions isas offered smaller code size offering alternative 16bit wide instruction set instead standard 32bit wide instructions com pressed risc isas reduced code size relative starting points 2530 yielding code significantly smaller 80x86 result surprised intuition variablelength cisc isa smaller risc isas offered 16bit 32bit formats since original risc isas leave sufficient opcode space free include unplanned compressed instructions instead developed complete new isas meant compilers needed different code generators separate compressed isas first compressed risc isa extensions eg arm thumb mips16 used fixed 16bit in struction size gave good reductions static code size caused increase dynamic instruction count led lower performance compared original fixedwidth 32bit instruction size led development second generation compressed risc isa designs mixed 16bit 32bit instruction lengths eg arm thumb2 micromips pow erpc vle performance similar pure 32bit instructions significant code size savings unfortunately different generations compressed isas incompati ble original uncompressed isa leading significant complexity documentation implementations software tools support commonly used 64bit isas powerpc micromips currently supports compressed instruction format surprising popular 64bit isa mobile platforms arm v8 include compressed instruction format given static code size dynamic instruction fetch bandwidth important metrics although static code size major concern larger systems instruction fetch bandwidth major bottleneck servers running commercial workloads often large instruction working set benefiting 25 years hindsight riscv designed support compressed instruc tions outset leaving enough opcode space rvc added simple extension top base isa along many extensions philosophy rvc reduce code size embedded applications improve performance energyefficiency applications due fewer misses instruction cache waterman shows rvc fetches 25 30 fewer instruction bits reduces instruction cache misses 20 25 roughly performance impact doubling instruction cache size 22 | riscv-spec-20191213 | segment70 | [] | 16.1 Overview | RV32ISPEC.pdf#segment70 | 2023-09-18 14:50:23 |
table 161 shows nine compressed instruction formats cr ci css use 32 rvi registers ciw cl cs ca cb limited 8 table 162 lists popular registers correspond registers x8 x15 note separate version load store instructions use stack pointer base address register since saving restoring stack prevalent use ci css formats allow access 32 data registers ciw supplies 8bit immediate addi4spn instruction riscv abi changed make frequently used registers map registers x8x15 simplifies decompression decoder contiguous naturally aligned set register numbers also compatible rv32e base isa 16 integer registers compressed registerbased floatingpoint loads stores also use cl cs formats respec tively eight registers mapping f8 f15 standard riscv calling convention maps frequently used floatingpoint registers registers f8 f15 allows register decompression decoding integer register numbers formats designed keep bits two register source specifiers place instructions destination register field move full 5bit destination register specifier present place 32bit riscv encoding immediates signextended signextension always bit 12 immediate fields scrambled base specification reduce number immediate muxes required immediate fields scrambled instruction formats instead sequential order many bits possible position every instruction thereby simplify ing implementations example immediate bits 1710 always sourced instruction bit positions five immediate bits 5 4 3 1 0 two source instruction bits four 9 7 6 2 three sources one 8 four sources many rvc instructions zerovalued immediates disallowed x0 valid 5bit register specifier restrictions free encoding space instructions requiring fewer operand bits | riscv-spec-20191213 | segment71 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.2.jpg?raw=true"
] | 16.2 Compressed Instruction Formats | RV32ISPEC.pdf#segment71 | 2023-09-18 14:50:23 |
increase reach 16bit instructions datatransfer instructions use zeroextended immediates scaled size data bytes 4 words 8 double words 16 quad words rvc provides two variants loads stores one uses abi stack pointer x2 base address target data register reference one 8 base address registers one 8 data registers stackpointerbased loads stores instructions use ci format clwsp loads 32bit value memory register rd computes effective address adding zeroextended offset scaled 4 stack pointer x2 expands lw rd offset 72 x2 clwsp valid rdx0 code points rdx0 reserved cldsp rv64crv128conly instruction loads 64bit value memory register rd computes effective address adding zeroextended offset scaled 8 stack pointer x2 expands ld rd offset 83 x2 cldsp valid rdx0 code points rdx0 reserved clqsp rv128conly instruction loads 128bit value memory register rd computes effective address adding zeroextended offset scaled 16 stack pointer x2 expands lq rd offset 94 x2 clqsp valid rdx0 code points rdx0 reserved cflwsp rv32fconly instruction loads singleprecision floatingpoint value memory floatingpoint register rd computes effective address adding zeroextended offset scaled 4 stack pointer x2 expands flw rd offset 72 x2 cfldsp rv32dcrv64dconly instruction loads doubleprecision floatingpoint value memory floatingpoint register rd computes effective address adding zeroextended offset scaled 8 stack pointer x2 expands fld rd offset 83 x2 instructions use css format cswsp stores 32bit value register rs2 memory computes effective address adding zeroextended offset scaled 4 stack pointer x2 expands sw rs2 offset 72 x2 csdsp rv64crv128conly instruction stores 64bit value register rs2 memory computes effective address adding zeroextended offset scaled 8 stack pointer x2 expands sd rs2 offset 83 x2 csqsp rv128conly instruction stores 128bit value register rs2 memory computes effective address adding zeroextended offset scaled 16 stack pointer x2 expands sq rs2 offset 94 x2 cfswsp rv32fconly instruction stores singleprecision floatingpoint value floatingpoint register rs2 memory computes effective address adding zeroextended offset scaled 4 stack pointer x2 expands fsw rs2 offset 72 x2 cfsdsp rv32dcrv64dconly instruction stores doubleprecision floatingpoint value floatingpoint register rs2 memory computes effective address adding zero extended offset scaled 8 stack pointer x2 expands fsd rs2 offset 83 x2 register saverestore code function entryexit represents significant portion static code size stackpointerbased compressed loads stores rvc effective reducing saverestore static code size factor 2 improving performance reducing dynamic instruction bandwidth common mechanism used isas reduce saverestore code size load multiple storemultiple instructions considered adopting riscv noted following drawbacks instructions instructions complicate processor implementations virtual memory systems data accesses could resident physical memory could requires new restart mechanism partially executed instructions unlike rest rvc instructions ifd equivalent load multiple store multiple unlike rest rvc instructions compiler would aware instructions generate instructions allocate registers order maxi mize chances saved stored since would saved restored sequential order simple microarchitectural implementations constrain instructions scheduled around load store multiple instructions leading potential perfor mance loss desire sequential register allocation might conflict featured registers selected ciw cl cs ca cb formats furthermore much gains realized software replacing prologue epilogue code subroutine calls common prologue epilogue code technique described section 56 23 reasonable architects might come different conclusions decided omit load store multiple instead use softwareonly approach calling saverestore millicode routines attain greatest code size reduction registerbased loads stores instructions use cl format clw loads 32bit value memory register rd computes effective address adding zeroextended offset scaled 4 base address register rs1 expands lw rd offset 62 rs1 cld rv64crv128conly instruction loads 64bit value memory register rd computes effective address adding zeroextended offset scaled 8 base address register rs1 expands ld rd offset 73 rs1 clq rv128conly instruction loads 128bit value memory register rd computes effective address adding zeroextended offset scaled 16 base address register rs1 expands lq rd offset 84 rs1 cflw rv32fconly instruction loads singleprecision floatingpoint value mem ory floatingpoint register rd computes effective address adding zeroextended offset scaled 4 base address register rs1 expands flw rd offset 62 rs1 cfld rv32dcrv64dconly instruction loads doubleprecision floatingpoint value memory floatingpoint register rd computes effective address adding zeroextended offset scaled 8 base address register rs1 expands fld rd offset 73 rs1 instructions use cs format csw stores 32bit value register rs2 memory computes effective address adding zeroextended offset scaled 4 base address register rs1 expands sw rs2 offset 62 rs1 csd rv64crv128conly instruction stores 64bit value register rs2 memory computes effective address adding zeroextended offset scaled 8 base address register rs1 expands sd rs2 offset 73 rs1 csq rv128conly instruction stores 128bit value register rs2 memory computes effective address adding zeroextended offset scaled 16 base address register rs1 expands sq rs2 offset 84 rs1 cfsw rv32fconly instruction stores singleprecision floatingpoint value floating point register rs2 memory computes effective address adding zeroextended offset scaled 4 base address register rs1 expands fsw rs2 offset 62 rs1 cfsd rv32dcrv64dconly instruction stores doubleprecision floatingpoint value floatingpoint register rs2 memory computes effective address adding zero extended offset scaled 8 base address register rs1 expands fsd rs2 offset 73 rs1 | riscv-spec-20191213 | segment72 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(16.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(16.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(16.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra4(16.3).jpg?raw=true"
] | 16.3 Load and Store Instructions | RV32ISPEC.pdf#segment72 | 2023-09-18 14:50:24 |
rvc provides unconditional jump instructions conditional branch instructions base rvi instructions offsets rvc control transfer instruction multiples 2 bytes cj performs unconditional control transfer offset signextended added pc form jump target address cj therefore target 2 kib range cj expands jal x0 offset 111 cjal rv32conly instruction performs operation cj additionally writes address instruction following jump pc2 link register x1 cjal expands jal x1 offset 111 instructions use cr format cjr jump register performs unconditional control transfer address register rs1 cjr expands jalr x0 0 rs1 cjr valid rs1x0 code point rs1x0 reserved cjalr jump link register performs operation cjr additionally writes address instruction following jump pc2 link register x1 cjalr expands jalr x1 0 rs1 cjalr valid rs1x0 code point rs1x0 corresponds cebreak instruction strictly speaking cjalr expand exactly base rvi instruction value added pc form link address 2 rather 4 base isa supporting offsets 2 4 bytes minor change base microarchitecture instructions use cb format cbeqz performs conditional control transfers offset signextended added pc form branch target address therefore target 256 b range cbeqz takes branch value register rs1 zero expands beq rs1 x0 offset 81 cbnez defined analogously takes branch rs1 contains nonzero value expands bne rs1 x0 offset 81 | riscv-spec-20191213 | segment73 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(16.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(16.4).jpg?raw=true"
] | 16.4 Control Transfer Instructions | RV32ISPEC.pdf#segment73 | 2023-09-18 14:50:24 |
rvc provides several instructions integer arithmetic constant generation integer constantgeneration instructions two constantgeneration instructions use ci instruction format target integer register cli loads signextended 6bit immediate imm register rd cli expands addi rd x0 imm 50 cli valid rdx0 code points rdx0 encode hints clui loads nonzero 6bit immediate field bits 1712 destination register clears bottom 12 bits signextends bit 17 higher bits destination clui expands lui rd nzimm 1712 clui valid rd x0 x2 immediate equal zero code points nzimm0 reserved remaining code points rdx0 hints remaining code points rdx2 correspond caddi16sp instruction integer registerimmediate operations integer registerimmediate operations encoded ci format perform operations integer register 6bit immediate caddi adds nonzero signextended 6bit immediate value register rd writes result rd caddi expands addi rd rd nzimm 50 caddi valid rdx0 nzimm0 code points rdx0 encode cnop instruction remaining code points nzimm0 encode hints caddiw rv64crv128conly instruction performs computation pro duces 32bit result signextends result 64 bits caddiw expands addiw rd rd imm 50 immediate zero caddiw corresponds sextw rd caddiw valid rdx0 code points rdx0 reserved caddi16sp shares opcode clui destination field x2 caddi16sp adds nonzero signextended 6bit immediate value stack pointer spx2 immediate scaled represent multiples 16 range 512496 caddi16sp used adjust stack pointer procedure prologues epilogues expands addi x2 x2 nzimm 94 caddi16sp valid nzimm0 code point nzimm0 reserved standard riscv calling convention stack pointer sp always 16byte aligned caddi4spn ciwformat instruction adds zeroextended nonzero immediate scaled 4 stack pointer x2 writes result rd instruction used generate pointers stackallocated variables expands addi rd x2 nzuimm 92 caddi4spn valid nzuimm0 code points nzuimm0 reserved cslli ciformat instruction performs logical left shift value register rd writes result rd shift amount encoded shamt field rv128c shift amount zero used encode shift 64 cslli expands slli rd rd shamt 50 except rv128c shamt0 expands slli rd rd 64 rv32c shamt 5 must zero code points shamt 5 1 reserved custom extensions rv32c rv64c shift amount must nonzero code points shamt0 hints base isas code points rdx0 hints except shamt 5 1 rv32c csrli cbformat instruction performs logical right shift value register rd writes result rd shift amount encoded shamt field rv128c shift amount zero used encode shift 64 furthermore shift amount signextended rv128c legal shift amounts 131 64 96127 csrli expands srli rd rd shamt 50 except rv128c shamt0 expands srli rd rd 64 rv32c shamt 5 must zero code points shamt 5 1 reserved custom extensions rv32c rv64c shift amount must nonzero code points shamt0 hints csrai defined analogously csrli instead performs arithmetic right shift csrai expands srai rd rd shamt 50 left shifts usually frequent right shifts left shifts frequently used scale address values right shifts therefore granted less encoding space placed encoding quadrant immediates signextended rv128 decision made 6bit shiftamount immediate also signextended apart reducing decode complexity believe rightshift amounts 96127 useful 6495 allow extraction tags located high portions 128bit address pointers note rv128c frozen point rv32c rv64c allow evaluation typical usage 128bit addressspace codes candi cbformat instruction computes bitwise value register rd signextended 6bit immediate writes result rd candi expands andi rd rd imm 50 integer registerregister operations instructions use cr format cmv copies value register rs2 register rd cmv expands add rd x0 rs2 cmv valid rs2x0 code points rs2x0 correspond cjr instruction code points rs2x0 rdx0 hints cmv expands different instruction canonical mv pseudoinstruction instead uses addi implementations handle mv specially eg using registerrenaming hardware may find convenient expand cmv mv instead add slight additional hard ware cost cadd adds values registers rd rs2 writes result register rd cadd expands add rd rd rs2 cadd valid rs2x0 code points rs2x0 correspond cjalr cebreak instructions code points rs2x0 rdx0 hints instructions use ca format cand computes bitwise values registers rd rs2 writes result register rd cand expands rd rd rs2 cor computes bitwise values registers rd rs2 writes result register rd cor expands rd rd rs2 cxor computes bitwise xor values registers rd rs2 writes result register rd cxor expands xor rd rd rs2 csub subtracts value register rs2 value register rd writes result register rd csub expands sub rd rd rs2 caddw rv64crv128conly instruction adds values registers rd rs2 signextends lower 32 bits sum writing result register rd caddw expands addw rd rd rs2 csubw rv64crv128conly instruction subtracts value register rs2 value register rd signextends lower 32 bits difference writing result register rd csubw expands subw rd rd rs2 group six instructions provide large savings individually occupy much encoding space straightforward implement group provide worthwhile im provement static dynamic compression defined illegal instruction 16bit instruction bits zero permanently reserved illegal instruction reserve allzero instructions illegal instructions help trap attempts execute zeroed nonexistent portions memory space allzero value redefined nonstandard extension similarly reserve instructions bits set 1 corresponding long instructions riscv variablelength encoding scheme illegal capture another common value seen nonexistent memory regions nop instruction cnop ciformat instruction change uservisible state except advancing pc incrementing applicable performance counters cnop expands nop cnop valid imm0 code points imm0 encode hints breakpoint instruction debuggers use cebreak instruction expands ebreak cause control transferred back debugging environment cebreak shares opcode cadd instruction rd rs2 zero thus also use cr format | riscv-spec-20191213 | segment74 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra4(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra5(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra6(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra7(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra8(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra91(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra10(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra11(16.5).jpg?raw=true"
] | 16.5 Integer Computational Instructions | RV32ISPEC.pdf#segment74 | 2023-09-18 14:50:25 |
implementations support c extension compressed forms instructions per mitted inside constrained lrsc sequences described section 83 also permitted inside constrained lrsc sequences implication implementation claims support c extensions must ensure lrsc sequences containing valid c instructions eventually complete | riscv-spec-20191213 | segment75 | [] | 16.6 Usage of C Instructions in LR/SC Sequences | RV32ISPEC.pdf#segment75 | 2023-09-18 14:50:25 |
portion rvc encoding space reserved microarchitectural hints like hints rv32i base isa see section 29 instructions modify architectural state except advancing pc applicable performance counters hints executed noops implementations ignore rvc hints encoded computational instructions modify architectural state either rdx0 eg cadd x0 t0 rd overwritten copy eg caddi t0 0 hint encoding chosen simple implementations ignore hints alto gether instead execute hint regular computational instruction happens mutate architectural state rvc hints necessarily expand rvi hint counterparts example cadd x0 t0 might encode hint add x0 x0 t0 primary reason require rvc hint expand rvi hint hints unlikely compressible manner underlying computational instruction also decoupling rvc rvi hint mappings allows scarce rvc hint space allocated popular hints particular hints amenable macroop fusion table 163 lists rvc hint code points rv32c 78 hint space reserved standard hints none presently defined remainder hint space reserved custom hints standard hints ever defined subspace | riscv-spec-20191213 | segment76 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.3.jpg?raw=true"
] | 16.7 HINT Instructions | RV32ISPEC.pdf#segment76 | 2023-09-18 14:50:25 |
table 164 shows map major opcodes rvc row table corresponds one quadrant encoding space last quadrant two leastsignificant bits set corresponds instructions wider 16 bits including base isas several instructions valid certain operands invalid marked either res indicate opcode reserved future standard extensions nse indicate opcode reserved custom extensions hint indicate opcode reserved microarchitectural hints see section 167 | riscv-spec-20191213 | segment77 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.4.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.5.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.6.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.7.jpg?raw=true"
] | 16.8 RVC Instruction Set Listings | RV32ISPEC.pdf#segment77 | 2023-09-18 14:50:25 |
b standard extension bit manipulation version 00 chapter placeholder future standard extension provide bit manipulation instruc tions including instructions insert extract test bit fields rotations funnel shifts bit byte permutations although bit manipulation instructions effective application domains particu larly dealing externally packed data structures excluded base isa useful domains add additional complexity instruction formats supply needed operands anticipate b extension brownfield encoding within base 30bit instruction space | riscv-spec-20191213 | segment78 | [] | Chapter 17 | RV32ISPEC.pdf#segment78 | 2023-09-18 14:50:25 |
j standard extension dynamically translated languages version 00 chapter placeholder future standard extension support dynamically translated languages many popular languages usually implemented via dynamic translation including java javascript languages benefit additional isa support dynamic checks garbage collection | riscv-spec-20191213 | segment79 | [] | Chapter 18 | RV32ISPEC.pdf#segment79 | 2023-09-18 14:50:25 |
standard extension transactional memory version 00 chapter placeholder future standard extension provide transactional memory operations despite much research last twenty years initial commercial implementations still much debate best way support atomic operations involving multiple addresses current thoughts include small limitedcapacity transactional memory buffer along lines original transactional memory proposals | riscv-spec-20191213 | segment80 | [] | Chapter 19 | RV32ISPEC.pdf#segment80 | 2023-09-18 14:50:25 |
p standard extension packedsimd instructions version 02 discussions 5th riscv workshop indicated desire drop packedsimd proposal floatingpoint registers favor standardizing v extension large floatingpoint simd operations however interest packedsimd fixedpoint operations use integer registers small riscv implementations task group working define new p extension | riscv-spec-20191213 | segment81 | [] | Chapter 20 | RV32ISPEC.pdf#segment81 | 2023-09-18 14:50:25 |
v standard extension vector operations version 07 current working group draft hosted https githubcomriscvriscvvspec base vector extension intended provide general support dataparallel execution within 32bit instruction encoding space later vector extensions supporting richer functionality certain domains | riscv-spec-20191213 | segment82 | [] | Chapter 21 | RV32ISPEC.pdf#segment82 | 2023-09-18 14:50:25 |
zam standard extension misaligned atomics v01 chapter defines zam extension extends extension standardizing support misaligned atomic memory operations amos platforms implementing zam misaligned amos need execute atomically respect accesses including nonatomic loads stores address size precisely execution environments implementing zam subject following axiom atomicity axiom misaligned atomics r w paired misaligned load store instructions hart h address size store instruction hart h address size r w store operation generated lies memory operations generated r w global memory order furthermore load instruction l hart h address size r w load operation generated l lies two memory operations generated r w global memory order restricted form atomicity intended balance needs applications require sup port misaligned atomics ability implementation actually provide necessary degree atomicity aligned instructions zam continue behave normally rvwmo intention zam implemented one two ways 1 hardware natively supports atomic misaligned accesses address size question eg misaligned accesses within single cache line simply following rules would applied aligned amos 2 hardware natively support misaligned accesses address size question trapping instructions including loads address size executing via number memory operations inside mutex function given memory address access size amos may emulated splitting separate load store operations preserved program order rules eg incoming outgoing syntactic dependencies must behave amo still single memory operation | riscv-spec-20191213 | segment83 | [] | Chapter 22 | RV32ISPEC.pdf#segment83 | 2023-09-18 14:50:25 |
ztso standard extension total store ordering v01 chapter defines ztso extension riscv total store ordering rvtso memory consistency model rvtso defined delta rvwmo defined chapter 141 ztso extension meant facilitate porting code originally written x86 sparc architectures use tso default also supports implementations inherently provide rvtso behavior want expose fact software rvtso makes following adjustments rvwmo load operations behave acquirercpc annotation store operations behave releasercpc annotation amos behave acquirercsc releasercsc annotations rules render ppo rules except 47 redundant also make redundant nonio fences pw sr set finally also imply memory operation reordered past amo either direction context rvtso case rvwmo storage ordering annotations concisely completely defined ppo rules 57 memory models load value axiom allows hart forward value store buffer subsequent program order loadthat say stores forwarded locally visible harts spite fact ztso adds new instructions isa code written assuming rvtso run correctly implementations supporting ztso binaries compiled run ztso indicate via flag binary platforms implement ztso simply refuse run | riscv-spec-20191213 | segment84 | [] | Chapter 23 | RV32ISPEC.pdf#segment84 | 2023-09-18 14:50:25 |
rv3264g instruction set listings one goal riscv project used stable software development target purpose define combination base isa rv32i rv64i plus selected standard extensions imafd zicsr zifencei generalpurpose isa use abbreviation g imafdzicsr zifencei combination instructionset extensions chapter presents opcode maps instructionset listings rv32g rv64g table 241 shows map major opcodes rvg major opcodes 3 lower bits set reserved instruction lengths greater 32 bits opcodes marked reserved avoided custom instructionset extensions might used future standard extensions major opcodes marked custom0 custom1 avoided future standard extensions recommended use custom instructionset extensions within base 32bit instruction format opcodes marked custom2rv128 custom3rv128 reserved future use rv128 otherwise avoided standard extensions also used custom instructionset extensions rv32 rv64 believe rv32g rv64g provide simple complete instruction sets broad range generalpurpose computing optional compressed instruction set described chapter 16 added forming rv32gc rv64gc improve performance code size energy efficiency though additional hardware complexity move beyond imafdc instructionset extensions added instructions tend domainspecific provide benefits restricted class applications eg multimedia security unlike commercial isas riscv isa design clearly separates base isa broadly applicable standard extensions specialized additions chapter 26 extensive discussion ways add extensions riscv isa | riscv-spec-20191213 | segment85 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.2(1).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.2(2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.2(3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.2(4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.2(5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.2(6).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.3.jpg?raw=true"
] | Chapter 24 | RV32ISPEC.pdf#segment85 | 2023-09-18 14:50:25 |
riscv assembly programmer handbook chapter placeholder assembly programmer manual table 251 lists assembler mnemonics x f registers role first standard calling convention may future different calling conventions note registers x1 x2 x5 special meanings encoded standard isa andor compressed extension tables 252 253 contain listing standard riscv pseudoinstructions | riscv-spec-20191213 | segment86 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2025.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2025.2.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2025.3.jpg?raw=true"
] | Chapter 25 | RV32ISPEC.pdf#segment86 | 2023-09-18 14:50:25 |
extending riscv addition supporting standard generalpurpose software development another goal riscv provide basis specialized instructionset extensions customized accelerators instruction encoding spaces optional variablelength instruction encoding designed make easier leverage software development effort standard isa toolchain building customized processors example intent continue provide full software support implementations use standard base perhaps together many nonstandard instructionset extensions chapter describes various ways base riscv isa extended together scheme managing instructionset extensions developed independent groups volume deals unprivileged isa although approach terminology used supervisorlevel extensions described second volume | riscv-spec-20191213 | segment87 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2026.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2026.2.jpg?raw=true"
] | Chapter 26 | RV32ISPEC.pdf#segment87 | 2023-09-18 14:50:25 |
End of preview. Expand
in Dataset Viewer.
YAML Metadata
Warning:
empty or missing yaml metadata in repo card
(https://huggingface.co/docs/hub/datasets-cards)
- Downloads last month
- 12