Source: http://patents.com/us-9818340.html
Timestamp: 2018-09-23 03:19:43
Document Index: 640970637

Matched Legal Cases: ['Application No. 2006', 'art.\n2', 'art.\n8', 'art.\n14', 'art 1', 'art 1']

US Patent # 9,818,340. Image display device and electronic appliance - Patents.com
United States Patent 9,818,340
Yamashita; Junichi (Tokyo, JP), Mitomi; Yutaka (Kanagawa, JP), Minami; Tetsuo (Tokyo, JP), Tanikame; Takao (Kanagawa, JP)
Yamashita; Junichi
Mitomi; Yutaka
Tanikame; Takao
Family ID: 1000002948219
13/064,195
US 20110163943 A1 Jul 7, 2011
11889144 Aug 9, 2007 7952542
Aug 18, 2006 [JP] 2006-222846
Current CPC Class: G09G 3/3233 (20130101); H01L 27/3262 (20130101); H01L 27/3265 (20130101); H01L 27/3276 (20130101); H01L 29/78678 (20130101); H01L 29/78696 (20130101); G09G 2320/0626 (20130101); G09G 2300/0819 (20130101); G09G 2300/0842 (20130101); G09G 2300/0861 (20130101); G09G 2320/0233 (20130101); G09G 2320/043 (20130101)
Current International Class: G09G 3/30 (20060101); G09G 3/3233 (20160101); H01L 27/32 (20060101); H01L 29/786 (20060101)
Field of Search: ;345/76-83 ;315/169.3
5376839 December 1994 Horiguchi et al.
7173590 February 2007 Uchino et al.
8823607 September 2014 Uchino
9406258 August 2016 Yamashita
9454928 September 2016 Uchino
9454929 September 2016 Uchino
2002/0074612 June 2002 Bulucea et al.
2003/0094656 May 2003 Koyama et al.
2004/0150593 August 2004 Yen et al.
2004/0233147 November 2004 Kawachi et al.
2005/0012736 January 2005 Uchino et al.
2005/0057456 March 2005 Hu et al.
2005/0116907 June 2005 Miyazawa
2005/0140607 June 2005 Sato et al.
2005/0140609 June 2005 Akimoto et al.
2005/0230753 October 2005 Hsieh et al.
2006/0028407 February 2006 Chou
2006/0066527 March 2006 Chou
2006/0066532 March 2006 Jeong
2006/0119556 June 2006 Winters et al.
2006/0132397 June 2006 Kim et al.
2006/0170628 August 2006 Yamashita et al.
2007/0001940 January 2007 Jo
2007/0115225 May 2007 Uchino et al.
2007/0152920 July 2007 Yamashita et al.
2007/0215945 September 2007 Tokunaga et al.
2009/0079487 March 2009 Arnborg et al.
2003-323154 Nov 2003 JP
2005-242341 Sep 2005 JP
Japanese Office Action dated Jun. 6, 2008 for corresponding Japanese Application No. 2006-222846. cited by applicant.
This is a Continuation Application of U.S. patent application Ser. No. 11/889,144, filed Aug. 9, 2007, which claims priority from Japanese Patent Application JP 2006-222846 filed in the Japanese Patent Office on Aug. 18, 2006, the entire contents of which being incorporated herein by reference.
1. An image display device comprising: scanning lines arranged in rows; signal lines arranged in columns; a scanner part configured to supply a control signal to the scanning lines; and pixel circuits in a matrix connected to the scanning lines and the signal lines, wherein at least one of the pixel circuits includes a sampling transistor, a drive transistor, a pixel capacitor, a light emitting device, a first switching transistor directly connected between a first voltage line and the pixel capacitor, a second switching transistor directly connected between a second voltage line and the light emitting device, and a third switching transistor directly connected between a third voltage line and the drive transistor, the sampling transistor is configured to supply a signal potential from the signal line to the pixel capacitor, the pixel capacitor connected between a current terminal and a control terminal of the drive transistor, and a channel length of the drive transistor is made longer than a channel length of each of the three switching transistors and transistors in the scanner part.
2. The image display device according to claim 1, wherein the channel length of the drive transistor is set to at least 10 .mu.m.
3. The image display device according to claim 1, wherein in at least one of the pixel circuits, the channel length of the drive transistor is set so that during a light emission period, a source potential and a gate potential of the drive transistor rise together, wherein a voltage difference between the gate potential and the source potential stays constant throughout the light emission period.
4. The image display device according to claim 1, wherein a current is configured to be applied to the pixel capacitor via the drive transistor while the signal potential is being sampled.
5. The image display device according to claim 1, wherein the drive transistor is formed by a low temperature poly-silicon process.
6. An electronic appliance having the image display device according to claim 1.
7. An image display device comprising: scanning lines arranged in rows; signal lines arranged in columns; a scanner part configured to supply a control signal to the scanning lines; and pixel circuits in a matrix connected to the scanning lines and the signal lines, wherein at least one of the pixel circuits includes a sampling transistor, a drive transistor, a pixel capacitor, a light emitting device, a first switching transistor directly connected between a first voltage line and the pixel capacitor, a second switching transistor directly connected between a second voltage line and the light emitting device, and a third switching transistor directly connected between a third voltage line and the drive transistor, the sampling transistor is configured to supply a signal potential from the signal line to the pixel capacitor, the pixel capacitor connected between a current terminal and a control terminal of the drive transistor, and a channel length of the drive transistor is made longer than a channel length of each of the three switching transistors and transistors in the scanner part.
8. The image display device according to claim 7, wherein the channel length of the drive transistor is set to at least 10 .mu.m.
9. The image display device according to claim 7, wherein in at least one of the pixel circuits, the channel length of the drive transistor is set so that during a light emission period, a source potential and a gate potential of the drive transistor rise together, wherein a voltage difference between the gate potential and the source potential stays constant throughout the light emission period.
10. The image display device according to claim 7, wherein a current is configured to be applied to the pixel capacitor via the drive transistor while the signal potential is being sampled.
11. The image display device according to claim 7, wherein the drive transistor is formed by a low temperature poly-silicon process.
12. An electronic appliance having the image display device according to claim 7.
13. An image display device comprising: scanning lines arranged in rows; signal lines arranged in columns; a scanner part configured to supply a control signal to the scanning lines; and pixel circuits in a matrix connected to the scanning lines and the signal lines, wherein at least one of the pixel circuits includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a drive transistor, a pixel capacitor, and a light emitting device; the first switching transistor is configured to supply a signal potential to the pixel capacitor, a gate of the first switching transistor is connected to a first scanning line; the second switching transistor is directly connected between a first voltage line and the pixel capacitor and is configured to supply a first predetermined potential to the pixel capacitor, a gate of the second switching transistor is connected to a second scanning line; the third switching transistor is directly connected between a second voltage line and the light emitting device and is configured to supply a second predetermined potential to an anode of the light emitting device, a gate of the third switching transistor is connected to a third scanning line; the fourth switching transistor is directly connected between a third voltage line and the drive transistor and is configured to supply a third predetermined potential to the drive transistor, a gate of the fourth switching transistor is connected to a fourth scanning line; and a channel length of the drive transistor is longer than a channel length of each of the first, second, third, fourth switching transistor, and transistors in the scanner part.
14. The image display device according to claim 13, wherein, while the signal potential is sampled, the drive transistor is configured to apply a negative feedback of an output current of the drive transistor to a first terminal of the pixel capacitor.
15. The image display device according to claim 14, wherein a potential of the first terminal of the pixel capacitor is increased towards a potential of a second terminal of the pixel capacitor by the negative feedback.
16. The image display device according to claim 13, wherein the channel length of the drive transistor is at least 10.mu.m.
17. The image display device according to claim 13, wherein the channel length of the drive transistor is set so that during a light emission period, a source potential of the drive transistor and a gate potential of the drive transistor rise together, wherein a voltage difference between the gate potential and the source potential stays constant throughout the light emission period.
18. The image display device according to claim 13, wherein a current is configured to be applied to the pixel capacitor via the drive transistor while the signal potential is being sampled.
19. The image display device according to claim 13, wherein the drive transistor is formed by a low temperature poly-silicon process.
20. The image display device according to claim 13, wherein the second predetermined potential is lower than a threshold voltage of the light emitting device.
21. An electronic appliance having the image display device according to claim 13.
FIG. 11 shows a schematic diagram depicting an exemplary conventional pixel circuit. The pixel circuit is arranged at the portion at which a scanning line in rows which supplies control signals intersects a signal line SL in columns which supplies video signals, and the circuit includes a sampling transistor Tr1, a pixel capacitance Cs, a drive transistor Trd, and a light emitting device EL. The sampling transistor Tr1 conducts in accordance with the control signal supplied from the scanning line to sample the video signal supplied from the signal line SL. The pixel capacitance Cs holds the input voltage corresponding to the sampled video signal. The drive transistor Trd supplies an output current Ids in a predetermined light emission period in accordance with the input voltage held at the pixel capacitance Cs. Generally, the output current Ids has dependence on the carrier mobility .mu..mu. and on the threshold voltage Vth of the channel region of the drive transistor Trd. The light emitting device EL emits light at the brightness corresponding to the video signal by the output current supplied from the drive transistor Trd. In addition, in the conventional example shown in FIG. 11, the pixel capacitance Cs is connected between a gate G of the drive transistor Trd and a power source potential Vcc. On the other hand, the anode of the light emitting device EL is connected to a source S of the drive transistor Trd, and the cathode thereof is grounded. A drain of the drive transistor Trd is connected to the power source potential Vcc.
Here, the operating characteristic of the drive transistor is expressed by Equation (1) below. Ids=(1/2).mu.(W/L)Cox(Vgs-Vth)2 (1)
In the Equation (1) for the transistor characteristics, Ids is the drain current carried between the source and the drain, and in the pixel circuit, it is the output current supplied to the light emitting device. Vgs is the gate voltage that is applied to the gate with reference to the source, and in the pixel circuit, it is the input voltage described above. Vth is the threshold voltage of the transistor. In addition, .mu. is the mobility of a semiconductor thin film configuring the channel of the transistor. In addition to this, W is the channel width, L is the channel length, and Cox is the gate capacitance. As apparent from Equation (1) for the transistor characteristics, in the case in which the thin film transistor operates in the saturation region, the gate voltage Vgs exceeds the threshold voltage Vth and increases, and then it is turned on to carry the drain current Ids. In principles, as expressed in Equation (1) for the transistor characteristics, if the gate voltage Vgs is constant, the same amount of the drain current Ids is supplied to the light emitting device at all times. Therefore, when video signals at the same level are supplied to all the individual pixels configuring the screen, all the pixels emit light at the same brightness, and the uniformity of the screen is supposed to obtain.
The drive current Ids necessary for the light emitting device formed of an organic electroluminescent device is as large as a few .mu.A per pixel, an N-channel drive transistor having high mobility .mu. is desirable in order to reduce the amplitude of the video signal to intend low power consumption. The pixel circuit shown in FIG. 11 is a source follower type in which an N-channel transistor is used for the drive transistor Trd.
Preferably, the channel length of the drive transistor is set to 10 .mu.m or greater. In addition, in the pixel circuit, the channel length of the drive transistor is set so that during the light emission period, the source potential of the drive transistor is varied, whereas the input voltage applied to the gate of the drive transistor is not varied with reference to the source potential. In addition, in the drive transistor, its output current has dependence on a carrier mobility in a channel region, and the third switching transistor conducts during the sampling period and connects the drive transistor to the third potential, takes the output current out of the drive transistor while the signal potential is being sampled, and applies the negative feedback of the output current to the pixel capacitance to correct the input voltage, whereby the dependence of the output current on the carrier mobility is cancelled.
According to an embodiment of the invention, the channel length of the drive transistor is made longer to suppress variations in the threshold voltage. With this configuration, variations are reduced in the gain in the bootstrap operation, and the uniformity of the screen can be improved significantly. More specifically, the channel length of the drive transistor is made longer than the channel length of the individual switching transistors, and the variations in the threshold voltage are suppressed. As compared with such a switching transistor that operates in the linear region as a mere switch, the threshold voltage of the drive transistor that operates in the saturation region in accordance with Equation (1) for the characteristics greatly affects the uniformity of the screen, and thus this configuration is effective. In addition, the channel length of the drive transistor is made longer than the channel length of the transistors configuring the peripheral scanner to suppress the variations in the threshold voltage, which is also effective. In the case in which the pixel array part and the scanner part are formed on the same substrate by TFT processes, the variations in the threshold voltage of the drive transistor greatly affect the uniformity of the screen, and thus it is effective that the channel length of the transistor of the scanner part is made much longer. In any cases, the channel length of the drive transistor is preferably set to 10 .mu.m or greater, whereby the range of the variations in the threshold voltage can be suppressed to such a level that does not affect the uniformity of the screen.
FIG. 1 shows a block diagram depicting the overall configuration of an image display device according to an embodiment of the invention;
Hereinafter, an embodiment of the invention will be described in detail with reference to the drawings. FIG. 1 shows a block diagram depicting the overall configuration of an image display device according to an embodiment of the invention. As shown in the drawing, the image display device is basically configured of a pixel array part 1, a scanner part and a signal part. The pixel array part 1 is configured of first scanning lines WS, second scanning line AZ1, third scanning lines AZ2 and fourth scanning lines DS arranged in rows, and signal lines SL arranged in columns, and pixel circuits 2 arranged in a matrix which are connected to the scanning lines WS, AZ1, AZ2 and DS and the signal lines SL, and a plurality of power source lines which supplies a first potential Vss1, a second potential Vss2 and a third potential Vcc necessary for the operation of the individual pixel circuits 2. The signal part is configured of a horizontal selector 3, which supplies video signals to the signal lines SL. The scanner part is configured of a write scanner 4, a drive scanner 5, a first correcting scanner 71 and a second correcting scanner 72, and they supply control signals to the first scanning lines WS, the fourth scanning lines DS, the second scanning lines AZ1 and the third scanning lines AZ2, and in turn scans the pixel circuits for every row.
Subsequently, when it goes to timing T2, the control signals AZ1 and AZ2 are at the high level, and then the switching transistors Tr2 and Tr3 are turned on. Consequently, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1-Vss2>Vth is satisfied, and Vss1-Vss2=Vgs>Vth is made, and after that, Vth correction to be done at timing T3 is prepared. In other words, the period from T2 to T3 corresponds to the reset period of the drive transistor Trd. In addition, when the threshold voltage of the light emitting device EL is VthEL, it is set to VthEL>Vss2. Thus, a negative bias is applied to the light emitting device EL, and the state is turned to a so-called reverse bias state. The reverse bias state is necessary to successfully perform the Vth correction operation and the mobility correcting operation.
At timing T3, the control signal AZ2 is turned to the low level, and right after this, the control signal DS is also turned to the low level. Thus, the transistor Tr3 is turned off, and the transistor Tr4 is turned on. Consequently, the drain current Ids is carried through the pixel capacitance Cs to start the Vth correction operation. At this time, the gate G of the drive transistor Trd is held at Vss1, and the current Ids is carried until the drive transistor Trd is cut off. When it is cut off, the source potential (S) of the drive transistor Trd is turned to Vss1-Vth. At timing T4 after the drain current is cut off, the control signal DS is again turned to the high level to cut off the switching transistor Tr4. Moreover, the control signal AZ1 is also returned to the low level, and the switching transistor Tr2 is also turned off. Consequently, Vth is held and fixed to the pixel capacitance Cs. As described above, the period from T3 to T4 is the period to detect the threshold voltage Vth of the drive transistor Trd. Here, the detecting period from T3 to T4 is called a Vth correction period.
As described above, after Vth correction is performed, the control signal WS is switched to the high level at timing T5, and the sampling transistor Tr1 is turned on to write the video signal Vsig to the pixel capacitance Cs. The pixel capacitance Cs is smaller enough than the equivalent capacitance Coled of the light emitting device EL. Consequently, most of the video signal Vsig is written to the pixel capacitance Cs. Precisely, Vsig-Vss1, the difference of Vsig from Vss1, is written to the pixel capacitance Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd is the level (Vsig-Vss1+Vth) that Vth detected and held before is added to Vsig-Vss1 sampled at this time. Hereinafter, for simplified description, when it is Vss1=0 V, the voltage Vgs between the gate and the source is Vsig+Vth as shown in the timing chart in FIG. 4. The sampling of the video signal Vsig is performed until timing T6 at which the control signal WS is returned to the low level. In other words, the period from T5 to T6 corresponds to the sampling period.
As described above, at timing T7, the gate potential (G) of the drive transistor Trd is allowed to rise, and the source potential (S) also rises together. This is the bootstrap operation. During the bootstrap operation, the voltage Vgs between the gate and the source held in the pixel capacitance Cs maintains the value of (Vsig+Vth). In other words, the bootstrap operation is that the anode potential Va of the light emitting device EL is allowed to rise while Vgs held in the pixel capacitance Cs is being maintained at constant. In association with the rise of the source potential of the drive transistor (S), that is, the rise of the anode potential Va of the light emitting device EL, the reverse bias state of the light emitting device EL is cancelled, and then the output current Ids flows to actually start the light emission of the light emitting device EL. The relation between the drain current Ids and the gate voltage Vgs at this time is given as Equation (2) below by substituting Vsig+Vth into Vgs of Equation (1) for the transistor characteristics above. Ids=k.mu.(Vgs-Vth)2=K.mu.(Vsig)2 (2)
Further with reference to FIG. 5, the loss in the bootstrap gain will be described in detail. Since the voltage Vgs between the gate and the source of the drive transistor Trd after the signal voltage Vsig is written has been subjected for Vth correction in advance, it is as below. Vgs=Vsig-Vss1+Vth Subsequently, the sampling transistor Tr1 is turned off, and then the switching transistor Tr4 is turned on, whereby the drive transistor Trd is connected to the power source Vcc, and the drain current Ids is carried through the light emitting device EL. At this time, the voltage corresponding to the drain current Ids is applied to the anode terminal of the light emitting device EL. In the timing chart shown in FIG. 4, the anode voltage (the source voltage of the drive transistor) at this time is denoted by Va. Thus, when the light emission operation, the source voltage of the drive transistor rises by Va-Vss1+Vth. On the other hand, since the gate voltage of the drive transistor Trd has the parasitic capacitance Cp, its rise is as below: (Va-Vss1+Vth).times.Cs/(Cs+Cp). AS described above, Vgs after the bootstrap operation is expressed by Equation (3) below. In addition, the drain current Ids corresponding to this Vgs is given by Equation (4) below. However, in Equation (3), Vss1 is 0 V for simplified description.
.times..times..times..times..times..times..times..mu..function..times. ##EQU00001##
Generally, the drive current necessary for the light emitting device such as an organic electroluminescent device is as large as a few .mu.A per pixel. In order to decrease the amplitude of the input video signal and to intend the low power consumption, the size ratio W/L of the drive transistor Trd is set as large as possible to enhance the current drive performance. On the other hand, it is preferable to reduce the pixel size for a high definition panel, and thus it is also preferable that the device area of the drive transistor Trd is small. Therefore, in order to design the drive transistor Trd to have the size ratio as large as possible and a smaller device area, generally, it tends to design a shorter length L (the channel length) of the drive transistor Trd. However, in TFTs having low temperature polysilicon in the device area, as shown in FIG. 6, the variations in the Vth characteristics are deteriorated as the length L of the drive transistor becomes shorter. Suppose the length L of the drive transistor Trd is designed short, because of the variations in the Vth characteristics, even though the influence of Vth is removed from the drain current Ids in the operation of canceling Vth, the Vth variations caused by the loss in the bootstrap gain are seen on the screen, causing the deteriorated uniformity. As apparent from Equation (3) described above, in such a pixel having Vth of the drive transistor Trd greater than that of the surrounding pixels, the brightness is relatively reduced more than that of the surrounding pixel, whereas in a pixel having a smaller Vth than that of the surrounding pixels, the brightness is relatively high. On this account, unevenness like streaks occurs on the screen.
For the measures against image quality defectives, in an embodiment of the invention, the length L of the drive transistor Trd is set long. More specifically, preferably, the length L of the drive transistor Trd is designed to be 10 .mu.m or greater. In the case in which the length L is 10 .mu.m or greater, as apparent from the graph shown in FIG. 6, the Vth variations are within 1 V. Here, in the case in which the loss in the bootstrap gain is 2.5%, the Vgs variations caused by the loss in the bootstrap gain are 25 mV. Suppose the gate voltage Vgs=2V that is applied to the drive transistor Trd in the white gray scale, the brightness difference caused by the variations is 2.5% by Equation (3). Generally, since the brightness difference visible in the uniformity in the white gray scale is 2 to 3%, the length L is designed to be 10 .mu.m or greater, which allows that the brightness variations caused by the loss in the bootstrap gain can be such level that can hardly visibly seen. Thus, the yields of fabricating the panel can be improved. As apparent from the graph shown in FIG. 6, in order to achieve high image quality, it is desirable that the length L of the drive transistor Trd is preferably longer from 15 .mu.m to 20 .mu.m.
Subsequently, when the period goes to timing T2, the control signals AZ1 and AZ2 are at the high level, and then the switching transistors Tr2 and Tr3 are turned on. Consequently, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1-Vss2>Vth is satisfied, and Vss1-Vss2=Vgs>Vth is made, and after that, Vth correction to be done at timing T3 is prepared. In other words, the period from T2 to T3 corresponds to the reset period of the drive transistor Trd. In addition, when the threshold voltage of the light emitting device EL is VthEL, it is set to VthEL>Vss2. Thus, a negative bias is applied to the light emitting device EL, and the state is a so-called reverse bias state. The reverse bias state is necessary to successfully perform the Vth correction operation and the mobility correcting operation.
As described above, after Vth correction is performed, the control signal WS is switched to the high level at timing T5, and the sampling transistor Tr1 is turned on to write the video signal Vsig to the pixel capacitance Cs. The pixel capacitance Cs is smaller enough than the equivalent capacitance Coled of the light emitting device EL. Consequently, most of the video signal Vsig is written to the pixel capacitance Cs. Precisely, Vsig-Vss1, the difference of Vsig from Vss1, is written to the pixel capacitance Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd is the level (Vsig-Vss1+Vth) that Vth detected and held before is added to Vsig-Vss1 sampled at this time. Hereinafter, for simplified description, when it is Vss1=0 V, the voltage Vgs between the gate and the source is Vsig+Vth as shown in the timing chart in FIG. 4. The sampling of the video signal Vsig is performed until timing T7 at which the control signal WS is returned to the low level. In other words, the period from T5 to T7 corresponds to the sampling period.
At timing T6 before timing T7 at which the sampling period is finished, the control signal DS is turned to the low level, and the switching transistor Tr4 is turned on. Thus, since the drive transistor Trd is connected to the power source Vcc, the pixel circuit goes from the non emission period to the light emission period. As described above, in the period from T6 to T7 in which the sampling transistor Tr1 is still in the ON state and the switching transistor Tr4 is in the ON state, the mobility of the drive transistor Trd is corrected. In other words, in this example, in the period from T6 to T7 in which the latter portion of the sampling period is overlapped with the beginning portion of the light emission period, the mobility is corrected. In addition, in the beginning of the light emission period in which the mobility is corrected, since the light emitting device EL is actually in the reverse bias state, it does not emit light. In the period from T6 to T7 to correct the mobility, the drain current Ids is carried through the drive transistor Trd in the state in which the gate G of the drive transistor Trd is fixed to the level of the video signal Vsig. Here, since Vss1-Vth<VthEL is set to allow the light emitting device EL in the reverse bias state, simple capacitance characteristics are shown, not the diode characteristics. Therefore, the current Ids carried through the drive transistor Trd is written to the capacitance C=Cs+Coled that combines the pixel capacitance Cs with the equivalent capacitance Coled of the light emitting device EL. Thus, the source potential (S) of the drive transistor Trd is rising. In the timing chart shown in FIG. 4, this rise is denoted by .DELTA. V. Since the rise .DELTA. V is eventually subtracted from the voltage Vgs between the gate and the source held in the pixel capacitance Cs, it means that negative feedback is applied. As described above, the negative feedback of the output current Ids of the drive transistor Trd is similarly applied to the input voltage Vgs of the drive transistor Trd, whereby the mobility .mu. can be corrected. In addition, the amount of negative feedback .DELTA. V can be optimized by adjusting the time width t of the period from T6 to T7 to correct the mobility.
At timing T7, the control signal WS is turned to the low level, and the sampling transistor Tr1 is turned off. Consequently, the gate G of the drive transistor Trd is separated from the signal line SL. Since the application of the video signal Vsig is released, the gate potential (G) of the drive transistor Trd is allowed to rise, and it rises together with the source potential (S). During this period, the voltage Vgs between the gate and the source held in the pixel capacitance Cs maintains the value of (Vsig-.DELTA. V+Vth). In association with the rise of the source potential (S), the reverse bias state of the light emitting device EL is cancelled, and then the output current Ids flows to actually start the light emission of the light emitting device EL. The relation between the drain current Ids and the gate voltage Vgs at this time is given as Equation (5) below by substituting Vsig-.DELTA. V+Vth into Vgs of Equation (1) for the transistor characteristics above. Ids=k.mu.(Vgs-Vth)2=k.mu.(Vsig-.DELTA.V)2 (5)
In Equation (5), k=(1/2) (W/L)Cox. It is revealed from Equation (5) for the characteristics that the term Vth is cancelled and the output current Ids supplied to the light emitting device EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting device EL is to emit light in accordance with the brightness corresponding to the video signal Vsig. At this time, Vsig is corrected by the amount of feedback .DELTA. V. The correcting amount .DELTA. V works so as to cancel the effect of the mobility .mu. positioned at the coefficient part of Equation (5) for the characteristics. Therefore, the drain current Ids substantially depends only on the video signal Vsig.
FIG. 9 shows a circuit diagram depicting the state of the pixel circuit 2 in the period from T6 to T7 to correct the mobility. As shown in the drawing, in the period from T6 to T7 to correct the mobility, the sampling transistor Tr1 and the switching transistor Tr4 are turned on, whereas the remaining switching transistors Tr2 and Tr3 are turned off. In this state, the source potential (S) of the drive transistor Tr4 is Vss1-Vth. The source potential (S) is also the anode potential of the light emitting device EL. As described above, Vss1-Vth<VthEL is set, and thus the light emitting device EL in the reverse bias state, and shows simple capacitance characteristics, not the diode characteristics. Therefore, the current Ids carried through the drive transistor Trd flows into the capacitance C=Cs+Coled that combines the pixel capacitance Cs with the equivalent capacitance Coled of the light emitting device EL. In other words, the negative feedback of a part of the drain current Ids is applied to the pixel capacitance Cs to correct the mobility.
FIG. 10 shows a graph depicting Equation (5) for the transistor characteristics described above, in which the vertical axis indicates Ids, and the horizontal axis indicates Vsig. Below the graph, Equation (5) for the characteristics is also shown. The graph shown in FIG. 10 depicts the characteristic curve as the pixel 1 is compared with the pixel 2. The mobility .mu. of the drive transistor of the pixel 1 is relatively great. In contrast to this, the mobility .mu. of the drive transistor included in the pixel 2 is relatively small. As described above, when the drive transistor is configured of a polysilicon thin film transistor, it is inevitable to vary the mobility .mu. among the pixels. For example, in the case in which the signal potential Vsig of the video signal at the same level is written to the pixels 1 and 2, if the mobility is not corrected at all, a large difference occurs between the output current Ids1' carried through the pixel 1 with a greater mobility .mu. and the output current Ids2' carried through the pixel 2' with a smaller mobility .mu.. As described above, since a large difference occurs between the output currents Ids caused by the variations in mobility .mu., unevenness like streaks occurs to impair the uniformity of the screen.
Then, in an embodiment of the invention, the negative feedback of the output current is applied to the input voltage side, whereby the variations in mobility are cancelled. As apparent from Equation (1) for the transistor characteristics, the greater mobility is, the larger the drain current Ids is. Therefore, the amount of negative feedback .DELTA.V becomes larger as the mobility is greater. As shown in the graph in FIG. 10, the amount of negative feedback .DELTA.V1 of the pixel 1 with a larger the mobility .mu. is greater than the amount of negative feedback .DELTA.V2 of the pixel 2 with a smaller mobility. Therefore, a larger negative feedback is applied as the mobility .mu. is greater, and then variations can be suppressed. As shown in the drawing, when .DELTA.V1 is corrected in the pixel 1 with a greater mobility .mu., the output current greatly drops from Ids1' to Ids1. On the other hand, sine the correcting amount .DELTA.V2 of the pixel 2 with a smaller mobility .mu. is small, the output current Ids2' does not so greatly drop to Ids2. Consequently, Ids1 is almost equal to Ids2, and the variations in mobility are cancelled. Since the cancellation of the variations in mobility is performed in the entire range of Vsig from the black level to the white level, the uniformity of the screen is significantly high. In summary, in the case in which there are the pixels 1 and 2 having different mobilities, the correcting amount .DELTA.V1 of the pixel 1 with a greater mobility is smaller than the correcting amount .DELTA.V2 of the pixel 2 with a smaller mobility. In other words, .DELTA.V is larger as the mobility is greater, and the reduced value of Ids is larger. Therefore, the mobility of the current values of the pixels having different mobilities is made equal, and the variations in mobility can be corrected.
Hereinafter for reference, the numerical analysis of mobility correction described above will be described. As shown in FIG. 9, in the state in which the transistor Tr1 and Tr4 are turned on, a variable V is taken for the source potential of the drive transistor Trd for analysis. The drain current Ids carried through the drive transistor Trd is as expressed in Equation (6) below where the source potential (S) of the drive transistor Trd is V. I.sub.ds=K.mu.(V.sub.gs-V.sub.th).sup.2=K.mu.(V.sub.sig-V-V.sub- .th).sup.2 (6)
.times..times..times..times..times..times..times..times..times..times..ti- mes..times..intg..times..times..times..intg..times..times..times..times..r- evreaction..intg..times..times..times..times..times..times..intg..times..t- imes..times..mu..function..times..times..times..times..times..revreaction.- .times..times..mu..times..times..revreaction..times..times..mu..times..tim- es..times..times..mu..times. ##EQU00002##
Equation (6) is substituted into Equation (7), and both sides are integrated. Here, the initial state of the source voltage V is -Vth, and the correcting time (T6 to T7) for mobility variations is t. When this differential equation is solved, the pixel current with respect to the time t to correct mobility is given by Equation (8) below.
.times..times..mu..times..times..times..mu..times. ##EQU00003##
The display device according to an embodiment of the invention has the device configuration of thin films as shown in FIG. 13. This drawing schematically shows the cross sectional structure of a pixel formed on an insulating substrate. As shown in the drawing, the pixel includes a transistor part including a plurality of thin film transistors (a single TFT is shown in the drawing), a capacitance part such as holing capacitance, and a light emitting part such as an organic electroluminescent device. The transistor part and the capacitance part are formed on the substrate by TFT processes, and the light emitting part such as the organic electroluminescent device is laminated thereon. A transparent counter substrate is bonded thereon with an adhesive to form a flat panel.
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