Source: http://www.google.com/patents/US7801225
Timestamp: 2017-11-24 22:23:39
Document Index: 587101719

Matched Legal Cases: ['Application No. 040126682', 'Application No. 18292', 'Application No. 2', 'Application No. 2', 'Application No. 040126682', 'Application No. 040126682', 'Application No. 99961782', 'Application No. 2001']

Patent US7801225 - Bit allocation among carriers in multicarrier communications - Google Patents
A technique is provided that may be employed in multicarrier communications to improve the efficiency of error correction using symbol-oriented error correction methodologies, by reducing the number of error correction code symbols (102, 104 . . . ) that are received in error that result from a single...http://www.google.com/patents/US7801225?utm_source=gb-gplus-sharePatent US7801225 - Bit allocation among carriers in multicarrier communications
Publication number US7801225 B2
Application number US 10/957,612
Also published as US6870888, US8218664, US20050058213, US20100195755
Publication number 10957612, 957612, US 7801225 B2, US 7801225B2, US-B2-7801225, US7801225 B2, US7801225B2
Original Assignee Shapiro Jerome M, Sandberg Stuart D, Tzannes Marcos C
Patent Citations (24), Non-Patent Citations (34), Classifications (8), Legal Events (5)
US 7801225 B2
1. A multicarrier data modulation method, comprising:
allocating a plurality of data bit signals of a serial input data stream among a plurality of carrier signals, wherein the plurality of data signals are modulated over the plurality of carrier signals by a modulation apparatus, wherein a predetermined number of the plurality of data bit signals are included in each one of a plurality of error correction symbols, wherein a number of the plurality of data bit signals modulated on at least one carrier signal is fewer than the predetermined number of data bit signals included in each of the plurality of error correction symbols, wherein each of said plurality of carrier signals is associated with a respective transmission channel, and wherein the allocating of the plurality of data bit signals among the carrier signals reduces a number of carrier signals that modulate data bit signals belonging to different error correction symbols during a transmission period.
2. The method according to claim 1, wherein each of the plurality of error correction symbols is a forward error correction coding symbol.
3. The method according to claim 1, wherein each of the plurality of error correction symbols has a size of one byte.
4. The method according to claim 1, wherein, during the transmission period, all of the data bit signals allocated to a one of the plurality of carrier signals are mapped to one error correction symbol.
5. The method according to claim 1, wherein the allocating the plurality of data bit signals among the plurality of carrier signals comprises determining numbers of data bit signals for transmission via the channels without exceeding a predetermined probability of bit transmission error, and allocating the plurality of data bit signals to the plurality of carrier signals in accordance with a carrier signal allocation sequence order, the order being such that the number of carrier signals that modulate data bit signals belonging to different error correction symbols is reduced.
6. The method according to claim 1, wherein the allocating the plurality of data bit signals among the plurality of carrier signals further comprises adjusting a transmission gain of at least one channel to change a data bit signal capacity of the at least one channel.
7. The method according to claim 5, wherein the allocating the plurality of data bit signals among the plurality of carrier signals further comprises adjusting a transmission gain of at least one channel to change a data bit signal capacity of the at least one channel.
8. A computer-readable memory comprising stored computer-executable program instructions that, in response to execution by a processor of an apparatus, enable the apparatus to:
provide a plurality of carrier signals for use in modulating a plurality of data bit signals of a serial input data stream, wherein a predetermined number of the plurality of data bit signals is included in each one of a plurality of error correction symbols before the plurality of data bit signals are modulated on the plurality of carrier signals, wherein a number of the plurality of data bit signals modulated on at least one carrier signal is fewer than the predetermined number of data bit signals included in each error correction symbol, and wherein each of said plurality of carrier signals is associated with a respective transmission channel; and
determine an allocation of the plurality of data bit signals among the plurality of carrier signals, wherein the allocation of the plurality of data bit signals among the plurality of carrier signals reduces a number of carrier signals that modulate data bit signals belonging to different error correction symbols during a transmission period.
9. The computer-readable memory according to claim 8, wherein each of the plurality of error correction symbols is a forward error correction coding symbol.
10. The computer-readable memory according to claim 8, wherein each of the plurality of error correction symbols has a size of one byte.
11. The computer-readable memory according to claim 8, wherein the allocation includes an allocation of only a set of data bit signals to a one of the plurality of carrier signals, wherein the set of data bit signals are mapped to only one error correction symbol.
12. The computer-readable memory according to claim 8, wherein the allocation comprises a determination of maximum numbers of bit signals transmittable via the channels without exceeding a desired maximum probability of bit transmission error, and an allocation of the maximum numbers of data bit signals to the plurality of carrier signals in accordance with a carrier signal allocation sequence order, the order being such that the number of carrier signals that are allocated data bit signals belonging to more than one error correction symbol during the transmission period is reduced.
13. The computer-readable memory according to claim 8, wherein the allocation comprises an adjustment of a transmission gain of at least one channel to change a data bit signal capacity of the at least one channel.
14. The computer-readable memory according to claim 12, wherein the allocation comprises an adjustment of a transmission gain of at least one channel to change a data bit signal capacity of the at least one channel.
15. A multicarrier data modulation system, comprising:
a transceiver adapted to generate a plurality of carrier signals for use in modulating a plurality of data bit signals of a serial input data stream; and
include a predetermined number of the plurality of data bit signals in each one of a plurality of error correction symbols before the plurality of data bit signals are modulated on the plurality of carrier signals, wherein a number of plurality of data bit signals configured to be modulated on at least one carrier signal is fewer than the predetermined number of the plurality of data bit signals that are included in each error correction symbol, and wherein each of said plurality of carrier signals is associated with a respective transmission channel, and
allocate the plurality of data bit signals among the plurality of carrier signals in a way that reduces the number of carrier signals that modulate data bit signals belonging to different error correction symbols during a transmission period.
16. The multicarrier data modulation system according to claim 15, wherein each of the plurality of error correction symbols is a forward error correction coding symbol.
17. The multicarrier data modulation system according to claim 16, wherein each of the plurality of error correction symbols has a size of one byte.
18. The multicarrier data modulation system according to claim 15, wherein, all the data bit signals allocated to a one of the plurality of carrier signals are mapped to only one error correction symbol.
19. The multicarrier data modulation system according to claim 15, wherein the processor is adapted to determine a maximum number of data bit signals transmittable via the channels without exceeding a desired maximum probability of bit transmission error, and to allocate the maximum number of data bit signals to the carrier signals in accordance with a carrier signal allocation sequence order, the order being such that the number of carrier signals that are allocated data bit signals belonging to different error correction symbols during transmission period is reduced.
20. The multicarrier data modulation system according to claim 15, wherein the processor is further adapted to adjust a transmission gain of at least one channel to change a data bit signal capacity of the at least one channel.
21. The multicarrier data modulation system according to claim 19, wherein the processor is further adapted to adjust a transmission gain of at least one channel to change a data bit signal capacity of the at least one channel.
22. A multicarrier data modulation method, comprising:
modulating, over a plurality of carrier signals, a plurality of data bit signals of a serial input data stream, wherein a predetermined number of the plurality of data bit signals is included in each one of a plurality of error correction symbols before the plurality of data bit signals are modulated on the plurality of carrier signals, wherein a number of data bit signals that are modulable on at least one carrier signal is fewer than the predetermined number of the plurality of data bit signals included in each error correction symbol, and wherein each of said plurality of carrier signals is associated with a respective transmission channel; and
allocating the plurality of data bit signals among the plurality of carrier signals, wherein the allocating of the plurality of data bit signals among the plurality of carrier signals reduces or minimizes the number of carrier signals that modulate data bit signals belonging to different error correction symbols during a transmission period.
23. The multicarrier data modulation method according to claim 22, wherein the allocating of the plurality of data bit signals comprises adjusting a signal-to-noise margin of at least one channel.
24. The multicarrier data modulation method according to claim 23, wherein the said adjusting is carried out in such a way so as to permit the at least one channel to be assigned data bit signals from only a single error correction symbol during the transmission period.
25. The multicarrier data modulation method according to claim 23, wherein the plurality of data bit signals are allocated among the plurality of carrier signals in accordance with a carrier signal allocation sequence order, the order being such that the number of carrier signals that modulate data bits signals belonging to different error correction symbols is reduced.
26. The multicarrier data modulation method according to claim 22, wherein the plurality of data bit signals are allocated among the plurality of carrier signals in accordance with a carrier signal allocation sequence order, the order being such that the number of carrier signals that modulate data bits signals belonging to different error correction symbols is reduced.
27. The multicarrier data modulation method according to claim 23, wherein a signal-to-noise ratio (SNR) of the at least one channel is approximately the sum of the SNR margin and a minimum required SNR for the at least one channel, wherein the data bit signals to be transmitted via the at least one channel belong to more than one error correction symbol during the transmission period, and wherein said adjusting comprises increasing the SNR margin so as to reduce the number of data bit signals transmittable by the at least one channel while decreasing an error rate probability associated with bit signal transmission via the at least one channel.
28. A method for modulating data bit signals over a transmission channel having a plurality of subchannels, comprising:
including a predetermined number of data bit signals of an input data stream to each of a plurality of error correction symbols;
modulating, over the plurality of subchannels, a plurality of data bit signals, including modulating over at least one of the plurality of subchannels fewer than the predetermined number of data bit signals included in each error correction symbol;
placing the plurality of subchannels into groups comprised of one or more subchannels based on data bit signal capacities of the subchannels, wherein a collective data bit signal capacity of each group comprises the predetermined number of data bit signals; and
allocating the plurality of data bit signals among the groups of subchannels such that data bit signals included in different error correction symbols are not modulated on the same subchannel, thereby reducing the number of error correction symbols that are affected by an error occurring on any given subchannel during a transmission period.
29. The method of claim 28, further comprising determining a subchannel order in which to allocate the plurality of data bit signals of the plurality of error correction symbols to the subchannels.
30. The method of claim 29, further comprising adjusting the number of data bit signals transmittable by a given subchannel.
31. The method of claim 30, wherein adjusting the number of data bit signals comprises adjusting a transmission gain for the given subchannel.
32. The method of claim 30, wherein adjusting the number of data bit signals comprises adjusting a signal-to-noise ratio for the given subchannel.
33. The method of claim 29, wherein the subchannel order is based upon the bit size of the error correction symbol and the number of data bit signals modulable on each subchannel.
34. The method of claim 28, further comprising adjusting the number of data bit signals transmittable by a given subchannel.
35. The method of claim 34, wherein adjusting the number of data bit signals comprises adjusting a transmission gain for the given subchannel.
36. The method of claim 34, wherein adjusting the number of data bit signals comprises adjusting a signal-to-noise ratio for the given subchannel.
37. The method of claim 28, wherein the allocating occurs during initialization of a multicarrier transceiver.
This application is a divisional of U.S. application Ser. No. 09/600,971 Jul. 20, 2000, now U.S. Pat. No. 6,870,888, which is a 371 of PCT/US99/27798, filed Nov. 23, 1999, which claims benefit of U.S. provisional patent application Ser. No. 60/109,876, filed Nov. 25, 1998, entitled “Method For Allocating Bits Among Carriers In A Multicarrier Communications System.” The entirety of the disclosure of said provisional application is incorporated herein by reference.
A superframe is 17 milliseconds in duration. A frame is effectively 250 micro-seconds in duration (or conversely, the frame rate is approximately 4 kHz) and is made up of a collection of bytes.
The bits comprised in each frame and superframe are transmitted over the subchannels. The number of bits carried on each subchannel (i.e., the “bit loading”) during each data symbol or data block transmission period is determined by transmitting a reference signal over the subchannels and measuring the characteristics of the subchannel, typically, the signal to noise ratio, based on this. The bit loading may vary from one subchannel to another, depending on the signal-to-noise ratio of the particular channels. The loading information is typically calculated at the receiving end of the subscriber line (e.g., at the subscriber premises in the case of transmission from the central office is to the subscriber) and is communicated to the other end. It is stored at both ends in the form of at least one “bit-loading table” that thereby defines the communications over the channel.
FIG. 6 illustrates an exemplary method of operation of the present invention.
It should be understood that each of the transceivers or modems 26, 34 comprises a respective processor 33 read only and random access memories (collectively referred to by numerals 50, 52, respectively), and transmitter and receiver circuitry blocks (not shown) which are interconnected via conventional bus circuitry (not shown), and are operable to permit the transceivers 26, 34 to carry out the DSL communications processes and the various other processes according to the present invention described herein. The read only and random access memories 50, 52 of these modems 26, 34 store program code instructions which are executable by the modems' processors, and when executed by the processors, cause the modems to carry out these processes. The memories 50, 52 also store the bit allocation tables 40, 42, respectively.
Referring now to FIG. 2, one example of a construction of the bit allocation table 42 that is used in the customer premises equipment is shown in further detail. Table 40, used at the central office, is essentially the same in construction and operation as table 42, and therefore, will not further be described. In column 50, table 42 lists the available communications channels in system 1 by channel number. In a full-rate ADSL system, there are up to two hundred and fifty-six such subchannels, each of bandwidth 4.1 kHz. For example, in one embodiment of the invention, upstream communications (i.e., from the customer premises to the central telephone office) are conducted on a first set of the channels while downstream communications (from the central office to the customer premises) are conducted on a second, different set of channels and a plurality of channels form a guard band between the upstream and down-stream communications that may be used for signaling between the modems 26, 34. For purposes of simplicity of illustration, however, only twelve channels are shown in the table portion 42 of FIG. 2.
In accordance with this embodiment of the present invention, the channel bit loading sequence order specified in columns 70. 72 of table 62 is such that the number of respective channels (and also, therefore, carrier signals associated with the channels) that are allocated bit signals belonging to more than one respective symbol of the data streams 100, 200 is minimized. More particularly, in table 62, during a respective data transmission period, respective bit signals allocated to respective channels are comprised in only a single respective symbol.
For example, if one assumes for purposes of illustration that data bits of the stream 100 illustrated in FIG. 4 are being transmitted during the first transmission period following initialization of the table 62, and each symbol has a size of eight bits, then in accordance with actual bit loading scheme of table 62, channel 2 is allocated all of the bits of the first symbol 102 of stream 100. Channel 9 is allocated all of the bits of the second symbol 104 of stream 100. Channel 3 is allocated 7 bits of the third symbol 106 of stream 100, and the remaining bit of 106 of stream 100 is allocated to channel 7. Channel 6 is allocated 6 bits of the fourth symbol 108 of stream 100, and the remaining two bits of the 108 is allocated to channel 5, and so forth, so as to ensure that in accordance with the bit loading specified in table 62, each of the channels is assigned bits from only a single respective symbol during a respective data transmission period.
As an example, consider the case where in bit allocation table 42 carriers numbered 2 and 9 do not have 8 respective bits allocated to them, but instead have 7 and 9 allocated to them respectfully. In this case, it would not be possible to order the loading of the channels in such a way that each of the channels is assigned bits from only a single respective symbol during a respective data transmission period. This problem can be solved if different channel transmission gains (e.g., different from G2 and G9) are used to change the numbers of bits allocated to these channels corresponding to these gains. For example, in most cases an additional 3 dB of transmission gain will enable the transmission of one additional bit on a channel with the same desired bit error rate probability. Therefore, if G2 is increased to G2+3 dB, and G9 is decreased to G9-3 dB, then channels 2 and 9 may each carry 8 bits (as in the original table 42) without changing the bit error rate probability of these channels, thereby enabling the use of a channel bit loading sequence order wherein each of the channels is assigned bits from only a single respective symbol during a respective data transmission period.
FIG. 6 illustrates an exemplary method for bit allocation among carriers in a multi-carrier communication system. In particular, control begins at step S100 and continues to step S110. In step S110, a plurality of carrier signals are provided for modulating data bit signals. Next, at step S120. the data bit signals are mapped to FECC signals. Control then continues to step S130.
In step S130, the plurality of data signals are allocated among the carrier signals. Optionally, in step S140, the respective maximum numbers of bit signals that may be transmitted via the respective channels without exceeding a desired maximum probability of bit transmission error are determined.
Optionally, in step S150, the respective actual number of bit signals to be transmitted via the respective channels based upon the respective maximum numbers are determined.
Alternatively, or in conjunction with steps S140 and S150, in step S160, the transmission gain of at least one channel is adjusted so as to change to a different number of bit signals a maximum number of bit signals that can be transmitted via the at least one channel without it exceeding a desired maximum probability of bit transmission error, and allocation of an actual number of bit signals to the carrier signal associated with the at least one channel in accordance with a different number. Control then continues to step S170.
In step S170, the bit signals are modulated using the carrier signals. Control then continues to step S180 where the control sequence ends.
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International Classification H04L1/00, H04K1/10, H04L27/26, H04L27/28
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHAPIRO, JEROME M.;SANDBERG, STUART D.;TZANNES, MARCOS C.;SIGNING DATES FROM 20000919 TO 20000925;REEL/FRAME:027085/0965