Source: http://www.google.com/patents/US7253026?dq=5,687,325
Timestamp: 2014-09-02 06:55:19
Document Index: 767530560

Matched Legal Cases: ['art.\n4', 'art.\n5', 'art 112', 'art 112', 'art 112', 'art 112', 'art 112', 'art 512', 'art 512', 'art 512', 'art 512', 'art 512', 'art 612', 'art 612', 'arts 720', 'arts 720', 'arts 720', 'arts 720', 'arts 720', 'art 934', 'art 936', 'art 936', 'art 934', 'art 934', 'art 936', 'art 572', 'art 572', 'art 572', 'art 572', 'art 572', 'art 572', 'art 572']

Patent US7253026 - Ultra-thin semiconductor package device and method for manufacturing the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness...http://www.google.com/patents/US7253026?utm_source=gb-gplus-sharePatent US7253026 - Ultra-thin semiconductor package device and method for manufacturing the sameAdvanced Patent SearchPublication numberUS7253026 B2Publication typeGrantApplication numberUS 11/324,831Publication dateAug 7, 2007Filing dateJan 3, 2006Priority dateMar 5, 2001Fee statusPaidAlso published asDE10210903A1, US7012325, US20020121680, US20060110858Publication number11324831, 324831, US 7253026 B2, US 7253026B2, US-B2-7253026, US7253026 B2, US7253026B2InventorsSang-Ho Ahn, Se-Yong OhOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (20), Non-Patent Citations (9), Referenced by (2), Classifications (77), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetUltra-thin semiconductor package device and method for manufacturing the sameUS 7253026 B2Abstract An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30-50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.
1. A method of manufacturing an ultra-thin semiconductor package device, said method comprising:
preparing a lead frame comprising a die pad, a tie bar connected to and supporting the die pad, and a plurality of leads disposed around the die pad;
defining a chip attaching part and a peripheral part on the die pad, said peripheral part surrounding the chip attaching part;
etching the chip attaching part so that the chip attaching part has a thickness less than a thickness of the leads, wherein the die pad peripheral part and the tie bar each have a thickness equal to the thickness of the leads;
die bonding a semiconductor chip to the chip attaching part of the die pad;
wire bonding the semiconductor chip to the leads; and
forming a package body by encapsulating the semiconductor chip, bonding wires, and a portion of the leads.
2. A method according to claim 1, wherein the thickness of the chip attaching part is between 30-50% of the thickness of the leads.
3. A method according to claim 1, wherein the die pad peripheral part protrudes upwardly and downwardly from the chip attaching part.
4. A method according to claim 1, wherein the die pad peripheral part protrudes in a single vertical direction from the chip attaching part.
5. A method according to claim 4, wherein the die pad is disposed below the leads.
6. A method according to claim 1, wherein an upper portion of the package body has a thickness different than a thickness of a lower portion of the package body.
preparing a wafer having a plurality of semiconductor chips formed on an active surface of the wafer;
attaching an adhesive layer to the backside of the semiconductor chips and attaching a UV tape to the adhesive layer;
irradiating the UV tape with UV light to remove the adhesiveness between the UV tape and the adhesive layer;
cutting the wafer into the plurality of semiconductor chips; and
removing the plurality of semiconductor chips from the wafer state UV tape, wherein the adhesive layer remains attached to the backside of the chips, and wherein said die bonding attaches the chips to the chip attaching part using the adhesive layer.
8. A method according to claim 7, wherein the wafer preparation step comprises:
attaching a UV tape to the active surface of the semiconductor chip;
grinding a backside opposite to the active surface of the semiconductor chip;
irradiating the UV tape attached to the active surface with UV light; and
removing the UV tape from the active surface of the semiconductor chip.
9. A method according to claim 7, wherein the adhesive layer comprises an epoxy resin.
10. A method according to claim 9, wherein the adhesive layer comprises a hardener made of amine.
11. A method according to claim 9, wherein the adhesive layer comprises a coupling agent made of silane.
12. A method according to claim 1, wherein the semiconductor chip comprises a first chip attached to a top surface of the chip attaching part and a second chip attached to a bottom surface of the chip attaching part, and wherein said die bonding comprises a first die bonding step for bonding the first chip and a second die bonding step for bonding the second chip.
13. A method according to claim 12, wherein the package body has a balanced structure with reference to the semiconductor chips.
14. A method according to claim 1, wherein the semiconductor chip comprises a first chip attached to a top surface of the chip attaching part and a second chip attached to a bottom surface of the chip attaching part, and wherein wire bonding comprises a first wire bonding step for electrically interconnecting the first chip to the leads and a second wire bonding step for electrically interconnecting the second chip to the leads.
15. A method according to claim 14, wherein bonding wires connected to one of the chips have different lengths from the bonding wires connected to the other chip.
16. A method according to claim 1, wherein the bonding wires are connected by balls formed on surfaces of the leads and stitches formed on the electrode pads.
17. A method according to claim 1, wherein forming the package body comprises injecting a mold resin in a temperature environment ranging between about 170 and 175� C.
18. A method according to claim 1, wherein the amount of etching is determined by a pressure and an applying time of an etchant.
19. A method o F manufacturing an ultra-thin semiconductor package device, said method comprising:
cutting the wafer into the plurality of semiconductor chips;
etching the chip attaching part so that the chip attaching part has a thickness less than a thickness of the leads;
removing the plurality of semiconductor chips from the wafer state UV tape, wherein the adhesive layer remains attached to the backside of the chips;
die bonding the semiconductor chips to the chip attaching part of the die pad using the adhesive layer;
wire bonding the semiconductor chips to the leads; and
forming a package body by encapsulating the semiconductor chips, bonding wires, and a portion of the leads.
20. A method of manufacturing an ultra-thin semiconductor package device, said method comprising:
etching the chip attaching part so that the chip attaching part has a thickness less than a thickness of the leads, wherein the amount of etching is determined by a pressure and an applying time of an etchant;
RELATED APPLICATION This application is a Divisional of U.S. patent Ser. No. 10/008,704, filed on Dec. 6, 2001 now U.S. Pat. No. 7,012,325, now pending, which claims priority from Korean Patent Application Nos. 2001-11182, filed on Mar. 5, 2001 and 2001-38717, filed on Jun. 30, 2001, which are herein incorporated by reference in their entirety.
Referring to FIG. 1, a conventional semiconductor package 10 includes a die pad 13 and a lead frame 15 having a plurality of leads 14. A semiconductor IC chip 11 is bonded to the die pad 13 by an adhesive 12. The semiconductor IC chip 11 is electrically interconnected to the leads 14 via bonding wires 16. The semiconductor IC chip 11 and bonding wires 16 are protected by a package body 17 made of an epoxy molding compound. Outer portions of the leads 14, which protrude from the package body 17, are bent in a form suitable for mounting the package onto a circuit board (not shown).
One of the advantages of the present invention lies in that the thickness of the die pad is smaller than the thickness of the leads. The die pad thickness is preferably equal to or less than 50%, and more preferably ranging between 30-50%, of the thickness of the leads. The overall thickness of the package device is preferably equal to or less than 0.7 mm.
According to another aspect of the present invention, a method of manufacturing an ultra-thin package device includes preparing a lead frame including a die pad, a tie bar, and a plurality of leads. The die pad is provided with a chip attaching part and a peripheral part surrounding the chip attaching part. The chip attaching part is etched to make it thinner. The amount of etching of the chip attaching part can be determined by a pressure and applying time of an etchant. The semiconductor chip is die bonded to the chip attaching part of the die pad. The semiconductor chip and leads are electrically interconnected through wire bonding. A package body is then formed by encapsulating the semiconductor chip, bonding wires, and inner portions of the leads. The package body is preferably formed at a low-temperature (i.e., under about 170-175� C.).
FIG. 3 a is a cross-sectional view of the semiconductor package of FIG. 2 taken along a line III-III, and FIG. 3 b is a partial detail view of the package of FIG. 3 a. FIG. 4 is a cross-sectional view of the semiconductor package of FIG. 2 taken along a line IV-IV.
First Embodiment FIG. 2 is a partial plan view of an ultra-thin semiconductor package according to a first embodiment of the present invention. FIG. 3 a is a cross-sectional view of the ultra-thin semiconductor package of FIG. 2, taken along line III-III. FIG. 3 b is a partial detail view of the ultra-thin semiconductor package of FIG. 3 a. FIG. 4 is a cross-sectional view of the ultra-thin semiconductor package of FIG. 2, taken along line IV-IV.
One of the advantages of various embodiments of the present invention lies in the fact that the thickness t1 of the chip attaching part 112 a of the die pad 112 is smaller than the thickness t2 of the leads 116. The lead frame 110 used in the production of the package device 100 is conventionally made of copper or iron-nickel alloy (e.g., alloy42). As explained below, the lead frame 110 is prepared from a thin metal plate, and the die pad 112, tie bar 114, and leads 116 are formed by etching or stamping the metal plate. Additional elements, including a dam bar and a side rail, are also formed by etching or stamping. These elements are not shown in the drawings, however, since they are not included in the final package device 100.
The lead frame 110 can have various thicknesses depending on the type of the package device 100. The lead frame thickness is being increasingly reduced according to the miniaturization trend in package devices. For example, lead frames traditionally having a thickness of 300 μm (12 mil), 250 μm (10 mil), 200 μm (8 mil), and 150 μm (6 mil) a currently being replaced with 100 μm (4 mil) lead frames. According to various aspects and embodiments of the present invention, even when a lead frame 110 having a thickness of about 100 μm is employed, the thickness of the die pad 112 (and particularly the chip attaching part 112 a) can be made ultra-thin. For example, the thickness of the chip attaching part 112 a can be reduced to between about 30-50% of the lead frame thickness. The thickness of leads 116 (t2) can be about 100 μm, while the thickness of the die pad 112 (t1) is about 40 μm. The tie bar 114 can have the same thickness as the die pad 112 (e.g., 40 μm). In this embodiment, the chip attaching part 112 a of the die pad 112 has a substantially identical thickness with the peripheral part 112 b. By making the die pad 112 thinner, it is possible to reduce the overall thickness of the package device 100. In this embodiment, the thickness (T) of the package device 100 is about 0.58 mm. Referring specifically to FIG. 3 b, the thickness of each of the adhesive layers 122 is between about 10-20 μm, the thickness (t3) of the semiconductor IC chip 120 is between about 100-150 μm, and the height (or loop height) (t4) of the bonding wires 124 from the upper surface of the chip 120 is about 80 μm.
The Second and Third Embodiments In the preceding embodiment, the die pad 112 is partially removed on both sides. In the second and third embodiments, described below, only one side of the die pad 112 is partially removed. If the die pad 112 is partially removed on one side, the die pad 112 will not align with both the top and bottom surfaces of the leads 116. In other words, the die pad 112 will appear to be shifted away from a center of package body 126 in either an upward or downward direction. This causes an imbalanced package body 126 in relation to the active surface (the surface where the chip electrode pads are formed) of each of the upper and lower semiconductor chips 120 a and 120 b. This may result in incomplete molding of the package body 126.
The Fourth Embodiment A fourth embodiment of the present invention will now be described with reference to FIGS. 7 a and 7 b, which provide cross-sectional views of the ultra-thin package device according to this embodiment.
The Fifth Embodiment FIGS. 8 to 10 show a stack package device having a die pad thickness made different from a lead thickness by partially removing one side of the die pad, according to a fifth embodiment of the present invention. Referring to FIG. 8, a stack package device 500 includes upper and lower semiconductor chips 120 a and 120 b attached, via an adhesive 122, to respective upper and lower sides of a die pad chip attaching part 512 a. A peripheral part 512 b of the die pad 512 is thicker than the chip attaching part 512 a but has the same thickness as the inner leads 516 a. The thickness of the chip attaching part 512 a is preferably about 30-50% of the thickness of the peripheral part 512 b. As a result, the die pad 512 has a cross-section having an approximate �U� shape, in which the protruding portions 512 b at the ends point upward.
The Sixth Embodiment In the stack package structure 600 of FIG. 10, according to a sixth embodiment of the invention, different die pad and lead thicknesses are obtained by partially removing one side of the die pad 612 a, as the fifth embodiment. Also similar to the fifth embodiment, the die pad chip attaching part 612 a has a thickness of approximately 30-50% of the thickness of the die pad peripheral part 612 b and the inner leads 616 a, which share the same thickness.
The Seventh Embodiment According to a seventh embodiment of this invention, the die pad can be divided into at least two portions. FIGS. 11 a and 11 b provide a plan view and cross-sectional view, respectively of an ultra-thin package device 700 in accordance with this embodiment.
The first and second die pads 720, 730 of the package device 700 in the seventh embodiment of the present invention include chip attaching parts 720 a, 730 a and peripheral parts 720 b, 730 b, respectively. The thickness of the chip attaching parts 720 a, 730 a is about 30-50% of the thickness of leads 716. Also, although FIGS. 11 a and 11 b show identical thicknesses of the die pad peripheral parts 720 b, 730 b and the chip attaching parts 720 a, 730 a, it is also possible to make the thickness of the peripheral parts the same as the thickness of the leads, similar to the fourth through sixth embodiments.
Referring FIG. 13 e, in the first die bonding step, each chip 910 is attached to a die pad 932 of a lead frame 930 produced according to the process of FIGS. 12 a through 12 f. The lead frame 930 includes the die pad 932 and leads 938. The die pad 932 includes a chip attaching part 934 and a peripheral part 936. The peripheral part 936 protrudes from the chip attaching part 934 and has the same thickness as the leads 938. The thickness of the chip attaching part 934 preferably ranges between about 30-50% of the thickness of the peripheral part 936.
Because the package device according to the present invention has very small thickness, the curing speed of the package body is higher. It is preferable, therefore to perform the molding step at a low temperature. The formation of the package body is preferably performed in a temperature environment ranging between about 170-175� C.
The ultra-thin package devices of the present invention can be used in various portable electronic appliances including digital cameras, MP3 players, Handheld Personal Computers (HPCs), Personal Digital Assistants (PDAs), mobile phones, and other devices. FIGS. 14 a and 14 b, for example, show a memory card into which an ultra-thin package device of the present invention is integrated. FIG. 14 a is a plan view of the memory card and FIG. 14 b is a cross-sectional view taken along the line 14 b-14 b of FIG. 14 a. Generally, memory cards are produced using flash memories. Several companies presently manufacture memory cards. For example, SmartMedia memory cards by Toshiba, MemoryStick cards by Sony, CompactFlash cards by Sandisk, MultiMedia Cards by Gimens and Sandisk, and SD (Secure Digital) cards are all available. The embodiment shown in FIGS. 14 a and 14 b shows the implementation of this invention in a MemoryStick memory card.
The thin package technology of the present invention can also be applied to a package device using a single semiconductor IC chip. Examples of this aspect of the invention are shown in FIGS. 15 and 16. Referring to FIG. 15, a package device 550 includes a single semiconductor IC chip 120. A chip attaching part 572 a of a die pad 572, to which the chip 120 is attached, is thinner than a die pad peripheral part 572 b. The thickness of the chip attaching part 572 a is preferably between about 30-50% of the thickness of the peripheral part 572 b. Leads 516 have the same thickness as the peripheral part 572 b. The peripheral part 572 b protrudes upwards towards the chip 120 from the chip attaching part 572 a, and the die pad is down set to achieve a balanced structure with reference to the leads 516.
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