Source: http://www.google.com/patents/US8225242
Timestamp: 2015-01-28 12:37:01
Document Index: 609948670

Matched Legal Cases: ['Application No. 038246783', 'Application No. 03824678', 'Application No. 03824678', 'Application No. 03', 'Application No. 03', 'Application No. 03', 'Application No. 2004', 'Application No. 2004', 'Application No. 2005', 'Application No. 2005', 'Application No. 92126114']

Patent US8225242 - Highly compact non-volatile memory and method thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar...http://www.google.com/patents/US8225242?utm_source=gb-gplus-sharePatent US8225242 - Highly compact non-volatile memory and method thereofAdvanced Patent SearchPublication numberUS8225242 B2Publication typeGrantApplication numberUS 12/274,959Publication dateJul 17, 2012Filing dateNov 20, 2008Priority dateSep 24, 2002Also published asCN1698131A, CN1698131B, EP1554732A1, US6983428, US20040060031, US20050219910, US20090086543, US20120281472, WO2004029976A1Publication number12274959, 274959, US 8225242 B2, US 8225242B2, US-B2-8225242, US8225242 B2, US8225242B2InventorsRaul-Adrian CerneaOriginal AssigneeSandisk Technologies Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (58), Non-Patent Citations (18), Classifications (18), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetHighly compact non-volatile memory and method thereofUS 8225242 B2Abstract A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.
CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of application Ser. No. 11/144,540, filed on Jun. 3, 2005, publication no. 2005/0219910 A1, now abandoned, which in turn is a divisional of application Ser. No. 10/254,483, filed on Sep. 24, 2002 now U.S Pat. No. 6,983,428, which applications are incorporated herein in their entirety by this reference.
FIELD OF THE INVENTION This invention relates generally to non-volatile semiconductor memory such as electrically erasable programmable read-only memory (EEPROM) and flash EEPROM, and specifically ones having highly compact and high performance write and read circuits
It will be understood that for multi-state memory, each of the master flip-flops, M, and the slave flip-flops, S, becomes an array with a dimension commensurate with the number of data bits required. For example, for a 4-state memory cell, the states will be encoded by two binary bits of data. M represents M(1) and M(2) and S represents S(1) and S(2) for each of the two bits respectively. Thus the �2k shift latch� will be formed by M1(1), S1(1), M1(2), S1(2), M2(1), S2(1), M2(2), S2(2), . . . , Mk(1), Sk(1), Mk(2), Sk(2).
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No. 11/122,738 on Oct. 18, 2005, 9 pages.Classifications U.S. Classification716/100, 365/185.11International ClassificationG11C7/18, G11C16/10, G11C7/06, G11C7/10, G11C16/26Cooperative ClassificationG11C16/10, G11C7/18, G11C7/06, G11C16/26, G11C2216/14, G11C7/1006European ClassificationG11C16/26, G11C7/10L, G11C16/10, G11C7/18, G11C7/06Legal EventsDateCodeEventDescriptionMay 20, 2011ASAssignmentOwner name: SANDISK TECHNOLOGIES INC., TEXASEffective date: 20110404Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDISK CORPORATION;REEL/FRAME:026317/0483RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services