Source: https://patents.google.com/patent/US7042898B2/en
Timestamp: 2019-12-11 23:59:16
Document Index: 455481165

Matched Legal Cases: ['§120', '§120', '§119', '§120', '§ 119', '§120']

US7042898B2 - Reducing delays associated with inserting a checksum into a network message - Google Patents
Reducing delays associated with inserting a checksum into a network message Download PDF
US7042898B2
US7042898B2 US09/802,426 US80242601A US7042898B2 US 7042898 B2 US7042898 B2 US 7042898B2 US 80242601 A US80242601 A US 80242601A US 7042898 B2 US7042898 B2 US 7042898B2
US09/802,426
US20010036196A1 (en
2001-03-09 Application filed by Alacritech Inc filed Critical Alacritech Inc
2001-06-19 Assigned to ALACRITECH, INC. reassignment ALACRITECH, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIGGEN, DAVID A., BLIGHTMAN, STEPHEN E. J., BOUCHER, LAURNCE B., CRAFT, PETER K., PHILBRICK, CLIVE M., STARR, DARYL D.
2001-10-02 Priority claimed from US09/970,124 external-priority patent/US7124205B2/en
2001-11-01 Publication of US20010036196A1 publication Critical patent/US20010036196A1/en
2002-03-06 Priority claimed from US10/092,967 external-priority patent/US6591302B2/en
2003-11-28 Priority claimed from US10/724,588 external-priority patent/US7502869B2/en
2006-05-09 Publication of US7042898B2 publication Critical patent/US7042898B2/en
2006-10-16 Priority claimed from US11/582,199 external-priority patent/US7664883B2/en
2007-01-22 Priority claimed from US11/656,809 external-priority patent/US7694024B2/en
2007-06-25 Priority claimed from US11/821,820 external-priority patent/US7673072B2/en
2021-04-26 Adjusted expiration legal-status Critical
230000001934 delay Effects 0 title 1
235000010384 tocopherol Nutrition 0 abstract 3
235000019731 tricalcium phosphate Nutrition 0 abstract 3
A first partial checksum for the header portion of a TCP header is generated on an intelligent network interface card (INIC) before all the data of the data payload of the TCP message has been transferred to the INIC. A pseudopacket with the first partial checksum and the data is assembled in DRAM on the INIC as the data arrives onto the INIC. When the last portion of the data of the data payload is received onto the INIC, a second partial checksum for the data payload is generated. The pseudopacket is read out of DRAM for transfer to a network. While the pseudopacket is being transferred, the second partial header is combined with the first partial header and the resulting final checksum is inserted into the pseudopacket so that a complete TCP packet with a correct checksum is output from the INIC to the network.
This application is a continuation-in-part of and claims the benefit under 35 U.S.C. §120 of U.S. patent application Ser. No. 09/464,283, filed Dec. 15, 1999, by Laurence B. Boucher et al., now U.S. Pat. No. 6,427,173, which in turn is a continuation-in-part of and claims the benefit under 35 U.S.C. §120 of U.S. patent application Ser. No. 09/439,603, filed Nov. 12, 1999, by Laurence B. Boucher et al., now U.S. Pat No. 6,247,060, which in turn claims the benefit under 35 U.S.C. §119(e)(1) of the Provisional Application Ser. No. 60/061,809, filed on Oct. 14, 1997. This application also is a continuation-in-part of and claims the benefit under 35 U.S.C. §120 of U.S. patent application Ser. No. 09/384,792, filed Aug. 27, 1999, now U.S. Pat. No. 6,434,620, which in turn claims the benefit under 35 U.S.C. § 119(e)(1) of the Provisional Application Ser. No. 60/098,296, filed Aug. 27, 1998. This application also is a continuation-in-part of and claims the benefit under 35 U.S.C. §120 of U.S. patent application Ser. No. 09/067,544, filed Apr. 27, 1998, now U.S. Pat. No. 6,226,880. The subject matter of all the above-identified patent applications, and of the two above-identified provisional applications, is incorporated by, reference herein.
FIG. 1 (Prior Art) is a simplified diagram of a TCP packet. FIG. 2 is a simplified diagram of a network interface card (NIC) 100 card called an intelligent network interface card (INIC). One of the operations the INIC performs is to read data for a TCP packet out of host memory 101 on a host computer 102 and to transmit that data as the data payload of a TCP message onto a network 107.
A first partial checksum for the header portion of a TCP header is generated on an intelligent network interface card (INIC) before all the data of the data payload of the TCP message has been transferred to the INIC. A pseudopacket with the first partial checksum and the data is assembled in DRAM on the INIC as the data arrives onto the INIC. When the last portion of the data of the data payload is received onto the INIC, a second partial checksum for the data payload is generated. This second partial checksum is not, however, written into DRAM. Rather, the pseudopacket is read out of DRAM for transfer to the network and while the pseudopacket is being transferred the second partial header is combined with the first partial header such that the resulting final TCP checksum is inserted into the pseudopacket. The pseudopacket is therefore converted into a complete TCP packet with a correct checksum as it is output from the INIC to the network.
FIG. 1 is a simplified diagram of a TCP packet.
FIG. 3 is a diagram of an intelligent network interface card (INIC) 200 in accordance with one embodiment of the present invention. INIC 200 is coupled to host computer 201 via PCI bus 202. For additional information on INIC 200, see U.S. patent application Ser. No. 09/464,283, filed Dec. 15, 1999 (the subject matter of which is incorporated herein by reference).
(a) transferring a data payload from a host memory to a first memory of a network interface device;
(b) on the network interface device and before the transferring of (a) is complete creating a pseudoheader and storing the pseudoheader in a second memory of the network interface device, the pseudoheader containing a header portion and a checksum portion, the checksum portion being a checksum of the header portion and not a checksum of the data payload;
(c) on the network interface device and before the transferring of (a) is complete transferring the pseudoheader from the second memory to the first memory;
(d) after (c) generating on the network interface device a checksum for the data payload; wherein the pseudoheader and the data payload together comprise a pseudopacket; and
(e) reading the pseudoheader and at least a portion of the data payload from the first memory and combining the checksum for the header portion with the checksum for the data payload to generate a final checksum, the final checksum being inserted into the pseudopacket to form a complete TCP packet, the complete TCP packet being output from the network interface device to a network.
2. The method of claim 1, wherein the first memory is DRAM and wherein the second memory is SRAM.
(a) means for transferring a data payload from a host memory to a first memory of a network interface device;
(b) means for creating, before the transferring of (a) is complete, a pseudoheader and storing the pseudoheader in a second memory of the network interface device, the pseudoheader containing a header portion and a checksum portion, the checksum portion being a checksum of the header portion and not a checksum of the data payload;
(c) means for transferring, before the transferring of (a) is complete, the pseudoheader from the second memory to the first memory;
(d) means for generating, after (c), a checksum for the data payload wherein the pseudoheader and the data payload together comprise a pseudopacket; and
(e) means for reading the pseudheader and at least a portion of the data payload from the first memory and for combining the checksum for the header portion with the checksum for the data payload to generate a final checksum, the final checksum being inserted into the pseudopacket to form a complete TCP packet, the complete TCP packet being output from the network interface device to a network.
6. The apparatus of claim 5, wherein the apparatus comprises a host computer, the network interface device being a part of the host computer, the host memory being another part of the host computer.
US09/802,426 1997-10-14 2001-03-09 Reducing delays associated with inserting a checksum into a network message Active 2021-04-26 US7042898B2 (en)
US09/970,124 US7124205B2 (en) 1997-10-14 2001-10-02 Network interface device that fast-path processes solicited session layer read commands
US10/092,967 US6591302B2 (en) 1997-10-14 2002-03-06 Fast-path apparatus for receiving data corresponding to a TCP connection
US10/724,588 US7502869B2 (en) 1997-10-14 2003-11-28 Intelligent network interface system and method for accelerated protocol processing
US11/582,199 US7664883B2 (en) 1998-08-28 2006-10-16 Network interface device that fast-path processes solicited session layer read commands
US11/821,820 US7673072B2 (en) 1997-10-14 2007-06-25 Fast-path apparatus for transmitting data corresponding to a TCP connection
US09/464,283 Continuation-In-Part US6427173B1 (en) 1997-10-14 1999-12-15 Intelligent network interfaced device and system for accelerated communication
US09/801,488 Continuation-In-Part US6687758B2 (en) 2001-03-07 2001-03-07 Port aggregation for network connections that are offloaded to network interface devices
US09/802,550 Continuation-In-Part US6658480B2 (en) 1997-10-14 2001-03-09 Intelligent network interface system and method for accelerated protocol processing
US09/802,551 Continuation-In-Part US7076568B2 (en) 1997-10-14 2001-03-09 Data communication apparatus for computer intelligent network interface card which transfers data between a network and a storage device according designated uniform datagram protocol socket
US09/970,124 Continuation US7124205B2 (en) 1997-10-14 2001-10-02 Network interface device that fast-path processes solicited session layer read commands
US20010036196A1 US20010036196A1 (en) 2001-11-01
US7042898B2 true US7042898B2 (en) 2006-05-09
ID=36499105
US09/802,426 Active 2021-04-26 US7042898B2 (en) 1997-10-14 2001-03-09 Reducing delays associated with inserting a checksum into a network message
US (1) US7042898B2 (en)
US20050286560A1 (en) * 2004-06-28 2005-12-29 Intel Corporation Processing receive protocol data units
US20060031818A1 (en) * 1997-05-08 2006-02-09 Poff Thomas C Hardware accelerator for an object-oriented programming language
US20070118665A1 (en) * 1997-10-14 2007-05-24 Philbrick Clive M TCP/IP offload device with fast-path TCP ACK generating and transmitting mechanism
US7779330B1 (en) * 2005-11-15 2010-08-17 Marvell International Ltd. Method and apparatus for computing checksum of packets
US8453035B1 (en) * 2008-03-25 2013-05-28 Oracle America, Inc. Method for efficient generation of a fletcher checksum using a single SIMD pipeline
US10033840B2 (en) 2000-04-17 2018-07-24 Circadence Corporation System and devices facilitating dynamic network link acceleration
US6728929B1 (en) * 2001-02-16 2004-04-27 Spirent Communications Of Calabasas, Inc. System and method to insert a TCP checksum in a protocol neutral manner
US7161960B2 (en) * 2002-03-26 2007-01-09 Nokia Corporation Apparatus, and associated method, for forming, and operating upon, multiple-checksum-protected data packet
US7134070B2 (en) * 2003-09-08 2006-11-07 Intel Corporation Checksum determination
US9490939B2 (en) * 2013-10-07 2016-11-08 Electronics And Telecommunications Research Instit Apparatus and method for calculating transmission control protocol checksum
US20170093709A1 (en) * 2015-09-25 2017-03-30 Karl S. Papadantonakis Crc update mechanism
WO2019106445A1 (en) * 2017-11-28 2019-06-06 Marvell World Trade Ltd. Distributed checksum calculation for communication packets
US10469633B2 (en) 2018-03-29 2019-11-05 Marvell World Trade Ltd. Low-latency pipeline for media-to-ethernet frame packaging
US4336538A (en) 1975-07-26 1982-06-22 The Marconi Company Limited Radar systems
US5541920A (en) * 1995-06-15 1996-07-30 Bay Networks, Inc. Method and apparatus for a delayed replace mechanism for a streaming packet modification engine
WO1998019412A1 (en) 1996-10-31 1998-05-07 Iready Corporation Multiple network protocol encoder/decoder and data processor
WO1999004343A1 (en) 1997-07-18 1999-01-28 Interprophet Corporation Tcp/ip network accelerator system and method
WO2000013091A1 (en) 1998-08-28 2000-03-09 Alacritech, Inc. Intelligent network interface device and system for accelerating communication
WO2001005123A1 (en) 1999-07-13 2001-01-18 Alteon Web Systems, Inc. Apparatus and method to minimize incoming data loss
WO2001005116A2 (en) 1999-07-13 2001-01-18 Alteon Web Systems, Inc. Routing method and apparatus
WO2001004770A2 (en) 1999-07-13 2001-01-18 Alteon Web Systems, Inc. Method and architecture for optimizing data throughput in a multi-processor environment using a ram-based shared index fifo linked list
WO2001005107A1 (en) 1999-07-13 2001-01-18 Alteon Web Systems, Inc. Apparatus and method to minimize congestion in an output queuing switch
WO2001040960A1 (en) 1999-11-30 2001-06-07 3Com Corporation Fifo-based network interface supporting out-of-order processing
US5802258A (en) * 1996-05-03 1998-09-01 International Business Machines Corporation Loosely coupled system environment designed to handle a non-disruptive host connection switch after detection of an error condition or during a host outage or failure
2001-03-09 US US09/802,426 patent/US7042898B2/en active Active
"Toshiba Delivers First Chips to Make Consumer Devices Internet-Ready Based on iReady Design," Press Release Oct. 14, 1998. 3 pages, (printed Nov. 28, 1998).
"Toshiba Delivers First Chips to Make Consumer Devices Internet-Ready Based On iReady's Design," Press Release Oct. 1988. 3 pages, downloaded Nov. 28, 1998.
"Two-Way TCP Traffic over Rate Controlled Channels: Effects and Analysis", IEEE Transactions on Networking, vol. 6, No. 6, pp. 729-743 (Dec. 1998).
Adaptec article, "EtherStorage Frequently Asked Questions," 5 pages, printed Jul. 19, 2000.
Adaptec article, "EtherStorage White Paper," 7 pages, printed Jul. 19, 2000.
Adaptec Press Release, "Adaptec Announces EtherStorage Technology", 2 pages, May 4, 2000, printed Jun. 14, 2000.
Andrew S. Tanenbaum, Computer Networks, Third Edition, 1996, ISBN 0-13-349945-6. (entire book).
Article by D. Hitz, et al., "File System Design For An NFS File Server Appliance", 13 pages, 1996.
Article by S. Taylor entitled "Montreal start-up battles data storage bottleneck," dated Mar. 7, 2000.
CIBC World Markets article by J. Berlino et al., "Computers; Storage", 9 pages, dated Aug. 7, 2000.
David Lammers, EETimes, Jun. 13, 1997, Tuner for Toshiba, Toshiba taps iReady for Internet tuner. 3 pages, printed Nov. 2, 1998.
EETIMES article entitled: Enterprise system uses flexible spec, by Christopher Harrer and Pauline Shulman, dated Aug. 10, 1998, Issue 1020. 3 pages, printed Nov. 25, 1998.
Gigabit Ethernet Technical Brief, Achieving End-to End Performance. Alteon Networks, Inc., First Edition, Sep. 1996.
Internet pages directed to; Technical Brief on Alteon Ethernet Gigabit NIC technology, www.alteon.com, 14 pages, printed Mar. 15, 1997.
Internet pages entitled : Hardware Assisted Protocol Processing (which Eugene Feinberg is working on). 1 page, printed Nov. 25, 1998.
Internet pages entitled: Comparison of Novell Netware and TCP/IP Protocol Architectures, by Janique S. Carbone, 19 pages, Jul. 16, 1995, downloaded and printed Apr. 10, 1998.
Internet pages entitled: DART Fast Application-Level Networking Via Data-Copy Avoidance, by Robert J. Walsh, 25 pages. Printed Jun. 3, 1999.
Internet pages entitled: iReady About Us and iReady Products. 5 pages, printed Nov. 25, 1998.
Internet pages entitled: Northridge/Southridge vs. Intel Hub Architecture, 4 pages, printed Feb. 19, 2001.
Internet pages entitled: Smart Ethernet Network Interface Card (which Berend Ozceri is developing). 2 pages, printed Nov. 25, 1998.
Internet pages from IReady News Archives entitled, "iReady Rounding Out management team with two key executives," 2 pages, downloaded Nov. 28, 1998.
Internet pages from iReady Products, web site http://www.ireadyco.com/products.html, 2 pages, downloaded Nov. 25, 1998.
Internet pages from website http://www.ireadyco.com/about.html, 3 pages, downloaded Nov. 2, 1998.
Internet pages of InterProphet entitled: Frequently Asked Questions, by Lynne Jolitz, 4 pages. Printed Jun. 14, 1999.
Internet pages of XaQti Corporation entitled: Giga POWER Protocol Processor Product Preview. 4 pages, printed Nov. 25, 1998.
Internet pages of Xpoint Technologies www.xpoint.com website, 5 pages, printed Dec. 19, 1997.
Internet web pages from "Adaptec.com" website directed to the Adaptec, AEA-7110C iSCSI Host Bus Adapter and about Adaptec's IP storage activities, 11 pages, downloaded and printed Oct. 1, 2001.
Internet web pages from "iSCSIhba.com" website directed to JNI iSCSI HBAs including the "FCE-3210/6410", 10 pages, downloaded and printed Oct. 1, 2001.
Internet web pages from the "iSCSI Storage.com" website that mention an Emulex HBA, 2 pages, downloaded and printed Oct. 1, 2001.
Internet web pages from the "iSCSIhba.com" website that mention QLogic HBAs including the "SANblade 2300 Series", 8 pages, downloaded and printed Oct. 1, 2001.
Internet-draft of J. Satran, et al., "SCSI/TCP (SCSI over TCP)", 38 pages, dated Feb. 2000.
Interprophet website, http://www.interprophet.com/technology.html, 17 pages, downloaded Mar. 1, 2000.
iReady Corporation, The i-1000 Internet Tuner, Modular Internet Design System, 2 pages, date unknown.
IReady News Archive, "Revolutionary Approach to Consumer Electronics Internet Connectivity Funded," San Jose, CA Nov. 20, 1997. 2 pages, printed Nov. 2, 1998.
IReady News Archive, "Seiko Instruments Inc. (SII) Introduces World's First Internet- Ready Intelligent LCD Modules Based on IReady Technology," Santa Clara, CA and Chiba, Japan, Oct. 26, 1998. 2 pages, printed Nov. 2, 1998.
IReady News Archives, "Toshiba, iReady shipping Internet chip," 1 page, posted at 9:39 AM PT, Oct. 14, 1998.
Jato Technologies Internet pages entitled: Network Accelerator Chip Architecture (twelve-slide presentation), 13 pages, printed Aug. 19, 1998.
Merrill Lynch article by S. Milunovich, "Storage Futures", 22 pages, dated May 10, 2000.
NEWSwatch-IReady Internet Tuner to Web Enable Devices, Nov. 15, 1996. 2 pages, printed Nov. 2, 1998.
Ross et al. "FX1000: A High Performance Single Chip Gigabit Ethernet NIC". IEEE Feb. 23-26, 1997. pp. 218-223. *
U.S. Appl. No. 08/964,304, Napolitano, et al.
U.S. Appl. No. 60/053,240, by Jolitz et al. filed Jul. 18, 1997.
VT8501 Apollo MVP4 Documentation, VIA Technologies, Inc., pp. i-iv, 1-11, cover and copyright page, revision 1.3 (Feb. 1, 2000).
Zilog Product Brief entitled "Z85C30 CMOS SCC Serial Communication Controller", Zilog Inc., 3 pages (1997).
US9923987B2 (en) 2000-04-17 2018-03-20 Circadence Corporation Optimization of enhanced network links
US10329410B2 (en) 2000-04-17 2019-06-25 Circadence Corporation System and devices facilitating dynamic network link acceleration
US10154115B2 (en) 2000-04-17 2018-12-11 Circadence Corporation System and method for implementing application functionality within a network infrastructure
US10205795B2 (en) 2000-04-17 2019-02-12 Circadence Corporation Optimization of enhanced network links
US7924868B1 (en) 2002-12-13 2011-04-12 Nvidia Corporation Internet protocol (IP) router residing in a processor chipset
US20010036196A1 (en) 2001-11-01
EP0772130B1 (en) 2002-08-14 Method and apparatus for transmission and processing of virtual commands
US20050097401A1 (en) 2005-05-05 Microcomputer, electronic equipment and debugging system
US6725319B2 (en) 2004-04-20 Memory device interface memory translator hub
US7047335B2 (en) 2006-05-16 Method for receiving user defined frame information structure (FIS) types in a serial-ATA (SATA) system
CN100493096C (en) 2009-05-27 Interface apparatus
JP2862177B2 (en) 1999-02-24 Control method of Ic card and ic card
EP0654742A2 (en) 1995-05-24 Multiple bus interface
KR100854946B1 (en) 2008-08-29 Arbitration system having a packet memory and method for memory responses in a hub-based memory system
CN1172247C (en) 2004-10-20 Storage controlling apparatus and tis controllong method
CN1214396C (en) 2005-08-10 Semiconductor storage having data masking pin and storage system including the same
DE19852986B4 (en) 2011-02-03 Circuit arrangement and method for data masking
US7043568B1 (en) 2006-05-09 Configuration selection for USB device controller
JP3165022B2 (en) 2001-05-14 Computer systems and message transfer method
US20010021949A1 (en) 2001-09-13 Network interface device employing a DMA command queue
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BLIGHTMAN, STEPHEN E. J.;BOUCHER, LAURNCE B.;CRAFT, PETER K.;AND OTHERS;REEL/FRAME:011908/0107;SIGNING DATES FROM 20010514 TO 20010607