Source: http://www.google.com/patents/US8134197?dq=6,411,947
Timestamp: 2014-03-10 17:58:56
Document Index: 288095110

Matched Legal Cases: ['Application No. 200780011084', 'Application No. 200780011164', 'Art. 94', 'Art. 94', 'Art. 94', 'Art. 94']

Patent US8134197 - Nanowire transistor with surrounding gate - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsOne aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor...http://www.google.com/patents/US8134197?utm_source=gb-gplus-sharePatent US8134197 - Nanowire transistor with surrounding gateAdvanced Patent SearchPublication numberUS8134197 B2Publication typeGrantApplication numberUS 12/192,618Publication dateMar 13, 2012Filing dateAug 15, 2008Priority dateApr 4, 2006Also published asCN101410961A, CN101410961B, CN101410963A, CN101410963B, CN101416288A, CN101416317A, CN101416317B, US7425491, US8062949, US20070232007, US20080315279, US20100330759, US20120168855Publication number12192618, 192618, US 8134197 B2, US 8134197B2, US-B2-8134197, US8134197 B2, US8134197B2InventorsLeonard ForbesOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (92), Non-Patent Citations (51), Classifications (18), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetNanowire transistor with surrounding gateUS 8134197 B2Abstract One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
What is claimed is: 1. A transistor array comprising a plurality of transistors arranged in rows and columns, wherein a lithographic process is used to fabricate features used to form the transistors in the array, and wherein the lithographic process is constrained by a minimum feature size, each transistor in the transistor array comprising:
a crystalline substrate;
a first source/drain region formed in the crystalline substrate;
a crystalline semiconductor pillar formed on the substrate in contact with the first source/drain region, the semiconductor pillar having cross-section dimensions less than the minimum feature size;
a second source/drain region formed in a top portion of the pillar;
a gate insulator formed around the pillar; and
a surrounding gate formed around and separated from the pillar by the gate insulator.
2. The transistor array of claim 1, wherein the semiconductor pillar has a cross-section dimension on the order of one third of the minimum feature size.
3. The transistor array of claim 1, wherein the semiconductor pillar has a cross-section dimension on the order of 30 nm.
4. The transistor array of claim 1, wherein the gate insulator includes silicon oxide.
5. The transistor array of claim 1, wherein the gate includes a polysilicon gate.
6. The transistor array of claim 1, wherein the gate includes a metal gate.
7. The transistor array of claim 1, wherein the crystalline semiconductor pillar has a height to provide a channel length on the order of 100 nm between the first and second source/drain regions.
8. The transistor array of claim 1, further comprising a gate contact to a word line adjacent to the gate, and a source/drain contact on the semiconductor pillar in contact with the second/source drain region.
9. The transistor array of claim 1, wherein the gate insulator includes an insulator material between the surrounding gate and the pillar, and wherein the insulator material is also between the gate and the crystalline substrate.
10. The transistor array of claim 9, wherein the insulator material includes an insulator formed by a thermal oxidation process on the crystalline substrate and the crystalline semiconductor material.
11. The transistor array of claim 1, wherein array has a center-to-center spacing between adjacent rows and between adjacent columns of twice the minimum feature size (2F).
12. A transistor array comprising a plurality of transistors arranged in rows and columns, wherein a lithographic process is used to fabricate features used to form the transistors in the array and wherein the lithographic process is constrained by a minimum feature size, each transistor in the transistor array comprising:
a first source/drain region formed in the crystalline silicon substrate;
a crystalline silicon pillar formed on the substrate in contact with the first source/drain region, the silicon pillar having cross-section dimensions less than a minimum feature size;
a gate insulator formed around the pillar;
a surrounding gate formed around and separated from the pillar by the gate insulator; and
a gate contact positioned adjacent to and in contact with the surrounding gate, the surrounding gate and the gate contact being etched to have a top surface below a top surface of the pillar.
13. The transistor array of claim 12, wherein the semiconductor pillar has a cross-section dimension on the order of one third of the minimum feature size.
14. The transistor array of claim 12, wherein the semiconductor pillar has a cross-section dimension on the order of 30 nm.
15. A memory device comprising a memory array, wherein the memory array includes the transistor array of claim 12.
16. A memory device comprising control circuitry, wherein the control circuitry of the memory device includes the transistor array of claim 12.
17. The transistor array of claim 12, wherein the crystalline silicon pillar has a cross-section dimension on the order of one third of the minimum feature size.
18. The transistor array of claim 12, wherein the crystalline silicon pillar has a height to provide a channel length on the order of 100 nm between the first and second source/drain regions.
19. The transistor array of claim 12, wherein array has a center-to-center spacing between adjacent rows and between adjacent columns of twice the minimum feature size (2F).
20. A transistor array comprising a plurality of transistors arranged in rows and columns, wherein a lithographic process is used to fabricate features used to form the transistors in the array, and wherein the lithographic process is constrained by a minimum feature size, each transistor in the transistor array comprising:
at least one gate line positioned adjacent to and in contact with the surrounding gate, the surrounding gate and the gate line being etched to have a top surface below a top surface of the pillar.
21. The transistor array of claim 20, wherein the at least one gate line includes first and second gate lines adjacent to and in contact with the surrounding gate on opposing sides of the pillar.
22. The transistor array of claim 20, comprising a drain line over the crystalline silicon pillar; and a doped region functioning as a source line within the crystalline silicon substrate beneath the crystalline silicon pillar.
23. The transistor array of claim 20, wherein array has a center-to-center spacing between adjacent rows and between adjacent columns of twice the minimum feature size (2F).
24. A semiconductor structure, wherein a lithographic process is used to fabricate features used to form the structure and wherein the lithographic process is constrained by a minimum feature size, the structure comprising:
a crystalline substrate; and
a semiconductor pillar formed on the substrate in contact with the first source/drain region, the semiconductor pillar having cross-section dimensions less than the minimum feature size, the semiconductor pillar having a crystallized bottom portion and an amorphous top portion indicative of a partially-completed solid phase epitaxy (SPE) process.
25. The structure of claim 24, further comprising a silicon nitride layer on the substrate, the silicon nitride layer being separated from the pillar by a void.
26. The structure of claim 25, wherein the silicon nitride layer includes islands of silicon nitride, each island having a width corresponding to a minimum feature size and separated from another island by the minimum feature size. Description
CROSS REFERENCE TO RELATED APPLICATIONS This application is a Divisional of U.S. application Ser. No. 11/397,527, filed Apr. 4, 2006 now U.S. Pat. No. 7,425,491, which is incorporated herein by reference in its entirety.
This application is related to the following commonly assigned U.S. patent applications which are filed on even date herewith and are herein incorporated by reference in their entirety: �Grown Nanofin Transistors,� U.S. application Ser. No. 11/397,430, filed on Apr. 4, 2006; �Etched Nanofin Transistors,� U.S. application Ser. No. 11/397,358, filed on Apr. 4, 2006; �DRAM With Nanofin Transistors,� U.S. application Ser. No. 11/397,413, filed on Apr. 4, 2006; and �Tunneling Transistor With Sublithographic Channel,� U.S. application Ser. No. 11/397,406, filed on Apr. 4, 2006.
TECHNICAL FIELD This disclosure relates generally to semiconductor devices, and more particularly, to nanowire transistors that have a surrounding gate.
FIG. 3 illustrates a dual-gated MOSFET with a drain, a source, and front and back gates separated from a semiconductor body by gate insulators, and also illustrates an electric field generated by the drain. Some characteristics of the dual-gated and/or double-gated MOSFET are better than the conventional bulk silicon MOSFETs, because compared to a single gate the two gates better screen the electric field generated by the drain electrode from the source-end of the channel. The surrounding gate further screens the electric field generated by the drain electrode from the source. Thus, sub-threshold leakage current characteristics are improved, because the sub-threshold current is reduced more quickly as the gate voltage is reduced when the dual-gate and/or double gate MOSFET turns off. FIG. 4 generally illustrates the improved sub-threshold characteristics of dual gate, double-gate, or surrounding gate MOSFETs in comparison to the sub-threshold characteristics of conventional bulk silicon MOSFETs.
Advances have been made in the growth of II-V compound semiconductor nanowires and in the fabrication of III-V compound semiconductor nanowire transistors. The growth of the II-V compound semiconductor transistors is achieved by vapor-liquid-solid (VLS) epitaxial growth of vertical nanowires on gold dots. Silicon nanowire transistors have been previously described by vapor phase epitaxial growth through a hole or by solid phase epitaxial growth over a polysilicon DRAM capacitor plate to make a polycrystalline nanowire transistor.
SUMMARY An embodiment of the present subject matter provides nanowire transistors from amorphous semiconductor nanorods that are recrystallized on the surface of a semiconductor wafer. The silicon nanorods are formed with dimensions smaller than lithographic dimensions by a sidewall spacer technique. The recrystallization of the amorphous nanorods uses solid phase epitaxial growth. The resulting nanowires can be used as the body regions of transistors where both the thickness of the body of the transistor and channel length have dimensions smaller than lithographic dimensions. The nanowire transistors have a wraparound gate. Various nanowire transistor embodiments use silicon nanowires.
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator.
An aspect relates to a transistor. A transistor embodiment includes a crystalline substrate, a first source/drain region formed in the crystalline substrate, and a crystalline semiconductor pillar formed on the substrate in contact with the first source/drain region. The transistor includes a second source/drain region formed in a top portion of the pillar, a gate insulator formed around the pillar, and a surrounding gate formed around and separated from the pillar by the gate insulator. The pillar has cross-section dimensions less than a minimum feature size.
FIG. 4 generally illustrates the improved sub-threshold characteristics of dual gate, double-gate, or surrounding gate MOSFETs in comparison to the sub-threshold characteristics of conventional bulk silicon MOSFETs.
FIGS. 5A-5H illustrate an embodiment of a process to form crystalline nanorods with surrounding gates.
FIGS. 6A-6C illustrate an embodiment of a process to form isolated transistors with source, drain and gate contacts, using the nanorods with wraparound gates illustrated in FIGS. 5A-5H.
FIGS. 7A-7C illustrate an embodiment of a process to form an array of transistors, using the nanorods with wraparound gates illustrated in FIGS. 5A-5H.
FIG. 8 illustrates a flow diagram for forming a nanowire transistor with surrounding gates, according to various embodiments of the present subject matter.
FIG. 9 is a simplified block diagram of a high-level organization of various embodiments of a memory device according to various embodiments of the present subject matter.
FIG. 10 illustrates a diagram for an electronic system having nanowire transistors, according to various embodiments.
FIG. 11 depicts a diagram of an embodiment of a system having a controller and a memory.
The following discussion refers to silicon nanowire transistor embodiments. Those of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to use the teaching contained herein to form nanowire transistors using other semiconductors.
FIGS. 5A-5H illustrate an embodiment of a process to form crystalline nanorods with surrounding gates. FIG. 5A illustrates a first layer 503 on a substrate 504, with holes 505 formed in the first layer. The first layer is able to be etched to define the holes within the layer. According to various embodiments, the holes 505 are formed in a silicon nitride layer 503 on a silicon substrate 504, such that the holes extend through the silicon nitride layer to the silicon substrate. In the illustrated embodiment, the holes are formed with dimensions corresponding to the minimum feature size. The center of each hole corresponds to the desired location of the nanowire transistor. An array of nanowire transistors can have a center-to-center spacing between rows and columns of 2F.
A layer of oxide is provided to cover the first layer after the holes have been etched therein. Various embodiments form a silicon oxide over the silicon nitride layer. Some embodiments deposit the silicon oxide by a chemical vapor deposition (CVD) process.
FIG. 5B illustrates the structure after the oxide is directionally etched to leave oxide sidewalls 506 on the sides of the hole, which function to reduce the dimensions of the resulting hole, and the resulting structure is planarized. In 100 nm technology, for example, the oxide sidewalls reduce the dimensions of the hole to about 30 nm. In this example, the thickness of the body region for the transistor will be on the order of ⅓ of the feature size. Some embodiments planarize the structure using a chemical mechanical polishing (CMP) process.
FIG. 5C illustrates a thick layer of an amorphous semiconductor material 507 formed over the resulting structure. The amorphous material fills the hole defined by the sidewalls 506. Various embodiments deposit amorphous silicon as the amorphous material. FIG. 5D illustrates the resulting structure after it is planarized, such as by CMP, to leave amorphous semiconductor material only in the holes.
FIG. 5E illustrates the resulting structure after the sidewalls (e.g. silicon oxide sidewalls) are removed. The structure is heat treated to crystallize the amorphous semiconductor 507 (e.g. a-silicon) into crystalline nanorods (represented as 507-C) using a process known as solid phase epitaxy (SPE). The amorphous semiconductor pillar 507 is in contact with the semiconductor wafer (e.g. silicon wafer), and crystal growth in the amorphous semiconductor pillar is seeded by the crystals in the wafer. The crystal formation from the SPE process is illustrated by the arrows 508 in FIG. 5E.
FIG. 5F illustrates the structure after the first layer (e.g. silicon nitride) is removed, leaving crystalline nanorods 507-C extending away from the substrate surface, and after a gate insulator 509 is formed over the resulting structure. An embodiment forms the gate insulator by a thermal oxidation process. Thus, for an embodiment in which the wafer is a silicon wafer and the nanorods are crystalline silicon nanorods, the gate insulator is a silicon oxide. Other gate insulators, such as high K insulators, may be used.
FIG. 5G illustrates a side view and FIG. 5H illustrates a cross-section view along 5H-5H of FIG. 5G view of the structure after a gate material 510 is formed on the sidewalls of the crystalline nanorods 507-C. An embodiment deposits the gate material and etches the resulting structure to leave the gate material only on the sidewalls of the nanorods. Polysilicon is used as the gate material, according to various embodiments. The height of the pillars, which determines the channel length of the transistors, can be less than the minimum lithographic dimensions. Various embodiments provide a channel length on the order of approximately 100 nm. These nanorods with wraparound gates can be used to form nanowire transistors with surrounding or wraparound gates. The process continues in FIGS. 6A-6C for some embodiments of standalone transistors, and continued in FIGS. 7A-7C for some embodiments of transistor arrays.
FIGS. 6A-6C illustrate an embodiment of a process to form isolated transistors with source, drain and gate contacts, using the nanorods with wraparound gates illustrated in FIGS. 5A-5H. The illustrated structure includes a crystalline nanorod 607-C, a gate insulator 609, and a surrounding gate 610. Gate contacts 611 for the wraparound gates are patterned. Various embodiments deposit polysilicon to function as gate contacts for the wraparound gates. Both the wraparound gate and the gate contact, also referred to as a gate pad, are recessed below the top of the nanowire. A directional etching process may be used to recess the wraparound gate and the gate pad. As illustrated in FIG. 6B, the resulting structure is filled with an insulator fill (e.g. oxide) 612 and planarized to the top of the nanowires. The top of the nanowires are exposed by removing the gate insulator from the top of the nanowire. For example, an etch can be used to remove silicon oxide from the top of the nanowire. The top of the nanowires can be doped and contact areas defined. The doped top portion 613 of the nanowires can function as a drain region. The substrate is appropriately doped to diffuse under the crystalline nanorod, and extend up into a bottom portion of the nanorod. This doped region can function as a source region. This doped region 614 also extends to a contact area. The doped region can be formed before the first layer is deposited and holes formed therein. The dopant can also be implanted and diffused before the surrounding gate is formed. Appropriate doping can be provided to provide NMOS or PMOS transistors. As illustrated in FIG. 6C, a contact 615 can be etched to the buried source, a contact 616 can be etched to the buried gate pad, and a contact 617 can also be formed for the drain. Those of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that other stand alone transistor designs may be used.
FIGS. 7A-7C illustrate an embodiment of a process to form an array of transistors, using the nanorods with wraparound gates illustrated in FIGS. 5A-5H. FIG. 7A illustrates a top view of adjacent transistors in a row of an embodiment of a transistor array. According to the illustrated embodiment, one word line 719 is formed adjacent to one row of transistors, such that the wraparound gates 710 of each transistor 718 in the row are in contact with the adjacent word line. FIB. 7B illustrates a top view of adjacent transistors in a row of another embodiment of a transistor array. According to various embodiments, polysilicon or gate material can be used for the gate wiring, a buried doped region can form a source region 720 and the source wiring 721, and metal contacts 722 and metal used for the drain wiring 723. In some embodiments, the nanowire structure with only wraparound gates is then backfilled with oxide and patterned and etched to leave oxide 724 between the pillars in one direction and expose the wrap around gates on the side. Polysilicon can be deposited and directionally etched to leave only on the sidewalls of the oxide blocks and exposed gate sides. As described with respect to FIG. 6C, the wraparound gates can be further directionally etched to recess them below the top of the nanowire transistors. This will form the gate contacts and wiring. The structure can be planarized and backfilled with oxide and the top of the nanowires doped and contacted for the drain wiring using conventional techniques. Those of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that other transistor array designs may be used.
FIG. 8 illustrates a flow diagram for forming a nanowire transistor with surrounding gates, according to various embodiments of the present subject matter. At 825, holes are formed in a substrate. For example, the substrate can include a first layer on a wafer, such as a layer of silicon nitride on a silicon wafer, and the holes are formed in the first layer to expose the wafer. The holes are defined by walls formed by the first layer. At 826, spacer sidewalls are formed within the holes against the walls formed by the first layer to effectively reduce the dimensions of the holes. An example of a spacer sidewall is silicon oxide. At 827, the holes are filled by an amorphous semiconductor (e.g. a-silicon). The spacer sidewalls are removed at 828, leaving pillars of amorphous semiconductor extending away from the wafer. The resulting structure is heat-treated or annealed at 829 to recrystallize the amorphous semiconductor, using the wafer to seed the crystalline growth. The recrystallization process is referred to as solid phase epitaxy (SPE). The resulting structure includes crystalline nanowires extending away from the wafer. At 830, a surrounding gate insulator and a surrounding gate are formed around the crystalline nanowires. Source/drain regions are formed at 831. The bottom of the nanowire is doped to form a first source/drain region, and the top of the nanowire is doped to form a second source/drain region. The first source/drain region can be formed by doping the substrate before depositing the first layer and patterning and etching the holes. The first source/drain can also be formed by implanting dopants adjacent to the nanorod before the gate is formed. These implanted dopants are capable of diffusing completely under the nanorod because the nanorods are very thin. This doping can be performed after the first layer is removed off of the substrate.
FIG. 9 is a simplified block diagram of a high-level organization of various embodiments of a memory device according to various embodiments of the present subject matter. The illustrated memory device 932 includes a memory array 933 and read/write control circuitry 934 to perform operations on the memory array via communication line(s) or channel(s) 935. The illustrated memory device 932 may be a memory card or a memory module such as a single inline memory module (SIMM) and dual inline memory module (DIMM). One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that semiconductor components in the memory array and/or the control circuitry are able to be fabricated using the nanowire transistors with surrounding gates, as described above. The structure and fabrication methods for these devices have been described above.
The memory array 933 includes a number of memory cells 936. The memory cells in the array are arranged in rows and columns. In various embodiments, word lines 937 connect the memory cells in the rows, and bit lines 938 connect the memory cells in the columns. The read/write control circuitry 934 includes word line select circuitry 939 which functions to select a desired row, bit line select circuitry 940 which functions to select a desired column, and read circuitry 941 which functions to detect a memory state for a selected memory cell in the memory array 933.
FIG. 10 illustrates a diagram for an electronic system 1042 having one or more nanowire transistors with surrounding gates, according to various embodiments. The electronic system includes a controller 1043, a bus 1044, and an electronic device 1045, where the bus provides communication channels between the controller and the electronic device. In various embodiments, the controller and/or electronic device include nanowire transistors as previously discussed herein. The illustrated electronic system may include, but is not limited to, information handling devices, wireless systems, telecommunication systems, fiber optic systems, electro-optic systems, and computers.
FIG. 11 depicts a diagram of an embodiment of a system 1146 having a controller 1147 and a memory 1148. The controller and/or memory may include nanowire transistors. The illustrated system also includes an electronic apparatus 1149 and a bus 1150 to provide communication channel(s) between the controller and the electronic apparatus, and between the controller and the memory. The bus may include an address, a data bus, and a control bus, each independently configured; or may use common communication channels to provide address, data, and/or control, the use of which is regulated by the controller. In an embodiment, the electronic apparatus 1149 may be additional memory configured similar to memory 1148. An embodiment may include a peripheral device or devices 1151 coupled to the bus. Peripheral devices may include displays, additional storage memory, or other control devices that may operate in conjunction with the controller and/or the memory. In an embodiment, the controller is a processor. Any of the controller, the memory, the electronic apparatus, and the peripheral devices may include nanowire transistors. The system may include, but is not limited to, information handling devices, telecommunication systems, and computers. Applications containing nanowire transistors as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others.
The memory may be realized as a memory device containing nanowire transistors according to various embodiments. It will be understood that embodiments are equally applicable to any size and type of memory circuit and are not intended to be limited to a particular type of memory device. Memory types include a DRAM, SRAM (Static Random Access Memory) or Flash memories. Additionally, the DRAM could be a synchronous DRAM commonly referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM). Various emerging memory technologies are capable of using nanowire transistors.
This disclosure includes several processes, circuit diagrams, and structures. The present subject matter is not limited to a particular process order or logical arrangement. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations or variations of the present subject matter. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon reviewing and understanding the above description. The scope of the present subject matter should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4941026Aug 26, 1988Jul 10, 1990General Electric CompanySemiconductor devices exhibiting minimum on-resistanceUS5013680Jul 18, 1990May 7, 1991Micron Technology, Inc.Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithographyUS5646900Jan 11, 1996Jul 8, 1997Mitsubishi Denki Kabushiki KaishaSense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory deviceUS5909618Jul 8, 1997Jun 1, 1999Micron Technology, Inc.Method of making memory cell with vertical transistor and buried word and body linesUS5982162 *Jan 9, 1997Nov 9, 1999Mitsubishi Denki Kabushiki KaishaInternal voltage generation circuit that down-converts external power supply voltage and semiconductor device generating internal power supply voltage on the basis of reference voltageUS6063688Sep 29, 1997May 16, 2000Intel CorporationFabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definitionUS6097065Mar 30, 1998Aug 1, 2000Micron Technology, Inc.Circuits and methods for dual-gated transistorsUS6104061Feb 27, 1998Aug 15, 2000Micron Technology, Inc.Memory cell with vertical transistor and buried word and body linesUS6104068Sep 1, 1998Aug 15, 2000Micron Technology, Inc.Structure and method for improved signal processingUS6150687Jul 8, 1997Nov 21, 2000Micron Technology, Inc.Memory cell having a vertical transistor with buried source/drain and dual gatesUS6177299Jan 15, 1998Jan 23, 2001International Business Machines CorporationTransistor having substantially isolated body and method of making the sameUS6191448Mar 7, 2000Feb 20, 2001Micron Technology, Inc.Memory cell with vertical transistor and buried word and body linesUS6238976 *Feb 27, 1998May 29, 2001Micron Technology, Inc.Method for forming high density flash memoryUS6320222Sep 1, 1998Nov 20, 2001Micron Technology, Inc.Structure and method for reducing threshold voltage variations due to dopant fluctuationsUS6350635Aug 24, 1998Feb 26, 2002Micron Technology, Inc.Memory cell having a vertical transistor with buried source/drain and dual gatesUS6355961Apr 28, 2000Mar 12, 2002Micron Technology, Inc.Structure and method for improved signal processingUS6376317Jun 28, 2000Apr 23, 2002Micron Technology, Inc.Methods for dual-gated transistorsUS6377070Feb 9, 2001Apr 23, 2002Micron Technology, Inc.In-service programmable logic arrays with ultra thin vertical body transistorsUS6399979Jun 16, 2000Jun 4, 2002Micron Technology, Inc.Memory cell having a vertical transistor with buried source/drain and dual gatesUS6413802Oct 23, 2000Jul 2, 2002The Regents Of The University Of CaliforniaFinfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufactureUS6413825Apr 28, 2000Jul 2, 2002Micron Technology, Inc.Method for signal processingUS6414356Jun 28, 2000Jul 2, 2002Micron Technology, Inc.Circuits and methods for dual-gated transistorsUS6424001Feb 9, 2001Jul 23, 2002Micron Technology, Inc.Flash memory with ultra thin vertical body transistorsUS6448601Feb 9, 2001Sep 10, 2002Micron Technology, Inc.Memory address and decode circuits with ultra thin body transistorsUS6492233Feb 20, 2001Dec 10, 2002Micron Technology, Inc.Memory cell with vertical transistor and buried word and body linesUS6496034Feb 9, 2001Dec 17, 2002Micron Technology, Inc.Programmable logic arrays with ultra thin body transistorsUS6504201Aug 30, 2000Jan 7, 2003Micron Technology, Inc.Memory cell having a vertical transistor with buried source/drain and dual gatesUS6531727Feb 9, 2001Mar 11, 2003Micron Technology, Inc.Open bit line DRAM with ultra thin body transistorsUS6559491Feb 9, 2001May 6, 2003Micron Technology, Inc.Folded bit line DRAM with ultra thin body transistorsUS6566682Feb 9, 2001May 20, 2003Micron Technology, Inc.Programmable memory address and decode circuits with ultra thin vertical body transistorsUS6639268May 20, 2002Oct 28, 2003Micron Technology, Inc.Flash memory with ultra thin vertical body transistorsUS6649476Feb 15, 2001Nov 18, 2003Micron Technology, Inc.Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate arrayUS6653174Dec 17, 2001Nov 25, 2003T-Ram, Inc.Thyristor-based device over substrate surfaceUS6664806Aug 29, 2002Dec 16, 2003Micron Technology, Inc.Memory address and decode circuits with ultra thin body transistorsUS6720216Aug 29, 2002Apr 13, 2004Micron Technology, Inc.Programmable memory address and decode circuits with vertical body transistorsUS6747313Oct 13, 2000Jun 8, 2004Hyundai Electronics Industries Co., Ltd.Thin film transistorUS6762448Apr 3, 2003Jul 13, 2004Advanced Micro Devices, Inc.FinFET device with multiple fin structuresUS6801056Oct 29, 2002Oct 5, 2004Micron Technology, Inc.Monotonic dynamic-static pseudo-NMOS logic circuitUS6818937Jun 4, 2002Nov 16, 2004Micron Technology, Inc.Memory cell having a vertical transistor with buried source/drain and dual gatesUS6855582Jun 12, 2003Feb 15, 2005Advanced Micro Devices, Inc.FinFET gate formation using reverse trim and oxide polishUS6881627Aug 28, 2002Apr 19, 2005Micron Technology, Inc.Flash memory with ultra thin vertical body transistorsUS6890812Dec 11, 2002May 10, 2005Micron Technology Inc.Method of forming a memory having a vertical transistorUS6894532Dec 17, 2002May 17, 2005Micron Technology, Inc.Programmable logic arrays with ultra thin body transistorsUS6903367Aug 8, 2003Jun 7, 2005Micron Technology Inc.Programmable memory address and decode circuits with vertical body transistorsUS6946879Feb 13, 2003Sep 20, 2005Micron Technology, Inc.Logic array and dynamic logic methodUS6964903Jan 25, 2002Nov 15, 2005Micron Technology, Inc.Method of fabricating a transistor on a substrate to operate as a fully depleted structureUS7120046May 13, 2005Oct 10, 2006Micron Technology, Inc.Memory array with surrounding gate access transistors and capacitors with global and staggered local bit linesUS7326611Feb 3, 2005Feb 5, 2008Micron Technology, Inc.DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arraysUS7371627May 13, 2005May 13, 2008Micron Technology, Inc.Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit linesUS7425491Apr 4, 2006Sep 16, 2008Micron Technology, Inc.Nanowire transistor with surrounding gateUS7439576Aug 29, 2005Oct 21, 2008Micron Technology, Inc.Ultra-thin body vertical tunneling transistorUS7446372Sep 1, 2005Nov 4, 2008Micron Technology, Inc.DRAM tunneling access transistorUS7491995Apr 4, 2006Feb 17, 2009Micron Technology, Inc.DRAM with nanofin transistorsUS20020028541Aug 13, 2001Mar 7, 2002Lee Thomas H.Dense arrays and charge storage devices, and methods for making sameUS20020060338Nov 6, 2001May 23, 2002Zhibo ZhangMethods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls and vertical field effect transistors fabricated therebyUS20020177265Apr 2, 2002Nov 28, 2002Stmicroelectronics S.A.Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistorUS20030006410Mar 1, 2000Jan 9, 2003Brian DoyleQuantum wire gate device and method of making sameUS20030008515Jul 3, 2001Jan 9, 2003Tai-Ju ChenMethod of fabricating a vertical MOS transistorUS20030227072Jun 10, 2002Dec 11, 2003Leonard ForbesOutput prediction logic circuits with ultra-thin vertical transistors and methods of formationUS20040007721May 5, 2003Jan 15, 2004Micron Technology, Inc.Folded bit line DRAM with vertical ultra thin body transistorsUS20040108545Dec 4, 2002Jun 10, 2004Yoshiyuki AndoIon implantation methods and transistor cell layout for fin type transistorsUS20040174734Mar 4, 2003Sep 9, 2004Micron Technology, Inc.Vertical gain cellUS20040217391Apr 29, 2003Nov 4, 2004Micron Technology, Inc.Localized strained semiconductor on insulatorUS20040219722May 1, 2003Nov 4, 2004Pham Daniel T.Method for forming a double-gated semiconductor deviceUS20040235243Jun 29, 2004Nov 25, 2004Micron Technology, Inc.Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitorUS20050023616Aug 31, 2004Feb 3, 2005Micron Technology, Inc.Localized strained semiconductor on insulatorUS20050032297 *Sep 9, 2004Feb 10, 2005Kamins Theodore I.Field effect transistor fabrication including formation of a channel in a poreUS20050190617Jan 18, 2005Sep 1, 2005Micron Technology, Inc.Folded bit line DRAM with vertical ultra thin body transistorsUS20060043471Aug 26, 2004Mar 2, 2006Tang Sanh DVertical transistor structures having vertical-surrounding-gates with self-aligned featuresUS20060046200Sep 1, 2004Mar 2, 2006Abatchev Mirzafer KMask material conversionUS20060046391Aug 30, 2004Mar 2, 2006Tang Sanh DVertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory arrayUS20060046424Aug 24, 2004Mar 2, 2006Chance Randal WMethods of forming semiconductor constructionsUS20060063350Nov 14, 2005Mar 23, 2006Chance Randal WSemiconductor constructionsUS20060076625Jan 12, 2005Apr 13, 2006Lee Sung-YoungField effect transistors having a strained silicon channel and methods of fabricating sameUS20060258119Jul 21, 2006Nov 16, 2006Wells David HMemory array buried digit lineUS20060278910Jun 13, 2005Dec 14, 2006Leonard ForbesVertical transistor, memory cell, device, system and method of forming sameUS20070018206Jul 6, 2005Jan 25, 2007Leonard ForbesSurround gate access transistors with grown ultra-thin bodiesUS20070052012Aug 24, 2005Mar 8, 2007Micron Technology, Inc.Vertical tunneling nano-wire transistorUS20070082448Jun 30, 2006Apr 12, 2007Samsung Electronics Co., Ltd.Semiconductor devices having transistors with vertical channels and method of fabricating the sameUS20070228433Apr 4, 2006Oct 4, 2007Micron Technology, Inc.DRAM with nanofin transistorsUS20070228491Apr 4, 2006Oct 4, 2007Micron Technology, Inc.Tunneling transistor with sublithographic channelUS20070231980Apr 4, 2006Oct 4, 2007Micron Technology, Inc.Etched nanofin transistorsUS20070231985Apr 4, 2006Oct 4, 2007Micron Technology, Inc.Grown nanofin transistorsUS20070232007Apr 4, 2006Oct 4, 2007Micron Technology, Inc.Nanowire transistor with surrounding gateUS20080315279Aug 15, 2008Dec 25, 2008Micron Technology, Inc.Nanowire transistor with surrounding gateUS20100330759Aug 26, 2008Dec 30, 2010Micron Technology, Inc.Nanowire transistor with surrounding gateDE19943390A1Sep 10, 1999May 3, 2001Walter HanschSemiconductor component comprises vertical stack comprising source, drain and intermediate layer, gate comprising insulating and conducting layer connecting source and drain and tunnel current flowing in section of gateWO2005079182A2Jan 22, 2004Sep 1, 2005Jochen BeintnerVertical fin-fet mos devicesWO2007114927A1Apr 3, 2007Oct 11, 2007Micron Technology IncEtched nanofin transistorsWO2007120492A1Apr 3, 2007Oct 25, 2007Micron Technology IncNanowire transistor with surrounding gateWO2007120493A1Apr 3, 2007Oct 25, 2007Micron Technology IncNanofin tunneling transistorsWO2007136461A2Apr 3, 2007Nov 29, 2007Micron Technology IncGrown nanofin transistors* Cited by examinerNon-Patent CitationsReference1"Chinese Application No. 200780011084.7, Amendment filed Jan. 16, 2011", (with English translation of amended claims), 13 pgs.2"Chinese Application No. 200780011164.2, Office Action issued Oct. 23, 2009 and received Nov. 26, 2009", 5 pgs.3"Chinese Application Serial No. 200780011084.7, Office Action mailed Sep. 26, 2010", 5 pgs.4"Chinese Application Serial No. 200780011164.2, Amendment filed Jan. 17, 2010", (with English translation of amended claims), 16 pgs.5"Chinese Application Serial No. 200780011164.2, Office Action mailed Mar. 10, 2010", 8 pgs.6"Chinese Application Serial No. 200780012174.8, Office Action mailed Dec. 3, 2010", with English translation, 5 pgs.7"Chinese Application Serial No. 200780012174.8, Office Action mailed Mar. 30, 2011", 4 pgs.8"Chinese Application Serial No. 200780012174.8, Office Action response filed Jan. 28, 2011", (with English translation of amended claims), 12 pgs.9"Chinese Application Serial No. 200780012174.8, Response filed Feb. 10, 2011", (with English translation of amended claims), 13 pgs.10"European Application Serial No. 07754621.6, Examination Notification Art. 94(3) mailed Feb. 4, 2011", 5 Pgs.11"European Application Serial No. 07754621.6, Response filed May 16, 2011 to Examination Notification Art. 94(3) mailed Feb. 4, 2011", 7 pgs.12"European Application Serial No. 07754850.1, Office Action mailed Jun. 9, 2011", 5.13"European Application Serial No. 07754850.1, Office Action Mailed May 25, 2010", 6 pgs.14"European Application Serial No. 07754850.1, Office Action Response mailed Nov. 17, 2010", 19 pgs.15"European Application Serial No. 07809002.4, Examination Notification Art. 94(3) mailed Feb. 4, 2011", 5 pgs.16"European Application Serial No. 07809002.4, Response filed May 23, 2011 to Examination Notification Art. 94(3) mailed Feb. 4, 2011", 11 pgs.17"Japanese Application Serial No. 2009-504232, Amendment filed Mar. 31, 2010", (with English translation of amended claims), 16 pgs.18"Japanese Application Serial No. 2009-504238, Voluntary Amendment filed Mar. 24, 2010", (with English translation of amended claims), 17 pgs.19"Japanese Application Serial No. 2009-504280, Amendment filed Mar. 31, 2010", with English translation, 15 pgs.20"Taiwan Application Serial No. 096112121, Office Action mailed Dec. 24, 2010", English translation, 7 pgs.21"Taiwan Application Serial No. 96112122, Notice of Allowance Mar. 8, 2011", 2 pgs.22"Taiwan Application Serial No. 96112122, Office Action mailed Sep. 17, 2010", 6 pgs.23"Taiwan Application Serial No. 96112122, Office Action Response filed Jan. 6, 2011", with English translation of claims and abstract, 36 pgs.24"Taiwan Application Serial No. 96112124, Notice of Allowance mailed Jul. 13, 2011", 2.25"Taiwan Application Serial No. 96112125, Office Action mailed Dec. 2, 2010", with English translation of claims, 15 pgs.26"Taiwanese Application Serial No. 096112121, Office Action mailed Apr. 7, 2011", Notification letter, 2 pgs.27"Taiwanese Application Serial No. 96112125, Response filed Jun. 6, 2011 to Office Action mailed Dec. 2, 2010", 33 pgs.28Adler, E., et al., "The Evolution of IBM CMOS DRAM Technology", IBM Journal of Research & Development, 39(1-2), (Jan.-Mar. 1995), 167-188.29Bryllert, Tomas, et al., "Vertical high mobility wrap-gated InAs nanowire transistor", IEEE Device Research Conference, Santa Barbara, CA, (Jun. 2005), 157-158.30Cho, Hyun-Jin, et al., "A Novel Pillar DRAM Cell for 4Gbit and Beyond", 1998 Symposium on VLSI Technology Digest of Technical Papers, Jun. 9-11, 1998, 38-39.31Denton, Jack P., et al., "Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate", IEEE Electron Device Letters, 17(11), (Nov. 1996), 509-511.32Doyle, B. S., et al., "High performance fully-depleted tri-gate CMOS transistors", IEEE Electron Device Letters, vol. 24, No. 4, (Apr. 2003), 263-265.33Doyle, B. S., et al., "Tri-Gate fully-depleted CMIS transistors: fabrication, design and layout", 2003 Symposium on VLSI Technology Digest of Technical Papers, Kyoto, Japan, Jun. 10-12, 2003, 133-134.34 *Excimer laserr annealing of amorphous and solid-phase-crystallized silicon films. Mitsutoshi et al. Journal of Applied Physics vol. 86, No. 10. Nov. 15, 1999.35 *http://web.archive.org/web/20020211230307/http://britneyspears.ac/physics/fabrication/photolithography.htm, Feb. 11, 2002.36Huang, Xuejue, et al., "Sub-50 nm P-Channel FinFET", IEEE Transactions on Electron Devices, vol. 48, No. 5, (May 2001), 880-886.37Kalavade, Pranav, et al., "A novel sub-10 nm transistor", 58th DRC. Device Research Conference. Conference Digest, (Jun. 19-21, 2000), 71-72.38Kedzierski, Jakub, et al., "Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)", IEDM Tech. Dig., (2003), 315-318.39Kim, Keunwoo, et al., "Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device", International Symposium on Low Power Electronics and Design, Newport, CA, Aug. 9-11, 2004; http://www.islped.org, (2004), 102-107.40Lee, Choonsup, et al., "A Nanochannel Fabrication Technique without Nanolithography", Nano Letters, vol. 3, No. 10, (2003), 1339-1340.41Miyano, Shinji, et al., "Numerical Analysis of a Cylindrical Thin-Pillar Transistor (CYNTHIA)", IEEE Transactions on Electron Devices, vol. 39, No. 8, (Aug. 1992), 1876-1881.42Nirschl, TH., et al., "The Tunneling Field Effect Transistor (TFET) as an Add-on for Ultra-Low-Voltage Analog and DIgital Processes", IEEE International Electron Devices Meeting, 2004; IEDM Technical Digest, (Dec. 13-15, 2004), 195-198.43Rahman, Anisur, et al., "Theory of Ballistic Nanotransistors", IEEE Transactions on Electron Devices, vol. 50, No. 9, (Sep. 2003), 1853-1864.44Samuelson, L., et al., "Semiconductor nanowires for 0D and 1D physics and applications", Physica E 25, (Jul. 27, 2004), 313-318.45Samuelson, Lars, "Semiconductor Nanowires as a Novel Electronic Materials Technology for Future Electronic Devices", IEEE Device Research Conference, Santa Barbara, CA, (Jun. 2005), 245.46Shimomura, K., et al., "A 1V 46ns 16Mb SOI-DRAM with Body Control Technique", 1997 IEEE International Solid-State Circuits, 32(11), (Nov. 1997), 1712-1720.47Shimomura, K., et al., "A 1-V 46-ns 16-Mb SOI-DRAM with body control technique", IEEE Journal of Solid-State Circuits, 32(11), (Nov. 1997), 1712-1720.48Takato, H., et al., "High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs", IEEE International Electron Devices Meeting, Technical Digest, (1988), 222-225.49Wong, Hon-Sum Philip, et al., "Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel", IEEE Int. Electron Device Meeting, (1997), 427-430.50Xuan, Peiqi, et al., "60nm Planarized Ultra-thin Body Solid Phase Epitaxy MOSFETs", IEEE Device Research Conference, Conference Digest. 58th DRC, (Jun. 19-21, 2000), 67-68.51Ziegler, James F., et al., "Cosmic Ray Soft Error Rates of 16-Mb DRAM Memory Chips", IEEE Journal of Solid-State Circuits, vol. 33, No. 2, (Feb. 1998), 246-252.* Cited by examinerClassifications U.S. Classification257/314, 257/E29.2, 257/E29.001International ClassificationH01L21/331Cooperative ClassificationY10S977/70, Y10S977/762, H01L29/66666, H01L29/0673, H01L29/0665, H01L29/0676, H01L29/7827, B82Y10/00European ClassificationB82Y10/00, H01L29/06C6W2, H01L29/66M6T6F12, H01L29/06C6, H01L29/06C6W4, H01L29/78CLegal EventsDateCodeEventDescriptionMay 8, 2012CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google