Source: http://www.google.com/patents/US8190863?dq=5987118
Timestamp: 2013-12-20 05:52:09
Document Index: 596154647

Matched Legal Cases: ['Application No. 2007', 'Application No. 200580022604', 'Application No. 09414100', 'Application No. 2007', 'Application No. 200580022604', 'Application No. 200580022604']

Patent US8190863 - Apparatus and method for heterogeneous chip multiprocessors via resource ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes...http://www.google.com/patents/US8190863?utm_source=gb-gplus-sharePatent US8190863 - Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restrictionAdvanced Patent SearchPublication numberUS8190863 B2Publication typeGrantApplication numberUS 10/884,359Publication dateMay 29, 2012Filing dateJul 2, 2004Priority dateJul 2, 2004Also published asCN1981280A, CN100561461C, US20060005082, US20120239875, WO2006014254A1Publication number10884359, 884359, US 8190863 B2, US 8190863B2, US-B2-8190863, US8190863 B2, US8190863B2InventorsTryggve Fossum, George Chrysos, Todd A. DuttonOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (20), Non-Patent Citations (9), Referenced by (1), Classifications (29), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetApparatus and method for heterogeneous chip multiprocessors via resource allocation and restrictionUS 8190863 B2Abstract A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.
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No. 2007-519337 mailed Jun. 11, 2010, p. 1.2First Office Action from foreign counterpart China Patent Application No. 200580022604.5 mailed Feb. 15, 2008, pp. 16.3Foreign counterpart Patent Application No. 09414100, mailed Nov. 11, 2011, pp. 22.4Non-Final Notice of Reasons for Rejection for Japanese Application No. 2007-519337 mailed Jun. 30, 2009., 5 pgs.5Patent Grant from foreign counterpart China Patent Application No. 200580022604.5 mailed Jul. 17, 2009, pp. 2.6PCT International Search Report for foreign counterpart Patent Application No. PCT/US2005/022773 mailed Oct. 18, 2005, pp. 4.7PCT International Written Opinion for foreign counterpart Patent Application No. PCT/US2005/022773 mailed Oct. 18, 2005, pp. 5.8PCT, International Preliminary Report on Patentability for International Application No. PCT/US2005/022773, Jun. 25, 2005.9Second Office Action from foreign counterpart China Patent Application No. 200580022604.5 mailed Aug. 15, 2008, pp. 11.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS20110099397 *Dec 29, 2010Apr 28, 2011Efraim RotemOperating point management in multi-core architectures* Cited by examinerClassifications U.S. Classification712/229, 711/154, 713/300International ClassificationG06F1/00, G06F9/00, G06F7/38, G06F13/28, G06F9/44, G06F1/32, G06F15/76, G06F13/00Cooperative ClassificationG06F9/5094, G06F9/3869, G06F9/3836, G06F1/3203, G06F9/30181, G06F9/5061, Y02B60/1282, Y02B60/1278, G06F9/3802, G06F1/3287European ClassificationG06F9/50P, G06F9/38B, G06F9/38P2, G06F1/32P, G06F9/30X, G06F9/38E, G06F9/50C, G06F1/32P5SLegal EventsDateCodeEventDescriptionJul 4, 2004ASAssignmentOwner name: INTEL CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FOSSUM, TRYGGVE;CHRYSOS, GEORGE;DUTTON, TODD A.;REEL/FRAME:016791/0180Effective date: 20040702Jul 4, 2004XASNot any more in us assignment databaseFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FOSSUM, TRYGGVE;CHRYSOS, GEORGE;DUTTON, TODD A.;REEL/FRAME:015556/0637RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google