Source: http://www.google.com/patents/US7636257?dq=6,163,776
Timestamp: 2016-08-30 05:59:55
Document Index: 200865671

Matched Legal Cases: ['Application No. 60', 'art 2', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064']

Patent US7636257 - Methods of operating p-channel non-volatile memory devices - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsMethods of operating non-volatile memory devices are described. The memory devices comprise memory cells having an n-type semiconductor substrate and p-type source and drain regions disposed below a surface of the substrate and separated by a channel region. A tunneling dielectric layer is disposed above...http://www.google.com/patents/US7636257?utm_source=gb-gplus-sharePatent US7636257 - Methods of operating p-channel non-volatile memory devicesAdvanced Patent SearchPublication numberUS7636257 B2Publication typeGrantApplication numberUS 11/417,939Publication dateDec 22, 2009Filing dateMay 4, 2006Priority dateJun 10, 2005Fee statusPaidAlso published asCN1877857A, CN101964209A, CN101964209B, US7986556, US20060281260, US20100117139Publication number11417939, 417939, US 7636257 B2, US 7636257B2, US-B2-7636257, US7636257 B2, US7636257B2InventorsHang-Ting LueOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (71), Non-Patent Citations (39), Referenced by (16), Classifications (12), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetMethods of operating p-channel non-volatile memory devices
This application is based upon and claims the benefit of, under 35 U.S.C. � 119(e), U.S. Provisional Patent Application No. 60/689,767, filed on Jun. 10, 2005, the entire contents of which is incorporated herein by reference.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5286994Jun 23, 1992Feb 15, 1994Rohm Co., Ltd.Semiconductor memory trap film assembly having plural laminated gate insulating filmsUS5319229Apr 27, 1992Jun 7, 1994Noriyuki ShimojiSemiconductor nonvolatile memory with wide memory window and long data retention timeUS5952692Oct 28, 1997Sep 14, 1999Hitachi, Ltd.Memory device with improved charge storage barrier structureUS6005809Jun 19, 1998Dec 21, 1999Taiwan Semiconductor Manufacturing Company, Ltd.Program and erase method for a split gate flash EEPROMUS6011725Feb 4, 1999Jan 4, 2000Saifun Semiconductors, Ltd.Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingUS6026026Dec 5, 1997Feb 15, 2000Hyundai Electronics America, Inc.Self-convergence of post-erase threshold voltages in a flash memory cell using transient responseUS6074917Nov 11, 1998Jun 13, 2000Advanced Micro Devices, Inc.LPCVD oxide and RTA for top oxide of ONO film to improve reliability for flash memory devicesUS6169693Oct 28, 1999Jan 2, 2001Hyundai Electronics America, Inc.Self-convergence of post-erase threshold voltages in a flash memory cell using transient responseUS6218700Oct 28, 1998Apr 17, 2001Stmicroelectronics S.A.Remanent memory deviceUS6512696Nov 13, 2001Jan 28, 2003Macronix International Co., Ltd.Method of programming and erasing a SNNNS type non-volatile memory cellUS6671209Oct 22, 2001Dec 30, 2003Macronix International Co., Ltd.Erasing method for p-channel NROMUS6680505Mar 28, 2002Jan 20, 2004Kabushiki Kaisha ToshibaSemiconductor storage elementUS6709928Jul 31, 2001Mar 23, 2004Cypress Semiconductor CorporationSemiconductor device having silicon-rich layer and method of manufacturing such a deviceUS6720630May 30, 2001Apr 13, 2004International Business Machines CorporationStructure and method for MOSFET with metallic gate electrodeUS6784480Feb 12, 2002Aug 31, 2004Micron Technology, Inc.Asymmetric band-gap engineered nonvolatile memory deviceUS6818558Jun 28, 2002Nov 16, 2004Cypress Semiconductor CorporationMethod of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devicesUS6897533Sep 18, 2002May 24, 2005Advanced Micro Devices, Inc.Multi-bit silicon nitride charge-trapping non-volatile memory cellUS6903968 *Jan 22, 2004Jun 7, 2005Applied Intellectual Properties Co., Ltd.Nonvolatile memory capable of storing multibits binary information and the method of forming the sameUS6912163Sep 9, 2003Jun 28, 2005Fasl, LlcMemory device having high work function gate and method of erasing sameUS6942320Jan 24, 2002Sep 13, 2005Industrial Technology Research InstituteIntegrated micro-droplet generatorUS7075828Jun 24, 2004Jul 11, 2006Macronix International Co., Intl.Operation scheme with charge balancing erase for charge trapping non-volatile memoryUS7115469Jan 8, 2004Oct 3, 2006Spansion, LlcIntegrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) processUS7115942Dec 8, 2004Oct 3, 2006Chih-Hsin WangMethod and apparatus for nonvolatile memoryUS7133313Jun 24, 2004Nov 7, 2006Macronix International Co., Ltd.Operation scheme with charge balancing for charge trapping non-volatile memoryUS7151692May 20, 2005Dec 19, 2006Macronix International Co., Ltd.Operation scheme for programming charge trapping non-volatile memoryUS7164603Jun 24, 2004Jan 16, 2007Yen-Hao ShihOperation scheme with high work function gate and charge balancing for charge trapping non-volatile memoryUS7190614May 20, 2005Mar 13, 2007Macronix International Co., Ltd.Operation scheme for programming charge trapping non-volatile memoryUS7209390Jun 24, 2004Apr 24, 2007Macronix International Co., Ltd.Operation scheme for spectrum shift in charge trapping non-volatile memoryUS7391652May 5, 2006Jun 24, 2008Macronix International Co., Ltd.Method of programming and erasing a p-channel BE-SONOS NAND flash memoryUS20030030100Jul 2, 2002Feb 13, 2003Samsung Electronics Co., Ltd.Non-volatile memory device and method for fabricating the sameUS20030032242Jul 12, 2002Feb 13, 2003Samsung Electronics Co., Ltd.Method of forming non-volatile memory having floating trap type deviceUS20030042534Aug 30, 2001Mar 6, 2003Micron Technology, Inc.Scalable flash/NV structures and devices with extended enduranceUS20030117855Feb 11, 2003Jun 26, 2003Hyundai Electronics Industries Co., Ltd.Method of erasing a flash memory cellUS20030146465Feb 7, 2002Aug 7, 2003Ching-Yuan WuScalable multi-bit flash memory cell and its memory arrayUS20030224564Jun 4, 2002Dec 4, 2003Samsung Electronics Co., LtdNon-volatile memory cell having a silicon-oxide nitride-oxide-silicon gate structure and fabrication method of such cellUS20040079983Oct 14, 2003Apr 29, 2004Chae Soo-DooNonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon memoryUS20040183126Mar 17, 2003Sep 23, 2004Geum-Jong BaeLocal sonos-type structure having two-piece gate and self-aligned ono and method for manufacturing the sameUS20040251489Jun 10, 2004Dec 16, 2004Sang-Hun JeonSONOS memory device and method of manufacturing the sameUS20050006696May 21, 2004Jan 13, 2005Kabushiki Kaisha ToshibaSemiconductor memoryUS20050023603Aug 30, 2004Feb 3, 2005Micron Technology, Inc.Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulatorsUS20050074937Dec 30, 2003Apr 7, 2005Anam Semiconductor, Inc.Method for fabricating flash memory deviceUS20050093054Nov 4, 2004May 5, 2005Jung Jin H.Non-volatile memory devices and methods of fabricating the sameUS20050219906May 20, 2005Oct 6, 2005Macronix International Co., Ltd.Operation scheme for programming charge trapping non-volatile memoryUS20050237801Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Operation scheme with charge balancing for charge trapping non-volatile memoryUS20050237809Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memoryUS20050237813Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Method and system for self-convergent erase in charge trapping memory cellsUS20050237815Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Operation scheme with charge balancing erase for charge trapping non-volatile memoryUS20050237816Jun 24, 2004Oct 27, 2005Macronix International Co., Ltd.Operation scheme for spectrum shift in charge trapping non-volatile memoryUS20050270849Jun 2, 2004Dec 8, 2005Macronix International Co. Ltd.Program/erase method for p-channel charge trapping memory deviceUS20050281085May 20, 2005Dec 22, 2005Macronix International Co., Ltd.Operation scheme for programming charge trapping non-volatile memoryUS20060118858Oct 11, 2005Jun 8, 2006Samsung Electronics Co., Ltd.Non-volatile semiconductor memory device with alternative metal gate materialUS20060198189Jan 3, 2006Sep 7, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS20060198190Jan 3, 2006Sep 7, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS20060202252Jan 3, 2006Sep 14, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS20060202261Jan 3, 2006Sep 14, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysUS20060258090May 12, 2005Nov 16, 2006Micron Technology, Inc.Band-engineered multi-gated non-volatile memory device with enhanced attributesUS20060261401May 17, 2005Nov 23, 2006Micron Technology, Inc.Novel low power non-volatile memory and gate stackUS20060281260May 4, 2006Dec 14, 2006Hang-Ting LueMethods of operating p-channel non-volatile memory devicesUS20070012988Jul 14, 2005Jan 18, 2007Micron Technology, Inc.High density NAND non-volatile memory deviceUS20070029625Aug 4, 2005Feb 8, 2007Macronix International Co., Ltd.Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layerUS20070031999Aug 4, 2005Feb 8, 2007Macronix International Co. Ltd.Non-volatile memory cells and methods of manufacturing the sameUS20070045718Aug 31, 2005Mar 1, 2007Micron Technology, Inc.Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injectionUS20070069283Sep 27, 2005Mar 29, 2007Macronix International Co., Ltd.Method of forming bottom oxide for nitride flash memoryUS20070120179Aug 16, 2006May 31, 2007Park Hong-BaeSONOS type non-volatile memory devices having a laminate blocking insulation layer and methods of manufacturing the sameUS20090039417Feb 17, 2005Feb 12, 2009National University Of SingaporeNonvolatile Flash Memory Device and Method for Producing Dielectric Oxide Nanodots on Silicon DioxideCN1606165ANov 10, 2004Apr 13, 2005北京大学Flash memory storing unit and method for making sameEP0016246A1Oct 3, 1979Oct 1, 1980International Business Machines CorporationSemiconductor field effect structure of the Metal-Insulator-Metal or Metal-Insulator-Semiconductor type, and memory device comprising such structureEP1411555A2Apr 14, 2003Apr 21, 2004Samsung Electronics Co., Ltd.Nonvolatile silicon/oxide/nitride/silicon/nitride/oxide/silicon memoryEP1677311A1Jan 3, 2006Jul 5, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysEP1677312A1Jan 3, 2006Jul 5, 2006Macronix International Co., Ltd.Non-volatile memory cells, memory arrays including the same and methods of operating cells and arraysJP2004363329A Title not available* Cited by examinerNon-Patent CitationsReference1Aminzadeh et al., "Conduction and Charge Trapping in Polysilicon-Silicon Nitride-Oxide-Silicon Structures under Positive Gate Bias," IEEE Transactions on Electron Devices . . . vol. 35, No. 4, Apr. 1998, pp. 459-467.2Baik, Seung, et al., "High Speed and Nonvolatile Si Nanocrystal Memory for Scaled Flash Technology using Highly Field-Sensitive Tunnel Barrier," IEEE IEDM 03-545, 22.3.1-22.3.4.3Blomme et al., "Multilayer tunneling barriers for nonvolatile memory applications," Device Research Conference, 2002. 60th DRC. Conference Digest, 2002, 153-4.4Blomme et al., Write/Erase Cycling Endurance of Memory Cells With SiO2/HfO2 Tunnel Dielectric, IEEE Transactions on Device and Materials Reliability, vol. 4, No. 3, Sep. 2004, pp. 345-351.5Buckley, J., et al., "Engineering of 'Conduction band-Crested Barriers' or 'Dielectric Constant-Crested Barriers' in view of their application of floating-gate non-volatile memory devices," VLSI 2004, 55-56.6Chindalore et al., " A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories," IEEE Electron Dev Lett 24(4) Apr. 2003, 257-259.7Cho et al., "Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONOS Flash EEPROM Cells," IEEE Electron Device Letters, vol. 24 No. 4, Apr. 2003, pp. 260-262.8DiMaria, D.J., et al., "Conduction Studies in Silicon Nitride: Dark Currents and Photocurrents," IBM J. Res. Dev. May 1977, 227-244.9Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Lett 21(11) Nov. 2000, 543-545.10Govoreanu et al., "An Investigation of the Electron Tunneling Leakage Current through Ultrathin Oxides/High-k Gate Stacks at Inversion Conditions," IEEE 2003, pp. 287-290, SISPAD Intl. Conf. Sep. 3-5, 2003.11Govoreanu et al., "Simulation of Nanofloating Gate Memory with High-k Stacked Dielectrics," IEEE 2003, pp. 299-302, SISPAD Intl. Conf. Sep. 3-5, 2003.12Govoreanu, et al., "Variot: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices," IEEE Electron Device Letters, vol. 24, No. 2, Feb. 2003, pp. 94-101.13Hijaya, S., et al., "High-Speed Write/Erase EAROM Cell with Graded Energy BAnd-Gap Insulator," Electronics and Comm in Japan, Part 2, vol. 68, No. 2, Jun. 6, 1984, 28-36.14Hinkle, C.L., et al., "Enhanced tunneling in stacked gate dielectrics with ultra-thin HfO2 (ZrO2) layers sandwiched between thicker SiO2 Layers," Surface Science Sep. 20, 2004, vol. 566-568, 1185-1189.15Ito et al., "A Novel MNOS Techology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications," 2004 Symp. on VLSI Tech Digest of Tech Papers 2004, 80-81.16Kim et al., "Robust Multi-bit Programmable Flash Memory Using a Resonant Tunnel Barrier," Electron Devices Meeting, Dec. 5-7, 2005, IEDM Technical Digest, pp. 861-864.17Lee, Chang, et al., "A Novel SONOS Structure of SiO2/SiN/Al2O3 with TaN Metal Gate for Multi-Giga Bit Flash Memeries," IEEE 2003, 4 pages.18Lee, Chungho, et al., "Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single-and Double-Layer Metal Nanocrystals," IEEE IEDM 03-557, 22.6.1-22.6.4.19Likharev, "Layered tunnel barriers for nonvolatile memory devices," Applied Physics Letters, vol. 73, No. 15, Oct. 1998, pp. 2137-2139.20Lue et al., "A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory," Int'l Symp on VLSI Tech, Apr. 23-25, 2007, 2 pages.21Lue et al., "A Novel P-Channel NAND-Type Flash memory with 2-bit/cell Operation and High Programming Throughput (>20 MB/sec)," IEEE 2005, 4 pages.22Lue et al., "BE-SONOS: A Bandgap Engineering SONOS with Excellent Performance and Reliability," IEDM Tech. Digest. IEEE Intl., Dec. 2005, 547-550.23Lue, Hang-Ting, File History of U.S. Appl. No. 12/121,791, filed May 16, 2008, 69 pages.24Minami et al., "New Scaling Guidelines for MNOS Nonvolatile Memory Devices," IEEE Trans on Electron Devices 38(11) Nov. 1991 2519-2526.25Padilla, Alvaro, et al., "Dual-bit SONOS FinFET Non-Volatile Memory Cell and New Method of Charge Detection," Int'l Symp on VLSI Technology, Systems and Applications, Apr. 23-25, 2007, 2 pages.26Search Report mailed Feb. 14, 2007 in European Application No. 06000064.3 filed on Jan. 3, 2006, 7 pages.27Search Report mailed Feb. 14, 2007 in European Application No. 06000093.2 filed on Jan. 3, 2006, 7 pages.28Search Report mailed May 9, 2008 in European Application No. 06000064.3 filed on Jan. 3, 2006, 3 pages.29Search Report mailed May 9, 2008 in European Application No. 06000093.2 filed on Jan. 3, 2006, 4 pages.30Search Report mailed Nov. 14, 2007 in European Application No. 06000064.3 filed on Jan. 3, 2006, 4 pages.31Shih et al., "A Novel 2-bit/cell Nitride Storage Flash memory with Greater than 1M P/E-cycle Endurance," IEEE 2004, pp. 36.3.1-36.3.4, IEDM 04-881 to 884.32Sung et al., "Multi-Layer SONOS with Direct Tunnel Oxide for High Speed and Long Retention Time," IEEE 2002 Silicon Nanoelectronics Workshop, Jun. 2002, pp. 83-84.33Takata, M., et al., "New Non-Volatile Memory with Extremely High Density Metal Nano-Dots," IEEE IEDM 03-553, 22.5.1-22.5.4.34Tsai et al., " Novel SONOS-Type Nonvolatile Memory Device with Suitable Band Offset in HfAlO Charge-Trapping Layer," Int'l Symp. on VLSI Tech, Systems and Applications, Apr. 23-25, 2007, 2 pages.35Walker, et al., "3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications," 2003 Symposium on VLSI Tech Digest of Technical Papers, 29-30.36Wen, Huang-Chun, et al., "Issues associated with p-type band-edge effective work function metal electrodes: Fermi-level pinning and flatband roll-off," In'l Symp on VLSI Technology, Systems and Applications, Apr. 23-25, 2007, 2 pages.37White et al., "On the Go with SONOS" IEEE Circuits and Devices, Jul. 2000, 22-31.38Yamada et al., "A self-convergence erasing scheme for a simple stacked gate flash EEPROM," Proceedings of the International Electron Devices Meeting, IEEE, Dec. 1991, 307-310.39Yeh, C.C., et al., "Phines: a Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory," IEDM Tech Digest 2002, 931-934.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7986556Nov 6, 2009Jul 26, 2011Macronix International Co., Ltd.Methods of operating non-volatile memory devicesUS7995386 *Aug 9, 2011Spansion LlcApplying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturbUS8072022 *Dec 24, 2008Dec 6, 2011Intel CorporationApparatus and methods for improved flash cell characteristicsUS8222688Apr 26, 2010Jul 17, 2012Cypress Semiconductor CorporationSONOS stack with split nitride memory layerUS8643124Jan 14, 2011Feb 4, 2014Cypress Semiconductor CorporationOxide-nitride-oxide stack having multiple oxynitride layersUS8685813Mar 23, 2012Apr 1, 2014Cypress Semiconductor CorporationMethod of integrating a charge-trapping gate stack into a CMOS flowUS8710578Mar 27, 2012Apr 29, 2014Cypress Semiconductor CorporationSONOS stack with split nitride memory layerUS8710579Jul 17, 2012Apr 29, 2014Cypress Semiconductor CorporationSONOS stack with split nitride memory layerUS8940645Jul 1, 2012Jan 27, 2015Cypress Semiconductor CorporationRadical oxidation process for fabricating a nonvolatile charge trap memory deviceUS9105512Apr 29, 2014Aug 11, 2015Cypress Semiconductor CorporationSONOS stack with split nitride memory layerUS9184162 *Feb 6, 2015Nov 10, 2015GlobalFoundries, Inc.FinFET integrated circuits and methods for their fabricationUS9355849Jun 13, 2013May 31, 2016Cypress Semiconductor CorporationOxide-nitride-oxide stack having multiple oxynitride layersUS20090166717 *Dec 28, 2008Jul 2, 2009Jin-Hyo JungNonvolatile memory device and method for manufacturing the sameUS20100128521 *Nov 21, 2008May 27, 2010Spansion LlcApplying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturbUS20100155807 *Dec 24, 2008Jun 24, 2010Pranav KalavadeApparatus and methods for improved flash cell characteristicsUS20150179644 *Feb 6, 2015Jun 25, 2015GlobalFoundries, Inc.Finfet integrated circuits and methods for their fabrication* Cited by examinerClassifications U.S. Classification365/185.18, 365/185.28, 365/185.05International ClassificationG11C11/34Cooperative ClassificationG11C16/0483, H01L27/115, G11C16/0475, H01L27/11568European ClassificationG11C16/04N, H01L27/115G4, H01L27/115, G11C16/04M2Legal EventsDateCodeEventDescriptionJul 28, 2006ASAssignmentOwner name: MACRONIX INTERNATIONAL CO., LTD., TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUE, HANG-TING;REEL/FRAME:018017/0316Effective date: 20060724Nov 9, 2010CCCertificate of correctionMar 11, 2013FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services