Source: http://www.google.com/patents/US6459592?dq=U.S.+Patent+%23+5,723,324
Timestamp: 2015-05-06 03:09:06
Document Index: 310103029

Matched Legal Cases: ['art 57', 'art 57', 'art 57', 'art 21', 'art 21', 'art 21', 'art 21', 'arts 21', 'art 21', 'art 21', 'art 21', 'art 21', 'art 21', 'art 21', 'art 31', 'art 31', 'art 31', 'art 31']

Patent US6459592 - Circuit assembly including VLSI package - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA VLSI package assembly comprising a package substrate carrying thereon an IC chip, a mother board supporting thereon the package substrate, and a connection means for providing electric connection between the substrate and the mother board. The connections means has a high durability against stresses...http://www.google.com/patents/US6459592?utm_source=gb-gplus-sharePatent US6459592 - Circuit assembly including VLSI packageAdvanced Patent SearchPublication numberUS6459592 B1Publication typeGrantApplication numberUS 09/416,064Publication dateOct 1, 2002Filing dateOct 12, 1999Priority dateOct 14, 1998Fee statusLapsedPublication number09416064, 416064, US 6459592 B1, US 6459592B1, US-B1-6459592, US6459592 B1, US6459592B1InventorsYasuhito AnzaiOriginal AssigneeOki Electric Industry Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (10), Referenced by (7), Classifications (30), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetCircuit assembly including VLSI package
US 6459592 B1Abstract
What is claimed is: 1. A VLSI package assembly, comprising:
A PKG substrate carrying on one major surface thereof an IC chip, and having on another surface thereof a plurality of first connection pads arranged in a two-dimensional format; a motherboard having a plurality of second connection pads two-dimensionally arranged on one surface thereof confronting said other surface of the PKG structure, each of the first connection pads having a smaller exposed area for soldering than that of the second connection pads, the first pads treated with an electrolytic plating process and the second pads treated with a non-electrolytic plating process; and a plurality of solder bumps, the pluralities of first and second connection pads and the plurality of solder bumps together defining an electric path assembly including respective opposing ones of the pluralities of first and second connection pads and respective ones of the solder bumps electrically connecting between the opposing first and second connection pads, wherein said electric path assembly includes by itself an anti-stress structure with a high durability against stresses occurring therein. 2. A VLSI package assembly, comprising:
a PKG substrate carrying on one major surface thereof an IC chip, and having on another surface thereof a plurality of first connection pads arranged in a two-dimensional format; a motherboard having a plurality of second connection pads two-dimensionally arranged on one surface thereof confronting said other surface of the PKG structure, each of the first connection pads having a smaller exposed area for soldering than that of the second connection pads and one of said first and second connection pads includes a resilient flat plate which is partly divided into two pieces, that are separable from each other, and one of which is separable from the surface on which it is mounted; and a plurality of solder bumps, the pluralities of first and second connection pads and the plurality of solder bumps together defining an electric path assembly including respective opposing ones of the pluralities of first and second connection pads and a deformable structure which is deformable in response to a stress exerted thereon, and respective ones of the solder bumps electrically connecting between the opposing first and second connection pads, wherein said electric path assembly includes by itself an anti-stress structure with a high durability against stresses occurring therein. 3. A VLSI package assembly according to claim 2, in which the exposed areas of said first and second pads are respectively circular.
a PKG substrate having a major surface and an other surface; an IC mounted on the substrate major surface; a motherboard having one surface confronting the other surface of the PKG substrate; and an electric path assembly, including a two-dimensional array of first connection pads on the other surface of the PKG substrate, a two-dimensional array of second connection pads on the one surface of the motherboard, each of the second connection pads being in opposing relation to a respective one of the first connection pads, one of the first and second connection pads including a resilient flat plate partially divided into two pieces which are separable from each other, one of the two pieces being fixed to one of the motherboard and the substrate, and the other being a tongue part connected with the solder bump and separable from one of the motherboard and the substrate; and an array of solder bumps interposed between the arrays of first and second connections pads so that each solder bump connects a respective pair of opposing first and second connection pads, to define a respective electric current conduit between the substrate and the motherboard, wherein each electric current conduit contains therein an anti-stress structural means for relieving stresses occurring therein. 10. A VLSI package assembly according to claim 9, wherein the anti-stress structural means of each electric current conduit is defined by a division in at least one pad of the first and second pads thereof, partially separating the one pad into first and second resiliently connected parts the first part being connected to the solder bump more strongly than the second part.
a PKG substrate carrying on one major surface thereof an IC chip, and having another surface; a motherboard having one surface confronting the other surface of the PKG substrate; an electric path assembly, including a plurality of first connection pads arranged in a two-dimensional format on the other surface of the PKG substrate; a plurality of second connection pads two-dimensionally arranged on the one surface such that each second connection pad opposing a respective one of the first connection pads; and a two-dimensional array of solder bumps arranged between the pluralities of first and second connection pads, such that each solder bump connects a respective pair of opposing first and second connection pads to define a respective electric current conduit between the substrate and the motherboard, wherein each of the second connection pads includes a resilient flat plate which is partially divided into two pieces which are separable from each other, one of the two pieces fixed to said motherboard, the other a tongue part connected with the solder bump and separable from said motherboard thereby to relieve stresses occurring in the electric current conduit.
Recently, the degree of integration of the VLSI has been more enhanced and accordingly the number of the connection pins per one IC package substrate has been much increased. The connection pins are formed on the bottom surface of the IC package substrate in a two-dimensional manner so as to suppress the largeness of the size of the package substrate. An example of such a two-dimensional arrangement of the connection pin is the so-called �pin grid array (PGA)�. The PGA technique is so effective in enhancing the degree of integration of a VLSI since such technique can avoid the situation in which the pitch between the connection pins becomes too narrow because of the two-dimensional arrangement of the connection terminals.
FIG. 2C is a plan view of the arrangement of FIG. 2A along a line A�A appearing in FIG. 2A. As seen from FIG. 2C, the mother board I/O pad 57 includes a soldering connection part 57 a which is to be connected with the soldering bump 55 and an external connection part 57 b. It is now to be understood that a central portion of the soldering connection part 57 a is exposed to the outside through an aperture 60 a of the soldering resist 61 so that the central portion can be connected with the soldering bump 55.
FIG. 2C is a plan view showing a single I/O pad along a line A�A appearing in FIG. 2A.
In this embodiment, each of the mother board I/O pads 21 is made of a flat metallic member, which is divided into the annular outer part 21 a and the circular tongue part 21 b. The circular tongue part 21 b is separated or separable from the annular outer part 21 a through a chemical method such as etching. In this instance, it is to be understood that the solder bump 15 is adhered both to the outer and the inner parts 21 a and 21 b. In the second embodiment, the mother board I/O pad 21 includes the tongue part 21 b that is separated or separable from the fixed part 21 a, and therefore the tongue part 21 b can absorb stress or force caused by the terminal expansions of the PKG substrate 13 and mother board 16 or dropping of the BGA package 20. Even when the mother board I/O pad 21 is displaced relative to the PKG I/O pad 14 the electrical connection between the solder bump 15 and tongue part 21 b can be kept because the tongue part 21 b is peeled off from the mother board 16 and is separated from the outer part 21 a, as seen from FIG. 4A.
In this third embodiment, the tongue part 31 b is separated from the fixed part 31 a because of breakage of the bump 15 in case the electrical connection assembly is subjected to a stress or force because of thermal expansions of the PKG substrate 13 and the mother board 16 under abrupt changes in the environmental temperature or shocks because of dropping of the device, whereby the electrical connection within the electrical connection assembly is kept since the solder bump 15 continues to contact with at least the tongue 31 b. It is now to be understood that the pad 14 on the PKG substrate 13 may be modified to have a similar structure as in the pad 21 or 31, if desired. That is, the pad 14 may be separated or separable into an outer annular part and an inner circular part. The outer annular part is fixed to the substrate 13 while the inner circular part is separated or separable from the outer annular part.
Furthermore, a specific treatment may be applied to the surface of the mother board 16 so that the tongue part 31 b can be more readily peeled from the mother board 16 than the fixed part 31 a. In the VLSI assembly according to the present invention, the electric connection pad is separable into two parts such as central and peripheral parts so that the central part can be separated from the peripheral part thereby to absorb stresses or forces applied to the assembly.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5011066 *Jul 27, 1990Apr 30, 1991Motorola, Inc.Enhanced collapse solder interconnectionUS5147084 *Aug 9, 1991Sep 15, 1992International Business Machines CorporationInterconnection structure and test methodUS5329423 *Apr 13, 1993Jul 12, 1994Scholz Kenneth DCompressive bump-and-socket interconnection scheme for integrated circuitsUS5477933 *Oct 24, 1994Dec 26, 1995At&T Corp.Electronic device interconnection techniquesUS5834848 *Dec 2, 1997Nov 10, 1998Kabushiki Kaisha ToshibaElectronic device and semiconductor packageUS5847456 *Feb 18, 1997Dec 8, 1998Nec CorporationSemiconductor deviceUS5889326 *Feb 27, 1997Mar 30, 1999Nec CorporationStructure for bonding semiconductor device to substrateUS6002172 *Mar 12, 1997Dec 14, 1999International Business Machines CorporationSubstrate structure and method for improving attachment reliability of semiconductor chips and modulesUS6081038 *Apr 5, 1999Jun 27, 2000Shinko Electric Industries Co., Ltd.Semiconductor chip package structureUS6125043 *Sep 15, 1998Sep 26, 2000Robert Bosch GmbhCircuit board arrangement with accurately positioned components mounted thereon* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6940178Feb 22, 2002Sep 6, 2005Chippac, Inc.Self-coplanarity bumping shape for flip chipUS7018219 *Feb 25, 2004Mar 28, 2006Rosenau Steven AInterconnect structure and method for connecting buried signal lines to electrical devicesUS7211901Jun 3, 2005May 1, 2007Chippac, Inc.Self-coplanarity bumping shape for flip chipUS7407877Jun 3, 2005Aug 5, 2008Chippac, Inc.Self-coplanarity bumping shape for flip-chipUS20130153645 *Nov 19, 2012Jun 20, 2013Princeton Lightwave, Inc.Process for Hybrid Integration of Focal Plane ArraysDE112005000438B4 *Feb 24, 2005Dec 19, 2013Avago Technologies General Ip (Singapore) Pte. Ltd.Eine Zwischenverbindungsstruktur und ein Verfahren zum Verbinden von vergrabenen Signalleitungen mit elektrischen VorrichtungenWO2002069372A2 *Feb 25, 2002Sep 6, 2002Chippac IncSelf-coplanarity bumping shape for flip chip* Cited by examinerClassifications U.S. Classification361/760, 174/261, 361/790, 361/764, 174/34, 361/767, 257/E23.07, 257/737, 257/772International ClassificationH05K1/18, H05K3/32, H01L23/498, H05K3/40, H05K3/34, H01L23/12Cooperative ClassificationH05K3/4092, H01L23/49838, H05K2201/0397, H05K3/326, H05K3/3436, H01L2224/32225, H05K2201/09663, H05K2201/09381, H01L2224/73204, H01L2224/16225, H05K2201/10734, H01L2924/15311European ClassificationH05K3/34C4B, H01L23/498G, H05K3/32C2Legal EventsDateCodeEventDescriptionNov 18, 2014FPExpired due to failure to pay maintenance feeEffective date: 20141001Oct 1, 2014LAPSLapse for failure to pay maintenance feesMay 9, 2014REMIMaintenance fee reminder mailedMar 21, 2014ASAssignmentOwner name: LAPIS SEMICONDUCTOR CO., LTD., JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI SEMICONDUCTOR CO., LTD;REEL/FRAME:032495/0483Effective date: 20111003Mar 18, 2010FPAYFee paymentYear of fee payment: 8Feb 19, 2009ASAssignmentOwner name: OKI SEMICONDUCTOR CO., LTD., JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022299/0368Effective date: 20081001Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100216;REEL/FRAME:22299/368Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100216;REEL/FRAME:22299/368Effective date: 20081001Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022299/0368Effective date: 20081001Mar 13, 2006FPAYFee paymentYear of fee payment: 4Dec 30, 1999ASAssignmentOwner name: OKI ELECTRIC INDUSTRY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ANZAI, YASUHITO;REEL/FRAME:010464/0864Effective date: 19991220Owner name: OKI ELECTRIC INDUSTRY CO., LTD. 7-12, TORANOMON 1-Owner name: OKI ELECTRIC INDUSTRY CO., LTD. 7-12, TORANOMON 1-Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ANZAI, YASUHITO;REEL/FRAME:010464/0864Effective date: 19991220RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services