Source: http://www.google.com/patents/US6734505?dq=7,339,580
Timestamp: 2015-03-31 18:55:03
Document Index: 796072583

Matched Legal Cases: ['art 32', 'art 32', 'art 32', 'art 32', 'art 32', 'art 32', 'art 32', 'art 32', 'art 32', 'art 32', 'art 32', 'art 32']

Patent US6734505 - Thin film transistor and use of same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsDisclosed are a thin film transistor capable of controlling gray level of an organic LED element by discretely controlling current levels, a method of manufacturing the thin film transistor, an array substrate including the thin film transistor, a display device, and a method of driving the display device....http://www.google.com/patents/US6734505?utm_source=gb-gplus-sharePatent US6734505 - Thin film transistor and use of sameAdvanced Patent SearchPublication numberUS6734505 B2Publication typeGrantApplication numberUS 10/222,339Publication dateMay 11, 2004Filing dateAug 15, 2002Priority dateAug 16, 2001Fee statusPaidAlso published asUS7002181, US20030038288, US20040222472Publication number10222339, 222339, US 6734505 B2, US 6734505B2, US-B2-6734505, US6734505 B2, US6734505B2InventorsHiroshi Suzuki, Takatoshi TsujimuraOriginal AssigneeInternational Business Machines CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (10), Referenced by (5), Classifications (36), Legal Events (8) External Links: USPTO, USPTO Assignment, EspacenetThin film transistor and use of same
US 6734505 B2Abstract
a first insulating film having a first and a second surface; an active layer positioned on a portion of said first surface of said first insulating film; a second insulating film positioned on said active layer and on said first surface of said first insulating film; a first gate electrode having a first area positioned on said second surface of said first insulating film; a second gate electrode positioned an said second insulating film, said second gate electrode having a second area less than or greater than said first area of said first gate electrode; and a first conductor connected to said first gate electrode for selectively applying a first voltage to said first gate electrode and operate said transistor in conjunction with or independent of said second gate electrode; and a second conductor connected to said second gate electrode for selectively applying a second voltage to said second gate electrode and operate said transistor in conjunction with or independent of said first gate electrode. 2. The thin film transistor according to claim 1, further including two conductive layers positioned on said active layer, each of said conductive layers including a side wall and a bottom wall connecting said sidewalls therein defining a channel, said bottom wall defined by said active layer.
5. The thin film transistor according to claim 4, wherein said predetermined width of each of said fist and second gate electrodes is greater than said predetermined width of said bottom wall of said channel.
9. The invention according to claim 1, wherein said thin film transistor is electrically connected to an organic LED element whereby the brightness of the LED is varied responsive to said gate or gates that are operating said transistors.
providing a first insulating film having a first and a second surface; positioning an active layer on a portion of said first surface of said first insulating film; positioning a second insulating film on said active layer and on said first surface of said first insulating film; positioning a first gate electrode having a first area on said second surface of said first insulating film; positioning a second gate electrode on said second insulating film, said second gate electrode having a second area less than or greater than said first area of said first gate electrode; connecting a first conductor to said first gate electrode for applying a first voltage to said first gate electrode; and connecting a second conductor to said second gate electrode for applying a second voltage to said second gate electrode. 15. The method of manufacturing a thin film transistor according to claim 14, wherein said step of positioning said active layer on said portion of said first surface of said fist insulating film is accomplished by chemical vapor deposition.
An organic LED (light emitting diode) has a very high response speed and is a self-emitting device, and thus, it is expected that the application of the organic LED to a display device will allow providing an excellent flat display device having a wide viewing angle. The application of the organic LED to the flat display device replaces a liquid crystal display device. The above-mentioned organic LED is a current-driven element, and thus, the achievement of high-resolution display requires a continuous feed of a current through the organic LED element even during non-selection of a scanning line.
FIG. 9 is a diagram showing a circuit configuration for driving an organic LED, which has been heretofore proposed. The conventional circuit configuration shown in FIG. 9 includes a switching thin film transistor, hereinafter referred to as TFT 80, for generally performing switching, and a driver TFT 84 for driving an organic LED element 82. Switching TFT 80 is driven to be turned on and off in accordance with a signal supplied through a scan line 86, and thus supplies to driver TFT 84 a signal supplied through a signal line 88.
As shown in FIG. 10, the organic LED element varies in its current-voltage characteristics for each pixel because of various factors. Thus, the same gray level cannot be applied to the organic LED element stably even when a certain gate voltage Vgate is applied to the organic LED element formed for one pixel each, as shown in FIG. 10. Consequently, a problem exists: when the current level is changed only by changing the gate voltage by use of the circuit configuration shown in FIG. 9 and then gray level control is performed by direct use of the changed current level, the use of only this gray level control does not permit display of precise gray level throughout the whole screen of the display device.
A method of performing gray level control by changing a luminous area of the organic LED element through only on-off control by utilizing the characteristics that a maximum current value Imax and a minimum current value Imindo not vary pixel by pixel even if the current-voltage characteristics vary as shown in FIG. 10, that is, a so-called area gray level control method, has been also proposed in order to solve the above-mentioned problem. FIG. 11 shows a drive circuit which has been heretofore proposed to implement the area gray level control method. In the drive circuit shown in FIG. 11, a plurality of organic LED elements 82 are arranged for each pixel 96, and the drive circuit is adapted to be capable of controlling the gray level by controlling the number of organic LED elements 82 to emit light in the luminous area.
FIG. 12 is a plan view showing a configuration in which a plurality of organic LED elements 82 are arranged for each pixel for performing the conventional area gray level control. Organic LED elements 82 are configured in such a manner that a signal is supplied to these organic LED elements from a wiring 98.
For driving the organic LED, a thin film transistor (TFT), as described above, is often used to drive the organic LED for display per pixel. The TFT for use in this case, particularly, the driver TFT, is required to be capable of providing a high level of current with stability. Various TFT structures have been heretofore proposed as TFT structures having stabilized current characteristics. A so-called dual gate TFT structure is disclosed in the gazette of Japanese Patent Laid-Open No. Hei 8(1996)-241997, for example. In this structure, gate electrodes are located oppositely to each other so as to sandwich an active layer with insulating layers interposed between the gate electrodes, and one of the gate electrodes is formed shorter than the other gate electrode in a source-drain direction.
FIG. 5 is a set of four graphs showing a method of driving the elements of the thin film transistor array substrate of the present invention, by use of a correlation between control of the controllers and on-off control of a top gate part and a bottom gate part of the driver TFT corresponding to the control of the controllers;
FIGS. 7(a) to 7(d) are cross-sectional views in elevation illustrating a method of manufacturing a thin film transistor including the driver TFT and the controllers of the present invention;
FIG. 2 is a perspective view showing in detail the arrangement of first and second gate electrodes 12 and 14 of dual gate TFT of the present invention relative to channel 26. As shown in FIG. 2, first and second gate electrodes 12 and 14 are formed in such a manner that an area S1 of first gate electrode 12 is different from an area S2 of second gate electrode 14. As described above, first and second gate electrodes 12 and 14 are formed in such a manner that the areas S1 and S2 are different from each other. Therefore, when first and second gate electrodes 12 and 14 are turned on, the conductance of first gate electrode 12 differs from the conductance of second gale electrode 14, thus enabling at least four levels of gray level control.
FIG. 3 is a diagram showing a schematic circuit configuration of a transistor element and an organic LED element, which are formed in one pixel of a thin film transistor array substrate using dual gate TFT of the present invention. As shown in FIG. 3, switching TFT 30 for switching on and off organic LED element 29, and driver TFT 32 for feeding a current to organic the LED element are formed in the pixel of the thin film transistor array substrate of the present invention.
FIG. 5 is a set of four graphs illustrating a method of driving the respective elements of the thin film transistor array substrate of the present invention, by use of a correlation between the control of controllers 34 and 36 and the on-off control of top gate part 32 a (T) and bottom gate part 32 b (B) of driver TFT 32 corresponding to the control of controllers 34 and 36. In FIG. 5, Vth indicates a threshold voltage applied to the respective gate electrodes of controllers 34 and 36 in order to turn on and off top gate part 32 a and bottom gate part 32 b. Controller 34 can independently perform on-off control of top gate part 32 a, and controller 36 can independently perform on-off control of bottom gate part 32 b. Thus, current levels I1 to I4, where I is defined as current to an LED, can be discretely controlled corresponding to the on-off control of controller 34 and the on-off control of controller 36. Table 1 shows the correspondence between the current levels I1 to I4, as shown in FIG. 5, and the on/off switching states of controllers 34 and 36 which are turned on and off by the driving method of the present invention (varying the threshold voltage Vth to the gate electrodes 36 c and 34 c of controllers 34 and 36, respectively.
I1 I2 OFF
I3 I4 FIG. 6 is a graph showing current characteristics supplied to organic LED element 29 (FIG. 3) according to respective control levels by the driving method of the present invention. In FIG. 6, Vt represents the potential of the second gate electrode (constituting top gate part 32 a), and Vb represents the potential of the first gate electrode (constituting bottom gate part 32 b). The current characteristics shown in FIG. 6 refer to a current supplied to organic LED element 29, which is obtained by plotting a drain-source current Ids of driver TFT 32 versus a drain-source voltage Vds of the driver TFT. As shown in FIG. 6, controllers 34 and 36 undergo the on-off control in accordance with select signals applied to controllers 34 and 36, and thus, controllers 34 and 36 control top gate part 32 a and bottom gate part 32 b independently of each other. Accordingly, the drain-source current Ids can be controlled in four gray levels. In the present invention, the discrete current levels shown in FIG. 6 can be appropriately set to required levels by changing the area S2 of second gate electrode 14 of top gate part 32 a and area S1 of first gate electrode 12 of bottom gate part 32 b. FIGS. 7(a) to 7(d) are cross-sectional views in elevation illustrating a method of manufacturing a thin film transistor including driver TFT and the controllers of the present invention. A description will be given with regard to the embodiment shown in FIGS. 7(a) to 7(d), in which each of the controllers 34 and 36 is formed of a bottom gate TFT and the configuration shown in FIG. 4 is adopted. In a method of manufacturing driver TFT of the present invention, as shown in FIG. 7(a), first gate electrode 12 and gate electrodes 34 c and 36 c for the controllers are formed on insulating substrate 10 by means of sputtering, vacuum deposition and appropriate photolithography.
As shown in FIG. 7(b), first gate insulating film 16 is deposited on the resultant structure, and active layer 18 is deposited on the first gate insulating film by means of a method such as chemical vapor deposition using a material such as amorphous silicon, polycrystalline silicon or single-crystal silicon, and then the active layer is formed by means of appropriate photolithography.
In FIG. 7(c), source electrode 20 and drain electrode 22 are formed, and second gate insulating film 24 is deposited thereon, and then second gate electrode 14 is formed on the second gate insulating film. In the described embodiment of the present invention, in point of supplying high current levels with stability, it is preferable that second gate electrode 14 have a smaller area than first gate electrode 12 and that the second gate electrode extends longer than the length between the both ends of channel 26 defined as the length of active layer 18 between source electrode 20 and drain electrode 22.
Furthermore, as shown in FIG. 7(d), passivation layer 28 is deposited by means of, for example, chemical vapor deposition so as to coat the elements under the passivation layer. Thereafter, gate electrodes 34 c and 36 c of controllers 34 and 36 are connected to select signal lines 38 a and 38 b through contact holes 46 and 48, and then drain electrode 34 b and source electrode 36 a are connected to switching TFT 30 through contact holes 44 and 42.
Select signal lines 38 a and 38 b, and any other necessary wiring and the like can be formed by means of an appropriate method such as sputtering, vacuum deposition and a photolithography process. Any known deposition method and photolithography may be used in the above-mentioned process, or the photolithography process may take place through any procedure so long as the structure shown in FIG. 7(d) can be obtained.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5017983 *Aug 3, 1989May 21, 1991Industrial Technology Research InstituteAmorphous silicon thin film transistor with a depletion gateUS5140391 *Oct 19, 1990Aug 18, 1992Sony CorporationThin film MOS transistor having pair of gate electrodes opposing across semiconductor layerUS5808595 *Jun 28, 1996Sep 15, 1998Sharp Kabushiki KaishaThin-film transistor circuit and image displayUS6342717 *Feb 7, 2000Jan 29, 2002Sony CorporationSemiconductor device and method for producing sameJP2616153B2 Title not availableJP2000148087A Title not availableJP2000243963A Title not availableJP2000284750A Title not availableJP2000347624A Title not availableJPH08241997A Title not available* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7002181 *Jan 27, 2004Feb 21, 2006Toppoly Optoelectronics CorporationThin film transistor and use of sameUS7705817 *Apr 20, 2005Apr 27, 2010Samsung Electronics Co., Ltd.Organic light emitting diode display device and fabricating method thereofUS7880380Mar 7, 2008Feb 1, 2011Semiconductor Energy Laboratory Co., Ltd.Display device and electronic apparatusUS8917016Jan 20, 2011Dec 23, 2014Semiconductor Energy Laboratory Co., Ltd.Display device and electronic apparatusUS20140299852 *Dec 26, 2013Oct 9, 2014Everdisplay Optronics (Shanghai) LimitedOrganic electronic light emitting device and method of fabricating the same* Cited by examinerClassifications U.S. Classification257/365, 257/E21.415, 257/E29.275, 257/E27.111, 257/366, 257/E21.412International ClassificationH01L27/32, G09G3/32, H01L21/84, H01L27/12, H01L21/77, G09F9/00, H01L21/336, H01L29/786, G02F1/1368, G09F9/30, H01L51/50Cooperative ClassificationH01L27/124, H01L27/3244, G09G2300/0866, H01L29/66772, G09G2300/0814, G09G2300/0465, G09G2320/043, H01L29/6675, G09G2300/0842, G09G3/3233, G09G2300/0426, H01L29/78648European ClassificationH01L29/66M6T6F15A, H01L29/66M6T6F15C, H01L29/786D2, H01L27/12T, H01L29/786D, H01L27/12, G09G3/32A8CLegal EventsDateCodeEventDescriptionApr 3, 2014ASAssignmentOwner name: INNOLUX CORPORATION, TAIWANEffective date: 20121219Free format text: CHANGE OF NAME;ASSIGNOR:CHIMEI INNOLUX CORPORATION;REEL/FRAME:032604/0487Nov 14, 2011FPAYFee paymentYear of fee payment: 8Mar 8, 2011ASAssignmentFree format text: MERGER;ASSIGNOR:TPO DISPLAYS CORP.;REEL/FRAME:025919/0563Owner name: CHIMEI INNOLUX CORPORATION, TAIWANEffective date: 20100318Jan 23, 2011ASAssignmentOwner name: TPO DISPLAYS CORP., TAIWANEffective date: 20060605Free format text: CHANGE OF NAME;ASSIGNOR:TOPPOLY OPTOELECTRONICS CORP.;REEL/FRAME:025681/0260Nov 19, 2007REMIMaintenance fee reminder mailedNov 13, 2007FPAYFee paymentYear of fee payment: 4Jul 18, 2005ASAssignmentOwner name: TOPPOLY OPTOELECTRONICS CORPORATION, TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:016536/0563Effective date: 20050711Aug 15, 2002ASAssignmentOwner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, HIROSHI;TSUJIMURA, TAKATOSHI;REEL/FRAME:014096/0428Effective date: 20020806Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, HIROSHI;TSUJIMURA, TAKATOSHI;REEL/FRAME:013218/0119Effective date: 20020806Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION NEW ORFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, HIROSHI /AR;REEL/FRAME:014096/0428Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION NEW ORFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SUZUKI, HIROSHI /AR;REEL/FRAME:013218/0119RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services