Source: https://patents.justia.com/patent/8148822
Timestamp: 2020-06-05 04:15:44
Document Index: 440728758

Matched Legal Cases: ['application No. 60', 'application No. 60', 'Application No. 095127947', 'Application No. 095127948', 'Application No. 095127948', 'Application No. 095127947', 'Application No. 095127947']

US Patent for Bonding pad on IC substrate and method for making the same Patent (Patent # 8,148,822 issued April 3, 2012) - Justia Patents Search
Justia Patents At Least One Layer Of Molybdenum, Titanium, Or TungstenUS Patent for Bonding pad on IC substrate and method for making the same Patent (Patent # 8,148,822)
Bonding pad on IC substrate and method for making the same
May 17, 2006 - Megica Corporation
A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.
This application claims the benefits of U.S. provisional application No. 60/703,933, filed Jul. 29, 2005. This application also claims the benefits of U.S. provisional application No. 60/703,932, filed Jul. 29, 2005.
It is one object of the present invention to provide a novel multi-layer bonding pad or bump structure directly bonded to a copper pad or layer of an IC substrate, which is particularly compatible with standard wire bonding, tape automated bonding (TAB), chip-on-film (COF) bonding, or chip-on-glass (COG) bonding processes.
This invention pertains to the use of an embossing process to form a novel multi-layer bonding pad or bump structure directly bonded to a copper pad or aluminum layer of an IC substrate, which is particularly compatible with standard wire bonding, tape automated bonding (TAB), chip-on-film (COF) bonding, or chip-on-glass (COG) bonding processes.
The insulating layer surrounding the inlaid copper contact pad 12 includes, but not limited to, low-k (k<3.0) or ultra low-k (k<2.2) dielectric materials. By way of example, the aforesaid low-k dielectric materials may comprise SiLK™, Black Diamond™, polyarylene ether, polyarylene, polybenzoxazole, porous silicon oxide and spin-on dielectrics with a SiwCxOyHz composition.
The insulating layer surrounding the inlaid copper contact pad 12 may include low-k (k<3.0) or ultra low-k (k<2.2) dielectric materials. By way of example, the aforesaid low-k dielectric materials may comprise SiLK™, Black Diamond™, polyarylene ether, polyarylene, polybenzoxazole, porous silicon oxide and spin-on dielectrics with a SiwCxOyHz composition.
Inlaid copper contact pads 120a, 120b and 120c are formed at the top surface of the IC substrate 100. These inlaid copper contact pads are part of the top metal layer of the multilevel interconnection of the IC substrate 100 and is respectively electrically connected with the underlying integrated circuit. The inlaid copper contact pads 120a, 120band 120c may be formed by conventional damascene process generally including the step of etching a trench opening into an insulating layer, filling the trench opening with copper, and then removing excess copper outside the trench opening by using a conventional chemical mechanical polishing (CMP) process.
A passivation layer 140 covers the top surface of the IC substrate 100. The inlaid copper contact pads 120a, 120b and 120c are exposed by openings 160a, 160b and 160c respectively, which are formed in the passivation layer 140. Typically, the openings 160, 160b and 160c have a dimension of about 0.5-15 micrometers. In another case, the diameter of the openings 160,160b and 160c may range between 15 and 300 micrometers.
This preferred embodiment features the gold bonding structure 300a, gold pad-on-redistribution layer structure 300b and solder bump structure 300c, which are simultaneously fabricated on the IC substrate 100. The gold bonding structure 300a, gold pad-on-redistribution layer structure 300b and solder bump structure 300c are landed on the inlaid copper contact pads 120a, 120b and 120c, respectively.
The gold bonding structure 300b comprises an electrically conductive adhesion/barrier layer 180a that is directly bonded to the inlaid copper contact pad 120a and extends to the top surface of the passivation layer 140. The electrically conductive adhesion/barrier layer 180a, which contours the top surface of the passivation layer 140 and sidewalls of the opening 160a, seals the opening 160a and prevents the inlaid copper contact pad 120a from contacting with the air. Preferably, the electrically conductive adhesion/barrier layer 180a has a thickness ranging between 0.1 micrometer and 10 micrometers.
A first intermediate metal layer 132a is disposed on the electrically conductive adhesion/barrier layer 180a. According to this preferred embodiment, the first intermediate metal layer 132a is made of copper (>95% wt.). The first intermediate metal layer 132a has a thickness of about 0.1-10 micrometers. A second intermediate metal layer 122a is disposed on the first intermediate metal layer 132a. According to this preferred embodiment, the second intermediate metal layer 122a is made of nickel (>95% wt.). The second intermediate metal layer 122a has a thickness of about 0.1-10 micrometers. An electroless Au layer 190a is disposed on the second intermediate metal layer 122a. An Au bonding metal layer 200a is disposed on the electroless Au layer 190a.
The gold pad-on-redistribution layer structure 300b comprises an electrically conductive adhesion/barrier layer 180b that is directly bonded to the inlaid copper contact pad 120b and extends to the top surface of the passivation layer 140. The electrically conductive adhesion/barrier layer 180b, which contours the top surface of the passivation layer 140 and sidewalls of the opening 160b, seals the opening 160b and prevents the inlaid copper contact pad 120b from contacting with the air. Preferably, the electrically conductive adhesion/barrier layer 180b has a thickness ranging between 0.1 micrometer and 10 micrometers.
A first intermediate metal layer 132b is disposed on the electrically conductive adhesion/barrier layer 180b. The first intermediate metal layer 132b is made of copper (>95% wt.). The first intermediate metal layer 132b has a thickness of about 0.1-10 micrometers. A second intermediate metal layer 122b is disposed on the first intermediate metal layer 132b. The second intermediate metal layer 122b is made of nickel (>95% wt.). The second intermediate metal layer 122b has a thickness of about 0.1-10 micrometers. The electrically conductive adhesion/barrier layer 180b, first intermediate metal layer 132band second intermediate metal layer 122b constitute a redistribution trace layer 280, which is an additional metal path for electrical interconnect on which the connections from the original contact pad 120b is redistributed over the surface of the passivation layer 140. An Au bonding metal layer 200b is disposed on the other end of the redistribution trace layer 280. Likewise, an electroless Au layer 190a is interposed between the Au bonding metal layer 200b and the second intermediate metal layer 122b.
The solder bump structure 300c comprises an electrically conductive adhesion/barrier layer 180c that is directly bonded to the inlaid copper contact pad 120c and extends to the top surface of the passivation layer 140. The electrically conductive adhesion/barrier layer 180c, which contours the top surface of the passivation layer 140 and sidewalls of the opening 160c, seals the opening 160c and prevents the inlaid copper contact pad 120c from contacting with the air. Preferably, the electrically conductive adhesion/barrier layer 180c has a thickness ranging between 0.1 micrometer and 10 micrometers.
A first intermediate metal layer 132c is disposed on the electrically conductive adhesion/barrier layer 180c. According to this preferred embodiment, the first intermediate metal layer 132c is made of copper (>95% wt.). The first intermediate metal layer 132c has a thickness of about 0.1-10 micrometers. A second intermediate metal layer 122c is disposed on the first intermediate metal layer 132c. According to this preferred embodiment, the second intermediate metal layer 122c is made of nickel (>95% wt.). The second intermediate metal layer 122c has a thickness of about 0.1-10 micrometers. A solder bump or post 250 is disposed on the second intermediate metal layer 122c.
The solder bump or post 250 may be jointed as chip, substrate, passive component such as capacitor or resist, or photodiode sensor, solar cell, etc. Preferably, the solder bump or post 250 comprises SnPb, SnAg, SnAgCu or Sn alloys. The solder bump or post 250 can be re-flowed as jointed.
Inlaid copper contact pads 120a, 120b and 120c are formed at the top surface of the IC substrate 100. These inlaid copper contact pads are part of the top metal layer of the multilevel interconnection of the IC substrate 100 and is respectively electrically connected with the underlying integrated circuit. The inlaid copper contact pads 120a, 120b and 120c may be formed by conventional damascene process generally including the step of etching a trench opening into an insulating layer, filling the trench opening with copper, and then removing excess copper outside the trench opening by using a conventional chemical mechanical polishing (CMP) process.
A passivation layer 140 covers the top surface of the IC substrate 100. The inlaid copper contact pads 120a, 120b and 120c are exposed by openings 160a, 160b and 160c respectively, which are formed in the passivation layer 140. Typically, the openings 160, 160b and 160c have a dimension of about 0.5-15 micrometers. In another case, the diameter of the openings 160, 160b and 160c may range between 15 and 300 micrometers. The passivation layer 140 may comprise silicon oxide, silicon nitride, silicon oxy-nitride, and a combination thereof, for example, silicon oxide/silicon nitride (ON), silicon oxide/silicon nitride/silicon oxide (ONO), silicon oxy-nitride/silicon oxide/silicon nitride/silicon oxide, silicon oxide/silicon nitride/silicon oxy-nitride/silicon oxide, etc.
An electrically conductive adhesion/barrier layer 180 is blanket deposited over the IC substrate 100. The electrically conductive adhesion/barrier layer 180 is directly bonded to the inlaid copper contact pads 120a, 120b and 120c and extends to the top surface of the passivation layer 140. The electrically conductive adhesion/barrier layer 180 contours the top surface of the passivation layer 140 and sidewalls of the openings 160a, 160b and 160c and seals the openings 160a, 160b and 160c. Preferably, the electrically conductive adhesion/barrier layer 180a has a thickness ranging between 0.1 micrometer and 10 micrometers.
As shown in FIG. 10, a patterned photoresist layer 400 is formed on the electrically conductive adhesion/barrier layer 180. The patterned photoresist layer 400 is formed by conventional lithography methods generally including the steps of photoresist coating, baking, exposure and development. The photoresist may be a dry film. The patterned photoresist layer 400 has an opening 402a, opening 402b and opening 402c. The opening 402a is directly above the inlaid copper contact pad 120a. The opening 402b is directly above the inlaid copper contact pad 120b and defines a redistribution route. The opening 402c is directly above the inlaid copper contact pad 120c.
An electroplating process is carried out to plate copper layers 132a, 132b and 132c into the openings 402a, 402b and 402c, respectively. The thickness of the copper layers 132a, 132b and 132c ranges between 0.1 and 10 micrometers. In another case, the thickness of the copper layers 132a, 132b and 132c ranges between 10 and 250 micrometers. Subsequently, another electroplating process is carried out to plate nickel layers 122a, 122b and 122c into the openings 402a, 402b and 402c, respectively. As previously mentioned, the nickel layers 122a, 122b and 122c prevent surface oxidation of the underlying copper layer and it also acts as a strong barrier. The patterned photoresist layer 400 is then stripped off.
As shown in FIG. 11, another patterned photoresist layer 500 is formed on the IC substrate 100. The patterned photoresist layer 500 has an opening 502a that is directly above the inlaid copper contact pad 120a, and an opening 502b that is not directly above the inlaid copper contact pad 120b. The opening 502a exposes a top surface of the nickel layer 122a. The opening 502b exposes a pre-selected redistribution region of the nickel layer 122b. Electroless Au layers 190a and 190b are plated into the openings 502a and 502b, respectively. The electroless Au layers 190a and 190b are also optional. Thereafter, electroplating Au layers 200a and 200b are plated into the openings 502a and 502b, respectively. The patterned photoresist layer 500 is then removed.
As shown in FIG. 12, another patterned photoresist layer 600 is formed on the IC substrate 100. The patterned photoresist layer 600 has an opening 602c that is directly above the inlaid copper contact pad 120c and exposes a top surface of the nickel layer 122c. A solder bump 250 is formed on the exposed nickel layer 122c in the opening 602c. The patterned photoresist layer 600 is then removed.
As shown in FIG. 13, after removing the patterned photoresist layer 600, an etching process is performed to removed the exposed electrically conductive adhesion/barrier layer 180, thereby forming electrically conductive adhesion/barrier layers 180a, 180b and 180c.
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Patent number: 8148822
Patent Publication Number: 20070023919
Inventors: Mou-Shiung Lin (Hsin-Chu), Hsin-Jung Lo (Taipei County), Chiu-Ming Chou (Kaohsiung), Chien-Kang Chou (Tainan Hsien), Ke-Hung Chen (Kao-Hsiung)
Application Number: 11/383,762