Source: http://www.google.com/patents/US20030207572?dq=5,583,822
Timestamp: 2017-10-21 16:14:27
Document Index: 82442128

Matched Legal Cases: ['arts 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3', 'art 3']

Patent US20030207572 - Semiconductor device and its manufacturing method - Google Patents
The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor...http://www.google.com/patents/US20030207572?utm_source=gb-gplus-sharePatent US20030207572 - Semiconductor device and its manufacturing method
Publication number US20030207572 A1
Application number US 10/437,916
Also published as US6989334, US7247576, US7678706, US20060049499, US20070298545, WO1999049512A1
Publication number 10437916, 437916, US 2003/0207572 A1, US 2003/207572 A1, US 20030207572 A1, US 20030207572A1, US 2003207572 A1, US 2003207572A1, US-A1-20030207572, US-A1-2003207572, US2003/0207572A1, US2003/207572A1, US20030207572 A1, US20030207572A1, US2003207572 A1, US2003207572A1
Inventors Miyaki Yoshinori, Suzuki Hiromichi, Suzuki Kazunari, Nishita Takafumi, Ito Fujio, Tsubosaki Kunihiro, Kameoka Akihiko, Nishi Kunihiko
Original Assignee Miyaki Yoshinori, Suzuki Hiromichi, Suzuki Kazunari, Nishita Takafumi, Ito Fujio, Tsubosaki Kunihiro, Kameoka Akihiko, Nishi Kunihiko
Patent Citations (10), Referenced by (7), Classifications (73), Legal Events (7)
US 20030207572 A1
1. A semiconductor device sealing the die pad and a semiconductor chip mounted on it with a resin, characterized in that the main surface of the semiconductor chip is covered by an layer of organic material and an outward appearance of the die pad is smaller than that of the semiconductor chip.
2. A semiconductor device according to claim 1, characterized in that said layer of organic material is made of polyimide resins.
3. A semiconductor device according to claim 1, characterized in that said layer of organic material is made of photosensitive polyimide resins.
4. A semiconductor device according to claim 1, characterized in that a passivation film of the inorganic insulation materials is formed on the top layer of conductive wirings formed on the main surface of said semiconductor chip and said layer of organic material is formed on said passivation film.
5. A semiconductor device according to claim 4, characterized in that a bonding pad is formed by making an hole to said layer of organic material and said passivation film, and said bonding pad and a lead are electrically connected through a wire.
6. A semiconductor device according to claim 4, characterized in that said passivation film is composed of any one of silicon oxide film, silicon nitride film or those lamination films.
7. A semiconductor device according to claim 1, characterized in that said die pad comprises the Fe—Ni alloys or Cu.
8. A method for making a semiconductor device characterized by comprising steps of:
(a) making a passivation film of the inorganic insulation materials on a top layer of conductive wirings after forming the top layer of conductive wirings on the main surface of a semiconductor wafer, and then making an layer of organic material on said passivation film,
(f) sealing said semiconductor chip and said die pad by resin mold.
9. A method for making a semiconductor device according to claim 8, characterized in that said resist removal liquid includes the phenol system solvent as the main component.
10. A method for making a semiconductor device according to claim 8, characterized in that it is further provided between the step (c) and the step (d), thinning a thickness of said semiconductor wafer by grounding the back of said semiconductor wafer in the state that the main surface of said semiconductor wafer is covered with the second photo resist film and a protect tape and then heating said layer of organic material.
11. A method for making a semiconductor device, characterized by comprising the steps of:
(a) making a passivation film of the inorganic insulation materials on a top layer of conductive wirings after forming the top layer of conductive wirings on the main surface of a semiconductor wafer, and then making an photosensitive polyimide resin layer on said passivation film,
(b) making a hole to said photosensitive polyimide resin layer formed on said top layers of conductive wirings by exposing and developing said photosensitive polyimide resin layer,
(c) exposing a bonding pad by holing said passivation film formed on the said top layer of conductive wirings by etching method using said photosensitive polyimide resin layer having said hole as a mask,
(d) heating said photosensitive polyimide resin layer to the high temperature,
(e) making a semiconductor chip by dicing said semiconductor wafer,
(f) preparing a lead frame with a die pad with a outward appearance that is smaller than that of said semiconductor chip, and then mounting said semiconductor chip to said die pad,
(g) sealing said semiconductor chip and said die pad with resin.
12. A semiconductor device sealing a semiconductor chip, covering a passivation film of the inorganic insulation materials formed on a top of layer of conductive wirings with an layer of organic material, and a die pad, whose an outward appearance is smaller than that of said semiconductor chip and which is mounted on said semiconductor chip, characterized in that said layer of organic material and said resins make an interface in a main surface side of said semiconductor chip sealed by said resins, and that said semiconductor chip and said resins make an interface except of an area with which said semiconductor chip and said die pad in a back surface side of said semiconductor chip overlap.
13. A method of making a semiconductor device, characterized by comprising steps of:
(a) making a passivation film of the inorganic insulation materials on a top layer of conductive wirings after forming the top layer of conductive wirings on the main surface of a semiconductor wafer, and then covering said passivation film with said layer of organic material.
(b) ething a part of said layer of organic material by using a photo resist film as a mask,
(d) mounting, after separating said semiconductor wafer into a plurality of semiconductor chip, said semicondudtor chip on a die pad with an outer appearance which is smaller than that of said semiconductor chip, and then sealing said semiconductor chip and said die pad by resin mold.
14. A method for making a semiconductor device characterized by comprising steps of:
(a) making a passivation film of the inorganic insulation materials on a top layer of conductive wirings after forming the top layer of conductive wirings on the main surface of a semiconductor wafer, and then covering said passivation film with said layer of organic material,
(e) backing said layer of organic material after removing said second photo resist film by using a resist removal liquid,
(d) mounting, after separating said semiconductor wafer into a plurality of semiconductor chip, said semiconductor chip on a die pad of a lead frame with an outward appearance which is smaller than that of said semiconductor chip, and then sealing said semiconductor chip and said die pad by resin mold.
15. A method for making a semiconductor device according to claim 14, characterized in that the step (e) is performed at such a temperature that the bonding power between said layer of organic material and said resins is recovered.
16. A method for making a semiconductor device characterized by comprising steps of:
(c) removing said photo resist film by using a resist removal liqiud, and then grounding the back surface of said semiconductor wafer after covering said layer of organic materil with a second photo resist film,
(e) mounting, after separating said semiconductor wafer into a plurality of semiconductor chip, said semicondudtor chip on a die pad with an outer appearance which is smaller than that of said semiconductor chip, and then sealing said semiconductor chip and said die pad by resin mold.
17. A method for making a semiconductor device according to claim 16, characterized in that the step (d) is performed at such a temperature that the bonding power between said layer of organic material and said resins is recovered.
18. A method for making a semiconductor device, characterized by comprising steps of:
(a) making a passivation film of the inorganic insulation materials on a top layer of conductive wirings after forming the top layer of conductive wirings on the main surface of a semiconductor wafer, and then covering said passivation film with a photosensitive polyimide resin layer,
(c) baking said photosensitive polyimide resin layer,
19. A method for making a semiconductor device according to claim 18, characterized in that the step (c) is performed at such a temperature that the bonding power between said photosensitive polyimide resin layer and said resins is recovered.
20. A method for making a semiconductor device, characterized by comprising steps of:
(d) backing said photosensitive polyimide resin layer after removing said photo resist film by using a resist removal liquid,
21. A method for making a semiconductor device according to claim 20, characterized in that the step (d) is performed at such a temperature that the bonding power between said photosensitive polyimide resin layer and said resins is recovered.
The Japanese patent Laid-open No. Toku-Kai-Syou 63-204753 official gazette and the Japanese patent Laid-open No. Toku-Kai-Hei 6-216303 official gazette are proposing the lead frame structure that restrains an occurrence of a package crack, that is, they are proposing the lead frame structure which has the die pad whose outward appearance is smaller than that of the semiconductor chip mounted on it. According to this lead frame structure, an interface of a die pad and a resin becomes small, and the quantity of accumulated moisture also becomes small in the interface of them. And the occurrence of a package crack in the back vicinity of a die pad is restrained because a part of the back of a silicon wafer with good adhesion with a resin as compared with a lead frame comes to touch a resin and makes a direct interface. On the other hand, as for the side of the main surface (element formation surface) of a chip mounted on a die pad, the surface passivation film (final passivation film) formed to the top layer part of a chip contacts with the resin that constitute a package. This final passivation film is made of inorganic system insulation materials such as the silicon oxide film or the silicon nitride film that formed by the method of a CVD (CHEMICAL VAPOR DEPOSITION), and the adhesion strength with the resin that constitutes a package is larger than that of a lead frame (metal) and a resin.
(1) The semiconductor device of this invention is composed of the package that seals the die pad of a lead frame and a semiconductor chip mounted on it by resin, and coating the main surface of the above semiconductor chip with an layer of organic material, and the outward appearance of the above die pad was made smaller than the outward appearance of the above semiconductor chip.
(2) As for the semiconductor device of this invention, the layer of organic material of the foregoing (1) is composed of a polyimide resin.
(3) As for the semiconductor device of this invention, the layer of organic material of the foregoing (1) is composed of a photosensitive polyimide resin.
(4) As for the semiconductor device of this invention, the final passivation film that comprises the insulation materials of an inorganic system in the upper part of the top layer of conductive wirings formed on the main surface of the semiconductor chip of the foregoing (1) is formed, and the above layer of organic material is formed over the above final passivation film.
(5) As for the semiconductor device of this invention, a bonding pad is formed by holing the layer of organic material of the foregoing (4) and the above final passivation film, and this bonding pad and a lead of the above lead frame are electrically connected through a wire.
(6) As for the semiconductor device of this invention, the final passivation film of the foregoing (4) is composed of one of silicon oxide film, silicon nitride film or those lamination films.
(7) As for the semiconductor device of this invention, the lead frame of the foregoing (1) is composed of the Fe—Ni alloy or Cu.
(8)The method of manufacturing the semiconductor device of this invention includes the following steps.
(a) a step of forming the final passivation film that comprises the insulation materials of an inorganic system in the upper part of the top layer of conductive wirings after forming the top layer of conductive wirings on the main surface of a semiconductor wafer, and then an layer of organic material is formed over the above final passivation film.
(9) As for the method of manufacturing the semiconductor device of this invention, the resist removal liquid of a resist of the foregoing (8) includes the solvent of a phenol system as the main component.
(10) As for the method of manufacturing the semiconductor device of this invention, after above step of (c) and before above step of (d), further including a step of thinning the thickness of the above semiconductor wafer by grinding of the back in the condition that the main surface of the above semiconductor wafer is covered with the second photo resist film and a protect tape, and further a step of heating hotly the above layer of organic material after removing the above protect tape and the second photo resist film by using a resist removal liquid.
(11) The method of manufacturing the semiconductor device of this invention includes the following processes.
(a) a step of forming the final passivation film that comprises the insulation materials of an inorganic system in the upper part of the above top layer of conductive wirings after forming the top layer of conductive wirings on the main. surface of a semiconductor wafer, and then a photosensitive polyimide resin layer is formed over the above final passivation film.
[0035]FIG. 1 is the perspective view of TQFP that is one embodiment of this invention.
[0036]FIG. 2 is the cross-sectional view of TQFP that is one embodiment of this invention.
[0037]FIG. 3 is the cross-sectional view of a semiconductor chip sealed to TQFP that is one embodiment of this invention.
[0038]FIG. 4 is the main part cross-sectional view of the semiconductor wafer that shows a method of manufacturing TQFP that is one embodiment of this invention.
[0039]FIG. 5 is the main part cross-sectional view of the semiconductor wafer that shows a method of manufacturing TQFP that is one embodiment of this invention.
[0040]FIG. 6 is the main part cross-sectional view of the semiconductor wafer that shows a method of manufacturing TQFP that is one embodiment of this invention.
[0041]FIG. 7 is the main part cross-sectional view of the semiconductor wafer that shows a method of manufacturing TQFP that is one embodiment of this invention.
[0042]FIG. 8 is the explanation figure that shows the back grinding process of a semiconductor wafer.
[0043]FIG. 9 is the explanation figure that shows dicing process of a semiconductor wafer.
[0044]FIG. 10 is the main part plan view of the lead frame that is used for manufacturing of TQFP that is one embodiment of this invention.
[0045]FIG. 11 is the explanation figure that shows the process that mounts a semiconductor chip on a die pad.
[0046]FIG. 12 is the explanation figure that shows the process that mounts a semiconductor chip on a die pad.
[0047]FIG. 13 is the explanation figure that shows the process that mounts a semiconductor chip on a die pad.
[0048]FIG. 14 is the flow diagram that shows the manufacturing process of TQFP that is one embodiment of this invention.
[0049]FIG. 15 is the flow diagram that shows the manufacturing process of TQFP that is the other embodiment of this invention.
[0050]FIG. 16 is the flow diagram that shows the manufacturing process of TQFP that is the other embodiment of this invention.
[0051]FIG. 17 is the flow diagram that shows the manufacturing process of TQFP that is the other embodiment of this invention.
[0054]FIG. 1 is the perspective view of TQFP(THIN QUAD FLAT PACKAGE) of which one embodiment of this invention.
[0055]FIG. 2 is the cross-sectional view of this TQFP.
[0056]FIG. 3 is the enlarged sectional view of a semiconductor chip sealed to this TQFP.
A plurality of the one end parts (inner lead parts 3A) of leads 3 which composes the external connection terminal of TQFP are arranged in the periphery of above semiconductor chip 2. Leads 3 comprises the Fe—Ni alloys such as 42 alloys or Cu. Inner leads part 3A is electrically connected with semiconductor chip 2 through wires 4 made of Au and Al, etc..
[0068]FIG. 4 is the cross-sectional view that shows the main part (about one chip) of semiconductor wafer 2A that deposits final passivation film 7 on the upper part of the top layer of conductive wirings 6 for example are formed by the method of patterning Al alloy film deposited on semiconductor wafer 2A by sputtering method. And, final passivation film 7 for example is formed by depositing a silicon oxide film or a silicon nitride film on semiconductor wafer 2A by the CVD method.
Then, given semiconductor chip 2 is mounted on a lead frame. As it is shown in FIG. 10, circular die pad 5 that mounts semiconductor chip 2 on the central part of lead frame LF is supported by suspension leads 16 of 4 pieces. As described above, a remarkable point is that the size of this die pad 5 is smaller than the size of semiconductor chip 2 that is mounted on it. it is arranged to the periphery of above die pad 5 so that the die pad 5 is surrounded by a plurality of leads 3, and it is formed to the halfway part of each leads 3 so that dam bar 17 that served as support of leads 3 and prevention of overflow of a resin at the time of molding connects leads 3 each other. As for leads 3, the inside part of this dam bar 17 composes inner leads part 3A, and outer leads part 3B is composed of the outside part. And, plating of Ag/Ni is done on the tip (bonding area) of inner leads part 3A. External frame 18 and inside frame 19 are formed to most outward part of lead frame LF, and guide hole 20 that becomes a guide at the time of the positioning to the molded die assembly of lead frame LF is formed to part of external frame 18. And, while actual lead frame LF becomes matrix structure on which 5˜6 semiconductor chips 2 can be mounted, the figure is shown only one chip area (unit frame).
Above die pad 5, suspension leads 16, leads 3, dam bar 17, external frame 18 and inside frame 19 that constitute lead frame LF are formed by manufacture of press working or etching of the hoop material of thickness of sheet 0.15 mm that comprises 42 alloys and Cu, etc.. And, in case above each part of lead frame LF is formed by press working, burr (BURR) occurs on the side of the back of a cutting place. A semiconductor chip 2 cannot be bonded when a burr forms in the periphery of die pad 5 because this lead frame LF is composed of the die pad 5 which has the area smaller than the area of semiconductor chip 2 mounted on that. Therefore, a burr is made to form in the other side of a chip mounting surface by turning a chip mounting surface to an upper part when pressing die pad 5 and punching it from the upper part to downward. On the other hand, as for a wire, when there is a burr in the under side, it is hard to bond the tip of inner lead part 3A at the time of wire bonding, and the bonding inferior sometimes arises. Therefore, when pressing inner lead part 3A, a bonding surface is turned to upside down and is punched from the upper part to downward, and a burr is made to the wire bonding surface side.
(moisture-absorption condition: 85° C./85% RH
Moisture- an layer of
Absorption organic Chip surface
time material Chip size exfoliation Crack
24 hours P (high- 6.48 × 6.66 0/45 0/45
48 hours P (high- 6.48 × 6.66 0/45 0/45
24 hours Absence 6.38 × 8.38 45/45 2/45
48 hours Absence 6.38 × 8.38 40/40 1/40
US5885852 * Apr 28, 1997 Mar 23, 1999 Hitachi, Ltd. Packaged semiconductor device having a flange at its side surface and its manufacturing method
CN105321812A * Jun 17, 2015 Feb 10, 2016 株式会社东芝 Semiconductor package and method of manufacturing same
U.S. Classification 438/689, 257/E23.04, 257/E23.037
Cooperative Classification H01L2224/02166, H01L2224/32055, H01L2224/45144, H01L2224/45124, H01L24/45, H01L2924/181, H01L2924/00014, H01L24/48, H01L24/32, H01L24/29, H01L2924/0132, H01L21/56, H01L2224/48465, H01L2224/743, H01L2924/01006, H01L2224/48091, H01L2924/01013, H01L2224/29007, H01L2924/07802, H01L2924/01047, H01L2924/1433, H01L24/28, H01L2224/29339, H01L2224/32245, H01L24/743, H01L23/49513, H01L2924/01029, H01L2924/01079, H01L2924/0665, H01L2924/01015, H01L2224/274, H01L2924/01005, H01L24/83, H01L24/85, H01L2924/014, H01L2224/2919, H01L2224/83192, H01L2924/01045, H01L2224/97, H01L23/562, H01L23/3171, H01L2224/83855, H01L2224/92, H01L23/3192, H01L24/27, H01L2224/92247, H01L2224/32014, H01L2924/01082, H01L23/49503, H01L2224/73265, H01L23/3142, H01L2224/48247, H01L2924/12044, H01L2924/01033, H01L2924/01078, H01L2224/85, H01L2924/10253
European Classification H01L24/31, H01L21/56, H01L23/31H6, H01L23/31P12, H01L23/31P6, H01L24/27, H01L24/743, H01L23/562, H01L24/83, H01L23/495A, H01L23/495A6
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MIYAKI, YOSHINORI;SUZUKI, HIROMICHI;SUZUKI, KAZUNARI;AND OTHERS;REEL/FRAME:022892/0454