Source: https://patents.google.com/patent/US20070076508A1/en
Timestamp: 2018-11-14 05:25:34
Document Index: 430320108

Matched Legal Cases: ['art 20', 'art 20', 'art 20', 'art 20', 'art 20', 'art 20']

US20070076508A1 - Semiconductor memory chip - Google Patents
US20070076508A1
US20070076508A1 US11242150 US24215005A US2007076508A1 US 20070076508 A1 US20070076508 A1 US 20070076508A1 US 11242150 US11242150 US 11242150 US 24215005 A US24215005 A US 24215005A US 2007076508 A1 US2007076508 A1 US 2007076508A1
US11242150
US7221615B2 (en )
The reception interface section can further include a CRC-bit decoder for evaluating CRC-bits within the signal frames and checking correctness/incorrectness of commands and data in each signal frame, and the frame decoder can further include a wrong command protection unit for releasing to the memory core only commands checked by the CRC-bit decoder as being correct.
The frame decoder 10 receives frame data fdata from the reception interface section 50 and system information and timing parameters smrs from a system mode register SMR (not shown) and is adapted for decoding one or more commands included in one or more frames and outputting in accordance with each decoded frame data, address and command signals as well as control signals S1 forming a read/write access indication to the memory core 30. Further, the frame decoder 10 supplies write data, IDB address signals and activate signals S2 to the intermediate data buffer 20. Write data signals intermediately stored in the IDB 20 and, optionally, write data mask bits are supplied as signals S3 from the IDB 20 to the memory core 30. The operation of the blocks 10, 20 and the transfer of the signals S1, S2 and S3 are synchronous to a frame clock signal clk_frd. It is, however, to be noted that the reading of the system information and timing parameters from the SMR is an optional solution. Such values can also be delivered within the frame accompanying the normal command addresses.
The manner of CRC-bit evaluation by the CRC-bit decoder 11 and other system commands are not part of the novelty of the present invention and are therefore not discussed here in detail because this does not affect the principle functionality. Likewise, the widths of the busses carrying f data and the signal streams S1, S2 and S3 are not critical to the present invention.
Main functional blocks of the frame decoder 10 depicted in FIG. 2 are a command type decoding section 1 arranged for decoding the types of one or more commands included in one or more frames and outputting control signals according to each decoded command type. As shown in FIG. 2, these control signals include a group-, bank-, column- and row addresses to the memory core 30 concerning data and commands relevant for the core, dual commands to the memory core and to IDB 20, IDB relevant commands and write data. The control signals and data and command signals relevant for the memory core 30 as well as the dual commands to the memory core are supplied from the command type decoding section 1 to a memory command evaluator/generator section 2, while the IDB relevant commands and data signals are supplied from the command type decoding section 1 to an intermediate data buffer command evaluator/generator section 3, and system relevant commands are supplied from the command type decoding section 1 to a system command evaluator/generator section 4.
The memory command evaluator/generator section 2 is arranged for scheduling and preparing of single commands to the memory core 30 and includes a buffer 2 a implementing the delay action of the block DEL in FIG. 1. The memory command evaluator/generator section 2 supplies to the memory core 30 data and indication signals of read/write access as well as group-, row-, column- and bank select signals.
The intermediate data buffer command evaluator/generator section 3 is arranged for scheduling and preparing of control signals as well as data to the IDB 20 (IDB data-, address-and activation signals).
The system command evaluator/generator section 4 is arranged for preparing and scheduling of system commands relevant for system management, for example access to the system mode register SMR (not shown) or power down action. It is to be mentioned that idle command frames do not require further action. Within the command type decoding section 1, the memory command evaluator/generator section 2, the intermediate data buffer command evaluator/generator section 3, and the system command evaluator/generator section 4 the frame data are processed in such a way that externally no greater control logic is necessary. For the memory command evaluator/generator section 2, the intermediate data buffer command evaluator/generator section 3 and the system command evaluator/generator section 4, this means that their output is aligned to the frame clock signal clk_frd and has the correct timing considering all relevant memory restrictions.
FIG. 3 shows a plan view representation of an exemplary embodiment of the present semiconductor memory chip which includes the arrangement within the chips area of a plurality of memory banks of the memory core 30, the frame decoder 10 and the intermediate data buffer 20. In the presently preferred embodiment shown in FIG. 3, 16 memory banks are divided into two groups, upper Group 0 and lower Group 1 (upper and lower memory bank sections). Each bank is split into two parts, namely, a left part A and a right part B. The intermediate data buffer 20 is physically divided into two parts, namely, a left part 20A and a right part 20B, according to the split bank topology. For each write access to the IDB 20A, 20B, the write data are split into two parts and written concurrently by the frame decoder 10 to the left IDB 20A and the right IDB 20B. Also, the control signals S2 (FIG. 1) from the frame decoder 10 to the IDB must be doubled up for left and right (left part S2A and right part S2B of the control signals). Write access to the banks (read from the IDBs parts) also utilizes the left part 20A and the right part 20B of the IDB 20. The separation between the upper and lower groups (Group 0 and Group 1) of the memory banks has to be considered by the control logic 2 (signals S1A, S1B, S3A (GR0), S3A (GR1), S3B (GR0) and S3B (GR1)). Synchronized by the frame clock signal clk frd, the interface to the memory banks formed by the frame decoder 10 and the left part 20A and the right part 20B of the IDB 20 is kept in a fully synchronous manner.
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Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WALLNER, PAUL;STREIBL, MARTIN;MENKE, MANFRED;AND OTHERS;REEL/FRAME:016842/0001;SIGNING DATES FROM 20051020 TO 20051108