Source: http://www.google.com/patents/US6816410?dq=5,825,352
Timestamp: 2015-07-29 19:05:33
Document Index: 736524739

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US6816410 - Method for programming a three-dimensional memory array incorporating serial ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction...http://www.google.com/patents/US6816410?utm_source=gb-gplus-sharePatent US6816410 - Method for programming a three-dimensional memory array incorporating serial chain diode stackAdvanced Patent SearchPublication numberUS6816410 B2Publication typeGrantApplication numberUS 10/809,146Publication dateNov 9, 2004Filing dateMar 25, 2004Priority dateApr 28, 2000Fee statusLapsedAlso published asUS6631085, US6754102, US6767816, US6784517, US20030022420, US20030027378, US20030031067, US20030053332, US20040179398Publication number10809146, 809146, US 6816410 B2, US 6816410B2, US-B2-6816410, US6816410 B2, US6816410B2InventorsBendik Kleveland, Roy E. ScheuerleinOriginal AssigneeMatrix Semiconductor, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (2), Referenced by (34), Classifications (47), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMethod for programming a three-dimensional memory array incorporating serial chain diode stack
US 6816410 B2Abstract
This application is a divisional of Prior application Ser. No. 10/253,074 filed Sep. 24, 2002 now U.S. Pat. No. 6,754,102, which is a divisional of application Ser. No. 09/897,705 filed Jun. 29, 2001 now U.S. Pat. No. 6,631,085, which is a continuation-in-part of U.S. application Ser. No. 09/814,727 filed Mar. 21, 2001 now U.S. Pat. No. 6,420,215, which is a continuation-in-part of U.S. application Ser. No. 09/560,626 filed Apr. 28, 2000 now abandoned; each of which applications is hereby incorporated by reference; and which application Ser. No. 09/897,705 now U.S. Pat. No. 6,631,085 also claims the benefit of the following U.S. provisional applications: U.S. Provisional Application No. 60/277,794 filed on Mar. 21, 2001; U.S. Provisional Application No. 60/277,815 filed on Mar. 21, 2001; and U.S. Provisional Application No. 60/277,738 filed on Mar. 21, 2001; each of which provisional applications is also hereby incorporated by reference.
Another way of fabricating three-dimensional memory arrays departs from the structures shown in these patents and uses “rail-stacks” as described in U.S. patent application Ser. No. 09/560,626 by N. Johan Knall, filed Apr. 28, 2000, which application describes a memory employing antifuses where a diode is formed upon programming a particular bit. In this connection see, “A Novel High-Density Low-Cost Diode Programmable Read Only Memory,” by de Graaf, Woerlee, AHart, Lifka, de Vreede, Janssen, Sluijs and Paulzen, IEDM-96, beginning at page 189 and U.S. Pat. Nos. 4,876,220; 4,881,114 and 4,543,594.
Turning now to FIG. 2, a diagram illustrating a section of a multi-level memory array 22 having bit lines B2 and B4 and word lines W3 and W5 is shown. Memory array 22 uses back-to-back diodes. In the diagram of FIG. 2, the designation “u” after a bit line or word line designation means that the corresponding bit line or word line is unselected. The designation “s” after a bit line or word line designation means that the corresponding bit line or word line is selected. In FIG. 2 the highlighted word line W3s and bit line B4s are selected. Thus by driving W3s high relative to B4s it is possible to program cell 24 so that it conducts from W3s to B4s. For simplification, only a diode and not an antifuse is shown at the selected cell, as once programmed, the cell acts like a diode. When driving W3s high it is also possible to program all of the other cells coupled to W3s, eg, cells 26 and 28. Thus, to avoid programming these cells, the corresponding bit lines should be biased to a level which precludes programming the cells. For example, making the bias on bit line 30 comparable to the bias on word line W3s will prevent cell 26 from programming. Similarly, making the bias on bit line 32 comparable to that of W3s will prevent cell 28 from programming. On the other hand, unselected word lines, W3u, must be kept relatively low in order to avoid accidentally reading or writing other cells connected to bit line B4s. Likewise, the unselected bit lines, B4u, must be kept relatively high in order to avoid accidentally reading or writing other cells connected to word line W3s. Hence, all of the unselected cells in the plane W3-B4 will be reverse-biased. Moreover, in order to avoid accidentally reading or writing cells in the plane B4-W5, all of the word lines W5u must be biased low. It is therefore clear that the unselected memory cells in plane W3-B4 as well as the unselected memory cells in the plane B2-W3 and the unselected memory cells in the plane B4-W5 are reverse-biased. Hence, for an array having N�N memory cells in each plane, approximately 3N2 memory cells are reverse-biased. Such leakage currents are described in greater detail and preferred bias voltages of the unselected word lines and bit lines are set forth in “Method and Apparatus for Biasing Selected and Unselected Array Lines When Writing a Memory Array” by Roy E. Scheuerlein, U.S. patent application Ser. No. 09/897,771, filed Jun. 29, 2001, and is hereby incorporated by reference.
In order to drive the selected word line 46 both high and low for the serial chain diode stack illustrated in FIG. 4, the driver circuit of FIG. 7A can be modified to that shown in FIG. 8. (Either word line driver circuit shown in FIG. 7A and FIG. 7B may be used, but only the circuit of FIG. 7A is shown in FIG. 8.) The FORWARD signal on line 48 will be set to forward bias the selected cell, whether the word line 46 connects to the cell above or below the word line. When the selected word line is to be driven high, and FORWARD is high, the word line is connected to Vhigh, and the unselected word lines are connected to Vbiaslow, as is the case in FIG.8. However, when the selected word line is to be driven low, the word line is connected to Vlow, and the unselected word lines are connected to Vbiashigh. The new ‘high-plane’ 50 and ‘low-plane’ 52 cells as well as the row select mux 54 are therefore additional circuits that are required by the serial chain diode stack.
Preferably, the memory cells are comprised of semiconductor materials, as described in U.S. Pat. No. 6,034,882 to Johnson et al., U.S. Pat. No. 5,835,396 to Zhang, U.S. patent application Ser. No. 09/560,626 by Knall, and U.S. patent application Ser. No. 09/638,428 by Johnson, each of which are hereby incorporated by reference. Specifically an antifuse memory cell is preferred. Other types of memory arrays that are, stackable over support circuits, such as MRAM and organic passive element arrays, can also be used. MRAM (magnetoresistive random access memory) is based on magnetic memory elements, such as a magnetic tunnel junction (MTJ). MRAM technology is described in “A 2556kb 3.0V ITIMTJ Nonvolatile Magnetoresistive RAM” by Peter K. Naji et al., published in the Digest of Technical Papers of the 2001 IEEE International Solid-State Circuits Conference, ISSCC 2001/Session 7/Technology Directions: Advanced Technologies/7.6, Feb. 6, 2001 and pages 94-95, 404-405 of ISSCC 2001 Visual Supplement, both of which are hereby incorporated by reference. Certain passive element memory cells incorporate layers of organic materials including at least one layer that has a diode-like characteristic conduction and at least one organic material that changes conductivity with the application of an electric field. U.S. Pat. No. 6,055,180 to Gudensen et al. describes organic passive element arrays and is also hereby incorporated by reference. Memory cells comprising materials such as phase-change materials and amorphous solids can also be used. See U.S. Pat. No. 5,751,012 to Wolstenholme et al. and U.S. Pat. No. 4,646,266 to Ovshinsky et al., both of which are hereby incorporated by reference.
On Mar. 21, 2001, the following U.S. patent applications were filed, each of which is hereby incorporated by reference: “Memory Device with Row and Column Decoder Circuits Arranged in a Checkerboard Pattern under a Plurality of Memory Arrays,” U.S. Provisional Application No. 60/277,794; “Passive Element Memory Array and Related Circuits Useful Therefor,” U.S. Provisional Application No. 60/277,815; “Tree-Dimensional Memory Array,” U.S. Provisional Application No. 60/277,738; and “Three-Dimensional Memory Array and Method of Fabrication,” U.S. application Ser. No. 09/814,727.
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regulating technique to enable data operations on large cross-point memory arrays with resistive memory elementsUS8937292Aug 15, 2011Jan 20, 2015Unity Semiconductor CorporationVertical cross point arrays for ultra high density memory applicationsUS20050030810 *Aug 6, 2004Feb 10, 2005Shepard Daniel RobertSCR matrix storage deviceCN100524511CJul 7, 2006Aug 5, 2009精工爱普生株式会社Ferroelectric random access memory device, display drive IC and electronic equipment* Cited by examinerClassifications U.S. Classification365/185.03, 257/E27.026, 365/185.28, 365/185.27, 365/63, 365/61, 365/175, 257/E27.073International ClassificationG11C5/02, G11C8/10, G11C7/06, G11C8/08, G11C17/18, H01L27/102, G11C7/18, H01L27/06Cooperative ClassificationG11C8/08, G11C13/0004, G11C13/0014, G11C5/025, G11C17/16, G11C7/062, G11C13/0028, G11C7/18, G11C8/10, G11C2207/063, G11C2213/71, H01L27/1021, H01L27/0688, G11C2213/72, G11C17/18, B82Y10/00, G11C17/165, G11C7/067European ClassificationG11C13/00R25A4, B82Y10/00, G11C13/00R5C, G11C17/16R, G11C7/06C, G11C5/02S, G11C7/18, H01L27/06E, G11C17/18, G11C8/08, G11C7/06S, H01L27/102D, G11C8/10Legal EventsDateCodeEventDescriptionApr 28, 2006ASAssignmentOwner name: SANDISK 3D LLC,CALIFORNIAFree format text: MERGER;ASSIGNOR:MATRIX SEMICONDUCTOR, INC.;REEL/FRAME:017544/0769Effective date: 20051020Mar 2, 2007ASAssignmentOwner name: SANDISK 3D LLC,CALIFORNIAFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTIVE MERGER TO ADD PAGES TO THE MERGER DOCUMENT PREVIOUSLY RECORDED PREVIOUSLY RECORDED ON REEL 017544 FRAME 0769. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:MATRIX SEMICONDUCTOR, INC.;REEL/FRAME:018950/0686Effective date: 20051020Owner name: SANDISK 3D LLC, CALIFORNIAFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECTIVE MERGER TO ADD PAGES TO THE MERGER DOCUMENT PREVIOUSLY RECORDED PREVIOUSLY RECORDED ON REEL 017544 FRAME 0769. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:MATRIX SEMICONDUCTOR, INC.;REEL/FRAME:018950/0686Effective date: 20051020May 19, 2008REMIMaintenance fee reminder mailedNov 9, 2008LAPSLapse for failure to pay maintenance feesDec 30, 2008FPExpired due to failure to pay maintenance feeEffective date: 20081109RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services