Source: http://www.google.com/patents/US7657856?dq=5,915,131
Timestamp: 2016-10-21 18:33:38
Document Index: 699453283

Matched Legal Cases: ['art 1', 'art 10', 'art 11', 'art 12', 'art 13', 'art 14', 'art 2', 'art 3', 'art 4', 'art 5', 'art 6', 'art 7', 'art 8', 'art 9']

Patent US7657856 - Method and system for parallel processing of IC design layouts - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsDisclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed...http://www.google.com/patents/US7657856?utm_source=gb-gplus-sharePatent US7657856 - Method and system for parallel processing of IC design layoutsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7657856 B1Publication typeGrantApplication numberUS 11/520,487Publication dateFeb 2, 2010Priority dateSep 12, 2006Fee statusLapsedPublication number11520487, 520487, US 7657856 B1, US 7657856B1, US-B1-7657856, US7657856 B1, US7657856B1InventorsMathew Koshy, Roland Ruehl, Min Cao, Li-Ling Ma, Eitan Cadouri, Tianhao ZhangOriginal AssigneeCadence Design Systems, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (68), Non-Patent Citations (50), Referenced by (8), Classifications (5), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod and system for parallel processing of IC design layouts
US 7657856 B1Abstract
Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.
The invention relates to the design and manufacture of integrated circuits, and more particularly, to systems and methods for performing physical verification during the circuit design process.
There are, however, significant obstacles for EDA vendors that wish to implement a parallel processing solution for IC layouts. Consider an example parallel processing approach in which an EDA tool geometrically divides an IC layout into multiple areas/portions and independently processes each portion using a different CPU. Such an approach is shown in FIG. 1 in which an example IC layout 107 has been divided into multiple geometric layout areas/portions 107 a, 107 b, 107 c, and 107 d. For PV processing, each layout portion 107 a, 107 b, 107 c, and 107 d may be processed for DRC correctness using a separate processor or CPU. Polygon 101 is located on a first layer and extends across all four layout portions 107 a-d. Polygon 103 a-d all reside on a second layer. Polygon 103 a is located in layout portion 107 a. Polygon 103 b is located in layout portion 107 b. Polygon 103 c is located in layout portion 107 c. Polygon 103 d is located in layout portion 107 d. Consider further if the PV tool needs to perform geometric operations across multiple layout portions. An example of a geometric operation that is commonly performed by PV tool is the “polyEnclose” operation that selects polygons on a first layer (layerA) that enclose polygons on a second layer (layerB). This operation may be performed with count-based select to identify polygons on the first layer that enclose a specific number of polygons on the second layer.
Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. An example of an EDA layout processing tool is a physical verification (PV) tool. To illustrate embodiments of the invention, the below description is made with respect to parallelism for PV tools. It is noted, however, that the present invention is not limited to PV tools, and may also be applied to other types of EDA layout processing tools.
In one approach, the IC layout is divided into a plurality of layout “windows”. A layout window is an area of the design layout assigned to an individual processing entity. A window by itself is a hierarchical layout with multiple layers. Shapes that touch the window boundary are cut into pieces along the window boundary. The pieces inside the boundary remain within the window layout. A design hierarchy has cell masters and cell instances, which are translations and/or rotations of the cell master. When a cell instance intersects a window boundary, a new master inside the window is generated that completes the hierarchy of the window's layout. Given a homogenous network of computers (i.e. each CPU has the same speed), window-based parallelism is implemented by mapping multiple windows to separate CPUs, where each window may be processed concurrently.
A high-level description of windows-based parallelism will now be described. FIG. 2A provides a high-level illustration of windows-based parallelism, in which parallelism is provided by dividing an IC layout 102 into a plurality of two-dimensional (2D) “windows” 104. Some or all of the different windows 104 may be processed by the EDA tool in parallel by different processing entities 106. Examples of such processing entities include processes, threads, tasks, CPUs, nodes, and/or networked computing stations.
A design hierarchy has cell masters and cell instances (linear transformations and translations of the master). When a window overlaps instances of a cell master, a new master inside the window is generated that completes the hierarchy of the window's layout. In some embodiments, two approaches are used to deal with cells and instances that intersect the window boundary. In the first approach, all shapes of the intersecting cell/instance are “promoted” to the top-level of the hierarchy, i.e., the instance disappears and shapes inside the window are “flattened”. In the second approach, a new cell (a “variant”, i.e., a modified copy of the original instance) is created and stored in the design hierarchy instead of the original cell/instance. In yet another approach, the layout is partially flattened, in which only a portion of the hierarchy is promoted to a higher level of the hierarchy or only a portion of the hierarchy is flattened.
Returning back to FIG. 3, once the windows have been suitably configured and interactions between windows have been addressed, some or all of the windows are processed in parallel to perform the EDA operations upon the layout (306). As noted above, each processing entity may receive one or more of the layout windows for processing. In one embodiment, a “lazy scheduling” approach is taken to assigning operations to processing entities. In this approach, the most computationally difficult jobs are assigned to the most powerful processing entities. As described in more detail below, sampling can be performed to help identify the most computationally difficult operations.
In addition, the type and/or quantity of certain structures within the window may affect the performance of processing for that window. The identification of certain types or quantities of structures within a window that will affect performance is very dependent upon the specific EDA tool operation that is being performed. For example, some types of processing, such as certain kinds of DRC rules checking, are dependent upon the density of structures within a given layout area. Therefore, all else being equal, windows having greater instance densities will be slower to process for these types of DRC verification than for other windows having smaller instance densities. Other examples include certain DRC rules that relate specifically to pattern density. Therefore, for these pattern density-related rules, windows having greater pattern densities will be slower to process for these types of DRC verification than for other windows having smaller pattern densities. The next action is to check or predict the expected performance of the processing system based upon the set of layout windows that have been identified (404). As described below, “sampling” can be used to provide performed estimation. If the expected performance meets the desired performance level (406), then the processing system continues with parallel execution of the identified layout windows (410).
Six common geometrical select operations for PV tools are referred to herein as the “polyInside”, “polyOutside”, “polyCut”, “polyTouch”, “polyInteract”, and “polyEnclose” operations.
1. An initial local regioning graph is formed by computing the initial node list and edge list based on the select phase one result in the current window and its direct neighbor windows. This step is referred to as “local regioning”. 2. A global regioning graph is computed by performing the synchronized global communication to aggregate the graph in each window. This step is referred to as “global regioning”.
FIG. 12B shows the result of performing local regioning on the example layout of FIG. 12A. Each window corresponds to a data structure containing the polygons or portions of polygons on layer A that reside in that window. Furthermore, the data structures track the correspondence of those polygon portions (referred to herein as “nodes”) that extend to neighboring windows. Finally, the flag value is set for the window based upon the geometric select operation performed within that window.
Here, it can be seen that window win(0,0) includes two nodes 1 and 9 of the polygon 1204. The figure graphically shows that these nodes 1 and 9 reside in the window win(0,0) and further that these nodes correspond to portions in other windows. In particular, symbol 1206 identifies the correspondence between node 1 in window win(0,0) and node 2 in neighboring window win(1,0). Similarly, symbol 1208 identifies the correspondence between node 9 in window win(0,0) and node 8 in neighboring window win(0,1). The flag for each of these nodes is set to “0”, indicating that none of these portions correspond to the condition for the polyInteract operation, i.e., none of these nodes interact or overlap with a polygon from layer B based upon a local select operation.
This type of information is similarly established for each of the windows. In window win(1,0), symbol 1210 illustrates that node 2 is contained in that window, and further that node 2 corresponds to node 1 in left neighboring window win(0,0) and node 3 in right neighboring window win(2,0). The flag values for these nodes are set to “0”, indicating that none of these nodes interact or overlap with a polygon from layer B. Symbols 1222, 1220, 1218 provide similar information for the contents windows win(0,1), win(0,2), and win(1,2), respectively.
In window win(2,1), symbol 1214 illustrates that node 4 is contained in the window, and further that node 4 corresponds to node 3 in lower neighboring window win(2,0) and node 5 in upper neighboring window win(2,2). It is noted that the flag value for node 4 is set to “1”, indicating that this node interact or overlap with a polygon from layer B as satisfying the selection condition for the polyInteract operation for a local select operation. This can be seen in the layout illustration of FIG. 12A, in which portion 4 of polygon 1204 on layer A intersects with polygon 1202 of layer B in window win(2,1).
In window win(2,0), symbol 1212 illustrates that node 3 is contained in that window, and further that node 3 corresponds to node 2 in left neighboring window win(1,0) as well as node 4 in upper neighboring window win(2,1). The flag values for node 3 is set to “0”, indicating that this node does not interact or overlap with a polygon from layer B based upon a local select operation. However, it can be seen that the flag value for node 4 is set to “1”, indicating that node 4 from upper neighboring window win(2,1) does satisfy the selection condition for the polyInteract operation. Similarly, in window win(2,2), symbol 1216 illustrates that node 5 is contained in that window, and further that node 5 corresponds to node 6 in left neighboring window win(1,2) as well as node 4 in lower neighboring window win(2,1). The flag values for node 5 is set to “0”, indicating that this node does not interact or overlap with a polygon from layer B for a local select. However, the flag value for node 4 is set to “1”, indicating that node 4 from lower neighboring window win(2,1) does satisfy the selection condition for the polyInteract operation.
The center window win(1,1) includes symbol 1224 which shows that the window does not contain any nodes, but there are nodes 2, 4, 6, and 8 in the neighboring windows win(1,0), win(2,1), win(1,2), and win(0,1), respectively. The flags for nodes 2, 6, and 8 are set to “0”, indicating that none of these nodes in neighboring windows satisfy the selection condition for the polyInteract operation. However, the flag value for node 4 is set to “1”, indicating that node 4 from right neighboring window win(2,1) does satisfy the selection condition for the polyInteract operation.
An optimization that can be performed is to only perform such aggregations for windows that contain flag data indicating relevant information, e.g., having a flag value set to “1”. For example, this optimization may be performed by not aggregating the data from window (1,1) to other windows since this window does not contain any nodes and/or any nodes having a flag value of “1”. In addition, an optimization can be performed to only perform aggregation and updating for a window having data that is relevant for processing. For example, this optimization may be performed by not updating the node data for window (1,1) since this window does not contain any nodes.
Where ‘T’ indicates an abutment relationship and ‘D’ indicates a disqualification.
Where ‘C’ indicates a cut relationship and ‘E’ indicates an enclosing relationship between shapes respectively.
Where ‘E’ indicates an enclosing relationship, ‘C’ indicates a cutting relationship and ‘{ }’ indicates the absence of a relationship with any interface region.
Optimizations may be performed to improve the processing efficiencies in the system. As described with respect to FIG. 11, aggregation action are performed to perform global regioning of the windows. As noted above, an optimization that may be performed is to only perform aggregations for windows that contain flag data indicating relevant information, e.g., having a flag value set to “1”. For example, this optimization may be performed by not aggregating the data from window (1,1) to other windows since this window does not contain any nodes and/or any nodes having a flag value of “1”. In addition, an optimization can be performed to only perform aggregation and updating for a window having data that is relevant for processing. For example, this optimization may be performed by not updating the node data for window (1,1) since this window does not contain any nodes. Another optimization that may be performed is to group multiple select operation together and handle the local/global regioning and count aggregation of multiple select operation in one communications loop. This optimization reduces the overall synchronization time that is needed for the process.
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