Source: http://www.google.com/patents/US7821106?dq=Frischling
Timestamp: 2014-07-22 10:20:23
Document Index: 66672729

Matched Legal Cases: ['Application No. 02796172', 'Application No. 02816578', 'Application No. 7002747', 'Application No. 2003', 'Application No. 2003', 'Application No. 02796172', 'Application No. 2003']

Patent US7821106 - Process for making contact with and housing integrated circuits - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished...http://www.google.com/patents/US7821106?utm_source=gb-gplus-sharePatent US7821106 - Process for making contact with and housing integrated circuitsAdvanced Patent SearchPublication numberUS7821106 B2Publication typeGrantApplication numberUS 12/042,108Publication dateOct 26, 2010Filing dateMar 4, 2008Priority dateAug 24, 2001Fee statusPaidAlso published asCN1547778A, CN100578816C, CN101714516A, EP1419534A2, EP2287916A2, EP2287916A3, US6911392, US7700957, US7880179, US8349707, US20030113979, US20050042786, US20080150063, US20100065883, US20110021002, US20130137259, WO2003019653A2, WO2003019653A3Publication number042108, 12042108, US 7821106 B2, US 7821106B2, US-B2-7821106, US7821106 B2, US7821106B2InventorsFlorian Bieck, J�rgen LeibOriginal AssigneeSchott AgExport CitationBiBTeX, EndNote, RefManPatent Citations (46), Non-Patent Citations (16), Classifications (79), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetProcess for making contact with and housing integrated circuitsUS 7821106 B2Abstract A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.
processing a semiconductor wafer, the semiconductor wafer having a top side and a bottom side, to form on the top side at least one optical element and means for making electrical contact with the at least one optical element, the electrical contact means being on the top side and having a bottom surface facing the top side of the semiconductor wafer;
before dicing, substantially thinning the semiconductor wafer;
forming a via in the semiconductor wafer after thinning the semiconductor wafer, the via extending from the bottom side of the semiconductor wafer to the bottom surface of the electrical contact means, the via having side walls;
forming an insulation layer on the side walls of the via; and
depositing metal in the via to produce an electrical contact between the bottom surface of electrical contact means and the bottom side of the semiconductor wafer.
2. The process according to claim 1, further comprising fixing a transparent cover to the top side of the semiconductor wafer prior to conducting the thinning step.
3. The process according to claim 2, wherein the fixing step comprises adhesively bonding the transparent cover to the semiconductor wafer.
4. The process according to claim 3, wherein the adhesively bonding step comprises forming an epoxy resin layer between the semiconductor wafer and the transparent cover.
forming at least one bottom side electrical contact on the bottom side of the semiconductor wafer; and
electrically connecting the bottom side electrical contact to the metal in the via.
6. The process according to claim 1, further comprising dicing the semiconductor wafer.
7. The process according to claim 1, wherein said depositing step comprises depositing a layer of metal onto the insulation layer on the side walls of the via.
8. The process according to claim 1, wherein the thinning step comprises thinning the semiconductor wafer to less than 200 microns.
9. The process according to claim 1, wherein the step of forming the via comprises etching. Description
CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation application of U.S. application Ser. No. 10/947,974 filed on Sep. 22, 2004, which issued on Apr. 20, 2010 as U.S. Pat. No. 7,700,957 and is a divisional application of U.S. application Ser. No. 10/228,699, filed on Aug. 26, 2002, which issued as U.S. Pat. No. 6,911,392, which claims the benefit of German Application No. DE 10141558.3-33 filed on Aug. 24, 2001, German Application No. DE 10141571.0-33 filed on Aug. 24, 2001, and German Application No. DE 10225373.0 filed on Jun. 6, 2002.
Although the proposed process leads to through-contact being made with the terminal contacts from the active front surface of the chip or wafer to the passive back surface, a number of significant drawbacks arise in the process, so that chips which have been produced using the claimed process are disproportionately expensive. This results, inter alia, from the fact that the trenches which are to be produced in the known process are significantly wider than would normally be encountered during standard division or dicing of a wafer. As a result, this means that the distances between the chips or the integrated circuits have to be relatively great, so that there is space for fewer chips on a wafer. If only for this reason, the known process provides only a relatively low chip yield from a semiconductor wafer. Furthermore, the production process as proposed is also relatively slow. On the one hand, this is in particular because the trenches have to be ground in sequentially, and secondly this is because during production of the trenches, what is known as the dicing saw can only operate at a relatively slow advance rate. Apart from all this, the dicing saws which have to be used are very expensive. A further significant problem of the process described in WO 99/40624 is that the terminal contacts are uncovered by dividing them when the trenches are being ground open. Dividing the terminal contacts in this way requires a very high level of dimensional accuracy, since otherwise at least part of the contact may be destroyed. However, even if accurate cutting of the terminal contact is achieved, it is not easy to produce a contact connection with the terminal contacts which have been uncovered in this way. The reasons for this are in particular that in accordance with the prior art contact is to be made by depositing contact tracks on the walls of the trenches, which are inclined in the wafer, but uniform and therefore targeted deposition is only possible perpendicular to the deposition direction. Further processes for making through-contact with chips are also described in �Future Systems-on-Silicon LSI Chips�, Koyanagi, M; Kurino, H; Lee, K. W.; Sakuma, K, IEEE Micro, July-August 1998, pp. 17-22, W098/52225 and DE 197 46 641. However, these processes are unsuitable for the packaging of optical chips.
SUMMARY OF THE INVENTION In view of this background, the present invention is based on the object of avoiding the above-mentioned drawbacks of the prior art, in order in this way to provide a less expensive and simpler process for producing electrical contact connections during the packaging in particular of optical chips.
According to the invention, the dry-etching process generally comprises photolithographic patterning of the surface which is to be processed and an anisotropic dry etch. The �ASE (Advanced Silicon Etching) Process�, which is based on SFe radicals, or the �Bosch Process� is preferably used. A suitable wet-etching process is etching by means of KOH solution. The latter process in particular has cost benefits.
In many cases, integrated semiconductor circuits which, alone or together with other circuit components or other circuits, are applied to dedicated semiconductor substrates or semiconductor wafers, are used to miniaturize electronic components. A semiconductor substrate of this type having an electronic component or preferably at least one electronic circuit constituent is to be referred to in the text which follows as a chip for the sake of simplicity. Particularly in the fields of optoelectronics and micro-op to-electromechanical systems (�MOEMS�), there are numerous possible applications for circuit arrangements of this type. For example, optical or sensor components of this type and non-optical components can be stacked on top of one another. In particular, numerous possibilities result from the combination of CMOS and CCD chips.
The passages which are used to lead the contacts through the semiconductor material may inter alia be produced by means of a dry-etching process. In particular an anisotropic dry-etching process, such as for example the �ASE process� based on SF6 radicals, is suitable for this purpose. In this context, an inexpensive alternative is anisotropic etching using KOH solution, which is recommended for Si wafers with a (100) orientation. Of course, combinations of the above-mentioned processes can also be used to produce the passages. Furthermore, these processes can also be employed to produce isolation trenches, in which case the isolation trenches can, for example, be etched in one step together with the passages. However, it is also possible, inter alia, in each case to use a different one of the above-mentioned processes or a different combination of these processes to etch the isolation trenches and to etch passages.
In a subsequent etching procedure, etching pits or blind openings 17 are etched into the substrate, the passivation layer 13 protecting the substrate from being etched outside the openings 16. For further processing, a depth in the range from approx. 50 to 200 μm is sufficient for the blind openings, given an overall substrate thickness of approx. 500 μm. One suitable process for producing the etching pits is anisotropic etching of an Si(100) substrate using KOH, during which process etching pits with an aperture angle of approximately 70� are formed, the diameter or cross section of the pits on the active surface being dependent on the etching depth and/or the aperture angle.
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Oct. 18, 199.Classifications U.S. Classification257/621, 438/459, 257/774, 257/82, 257/432, 257/619, 257/E21.577International ClassificationH01L21/76, H01L, H01L21/44, H01L21/3205, H01L25/16, H01L31/0203, H01L23/485, H01L21/00, H01L23/52, H01L31/02, H01L27/146, H01L23/12, H01L23/00, H01L23/31, H01L21/768, H01L29/40Cooperative ClassificationH01L2924/01057, H01L25/0657, H01L2225/06541, H01L2924/01006, H01L2221/68363, H01L23/3114, H01L21/76898, H01L27/14618, H01L2924/014, H01L2225/06513, H01L2924/01023, H01L27/14634, H01L2924/3025, H01L2924/01029, H01L2924/01033, H01L2924/01019, H01L2924/3511, H01L24/14, H01L2225/06582, H01L2924/10329, H01L2924/01004, H01L2924/14, H01L24/94, H01L2924/01058, H01L2924/01068, H01L2924/01032, H01L2924/01005, H01L2924/0106, H01L2924/01013, H01L2924/01082, H01L2924/01039, H01L2924/01075, H01L2224/16, H01L24/13, H01L27/14683, H01L2924/01015, H01L2225/06572, H01L21/76877, H01L31/0203, H01L2924/0102, H01L2924/01078, H01L27/14636, H01L2224/13099, H01L2924/01074, H01L27/1469, H01L2224/13025European ClassificationH01L24/14, H01L31/0203, H01L27/146V, H01L23/31H1, H01L27/146A6, H01L25/065S, H01L24/94, H01L24/13, H01L24/10, H01L21/768TLegal EventsDateCodeEventDescriptionMar 26, 2014FPAYFee paymentYear of fee payment: 4Oct 1, 2010ASAssignmentOwner name: WAFER-LEVEL PACKAGING PORTFOLIO LLC, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHOTT ELECTRONIC PACKAGING ASIA PTE. LTD.;REEL/FRAME:025077/0418Effective date: 20080722Sep 30, 2010ASAssignmentOwner name: SCHOTT ELECTRONIC PACKAGING ASIA PTE. LTD., SINGAPFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SCHOTT AG;REEL/FRAME:025066/0719Effective date: 20070725RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google