Source: http://www.google.com/patents/US8035176?dq=5787445
Timestamp: 2014-04-17 18:55:22
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Patent US8035176 - MEMS package and packaging method thereof - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsProvided are a Micro Electro-Mechanical System (MEMS) package and a method of packaging the MEMS package. The MEMS package includes: a MEMS device including MEMS structures formed on a substrate, first pad electrodes driving the MEMS structures, first sealing parts formed at an edge of the substrate,...http://www.google.com/patents/US8035176?utm_source=gb-gplus-sharePatent US8035176 - MEMS package and packaging method thereofAdvanced Patent SearchPublication numberUS8035176 B2Publication typeGrantApplication numberUS 12/517,557PCT numberPCT/KR2007/003562Publication dateOct 11, 2011Filing dateJul 25, 2007Priority dateDec 7, 2006Also published asEP2092567A1, US20100096713, WO2008069394A1Publication number12517557, 517557, PCT/2007/3562, PCT/KR/2007/003562, PCT/KR/2007/03562, PCT/KR/7/003562, PCT/KR/7/03562, PCT/KR2007/003562, PCT/KR2007/03562, PCT/KR2007003562, PCT/KR200703562, PCT/KR7/003562, PCT/KR7/03562, PCT/KR7003562, PCT/KR703562, US 8035176 B2, US 8035176B2, US-B2-8035176, US8035176 B2, US8035176B2InventorsSung-hae Jung, Myung-Lae Lee, Gunn Hwang, Chang-Kyu Kim, Chang-Han Je, Chang-Auck ChoiOriginal AssigneeElectronics And Telecommunications Research InstituteExport CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (5), Referenced by (6), Classifications (13), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMEMS package and packaging method thereofUS 8035176 B2Abstract Provided are a Micro Electro-Mechanical System (MEMS) package and a method of packaging the MEMS package. The MEMS package includes: a MEMS device including MEMS structures formed on a substrate, first pad electrodes driving the MEMS structures, first sealing parts formed at an edge of the substrate, and connectors formed on the first pad electrodes and the first sealing parts; and a MEMS driving electronic device including second pad electrodes and second sealing parts respectively corresponding to the first pad electrodes and the first sealing parts to be sealed with and bonded to the MEMS device through the connectors to form an air gap having a predetermined width.
forming third pad electrodes and metal balls on the vias, wherein the third pad electrodes and the metal balls are connected to an external substrate. Description
TECHNICAL FIELD The present invention relates to a Micro Electro-Mechanical System (MEMS) package and a packaging method thereof, and more particularly, to a package of an MEMS device and an electronic device for driving the MEMS device and a packaging method thereof.
BACKGROUND ART The methods of connecting a Micro Electro-Mechanical system (MEMS) device to an electronic device for driving the MEMS device (a driving circuit device), e.g., an application specific integrated circuit (ASIC) chip, can be classified into three types.
DISCLOSURE OF INVENTION Technical Solution The present invention provides a Micro Electro-Mechanical System (MEMS) package capable of reducing effects of a parasitic resistance and a parasitic capacitance, enabling chip level or wafer level packaging, and preventing a reduction in a manufacturing yield.
Advantageous Effects An MEMS device of the present invention can be directly bonded to an MEMS driving electronic device to improve yield. Also, an MEMS package can be manufactured on a wafer or chip level. In addition, effects of a parasitic resistance and a parasitic capacitance can be reduced to reduce the SNR of the MEMS device. Moreover, the MEMS device can be packaged and then bonded to the MEMS driving electronic device so as to realize a dual package structure. Thus, time and cost required for packaging can be saved to improve productivity.
MODE FOR THE INVENTION Hereinafter, the present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.
The MEMS driving electronic device 200 includes a substrate 202 having front and back surfaces 202 a and 202 b. A chip part 204 is installed on the front surface 202 a, second pad electrodes 206 are formed around the chip part 204, and second sealing parts 208 are formed at an edge of the substrate 202. The second sealing parts 208 are used to seal the MEMS 100 and the MEMS driving electronic device 200 together. The chip part 204 may include a capacitance-voltage (C-V) converter or an ADC.
Referring to FIG. 3, the sacrificial layer 108 is patterned to form a patterned sacrificial layer 108 a. Referring to FIG. 4, the patterned sacrificial layer 108 a is planarized using chemical mechanical polishing (CMP) to reduce a step difference between the silicon substrate 102 and the patterned sacrificial layer 108 a. Thus, a filling sacrificial layer 110 is formed inside the recessed part 104.
Referring to FIG. 8, the MEMS driving electronic device 200 including the substrate 202 having the second pad electrodes 206 and the second sealing parts 208 respectively corresponding to the first pad electrodes 116 and the first sealing parts 118 is provided. The substrate 202 includes the front and back surfaces 202 a and 202 b, the chip part 204 formed on the front surface 202 a, the second pad electrodes 206 formed around the chip part 204, and the second sealing parts 208 formed at the edge of the substrate 202. The MEMS driving electronic device 200 is sealed with and bonded to the MEMS device 100 through the connectors 102 to form the air gap having the predetermined width. The MEMS device 100 and the MEMS driving electronic device 200 are boned to each other, facing each other, using heat and pressure. After bonding, the metal balls 128 are formed on the third pad electrodes 124 to connect the MEMS package to an external substrate so as to complete the MEMS package.
Referring to FIG. 10, in the MEMS device 100, a silicon epitaxial layer 102 c of an SOI substrate 102 is selectively etched to form silicon epitaxial patterns so as to form the MEMS structures 130 formed of the silicon epitaxial patterns. The MEMS structures 130 are disposed above a space part 126 which is formed by selectively etching an oxide layer 102 b of the SOI substrate 102. First pad electrodes 116 and first sealing parts 118 are formed on the MEMS structures 130 of the SOI substrate 102. The first pad electrodes 116 are formed around the MEMS structures 130 formed above the space part 126 and thus used to drive the MEMS structures 130. The first sealing parts 118 are formed at the edge of the SOI substrate 102. The first sealing parts 118 are used to seal the MEMS device 100 with the MEMS driving electronic device 200.
Connectors 120 are formed on the first pad electrodes 116 and the first sealing parts 118. Vias 122 are formed in the MEMS structures 130 of the SOI substrate 102, the oxide layer 102 b, and a base silicon substrate 102 a. Third pad electrodes 124 and metal balls 128 are formed on the vias 122 to be connected to an external substrate (not shown). Thus, the first pad electrodes 116 are connected to the vias 122.
Referring to FIG. 10, the SOI substrate 102 including the base silicon substrate 102 a, the oxide layer 102 b, and the silicon epitaxial layer 102 c is provided. Referring to FIG. 11, the silicon epitaxial layer 102 c is patterned to form holes 132 exposing the oxide layer 102 b and the MEMS structures 130 formed of the silicon epitaxial patterns.
Referring to FIG. 12, portions of the oxide layer 102 b below the holes 132 are selectively etched to form the space part 126 under the MEMS structures 130. Thus, the MEMS structures 130 are formed above the space part 126. Referring to FIG. 13, the first pad electrodes 116 and the first sealing parts 118 are formed around the MEMS structures 132 that are above the space part 126.
Referring to FIG. 14, the vias 122 are formed in the MEMS structures 130 underneath the first electrode pads 116, the oxide layer 102 b, and the base silicon substrate 102 a. The SOI substrate 102 is selectively etched to form the vias 122. DRIE is selectively performed on a back surface of the SOI substrate 102 to form viaholes, and then a metal layer is filled in the viaholes so as to form the vias 122. Referring to FIG. 15, the connectors 120 are formed on the first pad electrodes 116 and the first sealing parts 118. Orders of processes of forming the first pad electrodes 116 and the first sealing parts 118 and forming the vias 122 and the third pad electrodes 124 may freely vary.
Connectors 120 are formed on the first pad electrodes 116 and the first sealing parts 118. Vias 122 including first and second vias 122 a and 122 b are formed in the silicon substrate 102 and the cap layer 142. Third pad electrodes 124 and metal balls 128 are formed on the vias 122 to be connected to an external substrate (not shown). Thus, the first pad electrodes 116 are connected to the vias 122.
Referring to FIG. 20, the first vias 122 a are formed in the viaholes 138 and 141 around the MEMS structures 140. In other words, the first vias 122 a are formed in the viaholes 138 and 141 around the space part 126. Referring to FIG. 21, the cap layer 142 is formed on the back surface of the silicon substrate 102 to seal the space part 126. Polyimide, dry film resist (DFR), or liquid crystal polymer (LCP) is stacked on and then adhered to the back surface of the silicon substrate 102 to form the cap layer 142. The cap layer 142 is formed on the back surface of the silicon substrate 102 in FIG. 21 but may be formed on a front surface of the silicon substrate 102. In this case, corresponding elements may be formed in an opposite way to the way shown here.
Referring to FIG. 22, the second vias 122 b are formed in the cap layer 142 to be connected to the first vias 122 a so as to form the vias 122 including the first and second vias 122 a and 122 b. If the cap layer 142 is formed of polyimid or DFR, second viaholes (not shown) are formed, and then a conductive material is filled in the second viaholes to form the second vias 122 b. If the cap layer 142 is formed of LCP, the cap layer 142 is selectively etched to form second viaholes (not shown), and then a conductive material is filled in the second viaholes so as to form the second vias 122 b. Referring to FIG. 23, the first pad electrodes 116 and the first sealing parts 118 are formed on surfaces of the first vias 122 a. The first pad electrodes 116 are formed around the MEMS structures 140, and the first sealing parts 118 are formed at the edge of the silicon substrate 102. The third pad electrodes 124 are formed on surfaces of the second vias 122 b. Referring to FIG. 24, the connectors 120 are formed on the first pad electrodes 116 and the first sealing parts 118.
INDUSTRIAL APPLICABILITY The present invention provides a Micro Electro-Mechanical System (MEMS) package capable of reducing effects of a parasitic resistance and a parasitic capacitance. The present invention provides a MEMS package enabling chip level or wafer level packaging, and preventing a reduction in a manufacturing yield. The present invention also provides a method of easily packaging an MEMS package.
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