Source: http://www.google.com/patents/US6162744?dq=6,202,008
Timestamp: 2017-04-29 16:23:18
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Matched Legal Cases: ['application No. 08', 'application No. 08', 'application No. 08', 'application No. 08', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09', 'application No. 09']

Patent US6162744 - Method of forming capacitors having high-K oxygen containing capacitor ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsIn a capacitor forming method, a first capacitor electrode is formed over a substrate. A high K oxygen containing capacitor dielectric layer is formed over the first capacitor electrode. A first annealing of the high K capacitor dielectric layer is conducted at a temperature of at least about 500° C....http://www.google.com/patents/US6162744?utm_source=gb-gplus-sharePatent US6162744 - Method of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layersAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6162744 APublication typeGrantApplication numberUS 09/033,064Publication dateDec 19, 2000Filing dateFeb 28, 1998Priority dateFeb 28, 1998Fee statusPaidPublication number033064, 09033064, US 6162744 A, US 6162744A, US-A-6162744, US6162744 A, US6162744AInventorsHusam N. Al-Shareef, Scott Jeffrey DeBoer, Randhir P. S. ThakurOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (75), Non-Patent Citations (42), Referenced by (56), Classifications (13), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetMethod of forming capacitors having high-K oxygen containing capacitor dielectric layers, method of processing high-K oxygen containing dielectric layers, method of forming a DRAM cell having having high-K oxygen containing capacitor dielectric layers
US 6162744 AAbstract
1. A method of forming a capacitor comprising:forming a first capacitor electrode over a substrate; forming a high K oxygen containing capacitor dielectric layer over the first capacitor electrode; first annealing the high K capacitor dielectric layer at a temperature of at least about 500° C. in a substantially non-oxidizing atmosphere; after the first annealing, second annealing the high K capacitor dielectric layer at a temperature of less than or equal to about 500° C. in an oxidizing atmosphere; and forming a second capacitor electrode over the high K oxygen containing capacitor dielectric layer. 2. The method of claim 1 wherein the first annealing temperature is greater than the second annealing temperature.
15. A method of forming a capacitor comprising:forming a first capacitor electrode over a substrate; forming a high K oxygen containing capacitor dielectric layer over the first capacitor electrode; in multiple steps including at least two different temperatures, annealing the capacitor dielectric layer, at least one of the multiple steps comprising annealing at a temperature of at least about 500° C. in a substantially non-oxidizing atmosphere; and forming a second capacitor electrode over the high K oxygen containing dielectric layer, the substrate not being exposed to a gaseous oxygen containing atmosphere at a temperature of greater than about 500° C. between the capacitor dielectric layer formation and formation of the second capacitor electrode, the multiple steps being conducted before forming the second capacitor electrode. 16. The method of claim 15 wherein the first annealing temperature is greater than the second annealing temperature.
23. A method of forming a capacitor comprising:forming a first capacitor electrode over a substrate; forming a conductive diffusion barrier layer over the first capacitor electrode; forming a substantially amorphous high K oxygen containing capacitor dielectric layer over the barrier layer; first annealing the high K capacitor dielectric layer at a temperature of at least about 500° C. and at a pressure at or below 1 atm in an atmosphere substantially inert to chemical reaction with the dielectric layer, the substrate not being exposed to oxidizing conditions between the forming of the dielectric layer and the first annealing; after the first annealing, second annealing the high K capacitor dielectric layer at a temperature of less than or equal to about 500° C. and at a pressure at or below 1 atm in an oxidizing atmosphere; and after the second annealing, forming a second capacitor electrode over the high K oxygen containing capacitor dielectric layer. 24. The method of claim 23 wherein the first annealing temperature is greater than the second annealing temperature.
28. A method of forming a capacitor comprising:forming a first capacitor electrode configured to at least one of, a) contain silicon, or b) be formed proximately over silicon; forming a high K capacitor dielectric layer comprising at least one of a titanate and a pentoxide over the first capacitor electrode; first annealing the high K capacitor dielectric layer at a temperature of from about 600° C. to 800° C. and at a pressure from about 1 Torr to about 1 atm in an atmosphere substantially inert to chemical reaction with the dielectric layer; after the first annealing, second annealing the high K capacitor dielectric layer at a temperature of less than or equal to about 500° C. and at a pressure of from about 1 Torr to about 1 atm in an oxidizing atmosphere comprising at least one of a gaseous nitrogen and oxygen containing compound, O2 and O3 ; and forming a second capacitor electrode over the high K oxygen containing capacitor dielectric layer. 29. The method of claim 28 wherein at least one of the first and second annealings is conducted in a plasma environment.
31. A method of processing a dielectric layer comprising:forming a high K oxygen containing dielectric layer over a substrate; first annealing the high K oxygen containing dielectric layer at a temperature of at least about 500° C. in a substantially non-oxidizing atmosphere; and after the first annealing, second annealing the high K oxygen containing dielectric layer at a temperature of less than or equal to about 500° C. in an oxidizing atmosphere. 32. The method of claim 31 wherein the first annealing temperature is greater than the second annealing temperature.
41. A method of forming a DRAM cell comprising:forming a first capacitor electrode over a substrate; forming a high K oxygen containing capacitor dielectric layer over the first capacitor electrode; first annealing the high K capacitor dielectric layer at a temperature of at least about 500° C. in a substantially non-oxidizing atmosphere; after the first annealing, second annealing the high K capacitor dielectric layer at a temperature of less than or equal to about 500° C. in an oxidizing atmosphere; forming a second capacitor electrode over the high K oxygen containing capacitor dielectric layer; providing a field effect transistor having a pair of source/drain regions, one of the source/drain regions being provided in electrical connection with the first capacitor electrode, the other of the source drain regions being provided in electrical connection with a bit line. Description
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INTEREST;ASSIGNORS:AL-SHAREEF, HUSAM N.;DEBOER, SCOTT JEFFERY;THAKUR, RANDHIR P. S.;REEL/FRAME:009013/0121Effective date: 19980227Jun 15, 1998ASAssignmentOwner name: MICRON TECHNOLOGY, INC., IDAHOFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:THAKUR, RANDHIR P.S.;REEL/FRAME:009261/0355Effective date: 19980605Aug 14, 2001CCCertificate of correctionMay 12, 2004FPAYFee paymentYear of fee payment: 4Jun 6, 2008FPAYFee paymentYear of fee payment: 8Sep 15, 2009ASAssignmentOwner name: NANYA TECHNOLOGY CORP., TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023220/0637Effective date: 20090605Jun 19, 2012FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services