Source: http://www.google.se/patents/US7951649
Timestamp: 2013-05-21 14:04:02
Document Index: 356220852

Matched Legal Cases: ['Application No. 026', 'Application No. 030', 'Application No. 092', 'Application No. 131', 'Application No. 148', 'Application No. 181', 'Application No. 201870', 'Application No. 221437', 'Application No. 226', 'Application No. 272', 'Application No. 274205', 'Application No. 296', 'Application No. 296', 'Application No. 361', 'Application No. 407', 'Application No. 507', 'Application No. 527', 'Application No. 735', 'Application No. 89', 'Application No. 920']

Patent US7951649 - Process for the collective fabrication of 3D electronic modules - Google PatentS�k Bilder Kartor Play YouTube Nyheter Gmail Drive Mer » Avancerad patents�kning | Webbhistorik | Logga in Avancerad patents�kning PatentThe invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically...http://www.google.se/patents/US7951649?utm_source=gb-gplus-sharePatent US7951649 - Process for the collective fabrication of 3D electronic modules PublikationsnummerUS7951649 B2Typ av kung�relseBeviljande Ans�kningsnummer12/438,179 Publiceringsdatum31 maj 2011 Registreringsdatum3 aug 2007 Prioritetsdatum22 aug 2006�ven publicerat somEP2054929A2US20090209052WO2008022901A2WO2008022901A3 UppfinnareChristian Val Ursprunglig innehavare3D Plus USA-klassificering438/113438/106438/110438/107438/114438/119438/109 Internationell klassificeringH01L21/50 Kooperativ klassningH01L22/32H01L21/563H01L25/0657H01L2225/06551H01L2924/01068H01L2221/68368H01L2924/01079H01L2224/73203H01L25/50H01L2225/06513H01L2225/06572H01L2924/01019 Europeisk klassificeringH01L 25/065SH01L 21/56FH01L 25/50H01L 22/32H�nvisningarCitat fr�n patent (33)Citat fr�n andra k�llor (31) H�nvisningar finns i f�ljande patent (3)Externa l�nkarUSPTO �verl�telse av �gander�tt till patent som har registrerats av USPTO EspacenetProcess for the collective fabrication of 3D electronic modulesUS 7951649 B2 Sammanfattning The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically insulating layer (4) of thickness ei, forming the insulating substrate provided with at least one silicon electronic component (11) having connection pads (2) connected to the test pads (20) through the insulating layer. The components are encapsulated in an insulating resin (6) of thickness er, filling the spaces between the components, then separated from one another by first grooves (30) with a width L1 and a depth P1 such that ei+er<P1<ei+er+es, the connection pads of components (2) being connected to tracks (3) that are flush with the grooves (30);
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H�nvisningar finns i f�ljande patent citeras i Registreringsdatum Publiceringsdatum S�kande TitelUS80128024 feb 20106 sep 2011Headway Technologies, Inc.Method of manufacturing layered chip packageUS835974018 dec 200929 jan 20133D PlusProcess for the wafer-scale fabrication of electronic modules for surface mountingUS2009026022824 okt 200822 okt 20093D PlusProcess for the vertical interconnection of 3d electronic modules by viasRoteraOriginalbildGoogles startsida - Webbplatskarta - Massh�mtningar av USPTO - Sekretesspolicy - Anv�ndarvillkor - Om Google Patent - Skicka feedbackDessa data tillhandah�lls av IFI CLAIMS Patent Services©2012 Google