Source: https://patents.google.com/patent/US7978753?oq=5920316
Timestamp: 2018-04-21 10:37:59
Document Index: 596375341

Matched Legal Cases: ['Application No. 60', 'Application No. 2', 'Application No. 2000', 'Application No. 2000', 'Application No. 2008', 'Application No. 2008', 'Application No. 2']

US7978753B2 - Multicarrier transmission system with low power sleep mode and rapid-on capability - Google Patents
US7978753B2
US7978753B2 US12615946 US61594609A US7978753B2 US 7978753 B2 US7978753 B2 US 7978753B2 US 12615946 US12615946 US 12615946 US 61594609 A US61594609 A US 61594609A US 7978753 B2 US7978753 B2 US 7978753B2
US12615946
US20100054312A1 (en )
This application is a continuation of application Ser. No. 11/425,507 filed Jun. 21, 2006, which is a continuation of application Ser. No. 11/289,516 filed Nov. 30, 2005, which is a continuation of application Ser. No. 11/090,183 filed Mar. 28, 2005, which is a continuation of application Ser. No. 10/778,083 filed Feb. 17, 2004, which is a continuation of application Ser. No. 10/175,815 filed Jun. 21, 2002, which is a continuation of application Ser. No. 09/581,400 filed Jun. 13, 2000 now U.S. Pat. No. 6,445,730 which is a 371 of International Application No. PCT/US99/01539 filed Jan. 26, 1999, which claims benefit of and priority to U.S. Application No. 60/072,447 filed Jan. 26, 1998 entitled “Multicarrier Transmission System with a Low Power Sleep Mode and with Instant-On Capability” each of which are incorporated herein by reference in their entirety.
In such systems, a pair of transceivers communicate with other by dividing the overall bandwidth of the channel interconnecting the subscriber and the central office into a large number of separate subchannels, each of limited bandwidth, operating in parallel with each other. For example, one common system divides three subscriber line channel into two hundred and fifty six subchannels, each of 4.3 kilohertz bandwidth. A first group of these (e.g., one hundred ninety six) is allocated to communications from the central office to the subscriber (this is known as the “downstream” direction); a second group (e.g., thirty-two) is allocated to communications from the subscriber to the central office (this is known as the “upstream” direction). The remaining subchannels are allocated to administrative, overhead and control (AOC) functions.
The problem of signal impairment is especially serious in those xDSL configurations which carry the DSL communications on a common line with ordinary voice communications but which omit the use of a “splitter” at either the subscriber premises the central office or both. A “splitter” is basically a filter which separates the low-frequency voice communications (e.g., from zero to four kilohertz) from the higher frequency data communications (which may extend up into the megahertz band) and provides a strong degree of isolation between the two. In the absence of a splitter, unique provisions must be made to accommodate voice and data communications on the same line. For a more detailed description of the problem and its solution, see the co-pending application of Richard Gross et al. entitled “Splitterless Multicarrier Modem”, Serial No. PCT/US98 21442, filed Oct. 9, 1998, and assigned to the assignee of the present invention, the disclosure of which is incorporated herein by reference.
Because of the complexity of DSL transceivers, and the conditions under which they must operate, it is necessary to initialize them prior to the transmission and reception of data. This initialization includes, inter alia, channel corrections such as “training” the frequency-domain and time-domain equalizers and the echo cancellers; setting the channel gains; negotiating the transmission and reception data rates; adjusting the fine gains on the subchannels over which communication is to take place; setting the coding parameters; and the like. Additionally, it includes measuring the signal-to-noise ratio of each of the subchannels, calculating the bit-allocation tables characteristic of each under given conditions of transmission, and exchanging these tables with other modems with a given modem communicates. For more detailed discussion of these procedures, refer to the application of Richard Gross et al., cited above and incorporated herein by reference. These procedures can require from seconds to tens of seconds. In a new installation, the time required is inconsequential. However, in an already-operating installation, the time required to initialize or re-initialize the system after a suspension of operation in connection with power conservation is generally unacceptable, since it is typically desired to have the modem respond to request for service nearly instantaneously.
A Frame Counter (FC) 24 connected to the controller 32 maintains a count of the number of frames of data transmitted from or received by the transceiver 10. The clock 30 maintains the count in counter 34 synchronous with that of a corresponding counter (not shown) in the CO transceiver. In DSL systems, typically, data is communicated in the form of a sequence of data frames (e.g., sixty-eight frames for ADSL as specified in ITU Document G.992.2), followed by a synchronization frame, each frame having a duration of one symbol period of approximately two hundred and fifty microseconds. Together, the sixty-nine frames comprise a “superframe”. Thus, the counter 34 typically maintains a count modulo sixty-nine. Finally, a State Memory (SM) 36 connected to the controller 32 records the state of the transceiver for reasons discussed more fully below.
Turning now to the receiver section 16, it is formed from a line conditioner 50; an analog-to-digital converter (ADC) 52; a serial-to-parallel converter 54; a Fast Fourier Transform (FFT) section 56; a decoder 58; and a parallel-to-serial converter 60. The conditioner 50 compensates for transmission distortions introduced by the line 14, and commonly includes a frequency-domain equalizer (FDQ) 50 a; a time-domain equalizer (TDQ) 50 b; and an echo canceller (EC) 50 c, among other elements. The ADC 52 converts the received signal to digital form and applies it to the serial-to-parallel converter 54. The converter 54 removes any cyclic prefix that may have been appended to the signal before it was transmitted, and applies the resultant signal to the FFT 56 which effectively “demodulates” the received signal. The output of the FFT is applied to decoder 58 which, in conjunction with a bit-allocation-table 62, recovers the symbols Xi and Xi and the bits associated with them. The output of detector 58 is applied to the parallel-to-serial converter 60 which restores the data stream, bi, that was originally applied to the transmitter. The controller 32 also controls the operation of the receiver portion 16 of the transceiver 10.
If entrance into sleep mode is permissible at this time; the CO transceiver responds to the power down or idle signal by transmitting an “Acknowledge Sleep Mode” notification (step 84) to the CPE transceiver. This and subsequent notifications described in connection with the sleep or idle mode may similarly take any of a variety of forms such as described above for the “Intend To Enter Sleep Mode” notification, but again preferably is in the form of a message transmitted over an embedded operations channel.
After it has received acknowledgment from the CO transceiver, the CPE transceiver transmits an “Entering Sleep Mode” notification (step 86) to the CO transceiver and ceases transmission, either immediately or after a given number of frames. The CO transceiver detects this notification; transmits its own “Entering Sleep Mode” notification (step 88); and enters sleep mode (step 90). In pursuance of this, the CO transceiver stores its state in its own state memory corresponding to the state memory 38 of CPE transceiver 10. The state of the CO or CPE transceivers preferably includes at least the frequency and time-domain equalizer coefficients (FDQ; TDQ) and the echo-canceller coefficients (ECC) of its receiver portion and the gain of its transmitter portion; the transmission and reception data rates; the transmission and reception coding parameters; the-transmission fine gains; and the Bit Allocation Tables. The CO transceiver continues to advance the frame count and superframe count during the period of power-down in order to ensure synchrony with the remote CPE transceiver when communications are resumed. In order to maintain synchronization during the power down or idle state, the CO transceiver continues to transmit to the CPE transceiver the synchronizing pilot tone 62 a. It may, at this time, perform its own power reduction. In particular, it may reduce or cut off power to the digital modulator/demodulator portions of its transmitter and receiver sections (corresponding to the IFFT 20 and FFT 56 of the CPE transceiver, FIG. 1); this provides a significant power reduction. Further, it may reduce power to parts of the analog circuitry. Power will be maintained, of course, to at least that portion of the analog driver circuitry which transmits the pilot tone and other control signals to the CPE transceiver, and to line circuits required to monitor the line 14 for signals from the CPE transceiver.
In response to the “Entering Sleep Mode” notification from the CO transceiver, the CPE transceiver enters the sleep mode (step 92). In particular, it stores its state (step 94) in state memory 38; as noted above in connection with the CO transceiver, this includes preferably at least the frequency and time-domain equalizer coefficients (FDQ; TDQ) and the echo-canceller coefficients (ECC) of its receiver and the gain of its transmitter; the transmission and reception data rates; the transmission and reception coding parameters; the transmission fine gains; and the Bit Allocation Tables. The phase and frequency offset of the phase-locked loop 62 is maintained by continued operation of the loop. The CPE transceiver 10 then reduces power to the digital modulator/demodulator circuitry comprising IFFT 20 and FFT 56, as well as to and transmitter data line drivers 26. However, it continues to advance the frame counter 34 in accordance with the received synchronizing signal 62 a. However, the CPE controller 32 now causes this signal to be applied to the PLL 62 from the output of the ADC 52 (FIG. 1) via the detector 64, which implements the DFT of a single tone, instead of directly from the output of the FFT 56 as was previously the case. This enables the FFT 56 to be powered down. The CPE and CO transceivers then operate in sleep mode (steps 95 and 97, respectively) until they awaken.
10. A method according to claim 9 including the step of maintaining synchronization in said transceiver with a synchronization signal transmitted to said transceiver during the time that said transceiver is in sleep mode.
US12615946 1998-01-26 2009-11-10 Multicarrier transmission system with low power sleep mode and rapid-on capability Active US7978753B2 (en)
US11425507 Continuation US7697598B2 (en) 1998-01-26 2006-06-21 Multicarrier transmission system with low power sleep mode and rapid-on capability
US13152558 Continuation US8437382B2 (en) 1998-01-26 2011-06-03 Multicarrier transmission system with low power sleep mode and rapid-on capability
US20100054312A1 true US20100054312A1 (en) 2010-03-04
US7978753B2 true US7978753B2 (en) 2011-07-12
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US7697598B2 (en) 2010-04-13 grant