Source: https://patents.google.com/patent/US9348767B2/en
Timestamp: 2019-05-26 04:41:10
Document Index: 235039879

Matched Legal Cases: ['Application No. 200480035019', 'Application No. 200480035019', 'Application No. 200480035019', 'Application No. 200480035019', 'Application No. 200480035019', 'Application No. 200480035019', 'Application No. 11', 'Application No. 2006', 'Application No. 2011', 'Application No. 10', 'Application No. 10']

US9348767B2 - Accessing private data about the state of a data processing machine from storage that is publicly accessible - Google Patents
US9348767B2
US9348767B2 US13/413,176 US201213413176A US9348767B2 US 9348767 B2 US9348767 B2 US 9348767B2 US 201213413176 A US201213413176 A US 201213413176A US 9348767 B2 US9348767 B2 US 9348767B2
US13/413,176
US20130067184A1 (en
2003-11-26 Priority to US10/724,321 priority Critical patent/US8156343B2/en
2012-03-06 Application filed by Intel Corp filed Critical Intel Corp
2012-03-06 Priority to US13/413,176 priority patent/US9348767B2/en
2013-03-14 Publication of US20130067184A1 publication Critical patent/US20130067184A1/en
2016-05-24 Publication of US9348767B2 publication Critical patent/US9348767B2/en
This application is a continuation of U.S. patent application Ser. No. 10/724,321, filed Nov. 26, 2003, entitled “ACCESSING PRIVATE DATA ABOUT THE STATE OF A DATA PROCESSING MACHINE FROM STORAGE THAT IS PUBLICLY ACCESSIBLE,” the content of which is hereby incorporated by reference.
FIG. 6. illustrates an embodiment of a programmable (parameterized) address mapping function that may be used in the system of FIG. 4. In FIG. 6, one would load the polynomial control register 604 with P.sub.0=1, P.sub.1=1, P.sub.2=0, P.sub.3=0 to implement primitive polynomial x.sup.4+x.sup.1+x.sup.0 and load the Optional mask register 610 with all zeroes. This logic is an adaptation of the equations governing generic w-bit wide MISR's and can be used to construct various address encoding combinational logic. The parameterized MISR state equations are:
S i(t+1)=S i−1(t)+I i+(P i ·S w−1(t)), 1≦i≦w−1
S 0(t+1)=I 0+(P 0 ·S w−1(t))
The encoding of the content values of the private-state data may be accomplished in a way similar to those described above for address obfuscation. One approach is to XOR-in the logical address offsets (for aligned regions of private-state data), or XOR-in some constant seed value, with the contents of a given element of private-state to be encoded. A more sophisticated encoding mechanism may be used on a stream of private-state data values. A variant of a feedback shift register technique (linear, non-linear, multi-input, etc.) may be used with an initial seed. The initial seed is defined to be the initial state loaded into the feedback shift register. For each data value in succession, the shift register may be advanced and its contents bit-wise XOR-ed to the contents of the internal register. This is referred to as a Vigenre cipher and an example of this is shown in tables 470,480 of FIG. 4 above, where each unencoded content (data) value in 470 is zero (e.g., entry 471) but does not appear as such when stored in encoded form in 480 (e.g., entry 481) in memory 408. With this cipher, the shift register is used to generate a pseudo-random sequence of bit-wise XOR masks. In this case as each pseudo-random byte-wide mask is produced by an MISR (see 480), it is bit-wise XOR'ed with the next data value in the address sequence. Only the polynomial and initial shift register seed value is needed to regenerate the exact same sequence again. In an embodiment, the encode and/or decode unit's configuration information (e.g., polynomial and initial seed) could be stored along with the encoded state region in memory 408. To decode the private-state, the configuration information (e.g., polynomial and initial seed) would be retrieved (and possibly decoded using another fixed encoding technique), and then used. As long as each mask in the sequence is applied to the corresponding data in the same order (e.g., one mask applied per addressable data unit), the bit-wise XOR masking will produce (decode) the original data. As discussed previously, the polynomial and initial MISR seed values may be changed (e.g., boot time, run time, etc) using various methods or change constraints. To recover the original data, the decode method(s) appropriate for the encoding method(s) originally used should be applied, i.e. to undo the encoding. Vigenre ciphers are just one example of a private-state data value encoding mechanism, which is efficient and permits programmability with simple binary coefficient lists, seeds, etc., and a modest amount of hardware with only a few gate delays. Other embodiments are also possible.
a storage element to store implementation-specific processor private-state data about an active task of the processor;
encryption logic to encode said processor private-state data prior to storage in a publicly accessible private-state location;
wherein the encryption logic comprises:
an address generation unit (AGU) to receive a micro-operation instruction for writing said processor private-state data, and compute an address based upon the instruction;
an address encoding unit to translate said address to point to said publicly accessible location; and
decryption logic to decode said encoded processor private-state data after said encoded processor private-state data has been read from the publicly accessible location; and
processor private-state data decoding hardware to decode said processor private-state data in response to an instruction for accessing the processor private-state data.
2. The processor of claim 1 wherein the decryption logic comprises:
a first cache to store said encoded processor private-state data; and
a second cache to store said decoded processor private-state data.
US13/413,176 2003-11-26 2012-03-06 Accessing private data about the state of a data processing machine from storage that is publicly accessible Active US9348767B2 (en)
US10/724,321 US8156343B2 (en) 2003-11-26 2003-11-26 Accessing private data about the state of a data processing machine from storage that is publicly accessible
US13/413,176 US9348767B2 (en) 2003-11-26 2012-03-06 Accessing private data about the state of a data processing machine from storage that is publicly accessible
US13/836,863 US9087000B2 (en) 2003-11-26 2013-03-15 Accessing private data about the state of a data processing machine from storage that is publicly accessible
US10/724,321 Continuation US8156343B2 (en) 2003-11-26 2003-11-26 Accessing private data about the state of a data processing machine from storage that is publicly accessible
US13/836,863 Continuation US9087000B2 (en) 2003-11-26 2013-03-15 Accessing private data about the state of a data processing machine from storage that is publicly accessible
US20130067184A1 US20130067184A1 (en) 2013-03-14
US9348767B2 true US9348767B2 (en) 2016-05-24
US10/724,321 Active 2026-11-16 US8156343B2 (en) 2003-11-26 2003-11-26 Accessing private data about the state of a data processing machine from storage that is publicly accessible
US13/413,176 Active US9348767B2 (en) 2003-11-26 2012-03-06 Accessing private data about the state of a data processing machine from storage that is publicly accessible
US13/836,863 Active US9087000B2 (en) 2003-11-26 2013-03-15 Accessing private data about the state of a data processing machine from storage that is publicly accessible
DE (1) DE112004002259B4 (en)
WO2005055024A1 (en) 2003-11-26 2005-06-16 Intel Corporation Accessing private data about the state of a data processing machine from storage that is publicly accessible
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2003-11-26 US US10/724,321 patent/US8156343B2/en active Active
2004-11-07 KR KR1020067010203A patent/KR100974973B1/en not_active IP Right Cessation
2004-11-07 DE DE112004002259T patent/DE112004002259B4/en not_active Expired - Fee Related
2004-11-07 CN CN200480035019.4A patent/CN1886711B/en active IP Right Grant
2004-11-07 JP JP2006541379A patent/JP2007515709A/en active Pending
2004-11-07 WO PCT/US2004/038734 patent/WO2005055024A1/en active Application Filing
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2013-03-15 US US13/836,863 patent/US9087000B2/en active Active
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DE112004002259B4 (en) 2013-06-06
CN1886711A (en) 2006-12-27
JP2007515709A (en) 2007-06-14
US20050114610A1 (en) 2005-05-26
US20130275772A1 (en) 2013-10-17
KR100974973B1 (en) 2010-08-09
DE112004002259T5 (en) 2006-10-26
US20130067184A1 (en) 2013-03-14
JP2011076632A (en) 2011-04-14
US9087000B2 (en) 2015-07-21
CN1886711B (en) 2014-07-23
WO2005055024A1 (en) 2005-06-16
JP5021078B2 (en) 2012-09-05
KR20060090296A (en) 2006-08-10
US8156343B2 (en) 2012-04-10
US20160232108A1 (en) 2016-08-11 Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices