Source: http://www.google.com/patents/US7919875?dq=5311516
Timestamp: 2017-09-20 03:06:17
Document Index: 1549708

Matched Legal Cases: ['Application No. 03025016', 'Application No. 03025016', 'Application No. 03025016', 'Application No. 03028639', 'Application No. 04', 'Application No. 0301938', 'Application No. 030109388', 'Application No. 03013839', 'Application No. 03013839', 'Application No. 03028639', 'Application No. 03025016', 'Application No. 06026978', 'Application No. 06026978', 'Application No. 03028639']

Patent US7919875 - Semiconductor device with recess portion over pad electrode - Google Patents
A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded...http://www.google.com/patents/US7919875?utm_source=gb-gplus-sharePatent US7919875 - Semiconductor device with recess portion over pad electrode
Publication number US7919875 B2
Application number US 11/956,160
Also published as CN1581428A, CN100367451C, EP1505643A2, EP1505643A3, EP1505643B1, US7312107, US20050048740, US20080093708
Publication number 11956160, 956160, US 7919875 B2, US 7919875B2, US-B2-7919875, US7919875 B2, US7919875B2
Inventors Takashi Noma, Katsuhiko Kitagawa, Hisao Otsuka, Akira Suzuki, Yoshinori Seki, Yukihiro Takao, Keiichi Yamaguchi, Motoaki Wakui, Masanori Iida
Original Assignee Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.
Patent Citations (134), Non-Patent Citations (47), Referenced by (14), Classifications (44), Legal Events (7)
Semiconductor device with recess portion over pad electrode
US 7919875 B2
a semiconductor die having an insulation film formed on a front surface thereof;
a first wiring formed on the insulation film;
a supporting body disposed on the insulation film and the first wiring;
an adhesive layer attaching the supporting body to the front surface of the semiconductor die so as to cover all lateral edges of the first wiring;
a recess portion formed in the semiconductor die and extending from a side of the semiconductor die horizontally with respect to the front surface and extending from a back surface of the semiconductor die vertically with respect to the front surface so as to extend into the supporting body; and
a second wiring disposed in the recess portion so as to be connected to the first wiring; and
a protection film disposed on the second wiring so as to be in contact with a side surface of the supporting body,
wherein, in plan view of the semiconductor device, a length of the recess portion along said side of the semiconductor die is shorter than a length of the semiconductor die along said side of the semiconductor die, and
in plan view of the semiconductor device a part of the first wiring is in the recess portion and not covered by the semiconductor die, and another part of the first wiring is covered by the semiconductor die.
2. The semiconductor device of claim 1, wherein part of the first wiring is disposed between the semiconductor die and the supporting body.
3. The semiconductor device of claim 2, wherein the length of the recess portion along said side of the semiconductor die is shorter than a length of the first wiring along said side of the semiconductor die so that both ends of the first wiring along said side of the semiconductor die are covered by the semiconductor die.
4. The semiconductor device of claim 2, wherein the recess portion extends horizontally so as not to reach a side of the first wiring that is normal to said side of the semiconductor die.
This application is a divisional of Ser. No. 10/910,805, filed Aug. 4, 2004, now U.S. Pat. No. 7,312,107.
The semiconductor device described above has disadvantages of increased thickness and higher manufacturing cost, since it uses two glass substrates. So, a method to bond the glass substrate only to the top surface of the semiconductor die, on which the first wiring is formed, has been considered. In this case, the bottom surface of the device is made of the semiconductor substrate which is easier to process by etching compared with the glass substrate. Taking this advantage, the first wiring is exposed by etching the semiconductor substrate and the insulation film in the dicing line region in order for the first wiring to be connected with the second wiring. As a result, a contact area between the first wiring and the second wiring is increased, compared with the conventional method using two glass substrates. After forming the second wirings, a protection film 110 and the conductive terminals, the semiconductor substrate is finally separated into individual semiconductor dice by cutting the glass substrate.
The first wiring 103 is provided on an insulation film 102 on a top surface of the semiconductor die 101. The semiconductor die 101 is bonded to the first glass substrate 104 a with the resin 105 a. A back surface of the semiconductor die 101 is bonded to the second glass substrate 104 b with the resin 105 b. One end of the first wiring 103 is connected to the second wiring 109. The second wiring 109 extends from the end of the first wiring 103 to a surface of the second glass substrate 104 b. The ball-shaped conductive terminal 111 is formed on the second wiring 109 extending onto the second glass substrate 104 b.
The semiconductor device described above has disadvantages of increased thickness and higher manufacturing cost, since it uses two glass substrates. So, a method to bond the glass substrate only to the top surface of the semiconductor die, on which the first wiring is formed, has been considered. In this case, the bottom surface of the device is made of the semiconductor substrate which is easier to process by etching compared with the glass substrate. Taking this advantage, the first wiring is exposed by etching the semiconductor substrate and the insulation film in the dicing line region in order for the first wiring to be connected with the second wiring. As a result, a contact area between the first wiring and the second wiring is increased, compared with the conventional method using two glass substrates. After forming the second wirings, a protection film and the conductive terminals, the semiconductor substrate is finally separated into individual semiconductor dice by cutting the glass substrate.
Next, electroless plating is applied to the surface above the semiconductor substrate 1 opposite from the surface facing the glass substrate 4 to form a Ni—Au plating film 9 on the second wirings 8, as shown in FIGS. 8A and 8B. The film is formed only on the second wirings 8 because it is formed by plating.
After that, portions of the protection film 10 above locations where the conductive terminals 11 are to be formed are removed by etching using a photoresist film (with openings at locations corresponding to the cushioning pads 7, not shown) as a mask and the conductive terminals 11 are formed on the Ni—Au plating film 9 at the locations corresponding to the cushioning pads 7. The conductive terminals 11 are electrically connected with the second wirings 8 through the Ni—Au plating film 9. The conductive terminals 111 are formed of solder bumps of gold bumps. When the gold bumps are used, thickness of the conductive terminal 11 can be reduced from 160 μm to several micrometers or several tens of micrometers.
US3756872 Oct 6, 1969 Sep 4, 1973 Lucas Industries Ltd Method of making non-planar semiconductor devices
US3787252 Nov 8, 1971 Jan 22, 1974 Honeywell Inf Systems Italia Connection means for semiconductor components and integrated circuits
US4179794 Apr 5, 1978 Dec 25, 1979 Nippon Gakki Seizo Kabushiki Kaisha Process of manufacturing semiconductor devices
US5648684 Jul 26, 1995 Jul 15, 1997 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack
US5691245 Oct 28, 1996 Nov 25, 1997 He Holdings, Inc. Methods of forming two-sided HDMI interconnect structures
US5910687 Jan 24, 1997 Jun 8, 1999 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
US6002163 Dec 21, 1998 Dec 14, 1999 General Electric Company Electronic device pad relocation, precision placement, and packaging in arrays
US6051489 May 13, 1997 Apr 18, 2000 Chipscale, Inc. Electronic component package with posts on the active side of the substrate
US6054760 Dec 23, 1996 Apr 25, 2000 Scb Technologies Inc. Surface-connectable semiconductor bridge elements and devices including the same
US6214639 Aug 3, 1999 Apr 10, 2001 Fujitsu Limited Method of producing a semiconductor device
US6339251 * Nov 29, 1999 Jan 15, 2002 Samsung Electronics Co., Ltd Wafer grooves for reducing semiconductor wafer warping
US6362529 Sep 22, 2000 Mar 26, 2002 Sharp Kabushiki Kaisha Stacked semiconductor device
US6399463 * Mar 1, 2001 Jun 4, 2002 Amkor Technology, Inc. Method of singulation using laser cutting
US6420211 Dec 23, 1999 Jul 16, 2002 Gemplus Method for protecting an integrated circuit chip
US6432744 Oct 31, 1998 Aug 13, 2002 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
US6485814 Feb 25, 2000 Nov 26, 2002 Fujitsu Limited High density thin film circuit board and method of production thereof
US6607941 * Jan 11, 2002 Aug 19, 2003 National Semiconductor Corporation Process and structure improvements to shellcase style packaging technology
US6649931 Nov 13, 2001 Nov 18, 2003 Hitachi, Ltd. Semiconductor wafer, semiconductor chip, semiconductor device and method for manufacturing semiconductor device
US6720661 Jun 1, 2001 Apr 13, 2004 Seiko Epson Corporation Semiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrument
US6753936 May 13, 2002 Jun 22, 2004 Dai Nippon Pringing Co., Ltd. Field sequential color liquid crystal display device
US6780251 Jul 18, 2002 Aug 24, 2004 Hitachi Kokusai Electric, Inc. Substrate processing apparatus and method for fabricating semiconductor device
US6805279 Jun 27, 2002 Oct 19, 2004 Taiwan Semiconductor Manufacturing Co., Ltd. Fluxless bumping process using ions
US7045870 Oct 2, 2002 May 16, 2006 Sony Corporation Solid image-pickup device and method for manufacturing the solid image pickup device
US7064047 * Jul 19, 2004 Jun 20, 2006 Fujitsu Limited Semiconductor device having a ball grid array and a fabrication process thereof
US7067354 * Jun 18, 2004 Jun 27, 2006 National Semiconductor Corporation Electrical die contact structure and fabrication method
US7101735 * Oct 30, 2003 Sep 5, 2006 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device
US7112881 * Sep 22, 2004 Sep 26, 2006 Sanyo Electric Co., Ltd. Semiconductor device
US7205635 * Oct 14, 2005 Apr 17, 2007 Mcsp, Llc Hermetic wafer scale integrated circuit structure
US7208340 * Dec 12, 2003 Apr 24, 2007 Sanyo Electric Co., Ltd. Semiconductor device manufacturing method
US7312107 Aug 4, 2004 Dec 25, 2007 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US20010005043 Dec 13, 2000 Jun 28, 2001 Masaki Nakanishi Semiconductor device and a method of manufacturing the same
US20020005400 Aug 31, 2001 Jan 17, 2002 Arnon Gat Rapid thermal processing chamber for processing multiple wafers
US20020016024 * Oct 1, 2001 Feb 7, 2002 Thomas Danielle A. Backside contact for touchchip
US20020025587 Jun 27, 2001 Feb 28, 2002 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
US20020038890 Jun 26, 2001 Apr 4, 2002 Shinji Ohuchi Semiconductor device and method for manufacturing the same, semiconductor wafer and semiconductor device manufactured thereby
US20020047210 Oct 10, 2001 Apr 25, 2002 Yuichiro Yamada Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
US20020048889 Jul 9, 2001 Apr 25, 2002 Nec Corporation Method of manufacturing semiconductor device with sidewall metal layers
US20020076855 Dec 15, 2000 Jun 20, 2002 Micro-Asi, Inc Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques
US20020089043 Dec 28, 1999 Jul 11, 2002 Sang Wook Park Semiconductor package with shortened electric signal paths
US20020105591 Jan 22, 2002 Aug 8, 2002 Olympus Optical Co., Ltd. Solid-state image pickup apparatus and fabricating method thereof
US20020110953 Apr 2, 2002 Aug 15, 2002 Ahn Kie Y. Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
US20020158060 Feb 28, 2001 Oct 31, 2002 Kyoji Uchiyama Wafer heating apparatus and ceramic heater, and method for producing the same
US20020185725 Jul 25, 2002 Dec 12, 2002 Moden Walter L. Low profile multi-IC chip package connector
US20030077878 Oct 19, 2001 Apr 24, 2003 Applied Materials, Inc. Method for dicing a semiconductor wafer
US20030134453 Jan 11, 2002 Jul 17, 2003 National Semiconductor Corporation Process and structure improvements to shellcase style packaging technology
US20030216009 * Apr 24, 2003 Nov 20, 2003 Hitachi, Ltd. Semiconductor device and manufacturing the same
US20040017012 Jul 11, 2003 Jan 29, 2004 Yuichiro Yamada Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
US20040041260 Aug 29, 2002 Mar 4, 2004 Wood Alan G. Semiconductor component with backside contacts and method of fabrication
US20040063268 Jun 17, 2003 Apr 1, 2004 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device
US20040137723 Oct 30, 2003 Jul 15, 2004 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device
US20040161920 * Dec 12, 2003 Aug 19, 2004 Sanyo Electric Co., Ltd. Semiconductor device manufacturing method
US20040229405 Jun 18, 2004 Nov 18, 2004 Ashok Prabhu Electrical die contact structure and fabrication method
US20050221585 * May 25, 2005 Oct 6, 2005 Xerox Corporation Use of a U-groove as an alternative to using a V-groove for protection against dicing induced damage in silicon
US20050266660 Jul 26, 2003 Dec 1, 2005 Dag Behammer Method for the production of indiviual monolithically integrated semiconductor circuits
US20060033198 Aug 18, 2005 Feb 16, 2006 Sanyo Electric Co., Ltd. Semiconductor device with sidewall wiring
US20060141750 * Nov 12, 2003 Jun 29, 2006 Nobuhiro Suzuki Semiconductor integrated device and method for manufacturing same
US20060270093 Jul 25, 2006 Nov 30, 2006 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US20070117352 * Jan 18, 2007 May 24, 2007 Taiwan Semiconductor Manufacturing Company, Ltd. Method for dicing semiconductor wafers
US20070166957 Dec 27, 2006 Jul 19, 2007 Sanyo Electric Co., Ltd Method of manufacturing semiconductor device
DE10238444A1 Aug 22, 2002 Mar 4, 2004 United Monolithic Semiconductors Gmbh Production of monolithic integrated semiconductor circuit comprises fixing wafer to rigid substrate after preparing component structures with front side surfaces, and further processing
DE19846232A1 Oct 7, 1998 Mar 9, 2000 Fraunhofer Ges Forschung Back face contacted semiconductor device, e.g. an ion-sensitive FET, is produced by metabolizing a back face contact hole for contacting a connection region or metallization level of a front face circuit structure
EP0468874A2 Jul 22, 1991 Jan 29, 1992 Sumitomo Electric Industries, Ltd. Lamp annealing process for semiconductor wafer and apparatus for execution of such process
EP1041617A1 Jan 20, 1999 Oct 4, 2000 Citizen Watch Co., Ltd. Semiconductor device and method of production thereof and semiconductor mounting structure and method
EP1085570A2 Dec 21, 1999 Mar 21, 2001 Vishay Intertechnology, Inc. Chip scale surface mount package for semiconductor device and process of fabricating the same
EP1429377B1 Dec 15, 2003 Mar 26, 2008 Sanyo Electric Co., Ltd. Method of reflowing conductive terminals
FR2767223B1 Title not available
1 A. Badihi. "ShellCase Ultrathin Chip Size Package", Mar. 14, 1999, Proceedings International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces; pp. 236-240.
2 EP Office Action dated Dec. 2, 2004, directed to EP Patent Application No. 03025016.1; 6 pages.
3 EP Office Action dated Mar. 20, 2007, directed to EP Patent Application No. 03025016.1; 3 pages.
4 EP Office Action dated Nov. 25, 2005, directed to EP Patent Application No. 03025016.1; 4 pages.
5 EP Office Action dated Oct. 31, 2005, directed to EP Patent Application No. 03028639.7; 9 pages.
6 European Office Action issued Jun. 10, 2010 directed to Application No. 04 018 715.5; 4 pages.
7 European Office Action, dated Apr. 10, 2006, directed to EP Application No. 0301938.3; (4 pages).
8 European Office Action, dated Aug. 10, 2005, directed to EP Application No. 030109388.3; (15 pages).
9 European Office Action, dated Sep. 20, 2004, directed to EP Application No. 03013839.0; (5 pages).
10 European Office Action, dated Sep. 26, 2005, directed to EP Application No. 03013839.0; (3 pages).
11 European Search Report dated Jan. 18, 2005, directed to European Patent Application No. 03028639.7; 5 pages.
12 European Search Report dated Jan. 28, 2004, directed to European Patent Application No. 03025016.1; 2 pages.
13 European Search Report, dated Apr. 3, 2009 directed at counterpart application No. EP 04 01 8715; 3 pages.
14 European Search Report, dated Jul. 21, 2009, directed to EP Application No. 06026978.4; (4 pages).
15 European Search Report, dated Sep. 12, 2003, directed to EP-03010938; (4 pages).
16 Extended EP Search Report dated Sep. 24, 2009, directed to European Patent Application No. 06026978.4; 15 pages.
17 Kameyama et al., Office Action mailed Jan. 29, 2010, directed at U.S. Appl. No. 11/645,811; 9 pages.
18 Kameyama, K. et al., U.S. Office Action mailed on Oct. 14, 2009, directed to U.S. Appl. No. 11/645,811; 8 pages.
19 Noma et al., U.S. Office Action mailed Jul. 20, 2010 directed to U.S. Appl. No. 10/876,532; 7 pages.
20 Noma et al., U.S. Office Action mailed Nov. 14, 2008, directed to U.S. Appl. No. 10/876,532; (9 pages).
21 Noma, T. et al., U.S. Office Action mailed Nov. 22, 2010, directed to U.S. Appl. No. 10/876,532; 7 pages.
22 Noma, T. et al., U.S. Office Action mailed on Oct. 27, 2009, directed to U.S. Appl. No. 12/133,171; 6 pages.
23 Noma, Takashi et al., U. S Office Action mailed Apr. 16, 2008, directed at U.S. Appl. No. 10/876,532; 7 pages.
24 Noma, Takashi et al., U.S Office Action mailed Apr. 12, 2007, directed at U.S. Appl. No. 10/910,805; 7 pages.
25 Noma, Takashi et al., U.S Office Action mailed Apr. 2, 2004, directed at U.S. Appl. No. 10/462,829; 8 pages.
26 Noma, Takashi et al., U.S Office Action mailed Apr. 28, 2009, directed at U.S. Appl. No. 11/488,890;8 pages.
27 Noma, Takashi et al., U.S Office Action mailed Apr. 28, 2009, directed at U.S. Appl. No. 11/645,811; 9 pages.
28 Noma, Takashi et al., U.S Office Action mailed Aug. 1, 2006, directed at U.S. Appl. No. 10/420,943; 8 pages.
29 Noma, Takashi et al., U.S Office Action mailed Aug. 27, 2007, directed at U.S. Appl. No. 11/035,399; 7 pages.
30 Noma, Takashi et al., U.S Office Action mailed Dec. 9, 2004, directed at U.S. Appl. No. 10/420,943; 8 pages.
31 Noma, Takashi et al., U.S Office Action mailed Feb. 2, 2007, directed at U.S. Appl. No. 10/420,943; 9 pages.
32 Noma, Takashi et al., U.S Office Action mailed Feb. 26, 2009, directed at U.S. Appl. No. 12/133,171; 7 pages.
33 Noma, Takashi et al., U.S Office Action mailed Jul. 11, 2008, directed at U.S. Appl. No. 90/008,219; 17 pages.
34 Noma, Takashi et al., U.S Office Action mailed Jul. 21, 2006, directed at U.S. Appl. No. 10/733,799; 7 pages.
35 Noma, Takashi et al., U.S Office Action mailed Jul. 27, 2005, directed at U.S. Appl. No. 10/876,532; 6 pages.
36 Noma, Takashi et al., U.S Office Action mailed Jun. 9, 2005, directed at U.S. Appl. No. 10/733,799; 7 pages.
37 Noma, Takashi et al., U.S Office Action mailed Mar. 15, 2006, directed at U.S. Appl. No. 10/876,532; 9 pages.
38 Noma, Takashi et al., U.S Office Action mailed Mar. 28, 2005, directed at U.S. Appl. No. 10/696,581; 10 pages.
39 Noma, Takashi et al., U.S Office Action mailed Mar. 5, 2007, directed at U.S. Appl. No. 10/876,532;7 pages.
40 Noma, Takashi et al., U.S Office Action mailed Mar. 7, 2007, directed at U.S. Appl. No. 11/035,399; 6 pages.
41 Noma, Takashi et al., U.S Office Action mailed May 26, 2009, directed at U.S. Appl. No. 10/876,532; 11 pages.
42 Noma, Takashi et al., U.S Office Action mailed Nov. 20, 2006, directed at U.S. Appl. No. 11/206,146;9 pages.
43 Noma, Takashi et al., U.S Office Action mailed Nov. 8, 2005, directed at U.S. Appl. No. 10/733,799; 5 pages.
44 Noma, Takashi et al., U.S Office Action mailed Oct. 11, 2006, directed at U.S. Appl. No. 10/910,805; 8 pages.
45 Noma, Takashi et al., U.S Office Action mailed on May 1, 2007, directed at U.S. Appl. No. 11/206,146;5 pages.
46 Noma, Takashi et al., U.S Office Action mailed Sep. 5, 2006, directed at U.S. Appl. No. 10/876,532; 7 pages.
47 Partial European Search Report mailed Nov. 5, 2004, directed to European Patent Application No. 03028639.7; 5 pages.
US8536694 * Aug 5, 2010 Sep 17, 2013 Lapis Semiconductor Co., Ltd. Semiconductor device
US8952519 * Jun 15, 2010 Feb 10, 2015 Chia-Sheng Lin Chip package and fabrication method thereof
US20110031615 * Aug 5, 2010 Feb 10, 2011 Oki Semiconductor Co., Ltd. Semiconductor device
US20110169159 * Jun 15, 2010 Jul 14, 2011 Chia-Sheng Lin Chip package and fabrication method thereof
U.S. Classification 257/783, 257/E23.02, 257/773, 257/620, 257/E23.012
International Classification H01L29/40, H01L23/48, H01L23/52, H01L23/31, H01L21/301, H01L23/485, H01L23/12
Cooperative Classification H01L2924/01023, H01L2924/01082, H01L2224/02313, H01L2221/68372, H01L2924/01078, H01L2221/68327, H01L2924/01079, H01L21/78, H01L2224/131, H01L21/6836, H01L21/6835, H01L2224/13144, H01L2224/05644, H01L24/11, H01L23/3114, H01L24/13, H01L2224/0558, H01L2924/01005, H01L2924/014, H01L2924/01033, H01L2924/01006, H01L24/12, H01L2924/00013, H01L2924/01013, H01L2224/0401
European Classification H01L21/78, H01L23/31H1, H01L21/683T, H01L24/12, H01L24/11, H01L21/683T2, H01L24/10
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NOMA, TAKASHI;KITAGAWA, KATSUHIKO;OTSUKA, HISAO;AND OTHERS;SIGNING DATES FROM 20041015 TO 20041021;REEL/FRAME:035530/0573
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KANTO SANYO SEMICONDUCTOR CO., LTD.;REEL/FRAME:038988/0665