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Patent US6985035 - System and method for linearizing a CMOS differential pair - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject...http://www.google.com/patents/US6985035?utm_source=gb-gplus-sharePatent US6985035 - System and method for linearizing a CMOS differential pairAdvanced Patent SearchPublication numberUS6985035 B1Publication typeGrantApplication numberUS 09/573,356Publication dateJan 10, 2006Filing dateMay 17, 2000Priority dateNov 12, 1998Fee statusPaidPublication number09573356, 573356, US 6985035 B1, US 6985035B1, US-B1-6985035, US6985035 B1, US6985035B1InventorsHaideh KhorramabadiOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (46), Non-Patent Citations (11), Referenced by (28), Classifications (43), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSystem and method for linearizing a CMOS differential pair
US 6985035 B1Abstract
An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.
1. A method for generating an effective overall transconductance in an amplifier comprising:
generating a first transconductance from a main differential pair amplifier that is centered about a zero offset voltage; generating a second transconductance from a first differential error amplifier that is symmetrically centered about a negative non zero offset voltage; generating a third transconductance from a second differential error amplifier that is symmetrically centered about a positive non zero offset voltage; adding the second transconductance to the third transconductance to form an error transconductance; and subtracting the error transconductance from the first transconductance to form the effective overall transconductance. 2. A method for reducing differential pair amplifier distortion comprising:
fabricating a differential pair amplifier on a substrate having a pair of MOS transistors each having a channel defined by a first length and a first width; fabricating a first differential pair error amplifier on the substrate having a pair of MOS transistors each having a channel defined by the first length and a second width; fabricating a second differential pair error amplifier on the substrate having a pair of MOS transistors each having a channel defined by the first length and a third width; and coupling the first differential pair error amplifier to the second differential pair error amplifier and the differential pair amplifier. 3. A differential amplifier comprising:
a main differential pair of FET transistors formed by a first transistor of the main differential pair and a second transistor of the main differential pair having a first input of the main differential pair formed by a gate of the first transistor of the main differential pair, having a second input of the main differential pair formed by a gate of the second transistor of the main differential pair, having a first current output of the main differential pair formed by a first drain of the first transistor of the main differential pair, having a second current output of the main differential pair formed by a drain of the second transistor of the main differential pair, with a main differential pair common source connection formed by a source of the first transistor of the main differential pair coupled to a source of the second transistor of the main differential pair; a main differential pair current source for producing a substantially constant direct current coupled to the main differential pair common source connection; a first auxiliary differential pair of FET transistors formed by a first transistor of the first auxiliary differential pair and a second transistor of the first auxiliary differential pair having a first input of the first auxiliary differential pair formed by a gate of the first transistor of the first auxiliary differential pair and coupled to the first input of the main differential pair, with a second input of the first auxiliary differential pair formed by a gate of the second transistor of the first auxiliary differential pair and coupled to the second input of the main differential pair, with a first current output of the first auxiliary differential pair formed by a drain of the first transistor of the first auxiliary differential pair and coupled to the second current output of the main differential pair, with a second current output of the first auxiliary differential pair formed by a drain of the second transistor of the first auxiliary differential pair and coupled to the first current output of the main differential pair, with a first auxiliary differential pair common source connection formed by a source of the first transistor of the first auxiliary differential pair being coupled to a source of the second transistor of the first auxiliary differential pair; a first auxiliary differential pair current source for producing a substantially constant direct current that is a known fraction of the current produced by the main differential pair current source, coupled to the first auxiliary differential pair common source connection; a second auxiliary differential pair of FET transistors formed by a first transistor of the second auxiliary differential pair and a second transistor of the second auxiliary differential pair having, a first input of the second auxiliary differential pair formed by a gate of the first transistor of the second auxiliary differential pair and coupled to the first input of the main differential pair, with a second input of the second auxiliary differential pair formed by a gate of the second transistor of the second auxiliary differential pair and coupled to the second input of the main differential pair, with a first current output of the second auxiliary differential pair formed by a drain of the first transistor of the second auxiliary differential pair and coupled to the second current output of the main differential pair, with a second current output of the second auxiliary differential pair formed by a drain of the second transistor of the second auxiliary differential pair and coupled to the first current output of the main differential pair, with a second auxiliary differential pair common source connection formed by a source of the first transistor of the second auxiliary differential pair being coupled to a source of the second transistor of the second auxiliary differential pair; and a second auxiliary differential pair current source for producing a substantially constant direct current that is a known fraction of the current produced by the main differential pair current source, coupled to the second auxiliary differential pair common source connection; wherein a first transconductance of the main differential pair of FET transistors is symmetrically centered about a zero offset voltage, and a second transconductance of the first auxiliary differential pair of FET transistors is symmetrically centered about a negative non-zero offset voltage, and a third transconductance of the second auxiliary differential pair of FET transistors is symmetrically centered about a positive non-zero offset voltage; wherein said second transconductance is combined with said third transconductance to form an error transconductance; wherein said error transconductance is subtracted from said first transconductance at the first and second drains of said main differential pair to reduce distortion in an output of the main differential pair. 4. The differential amplifier of claim 3, in which the first transistor of the first auxiliary differential pair has a first channel width to channel length ratio;
the second transistor of the second auxiliary differential pair has the first channel width to channel length ratio that is the same as the first channel width to channel length ratio of the first transistor of the first auxiliary differential pair; the second transistor of the first auxiliary differential pair has a second channel width to length ratio; and the first transistor of the second auxiliary differential pair has the second channel width to channel length ratio that is the same as the second channel width to channel length ratio of the second transistor of the first auxiliary differential pair, and the first channel width to channel length ratio is different from the second channel width to channel length ratio; whereby a transistor offset voltage is created by the differing first channel width to channel length ratio to the second channel width to channel length ratio. 5. The differential amplifier of claim 4, in which the main differential pair generates a main differential pair transconductance set in magnitude by the current supplied by the main differential pair current source, the transconductance generated being a function of a differential input voltage impressed across the first input of the main differential pair and the second input of the main differential pair and having a maximum magnitude of transconductance at zero volts differential input voltage;
the first auxiliary differential pair generates a first auxiliary differential pair transconductance set in magnitude by the current supplied by the first auxiliary differential pair current source, the transconductance generated being a function of the differential input voltage impressed across the first input of the main differential pair and the second input of the main differential pair and having a maximum magnitude of transconductance at a differential input voltage equal to a value of the transistor offset voltage; and the second auxiliary differential pair generates a second auxiliary differential pair transconductance set in magnitude by the current supplied by the second auxiliary differential pair current source, the transconductance generated being a function of the differential input voltage impressed across the first input of the main differential pair and the second input of the main differential pair and having a maximum magnitude of transconductance at a differential input voltage equal to a negative value of the transistor offset voltage; whereby the main differential pair transconductance, first auxiliary differential pair transconductance, and second auxiliary differential pair transconductance superimpose to generate a resultant output current of the main differential pair that is substantially free from distortion over an increased range of differential input voltages.
a main differential pair of FET transistors formed by a first transistor of the main differential pair and a second transistor of the main differential pair having a first input of the main differential pair formed by a gate of the first transistor of the main differential pair, having a second input of the main differential pair formed by a gate of the second transistor of the main differential pair, having a first current output of the main differential pair formed by a first drain of the first transistor of the main differential pair, having a second current output of the main differential pair formed by a drain of the second transistor of the main differential pair, with a main differential pair common source connection formed by a source of the first transistor of the main differential pair coupled to a source of the second transistor of the main differential pair; a main differential pair current source for producing a substantially constant direct current coupled to the main differential pair common source connection; a first auxiliary differential pair of FET transistors formed by a first transistor of the first auxiliary differential pair and a second transistor of the first auxiliary differential pair having a first input of the first auxiliary differential pair formed by a gate of the first transistor of the first auxiliary differential pair and coupled to the first input of the main differential pair, with a second input of the first auxiliary differential pair formed by a gate of the second transistor of the first auxiliary differential pair and coupled to the second input of the main differential pair, with a first current output of the first auxiliary differential pair formed by a drain of the first transistor of the first auxiliary differential pair and coupled to the second current output of the main differential pair, with a second current output of the first auxiliary differential pair formed by a drain of the second transistor of the first auxiliary differential pair and coupled to the first current output of the main differential pair, with a first auxiliary differential pair common source connection formed by a source of the first transistor of the first auxiliary differential pair being coupled to a source of the second transistor of the first auxiliary differential pair; a first auxiliary differential pair current source for producing a substantially constant direct current that is a known fraction of the current produced by the main differential pair current source, coupled to the first auxiliary differential pair common source connection; a second auxiliary differential pair of FET transistors formed by a first transistor of the second auxiliary differential pair and a second transistor of the second auxiliary differential pair having, a first input of the second auxiliary differential pair formed by a gate of the first transistor of the second auxiliary differential pair and coupled to the first input of the main differential pair, with a second input of the second auxiliary differential pair formed by a gate of the second transistor of the second auxiliary differential pair and coupled to the second input of the main differential pair, with a first current output of the second auxiliary differential pair formed by a drain of the first transistor of the second auxiliary differential pair and coupled to the second current output of the main differential pair, with a second current output of the second auxiliary differential pair formed by a drain of the second transistor of the second auxiliary differential pair and coupled to the first current output of the main differential pair, with a second auxiliary differential pair common source connection formed by a source of the first transistor of the second auxiliary differential pair being coupled to a source of the second transistor of the second auxiliary differential pair; and a second auxiliary differential pair current source for producing a substantially constant direct current that is a known fraction of the current produced by the main differential pair current source, coupled to the second auxiliary differential pair common source connection; whereby drain currents of the first auxiliary differential pair and the second auxiliary differential pairs of transistors contribute to the drain currents of the main differential pair to reduce distortion in the main differential pair output; wherein the first transistor of the first auxiliary differential pair has a first channel width to channel length ratio; the second transistor of the second auxiliary differential pair has the first channel width to channel length ratio that is the same as the first channel width to channel length ratio of the first transistor of the first differential pair; the second transistor of the first auxiliary differential pair has a second channel width to length ratio; the first transistor of the second auxiliary differential pair has the second channel width to channel length ratio that is the same as the second channel width to channel length ratio of the second transistor of the first auxiliary differential pair, and the first channel width to channel length ratio is different from the second channel width to channel length ratio; whereby a transistor offset voltage is created by the differing first channel width to channel length ratio to the second channel width to channel length ratio; wherein the first transistor of the main differential pair has a channel length of 0.6 micro-meters and a channel width of 38 micro-meters; the second transistor of the main differential pair has a channel length of 0.6 micro-meters and a channel width of 38 micro meters; the main differential pair current source sources 9 miliamps of current; the first transistor of the first auxiliary differential pair has a channel length of 0.6 micro-meters and a channel width of 3.9 micro meters; the second transistor of the first auxiliary differential pair has a channel length of 0.6 micro-meters and a channel width of 10 micro meters; the first auxiliary differential pair current source sources a current one sixteenth that of the main differential current source; the first transistor of the second auxiliary differential pair has a channel length of 0.6 micro-meters and a channel width of 10 micro meters; the second transistor of the second auxiliary differential pair has a channel length of 0.6 micro-meters and a channel width of 3.9 micro meters; and the second auxiliary differential pair current source sources a current one sixteenth that of the main differential current source. 7. A differential amplifier comprising:
a main differential pair of FET transistors formed by a first transistor of the main differential pair and a second transistor of the main differential pair having a first input of the main differential pair formed by a gate of the first transistor of the main differential pair, having a second input of the main differential pair formed by a gate of the second transistor of the main differential pair, having a first current output of the main differential pair formed by a first drain of the first transistor of the main differential pair, having a second current output of the main differential pair formed by a drain of the second transistor of the main differential pair, with a main differential pair common source connection formed by a source of the first transistor of the main differential pair coupled to a source of the second transistor of the main differential pair; a main differential pair current source for producing a substantially constant direct current coupled to the main differential pair common source connection; a first auxiliary differential pair of FET transistors formed by a first transistor of the first auxiliary differential pair and a second transistor of the first auxiliary differential pair having a first input of the first auxiliary differential pair formed by a gate of the first transistor of the first auxiliary differential pair and coupled to the first input of the main differential pair, with a second input of the first auxiliary differential pair formed by a gate of the second transistor of the first auxiliary differential pair and coupled to the second input of the main differential pair, with a first current output of the first auxiliary differential pair formed by a drain of the first transistor of the first auxiliary differential pair and coupled to the second current output of the main differential pair, with a second current output of the first auxiliary differential pair formed by a drain of the second transistor of the first auxiliary differential pair and coupled to the first current output of the main differential pair, with a first auxiliary differential pair common source connection formed by a source of the first transistor of the first auxiliary differential pair being coupled to a source of the second transistor of the first auxiliary differential pair; a first auxiliary differential pair current source for producing a substantially constant direct current that is a known fraction of the current produced by the main differential pair current source, coupled to the first auxiliary differential pair common source connection; a second auxiliary differential pair of FET transistors formed by a first transistor of the second auxiliary differential pair and a second transistor of the second auxiliary differential pair having, a first input of the second auxiliary differential pair formed by a gate of the first transistor of the second auxiliary differential pair and coupled to the first input of the main differential pair, with a second input of the second auxiliary differential pair formed by a gate of the second transistor of the second auxiliary differential pair and coupled to the second input of the main differential pair, with a first current output of the second auxiliary differential pair formed by a drain of the first transistor of the second auxiliary differential pair and coupled to the second current output of the main differential pair, with a second current output of the second auxiliary differential pair formed by a drain of the second transistor of the second auxiliary differential pair and coupled to the first current output of the main differential pair, with a second auxiliary differential pair common source connection formed by a source of the first transistor of the second auxiliary differential pair being coupled to a source of the second transistor of the second auxiliary differential pair; and a second auxiliary differential pair current source for o producing a substantially constant direct current that is a known fraction of the current produced by the main differential pair current source, coupled to the second auxiliary differential pair common source connection; whereby drain currents of the first auxiliary differential pair and the second auxiliary differential pairs of transistors contribute to the drain currents of the main differential pair to reduce distortion in the main differential pair output wherein the first transistor of the first auxiliary differential pair has a first channel width to channel length ratio; the second transistor of the second auxiliary differential pair has the first channel width to channel length ratio that is the same as the first channel width to channel length ratio of the first transistor of the first differential pair; the second transistor of the first auxiliary differential pair has a second channel width to length ratio; the first transistor of the second auxiliary differential pair has the second channel width to channel length ratio that is the same as the second channel width to channel length ratio of the second transistor of the first auxiliary differential pair, and the first channel width to channel length ratio is different from the second channel width to channel length ratio; whereby a transistor offset voltage is created by the differing first channel width to channel length ratio to the second channel width to channel length ratio; wherein the first transistor of the main differential pair comprises a parallel combination of 20 discrete transistors each having a channel length of 0.6 micro-meters and a channel width of 1.9 micro meters; the second transistor of the main differential pair comprises a parallel combination of 20 discrete transistors each having a channel length of 0.6 micro-meters and a channel width of 1.9 micro meters; the first transistor of the first auxiliary differential pair comprises a parallel combination of 2 discrete transistors each having a channel length of 0.6 micro-meters and a channel width of 1.95 micro meters; the second transistor of the first auxiliary differential pair comprises a parallel combination of 5 discrete transistors each having a channel length of 0.6 micro-meters and a channel width of 2 micro meters; the first transistor of the second auxiliary differential pair comprises a parallel combination of 2 discrete transistors each having a channel length of 0.6 micro-meters and a channel width of 2 micro meters; and the second transistor of the second auxiliary differential pair comprises a parallel combination of 2 discrete transistors each having a channel length of 0.6 micro-meters and a channel width of 1.95 micro meters. Description
This application claims the benefit of U.S. Provisional Application No. 60/136,115, filed May 26, 1999, the contents of which is hereby incorporated by reference; this application is also a continuation-in-part of application Ser. No. 09/547,968, filed Apr. 12, 2000, now U.S. Pat. No. 6,525,609, which is a continuation-in-part of application Ser. No. 09/493,942, filed Jan. 28, 2000, which is a continuation-in-part of application Ser. No. 09/483,551, filed Jan. 14, 2000, now U.S. Pat. No. 6,455,039 which is a continuation-in-part of application Ser. No. 09/439,101, filed Nov. 12, 1999, the disclosures of which are incorporated herein by reference; said application Ser. No. 09/547,968 claims the benefit of U.S. Provisional Application 60/129,133, filed Apr. 13, 1999; said application Ser. No. 09/493,942 claims the benefit of U.S. Provisional Application No. 60/117,609, filed Jan. 28, 1999 and U.S. Provisional Application No. 60/136,654, filed May 27, 1999; said application Ser. No. 09/483,551 claims the benefit of U.S. Provisional Application No. 60/116,003, filed Jan. 15, 1999; U.S. Provisional Application No. 60/117,322, filed Jan. 26, 1999; and U.S. Provisional Application No. 60/122,754, filed Feb. 25, 1999; and said application Ser. No. 09/439,101 claims the benefit of U.S. Provisional Application No. 60/108,459, filed Nov. 12, 1998; U.S. Provisional Application No. 60/108,209, filed Nov. 12, 1998; U.S. Provisional Application No. 60/108,210, filed Nov. 12, 1998; U.S. Provisional Application No. 60/117,609, filed Jan. 28, 1999; U.S. Provisional Application No. 60/136,115, filed May 26, 1999; U.S. Provisional Application No. 60/136,116, filed May 26, 1999; U.S. Provisional Application No. 60/136,654, filed May 27, 1999; and U.S. Provisional Application No. 60/159,726, filed Oct. 15, 1999.
Due to inherent amplifier nonlinearities the amplifiers produce distortion. Distortion tends to vary with the signal level presented to an amplifier. Strong input signals tend to increase distortion levels. Often to limit distortion the dynamic range of an amplifier is constrained to a narrow range of input signal levels to prevent distortion from arising. Strong signals tend to produce distortion arising from circuit nonlinearities. Constraint on signal level affects a receiver system's overall performance.
For example constraint on input levels requires tight automatic gain control (“AGC”) of the receiver giving rise to further problems of stability, response time, and maintenance of the required signal level range. Amplifiers with an increased dynamic range and improved linearity are thus desirable in designing receivers to decrease distortion and to relax systems requirements.
There is therefore provided in a present embodiment of the invention, a method for optimizing output current linearity at a differential current output port of an amplifier stage as a function of a change in differential voltage input between a first differential voltage input port and a second differential voltage input port. An embodiment of the method comprises providing a first differential pair amplifier, the first differential pair amplifier having first differential pair output drains, a first differential pair first gate connected to the first differential voltage input port, a first differential pair second gate connected to the second differential voltage input port, and first differential pair amplifier sources connected in parallel to a first current source to provide a first current source current.
And also providing, a second differential pair amplifier, the second differential pair amplifier having second differential pair output drains, a second differential pair first gate connected to the first differential voltage input port, a second differential pair second gate connected to the second differential voltage input port, and second differential pair amplifier sources connected in parallel to a second current source to provide a second current source current.
And also providing, a third differential pair amplifier, the third differential pair amplifier having third differential pair output drains, a third differential pair first gate connected to the first differential voltage input port, a third differential pair second gate connected to the second differential voltage input port, and third differential pair amplifier sources connected in parallel to a third current source to provide a third current source current.
Cross-connecting in parallel the second differential pair output drains, and the third differential pair output drains with the first differential pair output drains.
And finally, subtracting the second current source current and the third current source current from the first current source current to optimize output current linearity at the differential current output port when the differential input voltage is applied between the first differential voltage input port and the second differential voltage input port.
ACTIVE FILTER UTILIZING A LINEARIZED DIFFERENTIAL PAIR AMPLIFIER
ACTIVE FILTER INDUCTOR Q TEMPERATURE COMPENSATION FIGURES
RECEIVER FRONT END-PROGRAMMABLE ATTENUATOR AND LNA FIGURES
Frequency planning is the selection of local oscillator signals that create the intermediate frequency (IF) signals of the down conversion process. It is an analytical assessment of the frequencies being used and the distortion products associated with these frequencies that have been selected. By evaluating the distortion and its strength, an engineer can select local oscillator and IF frequencies that will yield the best overall receiver performance, such as selectivity and image response. In designing a radio receiver, the primary problems encountered are designing for sufficient sensitivity,