Source: https://patents.google.com/patent/WO2014007004A1/en
Timestamp: 2020-02-25 04:07:51
Document Index: 455481482

Matched Legal Cases: ['art 33', 'art 34', 'art 38', 'art 25', 'art 27', 'art, 23']

WO2014007004A1 - Solid-state imaging device, driving method for solid-state imaging device, and electronic device - Google Patents
Solid-state imaging device, driving method for solid-state imaging device, and electronic device Download PDF
WO2014007004A1
WO2014007004A1 PCT/JP2013/065047 JP2013065047W WO2014007004A1 WO 2014007004 A1 WO2014007004 A1 WO 2014007004A1 JP 2013065047 W JP2013065047 W JP 2013065047W WO 2014007004 A1 WO2014007004 A1 WO 2014007004A1
PCT/JP2013/065047
2013-05-30 Application filed by ソニー株式会社 filed Critical ソニー株式会社
2014-01-09 Publication of WO2014007004A1 publication Critical patent/WO2014007004A1/en
The solid-state imaging device of the present disclosure is equipped with a signal processing unit, which includes an AD converter that digitalizes an analogue pixel signal read out, using a signal line, from each pixel of a pixel array, that transfers the digitalized pixel data at a first speed faster than the frame rate, a memory unit that holds pixel data transferred from the signal processing unit, a data processing unit that reads out pixel data from the memory unit at a second speed slower than the first speed, and a control unit that performs control to halt operation of the current source connected to the signal line and at least operation of the AD converter of the signal processing unit when reading pixel data out from the memory unit.
The present disclosure relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an electronic device.
In recent years, solid-state imaging devices, especially CMOS (Complementary Metal Oxide Semiconductor) image sensors, have the advantages of low power consumption and high speed, and are used in electronic devices such as mobile phones, digital still cameras, single lens reflex cameras, camcorders, and surveillance cameras. It is becoming widely installed in equipment. Recently, high-performance, high-quality image sensors that are on-chip together with the pixel array unit (pixel unit) have also started to appear for functional circuit blocks such as image processing.
Conventionally, in a CMOS image sensor, as a method of reading a signal from each pixel of a pixel array unit, a non-volatile memory is provided after a signal processing unit that digitizes an analog pixel signal read from the pixel, and the non-volatile memory is used to perform high-speed processing. There is a technique for realizing reading (see, for example, Patent Document 1).
JP 2004-64410 A
In the above prior art, after the pixel data is stored in the nonvolatile memory, the data output unit that outputs (reads) the pixel data from the nonvolatile memory is operated at a lower speed than the transfer speed of the pixel data to the nonvolatile memory. We are trying to reduce power consumption. However, in the related art, since the power consumption is reduced only by the low-speed operation of the data output unit, the effect of reducing the power consumption is small.
Therefore, the present disclosure aims to provide a solid-state imaging device and a driving method of the solid-state imaging device that can realize readout of pixel data at a high speed with lower power consumption, and an electronic apparatus including the solid-state imaging device. To do.
In order to achieve the above object, a solid-state imaging device of the present disclosure includes:
A signal processing unit that includes an AD converter that digitizes an analog pixel signal read from each pixel of the pixel array unit to a signal line, and that transfers the digitized pixel data at a first speed higher than the frame rate;
A memory unit for holding pixel data transferred from the signal processing unit;
A data processing unit that reads pixel data from the memory unit at a second speed slower than the first speed;
When reading out pixel data from the memory unit, the solid-state imaging device includes a control unit that controls the operation of the current source connected to the signal line and the operation of at least the AD converter of the signal processing unit.
Further, a driving method of the solid-state imaging device of the present disclosure for achieving the above object is as follows.
A signal processing unit that includes an AD converter that digitizes a pixel signal read from each pixel of the pixel array unit to a signal line, and transfers the digitized pixel data at a first speed higher than the frame rate;
In driving a solid-state imaging device including a data processing unit that reads pixel data from a memory unit at a second speed that is slower than the first speed,
This is a driving method of a solid-state imaging device that performs driving to stop operation of a current source connected to a signal line and operation of at least an AD converter of a signal processing unit when reading pixel data from a memory unit.
By transferring pixel data from the signal processing unit to the memory unit at a first speed faster than the frame rate (so-called high-speed transfer), high-speed reading faster than the frame rate can be realized. Further, by reading out pixel data from the memory unit at a second speed that is slower than the first speed (so-called low-speed reading), it is possible to realize a reduction in power consumption corresponding to the reduction in the operation speed. In addition, when the pixel data is read from the memory unit, the current source and the signal processing unit at least the AD converter operation are stopped. Since power can be reduced by the amount originally consumed by the AD converter, further reduction in power consumption can be achieved.
According to the present disclosure, high-speed reading of pixel data can be realized with lower power consumption by using a memory unit and performing high-speed transfer to the memory unit and low-speed reading by intermittent driving.
FIG. 1 is a schematic perspective view illustrating a configuration example of a solid-state imaging device according to an embodiment of the present disclosure. FIG. 2 is a circuit diagram illustrating a specific configuration of the first chip side circuit and the second chip side circuit in the solid-state imaging device according to the first embodiment. FIG. 3 is a block diagram illustrating an example of a specific configuration of the signal processing unit in the solid-state imaging device according to the first embodiment. FIG. 4 is a timing chart for explaining the circuit operation of the solid-state imaging device according to the first embodiment. FIG. 5 is a circuit diagram showing an example of a circuit configuration for cutting off the current path between the signal line and the current source when the operation of the current source is stopped. FIG. 6 is a block diagram for explaining the operation of storing data from the data latch unit to the memory unit and outputting the data from the memory unit. FIG. 7 is a block diagram illustrating another example of a specific configuration of the signal processing unit in the solid-state imaging device according to the first embodiment. FIG. 8 is a layout diagram showing a layout example of a laminated chip in the case of adopting a configuration in which two systems of AD converters and accompanying circuit portions are provided. FIG. 9 is a layout diagram showing a layout example 1 of the multilayer chip in the case of adopting a configuration in which four systems of AD converters and accompanying circuit portions are provided. FIG. 10 is a layout diagram showing a layout example 2 of the laminated chip in the case of adopting a configuration in which four systems of AD converters and accompanying circuit portions are provided. FIG. 11 is a circuit diagram illustrating a specific configuration of a circuit on the first chip side in the solid-state imaging device according to the second embodiment. FIG. 12 is a circuit diagram illustrating a specific configuration of a circuit on the second chip side in the solid-state imaging device according to the second embodiment. FIG. 13 is a timing chart for explaining the circuit operation of the solid-state imaging device according to the second embodiment. FIG. 14 is a layout diagram illustrating a layout example of the multilayer chip in the solid-state imaging device according to the second embodiment. FIG. 15 is a circuit diagram illustrating a specific configuration of a circuit on the first chip side in the solid-state imaging device according to the third embodiment. FIG. 16 is a circuit diagram illustrating a specific configuration of a circuit on the second chip side in the solid-state imaging device according to the third embodiment. FIG. 17 is a layout diagram showing an example of the layout of the multilayer chip in the solid-state imaging device according to the third embodiment. FIG. 18 is a layout diagram illustrating another example of the layout of the laminated chips in the solid-state imaging device according to the third embodiment. FIG. 19 is a block diagram illustrating a configuration example of an imaging apparatus that is an example of the electronic apparatus of the present disclosure.
1. 1. Description of Solid-State Imaging Device, Solid-State Imaging Device Driving Method, and Electronic Device of the Present Disclosure Solid-state imaging device according to the first embodiment (example of column parallel AD conversion method)
2-1. System configuration 2-2. Circuit configuration 2-3. Circuit operation 2-4. Laminated chip layout 2-5. 2. Action and effect of the first embodiment Solid-state imaging device according to the second embodiment (example of pixel parallel AD conversion method)
3-1. System configuration 3-2. Circuit configuration 3-3. Circuit operation 3-4. Laminated chip layout 3-5. 3. Action and effect of the second embodiment Solid-state imaging device according to the third embodiment (another example of a pixel parallel AD conversion method)
4-1. System configuration 4-2. Circuit configuration 4-3. Circuit operation 4-4. Laminated chip layout 4-5. 4. Functions and effects of the second embodiment Other configuration examples Electronic equipment (example of imaging device)
7). Composition of this disclosure
<1. Description of Solid-State Imaging Device, Solid-State Imaging Device Driving Method, and Electronic Device in General of Present Disclosure>
The solid-state imaging device according to the present disclosure includes a signal processing unit, a memory unit, a data processing unit, and a control unit in addition to the pixel array unit. The pixel array section includes unit pixels including photoelectric conversion elements (hereinafter sometimes simply referred to as “pixels”) two-dimensionally arranged in a matrix (matrix). That is, the solid-state imaging device of the present disclosure is an XY address type solid-state device that can read out pixel signals in units of one pixel, a plurality of pixels, or one or a plurality of rows (lines). An imaging device. A CMOS image sensor can be exemplified as a typical XY address type solid-state imaging device.
In this pixel array section, a control line (row control line) is wired for each pixel row and a signal line (column signal line / vertical signal line) is wired for each pixel column with respect to the matrix pixel array. A current source may be connected to each of the signal lines. Then, a signal (analog pixel signal) is read from each pixel of the pixel array portion with respect to this signal line. This reading can be performed, for example, under a rolling shutter that performs exposure in units of one pixel or one line (one row). This readout under the rolling shutter may be referred to as rolling readout.
The signal processing unit includes an AD (analog-digital) converter that digitizes an analog pixel signal read from each pixel of the pixel array unit to the signal line, and converts the AD-converted image data into a frame rate (1 second). The number of images that can be captured per hit) can be transferred to the memory unit at a faster speed (first speed). As described above, by transferring the pixel data to the memory unit at a first speed faster than the frame rate (high-speed transfer), high-speed reading faster than the frame rate can be realized.
The memory unit is not particularly limited. The memory unit may be a non-volatile memory or a volatile memory. The data processing unit may be configured to read pixel data from the memory unit at a first speed, that is, a speed (second speed) slower than the transfer speed of the signal processing unit. Thus, by reading out pixel data at a speed slower than the first speed (low-speed reading), it is possible to realize low power consumption corresponding to the reduction in the operation speed.
Furthermore, when reading out pixel data from the memory unit under the control of the control unit, the pixel data while stopping the operation of the current source connected to each of the signal lines and the operation of at least the AD converter of the signal processing unit. Can be configured to perform intermittent driving. In this way, by performing intermittent driving that stops the operation of the current source and the operation of the AD converter when reading out the pixel data from the memory unit, power is consumed by the amount originally consumed by the current source and the AD converter during the stop period. Therefore, further reduction in power consumption can be achieved.
As described above, a solid-state imaging device capable of performing high-speed reading of pixel data with lower power consumption can be realized. Such a solid-state imaging device, that is, the solid-state imaging device of the present disclosure is used for imaging in an electronic device such as a mobile terminal device, a digital still camera, a single-lens reflex camera, a camcorder, or a surveillance camera having an imaging function such as a mobile phone. Part (image capturing part).
In the solid-state imaging device of the present disclosure including the above-described preferred configuration, the driving method thereof, and the electronic apparatus, when the pixel data is read from the memory unit, the operation of the current source and the operation of the AD converter are stopped. It can be configured to stop in units of vertical synchronization signals. “Stopping in units of vertical synchronization signals” also means “stopping in synchronization with vertical synchronization signals”.
Further, in the solid-state imaging device of the present disclosure including the above-described preferable configuration, the driving method thereof, and the electronic apparatus, the pixel array unit includes the signal processing unit, the memory unit, the data processing unit, and the control unit. The chip may be formed on at least one chip different from the formed chip, and may have a structure in which the chip in which the pixel array portion is formed and at least one other chip are stacked (so-called stacked structure). At this time, the control unit can be configured to control the circuit on the chip side in which the pixel array unit is formed and at least one other circuit on the chip side in synchronization.
In the solid-state imaging device of the present disclosure including the preferable configuration described above, the driving method thereof, and the electronic apparatus, the signal processing unit is configured to output the analog pixel signal read from the pixels of the pixel array unit for each pixel row. The signal processing can be performed in parallel (column parallel) in units of pixel columns.
In addition, the signal processing unit may include a data latch unit and a parallel-serial conversion unit, and the pixel data digitized by the AD converter may be pipeline-transferred to the memory unit. At this time, it is preferable to perform digitization processing by an AD converter within one horizontal period, and transfer the digitized pixel data to the data latch unit within the next one horizontal period. Here, the data latch unit latches the pixel data digitized by the AD converter. The parallel-serial conversion unit converts the pixel data output from the data latch unit from parallel data to serial data.
Alternatively, the signal processing unit may include a data latch unit, a data compression unit, and a parallel-serial conversion unit, and the pixel data digitized by the AD converter may be pipeline-transferred to the memory unit. it can. At this time, it is preferable to perform digitization processing by an AD converter within one horizontal period, and transfer the digitized pixel data to the data latch unit within the next one horizontal period. Here, the data compression unit compresses the pixel data output from the data latch unit. The parallel-serial conversion unit converts the pixel data output from the data compression unit from parallel data to serial data.
Further, in the solid-state imaging device of the present disclosure including the above-described preferable configuration, the driving method thereof, and the electronic apparatus, the signal processing unit includes two or more AD converters, and the two or more AD conversions are performed. The digital signal processing can be performed in parallel in the device. At this time, it is preferable to arrange two or more AD converters separately on both sides of the extension direction of the signal lines of the pixel array section.
Further, in the solid-state imaging device of the present disclosure including the preferable configuration described above, a driving method thereof, and an electronic device, a predetermined number of current sources, signal processing units, and memory units connected to the signal lines are provided. It is possible to adopt a configuration in which each pixel is used as a unit and provided for each unit. At this time, the signal processing unit performs signal processing in parallel (pixel parallel) in units of pixel signals read out for each unit of a predetermined number of pixels from each pixel of the pixel array unit. The signal processing may be performed in a predetermined order for a plurality of pixels.
Moreover, in the solid-state imaging device of the present disclosure including the preferable configuration described above, the driving method thereof, and the electronic device, for the data processing unit, a decoder that specifies a column address for the memory unit; A sense amplifier that reads pixel data at a specified address can be used. At that time, pixel data can be read from the memory portion through the sense amplifier and the decoder.
In the solid-state imaging device of the present disclosure including the preferable configuration described above, the driving method thereof, and the electronic apparatus, the data processing unit is configured to read pixel data from the memory unit during the exposure period. be able to.
Further, in the solid-state imaging device of the present disclosure including the above-described preferable configuration, the driving method thereof, and the electronic apparatus, the current source connected to the signal line is stopped in units of the vertical synchronization signal for the control unit. In this case, the current path between the signal line and the current source can be cut. At this time, it is preferable to apply a fixed potential to the signal line.
<2. Solid-State Imaging Device According to First Embodiment>
FIG. 1 is a schematic perspective view illustrating a configuration example of the solid-state imaging device according to the first embodiment of the present disclosure. Here, the case of a CMOS image sensor will be described as an example of the solid-state imaging device according to the first embodiment. However, the present invention is not limited to application to a CMOS image sensor.
As shown in FIG. 1, the solid-state imaging device 10A according to the first embodiment includes a first chip (semiconductor substrate) 20 and a second chip 30, and the first chip 20 is an upper chip, and the second chip. In this structure, 30 is stacked as a lower chip (so-called stacked structure).
In this stacked structure, the upper first chip 20 is a pixel chip in which a pixel array unit (pixel unit) 21 in which unit pixels 40 including photoelectric conversion elements are two-dimensionally arranged in a matrix is formed. The peripheral portion of the first chip 20 is provided with pad portions 22 1 and 22 2 for electrical connection with the outside, and vias (VIA) for electrical connection with the second chip 30. ) 23 1 and vias 23 2 are provided.
Here, the pad portion 22 1 and the pad portion 22 2 are provided on both the left and right sides of the pixel array portion 21, but a configuration provided on one side of the left and right is also possible. In addition, although the via 23 1 and the via 23 2 are provided on both upper and lower sides with the pixel array portion 21 in between, a configuration provided on one of the upper and lower sides may be employed. Also, a pad portion is provided in the lower second chip 30 to open the first chip 20 and bonding to the pad on the second chip 30 side, or substrate mounting from the second chip 30 by TSV (Through silicon via) It is also possible to adopt a configuration to do so.
The pixel signal obtained from each pixel 40 of the pixel array unit 21 is an analog signal, and this analog pixel signal is transmitted from the first chip 20 to the second chip 30 through the vias 23 1 and 23 2. Become.
The lower second chip 30 includes a signal processing unit 31, a memory unit 32, data processing, as well as a driving unit (not shown) that drives each pixel 40 of the pixel array unit 21 formed on the first chip 20. This is a circuit chip in which peripheral circuit parts such as the part 33 and the control part 34 are formed.
The signal processing unit 31 performs predetermined signal processing including digitization (AD conversion) on the analog pixel signal read from each pixel 40 of the pixel array unit 21. The memory unit 32 stores pixel data that has been subjected to predetermined signal processing by the signal processing unit 31. The data processing unit 33 reads out pixel data stored in the memory 32 in a predetermined order, and performs a process of outputting the data outside the chip.
The control unit 34, for example, based on the reference signals such as the horizontal synchronization signal XHS, the vertical synchronization signal XVS, and the master clock MCK given from the outside of the chip, the driving unit, the signal processing unit 31, the memory unit 32, and The operation of the peripheral circuit unit of the data processing unit 33 is controlled. At this time, the control unit 34 synchronizes the circuit on the first chip 20 side (pixel array unit 21) and the circuit on the second chip 30 side (signal processing unit 31, memory unit 32, and data processing unit 33). It will be controlled while taking.
As described above, the solid-state imaging device 10A formed by laminating the first chip 20 and the second chip 30 only needs to have a size (area) enough to form the pixel array unit 31 as the first chip 20. In addition, the size (area) of the first chip 20 and thus the size of the entire chip can be reduced. Furthermore, since a process suitable for creating the pixel 40 can be applied to the first chip 20 and a process suitable for creating the circuit can be applied to the second chip 30, respectively, the process can be optimized in manufacturing the solid-state imaging device 10A. There is also an advantage that can be achieved.
In addition, an analog pixel signal is transmitted from the first chip 20 side to the second chip 30 side, while a circuit portion that performs analog / digital processing is configured in the same substrate (second chip 30), and the first chip 20 side. High-speed processing can be realized by a configuration in which the circuit of the second chip 30 and the circuit on the second chip 30 side are controlled in synchronization. Incidentally, when adopting a configuration in which pixel signals are transmitted as digital data between different chips, a clock delay occurs due to the influence of parasitic capacitance and the like, which hinders high-speed processing.
FIG. 2 is a circuit diagram illustrating a specific configuration of the circuit on the first chip 20 side and the circuit on the second chip 30 side in the solid-state imaging device 10A according to the first embodiment. As described above, electrical connection between the circuit on the first chip 20 side and the circuit on the second chip 30 side is performed via the vias (VIA) 23 1 and 23 2 shown in FIG. .
(Circuit configuration on the first chip side)
First, the circuit configuration on the first chip 20 side will be described with reference to FIG. On the first chip 20 side, in addition to the pixel array unit 21 in which the unit pixels 20 are arranged in a matrix, each pixel 40 of the pixel array unit 21 is arranged based on an address signal given from the second chip 30 side. A row selection unit 25 for selecting in units of rows is provided. Here, it is assumed that the row selection unit 25 is provided on the first chip 20 side, but a configuration provided on the second chip 30 side is also possible.
As shown in FIG. 2, the unit pixel 40 has, for example, a photodiode 41 as a photoelectric conversion element. In addition to the photodiode 41, the unit pixel 40 includes four transistors, for example, a transfer transistor (transfer gate) 42, a reset transistor 43, an amplification transistor 44, and a selection transistor 45.
Here, for example, N-channel transistors are used as the four transistors 42 to 45. However, the conductivity type combinations of the transfer transistor 42, the reset transistor 43, the amplification transistor 44, and the selection transistor 45 illustrated here are merely examples, and are not limited to these combinations. That is, a combination using a P-channel transistor can be used as necessary.
A transfer signal TRG, a reset signal RST, and a selection signal SEL, which are drive signals for driving the pixel 40, are appropriately supplied from the row selection unit 25 to the unit pixel 40. That is, the transfer signal TRG is applied to the gate electrode of the transfer transistor 42, the reset signal RST is applied to the gate electrode of the reset transistor 43, and the selection signal SEL is applied to the gate electrode of the selection transistor 45.
The photodiode 41 has an anode electrode connected to a low potential power source (for example, ground), and photoelectrically converts received light (incident light) into photocharge (here, photoelectrons) having a charge amount corresponding to the amount of light. Then, the photocharge is accumulated. The cathode electrode of the photodiode 41 is electrically connected to the gate electrode of the amplification transistor 44 through the transfer transistor 42. A node 46 electrically connected to the gate electrode of the amplification transistor 44 is called an FD (floating diffusion / floating diffusion region) part.
The transfer transistor 42 is connected between the cathode electrode of the photodiode 41 and the FD portion 46. A transfer signal TRG whose high level (for example, V DD level) is active (hereinafter referred to as “High active”) is supplied from the row selection unit 25 to the gate electrode of the transfer transistor 42. In response to the transfer signal TRG, the transfer transistor 42 becomes conductive, and the photoelectric charge photoelectrically converted by the photodiode 41 is transferred to the FD unit 46.
The reset transistor 43 has a drain electrode connected to the pixel power source V DD and a source electrode connected to the FD unit 46. A high active reset signal RST is supplied from the row selection unit 25 to the gate electrode of the reset transistor 43. In response to the reset signal RST, the reset transistor 43 becomes conductive, and the FD unit 46 is reset by discarding the charge of the FD unit 46 to the pixel power source V DD .
The amplification transistor 44 has a gate electrode connected to the FD portion 46 and a drain electrode connected to the pixel power source VDD . Then, the amplification transistor 44 outputs the potential of the FD unit 46 after being reset by the reset transistor 43 as a reset signal (reset level) V reset . Further, the amplification transistor 44 outputs the potential of the FD section 46 after the signal charge is transferred by the transfer transistor 42 as a light accumulation signal (signal level) V sig .
For example, the selection transistor 45 has a drain electrode connected to the source electrode of the amplification transistor 44 and a source electrode connected to the signal line 26. A high active selection signal SEL is supplied from the row selection unit 25 to the gate electrode of the selection transistor 45. In response to the selection signal SEL, the selection transistor 45 is turned on, and the unit pixel 40 is selected and the signal output from the amplification transistor 44 is read out to the signal line 26.
As is apparent from the above, from the unit pixel 40, the reset potential of the FD section 46 is set as the reset level V reset , and then the potential of the FD section 46 after the transfer of the signal charge is set as the signal level V sig in order. It is read out to the signal line 26. Incidentally, the signal level V sig includes a component of the reset level V reset .
Here, the selection transistor 45 is configured to be connected between the source electrode of the amplification transistor 44 and the signal line 26, but the circuit is connected between the pixel power supply V DD and the drain electrode of the amplification transistor 44. It is also possible to adopt a configuration.
Further, the unit pixel 40 is not limited to the pixel configuration composed of the above four transistors. For example, a pixel configuration including three transistors in which the amplification transistor 44 has the function of the selection transistor 45, or a pixel configuration in which the transistors after the FD section 46 are shared among a plurality of photoelectric conversion elements (between pixels). There is no limitation on the configuration of the pixel circuit.
(Circuit configuration on the second chip side)
Next, the circuit configuration on the second chip 30 side will be described with reference to FIG. On the second chip 30 side, in addition to the signal processing unit 31, the memory unit 32, the data processing unit 33, and the control unit 34 described above, a current source 35, a decoder 36, a row decoder 37, and an interface (IF) A part 38 and the like are provided.
The current source 35 is connected to each signal line 26 from which a signal is read from each pixel 40 of the pixel array unit 21 for each pixel column. The current source 35 has, for example, a so-called load MOS circuit configuration including a MOS transistor whose gate potential is biased to a constant potential so as to supply a certain current to the signal line 26. The current source 35 including the load MOS circuit supplies the constant current to the amplification transistor 44 of the unit pixel 40 in the selected row, thereby operating the amplification transistor 44 as a source follower.
When the decoder 36 selects each pixel 40 of the pixel array unit 31 in units of rows under the control of the control unit 34, the decoder 36 gives an address signal for designating the address of the selected row to the row selection unit 25. The row decoder 37 designates a row address when writing pixel data to the memory unit 32 or reading pixel data from the memory unit 32 under the control of the control unit 34.
The signal processing unit 31 includes at least an AD converter 51 that digitizes (AD converts) an analog pixel signal read from each pixel 40 of the pixel array unit 21 through the signal line 26, and a pixel for the analog pixel signal. The signal processing (column parallel AD) is performed in parallel in units of columns.
The signal processing unit 31 further includes a reference voltage generation unit 52 that generates a reference voltage used when AD conversion is performed by the AD converter 51. The reference voltage generation unit 52 generates a reference voltage having a so-called ramp (RAMP) waveform (gradient waveform) in which the voltage value changes stepwise as time passes. The reference voltage generation unit 52 can be configured using, for example, a DAC (digital-analog conversion) circuit.
The AD converter 51 is provided for each pixel column of the pixel array unit 21, that is, for each signal line 26, for example. That is, the AD converter 51 is a so-called column-parallel AD converter that is arranged by the number of pixel columns of the pixel array unit 21. Then, the AD converter 51 generates a pulse signal having a magnitude (pulse width) in the time axis direction corresponding to the magnitude of the level of the pixel signal, for example, and sets the length of the pulse width period of the pulse signal. The AD conversion process is performed by measuring.
More specifically, as shown in FIG. 2, the AD converter 51 has at least a comparator (COMP) 511 and a counter 512. The comparator 511 receives the analog pixel signal (the signal level V sig and the reset level V reset described above) read from each pixel 40 of the pixel array unit 21 through the signal line 26 as a comparison input, and is supplied from the reference voltage generation unit 52. The reference voltage Vref of the ramp wave is used as a standard input, and both inputs are compared.
The comparator 511 outputs, for example, when the reference voltage V ref is larger than the pixel signal, the output is in the first state (for example, high level), and when the reference voltage V ref is equal to or lower than the pixel signal, the output is output. A second state (eg, low level) is entered. The output signal from the comparator 511 is a pulse signal having a pulse width corresponding to the level of the pixel signal.
For example, an up / down counter is used as the counter 512. The counter 512 is supplied with the clock CK at the same timing as the supply start timing of the reference voltage V ref to the comparator 511. The counter 512 which is an up / down counter performs a down (DOWN) count or an up (UP) count in synchronization with the clock CK, so that the period of the pulse width of the output pulse of the comparator 511, that is, the comparison operation The comparison period from the start to the end of the comparison operation is measured. During this measurement operation, the counter 512 counts down the reset level V reset and the signal level V sig sequentially read from the unit pixel 40 with respect to the reset level V reset and increases with respect to the signal level V sig . Count.
By this down count / up count operation, the difference between the signal level V sig and the reset level V reset can be obtained. As a result, the AD converter 51 performs a CDS (Correlated Double Sampling) process in addition to the AD conversion process. Here, the “CDS processing” removes the fixed pattern noise unique to the pixel such as reset noise of the unit pixel 40 and threshold variation of the amplification transistor 44 by taking the difference between the signal level V sig and the reset level V reset. It is processing to do. The count result (count value) of the counter 512 becomes a digital value obtained by digitizing the analog pixel signal.
(Example of the configuration of the signal processing unit)
The signal processing unit 31 according to this example includes a data latch unit 53 and a parallel-serial (hereinafter abbreviated as “parasiri”) conversion unit 54 in addition to the AD converter 51, and is digitized by the AD converter 51. The pipeline data is transferred to the memory unit 32 by pipeline. At that time, the signal processing unit 31 performs digitization processing by the AD converter 51 within one horizontal period, and performs processing of transferring the digitized pixel data to the data latch unit 53 within the next one horizontal period.
On the other hand, the memory unit 32 is provided with a column decoder / sense amplifier 39 as its peripheral circuit. The row decoder 37 (see FIG. 2) described above designates a row address for the memory unit 32, whereas the column decoder designates a column address for the memory unit 32. In addition, the sense amplifier amplifies the weak voltage read from the memory unit 32 through the bit line to a level that can be handled as a digital level. The pixel data read through the column decoder / sense amplifier 39 is output to the outside of the second chip 30 via the data processing unit 33 and the interface unit 38.
Here, the case where there is one column-parallel AD converter 51 is taken as an example, but the present invention is not limited to this, and two or more AD converters 51 are provided, and these two or more AD converters 51 are provided. It is also possible to adopt a configuration for performing digitization processing in parallel.
In this case, the two or more AD converters 51 are arranged separately in the extending direction of the signal line 26 of the pixel array unit 21, that is, on both the upper and lower sides of the pixel array unit 21. When two or more AD converters 51 are provided, two (two systems) of data latch units 53, parallel-serial conversion units 54, memory units 32, and the like are also provided.
As described above, in a solid-state imaging device having a configuration in which, for example, two systems of AD converters 51 are provided, row scanning is performed in units of two pixel rows. Then, the signal of each pixel in one pixel row is read out on one side in the vertical direction of the pixel array unit 21, and the signal of each pixel in the other pixel row is read out on the other side in the vertical direction of the pixel array unit 21, respectively. Digitization processing is performed in parallel by the two AD converters 51. Subsequent signal processing is also performed in parallel. As a result, pixel data can be read at a higher speed than when row scanning is performed in units of one pixel row.
Next, the circuit operation of the solid-state imaging device 10A according to the first embodiment having the above-described configuration will be described with reference to the timing chart of FIG.
(High-speed reading)
First, pixel signals from the pixels 40 of the pixel array unit 21 on the first chip 20 side are read at a reading speed faster than the frame rate, for example, 240 [fps] by rolling reading performed under a rolling shutter. Reads at high speed. The analog pixel signal read by the rolling readout is transmitted from the first chip 20 to the signal processing unit 31 on the second chip 30 side via vias (VIA) 23 1 and 23 2 .
Next, in the signal processing unit 31, the analog pixel signal is digitized by the AD converter 51. The pixel data digitized by the AD converter 51 is pipeline-transferred to the memory unit 32 and stored in the memory unit 32. At this time, the signal processing unit 31 performs digitization processing by the AD converter 51 within one horizontal period, and performs pipeline transfer to the memory unit 32 within the next one horizontal period.
The speed at which the digitized pixel data is transferred to the memory unit 32 is a reading speed by rolling reading, that is, 240 [fps]. Accordingly, the signal processing unit 31 transfers the pixel data digitized by the AD converter 51 to the memory unit 32 at a speed (first speed) faster than the frame rate.
By the way, in the rolling readout performed under the rolling shutter, as is well known, since the exposure timing is different for each pixel or line (row) in one screen, there is distortion (hereinafter sometimes referred to as “rolling distortion”). appear.
On the other hand, in the present embodiment, the pixel signal is read out from each of the unit pixels 40 by high-speed reading faster than the frame rate, and the digitized pixel data is read out at a first speed faster than the frame rate. 32 is transferred at high speed and stored. Thus, by temporarily storing the pixel data in the memory unit 32, it is possible to synchronize the pixel data, and thus it is possible to prevent the occurrence of rolling distortion.
The pixel data stored in the memory unit 32 is read by the data processing unit 33 via the column decoder / sense amplifier 39 at a second speed that is slower than the first speed, for example, 80 [fps]. The data is output to the outside of the second chip 30 via the interface unit 38. Thus, by reading out pixel data from the memory unit 32 at a second speed that is slower than the first speed (so-called low-speed reading), it is possible to reduce power consumption by the amount that the operation speed has slowed down. it can.
As is apparent from the timing chart of FIG. 4, reading of the pixel data from the memory unit 32 is performed during the exposure period. Incidentally, the conventional technique described in Patent Document 1 employs a configuration in which the pixel data is stored in the memory unit, and then enters a standby state, and then photographing is started, so that real-time image photographing cannot be performed. In contrast, the present embodiment employs a configuration in which pixel data is read from the memory unit 32 during the exposure period, so that pixel data of moving images and still images can be read in real time.
Further, as the memory unit 32, various types of memories can be used regardless of whether they are nonvolatile or volatile. For example, the volatile memory (for example, DRAM) can be reduced to 50 [msec] by performing the process from the start of writing pixel data to the memory unit 32 to the completion of reading of the pixel data by the data processing unit 33 at a speed of 20 [fps] or more. It is also possible to eliminate the refresh operation requiring a degree.
On the other hand, in the current CMOS image sensor, AD conversion and data output are performed by pipeline transfer of about several [μsec]. The writing speed of DRAM is equal or less, that is, several [μsec] or less. Therefore, with the pipeline configuration as shown in FIG. 3, it is possible to perform from pixel signal reading to pixel data writing in the memory unit 32.
Specifically, the AD converter 51 performs digitization processing within one horizontal period (XHS), transfers the digital data to the data latch unit 53 within the next one horizontal period, and the data latch unit 53 Save to. Thereafter, the parallel-serial conversion unit 54 converts the parallel signal into a serial signal, and writes the pixel data into the memory unit 32 under the designation of the row address by the row decoder 37 and the designation of the column address by the column decoder of the column decoder / sense amplifier 39. . In other words, the pixel data is AD converted in parallel by the AD converter 51, latched in the data latch unit 53, and then written in the memory unit 32 in parallel to realize pipeline transfer. In addition to the configuration of pipeline transfer in which data can be written from the data latch unit 53 to the memory unit 32 within one horizontal period, the data latch unit 53 stores the memory write and the next row of digital data in the next horizontal period. A method of pipeline transfer stored in the data latch unit 53 can also be adopted.
In the present embodiment, for the purpose of lowering power consumption, when reading pixel data from the memory unit 32, the operation of the current source 35 connected to each of the signal lines 26 and at least the AD converter of the signal processing unit 31 are used. For example, the operation of 51 is stopped in units of the vertical synchronization signal XVS. Here, “when reading out pixel data from the memory unit 32” can be said to be after the pixel data is stored in the memory unit 32 at high speed by pipeline transfer, or during the exposure period.
Incidentally, for the purpose of reducing power consumption, there is a conventional technique in which the power supply of an analog front-end circuit including an AD converter is cut off during a photographing (exposure) period so as to enter a standby state (for example, JP-A-2006-81048). reference). Since the related art employs a configuration in which the pixel signal is read out and is in a standby state from the start of exposure, high-speed driving cannot be performed, and the stop period varies depending on the exposure time. The effect of reducing power consumption is also limited.
On the other hand, in the present embodiment, as shown in the timing chart of FIG. 4, for example, 240 [fps] is one vertical period (a period between the vertical synchronization signals XVS), and one frame (1 V) in four vertical periods. = 1/60 [sec]). Then, during the three vertical periods after the pixel signal is read, the operation of the current source 35 used at the time of reading the pixel signal and at least the operation of the AD converter 51 are stopped.
Thus, the power supply design is facilitated by stopping the circuit operation in synchronization with the vertical synchronization signal XVS (in units of the vertical synchronization signal XVS) without depending on the exposure period. The operation of the current source 35 and the stop of the operation of at least the AD converter 51 of the signal processing unit 31 are executed under the control of the control unit 34.
In this embodiment, exposure is started by resetting the unit pixel 40 (shutter operation) after 240 [fps] high-speed rolling readout. It is possible to stop the operations of the current source 35 and the AD converter 51 during the exposure period. Therefore, by stopping each operation of the current source 35 and the AD converter 51 for a period from the start of reading pixel data from the memory unit 32 of the current frame to the start of reading pixel signals from the unit pixel 40 of the next frame, The power consumption can be reduced by the amount originally consumed by the current source 35 and the AD converter 51 during the stop period.
The operation of the current source 35 can be stopped by cutting (cutting) the current path between the signal line 26 and the current source 35 under the control of the control unit 34. More specifically, for example, as shown in FIG. 5, by inserting the transistors Q 1 between the signal line 26 and the current source 35 to the transistor Q 1 in a non-conducting state by a low level control signal, The operation of the current source 35 can be stopped.
Here, when the operation of the current source 35 is stopped, not only the current path between the signal line 26 and the current source 35 is interrupted but also a fixed potential may be applied to the signal line 26. More specifically, for example, as shown in FIG. 5, connects the transistor Q 2 between the signal line 26 and a fixed potential, the transistor Q 2, conducted by the inverted control signal of the control signal through the inverter INV By setting the state, a fixed potential can be applied to the signal line 26.
Thus, when the operation of the current source 35 is stopped, the fixed potential is applied to the signal line 26 in order to eliminate the influence on the FD portion 46 of the unit pixel 40 due to the signal line 26 being in a floating state. is there. That is, when the signal line 26 is in a floating state, for example, when the potential of the signal line 26 fluctuates, the fluctuation of the potential may cause the potential of the FD portion 46 to fluctuate due to coupling due to the parasitic capacitance of the amplification transistor 44. In order to eliminate such an influence on the FD section 46, a fixed potential is applied to the signal line 26.
Depending on the setting of the exposure time, the shutter operation may span the first vertical period (1XVS) and the next vertical period (2XVS). In such a case, it may be controlled to stop the operation of the current source 35 after the shutter operation. Thus, by stopping the operation of the current source 35 after the shutter operation, the influence of the standby operation of the current source 35, that is, the fluctuation of the power supply potential and the fluctuation of the potential of the signal line 26 can be prevented. If the shutter start is after the next vertical period (2XVS), there is no influence of the standby operation of the current source 35.
(Data storage in the memory part and data output from the memory part)
Next, an operation of storing data from the data latch unit 53 to the memory unit 32 and outputting data from the memory unit 32 will be described with reference to FIG. In FIG. 6, the AD converter 31 and accompanying circuit portions, that is, two circuit portions such as the data latch portions 53 (53 1 , 53 2 ) and the memory portions 32 (32 1 , 32 2 ) are provided. An example is given. However, basically the same can be said for one system.
The pixel data after AD conversion is latched in the data latch unit 53. With respect to the latched data, the parallel-serial conversion unit 54 caches 16 kbits in the column decoder in units of 128, for example. Next, data is stored in the memory unit 32 using a sense amplifier. In FIG. 6, the memory unit 32 has a four-bank configuration, but this is only an example, and the number of banks should be determined so that image data can be stored in units of horizontal pixels.
In this embodiment, a pipeline configuration is employed in which data is written to the bits of each memory unit in parallel with the rolling read, so that data storage from the data latch unit 53 to the memory unit 32 is completed in one vertical period. Can do. After completion of data writing to the memory unit 32, the operations of the current source 35 and the AD converter 51 are stopped as described above, and reading of data from the memory unit 32 is started.
Regarding the reading of data from the memory unit 32, in the three vertical periods (80 [fps] in this example) during the exposure period, the data is rearranged by the multiplexer 55 (55 1 , 55 2 ) and the data processing unit 33. The data is output from the interface unit 38 while being synthesized. When data is written to the memory unit 32, no data is output from the memory unit 32. Therefore, power consumption can be reduced by a method such as fixing the output of the interface unit 38. Specifically, for example, the power consumption can be reduced by stopping the clock supplied to the output unit of the interface unit 38.
(Another example of the configuration of the signal processing unit)
The signal processing unit 31 according to this example includes a data compression unit 56 in addition to the AD converter 51, the data latch unit 53, and the parallel-serial conversion unit 54, and the pixel data digitized by the AD converter 51 is processed. It has a pipeline configuration for pipeline transfer to the memory unit 32. At that time, the signal processing unit 31 performs digitization processing by the AD converter 51 within one horizontal period, and transfers the digitized pixel data to the data latch unit 53 within the next one horizontal period.
The data compression unit 56 is provided, for example, between the data latch unit 53 and the parallel-serial conversion unit 54, compresses the pixel data output from the data latch unit 53, and supplies the compressed pixel data to the parallel-serial conversion unit 54. As a compression method of the data compression unit 56, for example, DPCM (differential pulse-code modulation) can be exemplified.
As described above, the data compression unit 56 is provided between the data latch unit 53 and the memory unit 32, and the data compression unit 56 compresses the data before storing the data in the memory unit 32, thereby reducing the memory capacity of the memory unit 32. Can be reduced. And by reducing the capacity of the memory unit 32, the layout area of the second chip 30 on which the signal processing unit 31 is mounted can be reduced.
[2-4. Multilayer chip layout]
Here, as described above, a multilayer chip in the case of adopting a configuration in which a plurality of systems, for example, two systems, are provided for the AD converter 51 and the circuit portions associated therewith, and the signals of the respective pixels in the two pixel rows are processed in parallel. That is, consider the layout of a chip formed by stacking the first chip 20 and the second chip 30.
When adopting a configuration in which, for example, two systems of AD converters 51 and circuit portions associated therewith are employed, signals of each pixel in two pixel rows are sent to both sides in the extending direction of the signal line 26 of the pixel array unit 21, that is, the pixel array unit 21 Reading will be performed on both the upper and lower sides.
Incidentally, when adopting a configuration in which the memory unit is arranged on the same substrate (chip) as the pixel array unit as in the prior art described in Patent Document 1, AD converters and the like are arranged above and below the pixel array unit. Accordingly, it is necessary to divide the memory unit vertically. In that case, the layout distance of the output unit of the memory unit requires a distance of about (the size of the pixel array unit in the vertical direction + the size of the memory unit in the vertical direction), and the layout of the data output unit has a different configuration. This increases the chip size. In addition, in a clock synchronization method such as LVDS (low voltage differential), it is necessary to have a different system clock, which leads to an increase in the number of channels of the signal processing chip.
On the other hand, in the present embodiment, the first chip 20 in which the pixel array unit 21 is formed, the signal processing unit 31 including the AD converter 51, the memory unit 32, the data processing unit 33, and the control unit 34 are provided. A configuration of a laminated chip formed by laminating the formed second chip 30 is adopted. As a result, as shown in FIG. 8, the AD converters 51 1 and 51 2 are arranged on both the upper and lower sides of the second chip 30 (which can be said to be the upper and lower sides of the pixel array unit 21). The memory units 32 1 and 32 2 can be arranged adjacent to each other between 1 and 51 2 .
As described above, since the memory units 32 1 and 32 2 can be arranged adjacent to each other, the data output units (data output paths) of the memory units 32 1 and 32 2 can be configured together. As a result, data can be output through the same output unit, and only one set of clock synchronization signals is required. Therefore, an increase in the number of channels of the signal processing chip at the subsequent stage can be prevented. Incidentally, the control unit 34 is provided in an empty area such as between the memory unit 32 1 and the memory unit 32 2 .
In the above layout example, the case where a configuration in which two systems of AD converters 51 and accompanying circuit parts are provided has been described as an example. However, three or more systems are provided, and the degree of parallel readout of pixel signals from the pixel array unit 21 is increased. The same can be said when adopting a configuration to raise. For example, a layout sequence in the case of adopting a configuration in which four systems of AD converters 51 and accompanying circuit portions are employed will be described below.
FIG. 9 is a layout diagram showing a layout example 1 of the multilayer chip in the case of adopting a configuration in which four systems of AD converters 51 and accompanying circuit portions are provided. In the first layout example, two vias (VIA) are provided in the central portion of the pixel array unit 21 in the vertical direction, and the signals of each pixel in the four pixel rows are sent to the two vias on the upper and lower sides of the pixel array unit 21. Data is simultaneously read out to the second chip 30 side through 23 1 , 23 2 and two systems of vias 23 3 , 23 4 at the center.
On the second chip 30 side, four AD converters 51 1 to 51 4 are arranged in the vicinity of each of the vias 23 1 to 23 4 . Further, it arranged memory unit 32 1, 32 3 between the AD converter 51 1 and AD converter 51 3, the memory unit 32 2 between the AD converter 51 2 and AD converter 51 4, 32 4 Are arranged adjacent to each other. As described above, even when the AD converter 51 and the accompanying circuit portions are provided in four systems, the memory units 32 1 and 32 3 and the memory units 32 2 and 32 4 can be arranged adjacent to each other. As a result, even in this layout example 1, the same operation and effect as in the layout example of FIG. 8 can be obtained.
FIG. 10 is a layout diagram showing a layout example 2 of the laminated chip in the case of adopting a configuration in which four systems of AD converters 51 and accompanying circuit portions are provided. In the second layout example, similarly to the layout example of FIG. 8, two systems of vias 23 1 and 23 2 are provided on both upper and lower sides of the pixel array unit 21.
In the second chip 30 side, two AD converters 51 1 in the vicinity of one of the vias 23 1, 51 3 are positioned adjacent, 2 other via 23 2 two AD converters in the vicinity of 51 , 51 4 are disposed adjacent. Between the AD converter 51 3 and the AD converter 51 4 , a memory unit 32 13 corresponding to the AD converters 51 1 and 51 3 and a memory unit 32 24 corresponding to the AD converters 51 2 and 51 4 and Are arranged adjacent to each other. In the case of this layout example 2, and a memory unit 32 13 and the memory unit 32 24 can be placed adjacent. As a result, even in the second layout example, the same operations and effects as in the layout example of FIG. 8 can be obtained.
[2-5. Action and Effect of First Embodiment]
According to the solid-state imaging device 10A according to the first embodiment described above, the following actions and effects can be obtained. That is, the memory unit 32 is mounted, and the low-speed reading is performed by intermittent driving that stops the operation of the current source 35 and the AD converter 51 when performing high-speed transfer to the memory unit 32 and reading of pixel data from the memory unit 32. By performing the above, high-speed reading of pixel data can be realized with lower power consumption. Further, in the signal processing unit 31, not only the AD converter 51 but also the operation of other circuit parts is stopped, thereby further reducing power consumption.
Further, by reducing the reading speed by the data processing unit 33, that is, the data output rate, than the transfer rate of the pixel data to the memory unit 32, the number of channels of the interface unit 38 can be reduced and the signal processing block ( For example, the processing speed of DSP) can be reduced. This can contribute to lower power consumption of the entire system including the signal processing block at the subsequent stage.
In addition, the first chip 20 and the second chip 30 are connected to each other as a stacked chip, and the circuit on the first chip 20 side and the circuit on the second chip 30 side are synchronized under the control of the control unit 34. As a result, since the data after AD change can be pipeline-transferred to the memory unit 32, synchronous design is facilitated.
In addition, since pixel data is read from the memory unit 32 during the exposure period, the pixel data is stored in the memory unit, and then enters a standby state. In addition, pixel data of moving images and still images can be read out. Therefore, real-time imaging is possible.
Further, when the data compression unit 56 is provided between the data latch unit 53 and the memory unit 32 and the data compression unit 56 compresses the data and then stores the data in the memory unit 32, Since the memory capacity can be reduced, the layout area of the second chip 30 can be reduced.
Also, there is an advantage that rolling distortion can be further improved by providing two or more AD converters 51 and accompanying circuit portions and pipeline-transferring the data after AD conversion to the memory unit 32.
<3. Solid-State Imaging Device According to Second Embodiment>
Subsequently, a solid-state imaging device according to the second embodiment of the present disclosure will be described. Here, as in the first embodiment, the case of a CMOS image sensor will be described as an example of the solid-state imaging device according to the second embodiment. However, the present invention is not limited to application to a CMOS image sensor.
Similarly to the solid-state imaging device according to the first embodiment, the solid-state imaging device according to the second embodiment has a stacked structure in which the first chip 20 and the second chip 30 are stacked. A pixel array unit (pixel unit) 21 is formed on the first chip 20 side, and a signal processing unit 31 including an AD converter 51 on the second chip 30 side, a memory unit 32, a data processing unit 33, and a control unit. The circuit portion such as 34 is formed.
FIG. 11 is a circuit diagram illustrating a specific configuration of a circuit on the first chip side in the solid-state imaging device according to the second embodiment, and FIG. 12 illustrates the second chip side in the solid-state imaging device according to the second embodiment. It is a circuit diagram which shows the specific structure of this circuit.
The solid-state imaging device 10B according to this embodiment sets a predetermined number of pixels 40 of the pixel array unit 21 as a group (unit), reads pixel signals from each pixel 40 for each group, and reads the read pixel signals as group units. Therefore, the signal processing including AD conversion is performed in parallel. That is, the solid-state imaging device 10A according to the first embodiment is a column-parallel AD conversion system that performs AD conversion of pixel signals in units of pixel columns, whereas the solid-state imaging device 10B according to the second embodiment. Is a pixel parallel AD conversion method in which AD conversion is performed in parallel in units of groups of a predetermined number of pixels.
For example, when a predetermined number of pixels are grouped (one unit), a plurality of adjacent pixels belonging to the same pixel row are set as one unit, or a plurality of adjacent pixels in the vertical and horizontal directions are set as one unit. Can be considered. Further, the present invention is not limited to a configuration in which pixel signals are read out in units of groups with a plurality of pixels as one unit, and ultimately, a configuration in which pixel signals are read out in units of individual pixels may be employed.
In the configuration of this embodiment, vias (VIA) 23 that connect the pixel array unit 21 on the first chip 20 side and the signal processing unit 31 on the second chip 30 side are required in units of groups or pixels. The vias 23 for electrical connection between the chips can be realized by a well-known inter-wiring junction technique. The pixel signals read out in units of groups or pixels are transmitted from the first chip 20 side to the second chip 30 side through vias 23 provided in group units or pixel units.
Since the configuration of pixel parallel AD conversion is employed, a column selection unit 27 is provided on the first chip 20 side in addition to the pixel array unit 21 and the row selection unit 25 as shown in FIG. . The column selection unit 27 selects each pixel 40 of the pixel array unit 21 in group units (or pixel units) in the pixel column arrangement direction (row direction) based on the address signal given from the second chip 30 side. To do. Here, the configuration in which the row selection unit 25 and the column selection unit 27 are provided on the first chip 20 side is employed, but a configuration in which the row selection unit 25 and the column selection unit 27 are provided on the second chip 30 side may be employed.
Further, the unit pixel 40 is configured to include two selection transistors 45 and 47 in addition to the transfer transistor 42, the reset transistor 43, and the amplification transistor 44. The two selection transistors 45 and 47 are both connected in series to the amplification transistor 44. One selection transistor 45 is driven by a row selection signal VSEL provided from the row selection unit 25. The other selection transistor 47 is driven by a column selection signal HSEL provided from the column selection unit 27.
Note that under the driving by the row selection unit 25 and the column selection unit 27, selective scanning is performed in units of groups, and signals of a plurality of pixels in the group are transmitted to the second chip 30 side through one via 23. Therefore, pixel signals are read out in a predetermined order from a plurality of pixels in the group. On the second chip 30 side, analog pixel signals read for each group of a predetermined number of pixels are subjected to signal processing in a predetermined order (a reading order of pixel signals) for a plurality of pixels in the group. become.
Corresponding to the unit pixels 40 being grouped in units of a predetermined number, and vias 23 being provided for each group, signal lines connected to the vias 23 on the second chip 30 as shown in FIG. 26 is wired. A current source 35 is connected to the signal line 26, and an AD converter 51 and further a memory unit 32 are connected to the signal line 26.
That is, the signal processing unit 31 including the signal line 26, the current source 35, the AD converter 51, the memory unit 32, and the like is provided in units of groups each having a predetermined number of pixels. The memory unit 32 can be exemplified by a DRAM, but is not particularly limited. That is, as in the case of the first embodiment, the memory unit 32 may be a volatile memory or a non-volatile memory.
In the solid-state imaging device 10A according to the first embodiment adopting the above-described column parallel AD conversion method, AD conversion is performed during the horizontal period (XHS) and data is output. In order to read data at a higher frame rate, it is necessary to increase the number of pixels to be subjected to AD conversion at the same time. In order to increase the number of pixels to be subjected to AD conversion at the same time, it is necessary to perform AD conversion processing not in column parallel but in pixel parallel (unit of plural pixels).
If the readout speed can be increased by the pixel parallel AD conversion, the AD converter 51 can be stopped longer by that amount, so that the power consumption can be further reduced. As an example, by performing sensor reading (reading out pixel signals) at a reading speed of 960 [fps] and performing data output from the memory unit 32 at a speed of 64 [fps], the operation period of the AD converter 51 is It is possible to make it 1/10 or less of the data output period.
Next, the circuit operation of the solid-state imaging device 10B according to the second embodiment having the above-described configuration will be described with reference to the timing chart of FIG.
For reading pixel signals at a reading speed of 960 [fps], for example, about each pixel 40 of the pixel array unit 21, about 250 pixels, for example, 16 × 16 pixels are set as one unit (group). When the AD conversion time in the AD converter 51 is 4 [μsec], a pixel signal of 250 pixels can be read out in a time of 1 [msec] or less. However, the numerical value illustrated here is an example, and is not limited to these numerical values.
A pixel unit (group) having 16 × 16 pixels as one unit is selected by addressing using a row selection signal VSEL provided from the row selection unit 25 and a column selection signal HSEL provided from the column selection unit 27. Then, an analog converter signal read from one pixel in the pixel unit selected by the row selection signal VSEL and the column selection signal HSEL is AD converted by the AD converter 51.
At the time of AD conversion, CDS processing is performed by down-counting with respect to the reset level V reset in the counter 512 and up-counting with respect to the signal level V sig . The pixel data after the CDS processing is written into the memory unit 32 under the designation of the row address by the row decoder 37 and the designation of the column address by the column decoder of the column decoder / sense amplifier 39.
The row selection unit 25 and the column selection unit 27 perform selective scanning in units of pixel units (groups), while a plurality of pixels in the selected pixel unit are arranged in parallel in a predetermined order in units of pixel units. Pixel selective scanning is performed. An example of selection of a pixel in the pixel unit is selection by a raster scan method.
Thereafter, the remaining pixels in the pixel unit are subjected to pixel selection and AD conversion by the raster scan method by the row selection signal VSEL and the column selection signal HSEL, and the pixel data after the CDS processing is stored in the memory unit 32. The data stored in the memory unit 32 can be output (read) at a low speed by reading through the column decoder / sense amplifier 39.
Then, similarly to the solid-state imaging device 10A according to the first embodiment, when reading the pixel data from the memory unit 32, the operation of the current source 35 and the operation of at least the AD converter 51 of the signal processing unit 31 are stopped. Take control. Here, since the solid-state imaging device 10B according to the present embodiment employs the pixel parallel AD conversion method, the pixel signal readout speed can be increased. As a result, the AD converter 51 can be stopped for a longer period of time, so that lower power consumption can be achieved.
[3-4. Multilayer chip layout]
FIG. 14 is a layout diagram illustrating a layout example of the multilayer chip in the solid-state imaging device 10B according to the second embodiment.
As shown in FIG. 14, in the first chip 20, the pixel array unit 21 has a two-dimensional array of pixel units (groups) each having a predetermined number of pixels as a unit, and a via 23 is formed for each pixel unit. It has been configured. On the other hand, in the second chip 30, the signal processing unit 31 includes a circuit unit (pixel AD unit in the drawing) including the AD converter 51 and the memory unit 32 corresponding to the pixel unit of the pixel array unit 21. The via 23 is formed corresponding to the pixel unit for each pixel AD unit.
11 exemplifies a case where the row selection unit 25 and the column selection unit 27 are provided on the first chip 20 side. However, as illustrated in the layout example of FIG. It is also possible to adopt a configuration provided as peripheral circuits (HSEL, VSEL). Adopting such a configuration has an advantage that a larger area of the first chip 20 can be used as a region of the pixel array unit 21.
[3-5. Action and Effect of Second Embodiment]
According to the solid-state imaging device 10B according to the second embodiment described above, the following operations and effects are basically obtained in addition to the operations and effects described above in the solid-state imaging device 10A according to the first embodiment. be able to. That is, since the pixel parallel AD conversion method can increase the pixel signal reading speed, the AD converter 51 can be stopped for a long time. Therefore, further reduction in power consumption can be achieved as compared with the solid-state imaging device 10A according to the first embodiment of the column parallel AD conversion method.
<4. Solid-State Imaging Device According to Third Embodiment>
Subsequently, a solid-state imaging device according to a third embodiment of the present disclosure will be described. Here, as in the first and second embodiments, the case of a CMOS image sensor will be described as an example of the solid-state imaging device according to the third embodiment. However, the present invention is not limited to application to a CMOS image sensor.
Similarly to the solid-state imaging devices according to the first and second embodiments, the solid-state imaging device according to the third embodiment has a stacked structure in which the first chip 20 and the second chip 30 are stacked. A pixel array unit (pixel unit) 21 is formed on the first chip 20 side, and a signal processing unit 31 including an AD converter 51 on the second chip 30 side, a memory unit 32, a data processing unit 33, and a control unit. The circuit portion such as 34 is formed.
FIG. 15 is a circuit diagram illustrating a specific configuration of the circuit on the first chip side in the solid-state imaging device according to the third embodiment, and FIG. 16 is the second chip side in the solid-state imaging device according to the third embodiment. It is a circuit diagram which shows the specific structure of this circuit.
The solid-state imaging device 10C according to the present embodiment also adopts a pixel parallel AD conversion method, similarly to the solid-state imaging device 10B according to the second embodiment. That is, the solid-state imaging device 10C according to the present embodiment groups a predetermined number of pixels 40 of the pixel array unit 21 as a group, reads pixel signals from each pixel 40 for each group, and reads the read pixel signals in units of groups. The signal processing including AD conversion is performed in parallel.
However, the solid-state imaging device 10C according to the present embodiment is different from the solid-state imaging device 10B according to the second embodiment in the following points. That is, the solid-state imaging device 10B according to the second embodiment employs a configuration in which the memory unit 32 is provided together with the AD converter 51 in the signal processing unit 31, that is, a configuration in which the AD converter 51 and the memory unit 32 are mounted together. ing. In contrast, the solid-state imaging device 10C according to the present embodiment employs a configuration in which the memory unit 32 is provided outside the signal processing unit 31.
The grouping of unit pixels 40 in units of a predetermined number is the same as in the second embodiment. As an example, a plurality of adjacent pixels belonging to the same pixel row are set as one unit, or adjacent vertically and horizontally. For example, a plurality of pixels may be set as one unit. Further, the present invention is not limited to a configuration in which pixel signals are read out in units of groups with a plurality of pixels as one unit, and ultimately, a configuration in which pixel signals are read out in units of individual pixels may be employed.
Even in the configuration of the present embodiment, the via (VIA) 23 that connects the pixel array unit 21 on the first chip 20 side and the signal processing unit 31 on the second chip 30 side is required in units of groups or pixels. The vias 23 for electrical connection between the chips can be realized by a well-known inter-wiring junction technique. The pixel signals read out in units of groups or pixels are transmitted from the first chip 20 side to the second chip 30 side through vias 23 provided in group units or pixel units.
The configuration on the first chip 20 side is basically the same as that of the second embodiment. That is, since the configuration of the pixel parallel AD conversion is adopted, each pixel of the pixel array unit 21 is provided on the first chip 20 side in addition to the pixel array unit 21 and the row selection unit 25 as shown in FIG. A column selection unit 27 that selects 40 in the row direction in units of groups (or pixels) is provided. In addition, about the row selection part 25 and the column selection part 27, it is also possible to take the structure provided in the 2nd chip | tip 30 side.
Corresponding to the unit pixels 40 being grouped in units of a predetermined number and the vias 23 being provided for each group, the signal lines connected to the vias 23 on the second chip 30 as shown in FIG. 26 is wired. A current source 35 is connected to the signal line 26. Further, a signal processing unit 31 is provided for each signal line 26.
The signal processing unit 31 has a configuration in which the AD converter 51 and the memory unit 32 are mixedly mounted in the second embodiment, whereas the memory unit 32 is not included in the present embodiment. ing. That is, in the present embodiment, a configuration in which the memory unit 32 is provided outside the signal processing unit 31 is employed.
The AD converter 51 includes a comparator (COMP) 511, an Nbit (N is an integer of 2 or more) counter 512, and a latch unit 513. In the AD converter 51, the latch unit 513 includes unit circuits (latch circuits) for N bits of the counter 512, and is AD-converted by the operations of the comparator 511 and the counter 512, and the counter 512 performs an up / down counting operation. The digital data (pixel data) for one pixel subjected to CDS is latched.
As the row decoder 37, a row decoder 37 1 for selecting the latch unit 513 in the signal processing unit 31, a row decoder 37 2 to select each cell in the memory unit 32 in units of rows are provided.
Next, a circuit operation of the solid-state imaging device 10C according to the third embodiment having the above-described configuration will be described.
For one pixel in the pixel unit selected by addressing by the row selection signal VSEL and the column selection signal HSEL, the pixel signal is AD-converted by the AD converter 51, and CDS processing is performed by the up / down counting operation of the counter 512. The digital data obtained in this way is latched in the latch unit 513. Then, the digital data latched in the latch section 513, by selecting the selection signal RSEL supplied from the row decoder 37 1, sequentially read by the sense amplifiers of the column decoder / sense amplifier 39. Thereafter, the pipeline operation is performed by simultaneously performing the operation of writing to the memory unit 32 via the data latch unit 53 on a plurality of pixels.
In this way, pixel selection and AD conversion operations are performed by the raster scan method, and digital data after CDS processing by the counter 512 is transferred to the memory unit 32 via the latch unit 513 and the sense amplifier of the column decoder / sense amplifier 39. The writing operation is performed.
Note that it is possible to increase the reading speed by arranging a plurality of AD converters 51 and reading signals simultaneously from a plurality of pixels of two or more pixels, instead of performing AD conversion in units of one pixel.
In addition, when it is difficult to arrange unit circuits (latch circuits) corresponding to N bits of the counter 512 for the latch unit 513, unit circuits are arranged in units of several bits, which are smaller than N bits, and a selection signal is provided for each bit unit. After selection by RSEL, the data may be read by the sense amplifier of the column decoder / sense amplifier 39 and written to the memory unit 32. Thereby, a pixel unit with a smaller number of pixels can be formed, and the merit of increasing the reading speed can be obtained.
The data stored in the memory unit 32 can be output (read) at a low speed by reading through the data latch unit 53 and the column decoder / sense amplifier 39.
As in the solid-state imaging devices 10A and 10B according to the first and second embodiments, at the time of reading pixel data from the memory unit 32, at least the AD converter 51 of the operation of the current source 35 and the signal processing unit 31. Control to stop the operation. Here, also in the solid-state imaging device 10C according to the present embodiment, the pixel parallel AD conversion method is employed as in the solid-state imaging device 10B according to the second embodiment, so that the pixel signal readout speed can be increased. As a result, the AD converter 51 can be stopped for a longer period of time, so that lower power consumption can be achieved.
[4-4. Multilayer chip layout]
FIG. 17 is a layout diagram showing an example of the layout of the laminated chips in the solid-state imaging device 10C according to the third embodiment.
As shown in FIG. 17, the first chip 20 has a pixel array unit 21 in which pixel units each having a predetermined number of pixels as one unit are two-dimensionally arranged in a matrix, and a via 23 is formed for each pixel unit. Yes. On the other hand, the second chip 30 is provided with a circuit unit (a pixel AD unit in the figure) including the AD converter 51 and the like corresponding to the pixel unit of the pixel array unit 21, and the pixel unit is provided for each pixel AD unit. Correspondingly, a via 23 is formed, and a memory unit 32 is provided outside the formation region of the signal processing unit 31.
15 exemplifies a configuration in which the row selection unit 25 and the column selection unit 27 are provided on the first chip 20 side. However, as illustrated in the layout example of FIG. It is also possible to adopt a configuration provided as peripheral circuits (HSEL, VSEL). Adopting such a configuration has an advantage that a larger area of the first chip 20 can be used as a region of the pixel array unit 21.
FIG. 18 is a layout diagram showing another example of the layout of the laminated chips in the solid-state imaging device 10C according to the third embodiment.
In the layout example described above, a two-layer stacked structure in which two chips of the first chip 20 and the second chip 30 are stacked is adopted, whereas in the layout example, the first chip 20 and the second chip 30 are used. And a three-layer stacked structure in which three chips of the third chip 60 are stacked. However, the structure is not limited to a three-layer structure, and a four-layer structure or more is also possible.
As shown in FIG. 18, in this layout example, the pixel array unit 21 is arranged on the first chip 20, and the circuit unit (AD unit in the figure) including the AD converter 51 is arranged on the second chip 30. The memory unit 32 is arranged on the third chip 60, and the second chip 30 is laminated in the middle, for example. The order of stacking the first chip 20, the second chip 30, and the third chip 60 is arbitrary, but the second chip 30 on which the peripheral circuit including the control unit 35 is mounted should be in the middle. This is preferable because the first and third chips 20 and 60 to be controlled by the control unit 35 are located immediately above and immediately below the second chip 30.
As in the present layout example, the memory unit 32 is provided in a third chip 60 other than the second chip 30 provided with the circuit unit including the AD converter 51 and the peripheral circuit including the control unit 35, that is, the third chip 60. By adopting the configuration in which the memory area 32 is provided, the chip area can be reduced as compared with the layout example in which the memory section 32 is provided in the second chip 30. This point is also clear from the comparison between FIG. 17 and FIG. In this case, a configuration in which the second chip 30 on which a circuit unit including the AD converter 51 and the like is mounted and the third chip 60 on which the memory unit 32 and the like are mounted is connected by a via (VIA2). It is done. The vias (VIA1 / VIA2) for electrical connection between the chips can be realized by a well-known interconnecting technique.
[4-5. Operation and Effect of Third Embodiment]
According to the solid-state imaging device 10C according to the third embodiment described above, similarly to the solid-state imaging device 10B according to the second embodiment, the pixel parallel AD conversion method can be used to increase the pixel signal readout speed. Therefore, the AD converter 51 can be stopped for a long time. Therefore, further reduction in power consumption can be achieved as compared with the solid-state imaging device 10A according to the first embodiment of the column parallel AD conversion method.
In the solid-state imaging device 10C according to the present embodiment, the AD converter 51 and the memory unit 32 are not mixedly mounted in the signal processing unit 31 as in the solid-state imaging device 10B according to the second embodiment. 32 is provided outside the signal processing unit 31. As a result, the solid-state imaging device 10C according to the present embodiment can cope with a case where it is difficult to separate wells between an analog circuit such as a DRAM and the memory unit 32.
In each of the above embodiments, the case where the present invention is applied to a solid-state imaging device having a stacked structure has been described as an example. However, the technology of the present disclosure is not limited to application to a solid-state imaging device having a stacked structure. That is, when reading out pixel data from the memory unit 32, a technique for performing low-speed reading by intermittent driving that stops the operation of the current source 35 and at least the AD converter 51 of the signal processing unit 31 is the pixel array unit 21. And a peripheral circuit thereof are also applied to a so-called flat-structured solid-state imaging device, which is arranged on the same substrate (chip).
However, in the solid-state imaging device according to the second and third embodiments, since the pixel-parallel AD conversion method is used, the solid-state imaging device having the stacked structure has the pixel unit of the pixel array unit 21 and the signal processing. It can be said that it is preferable because a connection structure in which the pixel AD unit of the portion 31 is directly connected via the via 23 can be adopted.
<6. Electronic equipment>
The solid-state imaging device to which the technology of the present disclosure is applied includes an imaging device such as a digital still camera and a video camera, a portable terminal device having an imaging function such as a mobile phone, a copying machine using a solid-state imaging device for an image reading unit, and the like It can be used as an imaging unit (image capturing unit) in all electronic devices. In some cases, the above-described module form mounted on an electronic device, that is, a camera module is used as an imaging device.
FIG. 19 is a block diagram illustrating a configuration example of an imaging apparatus (camera apparatus) that is an example of the electronic apparatus of the present disclosure.
As illustrated in FIG. 19, the imaging apparatus 100 according to the present disclosure includes an optical system including a lens group 101 and the like, an imaging element 102, a DSP circuit 103 that is a camera signal processing unit, a frame memory 104, a display device 105, a recording device 106, An operation system 107, a power supply system 108, and the like are included. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.
The lens group 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 102. The imaging element 102 converts the amount of incident light imaged on the imaging surface by the lens group 101 into an electrical signal in units of pixels and outputs the electrical signal.
The display device 105 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 102. The recording device 106 records a moving image or a still image captured by the image sensor 102 on a recording medium such as a memory card, a video tape, or a DVD (Digital Versatile Disk).
The operation system 107 issues operation commands for various functions of the imaging apparatus 100 under the operation of the user. The power supply system 108 appropriately supplies various power supplies serving as operation power for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.
Such an image pickup apparatus 100 is applied to a camera module for a mobile device such as a video camera, a digital still camera, and a mobile phone. In the imaging apparatus 100, the solid-state imaging apparatus according to each of the above-described embodiments that can realize high-speed reading of pixel data with lower power consumption can be used as the imaging element 102. This can greatly contribute to the reduction in power consumption of the imaging apparatus 100.
<7. Configuration of the present disclosure>
[1] A signal processing unit that includes an AD converter that digitizes an analog pixel signal read from each pixel of the pixel array unit to a signal line, and transfers the digitized pixel data at a first speed faster than the frame rate;
A solid-state imaging device comprising: a control unit that performs control to stop operation of a current source connected to a signal line and at least operation of an AD converter of a signal processing unit when reading pixel data from a memory unit.
[2] The solid-state imaging device according to [1], wherein the control unit stops the operation of the current source and the operation of the AD converter in units of vertical synchronization signals.
[3] The signal processing unit, the memory unit, the data processing unit, and the control unit are formed on at least one chip different from the chip on which the pixel array unit is formed,
The solid-state imaging device according to [1] or [2], wherein the chip in which the pixel array unit is formed and at least one other chip are stacked.
[3A] A pixel array portion is formed on the first chip,
A signal processing unit, a memory unit, a data processing unit, and a control unit are formed on the second chip,
The solid-state imaging device according to the above [3], wherein the first chip and the second chip are stacked.
[3B] A pixel array portion is formed on the first chip,
A signal processing unit and a control unit are formed on the second chip,
A memory unit and a data processing unit are formed on the third chip,
The solid-state imaging device according to [3], wherein the first chip, the second chip, and the third chip are stacked.
[4] The solid-state imaging device according to [3], wherein the control unit controls the circuit on the chip side where the pixel array unit is formed and at least one other circuit on the chip side in synchronization.
[5] Any of the above [1] to [4], wherein the signal processing unit performs signal processing in parallel in units of pixel columns with respect to the analog pixel signal read from each pixel of the pixel array unit for each pixel row. A solid-state imaging device according to claim 1.
[6] The signal processing unit
A data latch unit for latching pixel data digitized by the AD converter;
A parallel-serial conversion unit that converts pixel data output from the data latch unit from parallel data to serial data;
The solid-state imaging device according to [5], wherein the pixel data digitized by the AD converter is pipeline-transferred to the memory unit.
[7A] The signal processing unit performs digitization processing by an AD converter within one horizontal period, and transfers the digitized pixel data to the data latch unit within the next one horizontal period. Imaging device.
[7B] The signal processing unit performs digitization processing by the AD converter within one horizontal period, and transfers the digitized pixel data to the memory unit via the data latch unit and the column decoder within the next one horizontal period. The solid-state imaging device according to [6] above.
[8] The signal processing unit
A data compression unit for compressing pixel data output from the data latch unit;
A parallel-serial conversion unit for converting pixel data output from the data compression unit from parallel data to serial data;
[9A] The signal processing unit performs digitization processing by an AD converter within one horizontal period, and transfers the digitized pixel data to the data latch unit within the next one horizontal period. Imaging device.
[9B] The signal processing unit performs digitization processing by an AD converter within one horizontal period, and converts the digitized pixel data into a data latch unit and a column decoder within the next one horizontal period. The solid-state imaging device according to [8], which is transferred to the memory unit via
[10] The signal processing unit includes two or more AD converters, and performs digital signal processing in parallel in the two or more AD converters according to any one of [5] to [9] The solid-state imaging device described.
[11] The solid-state imaging device according to [10], wherein the two or more AD converters are arranged separately on both sides of the extension direction of the signal line of the pixel array unit.
[12] The current source, the signal processing unit, and the memory unit connected to the signal line have a predetermined number of pixels as a unit, and are provided for each unit.
The signal processing unit performs any one of the above-described [1] to [4], in which signal processing is performed in parallel on an analog pixel signal read in units of a predetermined number of pixels from each pixel of the pixel array unit. The solid-state imaging device described in 1.
[13] The solid-state imaging device according to [12], wherein the signal processing unit performs signal processing on the analog pixel signal read for each unit of the predetermined number of pixels in a predetermined order for a plurality of pixels in the unit.
[14] The data processing unit includes a decoder that specifies a column address for the memory unit, and a sense amplifier that reads pixel data of the specified address,
The solid-state imaging device according to any one of [1] to [13], wherein pixel data is read from the memory unit through a sense amplifier and a decoder.
[15] The solid-state imaging device according to any one of [1] to [14], wherein the data processing unit reads pixel data from the memory unit during the exposure period.
[16] The control unit according to any one of [1] to [15], wherein when the operation of the current source connected to the signal line is stopped, the control unit cuts off a current path between the signal line and the current source. The solid-state imaging device described in 1.
[17] The solid-state imaging device according to [16], wherein the control unit applies a fixed potential to the signal line when interrupting the current path between the signal line and the current source.
[18] A plurality of chips including a chip in which the pixel array portion is formed are stacked,
A data processing unit that reads pixel data from the memory unit at a second speed slower than the first speed; and
When reading pixel data from the memory unit, a control unit that performs control to stop the operation of the current source connected to the signal line and the operation of at least the AD converter of the signal processing unit,
A solid-state imaging device formed on at least one chip different from the chip on which the pixel array portion is formed.
[18A] The first chip and the second chip are laminated,
The first chip has a pixel array portion,
The solid-state imaging device according to [18], wherein the second chip includes a signal processing unit, a memory unit, a data processing unit, and a control unit.
[18B] The first chip, the second chip, and the third chip are laminated,
In the second chip, a signal processing unit, a data processing unit, and a control unit are formed,
The solid-state imaging device according to the above [18], wherein a memory unit is formed on the third chip.
[19] A signal processing unit that includes an AD converter that digitizes an analog pixel signal read from each pixel of the pixel array unit to a signal line, and transfers the digitized pixel data at a first speed higher than the frame rate;
A method of driving a solid-state imaging device that performs driving to stop operation of a current source connected to a signal line and operation of at least an AD converter of a signal processing unit when reading pixel data from a memory unit.
[20] A signal processing unit that includes an AD converter that digitizes an analog pixel signal read from each pixel of the pixel array unit to a signal line, and transfers the digitized pixel data at a first speed faster than the frame rate;
An electronic apparatus having a solid-state imaging device including a control unit that controls the operation of a current source connected to a signal line and the operation of at least an AD converter of a signal processing unit when reading pixel data from a memory unit .
DESCRIPTION OF SYMBOLS 10A ... Solid-state imaging device concerning 1st Embodiment, 10B ... Solid-state imaging device concerning 2nd Embodiment, 10C ... Solid-state imaging device concerning 3rd Embodiment, 20 ... 1st chip | tip, 21... Pixel array part (pixel part), 22 1 , 22 2 ... Pad part, 23 (23 1 to 23 4 )... Via (VIA), 25. Line 27, column selection unit, 30 ... second chip, 31 ... signal processing unit, 32 (32 1 to 32 2 , 32 13 to 32 24 ) ... memory unit, 33 ... Data processing unit 34 ... Control unit 35 ... Current source 36 ... Decoder 37 ... Row decoder 38 ... Interface (IF) unit 39 ... Column decoder / sense amplifier , 40 ... unit pixel, 41 ... photodiode, 42 ... transfer transistor ( Transfer gate), 43 ... Reset transistor, 44 ... Amplification transistor, 45, 47 ... Selection transistor, 46 ... FD section, 51 (51 1 to 51 4 ) ... AD converter, 52・ ・ ・ Reference voltage generator 53 (53 A , 53 B ) Data latch 54, Parasiri (parallel-serial) converter 55 (55 A , 55 B ) Multiplexer 56 ... Data compression unit, 60 ... Third chip
The signal processing unit, the memory unit, the data processing unit, and the control unit are formed on at least one chip different from the chip on which the pixel array unit is formed,
The solid-state imaging device according to claim 1, wherein the solid-state imaging device has a structure in which a chip on which a pixel array unit is formed and at least one other chip are stacked.
4. The solid-state imaging device according to claim 3, wherein the control unit controls the circuit on the chip side where the pixel array unit is formed and at least one other circuit on the chip side in synchronization.
The solid-state imaging device according to claim 1, wherein the signal processing unit performs signal processing in parallel in units of pixel columns on an analog pixel signal read out from each pixel of the pixel array unit for each pixel row.
The solid-state imaging device according to claim 5, wherein pixel data digitized by the AD converter is pipeline-transferred to the memory unit.
The solid-state imaging device according to claim 6, wherein the signal processing unit performs digitization processing by an AD converter within one horizontal period, and transfers the digitized pixel data to the data latch unit within the next one horizontal period.
9. The solid-state imaging device according to claim 8, wherein the signal processing unit performs digitization processing by an AD converter within one horizontal period, and transfers the digitized pixel data to the data latch unit within the next one horizontal period.
The solid-state imaging device according to claim 5, wherein the signal processing unit includes two or more AD converters, and performs digital signal processing in parallel in the two or more AD converters.
The solid-state imaging device according to claim 10, wherein the two or more AD converters are arranged separately on both sides in the extending direction of the signal line of the pixel array unit.
The current source, the signal processing unit, and the memory unit connected to the signal line are provided for each unit, with a predetermined number of pixels as a unit.
The solid-state imaging device according to claim 1, wherein the signal processing unit performs signal processing in parallel on an analog pixel signal read from each pixel of the pixel array unit in units of a predetermined number of pixels.
The solid-state imaging device according to claim 12, wherein the signal processing unit performs signal processing on the analog pixel signal read for each unit of the predetermined number of pixels in a predetermined order for a plurality of pixels in the unit.
The data processing unit includes a decoder that specifies a column address for the memory unit, and a sense amplifier that reads pixel data of the specified address,
The solid-state imaging device according to claim 1, wherein pixel data is read from the memory unit through a sense amplifier and a decoder.
The solid-state imaging device according to claim 1, wherein the data processing unit reads pixel data from the memory unit during the exposure period.
The solid-state imaging device according to claim 1, wherein the control unit interrupts a current path between the signal line and the current source when stopping the operation of the current source connected to the signal line.
The solid-state imaging device according to claim 16, wherein the control unit applies a fixed potential to the signal line when interrupting the current path between the signal line and the current source.
A plurality of chips including a chip in which a pixel array part is formed are stacked,
PCT/JP2013/065047 2012-07-06 2013-05-30 Solid-state imaging device, driving method for solid-state imaging device, and electronic device WO2014007004A1 (en)
KR20147035801A KR20150035722A (en) 2012-07-06 2013-05-30 Solid-state imaging device, driving method for solid-state imaging device, and electronic device
CN201380035054.5A CN104429057B (en) 2012-07-06 2013-05-30 The driving method and electronic installation of solid-state imaging apparatus, solid-state imaging apparatus
JP2014523647A JP6308129B2 (en) 2012-07-06 2013-05-30 Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus
EP13812563.8A EP2871835A4 (en) 2012-07-06 2013-05-30 Solid-state imaging device, driving method for solid-state imaging device, and electronic device
US14/405,045 A-371-Of-International US9609213B2 (en) 2012-07-06 2013-05-30 Solid-state imaging device and driving method of solid-state imaging device, and electronic equipment
US201414405045A A-371-Of-International 2014-12-02 2014-12-02
US15/443,092 Continuation US9848147B2 (en) 2012-07-06 2017-02-27 Solid-state imaging device and driving method of solid-state imaging device, and electronic equipment
WO2014007004A1 true WO2014007004A1 (en) 2014-01-09
WO2015163170A1 (en) * 2014-04-24 2015-10-29 ソニー株式会社 Image pickup element, control method, and image pickup device
JP2015204471A (en) * 2014-04-10 2015-11-16 キヤノン株式会社 Method for controlling solid-state imaging element, electronic equipment, program, and storage medium
WO2016152510A1 (en) * 2015-03-23 2016-09-29 ソニー株式会社 Image sensor, processing method, and electronic device
WO2016152635A1 (en) * 2015-03-26 2016-09-29 ソニー株式会社 Image sensor, processing method, and electronic device
WO2017057291A1 (en) * 2015-10-01 2017-04-06 オリンパス株式会社 Imaging element, endoscope, endoscope system
CN107005665A (en) * 2014-12-25 2017-08-01 索尼公司 Solid imaging element and electronic installation
JPWO2016072280A1 (en) * 2014-11-05 2017-08-10 ソニー株式会社 Signal processing apparatus, image sensor, and electronic device
WO2018047642A1 (en) * 2016-09-08 2018-03-15 ソニーセミコンダクタソリューションズ株式会社 Imaging element, operation method for imaging element, imaging device, and electronic apparatus
WO2018047618A1 (en) * 2016-09-08 2018-03-15 ソニー株式会社 Imaging element and driving method, and electronic apparatus
WO2018079331A1 (en) * 2016-10-31 2018-05-03 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device, signal processing method thereof, and electronic device
JP2018527774A (en) * 2015-06-11 2018-09-20 ソニー株式会社 Data charge phase data compression architecture
JP2018527773A (en) * 2015-06-12 2018-09-20 ソニー株式会社 Data charge phase data compression tool
US10554910B2 (en) 2015-04-24 2020-02-04 Sony Corporation Solid state image sensor, semiconductor device, and electronic device
US9153609B2 (en) * 2011-05-12 2015-10-06 Olive Medical Corporation Image sensor with tolerance optimizing interconnects
See also references of EP2871835A4 *
US10368024B2 (en) 2014-04-10 2019-07-30 Canon Kabushiki Kaisha Solid-state image sensor capable of restricting digital signal processing operation during time sensitive and heavy load periods, method of controlling the same, electronic device, and storage medium
US9906746B2 (en) 2014-05-02 2018-02-27 Olympus Corporation Solid-state image pickup device and image pickup apparatus
JP2015213257A (en) * 2014-05-02 2015-11-26 オリンパス株式会社 Solid-state imaging apparatus and imaging apparatus
JPWO2016067386A1 (en) * 2014-10-29 2017-08-03 オリンパス株式会社 Solid-state imaging device
US9961286B2 (en) 2014-10-29 2018-05-01 Olympus Corporation Solid-state imaging device
CN107431775A (en) * 2015-03-23 2017-12-01 索尼公司 Imaging sensor, processing method and electronic equipment
US20180077374A1 (en) * 2015-03-26 2018-03-15 Sony Corporation Image sensor, processing method, and electronic apparatus
US9060143B2 (en) 2015-06-16 Solid-state imaging device, method of driving a solid-state imaging device, and electronic apparatus including a solid-state imaging device
JP5272860B2 (en) 2013-08-28 Solid-state imaging device and camera system
JP5791571B2 (en) 2015-10-07 Imaging device and imaging apparatus
JP2009049740A (en) 2009-03-05 Image device
TWI529923B (en) 2016-04-11 Solid-state image pickup apparatus, driving method for solid-state image pickup apparatus and electronic device
Ref document number: 13812563
Ref document number: 2014523647
Ref document number: 14405045
Ref document number: 2013812563
Ref document number: 20147035801