Source: http://www.google.com/patents/US6410365?dq=6188988
Timestamp: 2017-06-25 13:38:02
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Matched Legal Cases: ['arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 1', 'arts 103', 'arts 104']

Patent US6410365 - Semiconductor device with two stacked chips in one resin body and method of ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device according to this invention, wherein two semiconductor chips are sealed by one resin body using two lead frames, includes a wide part extending in the width direction of dam bars, the width of one dam bar being narrower than the width of another dam bar, and the two lead frames...http://www.google.com/patents/US6410365?utm_source=gb-gplus-sharePatent US6410365 - Semiconductor device with two stacked chips in one resin body and method of producingAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6410365 B1Publication typeGrantApplication numberUS 09/322,915Publication dateJun 25, 2002Filing dateJun 1, 1999Priority dateJun 1, 1998Fee statusLapsedAlso published asCN1237785A, US6479322, US6551858, US20020064903, US20020119598, US20030153134Publication number09322915, 322915, US 6410365 B1, US 6410365B1, US-B1-6410365, US6410365 B1, US6410365B1InventorsYouichi Kawata, Kouji Koizumi, Michiaki Sugiyama, Atsushi Fujishima, Yasuyuki Nakajima, Takatoshi HagiwaraOriginal AssigneeHitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (14), Non-Patent Citations (1), Referenced by (21), Classifications (64), Legal Events (7) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device with two stacked chips in one resin body and method of producing
US 6410365 B1Abstract
providing first and second semiconductor chips each having a main surface comprising a semiconductor element and a plurality of external terminals, and a lower surface opposing said main surface, wherein said first and second semiconductor chips are warped, providing a first lead frame comprising outer portions and inner portions extending from said outer portions, and a second lead frame comprising outer portions and inner portions extending from said outer portions, fixing the main surface of said first semiconductor chip to the inner portions of said first lead frame, electrically connecting the plurality of external terminals of said first semiconductor chip to the inner portions of said first lead frame, fixing the main surface of said second semiconductor chip to the inner portions of said second lead frame, and electrically connecting the plurality of external terminals of said second semiconductor chip to the inner portions of said second lead frame, disposing said first and second semiconductor chips, and the inner portions of said first lead frame and said second lead frame, within the interior of a mold cavity such that the lower surfaces of said first and second semiconductor chips are facing each other, and pressure injecting a resin comprising a mixture of fillers into said mold cavity so as to form a seal, wherein: a gap between the lower surface of said first semiconductor chip and the lower surface of said second semiconductor chip is maintained wider than a diameter of a largest particle of said fillers. 2. A method of producing a semiconductor device according to claim 1, wherein, in the steps of electrically connecting an external terminal of the first semiconductor chip to an inner portion of the first lead frame and electrically connecting an external terminal of the second semiconductor chip to an inner portion of the second lead frame, the electrical connections between said first and second semiconductor chips, and the inner portions of said first and second lead frames, are made by electrically conducting wires.
3. A method of producing a semiconductor device comprising the steps of:
providing first and second semiconductor chips each having a main surface comprising a semiconductor element and a plurality of external terminals, and a lower surface opposing said main surface, wherein said first and second semiconductor chips are warped, providing a first lead frame comprising outer portions and inner portions extending from said outer portions, and a second lead frame comprising outer portions and inner portions extending from said outer portions, fixing the main surface of said first semiconductor chip to the inner portions of said first lead frame, electrically connecting the plurality of external terminals of said first semiconductor chip to the inner portions of said first lead frame, fixing the main surface of said second semiconductor chip to the inner portions of said second lead frame, and electrically connecting the plurality of external terminals of said second semiconductor chip to the inner portions of said second lead frame, disposing said first and second semiconductor chips, and the inner portions of said first lead frame and said second lead frame, within the interior of a mold cavity such that the lower surfaces of said first and second semiconductor chips are facing each other, and pressure injecting a resin comprising a mixture of fillers into said mold cavity so as to form a seal, wherein: a damping material is provided between the lower surfaces of the first and second semiconductor chips, in the step of disposing said first and second semiconductor chips, and the inner portions of said first lead frame and said second lead frame, within the interior of the mold cavity. 4. A method of producing a semiconductor device according to claim 3, wherein said damping material is a resin film.
Hence, in the above stacked semiconductor, device, unlike the stacked semiconductor device of the aforesaid disclosure wherein element forming surfaces of two semiconductor chips are disposed opposing each other and an inner lead part is disposed in the gap between the two, the lower surfaces of two semiconductor chips are brought into contact with each other.
The first semiconductor chip is sealed by a resin fixed by the lead of the first lead frame, and the second semiconductor chip is sealed by a resin body fixed by the lead of the second lead frame. In other words, this resin-sealed semiconductor device is produced using two lead frames. Of these two lead frames, one of them does not have an outer lead part and has only an inner lead part. In other words, in this resin-sealed semiconductor device, the outer lead part of the other lead frame pulled out from the resin body isused as a common external connecting terminal for two semiconductor chips.
[5] Stacked semiconductor devices are produced by an assembly processing two lead frames. In the first lead frame, the tips of the outer lead parts of first leads are supported in the frame body, and the intermediate parts of first leads are interconnected by dam bars and supported in the frame body by dam bars. In the second lead frame, the tips of the outer lead parts of second leads are interconnected by dam bars, and supported in the frame body by dam bars. In other words, in the second lead frame, there is nothing supported in the area specified by the dam bars and frame body, so rigidity is low and bending occurs easily. Therefore, when the second lead frame is transported in a step at a subsequent stage after fixing the inner lead parts of the second leads to the circuit-forming surface of the semiconductor chip, the chip tends to wobble and easily fall off the second lead frame, so yield of the stacked semiconductor device declines.
[6] The method of producing a semiconductor device
FIG. 1 is a plan view of a first lead frame LFI used for producing the semiconductor device of this embodiment, and FIG. 2 is a plan view of a second lead frame LF2 used for producing this semiconductor device.
FIG. 3 is a sectional drawing of the lead frame L1P1 along a line III—III in FIG. 1. The inner lead parts 1 a of the leads 1 which comprise terminals other than open terminals comprise, in order from the side nearest the dam bar 5, parts 1 a 1 which extend parallel to the lower surface of the lead frame LF1, parts 1 a 2 which are bent upwards, and parts 1 a 3 which extend parallel to the first parts 1 a 1. The parts 1 a 3 are the parts disposed on the element-forming surface of the semiconductor chip in a production process described later, and the insulating films 4 described above are bonded to their lower surface.
As described later, the first lead frame LF1 and second lead frame LF2 are used with their lower surfaces superimposed. Therefore, the left-right orientation of the terminals of the lead frame LF1 shown in FIG. 1 is the reverse of that of the terminals of the lead frame LP2 shown in FIG. 2 so that similar terminals may overlap near the dam bars 5 when the lower surfaces of the lead frames LF1 and LF2 are superimposed.
As described above, in the case of the second lead frame LF2, the width of the dam bar 6 at both ends of the spaces between the leads 1 (near the leads 1) is narrower than the width of the dam bar 5 of the first lead frame LF1. In these example dimensions, whereas the width of the dam bar 6 near the leads 1 is 0.13 mm, the width of the dam bar 5 of the first lead frame LF1 is 0.15 mm. The difference (0.15 mm−0.13 mm=0.02 mm) in the width of these dam bars 5 and 6 is equal to the maximum value of mismatch in the width direction produced between the dam bar 5 of the lead frame LF1 and the dam bar 6 of the lead frame LF2 when the lead frames LF1, LF2 are superimposed and positioned in a mold in the resin body transfer mold step described later. That is, the width of the dam bar 6 of the second lead frame LF2 near the leads 1 is specified so that it does not extend beyond the dam bar 5 of the first lead frame LF1 when the lead frames LF1, LF2 are positioned in the mold. On the other hand, in the center of the space between the leads 1, due to the dummy lead 7 formed in the dam bar 6 of the second lead frame LF2, the tip of the dummy lead 7 does extend beyond the dam bar 5 of the first lead frame LF1 when the lead frames LF1, LP2 are superimposed.
The two aforesaid semiconductor chips 8 a and 8 b which comprise single crystal silicon are of identical dimensions, and a 64-megabit DRAM is formed on their element-forming surfaces. In the center of these element-forming surfaces, plural bonding pads BP which are formed by exposing part of aluminum (A1) interconnections, are formed. These bonding pads BP are arranged in one row in the length direction of the semiconductor chip 8 a (8 b). The above DRAM circuit pattern and the arrangement of the bonding pads BP are identical for the first semiconductor chip 8 a and second semiconductor chip 8 b. That is, the two semiconductor chips 8 a, 8 b have identical dimensions and an identical structure.
Next, as shown in FIG. 12, the two lead frames LF1, LF2 are superimposed so that the lower surfaces of the two semiconductor chips 8 a, 8 b are in contact. Contact of the lower surfaces of the two semiconductor chips 8 a, 8 b is maintained by the elasticity of the inner lead parts 1 a which are bent in the center (second parts 1 a 2). Also, in the lead frame LP1 and the lead frame LF2, the frame bodies 10, the first parts 1 a 1 of the inner lead parts 1 a and the dam bars 5, 6 are in contact. In the two semiconductor chips 8 a and 8 b, these lower surfaces may also be fixed using an adhesive.
As shown in the drawing, the lead frames LF1 and LF2 are fixed in the mold 30 by the pressing of the darn bars 5, 6 and the leads 1 near to them from a vertical direction by a clamp surface 32 a of the upper die 30 a, and a clamp surface 32 b of the lower die 30 b. In the region in which the dummy lead 7 is not formed in the dam bar 6 of the lead frame LF2, the width of the dam bar 6 is narrower than that of the dam bar 5, so the contact area of the clamp surface 32 b of the lower die 30 b and the dam bar 6 is small, as shown in FIG. 14(a). However, in the region in which the dummy lead 7 is formed on the side of the dam bar 6, both the dam bar 6 and the dummy lead 7 come in contact with the clamp surface 32 b of the lower die 30 b, as shown in FIG. 14(b). That is, by forming the dummy lead 7 on the side wall of the dam bar 6, the contact area of the clamp surface 32 b of the lower die 30 b and the dam bar 6 effectively increases although the width of the dam bar 6 is narrower.
Next, after solder plating the upper surfaces of the lead frames LF1 and LF2 exposed from the side of the resin body 11, unnecessary parts (of the dam bars 5, 6 and the frame body (10) of the lead frames LF1, LF2 are cut off, resin that remained in the gaps between the side of the package 11 and the dam bars 5, 6 is removed (deburring), and the outer lead parts 1 b of the leads 1 are formed into, for example, a gull-wing shape to give a TSOP 40, a finished product in which the two semiconductor chips 8 a, 8 b are sealed as shown in FIG. 17.
Moreover, by making the width of the dam bar 6 of the lead frame LF2 narrower than the width of the dam bar 5 of the lead frame LF1, the outer side face of the dam bar 6 is disposed further inside than the outer side face of the dam bar 5, as shown in FIG. 18(a). Even if a mismatch occurs between the two lead frames LF1 and LF2, the outer side face of the dam bar 6 is never disposed further outside than the outer side of the dam bar 5, as shown in FIG. 18(b). Therefore, when the outer lead parts 1 b are bent towards the dam bar 6, the lower surfaces of the outer lead parts 1 b are bent toward the outer side face of the dam bar 5, or further inside. Conversely, if the outer side face of the dam bar 6 were disposed further outside than the outer side face of the dam bar 5, the lower surfaces of the outer lead parts 1 b would be bent further outside than the outer side face of the dam bar 5 as shown in FIG. 18(c), so the length (L) from the side of the resin body 11 to the ends of the outer lead parts 1 b would exceed the specification of the TSOP.
In the above-mentioned embodiment, the dummy lead 7 formed in the dam bar 6 of the lead frame LF2 is disposed on the opposite side to the side on which the inner lead parts 1 a are interconnected, however this dummy lead 7 maybe disposed on the side on which the inner lead parts 1 a are interconnected as shown in FIGS. 22(a) and 22(b).
In this case also, as the contact area between the clamp surface 32 b of the lower die 30 b of the mold 30 and the dam bar S effectively increases as shown in FIG. 23, the same effect is obtained as in the above-mentioned embodiment.
Terminal names are assigned to the outer lead parts of the plural leads 103. A terminal Vcc is a power supply potential terminal which is fixed at a power supply potential (for example, 5 [V]). A terminal Vss is a reference potential terminal which is fixed at a reference potential (for example, 0 [V]).
The inner lead parts of the terminal IO/0A, terminal IO/1A, terminal IO/2A and terminal IO/3A situated inside the resin body 119 are bonded to the circuit-forming surface 115X of the semiconductor chip 115 via the insulating film 109, and are electrically connected to the electrodes BP1 of the semiconductor chip 115 via the electrically conducting wires as shown in FIG. 26.
The inner lead parts of the leads 104 connected to the respective leads 103 which are the terminal IO/0A, terminal IO/1A, terminal IO/2A and terminal I0/3A situated inside the resin body 119 are disposed outside the boundary of the semiconductor chip 116, and are not electrically connected to the electrodes BP2 of the semiconductor chip 116.
Of the four bus bar leads 107, two are connected to the leads 103 in the first stage, middle stage and final stage of the plural leads 103 arranged along the extending direction of one long side framepart of the frame body 101, and are formed in one piece with the inner lead parts of these leads 103. The other two bar leads 107 are connected to the leads 103 in the first stage, middle stage and final stage of the plural leads 103 arranged along the extending direction of the other long side frame part of the frame body 101, and are formed in one piece with the inner lead parts of these leads 103.
Next, the semiconductor chip 115 is bonded to the lead frame LF10, and the semiconductor chip 116 is bonded to the lead frame LF20. The lead frame LF10 and these miconductor chip 115 are bonded by thermocompression bonding of the first parts 103A of the leads 103 and the branch leads connected to the bus bar lead 107 to the circuit-forming surface 115X of the semiconductor chip 115 via the insulating film 109. The lead frame LF20 and the semiconductor chip 116 are bonded by thermocompression bonding of the first parts 104A of the leads 104 and the branch leads connected to the bus bar lead 108 to the circuit-forming surface 116X of the semiconductor chip 116 via the insulating film 110.
Next, the cutting parts (106B, 105B) of the dambars (106, 105) are cut simultaneously with a cutting die with the lead frame LF20 facing upwards, the dam bars (106, 105) are removed and the frame body 102 of the lead frame LF20 is removed as shown in FIGS. 47 and 48.
The plating step 145 is a process which uses, for example, a processing fluid such as an SO4 compound to form the electrically conducting film on the leads. The neutralizing step 147 is a step which use an alkaline processing fluid to neutralize the electrically conducting film formed in the plating step of the preceding stage. The hot water rinsing step 148 is a step which rinses off the processing fluids of the preceding stage with pure hot water. The drying step 149 is a step which vaporizes the moisture adhering to the electrically conducting film 114 and the resin body 119. The rinsing steps 142, 144 and 146 are steps which rinse off the processing fluids of the preceding stages with pure water.
[1] In the production of the semiconductor device 120, the leads 103 and leads 104 are joined by laser welding after forming the resin body 119. Hence, as the circuit-forming surfaces (115 x, 116 x) of the semiconductor chip 115 and semiconductor chip 116 are covered by the resin of the resin body 119, defects of the semiconductor chips 115 and 116 produced by scattering of scattering material (hot molten material) during welding can be prevented, and consequently, the yield of the semiconductor device 120 can be improved.
The semiconductor chips 115 and 116 have a structure essentially comprising a semiconductor substrate A1, a multi-interconnection layer A2 comprising plural insulating layers and interconnection layers stacked on the circuit-forming surface of this semiconductor substrate A1, and a surface protecting layer A3 formed so as to cover this multi-interconnection layer as shown in FIG. 31, so the lower surfaces of the semiconductor chips 115, 116 are warped in a convex direction. When these miconductor chips 115 and 116 are laminated with their lower surfaces superimposed, a gap is formed between the semiconductor chip 115 and the semiconductor chip 116 which gradually widens from the center of the chip towards the periphery. This gap can be eliminated by superimposing the semiconductor chips 115, 116 with the damper 151, which easily deforms under a relatively small tightening force, interposed between them. If the gap is eliminated, no spaces occur between the semiconductor chips 115, 116 due to the filler mixed with the resin when the resin body 119 is formed by the transfer molding method, therefore cracking of the semiconductor chips (115, 116) originating from the spaces is prevented.
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Nakanishi et al., "Development of High Density Memory IC Package by Stacking IC Chips," Proceedings of the 45th Electronic Components and Technology Conference, pp. 634-640, May, 1995.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6677181 *Sep 10, 2001Jan 13, 2004Hyundai Electronics Industries Co., Ltd.Method for fabricating stacked chip package deviceUS6844616 *Mar 15, 2002Jan 18, 2005Vanguard International Semiconductor Corp.Multi-chip semiconductor package structureUS6893898 *May 29, 2003May 17, 2005Renesas Technology Corp.Semiconductor device and a method of manufacturing the sameUS7436049 *Feb 2, 2005Oct 14, 2008Samsung Electronics Co., Ltd.Lead frame, semiconductor chip package using the lead frame, and method of manufacturing the semiconductor chip packageUS9000576 *Aug 21, 2012Apr 7, 2015Cyntec Co., Ltd.Package structure and manufacturing method thereofUS9013029 *Aug 8, 2012Apr 21, 2015Panasonic Intellectual Property Management Co., Ltd.Joined body having an anti-corrosion film formed around a junction portion, and a semiconductor device having the sameUS9065030 *Mar 23, 2011Jun 23, 2015Gne Tech Co., Ltd.Diode package having improved lead wire and manufacturing method thereofUS9392691 *Jul 16, 2014Jul 12, 2016International Business Machines CorporationMulti-stacked electronic device with defect-free solder connectionUS9474153 *Oct 16, 2015Oct 18, 2016International Business Machines CorporationMulti-stacked electronic device with defect-free solder connectionUS9599655 *Apr 4, 2014Mar 21, 2017Mitsubishi Electric CorporationSemiconductor deviceUS20020089048 *Mar 15, 2002Jul 11, 2002Kuang-Ho LiaoMulti-chip semiconductor package structureUS20030228720 *May 29, 2003Dec 11, 2003Hitachi, Ltd.Semiconductor device and a method of manufacturing the sameUS20040108583 *Dec 5, 2002Jun 10, 2004Roeters Glen E.Thin scale outline package stackUS20050167791 *Feb 2, 2005Aug 4, 2005Han-Shin YounLead frame, semiconductor chip package using the lead frame, and method of manufacturing the semiconductor chip packageUS20060003521 *Sep 8, 2005Jan 5, 2006Akira FukunagaMethod of and apparatus for manufacturing semiconductor deviceUS20120313229 *Aug 21, 2012Dec 13, 2012Cyntec Co., Ltd.Package structure and manufacturing method thereofUS20130087826 *Mar 23, 2011Apr 11, 2013Gne Tech Co., Ltd.Diode package having improved lead wire and manufacturing method thereofUS20130221502 *Aug 8, 2012Aug 29, 2013Panasonic CorporationJoined body, power semiconductor device, and manufacturing methods of joined body and power semiconductor deviceUS20150042373 *Apr 4, 2014Feb 12, 2015Mitsubishi Electric CorporationSemiconductor deviceUS20160044785 *Oct 16, 2015Feb 11, 2016International Business Machines CorporationMulti-stacked electronic device with defect-free solder connectionCN102332444A *Jun 16, 2011Jan 25, 2012沈健Semiconductor lead frame of whole matrix surface* Cited by examinerClassifications U.S. Classification438/123, 438/124International ClassificationH01L21/56, H01L23/495, H01L23/50, H01L21/60, H01L23/31, H01L21/50, H01L23/04, H01L23/28Cooperative ClassificationH01L2924/12042, H01L2924/181, H01L2224/45015, H01L2224/05554, H01L24/48, H01L2224/92147, H01L2224/48624, H01L2224/85205, H01L2224/73215, H01L2224/85201, H01L2924/01078, H01L2924/01006, H01L2924/01057, H01L2224/4826, H01L2224/32245, H01L2224/48091, H01L2224/04042, H01L2224/06136, H01L2924/01072, H01L2224/48465, H01L2224/85207, H01L2924/01014, H01L2924/014, H01L2924/01047, H01L2924/01039, H01L2224/48247, H01L24/49, H01L2924/01083, H01L2224/05624, H01L2924/0105, H01L24/05, H01L24/45, H01L23/4951, H01L23/49575, H01L2924/01013, H01L2924/01023, H01L2924/01028, H01L2924/01005, H01L2224/49113, H01L2924/01079, H01L2924/3511, H01L24/06, H01L2924/01029, H01L21/565, H01L2924/01016, H01L2224/45144, H01L23/49537European ClassificationH01L23/495L, H01L24/06, H01L23/495A4, H01L21/56M, H01L23/495F, H01L24/49, H01L24/05Legal EventsDateCodeEventDescriptionSep 24, 1999ASAssignmentOwner name: HITACHI, LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAWATA, YOUICHI;KOIZUMI, KOUJI;SUGIYAMA, MICHIAKI;AND OTHERS;REEL/FRAME:010262/0712;SIGNING DATES FROM 19990827 TO 19990830Owner name: HITACHI ULSI SYSTEMS CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KAWATA, YOUICHI;KOIZUMI, KOUJI;SUGIYAMA, MICHIAKI;AND OTHERS;REEL/FRAME:010262/0712;SIGNING DATES FROM 19990827 TO 19990830Nov 29, 2005FPAYFee paymentYear of fee payment: 4Nov 25, 2009FPAYFee paymentYear of fee payment: 8Mar 25, 2011ASAssignmentOwner name: RENESAS ELECTRONICS CORPORATION, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:026109/0976Effective date: 20110307Jan 31, 2014REMIMaintenance fee reminder mailedJun 25, 2014LAPSLapse for failure to pay maintenance feesAug 12, 2014FPExpired due to failure to pay maintenance feeEffective date: 20140625RotateOriginal ImageGoogle Home - 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