Source: http://www.google.com/patents/US7957470?dq=6106459
Timestamp: 2015-04-21 05:57:52
Document Index: 749611005

Matched Legal Cases: ['Application No. 60', 'Application No. 2', 'Application No. 2', 'Application No. 2', 'Application No. 2', 'art 10']

Patent US7957470 - System and method for adapting video decoding rate - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn embodiment of the present invention provides systems and methods for adaptive video decoding. An example method includes determining that a video decoding rate of received video input is to be reduced, and receiving video input comprising a first and a second plurality of pictures. The method also...http://www.google.com/patents/US7957470?utm_source=gb-gplus-sharePatent US7957470 - System and method for adapting video decoding rateAdvanced Patent SearchPublication numberUS7957470 B2Publication typeGrantApplication numberUS 12/143,956Publication dateJun 7, 2011Filing dateJun 23, 2008Priority dateDec 14, 1999Fee statusPaidAlso published asCA2394352A1, CA2394352C, EP1243141A1, EP1243141B1, EP2362659A1, EP2362659B1, US7869505, US8223848, US8429699, US20020009149, US20040218680, US20080253464, US20080279284, WO2001045425A1Publication number12143956, 143956, US 7957470 B2, US 7957470B2, US-B2-7957470, US7957470 B2, US7957470B2InventorsArturo A. Rodriguez, Peter Chan, Ajith Nair, Ramesh Nallur, Shashi GoelOriginal AssigneeRodriguez Arturo A, Peter Chan, Ajith Nair, Ramesh Nallur, Shashi GoelExport CitationBiBTeX, EndNote, RefManPatent Citations (101), Non-Patent Citations (52), Referenced by (3), Classifications (57), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetSystem and method for adapting video decoding rate
US 7957470 B2Abstract
An embodiment of the present invention provides systems and methods for adaptive video decoding. An example method includes determining that a video decoding rate of received video input is to be reduced, and receiving video input comprising a first and a second plurality of pictures. The method also includes reducing the video decoding rate while maintaining synchronization with an unmodified audio decoding rate, responsive to the determining that the video decoding rate of the received video input is to be reduced. The reducing includes foregoing decoding the first plurality of pictures and decoding the second plurality of pictures.
1. A method video decoding method performed by a processor comprising the steps of:
determining that a video decoding rate of received video input is to be reduced;
receiving video input comprising a first and a second plurality of pictures; and
responsive to the determining that the video decoding rate of the received video input is to be reduced, reducing the video decoding rate while maintaining synchronization with an unmodified audio decoding rate, including:
decoding by a video decoder the second plurality of pictures.
9. The DHCT of claim 1, wherein the processor is further configured to determine that the video decoding rate is to be reduced when at least one resource is constrained.
10. The DHCT of claim 1, wherein the processor is further configured to determine that the video decoding rate is to be reduced when inadequate memory is available.
11. The DHCT of claim 1, wherein the processor is further configured to determine that the video decoding rate is to be reduced when inadequate bus bandwidth is available.
12. A video decoding system for adapting to resource constraints, the system comprising:
reduce the video decoding rate and maintain the synchronization; and
configured to forego decoding the first plurality of pictures; and
decode the second plurality of pictures, wherein the reduction in the video decoding rate is responsive to the determination by the processor.
13. The system of claim 12, wherein the decode rate reduction logic further comprises repeating logic configured to repeat presentations of decoded pictures in place of the first plurality of pictures in which decoding was foregone.
14. The system of claim 12, wherein the decode rate reduction logic further comprises audio presentation logic configured to continue presentation of audio at a regular rate and to maintain audio and video synchronization as long as the video decoding rate is reduced.
15. The system of claim 12, further comprising constraint determination logic configured to determine that at least one resource is constrained, wherein the decode rate determination logic is responsive to the constraint determination logic.
16. The system of claim 12, wherein the decode rate determination logic is responsive to inadequate memory availability.
17. The system of claim 12, wherein the decode rate determination logic is responsive to inadequate bus bandwidth availability.
18. The system of claim 12, further comprising termination logic configured to terminate the reduced video decoding rate responsive to determining adequate resource availability.
20. The DHCT of claim 19, wherein the processor is further configured to repeat presentations of decoded pictures in place of the first plurality of pictures in which decoding was foregone.
This application is a divisional of U.S. patent application Ser. No. 10/854,874, now U.S. Pat. No. 7,869,505 filed May 27, 2004, which is a divisional of U.S. patent application Ser. No. 09/736,661, filed Dec. 14, 2000, which claims the benefit of U.S. Provisional Application No. 60/170,995, filed on Dec. 14, 1999, each of which is entirely incorporated herein by reference.
The video decoder 81 is assigned higher priority access to media memory 60 than any data transfer operation from system memory 49 to media memory 60. Consequently, graphical and textual objects produced by the processor 44 are subject to limited bus bandwidth to media memory 60 under tight bus bandwidth conditions and limited memory allocation. Furthermore, according to the memory limits of DHCTs 16, the color-depth and spatial resolution of the graphics overlay are constrained; the latter to a proportional horizontal and vertical dimension of the video picture resolution. Consequently, the video decoder 81 of this invention operates in one of two states: a non-constrained-resource-state, and a constrained-resource-state. In one embodiment, the memory controller in media engine 80 operates under a fixed priority scheme as predetermined and programmed into media engine 80 regardless of the resource state. In the non-constrained-resource-state, the high priority access to resources assigned to the video decoder 81 results in non-compromised picture quality, full-scale video picture and full picture rate, but the graphics overlay is potentially compromised. The graphics overlay is maintained with reduced spatial resolution and/or color depth but expanded to the video picture resolution on the way to the DENC 84 in a Display pipeline 85 circuit in the media engine 80. This results in reduced number of bytes and bus bandwidth consumed by operations that access the display buffer 66 and alpha-blend-plane 67. The expansion of the graphics overlays resolution is achieved by a Horizontal Picture Scaling Circuit (HPSC) 87 and a Vertical Picture Scaling Circuit (VPSC) 86, both located within the Display pipeline 85. Line buffers inside the display pipeline 85 or elsewhere in the media engine 80 serve as temporary repository memory to effect the scaling operations.
A �memory� constrained-resource state results in the video decoder 81 consuming less memory. For decompression of a compressed MPEG-2 video, memory reduction may result from eliminating decompression and reconstruction of B frames completely. This facilitates having to maintain a picture buffer with two rather than three sections in media memory 60; one section is used to store the past reference picture and the second to reconstruct the picture being decoded. Thus, the video decoder 81 decompresses only the I and P frames when it does not have sufficient memory to store all of the reference pictures. A decompression frame sequence could potentially be: F1, F4, F7, F10 F13, . . . Fk. The interspersed compressed B frames can be skipped because they do not serve as reference pictures. A preceding reference frame may be displayed in place of a skipped B frame such that a displayed frame sequence may be: F1, F1, F1, F4 F4, F4, F7, F7, F7, F10, F10, F10, . . . Fk. The memory resources freed up by foregoing decompression of B frames may then be allocated for storing other data such as graphical or text data as illustrated in FIG. 5A.
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No. 10/891,318 mailed Mar. 19, 2009.51Written Opinion cited in PCT/US00/33837 mailed Dec. 27, 2001.52Written Opinion cited in PCT/US02/40828 mailed Dec. 16, 2003.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8744167 *Dec 14, 2009Jun 3, 2014Samsung Electronics Co., Ltd.Method, medium, and apparatus of filtering depth noise using depth informationUS20100183236 *Dec 14, 2009Jul 22, 2010Samsung Electronics Co., Ltd.Method, medium, and apparatus of filtering depth noise using depth informationUS20100296572 *Jul 16, 2008Nov 25, 2010Kumar RamaswamyMethods and systems for transcoding within the distributiion chain* Cited by examinerClassifications U.S. Classification375/240.25, 382/239, 375/240.02, 382/235, 382/233, 375/240.28, 375/240.26International ClassificationH04N7/50, H04N7/46, H04B1/66, H04N7/26, H04N7/24, H04N21/258, H04N21/2662, H04N21/45, H04N21/4402, H04N21/454, H04N21/462Cooperative ClassificationH04N19/577, H04N19/587, H04N19/423, H04N19/90, H04N19/44, H04N21/4516, H04N19/159, H04N19/172, H04N19/156, H04N19/428, H04N19/132, H04N19/59, H04N19/61, H04N19/127, H04N19/42, H04N21/25808, H04N21/4621, H04N21/440263, H04N21/2662, H04N21/454European ClassificationH04N7/26L, H04N7/26Z6, H04N7/26D, H04N7/26A6R, H04N7/26A8P, H04N7/46E, H04N7/46S, H04N7/46T2, H04N7/26L2D4D, H04N7/26L2, H04N7/50, H04N7/26A4R, H04N7/26A6S2, H04N21/462Q, H04N21/454, H04N21/258C, H04N21/2662, H04N21/45M1, H04N21/4402SLegal EventsDateCodeEventDescriptionDec 8, 2014FPAYFee paymentYear of fee payment: 4Jul 27, 2009ASAssignmentOwner name: SCIENTIFIC-ATLANTA, LLC, GEORGIAFree format text: CHANGE OF NAME;ASSIGNOR:SCIENTIFIC-ATLANTA, INC.;REEL/FRAME:023012/0703Effective date: 20081205RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services