Source: http://www.google.com/patents/US7672186?dq=6076065
Timestamp: 2014-09-02 21:38:26
Document Index: 371028741

Matched Legal Cases: ['art.\n3', 'art.\n4', 'art 1', 'art 2', 'art 3', 'art 5', 'art 6', 'art 3', 'art 4', 'art 5', 'art 3', 'art 4', 'art 5', 'art 1', 'art 2', 'art 3', 'art 4', 'art 5', 'art 6']

Patent US7672186 - Antifuse replacement determination circuit and method of semiconductor ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsAn antifuse replacement determination circuit of a semiconductor memory device, in which the address of a bad memory cell is stored by destroying the insulation of an antifuse element, includes a charging circuit for charging a node of the antifuse element to have a predetermined voltage, and making...http://www.google.com/patents/US7672186?utm_source=gb-gplus-sharePatent US7672186 - Antifuse replacement determination circuit and method of semiconductor memory deviceAdvanced Patent SearchPublication numberUS7672186 B2Publication typeGrantApplication numberUS 12/129,168Publication dateMar 2, 2010Filing dateMay 29, 2008Priority dateJun 1, 2007Fee statusPaidAlso published asUS7983105, US20080298145, US20100103750Publication number12129168, 129168, US 7672186 B2, US 7672186B2, US-B2-7672186, US7672186 B2, US7672186B2InventorsMasamichi OgishimaOriginal AssigneeElpida Memory, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (5), Classifications (13), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetAntifuse replacement determination circuit and method of semiconductor memory deviceUS 7672186 B2Abstract An antifuse replacement determination circuit of a semiconductor memory device, in which the address of a bad memory cell is stored by destroying the insulation of an antifuse element, includes a charging circuit for charging a node of the antifuse element to have a predetermined voltage, and making the charge at the node self-discharge via the antifuse element after the charging of the node is completed; a comparison and determination circuit for comparing the voltage at the node of the antifuse element with a plurality of reference voltages when a predetermined time has elapsed after the completion of the charging of the node; and a determination part for determining, based on a determination result with respect to the comparison using the plurality of reference voltages in the comparison and determination circuit, whether or not replacement of the bad memory cell has been performed normally by using the antifuse element.
1. An antifuse replacement determination circuit of a semiconductor memory device, wherein:
it is determined by the antifuse replacement determination circuit whether or not the replacement of the bad memory cell has been performed normally by using the antifuse element, and
an antifuse element charging circuit for charging a node of the antifuse element to have a predetermined voltage, and making the charge at the node self-discharge via the antifuse element after the charging of the node is completed;
a comparison and determination circuit for comparing the voltage at the node of the antifuse element with a plurality of reference voltages when a predetermined time has elapsed after the completion of the charging of the node; and
an AF destruction result determination part for determining, based on a determination result with respect to the comparison using the plurality of reference voltages in the comparison and determination circuit, whether or not the replacement of the bad memory cell has been performed normally by using the antifuse element.
2. The antifuse replacement determination circuit in accordance with claim 1, wherein:
a first comparison and determination circuit for comparing the voltage at the node of the antifuse element with a first reference voltage VREF1;
a first latch circuit for storing a determination result with respect to the comparison of the first comparison and determination circuit;
a second comparison and determination circuit for comparing the voltage at the node of the antifuse element with a second reference voltage VREF2, wherein VREF1>VREF2;
a second latch circuit for storing a determination result with respect to the comparison of the second comparison and determination circuit;
a third comparison and determination circuit for comparing the voltage at the node of the antifuse element with a third reference voltage VREF0, wherein VREF1>VREF0>VREF2;
a third latch circuit for storing a determination result with respect to the comparison of the third comparison and determination circuit; and
a transfer-gate part for selecting one of the determination results stored in the latch circuits and transmitting the selected result to the AF destruction result determination part.
3. The antifuse replacement determination circuit in accordance with claim 2, further comprising:
a first determination executing part for making the first comparison and determination circuit compare the voltage at the node of the antifuse element with the first reference voltage VREF1, and transmitting the determination result stored in the first latch circuit to the AF destruction result determination part via the transfer-gate part;
a second determination executing part for making the second comparison and determination circuit compare the voltage at the node of the antifuse element with the second reference voltage VREF2, and transmitting the determination result stored in the second latch circuit to the AF destruction result determination part via the transfer-gate part; and
a third determination executing part for making the third comparison and determination circuit compare the voltage at the node of the antifuse element with the third reference voltage VREF0, and transmitting the determination result stored in the third latch circuit to the AF destruction result determination part via the transfer-gate part.
4. The antifuse replacement determination circuit in accordance with claim 1, wherein:
a transfer-gate part for selecting one of a first reference voltage VREF1, a second reference voltage VREF2, and a third reference voltage VREF0 for comparison with the voltage at the node of the antifuse element, and transmitting the selected reference voltage to the comparison and determination circuit, wherein VREF1>VRFF0>VREF2;
a first determination executing part for making the transfer-gate part select the first reference voltage VREF1, and making the comparison and determination circuit compare the voltage at the node of the antifuse element with the first reference voltage VREF1;
a second determination executing part for making the transfer-gate part select the second reference voltage VREF2, and making the comparison and determination circuit compare the voltage at the node of the antifuse element with the second reference voltage VREF2;
a third determination executing part for making the transfer-gate part select the third reference voltage VREF0, and making tie comparison and determination circuit compare the voltage at the node of the antifuse element with the third reference voltage VREF0; and
a single latch circuit for storing a determination result with respect to the comparison of the comparison and determination circuit.
5. The antifuse replacement determination circuit in accordance with claim 3, wherein the AF destruction result determination part determines that:
the antifuse element is in a normal state when it is determined through the operation of the first determination executing part that the voltage at the node of the antifuse element is higher tan or equal to the first reference voltage VREF1, and the antifuse element has an anticipated value which indicates non-destruction;
the antifuse element is in a normal state when it is determined through the operation of tie second determination executing part that the voltage at the node of the antifuse element is lower than the second reference voltage VREF2, and the antifuse element has an anticipated value which indicates destruction; and
6. The antifuse replacement determination circuit in accordance with claim 4, wherein the AF destruction result determination part determines that:
the antifuse element is in a normal state when it is determined through the operation of the first determination executing part that the voltage at the node of the antifuse element is higher than or equal to the first reference voltage VREF1, and the antifuse element has an anticipated value which indicates non-destruction;
the antifuse element is in a normal state when it is determined through the operation of the second determination executing part that the voltage at the node of the antifuse element is lower than the second reference voltage VREF2, and the antifuse element has an anticipated value which indicates destruction; and
7. The antifuse replacement determination circuit in accordance with claim 5, wherein when the antifuse element has an anticipated value which indicates destruction, if it is determined through the operation of the first determination executing part that the voltage at the node of the antifuse element is lower than the first reference voltage VREF1, and it is also determined through the operation of the second determination executing part that the voltage at the node of the antifuse element is higher than or equal to the second reference voltage VREF2, then the AF destruction result determination part generates a signal for indicating a determination that the antifuse element should be destroyed again.
8. The antifuse replacement determination circuit in accordance with claim 6, wherein when the antifuse element has an anticipated value which indicates destruction, if it is determined through the operation of the first determination executing part that the voltage at the node of the antifuse element is lower than the first reference voltage VREF1, and it is also determined through the operation of the second determination executing part that the voltage at the node of the antifuse element is higher than or equal to the second reference voltage VREF2, then the AF destruction result determination part generates a signal for indicating a determination that the antifuse element should be destroyed again.
9. The antifuse replacement determination circuit in accordance with claim 5, wherein the AF destruction result determination part determines that:
the antifuse element is in a normal state when it is determined through the operation of the third determination executing part that the voltage at the node of the anise element is higher than or equal to the third reference voltage VREF0, and the antifuse element has an anticipated value which indicates non-destruction;
10. The antifuse replacement determination circuit in accordance with claim 6, wherein the AF destruction result determination part determines that:
the antifuse element is in a normal state when it is determined through the operation of the third determination executing part that the voltage at the node of the antifuse element is higher than or equal to the third reference voltage VREF0, and the antifuse element has an anticipated value which indicates non-destruction;
the antifuse element has a failure when it is determined through the operation of the third determination executing part that the voltage at the node of the antifuse element is higher tan or equal to the third reference voltage VREF0, and the antifuse element has an anticipated value which indicates destruction.
11. The antifuse replacement determination circuit in accordance with claim 2, wherein:
the first reference voltage VREF1 is 0.35V;
12. The antifuse replacement determination circuit in accordance with claim 4, wherein:
13. An antifuse replacement determination method used in a semiconductor memory device, wherein:
an antifuse element charging step of charging a node of the antifuse element to have a predetermined voltage, and making the charge at the node self-discharge via the antifuse element after the charging of the node is completed;
a comparison and determination step of comparing the voltage at the node of the antifuse element with a plurality of reference voltages when a predetermined time has elapsed after the completion of the charging of the node; and
an AF destruction result determination step of determining, based on a determination result with respect to the comparison using the plurality of reference voltages in the comparison and determination step, whether or not the replacement of the bad memory cell has been performed normally by using the antifuse element.
With respect to dynamic memory circuits, a so-called �AF (antifuse) circuit� is known, in which an address of a bad bit (i.e., a bad memory cell) is stored by destroying a semiconductor element (a capacitance element or a MOS transistor), and when this address is selected, data is stored not in an ordinary DRAM memory cell, but in an SRAM element (or a flip-flop circuit). In the following description, such a replacement of an ordinary memory cell with an SRAM element (or a flip-flop circuit) is called �replacement by AF� or �AF replacement�. In addition, the destroyed semiconductor element is called an �AF element�.
When a memory device having an AF circuit is initialized so as to be actually used, the target address with respect to the AF replacement should be defined (this is called �Load�, which will be explained in detail later) by determining whether the relevant AF element has been destroyed. Such a determination is performed by supplying, in advance, an (electric) charge having a specific level to a node (or contact point) in the vicinity of a node of the AF element, and comparing the level of the charge with a reference level so as to determine whether the charge has escaped through the node due to the destruction of the AF element. Generally, the reference level is set to an optimum value for determining whether or not the AF element has been destroyed (called �AF destruction determination� below).
With respect to DRAMs, the yield decreases when a device, which does not normally operate and is determined to be a substandard product in a screening process, is found. Such a decrease in the yield prevents the reduction of the screening and forwarding cost. Recently, in most cases, approximately one or two bits which have a physical defect in each relevant memory cell cause a substandard product. Therefore, when such one or two bits are replaced by an AF circuit so as to produce a standard product the screening yield can be improved, and the manufacturing cost can be reduced.
More specifically, when one bit is replaced, the AY circuit generally have a number of AF elements, the number corresponding to the number of addresses (e.g., 26 addresses, where X=X0 to X13, Y=Y0 to Y9, Bank0, and Bank1); corresponding AF circuits for destroying and determining the AF elements; and another AF element and another AF circuit for determining whether the antifuse of the relevant one bit is to be activated. That is, when there are 26 addresses, 27 sets of the AF element and the AF circuit are provided.
When a substandard product is found in a screening process, first, the address of the bad bit is confirmed, and the AF element corresponding to this address is destroyed. This operation is called �Store�, and the process of performing Store is called a �Store process�. Next, it is confirmed if the address, which has been stored due to the destruction of the AF element, coincides with the anticipated address. This operation is called �Verify�, and the process of performing Verify is called a �Verify process�.
After that, AF replacement is performed, and normal operation of the relevant DRAM is confirmed by performing the screening process again. In the normal function of re-screening or ordinary use thereafter, when the relevant DRAM is initialized immediately after the power-on, an AF destruction determination similar to the above Verify is performed, and the result thereof is latched (i.e., stored). This operation is called �Load�, and the process of performing Load is called a �Load process�.
FIG. 5 shows a conventional AF destruction determination circuit. In FIG. 5, an AF destruction determination sequence control part 1A controls each part shown in FIG. 5 so as to perform the AF destruction determination. A charging control part 2 generates a �/Charge� signal for charging a node (or contact point) X1 of an AF element 11 via a node X0 in the vicinity of the AF element 11. A Verify execution part 3A generates a Verify signal for commanding the execution of the Verify process. A Load execution part 5 generates a Load signal for commanding the execution of the Load process. An AF destruction result determination part 6 determines whether a result of the AF destruction determination coincides with the anticipated result based on a determination result BB obtained through the Verify and Load processes.
Although detailed explanations of the AF element 11 and an AF element destruction circuit 12 are omitted, a DRAM-cell capacitance element or an N-channel transistor is used as the AF element and the AF element destruction circuit 12 generates and controls a high voltage for destructing such a capacitance element or a gate oxide film of the transistor. The AF element has the node X1, and the other node thereof is ordinarily connected to VSS (the source potential). Therefore, the node X1 of the destroyed AF element is conductive with VSS (via a low resistance).
The gate of a P-channel transistor P1 is connected to the output of a NOR circuit 13. When the Verify or Load signal input into the NOR circuit 13 has a value of �1�, the P-channel transistor P1 is switched on. That is, in the Verify and Load processes, a control for making the node X1 of the AF element be conductive with the node X0 of a comparison and determination circuit 20 (�AMP�).
In the Verify and Load processes, a P-channel transistor PO is switched on when charging the nodes X0 and X1 to an initial precharge level VCHARGE (e.g., 1.4V) The comparison and determination circuit 20 compares the potential of the node X0 with a reference level VREF0 (e.g., 1.1V). A flip-flop circuit 30 above the comparison and determination circuit 20 latches (i.e., stores) a determination result BB output from the comparison and determination circuit 20.
Below, the relevant AF destruction determination in accordance with a conventional technique will be explained with reference to FIGS. 5 and 6. In the AF destruction determination in the structure of FIG. 5, first, (i) the P-channel transistor P1 is switched on by means of the Verify or Load signal, so that the nodes X0 and X1 are conductive with each other, and (ii) the P-channel transistor P0 is switched on by means of the /Charge signal (see time t1 in FIG. 6), so as to precharge the nodes X0 and X1 to the level VCHARGE. This process corresponds to the �precharge period T1 using VCHARGE� in FIG. 6.
Next, the state of the /Charge signal is switched so as to switch off the P-channel transistor P0, thereby setting the nodes X0 and X1 to be in a floating state (see time t2 in FIG. 6). If the AF element 11 has not been destroyed, no charge loss occurs at the nodes X0 and X1, and thus they maintain the level VCHARGE (here, 1.4V, see the discharge curve Ds1 in FIG. 6). This level is higher than the reference level VREF0 (here, 1.1V) applied to the other input of the comparison and determination circuit 20. Therefore, a result of the AF destruction determination, which indicates that the AF element has not been destroyed, is obtained, and is stored as the determination result BB. In this case, as the anticipated value with respect to Verify indicates that the AF element has not been destroyed, it coincides with BB, so that the result of Verify is �Pass� (which means passing the relevant examination).
When the potential of the node X0 stays higher than VREF (1.1V), the result of the AF destruction determination, which indicates that the AF element has not been destroyed, is obtained even though the operator or user believes that the AF element has been destroyed. As this result is stored as BB, it does not coincide with the relevant anticipated value, so that the result of Verify is �Fail� (which indicates failing the relevant examination).
The above-described process corresponds to the �X0-reference level comparison and determination period T2�, in which the level of the /Charge signal is high, the P-channel transistor P0 is switched off, and the comparison and determination circuit 20 is activated.
With respect to a device, which has been determined to be a Fail device in the Verify process, no address replacement by means of the AF element 11 is performed in the Load process during actual use. In the re-screening process performed after the AF replacement process) or during actual use, a DRAM memory cell (in such a device), which has been determined to be a bad cell in the former screening, is selected, so that the device is determined to be a substandard product, and thus does not contribute to an increase in the yield. Therefore, the operation from the Store process is performed again.
The relevant conventional AF replacement processes will be shown in FIG. 7. In a screening process 51, a bad address is extracted from a device which is determined to be a substandard product. The AF element 11 corresponding to the above address is destroyed in a Store process 52. In a Verify process 53, the result of the AF element destruction is confirmed by the Verify operation using VREF0 (1.1V) as the reference voltage. When the relevant device obtains a result of Pass, it is forwarded to the next rescreening process 54.
In a DRAM initializing sequence of the re-screening process 54, an AF destruction determination similar to that performed in the Verify process 53 is performed in the Load operation. The result thereof is stored, and the relevant bad bit is replaced by means of the AM element 11, so that the device which obtains the Pass result is forwarded for shipment.
On the other hand, a device which obtains a Fail result in the Verity process 53 is subjected to the Store process 52 again, so as to repeat the series of the relevant processes until it obtains a Pass result in the Verify process 53.
The most serious problem with respect to the above-described AF replacement is that the decreased potential of the node X0 reaches almost the same level of VRFF0 (1.1V) due to insufficiently-decreased resistance of the AF element b this case, every time the AF replacement determination is performed, a different result may be obtained. For example, if a device obtains a Pass result (in the Verify process 53) due to �the level at X0<VREF0� (which is narrowly satisfied) by which it is determined that the AF element has been destroyed, ten it may be determined that the AT element has not been destroyed (in the Load operation of the re-screening process 54) due to �the level at X0>VREF0�. In this case, this device is determined to be a substandard product in the relevant re-screening process, and cannot contribute to an increase in the yield. Additionally, if such a device accidentally obtains a Pass result in the re-screening process 54 due to a determination that the AF element has been destroyed, and it is determined in the Load process during actual use (after the shipment) that the AF element has not been destroyed, then it causes a worse result such as the occurrence of a substandard market product.
In a conventional semiconductor integrated circuit device disclosed in Patent Document 1 (Japanese Unexamined Patent Application, First Publication No. 2002-074980), a specific node (e.g., �FUADD� in FIG. 1) is monitored so as to determine whether or not the relevant fuse should be subjected to a programmed operation.
As described later, the present invention provides a voltage comparison circuit for comparing the voltage at a node of the AM element with a plurality of reference voltages so as to more reliably determine the destruction or non-destruction of the AF element. Therefore, the method and structure for the determination are different between Patent Document 1 and the present invention.
As described above, in the conventional technique, a device having an unstable result of the AF replacement is obtained due to an insufficiently decreased resistance of the destroyed AF element and such a device does not contribute to an increase in the relevant yield, or produces a substandard market product as a worse result.
SUMMARY OF THE INVENTION In light of the above circumstances, an object of the present invention is to provide an antifuse replacement determination circuit of a semiconductor memory device, and a relevant antifuse replacement determination method, so as to detect that the AF replacement has been reliably performed, and to prevent a substandard product from occurring due to an erroneous determination applied to the AF element in the re-screening process, thereby achieving an anticipated increase in the yield, and preventing au erroneous determination with respect to the AF element from occurring in actual use after the shipment.
the semiconductor memory device has a memory cell array in which data is stored in each memory cell, and the address of a bad memory cell is stored as a bad address by destroying the insulation of an antifuse element so as to replace the bad memory cell with another memory element; it is determined by the antifuse replacement determination circuit whether or not the replacement of the bad memory cell has been performed normally by using the antifuse element; and the antifuse replacement determination circuit comprises:
the comparison and determination circuit includes three Comparison and determination circuits; and the antifuse replacement determination circuit has:
a first comparison and determination circuit for comparing the voltage at the node of the antifuse element with a first reference voltage VREF1; a first latch circuit for storing a determination result with respect to the comparison of the first comparison and determination circuit; a second comparison and determination circuit for comparing the voltage at the node of the antifuse element with a second reference voltage VREF2, wherein VREF1>VREF2; a second latch circuit for storing a determination result with respect to the comparison of the second comparison and determination circuit; a third comparison and determination circuit for comparing the voltage at the node of the antifuse element with a third reference voltage VREF0, wherein VREF1>VREF0>VREF2; a third latch circuit for storing a determination result with respect to the comparison of the third comparison and determination circuit; and a transfer-gate part for selecting one of the determination results stored in the latch circuits and transmitting the selected result to the AF destruction result determination part. In the above structure including the three comparison and determination circuits, the determination result obtained by each comparison arid determination circuit is transmitted to the AF destruction result determination pan via the transfer-gate part.
a first determination executing part (e.g., a Verify1 execution part 3 in a first embodiment explained later) for making the first comparison and determination circuit compare the voltage at the node of the antifuse element with the first reference voltage VREF1, and transmitting the determination result stored in the first latch circuit to the AF destruction result determination part via the transfer-gate part; a second determination executing part (e.g., a Verify2 execution part 4 in the embodiment) for making the second comparison and determination circuit compare the voltage at the node of the antifuse element with the second reference voltage VREF2, and transmitting the determination result stored in the second latch circuit to the AF destruction result determination part via the transfer-gate part; and a third determination executing part (e.g., a Load execution part 5 in the embodiment) for making the third comparison and determination circuit compare the voltage at the node of the antifuse element with the third reference voltage VRFF0, and transmitting the determination result stored in the third latch circuit to the AF destruction result determination part via the transfer-gate part. In another typical example:
the comparison and determination circuit has a single comparison and determination circuit; and the antifuse replacement determination circuit has:
a transfer-gate part for selecting one of a first reference voltage VREF1, a second reference voltage VREF2, and a third reference voltage VREF0 for comparison with the voltage at the node of the antifuse element, and transmitting the selected reference voltage to the comparison and determination circuit, wherein VREF1>VREF0>VREF2; a first determination executing part for making the transfer-gate part select the first reference voltage VREF1, and making the comparison and determination circuit compare the voltage at the node of the antifuse element with the first reference voltage VREF1; a second determination executing part for making the transfer-gate part select the second reference voltage VREF2, and making the comparison and determination circuit compare the voltage at the node of the antifuse element with the second reference voltage VREF2; a third determination executing part for making the transfer-gate part select the third reference voltage VREF0, and making the comparison and determination circuit compare the voltage at the node of the antifuse element with the third reference voltage VREF0; and a single latch circuit for storing a determination result with respect to the comparison of the comparison and determination circuit. In this structure having a single comparison and determination circuit, and the reference voltage input into the comparison and determination circuit is selected by switching, so that the voltage at the node of the antifuse element can be compared with the relevant three reference voltages. Accordingly in addition to the effect that the voltage at the node of the antifuse element can be compared with the relevant tree reference voltages, the area of the antifuse replacement determination circuit can be reduced.
the antifuse element is in a normal state when it is determined through the operation of the first determination executing part (e.g., the Verify1 execution part 3 in embodiments explained later) that the voltage at the node of the antifuse element is higher Man or equal to the first reference voltage VREF1 (corresponding to the maximum reference level in the embodiments), and the antifuse element has an anticipated value which indicates non-destruction; the antifuse element has a failure when it is determined through the operation of the first determination executing part that the voltage at the node of the antifuse element is lower t the first reference voltage VREF1, and tie antifuse element has an anticipated value which indicates non-destruction; the antifuse element is in a normal state when it is determined through the operation of the second determination executing part (e.g., the Verify2 execution part 4 in the embodiments) that the voltage at the node of the antifuse element is lower than the second reference voltage VREF2 (corresponding to the minimum reference level in the embodiments), and the antifuse element has an anticipated value which indicates destruction; and the antifuse element has a failure when it is determined through the operation of the second determination executing part that the voltage at the node of the antifuse element is higher than or equal to the second reference voltage VREF2, and the antifuse element has an anticipated value which indicates destruction. Accordingly, an erroneously-destroyed mode can be determined to be a failure by means of a comparison with the first reference level VREF1 (i.e., the maximum reference level), while an insufficiently-destroyed mode can be determined to be a failure by means of a comparison with the second reference level VRFF2 (i.e., the minimum reference level), thereby performing a more strict judgment in comparison with the conventional techniques. Therefore, in a Load process during re-screening or ordinary use, a stable determination result can be obtained through a determination using the third reference level VREF0 (VREF1>VREF0>VREF2), thereby considerably reducing the occurrence of a substandard product during re-screening or ordinary use.
In this case, typically, when the antifuse element has an anticipated value which indicates destruction, if it is determined through the operation of the fist determination executing part that the voltage at the node of the antifuse element is lower than the first reference voltage VREF1, and it is also determined through the operation of the second determination executing part that the voltage at the node of the antifuse element is higher tan or equal to the second reference voltage VREF2 (i.e., VREF1>the voltage of the node>VREF2), then the AF destruction result determination part generates a signal for indicating a determination that the antifuse element should be destroyed again.
the antifuse element is in a normal state when it is determined though the operation of the third determination executing part (e.g., the Load execution part 5 in the embodiments) that the voltage at the node of the antifuse element is higher than or equal to the third reference voltage VREF0 (corresponding to the intermediate reference level in the embodiments), and the antifuse element has an anticipated value which indicates non-destruction; the antifuse element has a failure when it is determined through the operation of the third determination executing part that the voltage at the node of the ant se element is lower than the third reference voltage VREF0, and the antifuse element has an anticipated value which indicates non-destruction; the antifuse element is in a normal state when it is determined through the operation of the third determination executing part that the voltage at the node of the antifuse element is lower than the third reference voltage VREF0, and the antifuse element has an anticipated value which indicates destruction; and the antifuse element has a failure when it is determined through the operation of the third determination executing part that the voltage at the node of the antifuse element is higher than or equal to the third reference voltage VREF0, and the antifuse element has an anticipated value which indicates destruction. Therefore, after the AF-element destruction determination is performed using the first and second determination executing parts, it can be performed by the third determination executing part. Therefore, a stable determination result can be obtained, thereby considerably reducing the occurrence of a substandard product dug re-screening or ordinary use.
the predetermined voltage applied to the node of the antifuse element is 1.4V; the first reference voltage VREF1 is 0.35V; the second reference voltage VREF2 is 0.95V; and the third reference voltage VREF0 is 1.1V. Accordingly, it is possible to reliably perform the destruction determination of the antifuse element by using a power source voltage of the semiconductor memory device.
the semiconductor memory device has a memory cell array in which data is stored in each memory cell, and the address of a bad memory cell is stored as a bad address by destroying the insulation of an antifuse element so as to replace the bad memory cell with another memory element; it is determined by the antifuse replacement determination method whether or not the replacement of the bad memory cell has been performed normally by using the antifuse element; and the antifuse replacement determination method comprises:
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the structure of an antifuse replacement determination circuit of a semiconductor memory device, with respect to a first embodiment of the present invention.
FIG. 6 is a diagram for explaining the AT destruction determination with respect to the conventional semiconductor memory device.
FIRST EMBODIMENT FIG. 1 is a diagram showing the structure of an antifuse replacement determination circuit of a semiconductor memory device, with respect to a first embodiment of the present invention.
In FIG. 1, an AF destruction determination sequence control part 1 controls each part shown in FIG. 1 so as to perform the AF destruction determination. A charging control part 2 generates a �/Charge� signal for charging the nodes X0 and X1 of an AF element 11. A �Verify1� execution part 3 generates a Verity1 signal for commanding the execution of a Verify1 process. A �Verify2� execution part 4 generates a Verify2 signal for commanding the execution of a Verify2 process. A Load execution part 5 generates a Load signal for commanding the execution of the Load process. An AF destruction result determination part 6 determines whether a result of the AF destruction determination coincides with an anticipated result (destruction or non-destruction), based on a determination result BB obtained through the Verify1, Verify2, and Load processes, which use comparison and determination circuits.
In the Verify1 operation, the comparison and detention circuit 21 (�AMP-V1�) compares the potential of the node X0 with the reference level VREF1 (e.g., 1.35V). In the Verify2 operation, the comparison and determination circuit 22 (�AMP-V2�) compares the potential of the node X0 with the reference level VREF2 (e.g., 0.95V). In the Load operation, the comparison and determination circuit 23 (�AMP-VL�) compares the potential of the node X0 with the reference level VREF0 (e.g., 1.1V).
The flip-flop circuits 31 to 33, which respectively correspond to the comparison and determination circuits 21 to 23, respectively latch (i.e., store) the results of determination output from the comparison and determination circuits 21 to 23. The signals output from the flip-flop-circuits 31 to 33 are respectively input into transfer gates 41 to 43 which respectively correspond to the flip-flop circuits 31 to 33. The transfer gates 41 to 43 each include a P-channel transistor, an N-channel transistor, and a gate circuit, and are provided for selecting and outputting one of a plurality of input signals (i-e., input from the flip-flop circuits 31 to 33).
Below, the relevant AF destruction determination in the antifuse replacement determination circuit of FIG. 1 will be explained with reference to FIG. 2. In the AF destruction determination, first, (i) the P-channel transistor PI is switched on by means of the Verify1, Verify2, or Load signal, so that the nodes X0 and X1 are conductive with each other, and (ii) the P-channel transistor PO is switched on by means of the /Charge signal (see time t1 in FIG. 2) whose level is shifted to Low (low level), so as to precharge the nodes X0 and X1 to the level VCHARGE (here, 1.4V). This process corresponds to the �precharge period T1 using VCHARGE� in FIG. 2.
Next, the level of the /Charge signal is shifted to nigh (high level) so that the �X0-reference level comparison and determination period T2� starts. When the level of the /Charge signal is set to High (see time t2), the P-channel transistor P0 is switched off, and the nodes X0 and X1 are set to be in a floating state. If the AF element has not been destroyed in this state, no charge loss occurs at the nodes X0 and X1, and thus they maintain the level VCHARGE (here, 1.4V).
In this state, first, the comparison and determination process is performed by the comparison and determination circuit 21 by using Verify1. If it is true that the AF element 11 has not been destroyed, the relevant level (i.e., 1.4V) is higher than the reference level VREF1 (1.35V) applied to the other input of the comparison and determination circuit 21, so that an AF destruction determination that the AF element has not been destroyed is obtained, and the corresponding result �Pass� is stored in the flip-flop circuit 31. This result is output via the transfer gate 41 as the determination result BB (Pass).
However, if the AF element has not been normally formed in the manufacturing process, or has been destroyed for any reason although it was not intended to be destroyed (that is, in a half-destroyed state), then the AF element may discharge toward the node VSS (on the opposite side with respect to the node X1) although it has a considerably high resistance. In this case, the potential level of the AF element may decrease below the VREF1 (1.35V), and a determination result (�Fail�) that the AF element has been destroyed is stored in the flip-flop circuit 31. This result is output via the transfer gate 41 as the determination result BB (Fail). As this result is opposite to the anticipated value of the Verify1 (i.e., �the AF element has not bee destroyed�), a determination result �Fail� is obtained. As such a device cannot be subjected to the AF replacement, it is disposed of as a substandard product (because there occurred a fault in the manufacturing process).
The next comparison and determination process is performed by the comparison and determination circuit 22 by using Verify2. In the comparison and determination using Verify2, if the AF element 11 has not been destroyed, then similar to the comparison and determination using Verify1, the level of the node X0 is higher than the reference level VREF2 (0.95V) for Verify2, so that an AF destruction determination that the AF element has not been destroyed is obtained, and the corresponding result is stored in the flip-flop circuit 32. This result is output via the transfer gate 42 as the determination result BB, i.e., �Pass� (of Verify2) which coincides with the anticipated value.
If the AF element has been destroyed, then when it has a relatively low resistance due to sufficient destruction thereof, and thus the potential level of the node X0 is lower than VREF2 (0.95V) for Verify2, the AF destruction determination provides a result that �the AF element has been destroyed� which coincides with the relevant anticipated value, so that the result of Verify is �Pass�. However, if the destruction state is insufficient although the AF element has bee destroyed, then the potential level of the node X0 does not decrease below VREF2 (0.95V), so that it is determined that �the AF element has not been destroyed� which does not coincide with the anticipated value. Therefore, the result of Verify2 by means of the comparison and determination circuit 22 is �Fail�. Similar to the convectional AF replacement, such a device is again subjected to the Store process so as to repeat the series of the relevant processes (because the destruction of the AF element is insufficient).
If it is assumed that a conventional serious problem occurs, in which the potential of the node X0 is almost equal to VREF0, that is, approximately 1.1V, then this level is considerably higher than the level of VREF2 (0.95V), so that a clear result such that �the AF element has not been destroyed� is obtained by the comparison and determination circuit 22. Accordingly, the Store process is again repeated.
As described above, in the structure of the present embodiment, no conventional problem occurs, in which the final level of X0 is almost equal to VREF0 (1.1V) due to a half destroyed state of the AF element, and thus every time the AF replacement determination is performed, a different result may be obtained. Therefore, the AF replacement is reliably performed in the present embodiment, and no substandard product due to an erroneous AF destruction determination occurs in the rescreening process, thereby providing an anticipated increase in the yield. Also in the actual use after the shipment, no erroneous AF determination occurs, and thus no substandard market product occurs.
In a screening process 51, a bad address is extracted from a device which is determined to be a substandard product The AF element corresponding to the above address is destroyed in a Store process 52.
In the re-screening process 54, an AF destruction determination similar to the Verify1 and Verify2 processes is performed through a DRAM initializing sequence (using an MRS (mode register set) command or the like) in which �Load� is performed using the reference level VREF0 (1.1V). The result of the determination is stored, and a bad bit is replaced by means of the AF element, so that the relevant device obtains a Pass result in the re-screening, and is forwarded for shipment.
The table of FIG. 3B shows the destruction state of the AF element each condition with respect to the Verify determination, the Verify determination (result), and the application of each sample with respect to each of steps S1 to S9.
As described above, in the structure of the present embodiment, no conventional problem occurs, in which the final level of X0 is almost equal to VREF0 (1.1V) due to a half destroyed state of the AF element, and thus every time the AF replacement determination is performed, a different result may be obtained. Therefore, the AF replacement is reliably performed in the present embodiment, and no substandard product due to an erroneous AF destruction determination occurs in the re-screening process, thereby providing an anticipated increase in the yield Also in the actual use after the shipment, no erroneous AF determination occurs, and thus no substandard market product occurs.
SECOND EMBODIMENT FIG. 4 is a diagram showing the structure of an antifuse replacement determination circuit of a semiconductor memory device, with respect to a second embodiment of the present invention. In the antifuse replacement determination circuit in FIG. 4, the three comparison and determination circuits 21, 22, and 23 used in the antifuse replacement determination circuit in FIG. 1 are integrated as a single comparison and determination circuit 20 (�AMP�), and the flip-flop circuits 31, 32, and 33 in FIG. 1 are also integrated as a single flip-flop circuit 30.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5420821 *Oct 6, 1993May 30, 1995Texas Instruments IncorporatedDecoder for salvaging defective memory cellsUS5487040 *Jul 12, 1993Jan 23, 1996Texas Instruments IncorporatedSemiconductor memory device and defective memory cell repair circuitUS5953266 *Jan 29, 1998Sep 14, 1999Micron Technology, Inc.Device and method for repairing a memory array by storing each bit in multiple memory cells in the arrayUS6784043 *Feb 14, 2003Aug 31, 2004Micron Technology, Inc.Methods for forming aligned fuses disposed in an integrated circuitJP2002074980A Title not available* Cited by examinerClassifications U.S. Classification365/225.7, 365/201International ClassificationG11C11/00Cooperative ClassificationG11C29/02, G11C29/785, G11C29/027, G11C17/18, G11C17/165European ClassificationG11C29/785, G11C17/16R, G11C29/02G, G11C17/18, G11C29/02Legal EventsDateCodeEventDescriptionMay 15, 2014ASAssignmentFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ELPIDA MEMORY, INC.;REEL/FRAME:032899/0588Effective date: 20130726Owner name: PS4 LUXCO S.A.R.L., LUXEMBOURGJul 29, 2013ASAssignmentEffective date: 20130726Free format text: SECURITY AGREEMENT;ASSIGNOR:PS4 LUXCO S.A.R.L.;REEL/FRAME:032414/0261Owner name: ELPIDA MEMORY INC., JAPANMar 14, 2013FPAYFee paymentYear of fee payment: 4Sep 7, 2010CCCertificate of correctionFeb 3, 2009ASAssignmentOwner name: ELPIDA MEMORY, INC., JAPANFree format text: RE-RECORD TO CORRECT THE ASSIGNEE S INFORMATION ON A DOCUMENT PREVIOUSLY RECORDED AT REEL 021614, FRAME 0403. (ASSIGNMENT OF ASSIGNOR S INTEREST);ASSIGNOR:OGISHIMA, MASAMICHI;REEL/FRAME:022219/0354Effective date: 20080528Owner name: ELPIDA MEMORY, INC.,JAPANFree format text: RE-RECORD TO CORRECT THE ASSIGNEE S INFORMATION ON A DOCUMENT PREVIOUSLY RECORDED AT REEL 021614, FRAME 0403. (ASSIGNMENT OF ASSIGNOR S INTEREST);ASSIGNOR:OGISHIMA, MASAMICHI;US-ASSIGNMENT DATABASE UPDATED:20100302;REEL/FRAME:22219/354Oct 1, 2008ASAssignmentOwner name: ELPIDA MEMORY INC., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OGISHIMA, MASAMICHI;REEL/FRAME:021614/0403Effective date: 20080528Owner name: ELPIDA MEMORY INC.,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OGISHIMA, MASAMICHI;US-ASSIGNMENT DATABASE UPDATED:20100302;REEL/FRAME:21614/403RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google