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Matched Legal Cases: ['Application No. 98', 'Application No. 98', 'Application No. 01', 'Application No. 01', 'Application No. 01', 'Application No. 02', 'Application No. 02', 'Application No. 10', 'Application No. 10', 'Application No. 01']

Strained germanium-on-insulator device structures - Patent # 7414259 - PatentGenius
7414259 Strained germanium-on-insulator device structures
Inventor: Langdo, et al.
Application: 11/126,550
Inventors: Langdo; Thomas A. (Cambridge, MA)
Hammond; Richard (Harriseahead, GB)
U.S. Class: 257/18; 257/E29.295
Field Of Search: 257/E29.295; 257/E29.297; 257/E29.298; 257/E29.2; 257/18; 257/190; 257/192
Foreign Patent Documents: 41 01 167; 0 514 018; 0 587 520; 0 683 522; 0 828 296; 0 829 908; 0 838 858; 1 020 900; 1 174 928; 2 701 599; 2 342 777; 61-141116; 2-210816; 3-036717; 4-307974; 5-166724; 6-177046; 6-244112; 06-252046; 7-094420; 7-106446; 7-240372; 9-219524; 10-270685; 11-233744; 2000-021783; 2000-31491; 2001319935; 2002-076334; 2002-164520; 2002-289533; WO 98/59365; WO 99/53539; WO 00/48239; WO 00/54338; WO 01/22482; WO 01/54202; WO 01/93338; WO 01/99169; WO 02/13262; WO 02/15244; WO 02/27783; WO 02/47168; WO 02/071488; WO 02/071491; WO 02/071495; WO 02/082514; WO 2004/006311; WO 2004/006326; WO 2004/006327; WO 2004/019403; WO 2004/019404
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1. A structure comprising: a substrate having a dielectric layer disposed thereon; and a strained semiconductor layer disposed in contact with the dielectric layer, whereinthe strained semiconductor layer comprises approximately 100% germanium and the dielectric layer consists essentially of silicon dioxide.
2. The structure of claim 1, further comprising: a transistor including: a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metalliccompound.
3. The structure of claim 2, further comprising: a gate dielectric layer disposed between the strained semiconductor layer and the gate.
8. The structure of claim 2, wherein the gate consists essentially of a metal compound, and the metal compound comprises a material selected from the group consisting of titanium nitride, titanium silicon nitride, tungsten nitride, tantalumnitride, tantalum silicide, nickel silicide, and iridium oxide.
9. The structure of claim 2, further comprising: an overlayer disposed above the strained semiconductor layer, wherein the overlayer induces at least a portion of the strain in the strained semiconductor layer.
13. A structure comprising: a substrate having a dielectric layer disposed thereon; and a strained semiconductor layer disposed in contact with the dielectric layer, wherein the strained semiconductor layer is tensilely strained and comprisesapproximately 100% germanium and the dielectric layer comprises silicon dioxide.
Strained silicon-on-insulator structures for semiconductor devices combine the benefits of two advanced approaches to performance enhancement: silicon-on-insulator (SOI) technology and strained silicon (Si) technology. The strainedsilicon-on-insulator configuration offers various advantages associated with the insulating substrate, such as reduced parasitic capacitances and improved isolation. Strained Si provides improved carrier mobilities. Devices such as strained Simetal-oxide-semiconductor field-effect transistors (MOSFETs) combine enhanced carrier mobilities with the advantages of insulating substrates.
Strained-silicon-on-insulator substrates are typically fabricated as follows. First, a relaxed silicon-germanium (SiGe) layer is formed on an insulator by one of several techniques such as separation by implantation of oxygen (SIMOX), waferbonding and etch back; wafer bonding and hydrogen exfoliation layer transfer; or recrystallization of amorphous material. Then, a strained Si layer is epitaxially grown to form a strained-silicon-on-insulator structure, with strained Si disposed overSiGe. The relaxed-SiGe-on-insulator layer serves as the template for inducing strain in the Si layer. This induced strain is typically greater than 10.sup.-3.
This structure has limitations. It is not conducive to the production of fully-depleted strained-semiconductor-on-insulator devices in which the layer over the insulating material must be thin enough [<300 angstroms (.ANG.)] to allow for fulldepletion of the layer during device operation. Fully depleted transistors may be the favored version of SOI for MOSFET technologies beyond the 90 nm technology node. The relaxed SiGe layer adds to the total thickness of this layer and thus makes itdifficult to achieve the thicknesses required for fully depleted silicon-on-insulator device fabrication. The relaxed SiGe layer is not required if a strained Si layer can be produced directly on the insulating material. Thus, there is a need for amethod to produce strained silicon--or other semiconductor--layers directly on insulating substrates.
The present invention includes a strained-semiconductor-on-insulator (SSOI) substrate structure and methods for fabricating the substrate structure. MOSFETs fabricated on this substrate will have the benefits of SOI MOSFETs as well as thebenefits of strained Si mobility enhancement. By eliminating the SiGe relaxed layer traditionally found beneath the strained Si layer, the use of SSOI technology is simplified. For example, issues such as the diffusion of Ge into the strained Si layerduring high temperature processes are avoided.
This approach enables the fabrication of well-controlled, epitaxially-defined, thin strained semiconductor layers directly on an insulator layer. Tensile strain levels of .about.10.sup.-3 or greater are possible in these structures, and are notdiminished after thermal anneal cycles. In some embodiments, the strain-inducing relaxed layer is not present in the final structure, eliminating some of the key problems inherent to current strained Si-on-insulator solutions. This fabrication processis suitable for the production of enhanced-mobility substrates applicable to partially or fully depleted SSOI technology.
In an aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon; and a first strained semiconductor layer disposed in contact with the dielectric layer, the semiconductor layer includingapproximately 100% germanium.
One or more of the following features may be included. The strained semiconductor layer may be compressively strained. The strained semiconductor layer may include a thin layer and the thin layer is disposed in contact with the dielectriclayer. The thin layer may include silicon.
In another aspect, the invention features a substrate having a dielectric layer disposed thereon, a strained semiconductor layer disposed in contact with the dielectric layer, and a transistor. The transistor includes a source region and a drainregion disposed in a portion of the strained semiconductor layer, and a gate disposed above the strained semiconductor layer and between the source and drain regions, the gate including a material selected from the group consisting of a dopedsemiconductor, a metal, and a metallic compound.
One or more of the following features may be included. The doped semiconductor may include polycrystalline silicon and/or polycrystalline silicon-germanium. The metal may include titanium, tungsten, molybdenum, tantalum, nickel, and/or iridium. The metal compound may include titanium nitride, titanium silicon nitride, tungsten nitride, tantalum nitride, tantalum silicide, nickel silicide, and/or iridium oxide. A contact layer may be disposed over at least a portion of the strainedsemiconductor layer, with a bottommost boundary of the contact layer being disposed above a bottommost boundary of the strained semiconductor layer. The contact layer may share an interface with the semiconductor layer.
In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, the dielectric layer having a melting point greater than about 1700.degree. C., and a strained semiconductor layer disposedin contact with the dielectric layer.
In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon; and a strained semiconductor layer disposed in contact with the dielectric layer. The strained semiconductor layer includesapproximately 100% silicon and has a misfit dislocation density of less than about 10.sup.5 cm/cm.sup.2. In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, and a strained semiconductorlayer disposed in contact with the dielectric layer. The strained semiconductor layer includes approximately 100% silicon and has a threading dislocation density selected from the range of about 10 dislocations/cm.sup.2 to about 10.sup.7dislocations/cm.sup.2.
In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon and a strained semiconductor layer disposed in contact with the dielectric layer. The semiconductor layer includesapproximately 100% silicon and has a surface roughness selected from the range of approximately 0.01 nm to approximately 1 nm.
In another aspect, the invention features a substrate having a dielectric layer disposed thereon, and a strained semiconductor layer disposed in contact with the dielectric layer. The strained semiconductor layer includes approximately 100%silicon and has a thickness uniformity across the substrate of better than approximately .+-.10%.
In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, and a strained semiconductor layer disposed in contact with the dielectric layer. The strained semiconductor layer includesapproximately 100% silicon and has a thickness of less than approximately 200 .ANG..
In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, and a strained semiconductor layer disposed in contact with the dielectric layer. The semiconductor layer includesapproximately 100% silicon and has a surface germanium concentration of less than approximately 1.times.10.sup.12 atoms/cm.sup.2.
In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, and a strained semiconductor layer disposed in contact with the dielectric layer. An interface between the strainedsemiconductor layer and the dielectric layer has a density of bonding voids of less than 0.3 voids/cm.sup.2.
In another aspect, the invention features a method for forming a structure, the method including providing a first substrate comprising a porous layer defining a cleave plane and having a first strained semiconductor layer formed thereon. Thefirst strained semiconductor layer is bonded to an insulator layer disposed on a second substrate, and removing the first substrate from the first strained semiconductor layer by cleaving at the cleave plane, the strained semiconductor layer remainingbonded to the insulator layer.
In another aspect, the invention features a method for forming a structure, the method including forming a first relaxed layer over a first substrate, the first relaxed layer including a porous layer defining a cleave plane. A strainedsemiconductor layer is formed over the first relaxed layer. The first strained semiconductor layer is bonded to an insulator layer disposed on a second substrate. The first substrate is removed from the strained semiconductor layer by cleaving at thecleave plane, the strained semiconductor layer remaining bonded to the insulator layer
One or more of the following features may be included. The porous layer may be disposed at a top portion of the first relaxed layer. A second relaxed layer may be formed over the first relaxed layer, with the strained semiconductor layer beingformed over the second relaxed layer. The first relaxed layer may be planarized, e.g., by chemical-mechanical polishing, prior to forming the second relaxed layer. At least a portion of the porous layer may remain disposed on the first strainedsemiconductor layer after cleaving. The portion of the porous layer may be removed from the strained semiconductor layer after cleaving. The portion of the porous layer may be removed by cleaning with a wet chemical solution that may include, e.g.,hydrogen peroxide and/or hydrofluoric acid. Removing the portion of the porous layer may include oxidation.
Referring to FIG. 1A, an epitaxial wafer 8 has a plurality of layers 10 disposed over a substrate 12. Substrate 12 may be formed of a semiconductor, such as Si, Ge, or SiGe. The plurality of layers 10 includes a graded buffer layer 14, whichmay be formed of Si.sub.1-yGe.sub.y, with a maximum Ge content of, e.g., 10-80% (i.e., y=0.1-0.8) and a thickness T.sub.1 of, for example, 1-8 micrometers (.mu.m).
A relaxed layer 16 is disposed over graded buffer layer 14. Relaxed layer 16 may be formed of uniform Si.sub.1-xGe.sub.x having a Ge content of, for example, 10-80% (i.e., x=0.1-0.8), and a thickness T.sub.2 of, for example, 0.2-2 .mu.m. Insome embodiments, Si.sub.1-xGe.sub.x may include Si.sub.0.70Ge.sub.0.30 and T.sub.2 may be approximately 1.5 .mu.m. Relaxed layer 16 may be fully relaxed, as determined by triple axis X-ray diffraction, and may have a threading dislocation density of<1.times.10.sup.6 dislocations/cm.sup.2, as determined by etch pit density (EPD) analysis. Because threading dislocations are linear defects disposed within a volume of crystalline material, threading dislocation density may be measured as either thenumber of dislocations intersecting a unit area within a unit volume or the line length of dislocation per unit volume. Threading dislocation density therefore, may, be expressed in either units of dislocations/cm.sup.2 or cm/cm.sup.3. Relaxed layer 16may have a surface particle density of, e.g., less than about 0.3 particles/cm.sup.2. Further, relaxed layer 16 produced in accordance with the present invention may have a localized light-scattering defect level of less than about 0.3 defects/cm.sup.2for particle defects having a size (diameter) greater than 0.13 microns, a defect level of about 0.2 defects/cm.sup.2 for particle defects having a size greater than 0.16 microns, a defect level of about 0.1 defects/cm.sup.2 for particle defects having asize greater than 0.2 microns, and a defect level of about 0.03 defects/cm.sup.2 for defects having a size greater than 1 micron. Process optimization may enable reduction of the localized light-scattering defect levels to about 0.09 defects/cm.sup.2for particle defects having a size greater than 0.09 microns and to 0.05 defects/cm.sup.2 for particle defects having a size greater than 0.12 microns.
Substrate 12, graded layer 14, and relaxed layer 16 may be formed from various materials systems, including various combinations of group II, group III, group IV, group V, and group VI elements. For example, each of substrate 12, graded layer14, and relaxed layer 16 may include a III-V compound. Substrate 12 may include gallium arsenide (GaAs), graded layer 14 and relaxed layer 16 may include indium gallium arsenide (InGaAs) or aluminum gallium arsenide (AlGaAs). These examples are merelyillustrative, and many other material systems are suitable.
A strained semiconductor layer 18 is disposed over relaxed layer 16. Strained layer 18 may include a semiconductor such as at least one of a group II, a group III, a group IV, a group V, and a group VI element. Strained semiconductor layer 18may include, for example, Si, Ge, SiGe, GaAs, indium phosphide (InP), and/or zinc selenide (ZnSe). In some embodiments, strained semiconductor layer 18 may include approximately 100% Ge, and may be compressively strained. Strained semiconductor layer18 comprising 100% Ge may be formed over, e.g., relaxed layer 16 containing uniform Si.sub.1-xGe.sub.x having a Ge content of, for example, 50-80% (i.e., x=0.5-0.8), preferably 70% (x=0.7). Strained layer 18 has a thickness T.sub.3 of, for example,50-1000 .ANG.. In an embodiment, T.sub.3 may be approximately 200-500 .ANG..
Strained layer 18 may be formed by epitaxy, such as by atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD), by molecular beam epitaxy (MBE), or by atomic layer deposition (ALD). Strainedlayer 18 containing Si may be formed by CVD with precursors such as silane, disilane, or trisilane. Strained layer 18 containing Ge may be formed by CVD with precursors such as germane or digermane. The epitaxial growth system may be a single-wafer ormultiple-wafer batch reactor. The growth system may also utilize a low-energy plasma to enhance layer growth kinetics. Strained layer 18 may be formed at a relatively low temperature, e.g., less than 700.degree. C., to facilitate the definition of anabrupt interface 17 between strained layer 18 and relaxed layer 16. This abrupt interface 17 may enhance the subsequent separation of strained layer 18 from relaxed layer 16, as discussed below with reference to FIGS. 4 and 5. Abrupt interface 17 ischaracterized by the transition of Si or Ge content (in this example) proceeding in at least 1 decade (order of magnitude in atomic concentration) per nanometer of depth into the sample. In an embodiment, this abruptness may be better than 2 decades pernanometer.
In an embodiment in which strained layer 18 contains substantially 100% Si, strained layer 18 may be formed in a dedicated chamber of a deposition tool that is not exposed to Ge source gases, thereby avoiding cross-contamination and improving thequality of the interface between strained layer 18 and relaxed layer 16. Furthermore, strained layer 18 may be formed from an isotopically pure silicon precursor(s). Isotopically pure Si has better thermal conductivity than conventional Si. Higherthermal conductivity may help dissipate heat from devices subsequently formed on strained layer 18, thereby maintaining the enhanced carrier mobilities provided by strained layer 18.
After formation, strained layer 18 has an initial misfit dislocation density, of, for example, 0-10.sup.5 cm/cm.sup.2. In an embodiment, strained layer 18 has an initial misfit dislocation density of approximately 0 cm/cm.sup.2. Because misfitdislocations are linear defects generally lying within a plane between two crystals within an area, they may be measured in terms of total line length per unit area. Misfit dislocation density, therefore, may be expressed in units of dislocations/cm orcm/cm.sup.2. In one embodiment, strained layer 18 is tensilely strained, e.g., Si formed over SiGe. In another embodiment, strained layer 18 is compressively strained, e.g., Ge formed over SiGe.
Strained layer 18 may have a surface particle density of, e.g., less than about 0.3 particles/cm.sup.2. As used herein, "surface particle density" includes not only surface particles but also light-scattering defects, and crystal-originated pits(COPs), and other defects incorporated into strained layer 18. Further, strained layer 18 produced in accordance with the present invention may have a localized light-scattering defect level of less than about 0.3 defects/cm.sup.2 for particle defectshaving a size (diameter) greater than 0.13 microns, a defect level of about 0.2 defects/cm.sup.2 for particle defects having a size greater than 0.16 microns, a defect level of about 0.1 defects/cm.sup.2 for particle defects having a size greater than0.2 microns, and a defect level of about 0.03 defects/cm.sup.2 for defects having a size greater than 1 micron. Process optimization may enable reduction of the localized light-scattering defect levels to about 0.09 defects/cm.sup.2 for particle defectshaving a size greater than 0.09 microns and to 0.05 defects/cm.sup.2 for particle defects having a size greater than 0.12 microns. These surface particles may be incorporated in strained layer 18 during the formation of strained layer 18, or they mayresult from the propagation of surface defects from an underlying layer, such as relaxed layer 16.
In alternative embodiments, graded layer 14 may be absent from the structure. Relaxed layer 16 may be formed in various ways, and the invention is not limited to embodiments having graded layer 14. In other embodiments, strained layer 18 may beformed directly on substrate 12. In this case, the strain in layer 18 may be induced by lattice mismatch between layer 18 and substrate 12, induced mechanically, e.g., by the deposition of overlayers, such as Si.sub.3N.sub.4, or induced by thermalmismatch between layer 18 and a subsequently grown layer, such as a SiGe layer. In some embodiments, a uniform semiconductor layer (not shown), having a thickness of approximately 0.5 .mu.m and comprising the same semiconductor material as substrate 12,is disposed between graded buffer layer 14 and substrate 12. This uniform semiconductor layer may be grown to improve the material quality of layers subsequently grown on substrate 12, such as graded buffer layer 14, by providing a clean,contaminant-free surface for epitaxial growth. In certain embodiments, relaxed layer 16 may be planarized prior to growth of strained layer 18 to eliminate the crosshatched surface roughness induced by graded buffer layer 14. (See, e.g., M. T. Currie,et al., Appl. Phys. Lett., 72 (14) p. 1718 (1998), incorporated herein by reference.) The planarization may be performed by a method such as chemical mechanical polishing (CMP), and may improve the quality of a subsequent bonding process (see below)because it minimizes the wafer surface roughness and increases wafer flatness, thus providing a greater surface area for bonding.
Referring to FIG. 1B, after planarization of relaxed layer 16, a relaxed semiconductor regrowth layer 19 including a semiconductor such as SiGe may be grown on relaxed layer 16, thus improving the quality of subsequent strained layer 18 growth byensuring a clean surface for the growth of strained layer 18. Growing on this clean surface may be preferable to growing strained material, e.g., silicon, on a surface that is possibly contaminated by oxygen and carbon from the planarization process. The conditions for epitaxy of the relaxed semiconductor regrowth layer 19 on the planarized relaxed layer 16 should be chosen such that surface roughness of the resulting structure, including layers formed over regrowth layer 19, is minimized to ensure asurface suitable for subsequent high quality bonding. High quality bonding may be defined as the existence of a bond between two wafers that is substantially free of bubbles or voids at the interface. Measures that may help ensure a smooth surface forstrained layer 18 growth, thereby facilitating bonding, include substantially matching a lattice of the semiconductor regrowth layer 19 to that of the underlying relaxed layer 16, by keeping the regrowth thickness below approximately 1 .mu.m, and/or bykeeping the growth temperature below approximately 850.degree. C. for at least a portion of the semiconductor layer 19 growth. It may also be advantageous for relaxed layer 16 to be substantially free of particles or areas with high threadingdislocation densities (i.e., threading dislocation pile-ups) which could induce non-planarity in the regrowth and decrease the quality of the subsequent bond.
Referring to FIG. 2A, in an embodiment, hydrogen ions are implanted into relaxed layer 16 to define a cleave plane 20. This implantation is similar to the SMARTCUT process that has been demonstrated in silicon by, e.g., SOITEC, based inGrenoble, France. Implantation parameters may include implantation of hydrogen (H.sub.2.sup.+) to a dose of 2.5-5.times.10.sup.16 ions/cm.sup.2 at an energy of, e.g., 50-100 keV. For example, H.sub.2.sup.+ may be implanted at an energy of 75 keV and adose of 4.times.10.sup.16 ions/cm.sup.2 through strained layer 18 into relaxed layer 16. In alternative embodiments, it may be favorable to implant at energies less than 50 keV to decrease the depth of cleave plane 20 and decrease the amount of materialsubsequently removed during the cleaving process (see discussion below with reference to FIG. 4). In an alternative embodiment, other implanted species may be used, such as H.sup.+ or He.sup.+, with the dose and energy being adjusted accordingly. Theimplantation may also be performed prior to the formation of strained layer 18. Then, the subsequent growth of strained layer 18 is preferably performed at a temperature low enough to prevent premature cleaving along cleave plane 20, i.e., prior to thewafer bonding process. This cleaving temperature is a complex function of the implanted species, implanted dose, and implanted material. Typically, premature cleaving may be avoided by maintaining a growth temperature below approximately 500.degree. C.
In some embodiments, such as when strained layer 18 comprises nearly 100% Ge, a thin layer 21 of another material, such as Si, may be formed over strained layer 18 prior to bonding (see discussion with respect to FIG. 3). This thin layer 21 maybe formed to enhance subsequent bonding of strained layer 18 to an insulator, such as an oxide. Thin layer 21 may have a thickness T.sub.21 of, for example, 0.5-5 nm.
In some embodiments, strained layer 18 may be planarized by, e.g., CMP, to improve the quality of the subsequent bond. Strained layer 18 may have a low surface roughness, e.g., less than 0.5 nm root mean square (RMS). Referring to FIG. 2B, insome embodiments, a dielectric layer 22 may be formed over strained layer 18 prior to ion implantation into relaxed layer 16 to improve the quality of the subsequent bond. Dielectric layer 22 may be, e.g., silicon dioxide (SiO.sub.2) deposited by, forexample, LPCVD or by high density plasma (HDP). An LPCVD deposited SiO.sub.2 layer may be subjected to a densification step at elevated temperature. Suitable conditions for this densification step may be, for example, a 10 minute anneal at 800.degree. C. in a nitrogen ambient. Alternatively, dielectric layer 22 may include low-temperature oxide (LTO), which may be subsequently densified at elevated temperature in nitrogen or oxygen ambients. Suitable conditions for this densification step can be a10 minute anneal at 800.degree. C. in an oxygen ambient. Dielectric layer 22 may be planarized by, e.g., CMP to improve the quality of the subsequent bond. In an alternative embodiment, it may be advantageous for dielectric layer 22 to be formed fromthermally grown SiO.sub.2 in order to provide a high quality semiconductor/dielectric interface in the final structure. In an embodiment, strained layer 18 comprises approximately 100% Ge and dielectric layer 22 comprises, for example, germanium dioxide(GeO.sub.2); germanium oxynitride (GeON); a high-k insulator having a higher dielectric constant than that of SiO.sub.2 such as hafnium oxide (HfO.sub.2) or hafnium silicate (HfSiON, HfSiO.sub.4); or a multilayer structure including GeO.sub.2 andSiO.sub.2. Ge has an oxidation behavior different from that of Si, and the deposition methods may be altered accordingly.
Referring to FIG. 3, epitaxial wafer 8 is bonded to a handle wafer 50. Either handle wafer 50, epitaxial wafer 8, or both have a top dielectric layer (see, e.g., dielectric layer 22 in FIG. 2B) to facilitate the bonding process and to serve asan insulator layer in the final substrate structure. Handle wafer 50 may have a dielectric layer 52 disposed over a semiconductor substrate 54. Dielectric layer 52 may include, for example, SiO.sub.2. In an embodiment, dielectric layer 52 includes amaterial having a melting point (T.sub.m) higher than a T.sub.m of pure SiO.sub.2, i.e., higher than 1700.degree. C. Examples of such materials are silicon nitride (Si.sub.3N.sub.4), aluminum oxide, magnesium oxide, etc. Using dielectric layer 52 with ahigh T.sub.m helps prevents possible relaxation of the transferred strained semiconductor layer 18 that may occur during subsequent processing, due to softening of the underlying dielectric layer 52 at temperatures typically used during devicefabrication (approximately 1000-1200.degree. C.). In other embodiments, handle wafer 50 may include a combination of a bulk semiconductor material and a dielectric layer, such as a silicon on insulator substrate. Semiconductor substrate 54 includes asemiconductor material such as, for example, Si, Ge, or SiGe.
Handle wafer 50 and epitaxial wafer 8 are cleaned by a wet chemical cleaning procedure to facilitate bonding, such as by a hydrophilic surface preparation process to assist the bonding of a semiconductor material, e.g., strained layer 18, to adielectric material, e.g., dielectric layer 52. For example, a suitable prebonding surface preparation cleaning procedure could include a modified megasonic RCA SC1 clean containing ammonium hydroxide, hydrogen peroxide, and water(NH.sub.4OH:H.sub.2O.sub.2:H.sub.2O) at a ratio of 1:4:20 at 60.degree. C. for 10 minutes, followed by a deionized (DI) water rinse and spin dry. The wafer bonding energy should be strong enough to sustain the subsequent layer transfer (see FIG. 4). In some embodiments, top surfaces 60, 62 of handle wafer 50 and epitaxial wafer 8, including a top surface 63 of strained semiconductor layer 18, may be subjected to a plasma activation, either before, after, or instead of a wet clean, to increase thebond strength. The plasma environment may include at least one of the following species: oxygen, ammonia, argon, nitrogen, diborane, and phosphine. After an appropriate cleaning step, handle wafer 50 and epitaxial wafer 8 are bonded together bybringing top surfaces 60, 62 in contact with each other at room temperature. The bond strength may be greater than 1000 mJ/m.sup.2, achieved at a low temperature, such as less than 600.degree. C.
Referring to FIG. 4 as well as to FIG. 3, a split is induced at cleave plane 20 by annealing handle wafer 50 and epitaxial wafer 8 after they are bonded together. This split may be induced by an anneal at 300-700.degree. C., e.g., 550.degree. C., inducing hydrogen exfoliation layer transfer (i.e., along cleave plane 20) and resulting in the formation of two separate wafers 70, 72. One of these wafers (70) has a first portion 80 of relaxed layer 16 (see FIG. 1A) disposed over strained layer18. Strained layer 18 is in contact with dielectric layer 52 on semiconductor substrate 54. The other of these wafers (72) includes substrate 12, graded layer 14, and a remaining portion 82 of relaxed layer 16. In some embodiments, wafer splitting maybe induced by mechanical force in addition to or instead of annealing. If necessary, wafer 70 with strained layer 18 may be annealed further at 600-900.degree. C., e.g., at a temperature greater than 800.degree. C., to strengthen the bond between thestrained layer 18 and dielectric layer 52. In some embodiments, this anneal is limited to an upper temperature of about 900.degree. C. to avoid the destruction of a strained Si/relaxed SiGe heterojunction by diffusion. Wafer 72 may be planarized, andused as starting substrate 8 for growth of another strained layer 18. In this manner, wafer 72 may be "recycled" and the process illustrated in FIGS. 1A-5 may be repeated. An alternative "recyling" method may include providing relaxed layer 16 that isseveral microns thick and repeating the process illustrated in FIGS. 1A-5, starting with the formation of strained layer 18. Because the formation of this thick relaxed layer 16 may lead to bowing of substrate 12, a layer including, e.g., oxide ornitride, may be formed on the backside of substrate 12 to counteract the bowing. Alternatively substrate 12 may be pre-bowed when cut and polished, in anticipation of the bow being removed by the formation of thick relaxed layer 16.
Referring to FIG. 4 as well as to FIG. 5, relaxed layer portion 80 is removed from strained layer 18. In an embodiment, removal of relaxed layer portion 80, containing, e.g., SiGe, includes oxidizing the relaxed layer portion 80 by wet (steam)oxidation. For example, at temperatures below approximately 800.degree. C., such as temperatures between 600-750.degree. C., wet oxidation will oxidize SiGe much more rapidly then Si, such that the oxidation front will effectively stop when it reachesthe strained layer 18, in embodiments in which strained layer 18 includes Si. The difference between wet oxidation rates of SiGe and Si may be even greater at lower temperatures, such as approximately 400.degree. C.-600.degree. C. Good oxidationselectivity is provided by this difference in oxidation rates, i.e., SiGe may be efficiently removed at low temperatures with oxidation stopping when strained layer 18 is reached. This wet oxidation results in the transformation of SiGe to a thermalinsulator 90, e.g., Si.sub.xGe.sub.yO.sub.z. The thermal insulator 90 resulting from this oxidation is removed in a selective wet or dry etch, e.g., wet hydrofluoric acid. In some embodiments, it may be more economical to oxidize and strip severaltimes, instead of just once.
In certain embodiments, wet oxidation may not completely remove the relaxed layer portion 80. Here, a localized rejection of Ge may occur during oxidation, resulting in the presence of a residual Ge-rich SiGe region at the oxidation front, onthe order of, for example, several nanometers in lateral extent. A surface clean may be performed to remove this residual Ge. For example, the residual Ge may be removed by a dry oxidation at, e.g., 600.degree. C., after the wet oxidation and stripdescribed above. Another wet clean may be performed in conjunction with--or instead of--the dry oxidation. Examples of possible wet etches for removing residual Ge include a Piranha etch, i.e., a wet etch that is a mixture of sulfuric acid and hydrogenperoxide (H.sub.2SO.sub.4:H.sub.2O.sub.2) at a ratio of, for example, 3:1. An HF dip may be performed after the Piranha etch. Alternatively, an RCA SC1 clean may be used to remove the residual Ge. The process of Piranha or RCA SC1 etching and HFremoval of resulting oxide may be repeated more than once. In an embodiment, relaxed layer portion including, e.g., SiGe, is removed by etching and annealing under a hydrochloric acid (HCl) ambient.
In the case of a strained Si layer, the surface Ge concentration of the final strained Si surface is preferably less than about 1.times.10.sup.12 atoms/cm.sup.2 when measured by a technique such as total reflection x-ray fluorescence (TXRF) orthe combination of vapor phase decomposition (VPD) with a spectroscopy technique such as graphite furnace atomic absorption spectroscopy (GFAAS) or inductively-coupled plasma mass spectroscopy (ICP-MS). In some embodiments, after cleaving, aplanarization step or a wet oxidation step may be performed to remove a portion of the damaged relaxed layer portion 80 as well as to increase the smoothness of its surface. A smoother surface may improve the uniformity of subsequent complete removal ofa remainder of relaxed layer portion 80 by, e.g., wet chemical etching. After removal of relaxed layer portion 80, strained layer 18 may be planarized. Planarization of strained layer 18 may be performed by, e.g., CMP; an anneal at a temperaturegreater than, for example, 800.degree. C., in a hydrogen (H.sub.2) or hydrochloric acid (HCl) containing ambient; or cluster ion beam smoothing.
Referring to FIG. 6, a SSOI substrate 100 has strained layer 18 disposed over an insulator, such as dielectric layer 52 formed on semiconductor substrate 54. Strained layer 18 has a thickness T.sub.4 selected from a range of, for example,50-1000 .ANG., with a thickness uniformity of better than approximately .+-.5% and a surface roughness of less than approximately 20 .ANG.. Dielectric layer 52 has a thickness T.sub.52 selected from a range of, for example, 500-3000 .ANG.. In anembodiment, strained layer 18 includes approximately 100% Si or 100% Ge having one or more of the following material characteristics: misfit dislocation density of, e.g., 0-10.sup.5 cm/cm.sup.2; a threading dislocation density of about 10.sup.1-10.sup.7dislocations/cm.sup.2; a surface roughness of approximately 0.01-1 nm RMS; and a thickness uniformity across SSOI substrate 100 of better than approximately .+-.10% of a mean desired thickness; and a thickness T.sub.4 of less than approximately 200.ANG.. In an embodiment, SSOI substrate 100 has a thickness uniformity of better than approximately .+-.5% of a mean desired thickness.
In an embodiment, dielectric layer 52 has a T.sub.m greater than that of SiO.sub.2. During subsequent processing, e.g., MOSFET formation, SSOI substrate 100 may be subjected to high temperatures, i.e., up to 1100.degree. C. High temperaturesmay result in the relaxation of strained layer 18 at an interface between strained layer 18 and dielectric layer 52. The use of dielectric layer with a T.sub.m greater than 1700.degree. C. may help keep strained layer 18 from relaxing at the interfacebetween strained layer 18 and dielectric layer 52 when SSOI substrate is subjected to high temperatures.
In an embodiment, the misfit dislocation density of strained layer 18 may be lower than its initial dislocation density. The initial dislocation density may be lowered by, for example, performing an etch of a top surface 92 of strained layer 18. This etch may be a wet etch, such as a standard microelectronics clean step such as an RCA SC1, i.e., hydrogen peroxide, ammonium hydroxide, and water (H.sub.2O.sub.2+NH.sub.4OH+H.sub.2O), which at, e.g., 80.degree. C. may remove silicon.
The presence of surface particles on strained layer 18, as described above with reference to FIG. 1A, may result in the formation of bonding voids at an interface 102 between strained layer 18 and dielectric layer 52. These bonding voids mayhave a density equivalent to the density of surface particles formed on strained layer 18, e.g., less than about 0.3 voids/cm.sup.2.
In some embodiments, strained semiconductor layer 18 includes Si and is substantially free of Ge; further, any other layer disposed in contact with strained semiconductor layer 18 prior to device processing, e.g., dielectric layer 52, is alsosubstantially free of Ge.
Referring to FIG. 7, in an alternative embodiment, relaxed layer portion 80 may be removed by a selective wet etch that stops at the strained layer 18 to obtain SSOI substrate 100 (see FIG. 6). In embodiments in which relaxed layer portion 80contains SiGe, a suitable selective SiGe wet etch may be a solution containing nitric acid (HNO.sub.3) and dilute HF at a ratio of 3:1 or a solution containing H.sub.2O.sub.2, HF, and acetic acid (CH.sub.3COOH) at a ratio of 2:1:3. Alternatively,relaxed layer portion 80 may be removed by a dry etch that stops at strained layer 18. In some embodiments, relaxed layer portion 80 may be removed completely or in part by a chemical-mechanical polishing step or by mechanical grinding.
Strained semiconductor-on-insulator substrate 100 may be further processed by CMOS SOI MOSFET fabrication methods. For example, referring to FIG. 8A, a transistor 200 may be formed on SSOI substrate 100. Forming transistor 200 includes forminga gate dielectric layer 210 above strained layer 18 by, for example, growing an SiO.sub.2 layer by thermal oxidation. Alternatively, gate dielectric layer 210 may include a high-k material with a dielectric constant higher than that of SiO.sub.2, suchas HfO.sub.2, HfSiON, or HfSiO.sub.4. In some embodiments, gate dielectric layer 210 may be a stacked structure, e.g., a thin SiO.sub.2 layer capped with a high-k material. A gate 212 is formed over gate dielectric layer 210. Gate 212 may be formed ofa conductive material, such as doped semiconductor, e.g., polycrystalline Si or polycrystalline SiGe; a metal, e.g., titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), nickel (Ni), or iridium (Ir); or metal compounds, e.g., titanium nitride(TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), tantalum nitride (TaN), tantalum silicide (TaSi), nickel silicide (NiSi), or iridium oxide (IrO.sub.2), that provide an appropriate workfunction. A source region 214 and a drain region 216are formed in a portion 218 of strained semiconductor layer 18, proximate gate dielectric layer 210. Source and drain regions 214, 216 may be formed by, e.g., ion implantation of either n-type or p-type dopants.
In some embodiments, strained semiconductor layer 18 may be compressively strained when, for example, layer 18 includes strained Ge. Compressively strained layers may be prone to undulation when subjected to large temperature changes. The riskof such undulation may be reduced by reducing the thermal budget of a process for fabricating devices, such as transistor 200. The thermal budget may reduced by, for example, using atomic layer deposition (ALD) to deposit gate dielectric layer 210. Furthermore, a maximum temperature for forming gate 212 may be limited to, e.g., 600.degree. C. by, for example, the use of materials comprising metal or metal compounds, rather than polysilicon or other gate materials that may require higher formationand/or dopant activation temperatures.
Referring to FIG. 8B, a transistor 250 formed on SSOI substrate 100 may have an elevated source region and an elevated drain region proximate a first and a second sidewall spacer 252, 254. These elevated regions may be formed as follows. Asemiconductor layer 256a-256c is formed selectively on exposed silicon surfaces, i.e., on top surface 258 of a gate 259 containing silicon, a top surface 260 of a source 262 defined in strained layer 18, and top surface 264 of a drain 266 defined instrained layer 18. In an embodiment, semiconductor layer 256a-256c is an epitaxial layer, such as epitaxial silicon, epitaxial germanium, or epitaxial silicon-germanium. No semiconductor layer is formed on non-silicon features, such as sidewall spacers252, 254 and dielectric isolation regions 268, 270. Semiconductor layer 256a-256c has a thickness T.sub.256 of, for example, approximately 100-500 .ANG..
Semiconductor layer 256a-256c has a low resistivity of, e.g., 0.001 ohm-cm, that facilitates the formation of low-resistance contacts. To achieve this low resistivity, semiconductor layer 256a-256c is, for example, epitaxial silicon doped with,for example, arsenic to a concentration of 1.times.10.sup.20 atoms/cm.sup.3. Semiconductor layer 256a-256c may be doped in situ, during deposition. In alternative embodiments, semiconductor layer 256a-256c may be doped after deposition by ionimplantation or by gas-, plasma- or solid-source diffusion. In some embodiments, the doping of semiconductor layer 256a-256c and the formation of source 262 and drain 266 are performed simultaneously. Portions of semiconductor layer 256a, 256c disposedover source 262 and drain 266 may have top surfaces substantially free of facets. In an embodiment, portions of source 262, drain 266, and/or gate 259 may be etched away to define recess prior to deposition of semiconductor layer 256a-256c, andsemiconductor layer 256a-256c may then be deposited in the recesses thus formed.
Referring to FIG. 8C, a metal layer 272 is formed over transistor 250. Metal layer 272 is formed by, for example, sputter deposition. Metal layer 272 has a thickness T.sub.272 of, e.g., 50-200 .ANG. and includes a metal such as cobalt,titanium, tungsten, nickel, or platinum. The metal is selected to react with semiconductor layer 256a-256c to form a low-resistance metal-semiconductor alloy when exposed to heat, as described below. The metal is also selected such that themetal-semiconductor alloy remains stable at temperatures typically required to complete transistor 250 fabrication, e.g., 400-700.degree. C.
Referring also to FIG. 8D, subsequent to deposition of metal layer 272, a first rapid thermal anneal is performed, e.g., at 550.degree. C. for 60 seconds. This heating step initiates a reaction between metal layer 272 and semiconductor layers256a-256c, forming a high resistivity phase of a metal-semiconductor alloy, e.g., cobalt silicide. (CoSi). Portions of metal layer 272 are removed by a wet etch, such as sulfuric acid and hydrogen peroxide. In an alternative embodiment, the wet etchmay be ammonium hydroxide, peroxide, and water. This wet etch removes portions of metal layer 272 disposed over dielectric material, such as over first and second sidewall spacers 252, 254 and isolation regions 268, 270. Portions 274 of metal layer 272disposed over semiconductor layer 256a-256c that have reacted to form the metal-semiconductor alloy remain in place after the anneal and wet etch.
Referring to FIG. 8E, SSOI substrate 100, including transistor 250, is subjected to a second heat treatment. For example, in an embodiment in which metal layer 272 includes cobalt, SSOI substrate 100 undergoes a rapid thermal anneal at800.degree. C. for 60 seconds in a nitrogen ambient. This heating step initiates a reaction in the metal-semiconductor alloy layer which substantially lowers its resistivity, to form a substantially homogeneous contact layer 276a-276c. Contact layer276a-276c includes a metal-semiconductor alloy, e.g., a metal silicide such as a low resistivity phase of cobalt silicide (CoSi.sub.2). Contact layer 276a-276c has a thickness T.sub.276 of, for example, 400 .ANG.. Contact layer 276a-276c has a lowsheet resistance, e.g., less than about 10 .OMEGA./.quadrature., and enables a good quality contact to be made to source 262 and drain 266, as well as to gate 259.
In some embodiments, during formation, contact layer 276a-276c may consume substantially all of semiconductor layer 256a-256c. A bottommost boundary 278a of contact layer 276a, therefore, shares an interface 280a with strained layer 18 in source262, and a bottommost boundary 278c of contact layer 276c, therefore, shares an interface 280c with strained layer 18 in drain 266. A bottommost boundary 278b of contact layer 276b shares an interface 280b with gate 259.
In other embodiments, contact layer portions 276a, 276c, disposed over source 262 and drain 266, may extend into strained layer 18. Interfaces 280a, 280c between contact layer 276a, 276c and strained layer 18 are then disposed within source 262and drain 266, respectively, above bottommost boundaries 282a, 282c of strained layer 18. Interfaces 280a, 280c have a low contact resistivity, e.g., less than approximately 5.times.10.sup.-7 .OMEGA.-cm.sup.2. In certain other embodiments, duringformation, contact layer 276a-276c may not consume all of semiconductor layer 256a-256c (see FIG. 8D). A bottommost boundary 278a of contact layer 276a, therefore, shares an interface with semiconductor layer 256a over source 262, and a bottommostboundary 278c of contact layer 276c, therefore, shares an interface with semiconductor layer 256c over drain 266.
Because strained layer 18 includes a strained material, carrier mobilities in strained layer 18 are enhanced, facilitating lower sheet resistances. This strain also results in a reduced energy bandgap, thereby lowering the contact resistivitybetween the metal-semiconductor alloy and the strained layer.
In alternative embodiments, an SSOI structure may include, instead of a single strained layer, a plurality of semiconductor layers disposed on an insulator layer. For example, referring to FIG. 9, epitaxial wafer 300 includes strained layer 18,relaxed layer 16, graded layer 14, and substrate 12. In addition, a semiconductor layer 310 is disposed over strained layer 18. Strained layer 18 may be tensilely strained and semiconductor layer 310 may be compressively strained. In an alternativeembodiment, strained layer 18 may be compressively strained and semiconductor layer 310 may be tensilely strained. Strain may be induced by lattice mismatch with respect to an adjacent layer, as described above, or mechanically. For example, strain maybe induced by the deposition of overlayers, such as Si.sub.3N.sub.4. In another embodiment, semiconductor layer 310 is relaxed. Semiconductor layer 310 includes a semiconductor material, such as at least one of a group II, a group III, a group IV, agroup V, and a group VI element. Epitaxial wafer 300 is processed in a manner analogous to the processing of epitaxial wafer 8, as described with reference to FIGS. 1-7.
Referring also to FIG. 10, processing of epitaxial wafer 300 results in the formation of SSOI substrate 350, having strained layer 18 disposed over semiconductor layer 310. Semiconductor layer 310 is bonded to dielectric layer 52, disposed oversubstrate 54. As noted above with reference to FIG. 9, strained layer 18 may be tensilely strained and semiconductor layer 310 may be compressively strained. Alternatively, strained layer 18 may be compressively strained and semiconductor layer 310 maybe tensilely strained. In some embodiments, semiconductor layer 310 may be relaxed.
Referring to FIG. 11, in some embodiments, a thin strained layer 84 may be grown between strained layer 18 and relaxed layer 16 to act as an etch stop during etching, such as wet etching. In an embodiment in which strained layer 18 includes Siand relaxed layer 16 includes Si.sub.1-yGe.sub.y, thin strained layer 84 may include Si.sub.1-xGe.sub.x, with a higher Ge content (x) than the Ge content (y) of relaxed layer 16, and hence be compressively strained. For example, if the composition ofthe relaxed layer 16 is 20% Ge (Si.sub.0.80Ge.sub.0.20), thin strained layer 84 may contain 40% Ge (Si.sub.0.60Ge.sub.0.40) to provide a more robust etch stop. In other embodiments, a second strained layer, such as thin strained layer 84 with higher Gecontent than relaxed layer 16, may act as a preferential cleave plane in the hydrogen exfoliation/cleaving procedure described above.
In an alternative embodiment, thin strained layer 84 may contain Si.sub.1-xGe.sub.x with lower Ge content than relaxed layer 16. In this embodiment, thin strained layer 84 may act as a diffusion barrier during the wet oxidation process. Forexample, if the composition of relaxed layer 16 is 20% Ge (Si.sub.0.80Ge.sub.0.20), thin strained layer 84 may contain 10% Ge (Si.sub.0.90Ge.sub.0.10) to provide a barrier to Ge diffusion from the higher Ge content relaxed layer 16 during the oxidationprocess. In another embodiment, thin strained layer 84 may be replaced with a thin graded Si.sub.1-zGe.sub.z layer in which the Ge composition (z) of the graded layer is decreased from relaxed layer 16 to the strained layer 18.
Referring again to FIG. 7, in some embodiments, a small amount, e.g., approximately 20-100 .ANG., of strained layer 18 may be removed at an interface 105 between strained layer 18 and relaxed layer portion 80. This may be achieved by overetchingafter relaxed layer portion 80 is removed. Alternatively, this removal of strained layer 18 may be performed by a standard microelectronics clean step such as an RCA SC1, i.e., hydrogen peroxide, ammonium hydroxide, and water (H.sub.2O.sub.2+NH.sub.4OH+H.sub.2O), which at, e.g., 80.degree. C. may remove silicon. This silicon removal may remove any misfit dislocations that formed at the original strained layer 18/relaxed layer 80 interface 105 if strained layer 18 was grown above thecritical thickness. The critical thickness may be defined as the thickness of strained layer 18 beyond which it becomes energetically favorable for the strain in the layer to partially relax via the introduction of misfit dislocations at interface 105between strained layer 18 and relaxed layer 16. Thus, the method illustrated in FIGS. 1-7 provides a technique for obtaining strained layers above a critical thickness without misfit dislocations that may compromise the performance of deeply scaledMOSFET devices.
Referring to FIG. 12, in some embodiments, handle wafer 50 may have a structure other than a dielectric layer 52 disposed over a semiconductor substrate 54. For example, a bulk relaxed substrate 400 may comprise a bulk material 410 such as asemiconductor material, e.g., bulk silicon. Alternatively, bulk material 410 may be a bulk dielectric material, such as Al.sub.2O.sub.3 (e.g., alumina or sapphire) or SiO.sub.2 (e.g., quartz). Epitaxial wafer 8 may then be bonded to handle wafer 400(as described above with reference to FIGS. 1-6), with strained layer 18 being bonded to the bulk material 410 comprising handle wafer 400. In embodiments in which bulk material 410 is a semiconductor, to facilitate this semiconductor-semiconductorbond, a hydrophobic clean may be performed, such as an HF dip after an RCA SC1 clean.
Referring to FIG. 13, after bonding and further processing (as described above), a strained-semiconductor-on-semiconductor (SSOS) substrate 420 is formed, having strained layer 18 disposed in contact with relaxed substrate 400. The strain ofstrained layer 18 is not induced by underlying relaxed substrate 400, and is independent of any lattice mismatch between strained layer 18 and relaxed substrate 400. In an embodiment, strained layer 18 and relaxed substrate 400 include the samesemiconductor material, e.g., silicon. Relaxed substrate 400 may have a lattice constant equal to a lattice constant of strained layer 18 in the absence of strain. Strained layer 18 may have a strain greater than approximately 1.times.10.sup.-3. Strained layer 18 may have been formed by epitaxy, and may have a thickness T.sub.5 of between approximately 20 .ANG.-1000 .ANG., with a thickness uniformity of better than approximately .+-.10%. In an embodiment, strained layer 18 may have a thicknessuniformity of better than approximately .+-.5%. Surface 92 of strained layer 18 may have a surface roughness of less than 20 .ANG..
Referring to FIG. 14, in an embodiment, after fabrication of the SSOI structure 100 including semiconductor substrate 54 and dielectric layer 52, it may be favorable to selectively relax the strain in at least a portion of strained layer 18. This could be accomplished by introducing a plurality of ions by, e.g., ion implantation after a photolithography step in which at least a portion of the structure is masked by, for example, a photoresist feature 500. Ion implantation parameters may be,for example, an implant of Si ions at a dose of 1.times.10.sup.15-1.times.10.sup.17 ions/cm.sup.2, at an energy of 5-75 keV. After ion implantation, a relaxed portion 502 of strained layer 18 is relaxed, while a strained portion 504 of strained layer 18remains strained.
Referring to FIGS. 15A-15E, SSOI structure 100 (see FIG. 6) may be formed by the use of a porous semiconductor substrate. Referring to FIG. 15A, substrate 12 may be formed of a semiconductor, such as Si, Ge, or SiGe. A plurality of pores 1514,i.e., microvoids, are formed to define a porous layer 1516 in a portion of substrate 12. Pores 1514 may have a median diameter of 5-10 nm and a pitch of 10-50 nm. Porous layer 1516 may have a porosity of 10-50% and may extend a depth of d.sub.15 intosubstrate 12 of approximately 1-5 .mu.m.
Referring to FIG. 15B, pores 1514 may be formed by, for example, submerging substrate 12 into a vessel 1517 containing an electrolyte 1518, such as hydrofluoric acid (HF), possibly mixed with ethanol, with a cathode 1520 and an anode 1522disposed in the electrolyte 1518. A back surface chucking holder 1519a with a vacuum pad 1519b may hold substrate 12 while it is submerged in vessel 1517. A current may be generated between cathode 1520 and anode 1522, through substrate 12, resultingin the electrochemical etching of substrate 12, thereby forming pores 1514 at a top surface 1524 of substrate 12. In an embodiment, prior to the formation of pores 1514, substrate 12 may be planarized, e.g., by CMP.
Referring to FIG. 15C, after the formation of pores 1514, a plurality of layers 10 may be formed over porous top surface 1524 of substrate 12, as described with reference to FIG. 1A. Layers 10 may include, for example, graded buffer layer 14,relaxed layer 16, and strained layer 18. Pores 1514 define cleave plane 20 in porous layer 1516 of substrate 12.
Referring to FIG. 15D, substrate 12 with layers 10 is bonded to handle wafer 50, including semiconductor substrate 54 and dielectric layer 52, as described with reference to FIG. 3. Prior to bonding, a dielectric layer may be formed on a topsurface of layers 10 to facilitate the bonding process and to serve as an insulator layer in the final substrate structure.
Referring to FIG. 15E as well as to FIG. 15D, a split is induced at cleave plane 20 by, for example, cleaving porous layer 1516 by a water or an airjet. The split results in the formation of two separate wafers 1570, 1572. One of these wafers(1572) has graded layer 14 and relaxed layer 16 (see FIG. 15C) disposed over strained layer 18, with a first portion 1580 of substrate 12 disposed over graded layer 14. First portion 1580 of substrate 12 may be just trace amounts of material surroundingpores 1514. Strained layer 18 is in contact with dielectric layer 52 on semiconductor substrate 54. The other of these wafers (1570) includes a second portion 1582 of substrate 12, including the bulk of substrate 12 with perhaps trace amounts ofmaterial surrounding pores 1514.
Referring to FIG. 6 as well as to FIG. 15E, first portion 1580 of substrate 12 is removed from graded layer 14 by a wet chemical cleaning process utilizing, for example a mixture of hydrogen peroxide (H.sub.2O.sub.2) and HF. Graded layer 14 andrelaxed layer 16 are removed in any one of the methods described for the removal of relaxed layer portion 80 with reference to FIGS. 4 and 5. Removal of graded and relaxed layers 14, 16 results in the formation of SSOI substrate 100.
Referring to FIG. 16A, SSOI substrate 100 (see FIG. 6) may also be formed by the use of porous intermediate layers. For example, plurality of layers 10 may be formed over substrate 12, layers 10 including graded layer 14, relaxed layer 16, andstrained layer 18 (see FIG. 1A). Prior to the formation of strained layer 18, a plurality of pores 1614 may be formed in a top portion of relaxed layer 16, thereby defining a porous layer 1616 in a top portion 1617 of relaxed layer 16. Pores 1614 maybe formed by the methods described above with reference to the formation of pores 1514 in FIG. 15B. Porous layer 1616 may have a thickness T.sub.16 of, e.g., 1-5 .mu.m. Strained layer 18 may then be formed directly over porous layer 1616. Pores 1614define cleave plane 20 in porous layer 1616.
Referring to FIG. 16B, in an alternative embodiment, after the formation of porous layer 1616 in a portion of relaxed layer 16, a second relaxed layer 1620 may be formed over relaxed layer 16 including porous layer 1616. Second relaxed layer1620 may include the same material from which relaxed layer 16 is formed, e.g., uniform Si.sub.1-xGe.sub.x having a Ge content of, for example, 10-80% (i.e., x=0.1-0.8) and having a thickness T.sub.17 of, e.g., 5-100 nm. In some embodiments,Si.sub.1-xGe.sub.x may include Si.sub.0.70Ge.sub.0.30 and T.sub.17 may be approximately 50 nm. Second relaxed layer 1620 may be fully relaxed, as determined by triple axis X-ray diffraction, and may have a threading dislocation density of<1.times.10.sup.6/cm.sup.2, as determined by etch pit density (EPD) analysis. Strained layer 18 may be formed over second relaxed layer 1620. Pores 1614 define cleave plane 20 in porous layer 1616.
Referring to FIG. 16D as well as to FIG. 16C, a split is induced at cleave plane 20 by, for example, cleaving porous layer 1616 by a water or an air jet. The split results in the formation of two separate wafers 1670, 1672. One of these wafers(1670) has top portion 1617 of relaxed layer 16 (see FIG. 16A) disposed over strained layer 18. Strained layer 18 is in contact with dielectric layer 52 on semiconductor substrate 54. The other of these wafers (1672) includes the substrate 12, gradedlayer 14, and a bottom portion 1674 of relaxed layer 16.
Referring to FIG. 6 as well as to FIG. 16D, top portion 1617 of relaxed layer 16 is removed in any one of the methods described for the removal of relaxed layer portion 80 with reference to FIGS. 4 and 5. Removal of top portion 1617 of relaxedlayer 16 results in the formation of SSOI substrate 100.
The bonding of strained silicon layer 18 to dielectric layer 52 has been experimentally demonstrated. For example, strained layer 18 having a thickness of 54 nanometers (nm) along with .about.350 nm of Si.sub.0.70Ge.sub.0.30 have beentransferred by hydrogen exfoliation to Si handle wafer 50 having dielectric layer 52 formed from thermal SiO.sub.2 with a thickness of approximately 100 nm. The implant conditions were a dose of 4.times.10.sup.16 ions/cm.sup.3 of H.sub.2.sup.+ at 75keV. The anneal procedure was 1 hour at 550.degree. C. to split the SiGe layer, followed by a 1 hour, 800.degree. C. strengthening anneal. The integrity of strained Si layer 18 and good bonding to dielectric layer 52 after layer transfer and annealwere confirmed with cross-sectional transmission electron microscopy (XTEM). An SSOI structure 100 was characterized by XTEM and analyzed via Raman spectroscopy to determine the strain level of the transferred strained Si layer 18. An XTEM image of thetransferred intermediate SiGe/strained Si/SiO.sub.2 structure showed transfer of the 54 nm strained Si layer 18 and .about.350 nm of the Si.sub.0.70Ge.sub.0.30 relaxed layer 16. Strained Si layer 18 had a good integrity and bonded well to SiO.sub.2 54layer after the annealing process.
XTEM micrographs confirmed the complete removal of relaxed SiGe layer 16 after oxidation and HF etching. The final structure includes strained Si layer 18 having a thickness of 49 nm on dielectric layer 52 including SiO.sub.2 and having athickness of 100 nm.
Raman spectroscopy data enabled a comparison of the bonded and cleaved structure before and after SiGe layer 16 removal. Based on peak positions the compostion of the relaxed SiGe layer and strain in the Si layer may be calculated. See, forexample, J. C. Tsang, et al., J. Appl. Phys. 75 (12) p. 8098 (1994), incorporated herein by reference. The fabricated SSOI structure 100 had a clear strained Si peak visible at .about.511/cm. Thus, the SSOI structure 100 maintained greater than 1%tensile strain in the absence of the relaxed SiGe layer 16. In addition, the absence of Ge-Ge, Si-Ge, and Si-Si relaxed SiGe Raman peaks in the SSOI structure confirmed the complete removal of SiGe layer 16.
In addition, the thermal stability of the strained Si layer was evaluated after a 3 minute 1000.degree. C. rapid thermal anneal (RTA) to simulate an aggregate thermal budget of a CMOS process. A Raman spectroscopy comparision was made of SSOIstructure 100 as processed and after the RTA step. A scan of the as-bonded and cleaved sample prior to SiGe layer removal was used for comparision. Throughout the SSOI structure 100 fabrication processs and subsequent anneal, the strained Si peak wasvisible and the peak position did not shift. Thus, the strain in SSOI structure 100 was stable and was not diminished by thermal processing. Furthermore, bubbles or flaking of the strained Si surface 18 were not observed by Nomarski optical microscopyafter the RTA, indicating good mechanical stability of SSOI structure 100.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on theinvention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embracedtherein.
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