Source: http://www.google.com/patents/US6489667?dq=7,550,386
Timestamp: 2014-07-24 06:29:32
Document Index: 717032609

Matched Legal Cases: ['art 61', 'art 61', 'art 61', 'art 61', 'art 61', 'art 61', 'art 61', 'art 61', 'art 61', 'art 61']

Patent US6489667 - Semiconductor device and method of manufacturing such device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsSemiconductor devices and methods of manufacturing such devices are disclosed. In one embodiment of this invention, a semiconductor chip is bonded to a first surface of a substrate. The substrate extends beyond the edge of the chip. Signal input/output pads on the chip are juxtaposed with an opening...http://www.google.com/patents/US6489667?utm_source=gb-gplus-sharePatent US6489667 - Semiconductor device and method of manufacturing such deviceAdvanced Patent SearchPublication numberUS6489667 B1Publication typeGrantApplication numberUS 09/422,115Publication dateDec 3, 2002Filing dateOct 20, 1999Priority dateOct 31, 1998Fee statusPaidPublication number09422115, 422115, US 6489667 B1, US 6489667B1, US-B1-6489667, US6489667 B1, US6489667B1InventorsIl Kwon Shim, Chang Kyu Park, Byung Joon Han, Vincent DiCaprio, Paul HoffmanOriginal AssigneeAmkor Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (18), Referenced by (14), Classifications (47), Legal Events (13) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and method of manufacturing such deviceUS 6489667 B1Abstract Semiconductor devices and methods of manufacturing such devices are disclosed. In one embodiment of this invention, a semiconductor chip is bonded to a first surface of a substrate. The substrate extends beyond the edge of the chip. Signal input/output pads on the chip are juxtaposed with an opening in the substrate. A molded support is formed on the portion of the first surface of the substrate that extends beyond between the sidewall of the edge of the chip. The support prevents bending of the substrate, and allows solder balls to be formed on the entire area of a second surface of the substrate opposite the first surface of the substrate. A heat dissipating plate is mounted on a surface of the chip opposite the substrate. The heat dissipating plate is attached to the support.
a semiconductor chip having a first surface and peripheral sidewalls, wherein the first surface has a plurality of conductive pads; a substrate having a first surface, an opposite second surface, one or more first openings between the first and second surfaces, a layer of metallizations, and a layer of a hardened insulative material at the second surface of the substrate covering said metallizations, wherein the chip is mounted adjacent to the first surface of the substrate such that one or more peripheral portions of the substrate extend beyond an adjacent sidewall of the chip and the pads are each juxtaposed with a respective one of the first openings; an adhesive layer between the first surface of the substrate and the first surface of the chip, wherein a perimeter of the adhesive layer is approximately coplanar with said sidewall of the chip; a plurality of conductors, wherein each conductor is between a respective one of the pads and a respective one of the metallizations and extends through a first opening; a hardened first packaging material in said one or more first openings, said first packaging material covering the pads and conductors; a hardened second packaging material between and contacting the one or more peripheral portions of the first surface of the substrate and the adjacent sidewall of the chip, said hardened second material contacting said first surface of the substrate outside of the perimeter of the adhesive layer; and a plurality of solder balls each connected to a respective one of the metallizations through the insulative layer. 2. The package of claim 1, wherein said substrate comprises a flexible layer positioned between said metallizations and said adhesive layer.
the hardened second packaging material has a first surface on said first surface of the substrate and an opposite second surface; and the second surface of the hardened second packaging material is level with the second surface of the chip. 9. The package of claim 1, wherein said pads are arranged on a central portion of the chip.
a semiconductor chip having a first surface and peripheral sidewalls, wherein the first surface has a plurality of conductive pads; a substrate having a first surface, an opposite second surface, one or more first openings between the first and second surfaces, a layer of metallizations, and a layer of a hardened insulative material at the second surface of the substrate covering said metallizations, wherein the chip is mounted adjacent to the first surface of the substrate such that one or more peripheral portions of the substrate extend beyond an adjacent sidewall of the chip and the pads are each juxtaposed with a respective one of the first openings; an adhesive layer between the first surface of the substrate and the first surface of the chip, wherein a perimeter of the adhesive layer is greater than a perimeter of the chip and smaller than a perimeter of the substrate; a plurality of conductors, wherein each conductor is between a respective one of the pads and a respective one of the metallizations and extends through a first opening; a hardened first packaging material in said one or more first openings, said first packaging material covering the pads and conductors; and a hardened second packaging material between and contacting the one or more peripheral portions of the first surface of the substrate and the adjacent sidewall of the chip, said hardened second material contacting said first surface of the substrate outside the perimeter of the adhesive layer. 14. The package of claim 13, wherein said substrate comprises a flexible layer positioned between said metallizations and said adhesive layer.
a semiconductor chip having a first surface and peripheral sidewalls, wherein the first surface has a plurality of conductive pads; a substrate having a first surface, an opposite second surface, one or more first openings between the first and second surfaces, a layer of metallizations, and a layer of a hardened insulative material at the second surface of the substrate covering said metallizations, wherein the chip is mounted adjacent to the first surface of the substrate such that one or more peripheral portions of the substrate extend beyond an adjacent sidewall of the chip and the pads are each juxtaposed with a respective one of the first openings; an adhesive layer having a first surface against the first surface of the substrate and second surface against the first surface of the chip, wherein a perimeter of the adhesive layer is greater than a perimeter of the chip and smaller than a perimeter of the substrate; a plurality of conductors, wherein each conductor is between a respective one of the pads and a respective one of the metallizations and extends through a first opening; a hardened first packaging material in said one or more first openings, said first packaging material covering the pads and conductors; and a hardened second packaging material between and contacting the one or more peripheral portions of the first surface of the substrate, the adjacent sidewall of the chip and said second surface of said adhesive layer. 17. The package of claim 16, wherein said substrate comprises a flexible layer positioned between said metallizations, and said adhesive layer.
CROSS-REFERENCE TO RELATED APPLICATION This application is related to an application entitled �Chip-Scale Semiconductor Package Of The Fan-Out Type And Method Of Manufacturing Such Packages� (application Ser. No. 09/422027), which was filed with the U.S. Patent and Trademark Office on the same day as the present application and is incorporated by reference herein.
FIELD OF THE INVENTION The present invention relates, in general, to semiconductor devices and a method of manufacturing such devices and, more particularly, to a semiconductor device having a substrate on one surface of a semiconductor chip, the substrate extending on the chip so as to exceed the outside edge of the chip, thus carrying an increased number of solder balls or signal input/output terminals on the device and being almost free from being bent, and effectively dissipating heat from the chip to the atmosphere, the invention also relating to a method of manufacturing such a semiconductor device.
DESCRIPTION OF THE PRIOR ART As is well known to those skilled in the art, a semiconductor device is used for mounting a semiconductor chip on a mother board in addition to intermediating input/output signals between the chip and the mother board. In accordance with the recent trend of compactness, lightness, thinness and smallness of semiconductor chips, it has been necessary to make the semiconductor device compact, light, thin and small.
SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a semiconductor device, of which the substrate extends on one surface of a semiconductor chip so as to exceed the outside edge of the chip and has an area larger than that of the chip, thus effectively carrying an increased number of circuit patterns and solder balls or signal input/output terminals on the device.
BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and other advantages of the present invention will be more clearly understood. from the following detailed description taken in conjunction with the accompanying drawings, in which:
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2a to 2 d show semiconductor devices 201, 202, 203 and 204 in accordance with four different examples of the primary embodiment of this invention.
In order to further improve the heat dissipating effect of the semiconductor device, a heat dissipating plate 90 may be attached to the lower surface of the chip 40, or the surface opposite to the pad carrying surface of the chip 40, as shown in FIGS. 2c and 2 d. In such a case, it is preferable to cover the sidewall of the heat dissipating plate 90 with the second packaging part 61 so as to allow the plate 90 to be firmly interlocked by the second packaging part 61. On the other hand, the lower surface of the heat dissipating plate 90, or the surface opposite to the chip contact surface of the plate 90, may be preferably leveled with the lower surface of the second packaging part 61, or the surface opposite to the substrate contact surface of the part 61. However, it should be understood that the structure of the heat dissipating plate 90 may be somewhat freely changed from the above-mentioned structure without affecting the functioning of this invention. This is well known to those skilled in the art.
The sidewall of the second packaging part 61 may be positioned inside the edge of the substrate 10, having the second circuit patterns, and may extend while being inclined downwardly relative to the sidewall of the chip 40 at an acute angle as shown in FIGS. 3a and 3 c. Alternatively, the sidewall of the second packaging part 61 may be positioned to be aligned with the edge of the substrate 10, having the second circuit patterns, and may extend in parallel to the sidewall of the chip 40 as shown in FIGS. 3b and 3 d. In addition, the lower surface of the chip 40, or the surface opposite to the pad carrying surface of the chip 40, may be preferably leveled with the lower surface of the second packaging part 61, or the surface opposite to the substrate contact surface of the part 61. In such a case, the lower surface of the chip 40 is totally exposed to the atmosphere, thus allowing the chip 40 to more effectively and quickly dissipate heat into the atmosphere during an operation of the semiconductor device.
In order to further improve the heat dissipating effect of the semiconductor device, a heat dissipating plate 90 may be attached to the lower surface of the chip 40, or the surface opposite to the pad carrying surface of the chip 40, as in FIGS. 3c and 3 d. In such a case, it is preferable to cover the sidewall of the heat dissipating plate 90 with the second packaging. part 61 so as to allow the plate 90 to be firmly interlocked by the second packaging part 61.
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