Source: http://www.google.com/patents/US7489545?ie=ISO-8859-1&dq=5,664,133
Timestamp: 2015-03-31 10:06:43
Document Index: 158748480

Matched Legal Cases: ['art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1', 'art 1']

Patent US7489545 - Memory utilizing oxide-nitride nanolaminates - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsStructures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate...http://www.google.com/patents/US7489545?utm_source=gb-gplus-sharePatent US7489545 - Memory utilizing oxide-nitride nanolaminatesAdvanced Patent SearchPublication numberUS7489545 B2Publication typeGrantApplication numberUS 11/492,749Publication dateFeb 10, 2009Filing dateJul 25, 2006Priority dateJul 8, 2002Fee statusPaidAlso published asUS7494873, US7847344, US20040004247, US20050023574, US20060258097, US20060261376Publication number11492749, 492749, US 7489545 B2, US 7489545B2, US-B2-7489545, US7489545 B2, US7489545B2InventorsLeonard Forbes, Kie Y. AhnOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (100), Non-Patent Citations (85), Referenced by (6), Classifications (15), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMemory utilizing oxide-nitride nanolaminates
US 7489545 B2Abstract
24. The method of claim 16, wherein storing a charge within a nitride storage layer includes storing a charge within a tungsten aluminum nitride storage layer. Description
This application is related to the following co-pending, commonly assigned U.S. patent applications: �Memory Utilizing Oxide Nanolaminates,� Ser. No. 10/190,717, and �Memory Utilizing Oxide-Conductor Nanolaminates,� Ser. No. 10/191,336 each of which disclosure is herein incorporated by reference.
Boulin et al., �Semiconductor Memory Apparatus with a Multi-Layer Insulator Contacting the Semiconductor,� U.S. Pat. No. 3,877,054;
Kahng et al., �Method for Fabricating Multilayer Insulator-Semiconductor Memory Apparatus,� U.S. Pat. No. 3,964,085;
DiMaria, D. J., �Graded or Stepped Energy Band-Gap-Insulator MIS structures (GI-MIS or SI-MIS),� Journal of Applied Physics, 50(9), 5826-9 (September 1979);
DeKeersmaecker et al., �Non-Volatile Memory Devices Fabricated From Graded or Stepped Energy Band Gap Insulator MIM or MIS Structure,� U.S. Pat. No. 4,217,601, RE31,083;
Eitan, �Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping,� U.S. Pat. No. 5,768,192;
Etian, B. et al., �NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,� IEEE Electron Device Lett., 21(11), 543-545 (November 2000);
Eitan, B. et al., �Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device, IEEE Electron Device Lett., 22(11), 556-558 (November 2001);
Frohman-Bentchkowsky, D., �An Integrated Metal-Nitride-Oxide-Silicon (MNOS) Memory,� Proceedings of the IEEE, 57(6), 1190-2 (June 1969);
Nakamuma et al., �Memory matrix using MIS semiconductor element,� U.S. Pat. No. 3,665,423;
Britton, J. et al., �Metal-Nitride-Oxide IC Memory Retains Data for Meter Reader,� Electronics, 45(22); 119-23 (23 Oct. 1972);
Cricchi, J. R. et al., �Hardened MNOS/SOS Electrically Reprogrammable Nonvolatile Memory,� IEEE Transactions on Nuclear Science, ns-24(6), 2185-9 (December 1977), Conference: IEEE Annual Conference on Nuclear and Space Radiation Effects, Sponsor: IEEE, 12-15 Jul. 1977, Williamsburg, Va., USA;
White, M. H., �Direct Tunneling in Metal-Nitride-Oxide-Silicon (MNOS) Structures,� Conference: Program of the 31st physical electronics conference (abstracts), page: 1 pp., Publisher: U.S. Dept. Commerce, Washington, D.C., USA, 1971, viii+46 Pages, Sponsor: American Phys. Soc., division of electron and atomic phys, 15-17 Mar. 1971, Gaithersburg, Md., USA;
White, M. H., Cricchi, J. R., �Characterization of Thin-Oxide MNOS Memory Transistors,� IEEE Transactions on Electron Devices, ED-19(12), 1280-8 (December 1972);
Wei, L. S., Simmons, J. G. �Trapping, Emission and Generation in MNOS Memory Devices,� Solid-State Electronics, 17(6), 591-8 (June 1974);
Ferris-Prabhu, A. V., �Charge Transfer in Layered Insulators,� Solid-State Electronics, 16(9), 1086-7 (September 1973);
Ferris-Prabhu, A. V., Lareau, L. J., �Amnesia in Layered Insulator FET Memory Devices,� Conference: 1973 International Electron Devices Meeting Technical Digest, Page: 75-7, Publisher: IEEE, New York, N.Y., USA, 1973, xvi+575 Pages, Sponsor: IEEE, 3-5 Dec. 1973, Washington, D.C., USA;
Ferris-Prabhu, A. V., �Tunneling Theories of Non-Volatile Semiconductor Memories,� Physica Status Solidi A, 35(1), 243-50 (16 May 1976));
L. Forbes, W. P. Noble and E. H. Cloud, �MOSFET Technology for Programmable Address Decode and Correction,� U.S. Pat. No. 6,521,950;
L. Forbes and J. Geusic, �Memory Using Insulator Traps,� U.S. Pat. No. 6,140,181; S. M. Sze, �Physics of Semiconductor Devices�, John Wiley & Sons, New York (1969);
V. M. Bermudez et al, �The Growth and Properties of Al and AlN Films on GaN,� J. Appl. Physics, Vol. 79, No. 1, pp. 110-119, 1996;
Benjamin, M. C., et al, �UV Photoemission Study of Heteroepitaxial AlGaN films Grown on 6H�SiC�, IEEE Conference Record, 1996 International Conf. on Plasma Science, Cat. No. 96CH35939, p. 141, 1996; Pankove, J. I., et al, �Photoemission from GaN�, Applied Physics Letters, Vol. 25, No. 1, pp. 53-55, 1974);
Pankove, J. I., et al, �Photoemission from GaN�, Applied Physics Letters, Vol. 25, No. 1, pp. 53-55, 1974);
Akasaki, I., et al, �Effects of AlN Buffer Layer on Crystallographic Structure and on Electrical and Optical Properties of GaN and Gal-x Alx N Films Grown on Sapphire Substrate by MOVPE�, J. of Crystal Growth, Vol. 98, pp. 209-219, 1989, North Holland, Amsterdam;
Molnar, R. J., et al, �Growth of Gallium Nitride by Electron-Cyclotron Resonance Plasma-Assisted Molecular-Beam Epitaxy: The Role of Charged Species�, J. of Appl. Phys., Vol. 76, No. 8, pp. 4587-4595, 1994;
Lei, T., et al., �Epitaxial Growth and Characterization of Zinc-Blende Gallium Nitride on Silicon�, J. of Appl. Phys., Vol. 71, No. 10, pp. 4933-43, 1992).
A. Yagishita et al., �Dynamic Threshold Voltage Damascene Metal Gate MOSFET (DT-DMG-MOS) With Low Threshold Voltage, High Drive Current and Uniform Electrical Characteristics,� Digest Technical Papers Int. Electron Devices Meeting, San Francisco, December 2000, pp. 663-666;
H. Shimada et al., �Tantalum Nitride Metal Gate FD-SOI CMOS FETs Using Low Resistivity Self-Grown BCC-Tantalum layer,� IEEE Trans. Electron Devices, Vol. 48, No. 8, pp. 1619-1626, 2000;
M. Moriwaki et al. �Improved Metal Gate Process By Simultaneous Gate-Oxide Nitridation During W/WN/Sub X/Gate Formation,� Jpn. J. Appl. Phys., Vol. 39. No. 4B, pp. 2177-2180, 2000;
Jin-Seong Park et al, �Plasma-Enhanced Atomic Layer Deposition of Tantalum Nitrides Using Hydrogen Radicals as a Reducing Agent�, Electrochemical and Solid-State Lett., 4(4) C17-C19, 2001;
Petra Alen et al., �Atomic Layer Deposition of Ta(al)N� Thin Films Using Trimethylaluminum as a Reducing Agent�, Jour, of the Electrochemical Society, 148 (10), G566-G571 (2001);
J.-S. Min et al., �Atomic Layer Deposition of TiN Films by Alternate Supply on Tetrakis (Ethylmethyllamino)-Titanium and Ammonia,� Jpn. J. Appl. Phys., Vol. 37, Part 1, No. 9A, pp. 4999-5004, 15 Sep. 1998;
Jaehyong Koo et al., �Study on the Characteristics of TiAlN Thin Film Deposited by Atomic Layer Deposition Method,� J. Vac. Sci. Technol. A, 19(6), 2831-2834 (2001);
Jae-Sik Min et al, �Metal-Organic Atomic-Layer Deposition of Titanium-Silicon-Nitride Films�, Appl. Phys, Lett., Vol. 75, No. 11, 1521-1523 (1999);
Bjorn Marlid et al, �Atomic layer deposition of BN thin films�, Thin Solid Films, 402, 167-171 (2002);
Anri Nakajima et al, �NH3-Annealed Atomic-Layer-Deposited Silicon Nitride as a High-K Gate Dielectric The High Reliability�, Appl. Phys. Lett., 80 (7), 1252-1254 (2002);
Anri Nakajima et al, �Soft Breakdown Free Atomic-Layer-Deposited Silicon-Nitride/SiO2 Stack Gate Dielectrics�, Technical Digest of International Electron Devices Meeting, page 01-133-134 (2001);
J. W. Kraus et al, �Atomic Layer Deposition of Tungsten Nitride Films Using Sequential Surface Reactions�, 147 (3) 1175-1181 (2000);
R. L. Pruurunen et al, �Growth of Aluminum Nitride on Porous Silica by Atomic Layer Chemical Vapor Deposition�, Applied Surface Science, 165, 193-202 (2000);
C. Adelmann et al, �Atomic-Layer Epitaxy of GaN Quantum Well and Quantum Dots an (0001) AlN�, Jour. Appl. Phys., Vol. 91, No. 8, pp. 5498-5500 (2002).
One of the inventors, along with others, has previously described programmable memory devices and functions based on the reverse stressing of MOSFET's in a conventional CMOS process and technology in order to form programmable address decode and correction in the U.S. Pat. No. 6,521,950 entitled, �MOSFET Technology for Programmable Address Decode and Correction.�. That disclosure, however, did not describe write once read only memory solutions, but rather address decode and correction issues. One of the inventors also describes write once read only memory cells employing charge trapping in gate insulators for conventional MOSFETs and write once read only memory employing floating gates. The same are described in co-pending, commonly assigned U.S. patent applications, entitled �Write Once Read Only Memory Employing Charge Trapping in Insulators,� Ser. No. 10/177,077 and �Write Once Read Only Memory Employing Floating Gates,� Ser. No. 10/177,083. The present application, however, describes transistor cells having oxide-nitride nanolaminate layers and used in integrated circuit device structures.
AlN is a low electron affinity material. For example, UV photoemission measurements of the surface and interface properties of heteroepitaxial AlGaN on 6H�SiC grown by organometallic vapor phase epitaxy (OMVPE) show a low positive electron affinity for Al/sub 0.55/Ga/sub 0.45/N sample and GaN, whereas the AlN samples exhibited the characteristics of negative electron affinity. On the other hand, in semi-insulating and degenerate n-type GaN samples prepared by chemical vapor deposition with heat-cleaned surface the electron affinity was found to lie between 4.1 and 2.1 eV.
Ta�N: Plasma-enhanced atomic layer deposition (PEALD) of tantalum nitride (Ta�N) thin films at a deposition temperature of 260� C. using hydrogen radicals as a reducing agent for Tertbutylimidotris(diethylamido) tantalum have been described. The PEALD yields superior Ta�N films with an electric resistivity of 400 μΩcm and no aging effect under exposure to air. The film density is higher than that of Ta�N films formed by typical ALD, in which NH3 is used instead of hydrogen radicals. In addition, the as-deposited films are not amorphous, but rather polycrystalline structure of cubit TaN. The density and crystallinity of the films increases with the pulse time of hydrogen plasma. The films are Ta-rich in composition and contain around 15 atomic % of carbon impurity. In the PEALD of Ta�N films, hydrogen radicals are used a reducing agent instead of NH3, which is used as a reactant gas in typical Ta�N ALD. Films are deposited on SiO2 (100 nm)/Si wafers at a deposition temperature of 260� C. and a deposition pressure of 133 Pa in a cold-walled reactor using (Net2)3 Ta=Nbut [tertbutylimidotris(diethylamido)tantalum, TBTDET] as a precursor of Ta. The liquid precursor is contained in a bubbler heated at 70� C. and carried by 35 sccm argon. One deposition cycle consist of an exposure to a metallorganic precursor of TBTDET, a purge period with Ar, and an exposure to hydrogen plasma, followed by another purge period with Ar. The Ar purge period of 15 seconds instead between each reactant gas pulse isolates the reactant gases from each other. To ignite and maintain the hydrogen plasma synchronized with the deposition cycle, a rectangular shaped electrical power is applied between the upper and lower electrode. The showerhead for uniform distribution of the reactant gases in the reactor, capacitively coupled with an rf (13.56 MHz) plasma source operated at a power of 100 W, is used as the upper electrode. The lower electrode, on which a wafer resides, is grounded. Film thickness and morphology were analyzed by field emission scanning electron microscopy.
Ta(Al)N(C): Technical work on thin films have been studied using TaCl5 or TaBr5 and NH3 as precursors and Al(CH3)3 as an additional reducing agent. The deposition temperature is varied between 250 and 400� C. The films contained aluminum, carbon, and chlorine impurities. The chlorine content decreased drastically as the deposition temperature is increased. The film deposited at 400� C. contained less than 4 atomic % chlorine and also had the lowest resistivity, 1300 μΩcm. Five different deposition processes with the pulsing orders TaCl5-TMA-NH3, TMA-TACl5�NH3, TaBr5�NH3, TaBr5�Zn�NH3, and TaBr5-TMA-NH3 are used. TaCl5, TaBr5, and Zn are evaporated from open boats held inside the reactor. The evaporation temperatures for TaCl4, TaBr5, and Zn are 90, 140, 380� C., respectively. Ammonia is introduced into the reactor through a mass flowmeter, a needle valve, and a solenoid valve. The flow rate is adjusted to 14 sccm during a continuous flow. TMA is kept at a constant temperature of 16� C. and pulsed through the needle and solenoid valve. Pulse times are 0.5 s for TaCl5, TaBr5, NH3, and Zn whereas the pulse length of TMA is varied between 0.2 and 0.8 s. The length of the purge pulse is always 0.3 s. Nitrogen gas is used for the transportation of the precursor and as a purging gas. The flow rate of nitrogen is 400 sccm.
TiN: Atomic layer deposition (ALD) of amorphous TiN films on SiO2 between 170� C. and 210� C. has been achieved by the alternate supply of reactant sources, Ti[N(C2H5CH3)2]4 [tetrakis(ethylmethylamino)titanium: TEMAT] and NH3. These reactant sources are injected into the reactor in the following order: TEMAT vapor pulse, Ar gas pulse, NH3 gas pulse and Ar gas pulse. Film thickness per cycle saturated at around 1.6 monolayers per cycle with sufficient pulse times of reactant sources at 200� C. The results suggest that film thickness per cycle could exceed 1 ML/cycle in ALD, and are explained by the rechemisorption mechanism of the reactant sources. An ideal linear relationship between number of cycles and film thickness is confirmed.
TiAlN: Koo et al published paper on the study of the characteristics of TiAlN thin film deposited by atomic layer deposition method. The series of metal-Si�N barriers have high resistivity above 1000 μΩcm. They proposed another ternary diffusion barrier of TiAlN. TiAlN film exhibited a NaCl structure in spite of considerable Al contents. TiAlN films are deposited using the TiCl4 and dimethylaluminum hydride ethypiperdine (DMAH-EPP) as the titanium and aluminum precursors, respectively. TiCl4 is vaporized from the liquid at 13-15� C. and introduced into the ALD chamber, which is supplied by a bubbler using the Ar carrier gas with a flow rate of 30 sccm. The DMAH-EPP precursor is evaporated at 60� C. and introduced into the ALD chamber with the same flow rate of TiCl4. The NH3 gas is also used as a reactant gas and its flow rate is about 60 sccm. Ar purging gas is introduced for the complete separation of the source and reactant gases. TiAlN films are deposited at the temperatures between 350 and 400� C. and total pressure is kept constant to be two torr.
TiSiN: Metal-organic atomic-layer deposition (MOALD) achieves near-perfect step coverage step and control precisely the thickness and composition of grown thin films. A MOALD technique for ternary Ti�Si�N films using a sequential supply of Ti[N(CH3)2]4 [tetrakis (dimethylamido) titanium: TDMAT], silane (SiH4), and ammonia (NH3), has been developed and evaluated the Cu diffusion barrier characteristics of a 10 nm Ti�Si�N film with high-frequency C-V measurements. At 180� C. deposition temperature, silane is supplied separately in the sequence of the TDMAT pulse, silane pulse, and the ammonia pulse. The silicon content is the deposited films and the deposition thickness per cycle remained almost constant at 18 at. % and 0.22 nm/cycle, even though the silane partial pressure varied from 0.27 to 13.3 Pa. Especially, the Si content dependence is sirikingly different from the conventional chemical-vapor deposition. Step coverage is approximately 100% even on the 0.3 μm diameter hole with slightly negative slope and 10:1 aspect ratio.
Silicon Nitride: Very recently extremely thin silicon nitride high-k (k=7.2) gate dielectrics have been formed at low temperature (<550� C.) by an atomic-layer-deposition technique with subsequent NH3 annealing at 550� C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of S�N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface. The wafers are cleaned with a NH4OH:H2O2:H2O=0.15:3:7 solution at 80� C. for 10 min and terminated with hydrogen in 0.5% HF solution to suppress the native oxidation. The silicon-nitride gate dielectrics are deposited by alternately supplying SiCl4 and NH3 gases. The SiCl4 exposure at 340-375� C. followed by NH3 exposure at 550� C. is cyclically repeated 20 times. The gas pressure of SiCl4 and NH3 during the deposition is 170 and 300 Torr, respectively. Just after the ALD, NIH3 annealing is carried out for 90 min at 550� C. The Teq value of the ALD silicon-nitride is determined to be 1.2�0.2 nm from the ratio of the accumulation capacitances of the silicon nitride and the SiO2 samples.
AlN: Aluminum nitride (AlN) has been grown on porous silica by atomic layer chemical vapor deposition (ALCVD) from trimethylaluminum (TMA) and ammonia precursors. The ALCVD growth is based on alternating, separated, saturating reactions of the gaseous precursors with the solid substrates. TMA and ammonia are reacted at 423 and 623 Kelvin (K), respectively, on silica which has been dehydroxylated at 1023 K pretreated with ammonia at 823 K. The growth in three reaction cycles is investigated quntitatively by elemental analysis, and the surface reaction products are identified by IR and solid state and Si NMR measurements. Steady growth of about 2 aluminum atoms/nm2 silica A/reaction cycle is obtained. The growth mainly took place through (I) the reaction of TMA which resulted in surface Al-Me and Si-Me groups, and (II) the reaction of ammonia which replaced aluminium-bonded methyl groups with amino groups. Ammonia also reacted in part with the silicon-bonded methyl groups formed in the dissociated reaction of TMA with siloxane bridges. TMA reacted with the amino groups, as it did with surface silanol groups and siloxane bridges. In general, the Al�N layer interacted strongly with the silica substrates, but in the third reaction cycle AlN-type sites may have formed.
GaN: Pseudo substrates of GaN templates have been grown by MOCVD on sapphire, apart from the quantum dot samples, which are grown on bulk 6H�SiC. Prior to GaN ALE, about 400-nm-thick fully relaxed AlN layers are deposited on all substrates. The N2 flux has been fixed to 0.5 sccm and the rf power to 300 W, which leads to maximum AlN and GaN growth rates of about 270 nm/h under N-limited metal-rich conditions. The Ga flux has been calibrated by measuring the GaN growth rate under N-rich conditions using reflection high-energy electron diffraction (RHEED) oscillations at Ts=650� C., where it is safe to assume that the Ga sticking coefficient is unity.
In embodiments of the present invention, the gate structure embodiment of FIG. 5, having silicon oxide-metal oxide-silicon oxide-nitride nanolaminates, is used in place of the gate structure provided in the following commonly assigned pending applications: Forbes, L., �Write Once Read Only Memory Employing Charge Trapping In Gate Insulators,� application Ser. No. 10/177,077; Forbes, L., �Write Once Read Only Memory Employing Floating Gates,� application Ser. No. 10/177,083; Forbes, L., �Write Once Read Only Memory with Large Work Funchtion Floating Gates,� application Ser. No. 10/177,213; Forbes, L., �Nanoncrystal Write Once Read Only Memory for Archival Storage,� application Ser. No. 10/177,214; Forbes, L., �Ferroelectric Write Once Read Only Memory for Archival Storage,� application Ser. No. 10/177,082; Forbes, L., �Vertical NROM Having a Storage Density of 1 Bit Per 1F2,� application Ser. No. 10/177,208; Forbes, L., �Multistate NROM Having a Storage Density Much Greater than 1 Bit Per 1F2,� application Ser. No. 10/177,211; Forbes, L., �NOR Flash Memory Cell with High Storage Density,� application Ser. No. 10/177,483.
Further, in embodiments of the present invention, the gate structure embodiment of FIG. 5, having silicon oxide-metal oxide-silicon oxide-nitride nanolaminates, is used in place of the gate structure provided in the following Eitan, B. et al., �NROM: A novel localized Trapping, 2-Bit Nonvolatile Memory Cell,� IEEE Electron Device Lett., 21(11), 543-545 (November 2000); Eitan, B. et al., �Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM device, IEEE Electron Device Lett., 22(11), 556-558 (November 2001); Maayan, E. et al., �A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate,� Dig. IEEE Int. Solid-State Circuits Conf., 100-101 (2002). In these embodiments, the gate structure embodiment of FIG. 5, having silicon oxide-metal oxide-silicon oxide-nitride nanolaminates used in place of the gate structures in those references, can be programmed in the reverse direction and read in the forward direction to obtain more sensitivity in the device characteristics to the stored charge.
FIGS. 7A-B and 8 are embodiments useful in illustrating the use of charge storage in the oxide-nitride nanolaminate layers to modulate the conductivity of the transistor cell according to the teachings of the present invention. That is, FIGS. 7A-7B illustrates the operation of an embodiment for a novel transistor cell 701 formed according to the teachings of the present invention. And, FIG. 8 illustrates the operation of a conventional DRAM cell 701. As shown in FIG. 7A, the embodiment consists of a gate insulator stack having insulator layers, 710, 708 and 718, e.g. 1. SiO2/oxide-nitride nanolaminate layers/SiO2. In the embodiment of FIG. 7A, the gate insulator stack having insulator layers, 710, 708 and 718, has a thickness 711 thicker than in a conventional DRAM cell, e.g. 801 and is equal to or greater than 10 nm or 100 Å (10−6 cm). In the embodiment shown in FIG. 7A a transistor cell has dimensions 713 of 0.1 μm (10−5 cm) by 0.1 μm. The capacitance, Ci, of the structure depends on the dielectric constant, ∈i, and the thickness of the insulating layers, t. In the embodiment, the dielectric constant is 0.3�10−12 F/cm and the thickness of the insulating layer is 10−6 cm such that Ci=∈i/t, Farads/cm2 or 3�10−7 F/cm2. In one embodiment, a charge of 1012 electrons/cm2 is programmed into the oxide-nitride nanolaminate layers of the transistor cell. Here the charge carriers become trapped in potential wells in the oxide-nitride nanolaminate layers 708 formed by the different electron affinities of the insulators 710, 708 and 718, as shown in FIG. 7A. This produces a stored charge ΔQ=1012 electrons/cm2�1.6�10−19 Coulombs. In this embodiment, the resulting change in the threshold voltage (ΔVt) of the transistor cell will be approximately 0.5 Volts (ΔVt=ΔQ/Ci or 1.6�10−7/3�10−7=� Volt). For ΔQ=1012 electrons/cm3 in an area of 10−10 cm2, this embodiment of the present invention involves trapping a charge of approximately 100 electrons in the oxide-nitride nanolaminate layers 708 of the transistor cell. In this embodiment, an original VT is approximately � Volt and the VT with charge trapping is approximately 1 Volt.
FIG. 7B aids to further illustrate the conduction behavior of the novel transistor cell of the present invention. As one of ordinary skill in the art will understand upon reading this disclosure, if the transistor cell is being driven with a control gate voltage of 1.0 Volt (V) and the nominal threshold voltage without the oxide-nitride nanolaminate layers charged is � V, then if the oxide-nitride nanolaminate layers are charged the transistor cell of the present invention will be off and not conduct. That is, by trapping a charge of approximately 100 electrons in the oxide-nitride nanolaminate layers of the transistor cell, having dimensions of 0.1 μm (10−5 cm) by 0.1 μm, will raise the threshold voltage of the transistor cell to 1.0 Volt and a 1.0 Volt control gate potential will not be sufficient to turn the device on, e.g. Vt=1.0 V, I=0.
According to the teachings of the present invention, the transistor cells, having the gate structure with oxide-nitride nanolaminate layers, in the array are utilized not just as passive on or off switches as transfer devices in DRAM arrays but rather as active devices providing gain. In the present invention, to program the transistor cell �off,� requires only a stored charge in the oxide-nitride nanolaminate layers of about 100 electrons if the area is 0.1 μm by 0.1 μm. And, if the transistor cell is un-programmed, e.g. no stored charge trapped in the oxide-nitride nanolaminate layers, and if the transistor cell is addressed over 10 nS a current of 12.5 μA is provided. The integrated drain current then has a charge of 125 fC or 800,000 electrons. This is in comparison to the charge on a DRAM capacitor of 50 fC which is only about 300,000 electrons. Hence, the use of transistor cells, having the gate structure with oxide-nitride nanolaminate layers, in the array as active devices with gain, rather than just switches, provides an amplification of the stored charge, in the oxide-nitride nanolaminate layers, from 100 to 800,000 electrons over a read address period of 10 nS.
The absence or presence of charge trapped in potential wells, formed by the oxide-nitride nanolaminate layers, is read by addressing the input lines 1112 or control gate lines and y-column/sourcelines to form a coincidence in address at a particular logic cell. The control gate line would for instance be driven positive at some voltage of 1.0 Volts and the y-column/sourceline grounded, if the oxide-nitride nanolaminate layers are not charged with electrons then the transistor would turn on tending to hold the interconnect line on that particular row down indicating the presence of a stored �one� in the cell. If this particular transistor cell has charge trapped in potential wells, formed by the oxide-nitride nanolaminate layers, the transistor will not turn on and the presence of a stored �zero� is indicated in the cell. In this manner, data stored on a particular transistor cell can be read.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3665423Mar 13, 1970May 23, 1972Nippon Electric CoMemory matrix using mis semiconductor elementUS3877054Nov 8, 1973Apr 8, 1975Bell Telephone Labor IncSemiconductor memory apparatus with a multilayer insulator contacting the semiconductorUS3964085Aug 18, 1975Jun 15, 1976Bell Telephone Laboratories, IncorporatedMethod for fabricating multilayer insulator-semiconductor memory apparatusUS4217601Feb 15, 1979Aug 12, 1980International Business Machines CorporationNon-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structureUS4507673Sep 21, 1983Mar 26, 1985Tokyo Shibaura Denki Kabushiki KaishaSemiconductor memory deviceUS4661833Oct 29, 1985Apr 28, 1987Kabushiki Kaisha ToshibaElectrically erasable and programmable read only memoryUS4939559Apr 1, 1986Jul 3, 1990International Business Machines CorporationDual electron injector structures using a conductive oxide between injectorsUS5016215Mar 12, 1990May 14, 1991Texas Instruments IncorporatedHigh speed EPROM with reverse polarity voltages applied to source and drain regions during reading and writingUS5017977Jan 19, 1990May 21, 1991Texas Instruments IncorporatedDual EPROM cells on trench walls with virtual ground buried bit linesUS5021999Dec 9, 1988Jun 4, 1991Mitsubishi Denki Kabushiki KaishaNon-volatile semiconductor memory device with facility of storing tri-level dataUS5027171Aug 28, 1989Jun 25, 1991The United States Of America As Represented By The Secretary Of The NavyDual polarity floating gate MOS analog memory deviceUS5111430Jun 21, 1990May 5, 1992Nippon Telegraph And Telephone CorporationNon-volatile memory with hot carriers transmitted to floating gate through control gateUS5253196Jan 9, 1991Oct 12, 1993The United States Of America As Represented By The Secretary Of The NavyDual-writing-polarity, non-volatileUS5274249Dec 20, 1991Dec 28, 1993University Of MarylandSuperconducting field effect devices with thin channel layerUS5293560Nov 3, 1992Mar 8, 1994Eliyahou HarariMulti-state flash EEPROM system using incremental programing and erasing methodsUS5298447Jul 22, 1993Mar 29, 1994United Microelectronics CorporationMethod of fabricating a flash memory cellUS5303182Nov 6, 1992Apr 12, 1994Rohm Co., Ltd.Nonvolatile semiconductor memory utilizing a ferroelectric filmUS5317535Jun 19, 1992May 31, 1994Intel CorporationGate/source disturb protection for sixteen-bit flash EEPROM memory arraysUS5388069Mar 18, 1993Feb 7, 1995Fujitsu LimitedNonvolatile semiconductor memory device for preventing erroneous operation caused by over-erase phenomenonUS5409859Apr 22, 1994Apr 25, 1995Cree Research, Inc.Method of forming platinum ohmic contact to p-type silicon carbideUS5424993Nov 15, 1993Jun 13, 1995Micron Technology, Inc.Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory deviceUS5430670Nov 8, 1993Jul 4, 1995Elantec, Inc.Differential analog memory cell and method for adjusting sameUS5434815Jan 19, 1994Jul 18, 1995Atmel CorporationStress reduction for non-volatile memory cellUS5438544Jan 28, 1994Aug 1, 1995Fujitsu LimitedNon-volatile semiconductor memory device with function of bringing memory cell transistors to overerased state, and method of writing data in the deviceUS5449941Oct 27, 1992Sep 12, 1995Semiconductor Energy Laboratory Co., Ltd.Semiconductor memory deviceUS5467306Oct 4, 1993Nov 14, 1995Texas Instruments IncorporatedMethod of using source bias to increase threshold voltages and/or to correct for over-erasure of flash epromsUS5477485Feb 22, 1995Dec 19, 1995National Semiconductor CorporationMethod for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrateUS5485422Jun 2, 1994Jan 16, 1996Intel CorporationMemory deviceUS5493140Jun 21, 1994Feb 20, 1996Sharp Kabushiki KaishaNonvolatile memory cell and method of producing the sameUS5508543Apr 29, 1994Apr 16, 1996International Business Machines CorporationLow voltage memoryUS5508544Sep 27, 1994Apr 16, 1996Texas Instruments IncorporatedThree dimensional FAMOS memory devicesUS5530581May 31, 1995Jun 25, 1996Eic Laboratories, Inc.Protective overlayer material and electro-optical coating using sameUS5602777May 24, 1995Feb 11, 1997Sharp Kabushiki KaishaSemiconductor memory device having floating gate transistors and data holding meansUS5627781Nov 8, 1995May 6, 1997Sony CorporationNonvolatile semiconductor memoryUS5670790Sep 19, 1996Sep 23, 1997Kabushikik Kaisha ToshibaElectronic deviceUS5677867Jun 30, 1995Oct 14, 1997Hazani; EmanuelMemory with isolatable expandable bit linesUS5698022Aug 14, 1996Dec 16, 1997Advanced Technology Materials, Inc.Metal oxide chemical vapor depositionUS5714766Sep 29, 1995Feb 3, 1998International Business Machines CorporationNano-structure memory deviceUS5754477Jan 29, 1997May 19, 1998Micron Technology, Inc.Differential flash memory cell and method for programmingUS5768192Jul 23, 1996Jun 16, 1998Saifun Semiconductors, Ltd.Non-volatile semiconductor memory cell utilizing asymmetrical charge trappingUS5795808Nov 12, 1996Aug 18, 1998Hyundai Electronics Industries C., Ltd.Method for forming shallow junction for semiconductor deviceUS5801401Jan 29, 1997Sep 1, 1998Micron Technology, Inc.Flash memory with microcrystalline silicon carbide film floating gateUS5828605Oct 14, 1997Oct 27, 1998Taiwan Semiconductor Manufacturing Company Ltd.Snapback reduces the electron and hole trapping in the tunneling oxide of flash EEPROMUS5852306Jan 29, 1997Dec 22, 1998Micron Technology, Inc.Flash memory with nanocrystalline silicon film floating gateUS5886368Jul 29, 1997Mar 23, 1999Micron Technology, Inc.Dielectric; reduce write and erase voltageUS5912488Jun 24, 1997Jun 15, 1999Samsung Electronics Co., LtdStacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programmingUS5916365Aug 16, 1996Jun 29, 1999Sherman; ArthurSequential chemical vapor depositionUS5936274Jul 8, 1997Aug 10, 1999Micron Technology, Inc.High density flash memoryUS5943262Oct 28, 1998Aug 24, 1999Samsung Electronics Co., Ltd.Non-volatile memory device and method for operating and fabricating the sameUS5959896Feb 27, 1998Sep 28, 1999Micron Technology Inc.Multi-state flash memory cell and method for programming single electron differencesUS5973356Jul 8, 1997Oct 26, 1999Micron Technology, Inc.Ultra high density flash memoryUS5989958Aug 20, 1998Nov 23, 1999Micron Technology, Inc.Flash memory with microcrystalline silicon carbide film floating gateUS5991225Feb 27, 1998Nov 23, 1999Micron Technology, Inc.Programmable memory address decode array with vertical transistorsUS6005790Dec 22, 1998Dec 21, 1999Stmicroelectronics, Inc.Floating gate content addressable memoryUS6011725Feb 4, 1999Jan 4, 2000Saifun Semiconductors, Ltd.Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingUS6013553Jul 15, 1998Jan 11, 2000Texas Instruments IncorporatedZirconium and/or hafnium oxynitride gate dielectricUS6020024Aug 4, 1997Feb 1, 2000Motorola, Inc.Nitrided layer prevents the formation of an oxide at the substrate interface and has a dielectric constant greater than 3.9.US6027961Jun 30, 1998Feb 22, 2000Motorola, Inc.CMOS semiconductor devices and method of formationUS6031263Jul 29, 1997Feb 29, 2000Micron Technology, Inc.DEAPROM and transistor with gallium nitride or gallium aluminum nitride gateUS6049479Sep 23, 1999Apr 11, 2000Advanced Micro Devices, Inc.Operational approach for the suppression of bi-directional tunnel oxide stress of a flash cellUS6072209Jul 8, 1997Jun 6, 2000Micro Technology, Inc.Four F2 folded bit line DRAM cell structure having buried bit and word linesUS6110529Jun 7, 1995Aug 29, 2000Advanced Tech MaterialsUsing a metalorganic reagent solution consisting a metalorganic complex dissolved in a solvent or suspending agent to deposit a metal, a metal oxide or a metal sulfideUS6115281Sep 11, 1998Sep 5, 2000Telcordia Technologies, Inc.Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitorsUS6122201Oct 20, 1999Sep 19, 2000Taiwan Semiconductor Manufacturing CompanyClipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROMUS6124729Feb 27, 1998Sep 26, 2000Micron Technology, Inc.Field programmable logic arrays with vertical transistorsUS6140181Sep 10, 1999Oct 31, 2000Micron Technology, Inc.Memory using insulator trapsUS6143636Aug 20, 1998Nov 7, 2000Micron Technology, Inc.High density flash memoryUS6153468May 17, 1999Nov 28, 2000Micron Technololgy, Inc.Method of forming a logic array for a decoderUS6160739Apr 16, 1999Dec 12, 2000Sandisk CorporationNon-volatile memories with improved endurance and extended lifetimeUS6166401Aug 20, 1998Dec 26, 2000Micron Technology, Inc.Flash memory with microcrystalline silicon carbide film floating gateUS6171900Apr 15, 1999Jan 9, 2001Taiwan Semiconductor Manufacturing CompanyCVD Ta2O5/oxynitride stacked gate insulator with TiN gate electrode for sub-quarter micron MOSFETUS6194228Oct 21, 1998Feb 27, 2001Fujitsu LimitedElectronic device having perovskite-type oxide film, production thereof, and ferroelectric capacitorUS6203613Oct 19, 1999Mar 20, 2001International Business Machines CorporationIntroducing metal nitrate-containing precursor into reactor containing substrate to form metal containing filmUS6222768Apr 26, 2000Apr 24, 2001Advanced Micro Devices, Inc.Auto adjusting window placement scheme for an NROM virtual ground arrayUS6225168Jun 4, 1998May 1, 2001Advanced Micro Devices, Inc.Highly reliable semiconductor device having an increased operating speed as compared to conventional transistors.US6232643Nov 13, 1997May 15, 2001Micron Technology, Inc.Memory using insulator trapsUS6238976Feb 27, 1998May 29, 2001Micron Technology, Inc.Method for forming high density flash memoryUS6243300Feb 16, 2000Jun 5, 2001Advanced Micro Devices, Inc.Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cellUS6246606Sep 2, 1999Jun 12, 2001Micron Technology, Inc.Memory using insulator trapsUS6249020Aug 27, 1998Jun 19, 2001Micron Technology, Inc.DEAPROM and transistor with gallium nitride or gallium aluminum nitride gateUS6255683 *Dec 29, 1998Jul 3, 2001Infineon Technologies AgDynamic random access memoryUS6269023Oct 23, 2000Jul 31, 2001Advanced Micro Devices, Inc.Method of programming a non-volatile memory cell using a current limiterUS6294813Feb 15, 2000Sep 25, 2001Micron Technology, Inc.Information handling system having improved floating gate tunneling devicesUS6297539Jul 6, 2000Oct 2, 2001Sharp Laboratories Of America, Inc.Zicronium or hafnium oxide doped with calcium, strontium, aluminum, lanthanum, yttrium, or scandiumUS6303481Dec 29, 2000Oct 16, 2001Hyundai Electronics Industries Co., Ltd.Method for forming a gate insulating film for semiconductor devicesUS6313518Mar 2, 2000Nov 6, 2001Micron Technology, Inc.Porous silicon oxycarbide integrated circuit insulatorUS6320784Mar 14, 2000Nov 20, 2001Motorola, Inc.Memory cell and method for programming thereofUS6320786Feb 5, 2001Nov 20, 2001Macronix International Co., Ltd.Method of controlling multi-state NROMUS6351411Jun 12, 2001Feb 26, 2002Micron Technology, Inc.Memory using insulator trapsUS6353554Dec 12, 2000Mar 5, 2002Btg International Inc.Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cellUS6365470Dec 29, 2000Apr 2, 2002Secretary Of Agency Of Industrial Science And TechnologyMethod for manufacturing self-matching transistorUS6380579Apr 11, 2000Apr 30, 2002Samsung Electronics Co., Ltd.Capacitor of semiconductor deviceUS6407435Feb 11, 2000Jun 18, 2002Sharp Laboratories Of America, Inc.Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced.US6429063Mar 6, 2000Aug 6, 2002Saifun Semiconductors Ltd.NROM cell with generally decoupled primary and secondary injectionUS6432779Jan 30, 2001Aug 13, 2002Motorola, Inc.Reduction to metal, or hydride thereofUS6438031Oct 26, 2000Aug 20, 2002Advanced Micro Devices, Inc.Method of programming a non-volatile memory cell using a substrate biasUS6445030Jan 30, 2001Sep 3, 2002Advanced Micro Devices, Inc.Flash memory erase speed by fluorine implant or fluorinationUS6449188Jun 19, 2001Sep 10, 2002Advanced Micro Devices, Inc.Low column leakage nor flash array-double cell implementationUS6456531Jun 19, 2001Sep 24, 2002Advanced Micro Devices, Inc.Method of drain avalanche programming of a non-volatile memory cellUS6456536Jun 19, 2001Sep 24, 2002Advanced Micro Devices, Inc.Method of programming a non-volatile memory cell using a substrate bias* Cited by examinerNon-Patent CitationsReference1Abbas, S.A., et al., "N-Channel Igfet Design Limitations Due to Hot Electron Trapping", Technical Digest, International Electron Devices Meeting,,Washington, DC,(Dec. 1975),35-38.2Adelmann, C, et al., "Atomic-layer epitaxy of GaN quantum wells and quantum dots on (0001) AIN", Journal of Applied Physics, 91(8). (Apr. 15, 2002),5498-5500.3Ahn, Seong-Deok, et al., "Surface Morphology Improvement of Metalorganic Chemical Vapor Deposition Al Films by Layered Deposition of Al and Ultrathin TiN", Japanese Journal of Applied Physics, Part 1 (Regular Papers, Short Notes & Review Papers),39(6A), (Jun. 2000),3349-3354.4Akasaki, Isamu, et al., "Effects of AIN Buffer Layer on Crystallographic Structure and on Electrical and Optical Properties of GaN and Ga1-xAlxN Films Grown on Sapphire Substrate by MOVPE", Journal of Crystal Growth, 98(1-2). (Nov. 1, 1989),209-219.5Alen, Petra, "Atomic Layer deposition of Ta(Al)N(C) thin films using trimethylaluminum as a reducing agent", Journal of the Electrochemical Society, 148(10). (Oct. 2001),G566-G571.6Asari, K, et al., "Multi-mode and multi-level technologies for FeRAM embedded reconfigurable hardware", Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International,(Feb. 15-17, 1999),106-107.7Benjamin, M., "UV Photoemission Study of Heteroepitaxial AlGaN Films Grown on 6H-SiC", Applied Surface Science, 104/105, (Sep. 1996),455-460.8Bermudez, V., "The Growth and Properties of Al and AlN Films on GaN(0001)-(1 x1)", Journal of Applied Physics, 79(1). (Jan. 1996),110-119.9Bright, A A., et al., "Low-rate plasma oxidation of Si in a dilute oxygen/helium plasma for low-temperature gate quality Si/SiO2 interfaces", Applied Physics Letters, 58(6), (Feb. 1991),619-621.10Britton, J, et al., "Metal-nitride-oxide IC memory retains data for meter reader", Electronics, 45(22), (Oct. 23, 1972),119-23.11Carter, R J., "Electrical Characterization of High-k Materials Prepared By Atomic Layer CVD", IWGI, (2001),94-99.12Chaitsak, Suticai, et al., "Cu(InGa)Se2 thin-film solar cells with high resistivity ZnO buffer layers deposited by atomic layer deposition", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 38(9A). (Sep. 1999),4989-4992.13Chang, C., "Novel Passivation Dielectrics-The Boron-or Phosphorus-Doped Hydrogenated Amorphous Silicon Carbide Films", Journal of the Electrochemical Society, 132, (Feb. 1985),418-422.14Cheng, Baohong, et al., "The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100nm MOSFET's", IEEE Transactions on Electron Devices, 46(7), (Jul. 1999),1537-1544.15Cricchi, J R., et al., "Hardened MNOS/SOS electrically reprogrammable nonvolatile memory", IEEE Transactions on Nuclear Science, 24(6), (Dec. 1977),2185-9.16Demichelis, F., "Influence of Doping on the Structural and Optoelectronic Properties of Amorphous and Microcrystalline Silicon Carbide", Journal of Applied Physics, 72(4). (Aug. 15, 1992),1327-1333.17Demichelis, F., "Physical Properties of Undoped and Doped Microcrystalline SIC:H Deposited By PECVD", Materials Research Society Symposium Proceedings, 219. Anaheim, CA,(Apr. 30-May 3, 1991),413-418.18Dimaria, D J., "Graded or stepped energy band-gap-insulator MIS structures (GI-MIS or SI-MIS)", Journal of Applied Physics, 50(9), (Sep. 1979),5826-5829.19Dipert, B., et al., "Flash Memory goes Mainstream", IEE Spectrum, No. 10, (Oct. 1993),48-50.20Eitan, Boaz, et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell", IEEE Electron Device Letters, 21(11), (Nov. 2000),543-545.21Elam, J W., et al., "Kinetics of the WF6 and Si2H6 surface reactions during tungsten atomic layer deposition", Surface Science, 479(1-3), (May 2001), 121-135.22Fauchet, P M., et al., "Optoelectronics and photovoitaic applications of microcrystalline SiC", Symp. on Materials Issues in Mecrocrystalline Semiconductors, (1989),291-292.23Ferris-Prabhu, A V., "Amnesia in layered insulator FET memory devices", 1973 International Electron Devices Meeting Technical Digest, (1973),75-77.24Ferris-Prabhu, A V., "Charge transfer in layered insulators", Solid-State Electronics, 16(9), (Sep. 1973),1086-7.25Ferris-Prabhu, A V., "Tunnelling theories of non-volatile semiconductor memories", Physica Status Solidi A, 35(1), (May 16, 1976),243-50.26Fisch, D E., et al., "Analysis of thin film ferroelectric aging", Proc. IEEE Int. Reliability Physics Symp., (1990),237-242.27Forbes, L., et al., "Field Induced Re-Emission of Electrons Trapped in SiO", IEEE Transactions on Electron Devices, ED-26 (11), Briefs,(Nov. 1979),1816-1818.28Forsgren, Katarina, "Atomic Layer Deposition of HfO2 using hafnium iodide", Conference held in Monterey, California, (May 2001),1 page.29Frohman-Bentchkowsky, D, "An Integrated metal-nitride-oxide-silicon (MNOS) memory", Proceedings of the IEEE, 57(6). (Jun. 1969),1190-1192.30Fuyuki, Takashi, et al., "Electronic Properties of the Interface between Si and TiO2 Deposited at Very Low Temperatures", Japanese Journal of Applied Physics, Part 1 (Regular Papers & Short Notes), 25(9). (Sept. 1986),1288-1291.31Fuyuki, Takashi, et al., "Initial stage of ultra-thin SiO2 formation at low temperatures using activated oxygen", Applied Surface Science, 117-118, (Jun. 1997),123-126.32Guha, S, et al., "Atomic beam deposition of lanthanum-and yttrium-based oxide thin films for gate dielectrics", Applied Physics Letters, 77, (2000),2710-2712.33Hubbard, K. J., et al., "Thermodynamic stability of binary oxides in contact with silicon", Journal of Materials Research, 11(11). (Nov. 1996),2757-2776.34Hwang, N., et al., "Tunneling and Thermal Emission of Electrons from a Distribution of Deep Traps in SiO", IEEE Transactions on Electron Devices, 40(6), (Jun. 1993),1100-1103.35Jeong, Chang-Wook, "Plasma-Assisted Atomic Layer Growth of High-Quality Aluminum Oxide Thin Films", Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 40(1), (Jan. 2001),285-289.36Juppo, Marika, "Use of 1,1-Dimethylhydrazine in the Atomic Layer Deposition of Transition Metal Nitride Thin Films", Journal of the Electrochemical Society, 147(9), (Sep. 2000),3377-3381.37Kim, C. T., et al., "Application of Al2O3 Grown by Atomic Layer Deposition to DRAM and FeRAM", International Symposium in Integrated Ferroelectrics, (Mar. 2000),316.38Klaus, J W., et al., "Atomic layer deposition of tungsten nitride films using sequential surface reactions", Journal of the Electrochemical Society, 147(3), (Mar. 2000),1175-81.39Koo, J, "Study on the characteristics of TiAIN thin film deposited by atomic layer deposition method", Journal of Vacuum Science & Technology A-Vacuum Surfaces & Films , 19(6), (Nov. 2001),2831-4.40Kukli, Kaupo, "Atomic Layer Deposition of Titanium Oxide Til4 and H2O2", Chemical Vapor Deposition, 6(6), (2000),303-310.41Kukli, Kaupo, "Tailoring the dielectric properties of HfO2- Ta2O3nanolaminates", Appl. Phys. Lett., 68, (1996),3737-3739.42Lee, Dong H., et al., "Metalorganic chemical vapor deposition of TiO2 Nanatase thin film on Si substrate", Applied Physics Letters, 66(7), (Feb. 1995),815-816.43Lei, T., "Epitaxial Growth and Characterization of Zinc-Blende Gallium Nitride on (001) Silicon", Journal of Applied Physics, 71(10), (May 1992),4933-4943.44Leskela, M, "ALD precursor chemistry: Evolution and future challenges", Journal de Physique IV (Proceedings), 9(8), (Sept. 1999),837-852.45Liu, C. T., "Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFETs", International Electron Devices Meeting 1998. Technical Digest, (1998),747-750.46Luan, H., "High Quality Ta2O5 Gate Dielectrics with Tox,eq less than 10A", IEDM, (1999),pp.141-144.47Lusky, et al., "Characterization of channel hot electron injection by the subthreshold slope of NROM/sup TM/device", IEEE Electron Device Letters, vol. 22, No. 11, (Nov. 2001),556-558.48Maayan, E., et al., "A 512Mb BROM Flash Data Storage: Memory with 8MB/s Data Rate", ISSCC 2002 / Session 6 / SRAM and Non-Volatile Memories.(Feb. 2002),4 pages.49Marlid, Bjorn, et al., "Atomic layer deposition of BN thin films", Thin Solid Films, 402(1-2), (Jan. 2002),167-171.50Martins, R, "Transport Properties of Doped Silicon Oxycarbide Microcrystalline Films Produced by Spatial Separation Techniques", Solar Energy Materials and Solar Cells, 41-42, (1996),493-517.51Martins, R., "Wide Band Gap Microcrystalline Silicon Thin Films", Diffusion and Defect Data : Solid State Phenomena, 44-46, Part 1, Scitec Publications,(1995),299-346.52Min, J., "Metal-organic atomic-layer deposition of titanium-silicon-nitride films", Applied Physics Letters, 75(11), (1999),1521-1523.53Min, Jae-Sik, et al., "Atomic layer deposition of TiN films by alternate supply of tetrakis (ethylmethylamino)-titanium and ammonia", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 37(9A). (Sep. 1998),4999-5004.54Moazzami, R, "Endurance properties of Ferroelectric PZT thin films", Int. Electron Devices Mtg., San Francisco,(1990),417-20.55Moazzami, R, "Ferroelectric PZT thin films for semiconductor memory", Ph.D Thesis, University of California, Berkeley, (1991).56Molnar, R., "Growth of Gallium Nitride by Electron-Cyclotron Resonance Plasma-Assisted Molecular-Beam Epitaxy: The Role of Charged Species", Journal of Applied Physics, 76(8). (Oct. 1994),4587-4595.57Morishita, S, "Atomic-layer chemical-vapor-deposition of SiO2by cyclic exposures of CH3OSi(NCO)3 and H2O2", Japanese Journal of Applied Physics Part 1- Regular Papers Short Notes & Review Papers , 34(10), (Oct. 1995),5738-42.58Moriwaki, Masaru, et al., "Improved metal gate process by simultaneous gate-oxide nitridation during W/WN/sub x/gate formation", Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers , 39(4B), (Apr. 2000) ,2177-2180.59Muller, R. S., et al., In: Device Electronics for Integrated Circuits, Second Edition, John Wiley & Sons, New York,(1986),p. 157.60Nakajima, Anri, et al., "NH3 annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability", Applied Physics Letters, 80(7). (Feb. 2002),1252-1254.61Nakjima, Anri, "Soft breakdown free atomic-layer-deposited silicon-nitride SiO2 stack gate dielectrics", International Electron Devices Meeting. Technical Digest, (2001),6.5.1-4.62Niilisk, A, "Atomic-scale optical monitoring of the initial growth of TiO2 thin films", Proceedings of the SPIE-The International Society for Optical Engineering, 4318. (2001),72-77.63Pankove, J., "Photoemission from GaN", Applied Physics Letters, 25(1), (Jul. 1, 1974),53-55.64Park, Jin-Seong, et al., "Plasma-Enhanced Atomic Layer Deposition of Tantaium Nitrides Using Hydrogen Radicals as a Reducing Agent", Electrochemical & Solid-State Letters, 4(4), (Apr. 2001),C17-19.65Puurunen, R L., et al., "Growth of aluminum nitride on porous silica by atomic layer chemical vapour deposition", Applied Surface Science, 165(2-3), (Sept. 12, 2000),193-202.66Renlund, G. M., "Silicon oxycarbide glasses: Part I. Preparation and chemistry", J. Mater. Res., (Dec. 1991),pp. 2716-2722.67Renlund, G. M., "Silicon oxycarbide glasses: Part II. Structure and properties", J. Mater. Res., vol. 6, No. 12,(Dec. 1991),pp. 2723-2734.68Ritala, Mikko, "Atomic Layer Epitaxy Growth of Titanium, Zirconium and Hafnium Dioxide Thin Films", Annales Academiae Scientiarum Fennicae. (1994),24-25.69Robertson, J., "Band offsets of wide-band-gap oxides and implications for future electronic devices", Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 18(3), (May-Jun. 2000),1785-1791.70Shimada, Hiroyuki, et al., "Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer", IEEE Transactions on Electron Devices, vol. 48, No. 8. (Aug. 200),1619-1626.71Sneh, Ofer, "Thin film atomic layer deposition equipment for semiconductor processing", Thin Solid Films, 402. (2002),248-261.72Song, Hyun-Jung, et al., "Atomic Layer Deposition of Ta2 O5 Films Using Ta2 O5 and NH3", Ultrathin SiO2 and High-K Materials for ULSI Gate Dielectrics. Symposium, (1999),469-471.73Suntola, T., "Atomic Layer Epitaxy", Handbook of Crystal Growth, 3; Thin Films of Epitaxy, Part B; Growth Mechanics and Dynamics. Amsterdam,(1994),601-663.74Suntola, Tuomo, "Atomic layer epitaxy", Thin Solid Films, 216(1), (Aug. 28, 1992),84-89.75Sze, S M., "Physics of Semiconductor Devices", New York : Wiley. (1981),504-506.76Sze, S M., "Physics of Semiconductor Devices", New York : Wiley.(1981),473.77Wei, L S., et al., "Trapping, emission and generation in MNOS memory devices", Solid-State Electronics, 17(6). (Jun. 1974),591-8.78White, M H., "Direct tunneling in metal-nitride-oxide-silicon (MNOS) structures", Programme of the 31st physical electronics conference. (1971), 1.79White, M H., et al., "Characterization of thin-oxide MNOS memory transistors", IEEE Transactions on Electron Devices, ED-19(12). (Dec. 1972),1280-1288.80Wilk, G. D., "High-K gate dielectrics: Current status and materials properties considerations", Journal of Applied Physics, 89(10). (May 2001),5243-5275.81Wood, S W., "Ferroelectric memory design", M.A.Sc. thesis, University of Toronto. (1992).82Yagishita, Atsushi, et al., "Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) with low threshold voltage, high drive current and uniform electrical characteristics", International Electron Devices Meeting 2000. Technical Digest. IEDM. (Dec. 2000),663-666.83Yoder, M, "Wide Bandgap Semiconductor Materials and Devices", IEEE Transactions on Electron Devices, 43. (Oct. 1996), 1633-1636.84Zhang, H., "Atomic Layer Deposition of High Dielectric Constant Nanolaminates", Journal of The Electrochemical Society, 148(4). (Apr. 2001),F63-F66.85Zhu, W J., et al., "Current transport in metal/hafnium oxide/silicon structure", IEEE Electron Device Letters, 23, (2002),97-99.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7915168 *Mar 10, 2010Mar 29, 2011Micron Technology, Inc.Semiconductor processing methodsUS8012824 *Jun 16, 2006Sep 6, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Process to make high-K transistor dielectricsUS8440567Feb 23, 2011May 14, 2013Micron Technology, Inc.Semiconductor processing methodsUS8735292Apr 8, 2013May 27, 2014Micron Technology, Inc.Semiconductor processing methodsUS8785272 *Sep 1, 2011Jul 22, 2014Taiwan Semiconductor Manufacturing Company, Ltd.Process to make high-K transistor dielectricsUS20110318915 *Sep 1, 2011Dec 29, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Process to make high-k transistor dielectrics* Cited by examinerClassifications U.S. Classification365/185.05, 365/185.03International ClassificationH01L29/792, H01L27/115, G11C11/56, G11C16/04Cooperative ClassificationH01L27/11568, H01L27/115, H01L29/792, G11C16/0416, G11C11/5671European ClassificationH01L29/792, G11C11/56M, H01L27/115, H01L27/115G4Legal EventsDateCodeEventDescriptionJul 11, 2012FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services