Source: https://patents.google.com/patent/US8468294
Timestamp: 2018-03-17 14:47:06
Document Index: 313371803

Matched Legal Cases: ['Application No. 2011', 'Application No. 2010', 'Application No. 2010', 'application No. 61', 'Application No. 2010', 'Application No. 2010', 'Application No. 2010', 'Application No. 2011', 'Application No. 2011']

US8468294B2 - Non-volatile memory with multi-gear control using on-chip folding of data - Google Patents
Non-volatile memory with multi-gear control using on-chip folding of data
US8468294B2
US8468294B2 US12642611 US64261109A US8468294B2 US 8468294 B2 US8468294 B2 US 8468294B2 US 12642611 US12642611 US 12642611 US 64261109 A US64261109 A US 64261109A US 8468294 B2 US8468294 B2 US 8468294B2
US12642611
US20110153913A1 (en )
This application is related to the following United States patent applications: one entitled “Maintaining Updates of Multi-Level Non-Volatile Memory in Binary Non-Volatile Memory,” by Gorobets et al. and having, now U.S. Published Application No. 2011/0153912A1; and one entitled “Data Transfer flows for On-Chip Folding” by Huang et al. and having, now U.S. Pat. No. 8,144,512, both of which are being filed concurrently herewith.
As each cell is, however, programmed to near its eventual target state, the sort of neighboring cell to cell couplings, or “Yupin” effect, described in U.S. Pat. No. 6,870,768 are presenting most of their effect. Because of this, when the fine program phase (shown on the bottom line) is executed, these couplings have largely been factored in to this final phase so the cell distributions are more accurately resolved to their target ranges. More detail on these subjects is given in U.S. Pat. Nos. 6,870,768 and 6,657,891 and in the U.S. patent application entitled “Atomic Program Sequence and Write Abort Detection” by Gorobets et al. having, now U.S. Pat. No. 8,054,684, and which is being filed concurrently herewith, and which presents a “diagonal” first-foggy-fine method.
A number of memory system arrangements where the non-volatile memory includes both binary and multi-level sections will now be described. In a first of these, in a flash memory having an array of memory cells that are organized into a plurality of blocks, the cells in each block being erased together, the flash memory is partitioned into at least two portions. A first portion forms the main memory for storing mainly user data. Individual memory cells in the main memory being configured to store one or more bits of data in each cell. A second portion forms a cache for data to be written to the main memory. The memory cells in the cache portion are configured to store less bits of data in each cell than that of the main memory. Both the cache portion and the main memory portion operate under a block management system for which cache operation is optimized. A more detailed presentation of this material is developed in the following U.S. patent application or provisional application numbers: Ser. No. 12/348,819, now U.S. Published Application. No. 2010/0174845A1; Ser. No. 12/348,825, now U.S. Pat. No. 8,040,744; Ser. No. 12/348,891, now U.S. Pat. No. 8,040,744; Ser. No. 12/348,895, now U.S. Published Application No. 2010/0174846A1; Ser. No. 12/348,899, now U.S. Published Application No. 2010/0174846A1; and 61/142,620, now expired, all filed on Jan. 5, 2009.
The various sorts of non-volatile memories described above can be operated in both binary foin s and multi-state (or multi-level) forms. Some memory systems store data in both binary and multi-state formats; for example, as data can typically be written more quickly and with less critical tolerances in binary form, a memory may initial write data in binary form as it is received from a host and later rewrite this data in a multi-state format for greater storage density. In such memories, some cells may be used in binary format with others used in multi-state format, or the same cells may be operated to store differing numbers of bits. Examples of such systems are discussed in more detail in U.S. Pat. No. 6,456,528; US patent publication number 2009/0089481; and the following U.S. patent application No. 61/142,620, now expired; Ser. No. 12/348,819, now U.S. Published Application No. 2010/0174845A1; Ser. No. 12/348,825, now U.S. Pat. No. 8,040,744; Ser. No. 12/348,891, now U.S. Pat. No. 8,040,744; Ser. No. 12/348,895, now U.S. Published Application No. 2010/0174846A1; and Ser. No. 12/348,899, now U.S. Published Application No. 2010/0174846A1. The techniques described in this section relate to rewriting data from a binary format into a multi-state format in a “folding” process executed on the memory device itself, without the requirement of transferring the data back to the controller for reformatting. The on-memory folding process can also be used in a special way to manage error correction code (ECC) where the relative state of the data in the memory cell, when stored in multi-state form, is taken into account when considering that the most probable errors are transitions between the neighboring states. (So called “Strong ECC” or “SECC”, where additional background detail on these subjects can be found in the following US patents, patent publications, and patent application numbers: 2009/0094482, now U.S. Pat. Nos. 7,911,836; 7,502,254; 2007/0268745, now U.S. Pat. No. 7,583,545; 2007/0283081 now U.S. Pat. Nos. 7,711,890; 7,310,347; 7,493,457; 7,426,623; 2007/0220197; 2007/0065119, now U.S. Pat. No. 7,913,004; 2007/0061502, now U.S. Pat. No. 7,752,382; 2007/0091677, now U.S. Pat. No. 7,954,037; 2007/0180346, now U.S. Pat. No. 8,020,060; 2008/0181000, now U.S. Pat. No. 7,660,166; 2007/0260808; 2005/0213393, now abandoned; U.S. Pat. Nos. 6,510,488; 7,058,818; 2008/0244338, now U.S. Pat. No. 7,966,550; 2008/0244367, now U.S. Pat. No. 7,975,209; 2008/0250300, now U.S. Pat. No. 7,904,793; and 2008/0104312, now U.S. Pat. No. 8,055,972.) The system can also use ECC management which does not consider state information and manages ECC based on single page information.
Although this folding has here been described as folding N logical pages of data from N physical pages of binary memory to one physical page of N-bit per cell memory. (Here, the physical page is taken as a whole word line.) More generally, the logical data can be scattered in any fashion between physical pages. In this sense, it is not a direct 3-page to single page mapping, but is more of a mapping with 3-to-1 ratio. More detail on on-chip data folding is given in U.S. application Ser. No. 12/478,997 filed on Jun. 5, 2009, now U.S. Pat. No. 8,027,195. Further detail and structures useful for folding as also presented in U.S. application Ser. No. 12/478,997 filed on Jun. 5, 2009, now U.S. Pat. No. 8.027,195.
In the exemplary embodiment, data is first written to the binary block 301 and then folded into D3 blocks. For example, once three 3 pages are written into the binary memory, then can then be folded into a single page in D3 memory 303 or follow the sort of diagonal lower-foggy-fine programming method described in “Atomic Program Sequence and Write Abort Detection” by Gorobets et al. having, now U.S. Pat. No. 8,054,684 and which is being filed concurrently herewith. In the on-chip folding embodiment, the binary and MLC portions will be from different blocks formed along the same bit lines. More generally, other rewrite techniques can be used. Although in some embodiments data may written directly to multi-state memory, under this arrangement discussed here user data is first written from the volatile. RAM into binary memory and then “triplets” (for the D3 example) of pages, such as in 315 for the logical groups X, X+1 and X+2, that are then combined and stored in a multi-state format as a “newly intact” physical page 331, where it is stored along with other such previously written “original” pages 333. When data of one of the pages stored in a D3 block is updated, rather than store the updated data in a D3 block, this can, at least initially, stored in a binary block Update Block, or UB, 317, as is described in the next section.
This arrangement also can support the higher performance of a parallel folding mode, such as is described in a U.S. patent application entitled “Method and System for Achieving Die Parallelism Through Block Interleaving”, having, now U.S. Published Application No. 2011/0153911. and being filed concurrently herewith, as it supports a virtual update block consolidation in that is de-coupled from folding operations. Also, as frequently updated Update blocks are in D1 blocks pool, with the D3 block pool being preferably used only for intact blocks, the system should experience higher endurance. By maintaining the update blocks in binary and only writing to MLC memory for intact blocks, this further allows for an on-chip data folding that supports physical data scrambling.
Steady state, where the amount of input to D1 is balanced to be more or less the same as the amount of folding from D1 to D3 . This arrangement gives the better performance for extended transfers of sequential.
Referring to the bottom line of FIG. 21, this shows the stages of the D1 to D3 folding process. (Although FIG. 21 is not drawn exactly to scale, the sizes of the various elements give a reasonable approximation of the relative time scales involved.) In the exemplary embodiment, three D1 blocks are available for folding into one D3 block, so that all of these D1 data pages are available for folding to D3 . For the first, foggy, and fine stages, the three word lines (call them x, y, z) from the D1 blocks are used. In the folding process, the page x is read into the read/write data latches (701) and then written into a D3 word line in a first programming step (703). For the foggy step, the x, y, and z are needed and are read into latches (705) and the memory executes a foggy write (707) to the D3 word line. The fine phase then follows, again the word lines x, y, and z are loaded into the read/write latches (709) and programmed into the D3 word line for the fine write (711). This completes the first, foggy, fine stages and the data can then be read out. (The foggy-fine programming algorithm is discussed in more detail above with respect to FIG. 7F.)
This allows for a balance to be achieved between the D1 writes and D1 to D3 folding that is here preferred for sustained writing of sequential data from a host. (It should be noted that the data being folded in 707, 711 is not the same set of data being written to D1 at 723, but a set of data from an earlier write to D1 .) As data has been transferred out of RAM at 721, this has opened up the RAM, which is relatively limited capacity, to receive more data form the host; and since the host to RAM transfer does not involve the non-volatile memory circuit or use its latches, these host to RAM transfers can be hidden behind the various phases of the multi-level memory write, further improving performance. Thus, the transfers at 735 and 737 are pipelined with the fine programming phase, as were the transfers at 731 and 733 hidden behind the initial phases (701-707), which provided the data subsequently transferred out of RAM at 721. (Referring back to FIG. 20, the transfers indicated at (1) can effectively be hidden behind those indicated at (2).) This process then continues on in this way until the transfer is complete.
For increased performance, this process can also be executed in parallel across multiple dies. FIG. 22A shows a 3-die example. Here, all of the die execute the phases of the folding operations in parallel. After both the foggy and fine phases, data is again transferred from RAM to the non-volatile memory, where it is written into D1 . In this example, there is a transfer of 2×16 KB of D1 data together to maximize the use of the RAM memory. The D1 transfers from RAM can be to any of the dies, for example cycling through them in order, and them all three dies run their folding phases in parallel. (More detail on such transfers is given in “Method and System for Achieving Die Parallelism Through Block Interleaving”, having Ser. No. 12/642,181)
Balanced mode folding uses a firmware or system algorithm to maintain sustained sequential write performance. In the architecture described above, host data must go to D1 blocks first, then get folded to D3 block. To keep sustained system write performance, over a given period of time the amount of data written to D1 should be the essentially the same as the amount of data folded from D1 to D3 . One arrangement for this was presented in the last section. (More generally, balanced mode can be with or without the insertion of D1 writes between the foggy and fine phases of the folding, as described in the last section.) To maintain this balance, there should be no garbage collection and the host data coming in is in sequential order, being sent to D1 update blocks instead of binary cache. If the amount of D1 write and D1 to D3 folding is out of balance, such as, for example, more D1 writes then folding, then there will be higher burst performance for this time period. Conversely, if the amount of Dl write is less than the amount of folding, the performance is lower than sustained performance.
There can be situations where the memory system needs to free up update block resource or perform some internal data management operations, such as program failure recovery, post-write read recovery (such as disclosed in the patent application entitled “Non-Volatile Memory and Method with Post-Write Read and Adaptive Re-Write to Manage Errors” by Dusija et al. having, now U.S. Published Application No. 2011/0099460A1, that is being filed concurrently herewith, read scrub, or wear leveling, among others. The system may go into urgent mode for garbage collection which involves copy and folding. This is considered the second mode or gear of folding control. For example, operations during the urgent mode could include D1 to D1 copy, D3 to D1 copy, or D1 to D3 urgent folding. According to product application for which the memory system is used, meta-block copy and urgent folding can be executed in series for a single host command, and there is no host transfer during garbage collection. For applications that have timeout limit (such as SD cards, where there is 250 ms write timeout limit), the excess time can be used in the urgent mode for operations such as scheduled phased garbage collection that may be required; for example, there could be a single sector host write, then x amount of copy steps preformed, or y amount of urgent D1 to D3 folding preformed, depending on the specific algorithm.
determining in the controller to operate the memory system according to one of a plurality of modes, including a first mode, wherein the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, wherein the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher rate than in the first mode;
operating the memory system according to determined mode;
wherein the non-volatile memory circuit comprises a plurality of non-volatile memory cells formed along a plurality of word lines and a plurality of bits lines formed as plurality of erase blocks, and wherein the physical pages of the first and second portions belong to differing erase blocks that share a common set of bit lines; and
wherein the memory system operates according to the second mode based on the number of available blocks in the first portion; and
wherein multi-state programming operations include a first phase and a second phase, and during the first mode one or more binary write operations to the first section of the memory are performed between the phases of the multi-state programming operations.
3. The method of claim 1, wherein the plurality of modes includes a third mode, wherein folding operations are background operations executed when the memory system is not receiving data from the host.
4. A method of operating a memory system including a controller and a non-volatile memory circuit, the non-volatile memory circuit having a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format, and the controller managing the storage of data on the non-volatile memory circuit and the transfer of data between the memory system and a host system, the method comprising:
wherein the memory system is operated according to the first mode in response to the controller determining that data received from the host is for logically sequential pages of data; and
5. The method of claim 4, wherein the second section store data in an N-bit per cell format,
7. The method of claim 4, wherein the plurality of modes includes a third mode, wherein folding operations are background operations executed when the memory system is not receiving data from the host.
8. The method of claim 4, wherein the multi-state programming operation uses a foggy-fine programming algorithm and the first phase includes a foggy programming operation and the second phase is a fine programming operation.
9. The method of claim 4, wherein the first phase further includes an initial programming operation prior to the foggy programming operation.
10. The method of claim 4, wherein the memory further includes a volatile buffer memory, the method further including:
11. The method of claim 4, wherein the non-volatile memory circuit comprises a plurality of non-volatile memory cells formed along a plurality of word lines and a plurality of bits lines formed as plurality of erase blocks, and wherein the physical pages of the first and second portions belong to differing erase blocks that share a common set of bit lines.
12. The method of claim 4, wherein the memory system operates according to the second mode in response to the controller determining that data received from the host is for logically non-sequential pages of data.
13. The method of claim 4, wherein the memory system operates according to the second mode in response to a program failure.
15. The method of claim 4, wherein the memory system operates according to the second mode in response to receiving a command from set of one or more commands.
16. The method of claim 4, wherein the memory system operates according to the second mode in response to the controller determining that the host has sent a command for writing control data.
18. The method of claim 4, wherein the memory system operates according to the second mode in response to receiving a write command for a predetermined address.
US12642611 2009-12-18 2009-12-18 Non-volatile memory with multi-gear control using on-chip folding of data Active 2031-08-30 US8468294B2 (en)
US12642611 US8468294B2 (en) 2009-12-18 2009-12-18 Non-volatile memory with multi-gear control using on-chip folding of data
EP20100799198 EP2513908A1 (en) 2009-12-18 2010-12-16 Non-volatile memory with multi-gear control using on-chip folding of data
KR20127018047A KR20120106800A (en) 2009-12-18 2010-12-16 Non-volatile memory with multi-gear control using on-chip folding of data
US12642649 Continuation-In-Part US8144512B2 (en) 2009-12-18 2009-12-18 Data transfer flows for on-chip folding
US13491879 Continuation-In-Part US8725935B2 (en) 2009-12-18 2012-06-08 Balanced performance for on-chip folding of non-volatile memories
US8468294B2 true US8468294B2 (en) 2013-06-18
US12642611 Active 2031-08-30 US8468294B2 (en) 2009-12-18 2009-12-18 Non-volatile memory with multi-gear control using on-chip folding of data
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EP2513908A1 (en) 2012-10-24 application
KR20120106800A (en) 2012-09-26 application
WO2011075594A1 (en) 2011-06-23 application
US20110153913A1 (en) 2011-06-23 application