Source: http://www.google.com/patents/US7746393?dq=No.+6,411,949&ei=AUR7T-LGJqSr0AHy2aSiBg
Timestamp: 2016-05-02 22:54:43
Document Index: 591074593

Matched Legal Cases: ['Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006', 'Application No. 2006']

Patent US7746393 - Image signal processor and deficient pixel detection method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA deficiency candidate detection circuit detects a deficient pixel candidate by comparing the image signal of a target pixel with the image signals of peripheral pixels, and address information of the deficient pixel candidate is stored in a position memory circuit. A deficiency determining circuit repeats...http://www.google.com/patents/US7746393?utm_source=gb-gplus-sharePatent US7746393 - Image signal processor and deficient pixel detection methodAdvanced Patent SearchPublication numberUS7746393 B2Publication typeGrantApplication numberUS 11/426,759Publication dateJun 29, 2010Priority dateOct 27, 1999Fee statusPaidAlso published asCN1164083C, CN1295255A, US7092018, US7755680, US20060232691, US20060233431Publication number11426759, 426759, US 7746393 B2, US 7746393B2, US-B2-7746393, US7746393 B2, US7746393B2InventorsTohru WatanabeOriginal AssigneeSanyo Electric Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (26), Non-Patent Citations (11), Classifications (32), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetImage signal processor and deficient pixel detection method
US 7746393 B2Abstract
a deficiency candidate detection circuit for comparing the signal corresponding to the target pixel with a threshold value calculated from the signals corresponding to the plurality of peripheral pixels to detect a deficient pixel candidate and for generating a comparison result;
a deficiency determining circuit for determining a deficient pixel according to a continuity of the deficient pixel candidate based on a plurality of comparison results produced by the deficiency candidate detection circuit over the plurality of screens;
a position memory circuit for storing deficiency information for a position of the deficient pixel; and
wherein the position memory circuit comprises:
a first memory for temporarily storing position information for the deficient pixel and a result of detection by the deficiency candidate detection circuit; and
a non-volatile second memory for storing position information for the deficient pixel read from the first memory.
2. The image signal processor according to claim 1, wherein one of the first memory and the non-volatile second memory is configured to store a level of the deficient pixel and position information of the deficient pixel.
3. The image signal processor according to claim 2, wherein one of the first memory and the non-volatile second memory is configured to store, by priority, the level of the deficient pixel.
4. The image signal processor of claim 3, wherein the level of the deficient pixel exceeds a level, thereby indicating a highly-deficient pixel.
5. The image signal processor according to claim 1, wherein the deficiency determining circuit is configured to determine a deficient pixel for each of a plurality of areas of a screen.
6. The image signal processor according to claim 5, wherein the deficiency determining circuit is configured to determine a deficient pixel repeatedly in a time division multiplexed manner for each of the plurality of areas.
7. The image signal processor according to claim 1, wherein the deficiency determining circuit shares part of the deficiency candidate detection circuit.
8. The image signal processor of claim 1, wherein the deficiency candidate detection circuit is connected to the image memory circuit.
9. The image signal processor of claim 1, wherein the deficiency determining circuit is connected to the deficiency candidate detection circuit.
10. The image signal processor of claim 1, wherein the position memory circuit is connected to the deficiency determining circuit.
11. The image signal processor of claim 1, wherein the deficiency correction circuit is connected to the position memory circuit.
12. The image signal processor of claim 1, wherein:
the deficiency candidate detection circuit is connected to the image memory circuit;
the deficiency determining circuit is connected to the deficiency candidate detection circuit;
the position memory circuit is connected to the deficiency determining circuit; and
the deficiency correction circuit is connected to the position memory circuit. Description
This application is a divisional and claims the benefit of priority under 35 USC 120 of U.S. application Ser. No. 09/696,393, filed Oct. 25, 2000, now U.S. Pat. No. 7,092,081, issued Aug. 15, 2006. Under the 35 USC 119, the Ser. No. 09/696,393 application claims the benefit of three foreign priority applications filed in Japan, serial number 2000-282166, filed Sep. 18, 2000; serial number 11-305805, filed Oct. 27, 1999; serial number 11-307125, filed Oct. 28, 1999. The disclosure of the prior applications are considered part of and are incorporated by reference in the disclosure of this application.
The CCD image sensor 1 has a matrix of light receiving pixels (not shown) which store charges according to the received image of a subject. The CCD sensor 1 transfers charges stored in the individual light receiving pixels line by line in accordance with a vertical drive signal φV and a horizontal drive signal φH, and produces an image signal Y0 according to a predetermined format.
The deficiency correction circuit 5 adjusts the image signal Y1 using correction information stored in the correction information member 6. For instance, information of a deficient pixel is replaced with the average value of information of pixels before and after the deficient pixel.
The correction information member 6 stores the positions of deficient pixels of the CCD image sensor 1. For example, the positions of deficient pixels are detected by monitoring the output of the CCD image sensor 1 beforehand, and the detection result is stored as correction address information in the memory 6.
The number of deficient pixels in the CCD image sensor 1 may increase with time. When such time-dependent changes occur, the correction address information in the correction information member 6 should be rewritten. However, ordinary users of image pickup devices do not have means for rewriting the contents of the correction information memory 6. This makes it harder to rewrite the correction address information.
To achieve this objective, according to a first aspect of this invention, there is provided an image signal processor for processing a plurality of image signals. The image signal processor comprises an image memory circuit for storing a signal corresponding to a target pixel and signals corresponding to a plurality of peripheral pixels adjacent to the target pixel. The image signal processor further comprises a deficiency candidate detection circuit, connected to the image memory circuit, for comparing the signal of the target pixel with a threshold value set in accordance with the signals of the plurality of peripheral pixels to thereby detect a deficient pixel candidate. Also provided is a deficiency determining circuit, connected to the deficiency candidate detection circuit, for determining a deficient pixel according to continuity of the deficient pixel candidate, detected by the deficiency candidate detection circuit, over a plurality of screens. A position memory circuit, connected to the deficiency determining circuit, stores deficiency information of a position of the deficient pixels determined by the deficiency determining circuit. Finally, a deficiency correction circuit, connected to the position memory circuit, corrects the signal of the target pixel which is deficient in accordance with the deficiency information.
The deficiency candidate detection circuit 12 generates a first threshold value Lw for determining a white deficiency and a second threshold value Lb for determining a black deficiency from the image signals Y(P1) to Y(P8) of the peripheral pixels P1-P8 supplied from the image memory circuit 11. The deficiency candidate detection circuit 12 compares the first and second threshold value Lw and Lb with the image signal Y(P0) to detect a pixels which is a possible deficiency pixel (hereinafter referred to as “deficiency candidate”).
The deficiency determining circuit 14 determines whether a pixel corresponding to the address stored in the position memory circuit 13 is a real deficiency pixel or not, based on the continuity of a deficiency candidate over a plurality of screens. Specifically, when a deficient pixel is accidentally detected because of some reasons on the subject side, (i.e., related to the subject, the deficient pixels will not be detected after a certain time passes. When a deficient pixel is detected after a certain time passes. When a deficient pixel is detected continuously over a predetermined time period, therefore, the deficiency determining circuit 14 determines a real deficient pixel.
The deficiency correction circuit 16 replaces the image signal (Y(P0) of the deficient pixel with a correction signal Y(c) in accordance with the address information which is stored in the position memory circuit 13 by the deficiency registering circuit 15. The correction signal Y(c) is produced by, for example, averaging the image signals of a plurality of peripheral pixels located around the target pixel. As a result, the deficiency correction circuit 16 outputs an image signal Y′(n) with corrected white and black deficiencies.
The first threshold value Lw and second threshold value Lb that have been generated through the first to fifth steps S1-S5 are held fixed according to the conditions of the peripheral pixels.
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No. 11/426,754, through Jan. 21, 2009.2Action and Response History retrieved from PAIR for U.S. Appl. No. 11/426,754, through Jun. 23, 2009.3Amendment filed on Nov. 2, 2006 for Japanese Patent Application No. 2006-002720 with English translation, 4 pages, corresponding to U.S. Appl. No. 11/426,759.4Amendment filed on Nov. 2, 2006 for Japanese Patent Application No. 2006-002721 with English translation, 5 pages, corresponding to U.S. Appl. No. 11/426,754.5Amendment filed on Sep. 6, 2007 for Japanese Patent Application No. 2006-002721 with English translation, 5 pages, corresponding to U.S. Appl. No. 11/426,754.6Decision of Rejection dated Jul. 11, 2007 with English translation for counterpart Japanese Application No. 2006-002720, 4 pages, corresponding to U.S. Appl. No. 11/426,754.7Decision of Rejection dated Jul. 12, 2007 with English translation for counterpart Japanese Application No. 2006-002721, 4 pages, corresponding to U.S. Appl. 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No. 11/426,754.11Patent Abstracts of Japan, Publication No. 05-260385, Publication Date: Oct. 8, 1993, Title: "Defect Picture Element Detection Circuit for Solid-State Image Pickup Device".Classifications U.S. Classification348/247International ClassificationH04N5/367, H04N5/372, H04N5/378, H04N5/335, G06T1/00, H01L27/148, H04N5/21, G09G3/00, H01L21/66, H04N1/028, H04N5/14, H04N9/64, G06T7/00, G01R31/28, G06T5/00Cooperative ClassificationG06T5/20, G06T5/005, G09G2330/10, G09G3/006, G06T7/0002, H01L27/14806, H04N5/3675, H04N5/21, H04N5/367European ClassificationH04N5/367, H04N5/367A, G09G3/00E, G06T5/00D, G06T7/00B, H01L27/148A, H04N5/21Legal EventsDateCodeEventDescriptionJun 29, 2006ASAssignmentOwner name: SANYO ELECTRIC CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WATANABE, TOHRU;REEL/FRAME:017867/0271Effective date: 20001023Owner name: SANYO ELECTRIC CO., LTD.,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WATANABE, TOHRU;REEL/FRAME:017867/0271Effective date: 20001023Nov 9, 2010CCCertificate of correctionJul 14, 2011ASAssignmentOwner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANYO ELECTRIC CO., LTD.;REEL/FRAME:026594/0385Effective date: 20110101Nov 26, 2013FPAYFee paymentYear of fee payment: 4May 6, 2014ASAssignmentOwner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONAFree format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:SANYO ELECTRIC CO., LTD;REEL/FRAME:032836/0342Effective date: 20110101RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services