Source: https://patents.justia.com/patent/4864567
Timestamp: 2020-01-29 18:08:25
Document Index: 216728659

Matched Legal Cases: ['ART 24', 'ART 24', 'ART 24', 'ART 24', 'ART 24', 'ART 24', 'ART 28', 'ART 28', 'ART 24', 'ART 28', 'ART 28', 'ART 28', 'ART 24', 'ART 24', 'ART 24', 'ART 24', 'ART 24', 'ART 28', 'ART 24', 'ART 24', 'ART 24', 'ART 24', 'ART 28', 'ART 28', 'ART 28', 'ART 28', 'ART 24']

US Patent for High throughput data communication system Patent (Patent # 4,864,567 issued September 5, 1989) - Justia Patents Search
Justia Patents US Patent for High throughput data communication system Patent (Patent # 4,864,567)
High throughput data communication system
May 4, 1988 - The United States of America as represented by the Secretary of the Navy
This patent application is co-pending with related patent application entitled "High Speed Modem" by the same inventor filed on the same date as this patent application.
The present Invention describes a high through-put data communications system for sending and receiving data over telephone lines at through-put rates that exceed those of conventional systems.
The system is comprised of two multiline modems that connect to business type telephone lines. Each modem determines its number of available ("on-hook") telephone lines and communicates that information to the other multiline modem. Both modems utilize the maximum number of available telephone lines at both locations.
Data is transmitted and received using time multiplexing techniques over a plurality of telephone lines. Both modems connect to conventional Personal Computers (PC's) executing standard off-the-shelf telecommunications software.
The present day telephone network utilizes a number of transmission methods to "connect" one subscriber telephone to another. The local loop to the central office is the primary connection from the "originating" telephone to the "answering" telephone. Alternate transmission methods such as microwave links and special toll connecting trunks are used to carry voice information beyond the network capabilities of the central office. Since the local loop to the central office is the only actual physical or "wire" connection, transmission of digital or computer data over telephone lines must be in a form suitable with all elements in the telephone network.
The high through-put data communications system described herein transmits and receives data using conventional telephone lines at speeds that exceed those of prior art systems. The system is comprised of two multiline modems connected to business type telephone systems. Each modem determines its number of available telephone lines and transmits this information to the other modem. Both modems utilize the maximum number of available telephone lines at both locations.
An operator enters a telephone number to be dialed using a standard Personal Computer (PC). The PC transmits this information to a multiline modem which interprets this information and commences dialing. The modem at the answering location answers the originating modem by issuing a carrier signal. When the first or originating modem senses this carrier signal, it transmits to the answering modem its number of available telephone lines. The answering modem also transmits its number of available telephone lines to the originating modem. Both modems compare their number of available telephone lines, and if a difference occurs, the modems modify their digital representation of available lines so that both modems utilize the same number of lines.
If more than one line is available at both locations, originating multiline modem will begin re-dialing the telephone number using its next available telephone line. Since this modem and the answering modem are connected to a business or multiline telephone network, the telephone network at the receiving location will automatically transfer to its next available telephone line. The re-dialing sequence continues until all available telephone lines have been seized and successfully connected. The originating multiline modem issues a carrier detect to the PC when all lines are connected. Industry standard telecommunications software can be executed in both the originating and answering PC's.
Referring now to FIG. 1 there is shown a high throughput data communications system 10 having a first station 11a comprised of a multiline modem 10a connecting to an originating computer 12a by means of serial RS-232 input/output port 14a. A second station 11b has a multiline modem 10b connecting an answering computer 12b by means of serial RS-232 input/output port 14b. A telephone network 15 having a plurality of telephone lines 16a-n and 17a-n connects to respective multiline modems 10a and 10b. Each computer 12a and 12b contains industry standard software telecommunications programs. Either computer 12a or 12b can act as the originating computer. Likewise, either computer 12a or 12b can act as the answering computer. For the purpose of this invention description, computer 12a will be considered the originating computer and computer 12b will be considered the answering computer. If computer 12b is set as an originating device, then computer 12a would be set to produce an answer frequency even though it is the originating device. Industry standard command sets usually require that an "R" be placed at the end of the dial command from originating computer 12a. Multiline modems 10a and 10b are both connected to multiline business telephone network 15 that automatically transfers to the next available free telephone line 16a-n or 17a-n when the telephone network 15 senses a "busy" signal.
An operator using originating computer 12a and industry standard telecommunication commands enters a telephone number to be dialed. Computer 12a passes this information over serial I/O port 14a to multiline modem 10a. Multiline modem 10a interprets the dial command from originating computer 12a and using telephone line 16a, commences dialing. Multiline modem 10b, upon receipt of a ring signal on line 17a through network 15 "answers" the originating computer's multiline modem 10a by issuing a carrier signal. Multiline modem 10a, upon receipt of the carrier signal over line 16a from answering multiline modem 10b, signals to microprocessor 26 (shown in FIG. 3) that a valid carrier signal has been received. This condition places the first available telephone linein an on-line or "connect" state. Originating modem 10a, having determined the number of available telephone lines, transmits this information to answering modem 10b. Answering modem 10b, having determined its number of available telephone lines, transmits this information to originating modem 10a. Both modems 10a and 10b subsequently compare their number of available telephone lines with the number of available telephone lines received from the other modem. If a difference occurs, both modems 10a and 10b modify their digital representation of the number of telephone lines so that the originating and answering modems utilize the maximum number of telephone lines available at both stations. It is not necessary that both modems 10a and 10b utilize the same lines, only the same number of lines. Business or multiline telephone systems automatically transfer to the next available telephone line when a busy signal is encountered. Modem 10a can, for example, use lines 16a and 16c of a three line business telephone system if these are the only free lines. Modem 10b, on the other hand, would connect to modem 10a using lines 17a and 17b of a six line business telephone system if all of its six lines are free. As long as both modems 10a and 10b use the same number of telephone lines, the system will operate error free.
UART's 24 and 28a-n also contain a number of interface lines and handshaking signals. These lines form part of the bi-directional data bus 32, read/write line 34, chip and register select lines 40 and 36a-n, clear to send, request to send, carrier detect lines 42a-n and interrupt request lines 46 and 48a-n. Lines are provided for receive data 52a-n (line 20 for UART 24) and transmit data 56a-n (line 22 for UART 24). Whenever one of the UART's 24, 28a-n receives serial data over its receive data line, its receive data register is loaded with this data. Once full, the receive data register signals to microprocessor 26 through the UART's 24, 28a-n interrupt request line 46, 48a-n that a byte of data is available in the receive data register. The interrupt status bit in the status register is also set whenever the interrupt request line 46, 48a-n is actuated. Microprocessor 26 will acknowledge this interrupt request and first read the contents of the UART's 24, 28a-n status register to insure that carrier detect and other status conditions are present and that the receive data register full bit is set. (UART 24 does not connect to a modem. Hence, its request to send and clear to send lines are tied together. Additionally, microprocessor 26 does not check UART 24 for a carrier detect output). Once this has been verified, microprocessor 26 reads the contents of the receive data register and transfers this byte of information to a location determined by the program stored in ROM 60. Reading the receive data register clears the interrupt and receive full status bits in the UART's 24, 28a-n status register. UART's 28a-n automatically generate an interrupt request if the carrier detect control lines from one or all of modems 62a-n signal a loss of carrier detect.
Commands sent from originating computer 12a (FIG. 1) are interpreted by microprocessor 26 using routines contained in ROM 60. Industry standard "AT" type commands are supported allowing multiline modem system 10a to work with a variety of commercially available packages. Address decoders 172 and 156 decode the logical state of address bus 160 continuously and enable or disable sections of circuitry in modem 10 to work with the state data bus 32. Components within modem 10a are memory mapped to respond to the logical state of various address decoders pre-programmed in ROM 60. Random Access Memory (RAM) 174 is used to provide temporary storage of operator initiated parameters, such as the number dialed, the number of telephone lines available, and whether pulse or tone dialing will be used. Select line 176 from address decoder 172 is used to enable RAM 174. Select line 178 from address decoder 172 is used to enable ROM 60.
Data Access Arrangements (DAA) 66a-n are commercially available communications components that provide a direct connect telephone line interface. They are certified to meet hazardous voltage, surge, and leakage current requirements and meet FCC standards. These DAA's are generally used as the direct connect telephone line interface for most applications in which voice or data is to be transmitted and received over the public switched telephone network. DAA's contain ring detect signals 70a-n and modem control signals 74a-n such as answer phone, automatic/manual dial and carrier detect. DAA's 66a-n also contain input lines 80a-n for pulse or toe dialing connection to hybrid duplexers 88a-n. Lines 92a-n and 94a-n are the DAA lines for connection to the telephone tip and ring lines. These lines connect to balanced sense relays 100a-n which in turn connect to respective tip lines 104a-n and respective ring lines 106a-n of respective lines 16a-n.
Pulse/tone repertory dialer 78 is a monolithic IC that responds to commands from microprocessor 26. Pulse/tone dialer 78, when issued a telephone number from microprocessor 26, outputs either standard dual tone multi-frequency (DTMF) or pulse type signals. Once the telephone number is "dialed," microprocessor 26 need only issue a re-dial command to pulse/tone dialer 78 in order to re-dial the same number. Pulse/tone select line 140 is an output signal issued from I/O controller 142 during the command mode to select either pulse or tone dialing. Output lines 144 and 146 from pulse/tone dialer 78 output pulse or DTMF signals. Analog switch 148 selects pulse or tone dial outputs 144 or 146 by means of pulse/tone select line 140. The output 150 of analog switch 148 is fed to multiplexer/latch 152. Multiplexer/latch 152 is logically enabled via address decode line 154 from address decoder 156. Once enabled, multiplexer/latch 152 connects one of its output lines 80a-n to output line 150 of analog switch 148. The selection of lines 80a-n is done under microprocessor 26 control using data bus 32. Once the system has connected using the first available telephone line, both modems 10a and 10b pass information to each other indicating the number of available lines. Both modems 10a and 10b modify their digital representations so that the maximum number of available telephone lines are used. Microprocessor 26 then issues a re-dial command and energizes the proper select line on multiplexer/latch 152. Address decoder 156 also contains select line 158 which enables pulse/tone repertory dialer 78. Output lines 154 and 158 of address decoder 156 respond to the logical state of address bus 160 from microprocessor 26. Since data on data bus 32 is present for only a few microseconds, multiplexer/latch 152 incorporates a latching or holding circuit in order to stabilize output lines 80a-n.
Microprocessor 26 first checks the status of UART 24 by reading the contents of its status register. Microprocessor 26 then reads UART 24 receive data register by means of address decoder 172, data bus 32, and read/write (R/W) line 34. If receive data is present, microprocessor 26 transfers the contents of UART's 24 receive register to the first available UART 28a-n (UART 28a if available). If data is present in UART 24's receive data register, that data is transferred to the first available UART in the UART 28a-n configuration set by the telephone ID word and address sequencer 180. Microprocessor 26 next checks the status register of the first available UART 28a-n. If a carrier detect is noted, microprocessor 26 checks that UART's (one of UART 28a-n) receive data register. If the register is full, its contents are transferred to UART 24 transmit register. (A full condition in any one of UART's 28a-n indicates that the answering modem 10b has transmitted data to originating modem 10a). This data is now transmitted by UART 24 over line 22 through voltage translator 18 to receive line 14r of originating computer 12a. This process continues until all available UART's 28a-n are read and their data transferred to UART 24 transmit register. The operational sequence ceases when all available UART's 28a-n are checked. In the event of another interrupt signal over line 170 to microprocessor 26, the sequence begins again and UART 24 is checked again, followed by all available UART's 28a-n. If UART 24 contains data, its receive data register is full and the contents of that data register are transferred to the next available UART in the UART 28a-n configuration set by the telephone ID word in address sequencer 180. The sequence continues by checking all available UART's 28a-n and transferring any data in those UART's 28a-n to UART 24.
The alternate transfer or writing from UART 24 to UART's 28a-n is accomplished internal to multiline modem 10a by means of address sequencer 180. Address sequencer 180 alternately enables UART's 28a-n by setting enable lines 182a-n to the proper logic state. Address decoder 172, upon receiving a write or load command from microprocessor 26, changes the output state of address sequencer 180 so that UART's 28a-n are alternately loaded with incoming data from UART 24. This process of alternate writing or loading to UART's 28a-n is accomplished transparent to the PC telecommunications software program running in originating computer 12a. This alternate write sequence to UART's 28a-n results in UART's 28a handling the first incoming byte of data from UART 24, UART 28b handling the second byte, UART 28n handling the nth byte and UART 28a handling the nth+1 byte of data, etc. When these bytes of data are modulated by modems 62a-n, answering modem 10b (FIG. 1) receives byte number one first over telephone line 17a, byte number two over telephone line 17b, byte number n over telephone line 17n, etc. This sequence continues until the file transfer is complete. This alternate writing to UART's is dependent on the number of available telephone lines 16a-n. If any one of the telephone lines 16a- n is unavailable (i.e. offhook), address sequencer 180 must skip the UART's associated with the unavailable telephone lines 16a-n. The following paragraphs describe how the address sequencer 180 accomplishes this selective type of loading or writing.
Pulse 232, in addition to loading the first available UART 28a, also drives OR gate 228. The output 236 from OR gate 228 clocks counter 208 to the next state (001) which sets output line 212a from decoder 210 to a logic LOW. This condition also sets line 212b to a logic HIGH. Since output line 218 from shift register 206 is a logic LOW, output line 220 from inverter 222 is at a logic HIGH, and clock signal 234 is able to pass through AND gate 224. The output on line 226 from AND gate 224 is fed to OR gate 228. Select line 194 is now at a logic LOW, which enables OR gate 228. The clock pulse on line 234 therefore appears at line 236 which increments counter 208 to the next state (010). The clock pulse on line 226 also passes through OR gate 242 to line 238 which shifts contents of shift register 206 one more space to the right. The third telephone line ID bit now appears at output line 218 (logic HIGH). Since this line is now HIGH, a clock pulse on line 234 cannot pass through AND gate 224 and increment counter 208. The next output line in the 212a-n sequence from decoder 210 is now at a logic HIGH. When select line 194 sends pulse 232, telephone line 16c's UART (not shown) is now selected or loaded with data from UART 24 (FIG. 3). When pulse 232 goes to a logic LOW, counter 208 is incremented to state "100" and shift register 206 shifts one place to the right. Output line 218 is now at a logic LOW and a clock pulse on line 234 increments counter 208 and moves shift register 206 one more place to the right. This process continues until the logic HIGH is encountered at the output of shift register 206.
1. A high throughput data communications system for use in a communication system that transfers first and second data over an equal number of a first and second plurality of telephone lines having each member of said first plurality of telephone lines serially connected to a respective member of said second plurality of telephone lines comprising:
a first station comprising first sensing means for selecting first particular lines having a quantity equal to the maximum number of telephone lines available at both said first and second plurality of telephone lines;
a second station comprising second sensing means for selecting second particular lines having a quantity equal to the maximum number of telephone lines available at both said first and second plurality of telephone lines;
said first station further comprises first interfacing means for receiving and transmitting the first data at a first data rate, first separating means connected to said first interfacing means for separating said first data to form a first separated data, said first separated data being at a second data rate that is lower than said first data rate, first modulating means connected to said separating means through lines including said first particular lines, said first modulating means for receiving said first separated data over said first particular lines exclusively and for converting said first separated data to a first separated analog data, said first separated analog data being at said second data rate, first sending means connected to said first modulating means for transmitting said first separating analog data over said first and second plurality of telephone lines respectively;
said second station connected to said second plurality of telephone lines, said second station comprising first receiving means for receiving said first separated analog data, first demodulating means connected to said first receiving means for receiving said first separated analog data, said first demodulating means for converting said first separated analog data to said first separated data, said first separated data being at said second data rate, first combining means connected to said first demodulating means through lines including said second particular lines for receiving said first separated data over said second particular lines exclusively and for combining said first separated data to said first data, said first data being at said first data rate, and second interfacing means connected to said first combining means for receiving said first data and for transmitting said first data, third interfacing means for receiving and transmitting the second data at the first data rate, second separating means connected to said second interfacing means for separating said second data to form a second separated data, said second separated data being at said second data rate, second modulating means connected to said second separating means through lines including said second particular lines, said second modulating means for receiving said second separated data over said second particular lines exclusively and for converting said second separated data to a second separated analog data, said second separated analog data being at said second data rate, second sending means connected to said second modulating means for transmitting said second separated analog data over said second and first plurality of telephone lines respectively; and
said first station connected to said first plurality of telephone lines further comprising second receiving means for receiving said second separated analog data, second demodulating means connected to said second receiving means for receiving said second separated analog data, said second demodulating means for converting said second separated analog data to said second separated data, said second separated data being at said second data rate, second combining means connected to said second demodulating means through lines including said first particular lines for receiving said second separated data over said first particular lines exclusively and for combining said second separated data to said second data, said second data being at said first data rate, and fourth interfacing connected to said second combining means for receiving said second data and for transmitting said second data.
2. A high throughput data communication system according to claim 1 further comprising:
3. A high throughput data communication system according to claim 2 further comprising:
said first sensing means further includes first dialing means for dialing a telephone number over the first of said first plurality of telephone lines, first transmit means for transmitting said first word over the first of said available first plurality of telephone lines,
said second sensing means further includes second dialing means for dialing a telephone number over the first of said second plurality of telephone lines, second transmit means for transmitting said second word over the first of said available second plurality of telephone lines,
4. A high throughput data communication system according to claim 3 wherein each of said first and second sensing means further comprises:
5. A high throughput data communication system according to claim 4 further comprising:
6. A high throughput data communication system according to claim 5 wherein each of said sensing means further comprises:
7. A high throughput data communication system for use in a communication system that transfers first and second data over a first and second plurality of telephone lines comprising:
first and second sensing means for selecting particular communication paths within said plurality of communication paths, said particular communication paths having a quantity equal to the maximum number of telephone lines available at both said first and second plurality of telephone lines; and
full duplex communication means for transmitting and receiving said first and second data wherein the only communication paths utilized are said selected particular first and second communication paths.
4270202 May 26, 1981 Stuttard et al.
4383316 May 10, 1983 Seidel
4578796 March 25, 1986 Charalambous et al
4637035 January 13, 1987 Betts
4736388 April 5, 1988 Eguchi
4775987 October 4, 1988 Miller
Patent number: 4864567
Inventor: Paul J. Giorgio (Providence, RI)
Attorneys: Arthur A. McGill, Prithvi C. Lall, Michael J. McGowan
Application Number: 7/195,992
Current U.S. Class: 370/118; 370/112; 375/8; 375/38