Source: http://www.google.com/patents/US7691545?ie=ISO-8859-1
Timestamp: 2015-04-01 23:02:44
Document Index: 201955350

Matched Legal Cases: ['Application No. 10', 'Application No. 200410094884', 'Application No. 1020000011542', 'Application No. 1019990067846', 'Application No. 08', 'Application No. 11', 'Application No. 2002', 'Application No. 58']

Patent US7691545 - Crystallization mask, crystallization method, and method of manufacturing ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA crystallization mask for laser illumination for converting amorphous silicon into polysilicon is provided, which includes: a plurality of transmissive areas having a plurality of first slits for adjusting energy of the laser illumination passing through the mask; and an opaque area....http://www.google.com/patents/US7691545?utm_source=gb-gplus-sharePatent US7691545 - Crystallization mask, crystallization method, and method of manufacturing thin film transistor including crystallized semiconductorAdvanced Patent SearchPublication numberUS7691545 B2Publication typeGrantApplication numberUS 11/523,932Publication dateApr 6, 2010Filing dateSep 19, 2006Priority dateNov 19, 2003Fee statusPaidAlso published asCN1630027A, CN100568447C, US7223504, US20050151146, US20070015069Publication number11523932, 523932, US 7691545 B2, US 7691545B2, US-B2-7691545, US7691545 B2, US7691545B2InventorsSu-Gyeong Lee, Hyun-Jae Kim, Myung-Koo KangOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (13), Non-Patent Citations (8), Referenced by (1), Classifications (17), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetCrystallization mask, crystallization method, and method of manufacturing thin film transistor including crystallized semiconductor
US 7691545 B2Abstract
A crystallization mask for laser illumination for converting amorphous silicon into polysilicon is provided, which includes: a plurality of transmissive areas having a plurality of first slits for adjusting energy of the laser illumination passing through the mask; and an opaque area.
depositing a thin film of amorphous silicon on a substrate;
illuminating a first laser beam having a first energy onto local regions of the thin film to crystallize the thin film using a mask including first openings; and
illuminating a second laser beam having a second energy lower than the first energy onto the thin film to partly recrystallize the thin film using a mask including second openings, wherein a translucent film is disposed in the second openings.
2. The method of claim 1, wherein the crystallization and the recrystallization comprise sequential lateral solidification.
3. The method of claim 2, wherein the first openings and second openings are formed on a single mask.
4. The method of claim 3, wherein the first slits and the second slits have different widths.
5. The method of claim 4, wherein the first slits and the second slits are provided at different masks.
6. The method of claim 4, wherein the first slits and the second slits are provided at a single mask. Description
This application is a divisional of U.S. patent application Ser. No. 10/993,648, filed Nov. 19, 2004 now U.S. Pat. No. 7,223,504 by Su-Gyeong Lee, Hyun-Jae Kim, and Myung-Koo Kang, entitled �CRYSTALLIZATION MASK, CRYSTALLLIZATION METHOD, AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR INCLUDING CRYSTALLIZED SEMICONDUCTOR,� which claims priority of Korean Patent Application No. 10-2003-0082222 filed Nov. 19, 2003.
The present invention relates to a crystallization mask, a crystallization method, and a method of manufacturing a thin film transistor including crystallized semiconductor.
In general, an LCD includes two panels having field generating electrodes and a liquid crystal layer interposed therebetween. This LCD displays desired images by applying electric field using the electrodes to the liquid crystal layer with dielectric anisotropy and adjusting the strength of the electric field to control the amount of light passing through the panels. In this case, TFTs are used for controlling signals transmitted to the electrodes.
In order to overcome such a problem, an organic EL or a polysilicon TFT LCD using a polysilicon with electron mobility of 20 to 150 cm2/Vsec as a semiconductor layer has been developed. The relatively high electron mobility polysilicon TFT enables to implement a chip in glass technique that a display panel embeds its driving circuits.
In recent years, one of the most widely used methods of forming a polysilicon thin film on a glass substrate with a low melting point is an eximer laser annealing technique. The technique irradiates light with the wavelength, which can be absorbed by amorphous silicon, from an eximer laser into an amorphous silicon layer deposited on a substrate to melt the amorphous silicon layer at 1,400□, thereby crystallizing the amorphous silicon into polysilicon. The crystal grain has a relatively uniform size ranging about 3,000-5,000□, and the crystallization time is only about 30-200 nanoseconds, which does not damage the glass substrate. However, there are disadvantages that non-uniform grain boundaries decrease the uniformity for electrical characteristics between the TFTs and make it hard to adjust the microstructure of the grains.
To solve these problems, a sequential lateral solidification process capable of adjusting the distribution of the grain boundaries has been developed. The process is based on the fact that the grains of polysilicon at the boundary between a liquid phase region exposed to laser beam and a solid phase region not exposed to laser beam grow in a direction perpendicular to the boundary surface. A mask having a slit pattern is provided, and a laser beam passes through transmittance areas of the mask to completely melt amorphous silicon, thereby producing liquid phase regions arranged in a slit pattern. Thereafter, the melted amorphous silicon cools down to be crystallized, and the crystal growth starts from the boundaries of the solid phase regions not exposed to the laser beam, and proceeds in the directions perpendicular to the boundary surface. The grains stop growing when they encounter each other at the center of the liquid phase region. This process is repeated after moving the slit pattern of the mask in the direction of the grain growth, and thus the sequential lateral solidification covers the whole area. The sizes of the grains can be as much as the widths of the slit pattern.
After the sequential lateral solidification, protrusions of protuberances of about 400-1,000 Å are formed on the surface of the polysilicon layer along the grain boundaries. These causes stress on the boundary surface of a gate insulating layer to be formed on the semiconductor layer. The stress in this process is found to be ten times more than that in the eximer laser annealing, and this results in degrading the characteristics of the TFTs.
The transmissive areas may further have a plurality of second slits having width different from the first slits and substantially fully transmitting the laser illumination.
The first slits may include translucent films and the second slits are openings.
The width of the first slits may be smaller than the width of the second slits.
The second slits may be arranged to form a plurality of slit columns and the second slits in adjacent slit columns may be offset by a half of a pitch between the second slits.
A crystallization method is provided, which includes: depositing an thin film of amorphous silicon on a substrate; illuminating a first laser beam having a first energy onto local regions of the thin film to crystallize the thin film; and illuminating a second laser beam having a second energy lower than the firs energy onto the thin film to partly recrystallize the thin film.
The crystallization and the recrystallization may include sequential lateral solidification and the crystallization and the recrystallization use first and second slits, respectively.
The first slits may include openings and the second slits include translucent films and the first slits and the second slits may have different widths.
The first slits and the second slits may be provided at different masks or a single mask.
A method of manufacturing a thin film transistor is provided, which includes: forming an amorphous silicon thin film on an insulating substrate; forming a polysilicon thin film by locally irradiating the amorphous silicon thin film with a laser beam and crystallizing the amorphous silicon thin film; patterning the polysilicon thin film to form a semiconductor layer; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer opposite the semiconductor layer; implanting impurities into the semiconductor layer to form a source region and a drain region opposite each other with respect to the gate electrode; and forming a source electrode and a drain electrode electrically connected to the source region and the drain region, respectively.
The method may further include: forming an interlayer insulating layer between the gate electrodes and the source and the drain electrodes and having contact holes exposing the source and the drain regions; forming a passivation layer having a contact hole exposing the drain electrode; and forming a pixel electrode connected to the drain electrode via the contact hole.
The thin film transistor array panel may be used for a liquid crystal display or an organic light emitting display.
FIG. 1 is a schematic diagram showing a SLS process for crystallizing amorphous silicon into polysilicon;
FIG. 2 schematically shows illumination of laser beam through a mask having a slit in the SLS process;
FIGS. 3A-3C schematically show crystallization of amorphous silicon into polysilicon in the SLS process;
FIG. 4 is a detailed structure of a polycrystalline silicon thin film during crystallization from amorphous silicon to polycrystalline silicon in the sequential lateral solidification process;
FIG. 5 is a schematic view of a crystallization mask according to an embodiment of the present invention;
FIGS. 6A and 6B schematically illustrate the removal of the protrusions according to an embodiment of the present invention;
FIG. 7 is a plan view of a crystallization mask according to another embodiment of the present invention;
FIGS. 11, 13, 15, 17, 19, 21 and 23 are layout views of the TFT array panel shown in FIGS. 8-10 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention;
FIGS. 12A, 14A, 16A, 18A, 20A, 22A and 24A are sectional views of the TFT array panels shown in FIGS. 11, 13, 15, 17, 19, 21 and 23 taken along the lines XIIA-XIIA′, XIVA-XIVA′, XVIA-XVIA′, XVIIIA-XVIII′, XXA-XXA′, XXIIA-XXIIA′, and XXIVA-XXIVA′, respectively;
FIGS. 12B, 14B, 16B, 18B, 20B, 22B and 24B are sectional views of the TFT array panels shown in FIGS. 11, 13, 15, 17, 19, 21 and 23 taken along the lines XIIB-XIIB′, XIVB-XIVB′, XVIB-XVIB′, XVIIIB-XVIIIB′, XXB-XXB′, XXIIB-XXIIB′, and XXIVB-XXIVB′, respectively;
FIG. 25 is a layout view of a TFT array panel according to an embodiment of the present invention; and
FIG. 26 is a sectional view of the TFT array panel taken along the lines XXVI-XXVI′.
In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, film, region or substrate is referred to as being �on� another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being �directly on� another element, there are no intervening elements present.
Now, a crystallization mask and method and a method of manufacturing a polysilicon TFT according to embodiments of the present invention will be described with reference to accompanying drawings.
FIG. 1 is a schematic diagram showing a SLS process for crystallizing amorphous silicon into polysilicon, FIG. 2 schematically shows illumination of laser beam through a mask having a slit in the SLS process, FIGS. 3A-3C schematically show crystallization of amorphous silicon into polysilicon in the SLS process, and FIG. 4 is a detailed structure of a polycrystalline silicon thin film during crystallization from amorphous silicon to polycrystalline silicon in the sequential lateral solidification process.
As shown in FIGS. 2, in the SLS process, a laser beam is illuminated a semiconductor layer 200 made of amorphous silicon and formed on an insulating substrate 500 through a mask 300 having a plurality of transmissive areas 310 in form of slit.
The mask 300 includes a plurality of columns of slits 301 and 302 and each slit in the slit columns 301 and 302 is elongated in a transverse direction. The slits 301 and 302 in each column are arranged with a predetermined pitch, and the slits 301 and 302 in adjacent two columns are offset by about half of the pitch and extensions of the transverse edges of the slits 301 or 302 in a column pass through the slits 302 or 301 in the adjacent column.
Then, the amorphous silicon in a plurality of local regions in the semiconductor layer 200, which is illuminated by the laser beam, is completely melted such that a plurality of liquid phase regions 210 are formed in an area of the semiconductor 200 as shown in FIG. 3A.
At this time, a grain 230 of polycrystalline silicon grows from a boundary surface between a liquid phase region 210 exposed to the laser beam and a solid phase region 220 that does not experience the laser beam along a direction perpendicular to the boundary surface as shown in FIG. 3B. The grains 230 stop growing when they meet at the center of the liquid phase region. They are grown to have a various size of a desired degree by performing the step along the growing direction of the grains to continue the lateral growth of the grains.
The SLS process illustrated in FIG. 1 moves the substrate by a width of the column in the transverse direction (i.e., x direction) with respect to the mask 300 after irradiating laser beams through the mask (referred to as a shot). Since the slits 301 and 302 are elongated in the x direction, the grain growth proceeds in the y direction by a width of the slits 301 and 302 as shown in FIG. 4.
The movement of the substrate 500 is performed by a stage mounting the substrate while a laser irradiation device is fixed.
However, the poly-crystallized semiconductor layer 200 may have protrusions along the grain growth as shown in FIG. 3C. In order to remove the protrusions, a mask having means for adjusting the energy of the laser beam incident on the semiconductor layer 200 is used, which will be described in detail with reference FIGS. 5, 6A and 6B.
FIG. 5 is a schematic view of a crystallization mask according to an embodiment of the present invention, and FIGS. 6A and 6B schematically illustrate the removal of the protrusions according to an embodiment of the present invention.
Referring to FIG. 5, a crystallization mask 400 according to this embodiment includes a plurality of slits 410 including translucent films for adjusting the energy of the laser beam passing therethrough. The slits 410 are arranged in a column and elongated in a transverse direction. The slits 410 have a width smaller than those of the mask shown in FIG. 1, and they preferably have a width and an interdistance corresponding to the protrusions.
After the crystallization shown in FIGS. 3A-3C, a laser beam is illuminated again through the mask 400 shown in FIG. 5. The mask 400 moves in the transverse direction and it is aligned so that the slits 410 face the protrusions. Although the laser beam has an energy sufficient for fully melting the semiconductor layer 200, the translucent film in the slits 410 absorbs a part of the energy such that the semiconductor layer 200 is not fully melted. For example, upper portions of the semiconductor layer 200 are melted to form liquid phase regions 211, while lower portions thereof are not melted. Therefore, the protrusions are removed.
Referring to FIGS. 6B, the melted portions of the semiconductor layer 200 are recrystallized into polysilicon 231 and the grain growth also starts from the boundary in a perpendicular manner.
FIG. 7 is a plan view of a crystallization mask according to another embodiment of the present invention.
Referring to FIGS. 7 a mask 340 according to this embodiment includes a plurality of areas having different transmittance. That is, slits 310 shown in FIG. 1 and the slits 410 shown in FIG. 5 are formed in the mask.
When using the mask 430 shown in FIG. 7, the slits 310 is used for crystallization and the slits 410 is used for recrystallization. That is, the crystallization is performed using the slits 310 and thereafter, the protrusions are removed by using the slits 410 to recrystallize.
Now, a TFT array panel for OLED according to an embodiment of the present invention is described in detail with reference to FIGS. 8-10.
The gate conductors 121 and 124 b are preferably made of low resistivity material including Al containing metal such as Al and Al alloy (e.g. Al�Nd), Ag containing metal such as Ag and Ag alloy, and Cu containing metal such as Cu and Cu alloy. The gate conductors 121 and 124 b may have a multi-layered structure including two films having different physical characteristics. One of the two films is preferably made of low resistivity metal including Al containing metal, Ag containing metal, and Cu containing metal for reducing signal delay or voltage drop in the gate conductors 121 and 124 b. The other film is preferably made of material such as Cr, Mo and Mo alloy, Ta or Ti, which has good physical, chemical, and electrical contact characteristics with other materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). Good examples of the combination of the two films are a lower Cr film and an upper Al�Nd alloy film and a lower Al film and an upper Mo film.
A plurality of data conductors including a plurality of data lines 171, a plurality of voltage transmission lines 172, and a plurality of first and second drain electrodes 175 a and 175 b are formed on the interlayer insulating film 160. The data lines 171 for transmitting data signals extend substantially in the longitudinal direction and intersect the gate lines 121. Each data line 171 includes a plurality of first source electrodes 173 a connected to the first source regions 153 a through the contact holes 163 a. Each data line 171 may include an expanded end portion having a large area for contact with another layer or an external driving circuit. The data lines 171 may be directly connected to a data driving circuit for generating the gate signals, which may be integrated on the substrate 110.
The second drain electrodes 175 b are separated from the data lines 171 and the voltage transmission lines 172 and connected to the second drain regions 155 b through the contact holes 165 b. The data conductors 171, 172, 175 a and 175 b are preferably made of refractory metal including Cr, Mo, Ti, Ta or alloys thereof. They may have a multi-layered structure preferably including a low resistivity film and a good contact film. A good example of the multi-layered structure includes a Mo lower film, an Al middle film, and a Mo upper film as well as the above-described combinations of a Cr lower film and an Al�Nd upper film and an Al lower film and a Mo upper film.
The switching TFT Qa transmits data signals from the data line 171 to the driving TFT Qb in response to the gate signal from the gate line 121. Upon the receipt of the data signal, the driving TFT Qb generates a current having a magnitude depending on the voltage difference between the second gate electrode 124 b and the second source electrode 173 b. In addition, the voltage difference is charged in the storage capacitor Cst to be maintained after the switching TFT Qa is turned off. The current driven by the driving TFT Qb enters into the light emitting member 30 through the pixel electrode 190 and reaches the common electrode 270. The current flowing in the light emitting member 30 means that positive charge carriers such as holes and negative charge carriers such as electrons are injected into the light emitting member 30 from the anode 190 and the cathode 270, respectively, and they are drifted by an electric field generated by the voltage difference between the anode 190 and the cathode 270. The holes and the electrons in the light emitting member 30 then meet each other to be recombined into excitons, which emit light with a predetermined wavelength. The intensity of the emitted light depends on the current driven by the driving TFT Qb and flowing in the light emitting member 30. The emitted light goes out of the display panel after passing through the common electrode 270 or the pixel electrode 190. A transparent common electrode 270 and an opaque pixel electrode 190 are applicable to a top emission type EL display, which displays an image on its top surface. On the contrary, a transparent pixel electrode 190 and an opaque common electrode 270 are applicable to a bottom emission type EL display, which displays an image on its bottom surface.
Now, a method of manufacturing the TFT array panel shown in FIGS. 8-10 is described with reference to FIGS. 11-24B as well as FIGS. 8-10.
FIGS. 11, 13, 15, 17, 19, 21 and 23 are layout views of the TFT array panel shown in FIGS. 8-10 in intermediate steps of a manufacturing method thereof according to an embodiment of the present invention, FIGS. 12A, 14A, 16A, 18A, 20A, 22A and 24A are sectional views of the TFT array panels shown in FIGS. 11, 13, 15, 17, 19, 21 and 23 taken along the lines XIIA-XIIA′, XIVA-XIVA′, XVIA-XVIA′, XVIIIA-XVIIIA′, XXA-XXA′, XXIIA-XXIIA′, and XXIVA-XXIVA′, respectively, and FIGS. 12B, 14B, 16B, 18B, 20B, 22B and 24B are sectional views of the TFT array panels shown in FIGS. 11, 13, 15, 17, 19, 21 and 23 taken along the lines XIIB-XIIB′, XIVB-XIVB′, XVIB-XVIB′, XVIIIB-XVIIIB′, XXB-XXB′, XXIIB-XXIIB′, and XXIVB-XXIVB′, respectively.
A blocking layer 111 is formed on an insulating substrate 110, and a semiconductor layer made of amorphous silicon is deposited on the blocking layer 111 preferably by LPCVD (low temperature chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition) or sputtering.
The semiconductor layer is subjected to SLS with masks shown in FIG. 5 or 7 to be crystallized. As described above, the masks shown in FIGS. 5 and 7 can remove protrusions generated during the SLS.
Next, the semiconductor layer is photo-etched to form a plurality of pairs of first and second semiconductor islands 151 a and 151 b as shown in FIGS. 11-12B.
Referring to FIGS. 13-14B, a gate insulating layer 140 and a gate metal layer are sequentially deposited on the gate insulating layer 140 and a first photoresist PR1 is formed thereon. The gate metal layer is etched by using the first photoresist PR1 as an etch mask to form a plurality of gate electrodes 124 b including storage electrodes 137 and a plurality of gate metal members 120 a. P type impurity is introduced into portions of the second semiconductor islands 151 b, which are not covered with the gate electrodes 124 b and the gate metal members 120 a as well as the first photoresist PR1, to form a plurality of P type extrinsic regions 153 b and 155 b. At this time, the first semiconductor islands 151 a are covered with the first photoresist PR1 and the gate metal members 120 a to be protected from impurity implantation.
Referring to FIGS. 15-16B, the first photoresist PR1 is removed and a second photoresist PR2 is formed. The gate metal members 120 a is etched by using the second photoresist PR2 as an etch mask to form a plurality of gate lines 121 including gate electrodes 124 a. N type impurity is injected into portions of the first semiconductor islands 151 a, which are not covered with the gate lines 121 and the gate electrodes 124 b as well as the second photoresist PR2, to form a plurality of N type extrinsic regions 153 a and 155 a. At this time, the second semiconductor islands 151 b are covered with the second photoresist PR2 to be protected from impurity implantation.
Referring to FIGS. 17-18B, an interlayer insulating film 160 is deposited and the interlayer insulating film 160 and the gate insulating layer 140 are photo-etched form a plurality of contact holes 163 a, 163 b, 165 a and 165 b exposing the extrinsic regions 153 a, 155 a, 153 b and 155 b, respectively, as well as a plurality of contact holes 164 exposing the gate electrodes 124 b. Referring to FIGS. 19-20B, a plurality of data conductors including a plurality of data lines 171 including first source electrodes 173 a, a plurality of voltage transmission line 172, a plurality of first and second drain electrodes 175 a and 175 b are formed on the interlayer insulating layer 160.
Referring to FIGS. 21-22B, a passivation layer 180 is deposited and is photo-etched to form a plurality of contact holes 185 exposing the second drain electrodes 175 b. Referring to FIGS. 23-24B, a plurality of pixel electrodes 190 are formed on the passivation layer 180. When the pixel electrodes 190 are made of reflective opaque material, they may be formed of the data metal layer along with the data lines 171.
Referring to FIGS. 8-10, a photosensitive organic film containing black pigment is coated on the pixel electrodes 190 and the passivation layer 180, and it is exposed to light and developed to form a partition 32 defining a plurality of openings on the pixel electrodes 190. Thereafter, a plurality of organic light emitting members 30 are formed in the openings by deposition or inkjet printing following a masking. The organic light emitting member 30 preferably has a multi-layered structure.
Next, a buffer layer 34 and a common electrode 270 are sequentially formed.
An auxiliary electrode (not shown) preferably made of low resistivity material such as Al may be formed before or after the formation of the common electrode 270.
Now, a TFT array panel for an LCD according to an embodiment of the present invention will be described in detail with reference to FIGS. 25 and 26.
FIG. 25 is a layout view of a TFT array panel according to an embodiment of the present invention and FIG. 26 is a sectional view of the TFT array panel taken along the lines XXVI-XXVI′.
Referring to FIGS. 25 and 26, a layered structure of the TFT array panel according to this embodiment is similar to the TFT array panel for an OLED shown in FIGS. 8-10.
Different from the TFT array panel shown for an OLED in FIGS. 8-10, the TFT array panel for an LCD shown in FIGS. 25 and 26 includes no light emitting members 30, no partition 32, and no buffer layer 34. Instead, an LCD including the TFT array panel may include a liquid crystal layer (not shown) disposed between the pixel electrodes 190 and a common electrode (not shown).
Each semiconductor island 151 further include a storage region 158 without impurity and dummy regions 159 containing impurity like the source and the drain regions 153 and 155. The semiconductor island 151 further includes lightly doped regions 152 and 156 disposed between intrinsic regions 151 and 158 and extrinsic regions 153, 155 and 159 and having impurity concentration lower than the source and the drain regions 153 and 155.
In addition, the TFT array panel further includes a plurality of storage electrode lines 131 preferably made of the same layer as the gate lines 121 and extending substantially parallel to the gate lines 121. The storage electrode lines 131 include storage electrodes 135 overlapping the storage regions 158.
The pixel electrodes 190 supplied with data signals generate electric fields in cooperation with the common electrode, which determine orientations of liquid crystal molecules in the liquid crystal layer disposed therebetween. A pixel electrode 190 and a common electrode form a liquid crystal capacitor and a pixel electrode 190 and a drain region 155 connected thereto and a storage electrode line 131 including the storage electrodes 137 form a storage capacitor.
Many of the above-described features of the TFT array panel shown in FIGS. 8-24 may be appropriate to the TFT array panel shown in FIGS. 25 and 26.
In particular, the semiconductor islands 151 of the TFT array panel can be formed by SLS with masks shown in FIGS. 5 and 7.
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