Source: http://www.google.de/patents/US5543351
Timestamp: 2013-05-26 06:06:27
Document Index: 335207434

Matched Legal Cases: ['art 14', 'art 15', 'art 14', 'art 15', 'art 15', 'art 14', 'art 15', 'art 215', 'art 215', 'art 215', 'art 214', 'art 215']

Patent US5543351 - Method of producing electrically insulated silicon structure - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Webprotokoll | Anmelden Erweiterte Patentsuche PatenteA silicon substrate comprises at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, an electrically insulating layer formed by oxidizing the silicon substrate from...http://www.google.de/patents/US5543351?utm_source=gb-gplus-sharePatent US5543351 - Method of producing electrically insulated silicon structure Ver�ffentlichungsnummerUS5543351 APublikationstypErteilung Anmeldenummer08/331,733 Ver�ffentlichungsdatum6. Aug. 1996Eingetragen31. Okt. 1994 Priorit�tsdatum19. M�rz 1992Auch ver�ffentlicht unterUS5405454 ErfinderYoshihiko HiraiKiyoshi MorimotoMasaaki NiwaKenji OkadaYasuaki TeruiMasaharu UdagawaJuro YasuiKoichiro YukiUrspr�nglich Bevollm�chtigterMatsushita Electric Industrial Co., Ltd.New Energy And Industrial Technology Development Organization US-Klassifikation438/410438/701257/E21.404438/962257/E29.4Internationale KlassifikationH01L29/04H01L21/335 UnternehmensklassifikationH01L29/66439H01L29/045B82Y10/00 Europ�ische KlassifikationB82Y 10/00H01L 29/66M6T6DH01L 29/04BReferenzenPatentzitate (20)Nichtpatentzitate (10) Referenziert von (47)Externe LinksUSPTO USPTO-Zuordnung EspacenetMethod of producing electrically insulated silicon structureUS 5543351 A Zusammenfassung A silicon substrate comprises at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, an electrically insulating layer formed by oxidizing the silicon substrate from the surfaces, and an electrically conductive portion insulated electrically by the electrically insulating layer from an outside of the silicon substrate.
What is claimed is: 1. A method for producing a quantum portion of a silicon substrate insulated electrically from an outside of the silicon substrate, said method comprising: etching the silicon substrate to form at least two surfaces of the silicon substrate extending substantially along respective crystal faces of (111) crystal orientation of the silicon substrate, said at least two surfaces having a first flatness and a first linearity; and oxidizing a portion of the silicon substrate from the surfaces to form an electrically insulating layer, to form the quantum portion under the electrically insulating layer so that the electrically insulating layer insulates electrically the quantum portion of the silicon substrate from the outside of the silicon substrate and to form a boundary between the quantum portion and the electrically insulating layer, the boundary having a second flatness and a second linearity, at least one of the second flatness and the second linearity being superior to the first flatness or the first linearity.
2. A method according to claim 1, wherein a pre-formed surface of the silicon substrate extending in a direction substantially perpendicular to a crystal face of (100) crystal orientation of the silicon substrate under an etching-resistant layer is etched to form the surfaces, so that a constricted neck portion of the silicon substrate is formed by a join of the surfaces.
13. A method according to claim 1, wherein an etching-resistant layer is arranged on the silicon substrate before etching the silicon substrate, and an angular error of a side of the etching-resistant layer relative to an imaginary cross line of the crystal faces of (111) crystal orientation is within .+-.1 degree.
In a method as shown in FIGS. 2A-2D, firstly, an upper surface along a crystal face of (100) crystal orientation of a silicon substrate 10 with an impurity or without the impurity is thermally oxidated by a depth of about 100 nm in a dry oxygen gas of 90 thermally oxidated upper surface, a rectangular resist mask is formed by a photolithography process. Two opposed sides of the rectangular resist mask extend substantially parallel or perpendicular to the &lt;110&gt; direction of the silicon substrate 10, that is, substantially parallel to an imaginary cross line formed by crystal faces of (111) crystal orientation of the silicon substrate 10. An angular error of each of the opposed sides of the rectangular resist mask relative to the &lt;110&gt; direction or the imaginary cross line within .+-.1 degree can be permitted. The thermally oxidated upper surface with the rectangular resist mask thereon is etched in CF.sub.4 gas through a reactive ion etching process so that a part of the thermally oxidated upper surface on which the rectangular resist mask is arranged remains and another part of the thermally oxidated upper surface on which the rectangular resist mask is not arranged is removed by the etching to expose a new upper surface of the silicon Substrate 10. The part of the thermally oxidated upper surface on which the rectangular resist mask is arranged forms an etching-resistant layer 12 on the silicon substrate 10, as shown in FIG. 2A. When the electrically conductive or semi-conductive quantum dot or line is desired, a width of the etching-resistant layer 12 must be adjusted and checked accurately.
Subsequently, the new upper surface is etched and displaced through a silicon dry etching process, but, the silicon substrate 10 under the etching-resistant layer 12 is prevented from being etched through the silicon dry etching process by the etching-resistant layer 12, so that a difference in level of a boundary between the etching-resistant layer 12 and the silicon substrate 10 relative to the new upper surface after being etched and displaced is formed by 200 nm, and side walls 22 extending between the boundary and the new upper surface after being etched and displaced is formed, as shown in FIG. 2B. It is preferable for an angle 21 between each of the side walls 22 and the new upper surface after being etched and displaced to be 90 etching process using, for example, the reactive ion etching process, for obtaining the angle 21 of 90
A flow rate of (SiCl.sub.4) gas:a flow rate of (SF.sub.6) gas:a flow rate of (CH.sub.2 F.sub.2) gas:a flow rate of (O.sub.2) gas is 12:13:40:19, in an etching gas,
Even if the angle 21 of 90 the angle 21 to be more than 90
Subsequently, the new upper surface after being etched and displaced is further etched through a crystal anisotropic (wet chemical) etching process in which an etching rate or speed in a direction perpendicular to the crystal face of (111) crystal orientation of the silicon substrate 10 is about 1/100 of an etching rate or speed in a direction perpendicular to the crystal face of (110) crystal orientation of the silicon substrate 10 and of an etching rate or speed in a direction perpendicular to the crystal face of (100) crystal orientation of the silicon substrate 10 so that a surface along the crystal face of (111) crystal orientation of the silicon substrate 10 remains and the other surfaces along the crystal faces of &lt;110&gt; crystal orientation and (100) crystal orientation of the silicon substrate 10 does not remain on the silicon substrate 10, after the crystal anisotropy etching process. Therefore, side walls 13 extending along the crystal faces of 111 crystal orientation of the silicon substrate 10 crossing each other remain to form a constricted neck portion 20 with a width of 10 nm so that the silicon substrate 10 is divided to a main part 14 and a sub-part 15 by the constricted neck portion 20, as shown in FIG. 2C. When the angle 21 is 90 the side walls 13 along the crystal faces of 111 crystal orientation of the silicon substrate 10 crossing each other in the constricted neck portion 20 is positioned at a substantially central level of the above mentioned difference in level of the boundary between the etching-resistant layer 12 and the silicon substrate 10 relative to the new upper surface after being etched and displaced. An angle between each of the side walls 13 along the crystal faces of 111 crystal orientation and the boundary along the crystal faces of 100 crystal orientation between the etching-resistant layer 12 and the silicon substrate 10 is 54.7.degree..
When an etchant mixture for the crystal anisotropy etching in which a mole percentage of ethylenediamine (NH.sub.2 (CH.sub.2).sub.2 NH.sub.2) is 43.8%, a mole percentage of pyrocatechol (C.sub.6 H.sub.5 (OH.sub.8) is 4.2%, and a mole percentage of pure water (H.sub.2 O) is 52% is used and a temperature thereof is 100 direction perpendicular to the crystal face of 111 crystal orientation of the silicon substrate 10 is 7 nm/min, that is, about 1/40 of the etching rate or speed in the direction perpendicular to the crystal face of 110 crystal orientation of the silicon substrate 10 and of the etching rate or speed in the direction perpendicular to the crystal face of 100 crystal orientation of the silicon substrate 10. Therefore, a shape of the constricted neck portion 20, particularly the width thereof, can be accurately adjusted by controlling a time of the crystal anisotropic etching. A linearity and flatness of each of the side walls 13 are improved by the crystal anisotropy etching in the direction perpendicular to the crystal faces of 111 crystal orientation, and a crystal damage or defect of the silicon substrate 10 caused by the dry etching process is removed by the crystal anisotropy etching. Therefore, a crystalline structure in the main part 14 and the sub-part 15 is substantially perfect.
Finally, the etching-resistant layer 12 is removed by hydrofluoric acid, and the silicon substrate 10 is thermally oxidized by a depth of about 50 nm from the side walls 13 thereof in a dry oxygen gas of 900 form an oxidized layer 24 so that the constricted neck portion 20 is oxidized completely, an electrically conductive or semi-conductive portion 31 which is not oxidized to remain in the sub-part 15 is electrically separated and insulated from the main part 14, and a size of the electrically conductive or semi-conductive portion 31 which is not oxidized to remain in the sub-part 15 is minimized by the oxidation. Further, a flatness and linearity of a boundary between the oxidized layer 24 and the remaining electrically conductive or semi-conductive portion 31 are further improved in comparison with those of an outer shape of the side walls 13. An electrical potential barrier height of the oxidized layer 24 reaches about 3 eV.
Subsequently, while the etching-resistant layer 212 remains on the sub-part 215, the silicon substrate 10 is thermally oxidized from the side walls 213 thereof in the dry oxygen gas of 900 layer 224, so that an upper surface of the sub-part 215 is prevented from being oxidized by the silicon-nitride etching-resistant layer 212, the constricted neck portion 220 is oxidized completely, an electrically conductive or semi-conductive portion 231 which is not oxidized to remain in the sub-part 215 is electrically separated and insulated from the main part 214, and a size of the electrically conductive or semi-conductive portion 231 which is not oxidized to remain in the sub-part 215 is minimized by the oxidation, as shown in FIG. 4D. Further, a flatness and linearity of a boundary between the oxidized layer 224 and the remaining electrically conductive or semi-conductive portion 231 are further improved in comparison with those of an outer shape of the side walls 213.
Subsequently, a thin oxide gate layer 240 with a thickness of 10 nm is formed as shown in FIG. 4F, by oxidizing thermally an upper surface of the electrically conductive or semi-conductive portion 231 in the oxygen gas of 900 thickness of 500 nm is formed over the electrically conductive or semi-conductive portion 231 as shown in FIG. 4G, by sputtering.
In a method as shown in FIGS. 5A-5D, the present invention is applied to a semiconductor or insulator (SOI), whose structure is formed through a separation-by-implanted-oxygen (SIMOX) process. In the separation-by-implanted-oxygen process, after oxygen ions are inserted into a silicon substrate 310, by an ion implantation process with an oxygen ion dosing rate of 1.8 * 10.sup.18 cm.sup.-2 and an accelerating voltage of 200 keV while keeping a temperature of the silicon substrate 310 at 500 along a crystal face of 100 crystal orientation of the silicon substrate 310 with an impurity or without the impurity, the silicon substrate 310 is treated with heat in a temperature of 1300 that an embedded electrically insulating (silicon-oxide) layer 311 with a thickness of 0.4 μm is formed in the silicon substrate 310 and an upper silicon layer 320 of the silicon substrate 310 is electrically separated or insulated by the electrically insulating (silicon-oxide) layer 311 from the remaining portion of the silicon substrate 310, as shown in FIG. 5A. A thickness of the upper silicon layer 320 can be easily decreased to about 150 nm through a thermal oxidation and an etching process with a hydrofluoric acid.
Subsequently, the upper silicon layer 320 is thermally oxidated by a depth of about 100 nm in a dry oxygen gas of 900 thermally oxidated upper surface, a rectangular resist mask is formed by a photolithography process. Two opposed sides of the rectangular resist mask extend substantially parallel or perpendicular to the &lt;110&gt; direction of the silicon substrate 310, that is, substantially parallel to an imaginary cross line formed by crystal faces of (111) crystal orientation of the silicon substrate 310. An angular error of each of the opposed sides of the rectangular resist mask relative to the &lt;110&gt; direction or the imaginary cross line within .+-.1 degree can be permitted. The thermally oxidated upper surface with the rectangular resist mask thereon is etched in CF.sub.4 gas through the reactive ion etching process so that a part of the thermally oxidated upper surface on which the rectangular resist mask is arranged remains and another part of the thermally oxidated upper surface on which the rectangular resist mask is not arranged is removed by the etching to expose a new upper surface of the upper silicon layer 320. The part of the thermally oxidated upper surface on which the rectangular resist mask is arranged forms an etching-resistant layer 312 on the upper silicon layer 320, as shown in FIG. 5B. When the electrically conductive or semi-conductive quantum dot or wire is desired, a width of the etching-resistant layer 312 must be adjusted and checked accurately. An angular error of each of opposed sides of the etching-resistant layer 312 relative to the axis of 110 crystal orientation or the imaginary cross line is preferably maintained within .+-.1 degree.
Subsequently, the new upper surface of the upper silicon layer 320 with the etching-resistant layer 312 thereon is etched through an anisotropic etching process in which the electrically insulating (silicon-oxide) layer 311 is not etched, an etching rate or speed in a direction perpendicular to the crystal face of 111 crystal orientation of the silicon substrate 310 or upper silicon layer 320 is about 1/100 of an etching rate or speed in a direction perpendicular to the crystal face of 110 crystal orientation of the silicon substrate 310 or upper silicon layer 320 and of an etching rate or speed in a direction perpendicular to the crystal face of 100 crystal orientation of the silicon substrate 310 or upper silicon layer 320, so that a surface along the crystal face of 111 crystal orientation of the silicon substrate 310 or upper silicon layer 320 remains and the other surfaces along the crystal faces of 110 crystal orientation and 100 crystal orientation of the silicon substrate 310 do not remain on the silicon substrate 310 or electrically insulating (silicon-oxide) layer 311, after the crystal anisotropy etching process. Therefore, side walls 313 of a part of the upper silicon layer 320 extending along the crystal faces of 111 crystal orientation of the silicon substrate 310 or upper silicon layer 320 crossing each other under the etching-resistant layer 312 remains on the electrically insulating silicon-oxide layer 311 to form a trapezoidal portion 315 under the etching-resistant layer 312, as shown in FIG. 5C. An angle between each of the side walls 313 and the electrically insulating silicon-oxide layer 311 is 54.7.degree., and a height of the trapezoidal portion 315 is equal to a thickness of the upper silicon layer 320.
When an etchant mixture for the anisotropic etching in which a mole percentage of ethylene-diamine (NH.sub.2 (CH).sub.2 NH.sub.2) is 43.8%, a mole percentage of pyrocatechol (C.sub.6 H.sub.5 (OH.sub.8) is 4.2%, and a mole percentage of pure water (H.sub.2 O) is 52% is used and a temperature thereof is 100 perpendicular to the crystal face of 111 crystal orientation of the silicon substrate 10 is 7 nm/min, that is, about 1/40 of the etching rate or speed in the direction perpendicular to the crystal face of 110 crystal orientation of the silicon substrate 10 and of the etching rate or speed in the direction perpendicular to the crystal face of 100 crystal orientation of the silicon substrate 10. Therefore, a shape of the trapezoidal portion 315, particularly the width thereof, can be accurately adjusted by controlling a time of the anisotropic etching. A linearity and flatness of each of the side walls 313 are improved by the crystal anisotropic etching in the direction perpendicular to the crystal faces of 111 crystal orientation.
Finally, the etching-resistant layer 312 is removed by a hydrofluoric acid, and the trapezoidal portion 315 is thermally oxidized by a depth of about 20 nm from the side walls 313 thereof in a dry oxygen gas of 900 C. to form an oxidized layer 324 in the trapezoidal portion 315 to leave an electrically conductive or semi-conductive portion which is not oxidized to remain in the trapezoidal portion 315, and a size of the electrically conductive or semi-conductive portion which is not oxidized to remain in the trapezoidal portion 315 is minimized by the oxidation. Further, a flatness and linearity of a boundary between the oxidized layer 324 in the trapezoidal portion 315 and the remaining electrically conductive or semi-conductive portion in the trapezoidal portion 315 are further improved in comparison with those of an outer shape of the side walls 313. An electrical potential barrier height of the oxidized layer 324 reaches about 3 eV.
In a method as shown in FIGS. 6A-6D, a silicon substrate 410 is treated for 45 minutes with heat of 950 which (B.sub.2 H.sub.6) gas diluted to 1000 ppm with argon gas flows with a flow rate of 210 cm.sup.3 /min, oxygen gas flows with a flow rate of 13 cm.sup.3 /min and nitrogen gas flows with a flow rate of 1300 cm.sup.3 /min, so that an upper portion of the silicon substrate 410 is changed to a high-impurity-concentration P-channel layer 411. Subsequently, a boron glass formed on the high-impurity-concentration P-channel layer 411 during the above heat treatment is removed in a dark room by dilute hydrofluoric acid. Subsequently, a low temperature epitaxial growth of a low-impurity-concentration N-channel layer 420 by a thickness of about 150 nm on the high-impurity-concentration P-channel layer 411 is performed by a sputtering equipment in which a temperature of the silicon substrate 410 is about 300 V, RF power is 40 W, a target material is a monocrystalline silicone doped with phosphorus by about 10.sup.17 cm.sup.-3 and bias voltage for the target is 200 V, so that a sharp P-N junction is formed, as shown in FIG. 6A. In order to prevent the sharp P-N junction from being damaged, it is necessary for the silicon substrate 410 with the P-N junction to be treated under a low-temperature condition.
Subsequently, a silicon-oxide layer with a thickness of about 100 nm is formed over the low-impurity-concentration N-channel layer 420 in a temperature of 300 process. Subsequently, on the silicon-oxide layer over the low-impurity-concentration N-channel layer 420, a rectangular resist mask is formed by the photolithography process. Two opposed sides of the rectangular resist mask extend substantially parallel or perpendicular to the &lt;110&gt; direction of the low-impurity-concentration N-channel layer 420, that is, substantially parallel to an imaginary cross line formed by crystal faces of (111) crystal orientation of the low-impurity-concentration N-channel layer 420. An angular error of each of the opposed sides of the rectangular resist mask relative to the &lt;110&gt; direction or the imaginary cross line within .+-.1 degree can be permitted. The silicon-oxide layer with the rectangular resist mask thereon is etched in CF.sub.4 gas through the reactive ion etching process so that a part of the thermally oxidated upper surface on which the rectangular resist mask is arranged remains and another part of the thermally oxidated upper surface on which the rectangular resist mask is not arranged is removed by the etching to expose a new upper surface of the low-impurity-concentration N-channel layer 420. The part of the thermally oxidated upper surface on which the rectangular resist mask is arranged forms an etching-resistant layer 412 on the low-impurity-concentration N-channel layer 420, as shown in FIG. 6B. When the electrically conductive or semi-conductive quantum dot or wire is desired, a width of the etching-resistant layer 412 must be adjusted and checked accurately.
Subsequently, the new upper surface of the low-impurity-concentration N-channel layer 420 with the etching-resistant layer 412 thereon is etched through an anisotropic etching process in which the high-impurity concentration P-channel layer 411 with an impurity concentration of 10.sup.20 cm.sup.-3 is not etched, an etching rate or speed in a direction perpendicular to the crystal face of 111 crystal orientation of the low-impurity-concentration N-channel layer 420 is about 1/100 of the etching rate or speed in a direction perpendicular to the &lt;110&gt; direction of the low-impurity-concentration N-channel layer 420 and of an etching rate of speed in a direction perpendicular to the crystal face of (100) crystal orientation of the low-impurity-concentration N-channel layer 420, so that a surface along the crystal face of (111) crystal orientation of the low-impurity concentration N-channel layer 420 remains and the other surfaces along the crystal faces of (110) crystal orientation and (100) crystal orientation of the low-impurity-concentration N-channel layer 420 do not remain on the high-impurity-concentration P-channel layer 411, after the crystal anisotropic etching process. Therefore, side walls 413 of a part of the low-impurity-concentration N-channel layer 420 extending along the crystal faces of (111) crystal orientation of the low-impurity-concentration N-channel layer 420 crossing each other under the etching-resistant layer 412 remain on the high-impurity-concentration P-channel layer 411 to form a trapezoidal portion 415 under the etching-resistant layer 412, as shown in FIG. 6C. An angle between each of the side walls 413 and the high-impurity-concentration P-channel layer 411 is 54.7.degree., and a height of the trapezoidal portion 415 is equal to a thickness of the low-impurity-concentration N-channel layer 420.
When an etchant mixture for the anisotropic etching in which a mole percentage of ethylene-diamine NH.sub.2 (CH).sub.2 NH.sub.2) is 43.8%, a mole percentage of pyrocatechol (C.sub.6 H.sub.5 (OH).sub.8) is 4.2%, and a mole percentage of pure water (H.sub.2 O) is 52% is used and a temperature thereof is 100 direction perpendicular to the crystal face of 111 crystal orientation of the low-impurity-concentration N-channel layer 420 is 7 nm/min, that is, about 1/40 of the etching rate or speed in the direction perpendicular to the crystal face of 110 crystal orientation of the low-impurity-concentration N-channel layer 420 and of the etching rate or speed in the direction perpendicular to the crystal face of 100 crystal orientation of the low-impurity-concentration N-channel layer 420. Therefore, a shape of the trapezoidal portion 415, particularly the width thereof, can be accurately adjusted by controlling a time of the crystal anisotropic etching. A linearity and flatness of each of the side walls 413 are improved by the crystal anisotropic etching in the direction perpendicular to the crystal faces of 111 crystal orientation.
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Jan. 2007Brask, JustinSemiconductor device structures and methods of forming semiconductor structuresDrehenOriginalbildGoogle-Startseite - Sitemap - USPTO-Bulk-Downloads - Datenschutzerkl�rung - Nutzungsbedingungen - �ber Google Patente - Feedback gebenDaten bereitgestellt von IFI CLAIMS Patent Services.© 2012 Google