Source: http://www.google.com/patents/US8187412?dq=4393663
Timestamp: 2017-12-15 03:19:24
Document Index: 589738093

Matched Legal Cases: ['§120', 'Application No. 200803957', 'Application No. 200803929', 'Application No. 200803956', 'Application No. 200803957', 'Application No. 200803929', 'Application No. 200803956', 'Application No. 200803957']

Patent US8187412 - Apparatus for providing device with gaps for capacitance reduction - Google Patents
A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have...http://www.google.com/patents/US8187412?utm_source=gb-gplus-sharePatent US8187412 - Apparatus for providing device with gaps for capacitance reduction
Publication number US8187412 B2
Application number US 12/341,568
Also published as CN101317259A, CN101317259B, US7485581, US8866202, US20070123016, US20090140380, US20120205819, WO2007064501A1
Publication number 12341568, 341568, US 8187412 B2, US 8187412B2, US-B2-8187412, US8187412 B2, US8187412B2
Inventors S. M. Reza Sadjadi, Zhi-Song Huang
Original Assignee Lam Research Corporation;
Patent Citations (27), Non-Patent Citations (21), Referenced by (4), Classifications (18), Legal Events (1)
Apparatus for providing device with gaps for capacitance reduction
US 8187412 B2
1. An apparatus for reducing capacitances between semiconductor devices, comprising:
computer readable code for shrinking widths of mask features with sidewall deposition, comprising a plurality of cycles, wherein each cycle comprises:
2. The apparatus, as recited in claim 1, wherein the computer readable code for shrinking the widths of the mask features comprises computer readable code for shrinking the widths of the mask features by 5-80% and shaping the deposition on the sidewalls of the mask features to form vertical sidewalls.
3. The apparatus, as recited in claim 2, wherein the computer readable code for shrinking the widths of the mask features comprises providing 3 to 20 shrink cycles.
4. The apparatus, as recited in claim 3, wherein each gap has a volume and each pocket has a volume, wherein the volume of each pocket is at least half the volume of the gap in which the pocket is located.
5. The apparatus, as recited in claim 1, wherein the shrink deposition gas source comprises at least one of a hydrocarbon, fluorocarbon, and hydrofluorocarbon gas source and the shrink profile shaping gas source comprises at least one of a CxFy, NF3, and CxHyFz gas source.
6. The apparatus, as recited in claim 5, wherein the computer readable code for closing the gaps comprises a plurality of cycles, wherein each cycle comprises:
computer readable code for a bread loaf deposition phase; and
computer readable code for a bread loaf profile shaping phase.
7. The apparatus, as recited in claim 1, wherein the computer readable code for shrinking the widths of the mask features comprises providing 3 to 20 shrink cycles.
8. The apparatus, as recited in claim 1, wherein each gap has a volume and each pocket has a volume, wherein the volume of each pocket is at least half the volume of the gap in which the pocket is located.
9. An apparatus for reducing capacitances between semiconductor wirings with a plurality of contact structures formed in a dielectric layer on a substrate with a mask covering the contact structures, comprising:
a shrink gas source; and
a dielectric gap etch gas source; and
a gap closing gas source;
computer readable code for shrinking the widths of the mask features with sidewall deposition:
computer readable code for etching gaps into the dielectric layer through the sidewall deposition;
10. The apparatus, as recited in claim 9, wherein the computer readable code for shrinking the widths of the mask features, comprises:
computer readable code for flowing a shrink gas from the shrink gas source into the processing chamber;
computer readable code for forming a plasma from the shrink gas, that shrinks the widths of the mask features; and
computer readable code for stopping the flow of the shrink gas from the shrink gas source into the processing chamber;
wherein the computer readable code for etching gaps into the dielectric layer through the sidewall deposition, comprises:
computer readable code for flowing a dielectric gap etch gas from the dielectric gap etch gas source into the processing chamber;
computer readable code for forming a plasma from the dielectric gap etch gas, that etches gaps in the dielectric layer; and
computer readable code for stopping the flow of the dielectric gap etch gas from the dielectric gap etch gas source into the processing chamber; and
wherein the computer readable codes for closing the gaps to form pockets in the gaps, comprises:
computer readable code for flowing a gap closing gas from the gap closing gas source into the processing chamber;
computer readable code for forming a plasma from the gap closing gas, that closes gaps in the dielectric layer to form pockets; and
computer readable code for stopping the flow of the gap closing gas from the gap closing gas source into the processing chamber.
11. The apparatus, as recited in claim 10, wherein the computer readable code for shrinking the widths of the mask features comprises at least one shrink cycle, wherein each shrink cycle comprises:
12. The apparatus, as recited in claim 11, wherein the computer readable code for shrinking the widths of the mask features comprises providing 3 to 20 shrink cycles.
13. The apparatus, as recited in claim 11, wherein the shrink gas source comprises a shrink deposition gas source, which comprises at least one of a hydrocarbon, fluorocarbon, and hydrofluorocarbon gas source, and the shrink profile shaping gas source, which comprises at least one of a CxFy, NF3, and CxHyFz gas source.
14. The apparatus, as recited in claim 10, wherein each gap has a volume and each pocket has a volume, wherein the volume of each pocket is at least half the volume of the gap in which the pocket is located.
15. The apparatus, as recited in claim 10, wherein the computer readable code for shrinking the widths of the mask features comprises computer readable code for shrinking the widths of the mask features by 5-80% and shaping the deposition on the sidewalls of the mask features to form vertical sidewalls.
This application is a continuation of prior U.S. patent application Ser. No. 11/291,411 entitled “Device with Gaps for Capacitance Reduction”, filed on Nov. 30, 2005, now U.S. Pat. No. 7,485,581 issued on Feb. 3, 2009 by inventors Sadjadi et al., which is incorporated herein by reference and from which priority under 35 U.S.C. §120 is claimed.
FIG. 3 is a more detailed flow chart of the step of shrinking the mask features 214 (step 112). As shown in FIG. 3, the shrinking the mask features comprises a plurality of cycles of a cyclic process comprising a shrink deposition phase (step 304) and profile shaping phase (step 308). An example of a shrink deposition phase (step 304) provides a flow of 150 sccm CH3F, 75 sccm N2, and 100 sccm Ar. The pressure is set to 80 mTorr. The substrate is maintained at a temperature of 20° C. The second RF source 448 provides 400 Watts at a frequency of 27 MHz and 0 Watts a frequency of 2 MHz. During the deposition phase the deposition gas is provided, the deposition gas is transformed into a plasma, and then the deposition gas is stopped.
An example of a shrink deposition phase (step 304) provides a flow of 150 sccm CH3F, 75 sccm N2, and 100 sccm Ar. The pressure is set to 80 mTorr. The substrate is maintained at a temperature of 20° C. The second RF source 448 provides 400 Watts at a frequency of 27 MHz and 0 Watts a frequency of 2 MHz.
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U.S. Classification 156/345.26, 156/345.43, 118/723.00E
Cooperative Classification H01L21/76843, H01L21/0337, H01L21/7682, H01L21/76802, H01L21/31144, H01L21/0338, H01L23/4821, H01L2924/0002
European Classification H01L21/311D, H01L21/768B6, H01L21/033F6, H01L21/033F4