Source: http://www.google.com/patents/US6531022?ie=ISO-8859-1&dq=5754119
Timestamp: 2014-11-23 05:14:56
Document Index: 353796145

Matched Legal Cases: ['Art 1', 'art 1', 'Art 2', 'art 2', 'Art 3', 'art 3']

Patent US6531022 - Mounting method of semiconductor element - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA mounting method of a semiconductor element capable of joining an electrode of a semiconductor element and a circuit board at high reliability. The method includes a step of forming an external electrode terminal by filling a hole formed in circuit board with a conductive paste, a step of positioning...http://www.google.com/patents/US6531022?utm_source=gb-gplus-sharePatent US6531022 - Mounting method of semiconductor elementAdvanced Patent SearchPublication numberUS6531022 B1Publication typeGrantApplication numberUS 09/528,116Publication dateMar 11, 2003Filing dateMar 17, 2000Priority dateJun 7, 1996Fee statusLapsedAlso published asCN1110078C, CN1195422A, EP0844657A1, EP0844657A4, US6051093, WO1997047031A1Publication number09528116, 528116, US 6531022 B1, US 6531022B1, US-B1-6531022, US6531022 B1, US6531022B1InventorsNorihito TsukaharaOriginal AssigneeMatsushita Electric Industrial Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (14), Non-Patent Citations (4), Referenced by (50), Classifications (86), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMounting method of semiconductor elementUS 6531022 B1Abstract A mounting method of a semiconductor element capable of joining an electrode of a semiconductor element and a circuit board at high reliability. The method includes a step of forming an external electrode terminal by filling a hole formed in circuit board with a conductive paste, a step of positioning the external electrode terminal and a protruding bump formed on an electrode of a semiconductor, and a step of pressing the semiconductor element to contact between the conductive paste in the hole and the protruding bump thereby electrically connecting the electrode of the semiconductor element and the external electrode terminal of the circuit board. An adhesive sheet of a thermosetting resin, a thermoplastic resin, or a mixed thermosetting and thermoplastic resin may be disposed on the circuit board where the bump breaks through the sheet to contact the paste.
TECHNICAL FIELD The present invention relates to a mounting method of semiconductor element for mounting a flip chip type semiconductor element on a circuit board of semiconductor element at high reliability and high density.
BACKGROUND ART Conventional mounting methods of semiconductor element are described below by referring to the drawings.
(Prior Art 1) FIG. 16 is a sectional view of mounting a semiconductor element on a circuit board in prior art 1.
(Prior Art 2) FIG. 17 is a sectional view of mounting a semiconductor element on a circuit board in prior art 2. Same parts as in the constitution in FIG. 16 are identified with same reference numerals and their explanation is omitted.
(Prior Art 3) FIG. 18 is a sectional view of mounting a semiconductor element on a circuit board in prior art 3. Same parts as in the constitution in FIG. 16 and FIG. 17 are identified with same reference numerals and their explanation is omitted.
DISCLOSURE OF THE INVENTION To achieve the above object, the mounting method of semiconductor element of the invention comprises a step of forming a hole in a position of a circuit board for connecting a circuit of the circuit board and an electrode of a semiconductor element, a step of filling the hole with a conductive paste for forming an external electrode terminal, a step of forming a protruding bump on the electrode of the semiconductor element, a step of positioning the external electrode terminal and the protruding bump formed on the electrode of the semiconductor element, and a step of pressing the semiconductor element to contact between the conductive paste in the hole and the protruding bump, thereby electrically connecting the electrode of the semiconductor element and the external electrode terminal of the circuit board.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a junction sectional view of a semiconductor element and a circuit board after mounting in embodiment 1 of the invention.
BEST MODE FOR CARRYING OUT THE INVENTION The invention as set forth in the claims is a mounting method of semiconductor element comprising a step of forming a hole in a position of a circuit board for connecting a circuit of the circuit board and an electrode of a semiconductor element, a step of filling the hole with a conductive paste for forming an external electrode terminal, a step of forming a protruding bump on the electrode of the semiconductor element, a step of positioning the external electrode terminal and the protruding bump formed on the electrode of the semiconductor element, and a step of pressing the semiconductor element to contact between the conductive paste in the hole and the protruding bump, thereby electrically connecting the electrode of the semiconductor element and the external electrode terminal of the circuit board. According to this method, the protruding bump contacts with the conductive paste in the hole of the circuit board, and is electrically connected, and hence open state or short circuit does not occur.
(Embodiment 1) FIG. 1 is a sectional view of a circuit board mounting a semiconductor element in embodiment 1 of the invention.
(Embodiment 2) FIG. 5 is a process diagram showing a forming method of a protruding bump on an electrode of a semiconductor element by employing a wire bonding method according to embodiment 2 of the invention, and the wire bonding method is described below while referring to FIG. 5.
(Embodiment 3) A mounting method of semiconductor element in embodiment 3 of the invention is described below while referring to FIG. 9.
(Embodiment 4) A mounting method of semiconductor element in embodiment 4 of the invention is described below while referring to FIG. 10.
(Embodiment 5) A mounting method of semiconductor element in embodiment 5 of the invention is described below while referring to FIG. 11.
(Embodiment 6) A mounting method of semiconductor element in embodiment 6 of the invention is described below while referring to FIG. 12.
(Embodiment 7) A mounting method of semiconductor element in embodiment 7 of the invention is described below while referring to FIG. 14.
(Embodiment 8) A mounting method of semiconductor element in embodiment 8 of the invention is described below while referring to FIG. 15.
INDUSTRIAL APPLICABILITY Therefore, according to the invention, by bringing the protruding bump formed on the electrode of the semiconductor element into contact with the conductive paste in the hole in the circuit board, and connecting the electrode of the semiconductor element and the external electrode terminal of the circuit board electrically, a short circuit between electrodes can be avoided, and the tolerable range for warping and curving of the circuit board is wide, so that an open state between the electrodes can be avoided, and mounting of high electrical reliability is realized.
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KgCircuit board with at least one electronic componentUS7408258Feb 20, 2004Aug 5, 2008Salmon Technologies, LlcInterconnection circuit and electronic module utilizing sameUS7427809Dec 16, 2004Sep 23, 2008Salmon Technologies, LlcRepairable three-dimensional semiconductor subsystemUS7560813Jan 10, 2006Jul 14, 2009John TrezzaChip-based thermo-stackUS7586747 *Jul 27, 2006Sep 8, 2009Salmon Technologies, Llc.Scalable subsystem architecture having integrated cooling channelsUS7659202Mar 30, 2007Feb 9, 2010John TrezzaTriaxial through-chip connectionUS7670874Feb 16, 2007Mar 2, 2010John TrezzaPlated pillar package formationUS7687397Apr 5, 2007Mar 30, 2010John TrezzaFront-end processed wafer having through-chip connectionsUS7687400Mar 19, 2007Mar 30, 2010John TrezzaSide stacking apparatus and methodUS7737367 *Jan 25, 2006Jun 15, 2010Panasonic CorporationMultilayer circuit board and manufacturing method thereofUS7754976 *Apr 15, 2002Jul 13, 2010Hamilton Sundstrand CorporationCompact circuit carrier packageUS7767493Jan 10, 2006Aug 3, 2010John TrezzaPost & penetration interconnectionUS7781886Jan 10, 2006Aug 24, 2010John TrezzaElectronic chip contact structureUS7785931Jun 12, 2009Aug 31, 2010John TrezzaChip-based thermo-stackUS7785987Jan 30, 2009Aug 31, 2010John TrezzaIsolating chip-to-chip contactUS7786592Jan 10, 2006Aug 31, 2010John TrezzaChip capacitive couplingUS7789285 *Oct 17, 2007Sep 7, 2010Intel CorporationSolder printing process to reduce void formation in a microviaUS7793817 *Sep 6, 2007Sep 14, 2010Panasonic CorporationElectronic component placing apparatus and electronic component mounting methodUS7808111Nov 6, 2006Oct 5, 2010John TrezzaProcessed wafer viaUS7838997Jan 10, 2006Nov 23, 2010John TrezzaRemote chip attachmentUS7847412Jun 6, 2006Dec 7, 2010John TrezzaIsolating chip-to-chip contactUS7851348Jan 10, 2006Dec 14, 2010Abhay MisraRoutingless chip architectureUS7884483Jan 10, 2006Feb 8, 2011Cufer Asset Ltd. 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L.L.C.Electrically conductive interconnect system and methodUS8154131Jan 10, 2006Apr 10, 2012Cufer Asset Ltd. L.L.C.Profiled contactUS8197626Apr 14, 2011Jun 12, 2012Cufer Asset Ltd. L.L.C.Rigid-backed, membrane-based chip toolingUS8197627Apr 15, 2011Jun 12, 2012Cufer Asset Ltd. L.L.C.Pin-type chip toolingUS8232194Oct 14, 2011Jul 31, 2012Cufer Asset Ltd. L.L.C.Process for chip capacitive couplingUS8283778Feb 16, 2007Oct 9, 2012Cufer Asset Ltd. L.L.C.Thermally balanced viaUS8341833 *Oct 23, 2008Jan 1, 2013Alps Electric Co., Ltd.Method for manufacturing printed wiring boardUS8410615 *Jul 7, 2011Apr 2, 2013Hitachi, Ltd.Semiconductor device and method for manufacturing the sameUS8456015Jan 6, 2010Jun 4, 2013Cufer Asset Ltd. L.L.C.Triaxial through-chip connectionUS20090090004 *Oct 23, 2008Apr 9, 2009Alps Electric Co., Ltd.Method for manufacturing printed wiring boardUS20110005822 *Oct 19, 2007Jan 13, 2011Yuuki MomokawaStructure of a package for electronic devices and method for manufacturing the packageUS20120068355 *Jul 7, 2011Mar 22, 2012Hitachi, Ltd.Semiconductor device and method for manufacturing the same* Cited by examinerClassifications U.S. Classification156/256, 257/793, 257/E23.021, 29/832, 156/298, 174/258, 427/96.9, 427/97.5, 427/97.2, 29/852, 257/E21.503, 156/306.6, 228/180.22, 156/306.9, 257/774, 156/299, 438/119, 257/506, 174/255, 156/261, 174/262, 257/E23.067, 174/260, 156/305, 156/273.5International ClassificationH01L21/60, H05K3/40, H01L23/485, H05K1/00, H05K3/32, H05K1/11, H01L23/498, H01L21/56Cooperative ClassificationH01L24/29, H01L2224/32225, H01L2224/73204, H01L24/83, H01L24/743, H01L24/75, H01L2224/75251, H01L2224/1134, H01L2224/13124, H01L2924/01006, H01L2224/75252, H01L2924/3511, H01L2924/01082, H01L2224/92225, H01L2224/16225, H01L2924/01033, H01L2224/13144, H05K1/113, H05K1/0393, H01L2224/16237, H01L2224/83101, H01L2924/01004, H01L2224/73203, H05K2201/10977, H05K2201/0367, H01L2924/01078, H05K2201/10674, H01L2924/01079, H01L2924/01005, H01L2224/92125, H01L2924/01029, H01L23/49827, H05K3/4069, H05K2203/1189, H01L2924/00013, H01L2924/01013, H01L24/10, H01L2224/13147, H01L2224/131, H01L21/563, H01L2224/83102, H01L2924/014, H01L2224/83192, H05K3/321, H01L2924/01047, H01L2224/16235, H01L2224/29298European ClassificationH01L24/10, H01L24/28, H05K1/11C2A, H01L23/498E, H05K3/32B, H01L21/56FLegal EventsDateCodeEventDescriptionMay 3, 2011FPExpired due to failure to pay maintenance feeEffective date: 20110311Mar 11, 2011LAPSLapse for failure to pay maintenance feesOct 18, 2010REMIMaintenance fee reminder mailedAug 18, 2006FPAYFee paymentYear of fee payment: 4Sep 16, 2003CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google