Source: http://www.google.com/patents/US6614083?dq=inventor:%22Arthur+R.+Hair%22
Timestamp: 2016-06-25 04:22:50
Document Index: 679907705

Matched Legal Cases: ['application No. 10', 'application No. 11', 'application No. 5', 'application No. 7', 'application No. 7', 'application No. 8', 'application No. 5', 'application No. 95']

Patent US6614083 - Wiring material and a semiconductor device having wiring using the material ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the electrode in doping of an impurity ion....http://www.google.com/patents/US6614083?utm_source=gb-gplus-sharePatent US6614083 - Wiring material and a semiconductor device having wiring using the material, and the manufacturing methodAdvanced Patent SearchPublication numberUS6614083 B1Publication typeGrantApplication numberUS 09/527,437Publication dateSep 2, 2003Filing dateMar 16, 2000Priority dateMar 17, 1999Fee statusPaidAlso published asUS7189604, US7411259, US7663238, US20040021183, US20070222075, US20080296578Publication number09527437, 527437, US 6614083 B1, US 6614083B1, US-B1-6614083, US6614083 B1, US6614083B1InventorsShunpei Yamazaki, Toru TakayamaOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (19), Non-Patent Citations (12), Referenced by (26), Classifications (32), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetWiring material and a semiconductor device having wiring using the material, and the manufacturing method
US 6614083 B1Abstract
What is claimed is: 1. A wiring comprising tungsten as its main component, wherein the wiring contains oxygen in 30 parts per million or less, and argon.
2. A wiring according to claim 1 wherein electric resistivity of the wiring is 40 μΩ�cm or less.
3. A semiconductor device having a wiring comprising tungsten as its main component, wherein the wiring contains oxygen in 30 parts per million or less, and argon.
4. A semiconductor device according to claim 3 wherein electric resistivity of the wiring is 40 μΩ�cm or less.
5. A semiconductor device having a wiring, the wiring comprising:
a first conductive film comprising tungsten on an insulating surface; and a second conductive film comprising tungsten nitride in contact with the first conductive film, wherein the wiring contains argon, and contains oxygen at 30 parts per million or less. 6. A semiconductor device according to claim 5 wherein stress of the first conductive film is −5�109 or over, and 5�109 dyn/cm2 or less.
7. A semiconductor device according to claim 5 wherein a width of the wiring is 5 μm or less.
8. A semiconductor device according to claim 5 wherein a thickness of the wiring is 0.1 to 0.7 μm.
9. A semiconductor device according to claim 5 wherein the wiring is used as a gate wiring of a TFT.
10. A semiconductor device according to claim 5 wherein the semiconductor device has a display device selected from the group consisting of an active matrix liquid crystal display, an active matrix EL display and an active matrix EC display.
11. A semiconductor device according to claim 5 wherein the semiconductor device is one selected from the group consisting of: video camera, digital camera, projector, goggle type display, car navigation system, a personal computer and a portable information terminal.
12. A semiconductor device having a wiring on an insulating surface, the wiring comprising:
a first conductive film comprising tungsten nitride; a second conductive film comprising tungsten; a third conductive film comprising tungsten nitride on a surface of the first conductive film, wherein the wiring contains argon, and contains oxygen at 30 parts per million or less. 13. A semiconductor device according to claim 12 wherein stress of the tungsten film is −5�109 or over, and 5�109 dyn/cm2 or less.
14. A semiconductor device according to claim 12 wherein a width of the wiring is 5 μm or less.
15. A semiconductor device according to claim 12 wherein a thickness of the wiring is 0.1 to 0.7 μm.
16. A semiconductor device according to claim 12 wherein the wiring is used as a gate wiring of a TFT.
17. A semiconductor device according to claim 12 wherein the semiconductor device has a display device selected from the group consisting of an active matrix liquid crystal display, an active matrix EL display and an active matrix EC display.
18. A semiconductor device according to claim 12 wherein the semiconductor device is one selected from the group consisting of: video camera, digital camera, projector, goggle type display, car navigation system, a personal computer and a portable information terminal.
at least one TFT over a substrate; and at least one wiring connected with the TFT over the substrate, wherein the wiring comprises tungsten, oxygen in 30 parts per million or less, and argon. 20. A semiconductor device according to claim 19 wherein electric resistivity of the wiring is 40 μΩ�cm or less.
21. A semiconductor device according to claim 19 wherein the wiring is used as a gate wiring of the TFT.
22. A semiconductor device according to claim 19 wherein the wiring is used as a source wiring of the TFT.
23. A semiconductor device according to claim 19 wherein the wiring is used as a drain wiring of the TFT.
24. A semiconductor device according to claim 19 wherein an active layer of the TFT has at least one LDD region.
25. A semiconductor device according to claim 19 wherein the semiconductor device comprises a display device selected from the group consisting of an active matrix liquid crystal display, an active matrix EL display, and an active matrix EC display.
26. A semiconductor device according to claim 19 wherein the semiconductor device is one selected from the group consisting of: video camera, digital camera, projector, goggle type display, car navigation system, a personal computer and a portable information terminal.
at least one TFT over a substrate; and at least one wiring connected with the TFT over the substrate, wherein the wiring comprises a first conductive film comprising tungsten and a second conductive film comprising tungsten nitride, and wherein the wiring includes argon and oxygen in 30 parts per million or less. 28. A semiconductor device according to claim 27 wherein the wiring comprises first, second, and third films and wherein the first and third films comprise tungsten nitride and the second film comprises tungsten.
29. A semiconductor device according to claim 27 wherein stress of the first conductive film is −5�109 or over, and 5�109 dyn/cm2 or less.
30. A semiconductor device according to claim 27 wherein a width of the wiring is 5 μm or less.
31. A semiconductor device according to claim 27 wherein a thickness of the wiring is 0.1 to 0.7 μm.
32. A semiconductor device according to claim 27 wherein the wiring is used as a gate wiring of the TFT.
33. A semiconductor device according to claim 27 wherein the wiring is used as a source wiring of the TFT.
34. A semiconductor device according to claim 27 wherein the wiring is used as a drain wiring of the TFT.
35. A semiconductor device according to claim 27 wherein an active layer of the TFT has at least one LDD region.
36. A semiconductor device according to claim 27 wherein the semiconductor device comprises a display device selected from the group consisting of an active matrix liquid crystal display, an active matrix EL display, and an active matrix EC display.
37. A semiconductor device according to claim 27 wherein the semiconductor device is one selected from the group consisting of: video camera, digital camera, projector, goggle type display, car navigation system, a personal computer and a portable information terminal.
In order to solve the above stated objects, the present invention uses a target comprising highly purified high melting point metal, and provides a high melting point metal film obtained by sputtering for the wiring material. Specifically, the use of tungsten (W) as the high melting point metal is one of the characteristics of the present invention. In addition, as other high melting point metals., molybdenum (Mo), tantalum (Ta), chromium (Cr), niobium (Nb) or vanadium (V) may be used. Further, a eutectic alloy (molybdenum-tantalum alloy) with such other high melting point metals (molybdenum etc.) may be used.
A high melting point metal film (tungsten) obtained as such includes scarce impurity elements, typically, amount of oxygen included could be reduced to no more than 30 parts per million (ppm), and an electric resistivity of 20 mW cm or less, typically 6-15 mW cm could be obtained. The stress of the film was −5�109−5�109 dyn/cm2.
High melting point metals are not resistant against oxidation in general, and they are easily oxidized in a heat treatment in an atmosphere in the existence of remaining oxygen of few ppm. As a result, increase in the electric resistiity and film peeling may occur. Further, introduction of trace impurity element contained in the reactive gas into the high melting point metal at ion doping, such as oxygen may also increase the electric resistivity.
FIG. 25 shows a result of measuring the number of pin holes by surface inspecting apparatus (manufactured by Hitachi, GI-4600) per 100 mm2 of a laminated films comprising under layer WNx (film thickness 30 nm) and upper layer W (thickness 120 nm) formed over a quartz substrate (127 mm�127 mm) after treating under conditions 1 through 4 shown below: Condition 1) After plasma nitrification treatment using ammonia gas and formation of silicon nitride film (film thickness 25 nm), heat treatment (550� C., 4 hours) Condition 2) After formation of silicon nitride film (thickness 25 nm), heat treatment (550� C., 4 hours)
Condition 3) After forming silicon nitride film (thickness 25 nm), silicon nitride oxide film is formed (thickness 200 nm) and heat treatment (550� C., 4 hours) Condition 4) silicon nitride oxide film is formed (thickness 200 nm) and heat treatment (550� C., 4 hours)
WN sputtering
T-S (mm)
Further, according to another structure of the present invention a semiconductor device that has at least a pixel matrix circuit and driver circuit on a same substrate is characterized by:
According to still another structure of the present invention the manufacturing method for semiconductor device that includes at least a pixel matrix circuit and a driver circuit, is characterized by comprising the steps of:
The embodiment mode of the present invention is explained in detail by the
Embodiments shown below.
A semiconductor film containing crystalline structure (crystalline silicon film in the present embodiment) 102 is formed according to a technology disclosed in the Japanese Patent Application Laid-Open No. Hei 7-130652 (corresponding to U.S. Pat. No. 5,643,826). The technology described in the gazette is the crystallization means that uses catalytic elements for promoting crystallization (one or plural of element selected from nickel, cobalt, germanium, tin, lead palladium, iron and copper; typically nickel) for crystallizing the amorphous silicon film.
More concretely, heat-treatment is conducted under the condition where the catalytic element(s) is held on the surface of the amorphous silicon film to convert the amorphous silicon film to the crystalline silicon film. Although the present Embodiment uses a technology described in the Embodiment 1 of the gazette a technology described in Embodiment 2 may also be used. Though single crystal silicon film and polycrystalline silicon film are both included in crystalline silicon film, the crystalline silicon film formed in the present embodiment is a silicon film having crystal grain boundaries.
By this process impurity region 106 including p-type impurity (boron in the present embodiment) at a concentration of 1�1015-1�1018 atoms/cm3 (typically 5�1016-5�1017 atoms/cm3) was formed. In the present specification, an impurity region containing p-type impurity region at least in the above stated concentration range is defined as a p-type impurity region (b). (FIG. 1C)
Next resist mask 105 is removed and resist masks 107-110 are newly formed. Then impurity regions imparting n-type 111-113 are formed by doping impurity element s imparting n-type (hereinafter referred to as n-type impurity element). As an n-type impurity element, typically an element belonging to group 15 or more specifically phosphorus or arsenic may be used. (FIG. 1D)
Then, p-type impurity element (boron in the present embodiment) is doped with resist masks 123-125 provided, and impurity regions 126 and 127 that include boron at a high concentration are formed. These resist masks 123-125 play a role of preventing the resistivity from increasing by introduction of impurity specifically oxygen into the high melting point metal film in p-type impurity element doping process. Here, boron is doped at a concentration of 3�102-3�1021 atoms/cm3 (typically 5�1020-1�1021 atoms/cm3) by ion doping using diborane (B2H6). In the present specification, an impurity region that includes p-type impurity region in the above stated concentration range is defined as p-type impurity region (a). (FIG. 2D) Needless to say, the impurity region may also be formed by doping into exposed active layer by etching the gate insulating film.
Further, n-type impurity element (phosphorus in embodiment 1) is doped in a self-aligned manner using resist masks 131 to 135 as masks with the masks left as they are. These resist masks 131 to 135 function to prevent increase in resistivity due to added impurity specifically oxygen into high melting point metal in the process of n-type impurity element doping. It is also acceptable to form impurity regions by doping with exposing active layer by etching the gate insulating film. The phosphorus doped into thus formed impurity regions 136 to 139 are set at a concentration of � to {fraction (1/10)} (specifically ⅓ to �) of the n-type impurity region (b) (provided it is higher by 5 to 10 times than boron concentration added in the channel doping process, specifically 1�1016 to 5�1018 atoms/cm3, typically 3�1017 to 3�1018). In the present Specification, an impurity region containing n-type impurity element at the above stated concentration range is defined as n-type impurity region (c). (FIG. 3A)
After resist masks 131 to 135 and 140 to 142 are removed, an insulating film 151 which will form a part of the first interlayer insulating film is formed. Insulating film 151 may be formed from a silicon nitride film, a silicon oxide film, an oxidized silicon nitride film or a laminate combining these films. The film thickness may be set at 0.1 to 0.4 μm. In embodiment 1, an oxidized silicon nitride film (provided nitrogen concentration is 25 to 50 atom %) of 0.3 μm thick formed by plasma CVD using Si H4, N2O and NH3 as raw material gases is used.
The catalytic element (nickel in embodiment 1) used in crystallization of an amorphous silicon film moved in the direction of the arrows and is captured in a region containing phosphorus at a high concentration (gettering) formed in the process of FIG. 3B. This is a phenomenon originated from Bettering effect of a metal element by phosphorus. As a result, the concentration of nickel contained in channel forming regions 152 to 156 is reduced below 1�1017 atoms/cm3 (preferably to 1�1016 atoms/cm3).
The voltage between the cathode and the anode in the solution changes along with time in accordance with the oxide film growth. The voltage is regulated by an increasing rate of 100 V/min with the current kept at constant, and the process is stopped when the voltage becomes 45 V. Thus the anodic oxide film 169 can be formed with a thickness of approximately 50 nm on the surface of shielding film 168. As a result the thickness of shielding film 168 became 90 nm. Note that the numerical values shown here for the anodic oxidation process are only examples, and that they may naturally be changed to the most suitable values depending upon the size of the element being manufactured, etc.
Further, a channel forming region 204, a source region 205, and a drain region 206 are formed in the n-channel TFT 302, and a region overlapping with the gate wiring by interposing a gate insulating film (such region is referred to as Lov region. ‘ov’ means overlap) 207 is formed in one side of the channel forming region (drain region side). Here, Lov region 207 contains phosphorus at a concentration of 2�1016 to 5�1019 atoms/cm3 and is formed to wholly overlap with the gate wiring.
A cross sectional view shown in FIG. 5 is an enlarged diagram showing n-channel TFT 303 shown in FIG. 4A in the state of being manufactured to the process of FIG. 3C. As shown here, LDD region 211 is further classified into Lov region 211 a and Loff region 21 b. Phosphorus is contained in the Lov region 211 a at a concentration of 2�1016 to 5�1019 atoms/cm3, whereas it is contained at a concentration 1 to 2 times as much (typically 1.2 to 1.5 times) in the Loff region 211 b. Further, channel forming regions 213 and 214, a source region 215, a drain region 216, Loff regions 217 to 220, and an n-type impurity region (a) 221 contacting the Loff regions 218 and 219 are formed in the pixel TFT 304. The source region 215, and the drain region 216 are each formed n-type impurity region (a) at this point, and the Loff regions 217 to 220 are formed by n-type impurity region (c).
Resist masks 1002 to 1005 and the protection film 1001 is removed next and laser annealing process (the first annealing condition) is performed under the same conditions as FIG. 1B. Crystallinity of the crystalline silicon film hidden by the resist masks 1002 to 1005 is improved in this process, and the doped n-type impurity element is activated as well as recrystallizing the silicon film that became amorphous in the n-type impurity region (b) 1006 to 1008. (FIG. 10B) A protection film 1011 is again formed into a thickness of 120 to 150 nm, and a resist mask 1012 is formed. Channel doping process is performed under the same conditions as FIG. 1C. P-type impurity regions (b) 1013 to 1015 are thus formed. (FIG. 10C)
First, a base film 101 is formed on a substrate 100 according to embodiment 1 and a semiconductor film comprising amorphous component is formed thereon.
In embodiment 9, amorphous silicon film 1101 is formed into 30 nm thickness by CVD. (FIG. 11A)
First a processes through FIG. 11A are performed by following the steps of embodiment 1, and then the state of FIG. 10B is obtained by the processes of embodiment 8. While embodiment 17 shows an example of performing patterning the crystalline silicon film after laser annealing process (the first annealing condition), it is possible to perform the processes in the reverse order.
The resist mask is next removed and a laser annealing process (the second annealing condition) is performed. By this process the doped n-type or p-type impurity element is effectively activated. At the same time the interface between the active layers and a gate insulating film is improved. Note that it is necessary to irradiate the laser light through the gate insulating having a thickness of 1 nm in embodiment 18 and the laser annealing conditions must be set taking that in mind.
In embodiment 19 a case of manufacturing TFTs by a different process 15, order from that of embodiment 1 is described by using FIGS. 14A to 14E. Note that because only a part of the way is different from embodiment 1 and others are similar, same reference numerals are used for the same process. The example is given by the same impurity element as embodiment 1 for the impurity elements doped.
After forming resist masks 816 to 820, gate wirings 821 to 824 and a wiring are formed by etching the first high melting point metal film 119 and the second high melting point metal film 120 in a single step. Here, the gate wirings 822 and 823 formed in the driver circuit are formed to overlap a portion of n-type impurity regions (b) 111 to 113 by interposing a gate insulating film. The overlapped portions will later become Lov regions. (FIG. 14B) N-type impurity element (phosphorus in embodiment 19) is next doped in a self-aligned manner using the gate wirings 821 to 824 as masks. At this time, the impurity was doped with resist masks 816 to 820 that are used for forming the wiring and the gate wirings, remained. Thus formed impurity regions 825 to 830 are adjusted to be doped with phosphorus at � to {fraction (1/10)} (typically ⅓ to �) of concentration in that of the n-type impurity region (b). (FIG. 14C)
Next n-type impurity element (phosphorus in embodiment 20) is doped in a self-aligned manner by using the gate wirings 1513 to 1516 as masks. Thus formed impurity regions 1517 to 1522 are adjusted to be doped with phosphorus at concentration of � to {fraction (1/10)} (typically ⅓ to �) that of the n-type impurity regions (b). (FIG. 16F)
New resist masks 1523 to 1526 are formed by remaining resist masks 1507 to 1511, and impurity regions 1527 to 1533 that include phosphorus at a high concentration are formed by doping n-type impurity element (phosphorus in embodiment 20). Needless to say, the impurity elements may be formed by exposing the active layers by etching the gate insulating film. Here too ion doping using phosphine (PH3) was performed, and the phosphorus concentration in those regions are set at 1�1020 to 1�1021 atoms/cm3 (typically 2�1020 to 5�1020 atoms/cm3). (FIG. 17A)
Here, catalytic element used for the crystallization of amorphous silicon, film in embodiment 20 (nickel in embodiment 20) moved in a direction shown by an arrow, and is captured (gettering) in the region that contain phosphorus at a high concentration, formed in the above stated process. This is a phenomenon originated in the gettering effect of metal element by phosphorus. As a result, the concentration of the catalytic element contained in regions 1534 and 153 to 156 that will later become channel forming regions became 1�1017 atoms/cm3 or less (preferably 1�1016 atoms/cm3 or less).
A heat treatment process at 400 to 500� C. for approximately 1 hour is performed preceding a crystallization process, and after removing hydrogen from within the film, heat treatment is performed at between 500 and 650� C. (preferably from 550 to 570� C.) for 4 to 12 hours (preferably between 4 and 6 hours). Heat treatment is performed at 550� C. for 4 hours in embodiment 21, forming a crystalline semiconductor film (a crystalline silicon film in embodiment 21) 1805. (See FIG. 18B.)
A gettering process for removing the nickel used in the crystallization process from the crystalline silicon film is performed next. First, a mask insulating film 1806 is formed to a thickness of 150 nm on the surface of the crystalline semiconductor film 1805, and an open section 1807 is formed by patterning. A process for doping a periodic table group 15 element (phosphorous in embodiment 21) into the exposed crystalline semiconductor film is then performed. A gettering region 1808 containing a phosphorous concentration of between 1�1019 and 1�1020 atoms/cm3 is thus formed. (See FIG. 18C.)
A heat treatment process is performed next in a nitrogen atmosphere at between 450 and 650� C. (preferably from 500 to 550� C.) for 4 to 24 hours (preferably between 6 and 12 hours). The nickel in the crystalline semiconductor film is made to move in the direction of the arrows by this heat treatment process, and is captured in the gettering region 1808 by a phosphorous gettering effect. In other words, the concentration of nickel contained in a crystalline semiconductor film 1809 can be reduced below 1�1017 atoms/cm3, preferably to 1�1016 atoms/cm3, because nickel is removed from the crystalline semiconductor film. (See FIG. 18D.)
FIGS. 19A to 19D is used in embodiment 22 to explain the formation process of a semiconductor film that becomes a TFT active layer. Specifically, the technique described in Japanese Patent Application Laid-open No. Hei 10-247735 (corresponding to U.S. Pat. No. 09/034,041) is used.
First, a base film 1902 is formed from a 200 nm thick nitrated silicon oxide film on a substrate (a glass substrate in embodiment 22) 1901 and an amorphous semiconductor film (an amorphous silicon film in embodiment 22) 1903 with a 200 nm thickness. This process may be performed by continuously forming the base film and the amorphous semiconductor film with out exposure to the atmosphere.
A heat treatment process at 400 to 500� C. for approximately 1 hour is performed preceding a crystallization process, and after removing hydrogen from within the film, heat treatment is performed at between 500 and 650� C. (preferably from 550 to 600� C.) for 6 to 16 hours (preferably between 8 and 14 hours). Heat treatment is performed at 570� C. for 14 hours in embodiment 22. As a result, crystallization proceeds roughly parallel to the substrate (in the direction shown by the arrows) with the open section 1905 as a starting point, forming a crystalline semiconductor film (a crystalline silicon film in embodiment 22) 1907, in which the growth directions of the crystals are macroscopically in alignment. (See FIG. 19B.)
A gettering process for removing the nickel used in the crystallization process from the crystalline silicon film is performed next. A process for doping a periodic table group 15 element (phosphorous in embodiment 22) is performed with the mask insulating film 1904 previously formed as a mask as it is, a gettering region 1908 containing a phosphorous concentration of between 1�1019 and 1�1020 atoms/cm3 in the crystalline semiconductor film exposed by the open section 1905 is formed. (See FIG. 19C.)
A heat treatment process is performed next in a nitrogen atmosphere at between 450 and 650� C. (preferably from 500 to 550� C.) for 4 to 24 hours (preferably between 6 and 12 hours). The nickel in the crystalline semiconductor film is made to move in the direction of the arrows by this heat treatment process, and is captured in the gettering region 1908 by a phosphorous gettering effect. In other words, the concentration of nickel contained in a crystalline semiconductor film 1909 can be reduced below 1�1017 atoms/cm3, preferably to 1�1016 atoms/cm3, because nickel is removed from the crystalline semiconductor film. (See FIG. 19D.)
By selectively doping the catalytic element to promote crystallization (nickel here) and then performing crystallization, the crystalline semiconductor film 1909 thus formed is a crystalline semiconductor film having extremely good crystallinity. Specifically, it has a crystal structure in which bar-like or column-like crystals are lined up with a fixed directionality. Additionally, the lo catalytic element is removed by the phosphorous gettering effect after crystallization, and the concentration of the catalytic element remaining in the crystalline semiconductor film 1909 is less than 1�1017 atoms/cm3, preferably 1�1016 atoms/cm3.
FIG. 20B shows a double layered structure similar to that of embodiment 1 Tungsten nitride (WNx) is formed as a lower layer, and tungsten, upper layer. The tungsten nitride film 1702 may be formed into 10 to 50 nm (preferably 10 to 30 nm) and tungsten film 1703 may be formed into 200 to 400 nm (preferably 250 to 350 nm). The films are continuously formed in a laminate by sputtering in embodiment 23 without exposure to the atmosphere.
FIG. 20C is an example in which a wiring 1704 comprising a material formed from tungsten as a main component is formed on a film having insulating surface (or a substrate) 1700, and is covered by an insulating film 1705. The insulating film 1705 may be formed from silicon nitride film, silicon oxide film, silicon oxynitride film SiOxNy (0<�x, y<1) or a laminate combining these films.
FIG. 22A is a personal computer, and comprises a main body 2001 an image input section 2002, a display device 2003, and a keyboard 2404. The present invention may be applied to the image input section 2002, display device 2003 or other signal control circuits.
FIG. 22E is a player that uses a recording medium on which a program is recorded (hereinafter referred to as a recording medium), and comprises a main body 2401, a display device 2402, a speaker section 2403 a recording medium 2404, and operation switches 2405 etc. Note that music appreciation, film appreciation, games, and the use of the Internet can be performed with this device using a DVD (digital versatile disk), a CD, etc. as a recording medium. The present invention can be applied to the display device 2402, and to other signal control circuits.
FIG. 22F is a digital camera, and comprises a main body 2501, a display device 25 02, a viewfinder 2503, operation switches 2504, and an image receiving section (not shown in the figure). The present invention can be applied to the display device 2502 and to other signal control circuits.
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LABORATORY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YAMAZAKI, SHUNPEI;KOYAMA, JUN;REEL/FRAME:010948/0209;SIGNING DATES FROM 20000627 TO 20000630Feb 2, 2007FPAYFee paymentYear of fee payment: 4Feb 10, 2011FPAYFee paymentYear of fee payment: 8Feb 18, 2015FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services