Source: http://www.google.com/patents/US7030869?ie=ISO-8859-1&dq=7389243
Timestamp: 2014-08-02 05:58:00
Document Index: 623245503

Matched Legal Cases: ['ART0', 'ART11', 'ART0', 'ART11', 'ART0', 'ART11', 'ART0', 'ART0']

Patent US7030869 - Signal drive circuit, display device, electro-optical device, and signal ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA signal drive circuit capable of flexibly dealing with the change of the panel size and reducing power consumption, a display device and an electro-optical device using that signal drive circuit, and a signal drive method. A signal driver (signal drive circuit) includes: a shift register which sequentially...http://www.google.com/patents/US7030869?utm_source=gb-gplus-sharePatent US7030869 - Signal drive circuit, display device, electro-optical device, and signal drive methodAdvanced Patent SearchPublication numberUS7030869 B2Publication typeGrantApplication numberUS 10/154,436Publication dateApr 18, 2006Filing dateMay 23, 2002Priority dateMay 24, 2001Fee statusPaidAlso published asCN1197050C, CN1388512A, US7030850, US20020190974, US20050156850Publication number10154436, 154436, US 7030869 B2, US 7030869B2, US-B2-7030869, US7030869 B2, US7030869B2InventorsAkira MoritaOriginal AssigneeSeiko Epson CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (18), Non-Patent Citations (2), Referenced by (13), Classifications (32), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSignal drive circuit, display device, electro-optical device, and signal drive methodUS 7030869 B2Abstract A signal drive circuit capable of flexibly dealing with the change of the panel size and reducing power consumption, a display device and an electro-optical device using that signal drive circuit, and a signal drive method. A signal driver (signal drive circuit) includes: a shift register which sequentially shifts image data corresponding to signal lines in units of blocks each of which including a plurality of signal lines; a line latch which latches the image data in synchronization with a horizontal synchronization signal LP; a drive voltage generation circuit which generates a drive voltage based on the image data; and a signal line drive circuit, wherein high impedance control is performed for output to the signal lines, based on block output select data BLK designated in units of blocks; and wherein partial display control is performed based on the partial display data PART. Display control for the block output select data BLK in units of blocks is given priority in comparison with the partial display data PART.
TECHNICAL FIELD The present invention relates to a signal drive circuit, a display device and electro-optical device using the signal drive circuit, and a signal drive method.
BACKGROUND In recent years, use of portable telephones and other types of electronic equipment has become widespread. Accompanied by this, liquid crystal panels having various sizes have been used. As such liquid crystal panels, a simple matrix type liquid crystal panel using an STN (Super Twisted Nematic) liquid crystal and an active matrix type liquid crystal panel using a thin film transistor (hereinafter abbreviated as �TFT�) liquid crystal are known. The simple matrix type liquid crystal panel using an STN liquid crystal prevents a decrease in contrast by preventing a decrease in frame response by devising the drive method, whereby the power consumption can be reduced. The active matrix type liquid crystal panel using a TFT liquid crystal is more suitable for video display due to high contrast by the high-speed frame response.
SUMMARY According to one aspect of the present invention, there is provided a signal drive circuit which drives signal lines of an electro-optical device having pixels specified by a plurality of scan lines and a plurality of signal lines which intersect each other, based on image data, the signal drive circuit comprising:
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING FIG. 1 is a block diagram schematically showing a display device to which is applied a signal drive circuit (signal driver) according to one embodiment of the present invention.
DETAILED DESCRIPTION Embodiments of the present invention will be described below.
A liquid crystal device 10 as the display device includes a liquid crystal display (hereinafter abbreviated as �LCD�) panel 20, a signal driver (signal drive circuit) (source driver in a narrow sense) 30, a scanning driver (scanning drive circuit) (gate driver in a narrow sense) 50, an LCD controller 60, and a power supply circuit 80.
The LCD controller 60 controls the signal driver 30, scanning driver 50, and power supply circuit 80 according to the content set by a host such as a central processing unit (hereinafter abbreviated as �CPU�) (not shown). More specifically, the LCD controller 60 supplies the setting of the operation mode or a vertical synchronization signal or horizontal synchronization signal generated therein to the signal driver 30 and the scanning driver 50, for example. The LCD controller 60 supplies polarization inversion timing of the common electrode voltage Vcom to the power supply circuit 80.
The scanning driver 50 includes a shift register 52, level shifters (hereinafter abbreviated as �L/S�) 54 and 56, and a scan line drive circuit 58.
The LCD controller 60 includes a control circuit 62, a random access memory (hereinafter abbreviated as �RAM�) (memory circuit in a broad sense) 64, a host input/output circuit (I/O) 66, and an LCD input/output circuit 68. The control circuit 62 includes a command sequencer 70, a command setting register 72, and a control signal generation circuit 74.
For example, in the case where the signal driver 30 is disposed at the position shown in FIG. 14A, the image data for one horizontal scan sequentially held by the shift register and latched in the line latch 36 is arranged in the order of P1 to PM corresponding to the signal lines S1 to SM by setting the shift direction switch signal SHL to �H�, as shown in FIG. 15A.
In the case where the signal driver 30 is disposed at the position shown in FIG. 14B, the image data supplied from the LCD controller 60 in the same order as that shown in FIG. 15A is held in the line latch 36 in the order of PM, . . . P3, P2, P1 corresponding to the signal lines S1 to SM by setting the shift direction switch signal SHL to �L�, as shown in FIG. 15B.
The block output select register 148 includes block output select data BLK0 to BLK11 which indicate whether or not to control the outputs of the signal line drive circuit in each block in a high impedance state corresponding to the blocks B0 to B11. In this embodiment, the signal lines of the LCD panel 20 are connected to the signal line drive circuit in the block in which the block output select data BLK0 to BLK11 is set to �1�, whereby the signal is driven based on the image data. The signal lines of the LCD panel 20 are not connected to the signal line drive circuit in the block in which the block output select data BLK0 to BLK11 is set to �0�, or the signal is not driven even if the signal lines are connected.
The partial display select register 150 includes partial display data PART0 to PART11 which indicate whether or not to drive a signal through the signal lines in each block based on the image data corresponding to the blocks B0 to B11. In this embodiment, the display is controlled by using the block in which the partial display data PART0 to PART11 is set to �1� which indicates the output is ON as the display area, and the block in which the partial display data PART0 to PART11 is set to �0� which indicates the output is OFF as the non-display area.
The switching circuit SWB0-0 outputs the output data of the SR0-1 as a left direction data output signal LOUT when the block output select data BLK (BLK0′) is �1� (logic level �H�). The switching circuit SWB0-0 outputs the image data shifted from the block B1 which is input as the right direction data input signal RIN as the left direction data output signal LOUT when the block output select data BLK (BLK0′) is �0� (logic level �L�).
The switching circuit SWB1-0 outputs the output data of the SR0-24 as a right direction data output signal ROUT when the block output select data BLK (BLK0′) is �1� (logic level �H�). The switching circuit SWB0-0 outputs the image data which has been input as the left direction data input signal LIN (DIO in block B0) as the right direction data output signal ROUT when the block output select data BLK (BLK0′) is �0� (logic level �L�).
The image data corresponding to the signal line S1 latched in the line latch LAT0-1 is supplied to the DAC0-1 of the drive voltage generation circuit. The DAC0-1 generates 64 levels of gray scale voltages when a DAC enable signal DACen is at a logic level of �H�, based on 6-bit gradation data supplied from the LAT0-1, for example.
The reference voltages at levels of V0 to V8 are supplied to the DAC0-1 from the power supply circuit 80, for example. When the DAC enable signal DACen becomes a logic level of �H�, the DAC0-1 selects one of the voltage ranges divided by V0 to V8 from 3 higher order bits among the 6-bit gradation data as the image data of each signal line, for example. When the voltage range between the reference voltages V2 and V3 is selected, the DAC0-1 selects V23 which is one of the eight levels between V2 and V3 specified by the 3 lower order bits among the 6-bit gradation data, for example.
Specifically, when the block output select data BLK (BLK0′) is �0�, the DAC enable signal DACen causes the operation of the drive voltage generation circuit 38 0 in the BLK0 to be terminated irrespective of the setting of the partial display data PART (PART0′). When the block output select data BLK (BLK0′) is �1�, the DAC operation is performed when the block B0 is set to be the partial display area. When the block B0 is set to be the partial non-display area, the DAC operation is terminated, thereby reducing consumption of current flowing through a ladder resistance.
The output terminal of the voltage-follower-connected operational amplifier OP0-1 is negative feedbacked. Therefore, the input impedance of the operational amplifier is extremely increased, whereby the input current barely flows. When an operational amplifier enable signal OPen is at a logic level of �H�, the operational amplifier converts the impedance of the drive voltage generated by the DAC0-1, and drives the signal line S1. This enables the signal to be driven irrespective of the output load of the signal line S1.
Specifically, when the block output select data BLK (BLK0′) is �0�, the operational amplifier enable signal OPen terminates the operation of the operational amplifier in the BLK0 (current consumption is reduced by terminating the current source of the operational amplifier) irrespective of the setting of the partial display data PART (PART0′). When the block output select data BLK (BLK0′) is �1�, the operational amplifier converts the impedance of the drive voltage generated by the drive voltage generation circuit, and drives the corresponding signal lines when the block B0 is set to be the partial display area. When the block B0 is set to be the partial non-display area, the operation of the operational amplifier is terminated, thereby reducing current consumption.
Source terminals of the n-type transistors QN1 and QN2 are connected to a ground level VSS through a current source 166 0-1 formed when one of the reference voltage select signals VREFN1 to VREFN3 is set at a logic level of �H�.
Source terminals of the p-type transistors QP3 and QP4 are connected to the power supply voltage level VDD through a current source 168 0-1 formed when one of the reference voltage select signals VREFP1 to VREFP3 is at a logic level of �L�.
The reference voltage select signal generation circuit controls the current sources 166 0-1 and 168 0-1 only when the logic level of the operational amplifier enable signal OPen is �H� by the reference voltage select signals VREFP1 to VREFP3 for the p-type transistors and the reference voltage select signals VREFN1 to VREFN3 for the n-type transistors corresponding to the state of the reference voltage select signals VREF1 to VREF3. When the logic level of the operational amplifier enable signal OPen is �L�, the reference voltage select signal generation circuit masks the reference voltage select signals VREF1 to VREF3. This eliminates current flowing through the current sources 166 0-1 and 168 0-1, whereby the differential amplification operation is terminated.
When the logic level of the operational amplifier enable signal OPen is �H�, if the output voltage VOUT is lower than the input voltage VIN, the potential of the drain terminal of then-type transistor QN2 is decreased in the first differential amplifier circuit 162 0-1, whereby the potential of the output voltage VOUT is increased through the p-type transistor QP12.
When the logic level of the operational amplifier enable signal OPen is �L�, since the reference voltage select signals VREF1 to VREF3 are masked as shown in FIG. 25, each of the transistors of the current sources 166 0-1 and 168 0-1 is turned OFF. The drain terminal of the p-type transistor QP11 is connected to the power supply voltage level VDD, and the drain terminal of the n-type transistor QN11 is connected to the ground level VSS. Therefore, the output voltage VOUT is in a high impedance state. In this case, a partial-non-display-level voltage generated by a partial-non-display-level voltage supply circuit VG0-1 described later is supplied to the signal lines to which the output voltage VOUT should be supplied.
When a non-display-level voltage supply enable signal LEVen is at a logic level of �H�, the partial-non-display-level voltage supply circuit VG0-1 generates a given non-display-level voltage VPART-LEVEL to be supplied to the signal lines when set to the non-display area (output is OFF) in the partial display select register.
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