Source: https://patents.google.com/patent/JP2012234964A/en
Timestamp: 2020-01-25 15:22:22
Document Index: 414255213

Matched Legal Cases: ['art 15', 'art 15', 'art 15', 'art 21', 'art 15', 'art 15', 'art 1', 'art 1', 'art 1', 'art 1', 'art 2', 'art 2', 'art 3', 'art 3', 'art 3', 'art 3', 'art 4', 'art 4', 'art 4', 'art 4', 'art 5', 'art 8', 'art 15', 'art 15', 'art 22']

JP2012234964A - Semiconductor device and manufacturing method of the same - Google Patents
JP2012234964A JP2011102400A JP2011102400A JP2012234964A JP 2012234964 A JP2012234964 A JP 2012234964A JP 2011102400 A JP2011102400 A JP 2011102400A JP 2011102400 A JP2011102400 A JP 2011102400A JP 2012234964 A JP2012234964 A JP 2012234964A
JP2011102400A
靜憲 大湯
浩二 谷口
耕治 浜田
Hiroaki Takeya
博昭 竹谷
2011-04-28 Application filed by Elpida Memory Inc, エルピーダメモリ株式会社 filed Critical Elpida Memory Inc
2011-04-28 Priority to JP2011102400A priority Critical patent/JP2012234964A/en
2012-11-29 Publication of JP2012234964A publication Critical patent/JP2012234964A/en
PROBLEM TO BE SOLVED: To provide a semiconductor device which can decrease channel resistance and increase an ON-state current, and cause each transistor to operate independently and stably.SOLUTION: A semiconductor device comprises: a fin part 15 formed so as to protrude from a bottom 18c of a gate electrode groove 18; a gate insulation film 21 covering surfaces of the gate electrode groove 18 and the fin part 15; a gate electrode 22 embedded in a lower part of the gate electrode groove 18 and formed so as to stride across the fin part 15 via the gate insulation film 21; a first impurity diffusion region 28 covering an upper part 21A of the gate insulation film 21 arranged on a first lateral face 18a; and a second impurity diffusion region 29 covering a part other than a lower end of the gate insulation film 21 arranged on a second lateral face 18b. A depth of the gate electrode groove 18 from a surface layer 13a of a semiconductor substrate 13 is 150-200 nm and a height from the bottom 18c of the gate electrode groove 18 to an upper part 15a of the fin part 15 is 10-40 nm.
According to one aspect of the present invention, a plurality of first element isolation regions provided in a semiconductor substrate so as to extend in a first direction and partitioning an active region having a plurality of element formation regions; A gate electrode trench provided in a surface layer of a semiconductor substrate, extending in the second direction intersecting the first element isolation region and the active region, and having first and second side surfaces and a bottom portion facing each other And the depth of the second groove portion formed in the first element isolation region is made deeper than the first groove portion formed in the active region in the gate electrode groove, and By forming the depth of the portion of the groove facing the second groove substantially the same as the depth of the second groove, a part of the active region protrudes from the bottom of the gate electrode groove. The fin portion, the gate electrode groove and the fin portion A gate insulating film covering the surface, a gate electrode formed so as to straddle the fin portion via the gate insulating film by being embedded in the lower portion of the gate electrode groove, and the first side surface. The first impurity diffusion region provided on the semiconductor substrate and the portion other than the lower end of the gate insulating film disposed on the second side surface are covered so as to cover the upper portion of the gate insulating film. A second impurity diffusion region provided in the semiconductor substrate, wherein a depth of a bottom portion of the gate electrode trench is 150 to 200 nm from a surface layer of the semiconductor substrate, and a bottom portion of the gate electrode trench The height from the top of the fin portion to 10 to 40 nm is provided.
1 is a schematic plan view of a memory cell array provided in a semiconductor device according to an embodiment to which the present invention is applied. FIG. 2 is a cross-sectional view of the memory cell array shown in FIG. 1 in the AA line direction. FIG. 2 is a cross-sectional view of the memory cell array shown in FIG. 1 in the BB line direction. It is a perspective view for demonstrating the cross-sectional structure of the fin part provided in the gate electrode groove | channel in the semiconductor device which is embodiment which applied this invention. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of a memory cell array provided in a semiconductor device according to an embodiment to which the present invention is applied, and is a plan view of a region where the memory cell array is formed; FIG. 3B is a diagram (part 1) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the AA line direction of the structure illustrated in FIG. 3A; FIG. 3B is a diagram (part 1) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view of the structure illustrated in FIG. 3A in the BB line direction. FIG. 3B is a diagram (part 1) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the CC line direction of the structure illustrated in FIG. 3A; FIG. 7 is a second diagram illustrating the manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a plan view of a region where the memory cell array is formed; FIG. 4B is a diagram (part 2) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view taken along the line AA of the structure illustrated in FIG. 4A; FIG. 4B is a second diagram illustrating the manufacturing process of the memory cell array provided in the semiconductor device that is the embodiment to which the present invention is applied, and is a cross-sectional view in the direction of the line BB of the structure illustrated in FIG. 4A; FIG. 4B is a diagram (part 2) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the CC line direction of the structure illustrated in FIG. 4A; FIG. 9 is a diagram (part 3) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a plan view of a region where the memory cell array is formed; FIG. 6B is a diagram (part 3) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the AA line direction of the structure illustrated in FIG. 5A; FIG. 5B is a diagram (part 3) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the BB line direction of the structure illustrated in FIG. 5A; FIG. 6B is a diagram (part 3) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the CC line direction of the structure illustrated in FIG. 5A; FIG. 8 is a diagram (part 4) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a plan view of a region where the memory cell array is formed; FIG. 6B is a diagram (part 4) illustrating a manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view taken along the line AA of the structure illustrated in FIG. 6A; FIG. 6B is a diagram (part 4) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the BB line direction of the structure illustrated in FIG. 6A; FIG. 6B is a diagram (part 4) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the CC line direction of the structure illustrated in FIG. 6A; FIG. 10 is a fifth diagram illustrating the manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a plan view of a region where the memory cell array is formed; FIG. 7B is a diagram (part 5) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the AA line direction of the structure illustrated in FIG. 7A; FIG. 7B is a view (No. 5) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view of the structure shown in FIG. FIG. 7B is a view (No. 5) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the CC line direction of the structure shown in FIG. 7A; FIG. 10 is a sixth diagram illustrating the manufacturing process of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a plan view of a region where the memory cell array is formed; FIG. 8B is a diagram (No. 6) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the AA line direction of the structure illustrated in FIG. 8A; FIG. 8B is a diagram (No. 6) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the BB line direction of the structure illustrated in FIG. 8A; FIG. 8B is a diagram (No. 6) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the CC line direction of the structure illustrated in FIG. 8A; FIG. 9 is a view (No. 7) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and a plan view of a region where the memory cell array is formed; FIG. 9B is a view (No. 7) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the AA line direction of the structure shown in FIG. 9A; FIG. 9B is a diagram (No. 7) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the BB line direction of the structure illustrated in FIG. 9A; FIG. 9B is a view (No. 7) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the CC line direction of the structure shown in FIG. 9A; FIG. 8 is a view (No. 8) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a plan view of a region where the memory cell array is formed; FIG. 10B is a diagram (part 8) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the AA line direction of the structure illustrated in FIG. 10A; FIG. 10B is a view (No. 8) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the BB line direction of the structure shown in FIG. 10A; It is FIG. (9) which shows the manufacturing process of the memory cell array provided in the semiconductor device which is embodiment which applied this invention, and is a top view of the area | region in which a memory cell array is formed. FIG. 11B is a diagram (No. 9) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the AA line direction of the structure illustrated in FIG. 11A; FIG. 11B is a diagram (No. 9) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the BB line direction of the structure illustrated in FIG. 11A; FIG. 10 is a diagram (No. 10) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a plan view of a region where the memory cell array is formed; FIG. 12B is a view (No. 10) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view taken along line AA of the structure shown in FIG. 12A; FIG. 13B is a view (No. 10) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the BB line direction of the structure shown in FIG. 12A; FIG. 14 is a view (No. 11) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and a plan view of a region where the memory cell array is formed; FIG. 13B is a view (No. 11) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view taken along the line AA of the structure shown in FIG. 13A; FIG. 13B is a view (No. 11) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view in the BB line direction of the structure shown in FIG. 13A; FIG. 13B is a view (No. 12) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and a cross-sectional view corresponding to the cut surface of FIG. 2A; FIG. 12B is a view (No. 12) illustrating a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and a cross-sectional view corresponding to the cut surface of FIG. 2B; It is FIG. (13) which shows the manufacturing process of the memory cell array provided in the semiconductor device which is embodiment which applied this invention, It is sectional drawing corresponding to the cut surface of FIG. 2A. FIG. 13B is a view (No. 13) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and a cross-sectional view corresponding to the cut surface in FIG. 2B; It is FIG. (14) which shows the manufacturing process of the memory cell array provided in the semiconductor device which is embodiment which applied this invention, It is sectional drawing corresponding to the cut surface of FIG. 2A. FIG. 14B is a view (No. 14) showing a manufacturing step of the memory cell array provided in the semiconductor device according to the embodiment to which the present invention is applied, and is a cross-sectional view corresponding to the cut surface of FIG. 2B; It is a top view which shows the other example of the layout of the memory cell array applicable to the semiconductor device which is embodiment which applied this invention. It is a figure which shows the relationship between the height of a fin part and the defect rate in the semiconductor device which is embodiment which applied this invention. It is a figure which shows the relationship between the depth of the 2nd impurity diffusion area | region and defect rate in the semiconductor device which is embodiment which applied this invention. It is a related figure for demonstrating the junction position of each impurity diffusion area | region in the semiconductor device which is embodiment which applied this invention. It is a top view which shows an example of the layout of the conventional DRAM. FIG. 22 is a cross-sectional view of the DRAM shown in FIG. 21 in the ZZ line direction.
FIG. 21 is a plan view showing an example of the layout of a conventional DRAM, and FIG. 22 is a cross-sectional view of the DRAM shown in FIG. 21 in the ZZ line direction.
Next, with reference to FIG. 21 and FIG. 22, the knowledge obtained by the inventor regarding the above-described disturb failure will be described.
Referring to FIG. 21, a plurality of regularly arranged active regions 302 are provided on the surface of a semiconductor substrate 301. Each active region 302 is surrounded by an element isolation region 303 in which a groove formed on the surface of the semiconductor substrate 301 is embedded with an insulating film. In the Y direction intersecting with the active region 302, a plurality of word lines WL extending in the Y direction are arranged.
Referring to FIG. 22, word lines WL <b> 1 and WL <b> 2 are formed by burying via a gate insulating film 305 in a groove provided on the surface of a semiconductor substrate 301 across a plurality of active regions 302 and element isolation regions 303. ing.
FIG. 1 is a schematic plan view of a memory cell array provided in a semiconductor device according to an embodiment to which the present invention is applied. FIG. 2A is a cross-sectional view of the memory cell array shown in FIG. FIG. 2B is a cross-sectional view of the memory cell array shown in FIG. 1 in the BB line direction. FIG. 2C is a perspective view for explaining a cross-sectional structure of the fin portion provided in the gate electrode groove in the semiconductor device of this embodiment.
2A schematically shows the bit line 34 actually extending in the X direction shown in FIG. 2A to 2C, the same components as those of the semiconductor device 10 shown in FIG.
A semiconductor device 10 according to an embodiment to which the present invention is applied includes a memory cell region in which the memory cell array 11 shown in FIGS. 1, 2A, and 2B is formed, and a peripheral (not shown) arranged around the memory cell region. Circuit area (area where peripheral circuits are formed).
As shown in FIGS. 1, 2A and 2B, a memory cell array 11 provided in the semiconductor device 10 includes a semiconductor substrate 13, a first element isolation region 14, and an active region having a plurality of element formation regions R. 16, the second element isolation region 17, the gate electrode trench 18, the fin portion 15 formed so that a part of the active region 16 protrudes from the bottom portion 18 c of the gate electrode trench 18, Second transistors 19-1, 19-2, a gate insulating film 21, a gate electrode 22 that is a buried gate electrode, a buried insulating film 24, a mask insulating film 26, and a first impurity diffusion region 28 The second impurity diffusion region 29, the opening 32, the bit line contact plug 33, the bit line 34, the cap insulating film 36, the sidewall film 37, the interlayer insulating film 38, and the contact A 41, a capacitor contact plug 42, the capacitor contact pad 44, a silicon nitride film 46, a capacitor 48, a.
As shown in FIGS. 1 and 2C, the gate electrode trench 18 is provided so as to extend across the first element isolation region 14 and the active region 16. In other words, the gate electrode trench 18 includes a continuous first trench 18A formed in the active region 16 and a second trench 18B formed in the first element isolation region 14.
As shown in FIGS. 2B and 2C, the bottom of the second groove 18 </ b> B formed in the first element isolation region 14 in the gate electrode groove 18 becomes the bottom 18 c of the gate electrode groove 18. Yes.
As shown in FIGS. 2A and 2C, in the gate electrode trench 18, the bottom of the first trench portion 18A formed in the active region 16 has a second depth that is opposite to the second trench portion 18B. The depth is the same as the depth of the bottom of the groove. On the other hand, in the central portion of the first groove portion 18A, the fin portion 15 is formed so that a part of the active region 16 protrudes from the bottom portion.
2A to 2C, the fin portion 15 has an upper portion 15a and a pair of side surfaces 15b and 15c facing each other.
As shown in FIG. 2C, the shape of the fin portion 15 may be an acute angle or may be rounded (it may not be an acute angle).
On the other hand, when the height H of the fin portion 15 is within the above range, it is possible to suppress the increase in the OFF leak current and improve the writing characteristics while sufficiently suppressing the disturb failure. That is, it is possible to satisfy any of the above characteristics that are in a trade-off relationship with the height of the fin portion (see FIG. 18).
2A to 2C, the first and second transistors 19-1 and 19-2 are trench gate type transistors, and include a gate insulating film 21 and a gate electrode that is a saddle fin type buried word line. 22, a buried insulating film 24, a first impurity diffusion region 28, and a second impurity diffusion region 29.
2A to 2C, the gate insulating film 21 is provided so as to cover the first and second side surfaces 18a and 18b of each gate electrode trench 18 and the bottom portion 18c of the gate electrode trench 18. ing. Further, it is provided so as to cover the surface of the fin portion 15 provided in the bottom portion 18c of the gate electrode groove 18 (that is, a pair of side surfaces 15b and 15c facing the upper portion 15a).
Referring to FIGS. 2A to 2C, the gate electrode 22 employs a saddle fin type embedded word line in order to reduce the OFF leak current and improve the write characteristics. By using the saddle fin type, the S coefficient can be reduced, so that the threshold voltage can be reduced while maintaining the OFF leakage current. Further, by using the saddle fin type, the current driving capability can be improved, so that the writing characteristics can be improved.
Here, if the depth of the second impurity diffusion region 29 is shallower than the apex of the fin portion 15, the problem of disturb failure becomes obvious. On the other hand, when the depth of the second impurity diffusion region 29 is deeper than the bottom portion 18c of the gate electrode trench 18, the doped impurity (for example, n-type impurity) reaches the fin portion 15 as well. It becomes lower than the voltage (Vt). When the channel concentration (for example, p-type impurity concentration) of the semiconductor substrate 13 is increased to compensate for the decrease in the threshold voltage (Vt), the first impurity diffusion region 28 (for example, the n-type diffusion layer). ) And the semiconductor substrate 13 (for example, p-channel), the electric field strength becomes large, and the problem that the information retention characteristics deteriorate becomes obvious (see FIG. 19).
FIG. 20 is a relationship diagram for explaining the junction position of each impurity diffusion region in the semiconductor device 10 of the present embodiment. In FIG. 20, the horizontal axis indicates the depth from the surface 13 a of the semiconductor substrate 13, and the vertical axis indicates the impurity concentration of the semiconductor substrate 13 and the first and second impurity diffusion regions 28 and 29. In the drawing, the intersection of each profile of the first and second impurity diffusion regions 28 and 29 and the profile with the semiconductor substrate 13 is a metallurgical joining position.
FIG. 20 shows the relationship between the depth of the gate electrode trench 18, the height H of the fin portion 15, and the junction position of the second impurity diffusion region 29.
A semiconductor device 10 according to an embodiment to which the present invention is applied has the following configuration. A plurality of first element isolation regions 14 made of a semiconductor substrate 13 and provided in the semiconductor substrate 13 so as to extend in the first direction and partitioning an active region 16 having a plurality of element formation regions R; Adjacent to a plurality of second element isolation regions 17 provided in the semiconductor substrate 13 so as to extend in a second direction intersecting the first direction and partitioning the active region 16 into a plurality of element formation regions R Between the second element isolation regions 17, 17 extending in the second direction intersecting the first element isolation region 14 and the active region 16 on the surface layer of the semiconductor substrate 13, and facing each other. Of the pair of gate electrode grooves 18 having the first and second side surfaces 18a, 18b and the bottom portion 18c, and the gate electrode groove 18, the first element than the first groove portion 18A formed in the active region 16. Second groove 18 formed in isolation region 14 And the depth of the portion of the first groove 18A facing the second groove 18B is substantially the same as the depth of the second groove 18B, so that the bottom of the gate electrode groove 18 is formed. A fin portion 15 formed so that a part of the active region 16 protrudes from 18 c, a gate insulating film 21 covering the surface of the gate electrode groove 18 and the fin portion 15, and a lower portion of the pair of gate electrode grooves 18. As a result, the upper surface of the semiconductor substrate 13 between the pair of gate electrodes 22 formed so as to straddle the fin portion 15 via the gate insulating film 21, and the second element isolation region 17 and the gate electrode trench 18. A pair of gate electrode grooves provided in 13a and arranged so that the two first impurity diffusion regions 28, 28 connected to the capacitor 48 and the second side surfaces 18b, 18b face each other. And a second impurity diffusion region 29 provided on the semiconductor substrate 13 between 8 and 18 and connected to the bit line 34, and the element formation region R shares the second impurity diffusion region 29. In addition, the first transistor 19-1 including at least one gate electrode 22 and the fin portion 15 and one first impurity diffusion region 28, the other gate electrode 22 and the fin portion 15, and the other first first. And the depth of the bottom 18c of the gate electrode trench 18 is 150 to 200 nm from the surface 13a of the semiconductor substrate 13, and the second transistor 19-2 is formed of at least the second impurity diffusion region 28. The height from the bottom portion 18c of the electrode groove 18 to the apex (upper portion) of the fin portion 15 is 10 to 40 nm.
According to the semiconductor device 10 of the present embodiment, the fin portion 15 is provided in the bottom portion 18c of the gate electrode trench 18, and the upper surface of the semiconductor substrate 13 sandwiched between the first side surface 18a and the second element isolation trench 54. A portion of the semiconductor substrate 13 positioned between the two gate electrode trenches 18 and the first impurity diffusion region 28 covering the upper portion 21A of the gate insulating film 21 disposed on the first side surface 18a. And a second impurity diffusion region 29 covering all but the lower end portion of the gate insulating film 21 disposed on the second side surface 18b of the pair of gate electrode trenches 18. Thus, when the first and second transistors 19-1 and 19-2 are operated, the first channel region is formed in the fin portion 15, and the gate insulating film 21 disposed on the first side surface 18a. The semiconductor substrate 13 in contact with the lower portion of the semiconductor substrate 13, the semiconductor substrate 13 in contact with the bottom surface 18c of the gate electrode groove 18 and the semiconductor substrate 13 below the bottom portion of the second impurity diffusion region 29 disposed on the second side surface 18b. The second channel region is formed, and the semiconductor substrate 13 that is in contact with the second side surface 18b and above the bottom of the second impurity diffusion region 29 is not provided with the channel region. .
3A to 3D, 4A to 4D, 5A to 5D, 6A to 6D, 7A to 7D, 8A to 8D, 9A to 9D, 10A to 10C, and 11A. 11C, 12A to 12C, 13A to 13C, FIG. 14, FIG. 15, and FIG. 16, the manufacturing method of the semiconductor device 10 (specifically, the memory cell array 11) of this embodiment. Will be described.
Here, the AA line shown in FIGS. 3A to 13A is the AA line shown in FIG. 1, and the BB line shown in FIGS. 3B to 13B is the BB line shown in FIG. It corresponds.
Moreover, the cross section along CC line shown to FIG. 3A-FIG. 9A is shown to FIG. 3D-FIG. 9D, respectively. The cross section along the CC line shows a cross section along the extending direction of the gate electrode 22 which is a buried word line in the semiconductor device 10 of the present embodiment.
9A to 9D, the surface of each of the gate electrode trenches 18 (that is, the first and second side surfaces 18a and 18b and the bottom portion 18c of the gate electrode trench 18) and the fin portion 15 are formed. A gate insulating film 21 is formed to cover the surface (that is, the pair of side surfaces 15b and 15c facing the upper portion 15a).
Next, the gate electrode 22 is formed so as to bury the lower portion of the gate electrode trench 18 across the fin portions 15 via the gate insulating film 21 so that the upper surface 22a is lower than the main surface 13a of the semiconductor substrate 13. (See FIG. 9D).
3D to 9D, the saddle fin type gate electrode 22 which is a buried word line is formed, and therefore, the cross-sectional views along the line CC shown in FIGS. 3A to 9A are omitted in the subsequent drawings. .
Next, in the steps shown in FIGS. 10A to 10C, phosphorus, which is an n-type impurity (impurity having a different conductivity from the p-type silicon substrate as the semiconductor substrate 13), is formed on the entire top surface of the structure shown in FIGS. (P) is ion-implanted under the conditions of an energy of 100 KeV and a dose of 1E14 atmos / cm 2 , so that the semiconductor substrate 13 positioned between the gate electrode trench 18 and the first element isolation region 17 is first The impurity diffusion region 28 is formed, and an impurity diffusion region 71 which is a part of the second impurity diffusion region 29 is formed in the semiconductor substrate 13 located between the two gate electrode trenches 18.
11A to 11C, the upper surface 24a of the buried oxide film 24, the upper surface 26a of the mask insulating film 26, and the upper surface 55a of the second element isolation insulating film 55 are positioned between the buried insulating films 24. A photoresist 73 having a groove-like opening 73a exposing the upper surface 26a of the mask insulating film 26 to be formed is formed.
12A to 12C, the impurity diffusion region 71 exposed from the photoresist 73 (in other words, the semiconductor substrate 13 on which the impurity diffusion region 71 is formed) is added to the n-type impurity (p that is the semiconductor substrate 13). By selectively ion-implanting phosphorus (P), which is an impurity of a conductivity type different from that of the silicon substrate, the depth of the bottom of the semiconductor substrate 13 positioned between the two gate electrode trenches 18 is reduced. A second impurity diffusion region 29 is formed so as to be between the apex of the upper surface 15 a of the fin portion 15 and the bottom portion 18 c of the gate electrode groove 18. In the ion implantation, the first ion implantation is performed under the condition of energy of 15 KeV and the dose of 5E14 atmos / cm 2 , and then the second ion implantation of the energy of 30 KeV and the dose of 2E13 atmos / cm 2. (Two-stage injection).
Next, in the steps shown in FIGS. 13A to 13C, the photoresist 73 shown in FIGS. 12A to 12C is removed.
14A and 14B, the bit line contact plug 33 that fills the opening 32 and the bit line 34 (see FIG. 1) that is disposed on the bit line contact plug 33 and extends in the X direction are collectively collected. Form.
Specifically, as shown in FIG. 14A, a polysilicon film, a titanium nitride film, and a tungsten film (not shown) are sequentially formed on the upper surface 24a of the buried insulating film 24 so as to bury the opening 32 (this is shown in FIG. At this time, a polysilicon film is formed so as to bury the opening 32.
15A and 15B, the interlayer insulating film 38, the mask insulating film 26, the buried insulating film 24, and the gate insulating film 21 are anisotropically etched (specifically, by the SAC (Self Aligned Contact) method). The contact hole 41 exposing a part of the upper surface 28a of the first impurity diffusion region 28 is formed by dry etching.
Next, in the process shown in FIGS. 16A and 16B, a thick silicon oxide film (SiO 2 film) not shown is formed on the silicon nitride film 46. The thickness of the silicon oxide film (SiO 2 film) can be set to, for example, 1500 nm.
According to the manufacturing method of the semiconductor device of the first embodiment, the fin portion 15 is provided in the bottom portion 18c of the gate electrode groove 18 and is sandwiched between the first side surface 18a and the second element isolation groove 54. A first impurity diffusion region 28 that covers the upper portion 21A of the gate insulating film 21 that includes the upper surface 13a of the semiconductor substrate 13 and is disposed on the first side surface 18a, and two gate electrode trenches 18 in the semiconductor substrate 13. A second impurity diffusion region 29 that is disposed in a portion located between the gate insulating films 21 and covers all but the lower end portion of the gate insulating film 21 disposed on the second side surface 18 b of the pair of gate electrode grooves 18. It has become. Thus, when the first and second transistors 19-1 and 19-2 are operated, the first channel region is formed in the fin portion 15, and the gate insulating film 21 disposed on the first side surface 18a. The semiconductor substrate 13 in contact with the lower portion of the semiconductor substrate 13, the semiconductor substrate 13 in contact with the bottom portion 18 c of the gate electrode groove 18, and the semiconductor substrate 13 below the bottom portion of the second impurity diffusion region 29 disposed on the second side surface 18 b. It is possible to form the second channel region and not form the channel region in the semiconductor substrate 13 that is in contact with the second side surface 18 b and above the bottom of the second impurity diffusion region 29.
Further, the gate electrode 22 is formed so as to bury the lower portion of each gate electrode trench 18 via the gate insulating film 21, and then the upper surface 22a of the gate electrode 22 is buried so as to bury each gate electrode trench 18. By forming the buried insulating film 24 covering the gate electrode 22, the gate electrode 22 does not protrude above the surface 13a of the semiconductor substrate 13.
FIG. 17 is a plan view showing another example of the layout of the memory cell array applicable to the semiconductor device according to the embodiment to which the present invention is applied. In FIG. 17, the same components as those in the structure shown in FIG.
The semiconductor device 10 according to the embodiment described above can be applied to a layout in which the active region 16 and the bit line 34 are formed in a zigzag shape as shown in FIG.
DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 11 ... Memory cell array 13 ... Semiconductor substrate 13a ... Main surface 14 ... 1st element isolation region 15 ... Fin part 15a ... Upper part 15b, 15c ... Side surface 16 ... Active region 17 ... 2nd element isolation region 18 ... Gate electrode groove 18A ... first groove 18B ... second groove 18a ... first side 18b ... second side 18b ... bottom 19-1 ... first transistor 19-2 ... second transistor 21 ... gate Insulating film 21A ... Upper part 22 ... Gate electrodes 22a, 24a, 26a, 28a, 29a, 36a, 38a, 42a, 52a, 55a, 59a, 86a ... Upper surface 24 ... Embedded insulating film 26 ... Mask insulating films 26A, 26B, 32, 66a, 73a ... opening 28 ... first impurity diffusion region 28b ... bottom surface 29 ... second impurity diffusion region 33 ... bit line contact Top plug 34 ... Bit line 36 ... Cap insulating film 37 ... Side wall film 38 ... Interlayer insulating film 41 ... Contact hole 42 ... Capacitor contact plug 44 ... Capacitor contact pad 46, 66 ... Silicon nitride film 48 ... Capacitor 51 ... First element Isolation groove 52 ... first element isolation insulating film 54,98 ... second element isolation groove 55 ... second element isolation insulating film 57 ... lower electrode 58 ... capacitance insulating film 59 ... upper electrode 65 ... pad oxide film 71 ... diffusion region 73 ... photoresist 85,101 ... first region 86: second region 91 ... grooves 93A ... bottom D 1, D 2, D 3 , D 4 ... depth H ... fin portion high R: Element formation region W 1 : Width
A second impurity diffusion region provided in the semiconductor substrate so as to cover a portion other than a lower end portion of the gate insulating film disposed on the second side surface,
2. The semiconductor device according to claim 1, wherein a depth of the second impurity diffusion region is shallower than a bottom portion of the gate electrode trench and deeper than an upper portion of the fin portion.
The semiconductor device according to claim 1, wherein the second impurity diffusion region is provided between two gate electrode trenches in the semiconductor substrate.
4. The semiconductor device according to claim 1, wherein a depth of the first impurity diffusion region is provided so as to be 5 to 10 nm shallower than an upper surface of the gate electrode. 5.
The fin portion has an upper portion and a pair of side surfaces facing each other,
The upper portion extends in the first direction, and both ends of the upper portion are provided across the first side surface and the second side surface in the first groove portion,
5. The semiconductor device according to claim 1, wherein the pair of side surfaces are arranged so as to be parallel to the first direction. 6.
A plurality of second element isolation regions provided in the semiconductor substrate so as to extend in a second direction intersecting the first direction and partitioning the active region into a plurality of element formation regions; The semiconductor device according to claim 1, comprising: a semiconductor device according to claim 1.
7. The semiconductor according to claim 1, further comprising a bit line that is electrically connected to the second impurity diffusion region and extends in a direction intersecting the gate electrode. 8. apparatus.
A second impurity diffusion region provided on the semiconductor substrate between the pair of gate electrode trenches arranged so that the second side surfaces face each other and connected to a bit line;
The semiconductor device according to claim 9, wherein a depth of the second impurity diffusion region is shallower than a bottom portion of the gate electrode trench and deeper than an upper portion of the fin portion.
The portion of the semiconductor substrate that is in contact with the second side surface and that is in contact with the second impurity diffusion region is not a channel region of the first and second transistors. The semiconductor device according to 9 or 10.
A portion of the semiconductor substrate located below the bottom surface of the first impurity diffusion region and in contact with the first side surface;
A portion in contact with the bottom of the gate electrode trench;
A portion in contact with the second side surface and a portion not in contact with the second impurity diffusion region;
The semiconductor device according to claim 9, wherein the fin portion is a channel region of the first and second transistors.
The thickness of the gate insulating film is in the range of 4 to 6 nm in terms of silicon oxide film;
The work function of the gate electrode is in the range of 4.6 to 4.8 eV;
13. The semiconductor device according to claim 9, wherein a threshold voltage of one or both of the first and second transistors is 0.8 to 1.0 V. 13.
An impurity having a conductivity type different from that of the semiconductor substrate is selectively ion-implanted into the semiconductor substrate between the pair of gate electrode grooves formed so that the second side surfaces face each other. Forming an impurity diffusion region, and
A method of manufacturing a semiconductor device, wherein the height from the bottom of the gate electrode trench to the top of the fin portion is in the range of 10 to 40 nm.
15. The semiconductor device according to claim 14, wherein a depth of the second impurity diffusion region is shallower than a bottom portion of the gate electrode trench and deeper than an upper portion of the fin portion.
The semiconductor substrate extends above the second impurity diffusion region formed in a portion disposed between the pair of gate electrode trenches in a direction intersecting the gate electrode, and the first 16. The method of manufacturing a semiconductor device according to claim 14, further comprising a step of forming a bit line electrically connected to the two impurity diffusion regions.
The method for manufacturing a semiconductor device according to claim 14, further comprising a step of forming a capacitor on the capacitor contact pad.
JP2011102400A 2011-04-28 2011-04-28 Semiconductor device and manufacturing method of the same Ceased JP2012234964A (en)
JP2011102400A JP2012234964A (en) 2011-04-28 2011-04-28 Semiconductor device and manufacturing method of the same
US13/458,298 US9041085B2 (en) 2011-04-28 2012-04-27 Semiconductor device and method of forming the same
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JP2012234964A true JP2012234964A (en) 2012-11-29
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