Source: http://www.google.com/patents/US4596010?ie=ISO-8859-1&dq=7,603,356
Timestamp: 2015-01-29 10:53:25
Document Index: 491653096

Matched Legal Cases: ['ART) 1631', 'ART 1511', 'ARTS 1511', 'ARTS 1511', 'ART 1511', 'ART 1631', 'ARTS 1512', 'ART 1512', 'ART 1921']

Patent US4596010 - Distributed packet switching arrangement - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn integrated packet switching and circuit switching system comprising a number of switching modules each connected to a corresponding plurality of user terminals. Each switching module includes a time-slot interchange unit for providing circuit-switched communication channels and a control unit that...http://www.google.com/patents/US4596010?utm_source=gb-gplus-sharePatent US4596010 - Distributed packet switching arrangementAdvanced Patent SearchPublication numberUS4596010 APublication typeGrantApplication numberUS 06/606,751Publication dateJun 17, 1986Filing dateMay 3, 1984Priority dateMay 3, 1984Fee statusPaidAlso published asCA1232665A1, DE3568120D1, EP0182812A1, EP0182812B1, WO1985005237A1Publication number06606751, 606751, US 4596010 A, US 4596010A, US-A-4596010, US4596010 A, US4596010AInventorsMark W. Beckner, James A. Davis, Eric J. Gausmann, Thomas L. Hiller, Philip D. Olson, Gilbert A. Van DineOriginal AssigneeAt&T Bell LaboratoriesExport CitationBiBTeX, EndNote, RefManPatent Citations (12), Non-Patent Citations (30), Referenced by (51), Classifications (7), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetDistributed packet switching arrangementUS 4596010 AAbstract An integrated packet switching and circuit switching system comprising a number of switching modules each connected to a corresponding plurality of user terminals. Each switching module includes a time-slot interchange unit for providing circuit-switched communication channels and a control unit that controls the operation of the time-slot interchange unit. Each switching module also includes a packet switching unit used both to provide packet-switched communication channels among the user terminals connected to that switching module, and to switch control information between the user terminals and the control unit to establish circuit-switched calls and packet-switched calls. A time-multiplexed switch interconnects the switching modules to provide circuit-switched communication channels and packet-switched communication channels between user terminals of different switching modules.
What is claimed is: 1. A switching system comprisinga plurality of switching modules each associated with a corresponding plurality of user terminals and inter-module connection means, each said switching module comprising circuit switching means for providing circuit-switched communication channels among its associated user terminals and between its associated user terminals and said intermodule connection means, and packet switching means connectible to said inter-module connection means for providing packet-switched communication channels among its associated user terminals and between its associated user terminals and said inter-module connection means, said inter-module connection means comprising means for interconnecting the circuit switching means of each of said switching modules for inter-module circuit-switched communication, and means for interconnecting the packet switching means of each of said switching modules for inter-module packet-switched communication. 2. A switching system in accordance with claim 1,each said switching module further comprising means for coupling said packet switching means to said circuit switching means and said circuit switching means further comprising means for providing predetermined communication channels between said coupling means and said inter-module connection means. 3. A switching system comprisinga plurality of switching modules each associated with a corresponding plurality of user terminals and inter-module connection means, each said switching module comprising circuit switching means for providing circuit-switched communication channels among its associated user terminals and between its associated user terminals and said intermodule connection means, and packet switching means comprising a plurality of packet switching nodes, at least a predetermined one of said nodes connectible to said inter-module connection means and certain ones of said nodes connectible to its associated user terminals, said packet switching means further comprising packet interconnect means for interconnecting said nodes to provide packet-switched communication channels among its associated user terminals and between its associated user terminals and the predetermined node of that switching module, said inter-module connection means comprising means for interconnecting the circuit switching means of each of said switching modules to provide circuit-switched communication channels between user terminals associated with different ones of said switching modules, and means for interconnecting the predetermined nodes of said switching modules to provide packet-switched communication channels between user terminals associated with different ones of said switching modules. 4. A switching system in accordance with claim 3, said means for interconnecting the predetermined nodes of said switching modules comprising means for connecting the predetermined node of each one of said switching modules to the predetermined node of each of the other ones of said switching modules.
CROSS-REFERENCE TO RELATED APPLICATION This application is related to the application of M. W. Beckner, J. A. Davis, E. J. Gausmann, T. L. Hiller, P. D. Olson, and G. A. Van Dine, Ser. No. 606,937 filed May 3, 1984, entitled "Integrated Packet Switching and Circuit Switching System", which is assigned to the assignee of the present invention.
TECHNICAL FIELD This invention relates to switching systems and, more particularly, to such systems that provide both packet switching and circuit switching service.
BACKGROUND OF THE INVENTION With the extensive use of personal computers and other data processing facilities both at home and in the office, a need exists for providing voice and data transmission and switching capabilities on a widespread basis. This has led to the development of the concept of an integrated services digital network (ISDN)--a switched communications network providing end-to-end digital connectivity among network users where voice and data services are provided over the same transmission and switching facilities. Because of the different characteristics of voice and data traffic--voice being typically continuous in one direction for relatively long intervals and tolerant of noise but sensitive to variations in delay, and data being bursty and sensitive to errors but tolerant of moderate delays and delay variations--two fundamentally different switching techniques have been traditionally applied. Circuit switching, where switched connections between users are dedicated for call duration, is the basis of the present-day switched voice telecommunication network. On the other hand, packet switching, where data packets from many calls share a single, high-speed line and are switched based on logical channel numbers included in the packets, was pioneered in the ARPANET network of the U.S. Department of Defense, and has now been implemented in a variety of public data networks.
SUMMARY OF THE INVENTION The aforementioned problem is solved and a technical advance is achieved in accordance with the principles of the invention in a switching arrangement wherein packet switching units are distributed to only those switching modules serving users requiring packet switching service, and each such unit advantageously provides packet-switched communication channels among the users served by that switching module without routing packets to a centralized entity. Only packet calls between users connected to different switching modules are completed via an inter-module connection unit that interconnects all the switching modules of the system.
GENERAL DESCRIPTION FIGS. 1 through 3, when arranged in accordance with FIG. 12, present a block diagram of an exemplary time division switching system illustrating the principles of the present invention. The system includes 27 switching modules, e.g., 501, 527, and a time-multiplexed switch 10 to provide circuit-switched communication channels among a plurality of conventional subscriber sets, e.g., 23 through 26. Each switching module includes a control unit which controls switching module operation including the establishment of circuit-switched channels by a time-slot interchange unit. For example, switching module 501 includes control unit 17 which controls the operation of time-slot interchange unit 11 and switching module 527 includes control unit 18 which controls the operation of time-slot interchange unit 12. The switching module control units, e.g., 17 and 18, and a central control 30 used to control the operation of time-multiplexed switch 10, communicate with each other via an interprocessor communication mechanism using predetermined control channels of time-multiplexed switch 10 and a control distribution unit 31 in a manner described in detail herein. When, for example, control unit 17 first detects an off-hook condition of subscriber set 23 and subsequently detects the dialing of a sequence of digits defining one of the other subscriber sets served by switching module 501, e.g., set 24, control unit 17 and central control 30 exchange control messages and control unit 17 thereafter effects the establishment of a bidirectional, circuit-switched communication channel between subscriber sets 23 and 24 by time-slot interchange unit 11 for the duration of a voice call between those sets 23 and 24. Further, when subscriber set 23 calls a subscriber set served by switching module 527, e.g., set 26, control units 17 and 18 and central control 30 exchange control messages to establish the call. Central control 30 writes instructions via a path 49 into a control memory 29 defining an available time-multiplexed switch 10 channel between time-slot interchange units 11 and 12. Control unit 17 effects the establishment by time-slot interchange unit 11 of a circuit-switched communication channel between subscriber set 23 and the available time-multiplexed switch 10 channel. Similarly, control unit 18 effects the establishment by time-slot interchange unit 12 of a circuit-switched communication channel between subscriber set 26 and the available time-multiplexed switch 10 channel. The switching system is of the time-space-time type with time-slot interchange unit 11 representing the first time stage, time-multiplexed switch 10 the space stage and time-slot interchange unit 12 the second time stage for the call from subscriber set 23 to subscriber set 26. The portion of the system described thus far is substantially as disclosed in U.S. Pat. No. 4,322,843 issued to H. J. Beuscher et al., on Mar. 30, 1982 and is described in detail later herein.
DETAILED DESCRIPTION FIG. 22 is a block diagram of a time division, circuit switching system substantially as disclosed in the above-cited Beuscher U.S. Pat. No. 4,322,843. The exemplary integrated packet switching and circuit switching system of FIG. 1 through 3 comprises the system of FIG. 22 to which four additional switching modules, 1000, 2000, 3000 and 4000, are added. The description which follows is arranged in two parts. First the FIG. 22 system is described. With that description as a foundation, the exemplary embodiment of the invention shown in FIG. 1 through 3 is then described.
FIG. 22 System The time division switching system of FIG. 22 is used to interconnect subscriber sets such as subscriber sets 23 through 26 and includes a time-multiplexed switch 10 comprising a time-shared space division switch having 64 input ports and 64 output ports. Also included are 27 time-slot interchange units of which representative time-slot interchange units 11 and 12 are specifically shown. Each time-slot interchange unit 11 and 12 includes a bidirectional time-slot interchanger. Additionally, each time-slot interchange unit 11 and 12 is connected to two input ports and two output ports of time-multiplexed switch 10. In the system of FIG. 22, time-slot interchange unit 11 is connected to two time-multiplexed switch input ports via time-multiplexed lines 13 and 14 and to two output ports, via time-multiplexed lines 15 and 16.
Exemplary Embodiment of the Invention An exemplary embodiment of the present invention, shown in FIGS. 1 through 3 arranged in accordance with FIG. 12, comprises the time division, circuit switching system of FIG. 22 into which four additional switching modules 1000, 2000, 3000, and 4000 are integrated. The additional switching modules are connected using input/output port pairs P55 through P62 of time-multiplexed switch 10. Only switching modules 1000 and 4000 are shown in detail in FIG. 2 and 3. A given switching module, e.g., 1000, provides both packet-switched communication channels and circuit-switched communication channels among the plurality of user terminals, e.g., 1001, 1002, connected thereto without transmitting such channels through time-multiplexed switch 10. Time-multiplexed switch 10 is only used for intermodule calls.
Switching Module 1000 Switching module 1000 (FIG. 2) includes two digital line units 1101 and 1102, a time-slot interchange unit 1011, a control unit 1017, a processor interface 1300 and a packet switching unit 1400. Time-slot interchange unit 1011 and control unit 1017 are substantially identical to time-slot interchange unit 11 and control unit 17 (FIG. 23) already described. Since in the present embodiment, the signaling between user terminals and control unit 1017 is done using message signaling via user D-channels, packet switching unit 1400 and processor interface 1300, the processor functions required in control unit 17 to detect on-hook and off-hook conditions, dialed digits, etc. are not required in control unit 1017. In control unit 17, the control interface 56 (FIG. 23) is used to convey control information to line units via path 27. In control unit 1017, the equivalent of control interface 56 is used to convey control information via a communication path 1027 to digital line units 1101 and 1102 and to packet switching unit 1400. Bus 1059, which is the equivalent of bus 59 in control unit 17 used for communication with processor 66, is also connected to processor interface 1300 and is the means by which signaling information is conveyed between user terminals and control unit 1017.
Digital Line Unit 1101 Digital line unit 1101 is shown in greater detail in FIG. 4. Each user access line, e.g., 1003, terminates on a separate one of a plurality of digital line circuits 1105. Recall that in the present embodiment user access line 1003 is a four-wire T-interface conveying a 192 kilobits per second bit stream in each direction on a separate pair of wires. Also recall that 144 kilobits per second are used to convey user information including message signaling and that the 144 kilobits per second comprises two 64 kilobits per second circuit-switched B-channels and one 16 kilobits per second packet-switched D-channel. User terminal 1001 transmits the 192 kilobits per second bit stream in 48-bit line frames at the rate of 4000 line frames per second. Each 48-bit line frame includes a framing bit that uses a bipolar violation to mark the start of a frame, various other control bits, DC balancing bits, superframe bits and spare bits and also includes two, 8-bit occurrences of each of the two B-channels and two, 2-bit occurrences of the single D-channel. Digital line circuit 1105 receives the 192 kilobits per second bit stream from user terminal 1001 via transformer coupling to provide DC isolation, common mode signal rejection and overvoltage protection. Digital line circuit 1105 detects the start of each line frame and thereafter stores the information from the two B-channels and the single D-channel in separate registers (not shown). Such received information is thereafter transmitted either to a time-slot assignment unit 1111 on a 32-channel bidirectional bus 1108 or to a second time-slot assignment unit 1112 on another 32-channel bidirectional bus 1109. The information defining the particular time slot or channel on one of the two buses 1108 or 1109 that each B-channel or D-channel is to be transmitted in, is determined based on information received from a line group controller 1106, which coordinates the operation of 16 of the digital line circuits 1105. A given time slot on one of the buses 1108 is used to transmit one 8-bit occurrence of one B-channel from one digital line circuit 1105 or one 2-bit occurrence of the D-channel from each of four of the digital line circuits 1105. Timeslot assignment unit 1111 receives information from each group of 16 line circuits 1105 via one of the buses 1108. Similarly, time-slot assignment unit 1112 receives information from each group of 16 line circuits 1105 via one of the buses 1109. The buses 1108 and 1109 can be load-shared in accordance with the assignments by the line group controllers 1106 defining the mapping between user B-channels and D-channels and time slots on the buses 1108 and 1109. The line group controllers 1106 in turn receive their information from a single line unit controller 1107 which communicates with control unit 1017 via communication path 1027 to initialize such mapping. Line unit controller 1107 also controls the operation of the time-slot assignment units 1111 and 1112. The function of the time-slot assignment units 1111 and 1112 is to place the time slots received from the digital line circuits 1105, on specified time slots of the 32-channel bidirectional data buses 1201 to time-slot interchange unit 1011 or on specified time slots of the 32-channel bidirectional data buses 1202 to packet switch unit 1400. Recall that the buses 1201 convey primarily B-channel information but that some D-channel information is conveyed thereon and subsequently transmitted in predetermined channels via time-slot interchange unit 1011 and bus 1205 to packet switching unit 1400. The buses 1202 convey only D-channel information directly to packet switching unit 1400.
Packet Switching Unit 1400 A more detailed diagram of packet switching unit 1400 and processor interface 1300 is presented in FIG. 5 through 11, arranged in accordance with FIG. 13. Packet switching unit 1400 includes six data fanout units 1600-0 through 1600-5 (FIG. 7) which distribute the time slots received on the buses 1202 from digital line units 1101 and 1102 and on the bus 1205 from time-slot interchange unit 1011, to 96 protocol handlers 1700-0 through 1700-95, only protocol handlers 1700-0, 1700-15, 1700-80 and 1700-95 being specifically shown in FIG. 8 and 9. Data fanout units 1600-0 through 1600-5 also transmit information received from the protocol handlers, in the assigned time slots on the buses 1202 to digital line units 1101 and 1102 and on the bus 1205 to time-slot interchange unit 1011. Each data fanout unit is associated with sixteen protocol handlers. For example, data fanout unit 1600-0 is associated with protocol handlers 1700-0 through 1700-15 and data fanout unit 1600-5 is associated with protocol handlers 1700-80 through 1700-95 The data fanout units 1600-0 through 1600-5 receive assignment information, referred to herein as assignment signals, concerning the mapping of time slots between the protocol handlers and the buses 1202 and 1205, from control unit 1017 via communication path 1027, a control fanout unit 1500 (FIG. 6) and a control bus 1501. The protocol handlers 1700-0 through 1700-95 receive, process and store packets from the D-channels of the user terminals associated therewith (or inter-module packets via bus 1205), and when enabled by packet interconnect 1800 (FIG. 10 and 11) transmit such stored packets to destination protocol handlers or, in the case of signaling packets, to processor interface 1300 (FIG. 5). Destination protocol handlers store the packets received from packet interconnect 1800 and subsequently transmit those packets in the D-channels of destination user terminals. Processor interface 1300, in response to signaling packets from protocol handlers, stores such signaling packets to be subsequently read by control unit 1017 via bus 1059. Processor interface 1300 also receives signaling information written via bus 1059 by control unit 1017, stores such information in signaling packets, and, when enabled by packet interconnect 1800, transmits the signaling packets to destination protocol handlers. At any given time, a number of the protocol handlers may be designated as spares. Such spare designation and other configuration and control information is transmitted by control unit 1017 via communication path 1027, control fanout unit 1500 and a control bus 1502 to packet interconnect 1800. Packet interconnect 1800 also distributes certain control information to specific protocol handlers via control buses 1702-0 through 1702-5 (FIG. 9). Packet interconnect 1800 includes six packet fanout units 1900-0 through 1900-5 (FIG. 11). Each packet fanout unit receives packets from and transmits packets to sixteen protocol handlers. For example, packet fanout unit 1900-0 receives packets from and transmits packets to protocol handlers 1700-0 through 1700-15 and packet fanout unit 1900-5 receives packets from and transmits packets to protocol handlers 1700-80 through 1700-95.
Data Fanout Unit 1600-0 Data fanout unit 1600-0 (FIG. 7) includes a multiplexer 1610 which receives the time slots from digital line units 1101 and 1102 on the 32-channel buses 1202 and from time-slot interchange unit 1011 on the 32-channel bus 1205 and transmits such received time slots on a single time-multiplexed line 1612 to a receive time-slot interchanger 1650. Receive time-slot interchanger 1650 performs the time-slot interchange function by transmitting the information received from multiplexer 1610, in predefined time slots on a time-multiplexed line 1613 to a demultiplexer 1620. The time-slot definitions used by receive time-slot interchanger 1650 are stored in a control RAM 1655 at system initialization or upon a subsequent system reconfiguration, by a processor 1632. Processor 1632 receives such time-slot definitions via a universal asynchronous receiver transmitter (UART) 1631, control bus 1501 and an associated UART 1511-0, from a processor 1510 included in control fanout unit 1500 (FIG. 6). Demultiplexer 1620 distributes the time slots on time-multiplexed line 1613 in a predetermined manner to sixteen, 32-channel bidirectional data buses 1601-0 through 1601-15 connected to the 16 protocol handlers 1700-0 through 1700-15 associated with data fanout unit 1600-0. Similarly, in the reverse direction, a multiplexer 1621 receives the time slots on the 32-channel buses 1601-0 through 1601-15 from protocol handlers 1700-0 through 1700-15 and transmits the received time slots on a single time-multiplexed line 1614 to a transmit time-slot interchanger 1653. In accordance with the time-slot definitions stored in control RAM 1655, transmit time-slot interchanger 1653 transmits the information received from multiplexer 1621 on a single time-multiplexed line 1615 to a demultiplexer 1611. Demultiplexer 1611 then distributes the time slots received on time-multiplexed line 1615 in a predetermined manner to the buses 1202 for transmission to the digital line units 1101 and 1102, and to bus 1205 for transmission to time-slot interchange unit 1011. Note that bus 1205 is connected to only one of the data fanout units, unit 1600-0. Data fanout unit 1600-0 receives timing signals from time-slot interchange unit 1011 via bus 1205 and distributes such timing signals to each of the data fanout units 1600-1 through 1600-5 as well as to time slot assignment and rate adapt units included in the protocol handlers, e.g., unit 1405 in protocol handler 1700-0 (FIG. 8), to properly time the operation of the various components therein. The distribution of timing signals is not shown in the drawing. Although the operation of data fanout unit 1600-0 is generally similar to that of time-slot interchange unit 11 (FIG. 23) already described, it is noted that whereas time-slot interchange unit 11 performs a circuit switching function, i.e., interchanging time slots to provide communication channels for calls, data fanout unit 1600-0 performs only a distribution function by mapping each time slot on the buses 1202 and 1205 to any specified time slot on the buses 1601-0 through 1601-15 on a relatively permanent basis and performs no switching function with respect to calls.
Protocol Handler 1700-0 Protocol handler 1700-0 (FIG. 8) includes a time-slot assignment and rate adapt unit 1405 which interfaces the bidirectional data bus 1601-0 from data fanout unit 1600-0, to 32 HDLC circuits 1406-0 through 1406-31. Each HDLC circuit, e.g., 1406-0, is used to terminate the HDLC link-level protocol from the 16 kilobits per second D-channel of one user terminal and is also referred to herein as a protocol processor. Recall that a given channel or time slot on data bus 1601-0 is used for up to four D-channels, i.e., eight bits comprised of two bits from each D-channel. Time slot assignment and rate adapt unit 1405 includes 32 incoming shift registers (not shown) and 32 outgoing shift registers (not shown), one incoming shift register and one outgoing shift register for each HDLC circuit. A given incoming shift register receives two bits from a predetermined time slot on data bus 1601-0 during each 125-microsecond frame. After four such frames, the given incoming shift register has accumulated eight bits and unit 1405 transmits a clock signal to the associated HDLC circuit, e.g., 1406-0, and the accumulated eight bits are transmitted into HDLC circuit 1406-0. Since the given incoming shift register receives information from only one time slot per 125-microsecond frame, the bits can be transmitted from the incoming shift register to HDLC circuit 1406-0 at a lower rate than they were received from data bus 1601-0. In the reverse direction, HDLC circuit 1406-0 transmits eight bits to a given outgoing shift register, and those bits are inserted in the predetermined time slot on data bus 1601-0. Two bits are inserted during each occurrence of the predetermined time slot over four 125-microsecond frames. Time-slot assignment and rate adapt unit 1405 can also be reconfigured such that a given HLDC circuit can terminate D-channels at higher rates, e.g., 64 or 256 kilobits per second, using multiple incoming and outgoing shift registers and multiple time slots.
Processor Interface 1300 A substantial portion of processor interface 1300 (FIG. 5) is identical to protocol handler 1700-0. Specifically, EPROM 1341, bus 1340, processor 1342, conductors 1344 and 1345, communications controller 1343, selector 1373, dual port RAM controller 1371, RAM 1370 and error detection and correction unit 1372 are identical to the corresponding elements of protocol handler 1700-0 that are numbered exactly 100 greater. However, instead of receiving information from 32 HDLC circuits as does RAM 1470 in protocol handler 1700-0, RAM 1370 of processor interface 1300 receives information from control unit 1017 via bus 1059 and a buffer 1352. An address counter 1351 is used by control unit 1017 as a means of indirectly addressing locations in RAM 1370. For example, to write certain control information into RAM 1370, control unit 1017 writes the address of the first RAM 1370 buffer to be used to store such information, into address counter 1351. As the first RAM 1370 buffer is filled, address counter 1351 is automatically incremented to define the locations of that buffer. Processor 1342 can be reset by control unit 1017 to reinitialize the system via one conductor of bus 1059.
Packet Interconnect 1800 The protocol handlers 1700-0 through 1700-95 as well as processor interface 1300 and a duplicate processor interface (not shown) are each connected to packet interconnect 1800 (FIG. 10 and 11) by means of a six-conductor bus (or alternatively, a bus comprising six differential pairs). (The duplicate processor interface is used to interface packet interconnect 1800 with a duplicate control unit (not shown) used to control switching module 1000 upon a failure of control unit 1017.) Protocol handlers 1700-0 through 1700-95 are connected to packet interconnect 1800 by the buses 1701-0 through 1701-95. Processor interface 1300 and the duplicate processor interface are connected to packet interconnect 1800 by the buses 1301 and 1302. Each of the buses 1701-0 through 1701-95, 1301 and 1302 is used to transmit three signals to packet interconnect 1800 (a Request To Send (RTS) signal, a Transmit Clock (TC) signal and a Transmit Data (TD) signal) and to receive three signals from packet interconnect 1800 (a Clear To Send (CTS) signal, a Receive Clock (RC) signal and a Receive Data (RD) signal). Protocol handler 1700-0, for example, operates as follows to transmit a packet via packet interconnect 1800. When the communications controller 1443 of protocol handler 1700-0 determines that a packet is ready for transmission to packet interconnect 1800, it transmits a logic zero RTS signal to packet interconnect 1800. Packet interconnect 1800 subsequently returns a logic zero CTS signal to protocol handler 1700-0. In response, the communications controller 1443 of protocol handler 1700-0 transmits the packet as the TD signal to packet interconnect 1800 as well as the bit rate clock as the TC signal. By the operation of packet interconnect 1800, only one protocol handler or processor interface is allowed to transmit at a time. The TD and TC signals transmitted by protocol handler 1700-0 are received by each of the protocol handlers 1700-0 through 1700-95 as well as processor interface 1300 and the duplicate processor interface as their RD and RC signals, respectively. However, typically only one destination is defined by a physical destination address at the beginning of the packet, and only that destination will use the RC signal to clock the bits of the packet into its communication controller for subsequent storage.
Control Fanout Unit 1500 Control fanout unit 1500 (FIG. 6) comprises a processor 1510, which communicates with control unit 1017 via communication path 1027, and ten UARTS 1511-0 through 1511-5 and 1512-0 through 1512-5. Each of the UARTS 1511-0 through 1511-5 communicates with an associated UART in one of the data fanout units 1600-0 through 1600-5. For example, UART 1511-0 communicates with UART 1631 of data fanout unit 1600-0 via a portion of control bus 1501 to allow processor 1510 to control processor 1632. Such control includes, for example, defining the mapping of time slots between the buses 1202 and 1205 from digital line units 1101 and 1102 and time-slot interchange unit 1011, to the buses 1601-0 through 1601-15 to protocol handlers 1700-0 through 1700-15. Each of the UARTS 1512-0 through 1512-5 communicates with an associated UART in one of the packet fanout units 1900-0 through 1900-5. For example, UART 1512-0 communicates with UART 1921 of packet fanout unit 1900-0 via a portion of control bus 1502 to allow processor 1510 to control processor 1922. Such control includes the definition of which ones of the protocol handlers 1700-0 through 1700-15 and which one of the duplicate communications controllers in each protocol handler are to be designated as active.
Circuit-Switched Calls The method of establishing circuit-switched calls varies from the method previously described with respect to FIG. 27 only in that message signaling is used between user terminals and the switching system and in that a given user terminal can have two circuit-switched calls to different parties active simultaneously using the two B-channels. Message signaling is implemented in switching module 1000 (FIG. 2) by transmitting signaling packets on the user D-channel to the associated protocol handler and switching those packets via packet interconnect 1800 to processor interface 1300. The signaling information is then read from processor interface 1300 by control unit 1017. Control information from control unit 1017 is transmitted in signaling packets by processor interface 1300 via packet interconnect 1800 to a given protocol handler and then to one of its associated user D-channels. A call between user terminal 1001 and subscriber set 23, for example, involves message signaling within switching module 1000 between the D-channel of user terminal 1001 and control unit 1017 at one end of the call and conventional in-band signaling within switching module 501 between subscriber set 23 and control unit 17 at the other end of the call.
Intra-Module Packet-Switched Call Example The following is example describing the setup and removal of an intra-module packet-switched call between user terminals 1001 and 1002. The necessary communications are indicated in FIG. 15 by a line, terminating with an arrowhead to indicate its direction, having an associated letter (A) through (M). To initiate the call, user terminal 1001 transmits a call request packet (A) in logical channel LCN1, to its associated protocol handler 1700-0. Protocol handler 1700-0 processes the call request packet including the task of verifying that the logical channel number LCN2, of user terminal 1001 is presently idle. Protocol handler 1700-0 selects an internal logical channel number (ILCN), e.g., ILCN3, to be associated with the call and to be used by the destination protocol handler in transmitting packets to protocol handler 1700-0. Protocol handler 1700-0 then stores an entry in its routing table mapping ILCN3 to LCN2 of user terminal 1001. (The entry is the upper entry in the protocol handler 1700-0 routing table shown in FIG. 17. The underscoring of ILCN3 in that entry indicated that protocol handler 1700-0 made the selection of ILCN3.) Protocol handler 1700-0 then transmits a packet origination request (B) via packet interconnect 1800 to processor interface 1300. The packet origination request defines the originating user terminal 1001, the called directory number and ILCN3 selected for the call by protocol handler 1700-0. The packet origination request is then read (C) from processor interface 1300 by control unit 1017. Control unit 1017 inserts the information of the packet origination request into a control message (D) and transmits that control message via time-slot interchange unit 1011, the predetermined control channel 55 of time-multiplexed switch 10 and via control distribution unit 31 to central control 30. Central control 30 translates the called directory number which, in the present example, defines user terminal 1002. Central control 30 then transmits a packet termination request (E) defining the called user terminal 1002, via control distribution unit 31, the time-multiplexed switch 10 control channel 55 and time-slot interchange unit 1011 to control unit 1017. Control unit 1017 maps the called user terminal 1002 to its associated protocol handler, e.g., 1700-95, and verifies that protocol handler 1700-95 and user terminal 1002 are both presently in service. Control unit 1017 then forwards the packet termination request (F) on to processor interface 1300. Based on the information defining the destination protocol handler 1700-95, processor interface 1300 transmits the packet termination request (G) via packet interconnect 1800 to protocol handler 1700-95. In response, protocol handler 1700-95 selects an internal logical channel number, e.g., ILCN8, it will associate with the call. Protocol handler 1700-95 stores an entry in its routing table (FIG. 17) mapping ILCN8 to LCN2 of user terminal 1002. Protocol handler 1700-95 then transmits a packet path setup message (H) containing information defining both ILCN3 and ILCN8, via packet interconnect 1800 to protocol handler 1700-0. In response, protocol handler 1700-0 stores a second entry in its routing table (FIG. 17) mapping LCN2 of user terminal 1001 to ILCN8 and protocol handler 1700-95. Then protocol handler 1700-0 transmits a packet setup complete message (I) via packet interconnect 1800 to protocol handler 1700-95. In response, protocol handler 1700-95 stores a second entry in its routing table (FIG. 17) mapping LCN2 of user terminal 1002 to ILCN3 and protocol handler 1700-0. Protocol handler 1700-95 then transmits an incoming call packet (J) to user terminal 1002. User terminal 1002 returns a call accepted packet (K) to protocol handler 1700-95, which, in response, transmits a packet path connected indication (L) via packet interconnect 1800 to protocol handler 1700-0. Finally, protocol handler 1700-0 transmits a call connected packet (M) to user terminal 1001 and the packet-switched communication channel between user terminals 1001 and 1002 has been established.
Inter-Module Packet-Switched Call Example The establishment of an inter-module packet-switched call from user terminal 1001 to user terminal 4001 involves the coordination of two protocol handlers, 1700-0 and 1700-1, in packet switching unit 1400 and two protocol handlers, 4700-0 and 4700-1, in packet switching unit 4400. To initiate the call, user terminal 1001 transmits a call request packet in logical channel LCN1, to its associated protocol handler 1700-0. Protocol handler 1700-0 processes the call request packet including the task of verifying that the logical channel number LCN2, of user terminal 1001 is presently idle. Protocol handler 1700-0 selects an internal logical channel number (ILCN), e.g., ILCN9, to be associated with the call and to be used by the inter-module protocol handler 1700-1 in transmitting packets to protocol handler 1700-0. Protocol handler 1700-0 then stores an entry in its routing table mapping ILCN9 to LCN2 of user terminal 1001 (FIG. 18). Protocol handler 1700-0 then transmits a packet origination request via packet interconnect 1800 to processor interface 1300. The packet origination request defines the originating user terminal 1001, the called directory number and ILCN9 selected for the call by protocol handler 1700-0. The packet origination request is then read from processor interface 1300 by control unit 1017. Control unit 1017 inserts the information of the packet origination request into a control message and transmits that control message via time-slot interchange unit 1011, the predetermined control channel 55 of time-multiplexed switch 10 and via control distribution unit 31 to central control 30. Central control 30 translates the called directory number which, in the present example, defines user terminal 4001. Central control 30 then transmits a packet termination request defining the called user terminal 4001, via control distribution unit 31, the time-multiplexed switch 10 control channel 61 and time-slot interchange unit 4011 to control unit 4017. Control unit 4017 maps the called user terminal 4001 to its associated protocol handler, e.g., 4700-0, and verifies that protocol handler 4700-0 and user terminal 4001 are both presently in service. Control unit 4017 then forwards the packet termination request on to processor interface 4300. Based on the information defining the destination protocol handler 4700-0, processor interface 4300 transmits the packet termination request via packet interconnect 4800 to protocol handler 4700-0. Protocol handlers 4700-0 determines based on a parameter in the packet termination request that the call is an intermodule call. Protocol handler 4700-0 thereafter exchanges control messages with the inter-module protocol handler 4700-1 to establish a packet-switched channel therebetween. Subsequently protocol handler 4700-1 exchanges control messages with the inter-module protocol handler 1700-1 in switching module 1000 and establishes a channel between the two inter-module protocol handlers. The communications between protocol handlers 4700-1 and 1700-1 are transmitted via the four predetermined channels of bus 4205, time-slot interchange unit 4011, time-multiplexed switch 10 channels 109 through 112 between input/output port pairs P61 and P55, time-slot interchange unit 1011 and the four predetermined channels of bus 1205 to protocol handler 1700-1. Recall that the predetermined channels between protocol handlers 4700-1 and 1700-1 can be used to convey packets at 256 kilobits per second, 64 kilobits per second or various other rates. Finally, protocol handler 1700-1 exchanges control messages with protocol handler 1700-0 to complete the packet-switched channel from protocol handler 4700-0 to protocol handler 1700-0. The additional steps required to set up the call are the same as in the intra-module call example described above.
Operator Services One or more of the switching modules, e.g., module 1000, of the system can be used to interface with telephone operator position terminals to provide operator services such as directory assistance and toll and assistance service, to customers served by the other switching modules of the system. For example, if switching module 1000 is used to provide such operator services, and the user terminals connected to module 1000, e.g., terminals 1001 and 1002, are operator position terminals, a digital conference circuit is connected to time-slot interchange unit 1011 to bridge available operator position terminals with subscriber sets or user terminals either directly connected to other switching modules or connected from other switching systems via digital or analog trunks. For example, a calling party, e.g., subscriber set 23, is connected via line unit 19, time-slot interchange unit 11, time-multiplexed switch 10 and time-slot interchange unit 1011 to the digital conference circuit. The called party, e.g., user terminal 4001, is connected via digital line unit 4101, time-slot interchange unit 4011, time-multiplexed switch 10 and time-slot interchange unit 1011 to the digital conference circuit. The operator position terminal, i.e., user terminal 1001, is connected via digital line unit 1101 and time-slot interchange unit 1011 to the digital conference circuit to bridge an operator with the calling and called parties. The message signaling between terminal 1001 and control unit 1017 includes keystroke messages transmitted by terminal 1001 in response to the depression of the various functional keys on terminal 1001 used in the provision of operator services. The general principles concerning the provision of operator services are described in issues of the Bell System Technical Journal of December 1970, July-August 1979 and March 1983.
First Alternative Embodiment In a first alternative embodiment, the switching modules 1000, 2000, 3000 and 4000 are interconnected with respect to packet traffic, in the star topology of FIG. 20. Each switching module 1000, 2000 and 3000 does intra-module packet switching and uses four time-multiplexed switch 10 channels to switch packets to and from switching module 4000. Switching module 4000 also does intra-module packet switching but uses four time-multiplexed switch 10 channels to each of the switching modules 1000, 2000 and 3000 to convey packets and performs packet switching for inter-module packet calls among modules 1000, 2000, 3000 and 4000. Alternatively, switching module 4000 could be used solely for intermodule packet switching. Under some circumstances, e.g., in systems requiring many such modules, the implementation of the star topology of FIG. 20 uses the circuit switching resources of time-multiplexed switch 10 more efficiently than a similar implementation of the mesh topology of FIG. 19. However, use of the star topology may increase the total packet transmission delay.
Second Alternative Embodiment In a second alternative embodiment, a packet switching ring network 5000, is added to the system of FIG. 1 through 3 to switch both inter-module and intramodule packet calls. An example of such a network is the network of the Western Electric No. 1 PSS system described the paper, "No. 1 PSS: Number One Packet Switching System Service Capabiliries and Architecture" by J. C. Ehlinger and R. W Stubblefield published in the record of the IEEE conference on Communications: Integrating Communication for World Progress (ICC '83) held in June 1983. FIG. 21 shows only the additions and changes to the system of FIG. 1 through 3 for this second alternative embodiment. The packet switching units 1400, 2400, 3400 and 4400 represent the packet switching units in the switching modules 1000, 2000, 3000 and 4000, respectively, of FIG. 1 through 3. Central control 30, in addition to the communication link 32 (FIG. 3) has a second communication link 5005 (FIG. 21) used to control ring network 5000. Each of the packet switching units is connected to ring network 5000 by means of a plurality of digital transmission facilities 5002, e.g., the 24-channel T1 carrier system disclosed in the J. H. Green et. al., U.S. Pat. No. 4,059,731. A given transmission facility 5002 is interfaced to ring network 5000 via a digital facility interface 5003 and to a given packet switching unit via a digital facility interface 5001. Each digital facility interface 5001 is connected via a 32-channel bidirectional data bus 5004 to one of the data fanout unit included in the packet switching unit. However only 24 of the 32 bus 5004 channels are used. In packet switching unit 1400, for example, each protocol handler is associated with one channel on one of the facilities 5002. The protocol handlers respond to signaling packets from user terminals by switching those packets to control unit -1017 (FIG. 2) as before. However, the protocol handlers respond to data packets by transmitting them on the associated facility 5002 channels at a 64 kilobits per second rate. Ring network 5000 determines by communicating with central control 30, the appropriate channels of the facilities 5002 in which the data packets are to be returned such that they are received by the correct destination protocol handlers to be switched to the destination user terminals. Virtual circuits are established in ring network 5000 between the incoming channels of the facilities 5002 and the outgoing channels thus determined.