Source: http://www.google.com/patents/US6993617?dq=6,606,102
Timestamp: 2016-07-28 10:59:11
Document Index: 366628704

Matched Legal Cases: ['ART) 195', 'ART) 195', 'ART) 195', 'ART 16550', 'ART 16550', 'ART 16550']

Patent US6993617 - System-on-a-chip having an on-chip processor and an on-chip dynamic random ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA system-on-a-chip device is provided, the system-on-a-chip device comprising an on-chip processor and an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor. The system-on-a-chip device also comprises at least one on-chip input/output (I/O) bus capable of...http://www.google.com/patents/US6993617?utm_source=gb-gplus-sharePatent US6993617 - System-on-a-chip having an on-chip processor and an on-chip dynamic random access memory (DRAM)Advanced Patent SearchPublication numberUS6993617 B2Publication typeGrantApplication numberUS 10/393,865Publication dateJan 31, 2006Filing dateMar 21, 2003Priority dateMay 1, 2002Fee statusPaidAlso published asUS20030208653Publication number10393865, 393865, US 6993617 B2, US 6993617B2, US-B2-6993617, US6993617 B2, US6993617B2InventorsLawrence Butcher, Duane Northcutt, Marc Schneider, Jerry Wall, James Hanko, Alan Ruberg, Satyanarayana Simha, Michael E. Duboce, Arvind SrinivasanOriginal AssigneeSun Microsystems, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (13), Non-Patent Citations (3), Referenced by (11), Classifications (11), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSystem-on-a-chip having an on-chip processor and an on-chip dynamic random access memory (DRAM)
US 6993617 B2Abstract
A system-on-a-chip device is provided, the system-on-a-chip device comprising an on-chip processor and an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor. The system-on-a-chip device also comprises at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM).
1. A system-on-a-chip device consisting of:
an on-chip processor;
an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor;
an on-chip peripheral component interconnect (PCI) input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM);
an on-chip arbiter capable of communicating with the component interconnect (PCI) input/output (I/O) bus;
an on-chip expansion bus (E-bus) input/output (I/O) bus;
an on-chip expansion bus (E-bus) controller capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;
an on-chip Ethernet controller;
an on-chip universal serial bus Host controller;
an on-chip universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;
an on-chip Smart Card Interface (SCI) universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;
an on-chip I2C universal asynchronous receiver/transmitter (UART) capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;
an on-chip GPIO capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;
an on-chip joint test access group (JTAG) device;
an on-chip AC97 interface capable of communicating with the on-chip expansion bus (E-bus) input/output (I/O) bus;
an on-chip private flash bus capable of latching configuration options at power-up;
a first on-chip peripheral component interconnect (PCI) controller capable of communicating with the on-chip peripheral component interconnect (PCI) input/output (I/O) bus, the on-chip memory controller, the on-chip processor, and the on-chip dynamic random access memory (DRAM);
a second on-chip peripheral component interconnect (PCI) controller capable of communicating with the on-chip peripheral component interconnect (PCI) input/output (I/O) bus, the on-chip E-bus controller, the on-chip Ethernet controller, and the on-chip USB Host controller;
a first on-chip phase-lock loop (PLL) clock generator capable of sending a signal to the on-chip processor; an
a second on-chip phase-lock loop(PLL) clock generator capable of sending a signal to the at least one on-chip peripheral component interconnect (PCI) controller.
2. A system-on-a-chip device consisting of:
an on-chip processor consisting of a central processing unit core consisting of one of a V8 or V9 architecture capable of executing a respective V8 or V9 Sparc instruction set, the architecture having a central processing unit clock;
an on-chip dynamic random access memory capable of communicating with the on-chip processor;
at least one on-chip input/output bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory, the on-chip input/output bus consisting of a peripheral component interconnect bus;
an on-chip memory controller capable of communicating with the on-chip processor, the on-chip dynamic random access memory, and the at least one on-chip input/output bus;
an on-chip peripheral component interconnect capable of communicating with the peripheral component interconnect bus, the on-chip peripheral component interconnect having an on-chip peripheral component interconnect clock;
an on-chip peripheral component interconnect controller capable of communicating on-chip and off-chip, the on-chip peripheral component interconnect controller being capable of communicating with the on-chip memory controller and the at least one on-chip input/output bus and with the on-chip dynamic random access memory via the on-chip memory controller;
an on-chip interrupt controller capable of communicating with the on-chip processor;
an on-chip arbiter capable of communicating with the on-chip input/output bus;
a microSPARC IIep device consisting of the on-chip processor, the on-chip dynamic random access memory, the on-chip memory controller, the on-chip peripheral component interconnect controller, the on-chip interrupt controller, and the on-chip arbiter;
a first on-chip phase-lock loop clock generator capable of sending a signal to the central processing unit clock of the on-chip processor;
a second on-chip phase-lock loop clock generator capable of sending a signal to the on-chip peripheral component interconnect controller to the on-chip peripheral component interconnect clock;
an on-chip expansion bus input/output bus;
an on-chip expansion bus input/output bus controller capable of communicating with the on-chip expansion bus input/output bus;
an on-chip external controller device consisting of the on-chip expansion bus input/output bus controller, the on-chip Ethernet controller, and the on-chip universal serial bus Host controller;
an on-chip peripheral component controller capable of communicating with the on-chip external controller device and the on-chip peripheral component interconnect bus;
an on-chip input/output core consisting of the on-chip peripheral component controller and the on-chip external controller device;
an on-chip Joint Test Access group device;
an on-chip audio bus interface capable of communicating with the on-chip expansion bus input/output bus, the on-chip audio bus interface consisting of an Intel AC97;
an on-chip multi-master bus consisting of an Intel-IV universal asynchronous receiver/transmitter capable of communicating with the on-chip expansion bus input/output bus;
an on-chip Smart Card Interface universal asynchronous receiver/transmitter capable of communicating with the on-chip expansion bus input/output bus;
an on-chip general purpose input/output interface capable of communicating with the on-chip expansion bus input/output bus;
an on-chip universal asynchronous receiver/transmitter capable of communicating with the on-chip expansion bus input/output bus; and
an on-chip private flash bus capable of latching configurations at power up.
This patent application claims priority pursuant to 35 U.S.C. �119(e) to U.S. provisional patent application Ser. No. 60/376,705, filed May 1, 2002, for SYSTEM-ON-A-CHIP HAVING AN ON-CHIP PROCESSOR AND AN ON-CHIP DYNAMIC RANDOM ACCESS MEMORY (DRAM).
This invention relates generally to computer hardware and, more particularly, to a device combining a processor, a dynamic random access memory (DRAM) and an input/output (I/O) bus in a system-on-a-chip.
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors, as well as a continual reduction in the lengths of the interconnections connecting the semiconductor devices that comprise the integrated circuit devices. Thus, there is a constant drive to reduce the size, or scale, of the components and/or the interconnection lengths of atypical integrated circuit device to increase the overall speed of the integrated circuit device, as well as devices incorporating such integrated circuit devices.
However, the incorporation of many different components, such as a processor and an input/output (I/O) bus and the like onto a single chip, to provide a reduction in the interconnection lengths connecting these various components, has been frustrated by the inability to provide adequate memory storage capacity onto the same chip. For example, conventional integrated circuit devices typically provide a dynamic random access memory (DRAM) chip separate and apart from the chip having the processor thereon. This leads to an increase in the interconnection lengths connecting the processor and the dynamic random access memory (DRAM) and decreases the overall speed of the conventional integrated circuit device.
In one aspect of the present invention, a system-on-a-chip device is provided, the system-on-a-chip device comprising an on-chip processor and an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor. The system-on-a-chip device also comprises at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM).
In another aspect of the present invention, a system-on-a-chip method is provided, the system-on-a-chip method comprising providing an on-chip processor and providing an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor. The system-on-a-chip method also comprises providing at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM).
FIG. 1 schematically illustrates a system-on-a-chip device in accordance with various exemplary embodiments of the present invention;
FIGS. 2–14 schematically illustrate various off-chip connections for respective on-chip components shown in FIG. 1; and
FIGS. 15–20 schematically illustrate various embodiments of a system-on-a-chip method according to the present invention.
Illustrative embodiments of a method and a device according to the present invention are shown in FIGS. 1–20. As shown in FIG. 1, in various illustrative embodiments of the present invention, a system-on-a-chip device 100 is provided, the system-on-a-chip device 100 comprising an on-chip processor 110, an on-chip dynamic random access memory (DRAM) 125 and at least one on-chip input/output (I/O) bus 140. In one embodiment, the on-chip processor 110 may comprise a central processing unit (CPU) core 110 having an architecture capable of executing one or more instruction sets. For example, the CPU core 110 may have a V8 architecture capable of executing the Sparc V8 instruction set. For another example, the CPU core 110 may have a V9 architecture capable of executing the Sparc V9 instruction set.
The on-chip dynamic random access memory (DRAM) 125 may be an embedded dynamic random access memory (eDRAM) having about 4 megabytes (4 MB) of embedded dynamic random access memory (eDRAM). The on-chip input/output (I/0) bus 140 may be a peripheral component interconnect (PCI) bus 140, connected, as shown in FIG. 3, to a peripheral component interconnect (PCI) 300, as indicated by the box labeled B in FIGS. 1 and 3.
The system-on-a-chip device 100 may further comprise an on-chip memory controller 115. The on-chip memory controller 115 may be capable of communicating with the on-chip processor 110 and the on-chip dynamic random access memory (DRAM) 125, as indicated by the double arrows in FIG. 1 connecting the on-chip memory controller 115, the on-chip processor 110 and the on-chip dynamic random access memory (DRAM) 125. The on-chip memory controller 115 may enable the on-chip dynamic random access memory (DRAM) 125 to be capable of communicating with the on-chip processor 110. The on-chip memory controller 115 may be connected, as shown in FIG. 2, to a programmable read only memory (PROM) device 200, as indicated by the box labeled A in FIGS. 1 and 2.
The system-on-a-chip device 100 may further comprise an on-chip peripheral component interconnect (PCI) controller 120. The on-chip peripheral component interconnect (PCI) controller 120 may be used to talk both on-chip and off-chip. The on-chip peripheral component interconnect (PCI) controller 120 may be capable of communicating with the on-chip memory controller 115 and the on-chip input/output (I/O) bus 140, as indicated by the double arrows in FIG. 1 connecting the on-chip peripheral component interconnect (PCI) controller 120, the on-chip memory controller 115 and the on-chip input/output (I/O) bus 140. The on-chip peripheral component interconnect (PCI) controller 120 may enable the on-chip dynamic random access memory (DRAM) 125 and/or the on-chip processor 110 to be capable of communicating with the on-chip input/output (I/O) bus 140 by way of the on-chip memory controller 115. The on-chip input/output (I/O) bus 140 may be connected, as shown in FIG. 3, to a peripheral component interconnect (PCI) device 300, as indicated by the box labeled B in FIGS. 1 and 3.
The system-on-a-chip device 100 may further comprise an on-chip interrupt controller 105. The on-chip interrupt controller 105 may be capable of communicating with the on-chip processor 110, as indicated by the double arrows in FIG. 1 connecting the on-chip interrupt controller 105 and the on-chip processor 110.
The system-on-a-chip device 100 may further comprise an on-chip arbiter 130. The on-chip arbiter 130 may be capable of communicating with the on-chip input/output (I/O) bus 140, as indicated by the double arrows in FIG. 1 connecting the on-chip arbiter 130 and the on-chip input/output (I/O) bus 140.
In various illustrative embodiments, the system-on-a-chip device 100 may comprise a microSPARC IIep device 135. The microSPARC IIep device 135 may comprise the on-chip processor 110, the on-chip dynamic random access memory (DRAM) 125, the on-chip memory controller 115, the on-chip peripheral component interconnect (PCI) controller 120, the on-chip interrupt controller 105 and the on-chip arbiter 130.
The system-on-a-chip device 100 may further comprise a first phase-lock loop (PLL) clock generator 170 capable of sending a signal to the on-chip processor 110 and a second phase-lock loop (PLL) clock generator 175 capable of sending a signal to the on-chip peripheral component interconnect (PCI) controller 120. The first phase-lock loop (PLL) clock generator 170 may receive a signal from a multiplexer 1020. The multiplexer 1020, in turn, may receive a signal, as shown in FIG. 6, from a universal serial bus (USB) clock (USB Clk) 600, as indicated by the box labeled E in FIGS. 1 and 6. The multiplexer 1020 may also receive a signal, as shown in FIG. 7, from a peripheral component interconnect clock (PCI Clk) 700, as indicated by the box labeled F in FIGS. 1 and 7. The first phase-lock loop (PLL) clock generator 170 may send a signal to the on-chip processor 110, to a central processing unit (CPU) clock, for example, as indicated by the arrow pointing away from the first phase-lock loop (PLL) clock generator 170.
The second phase-lock loop (PLL) clock generator 175 may also receive a signal, as shown in FIG. 7, from the peripheral component interconnect clock (PCI Clk) 700, as indicated by the box labeled F in FIGS. 1 and 7. The second phase-lock loop (PLL) clock generator 175 may send a signal to the on-chip peripheral component interconnect (PCI) controller 120, to an on-chip peripheral component interconnect (PCI) clock, for example, as indicated by the arrow pointing away from the second phase-lock loop (PLL) clock generator 175.
In various illustrative embodiments, the system-on-a-chip device 100 may comprise an on-chip expansion bus (E-Bus) input/output (I/O) bus 180 capable of communicating with an on-chip expansion bus (E-Bus) controller 155, as indicated by the double arrows in FIG. 1 connecting the on-chip expansion bus (E-Bus) input/output (I/O) bus 180 and the on-chip expansion bus (E-Bus) controller 155. The on-chip expansion bus (E-Bus) input/output (I/O) bus 180 may be connected, as shown in FIG. 8, to an off-chip expansion bus industry standard architecture (E-Bus/ISA) interface device 800, as indicated by the box labeled G in FIGS. 1 and 8.
The system-on-a-chip device 100 may further comprise an on-chip Ethernet controller 160. The on-chip Ethernet controller 160 may be connected, as shown in FIG. 4, to an Ethernet device 400, as indicated by the box labeled C in FIGS. 1 and 4.
The system-on-a-chip device 100 may further comprise an on-chip universal serial bus (USB) Host controller 165. The on-chip USB Host controller 16 may be connected, as shown in FIG. 5, to a universal serial bus (USB) device 500, as indicated by the box labeled D in FIGS. 1 and 5.
In various illustrative embodiments, the system-on-a-chip device 100 may comprise an on-chip external controller device 1025. The on-chip external controller device 1025 may comprise the on-chip expansion bus (E-Bus) controller 155, the on-chip Ethernet controller 160 and the on-chip universal serial bus (USB) Host controller 165.
The system-on-a-chip device 100 may further comprise an on-chip peripheral component interconnect (PCI) controller 150. The on-chip peripheral component interconnect (PCI) controller 150 may be capable of communicating with the on-chip external controller device 1025 and the on-chip peripheral component interconnect (PCI) input/output (I/O) bus 140, as indicated by the double arrows in FIG. 1 connecting the on-chip external controller device 1025, on-chip peripheral component interconnect (PCI) controller 150 and the on-chip peripheral component interconnect (PCI) input/output (I/O) bus 140.
In various illustrative embodiments, the system-on-a-chip device 100 may comprise an on-chip input/output core 1030. The on-chip Input/output core 1030 may comprise the on-chip peripheral component interconnect (PCI) controller 150 and the on-chip external controller device 1025.
The system-on-a-chip device 100 may further comprise an on-chip Joint Test Access Group (JTAG) device 1015. The on-chip JTAG device 1015 may be connected, as shown in FIG. 9, to a Test Port 900, as indicated by the box labeled H in FIGS. 1 and 9. The on-chip joint test access group (JTAG) device 1015 may operate according to the 1149.1 standard.
The system-on-a-chip device 100 may further comprise an on-chip audio bus interface 185 that may be capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus 180. For example, the on-chip audio bus interface 185 may be an on-chip Intel� AC97. The on-chip audio bus interface 185 may be connected, as shown in FIG. 10, to a coder/decoder (Codec) 1000, as indicated by the box labeled J in FIGS. 1 and 10.
The system-on-a-chip device 100 may further comprise an on-chip multi-master bus 190. For example, the multi-master bus 190 may be an Inter-IC (I2C) universal asynchronous receiver/transmitter (UART). The on-chip multi-master bus 190 may be capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus 180. The on-chip multi-master bus 190 may be connected, as shown in FIG. 11, to an I2C 2-wire serial data and serial clock bus (I2C SDA/SCL) 1100, as indicated by the box labeled K in FIGS. 1 and 11.
The system-on-a-chip device 100 may further comprise an on-chip Smart Card Interface (SCI) universal asynchronous receiver/transmitter (UART) 195. The on-chip Smart Card Interface (SCI) universal asynchronous receiver/transmitter (UART) 195 may be capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus 180. The on-chip Smart Card Interface (SCI) universal asynchronous receiver/transmitter (UART) 195 may be connected, as shown in FIG. 12, to a Smart Card Interface (SCI) device 1200, as indicated by the box labeled L in FIGS. 1 and 12.
The system-on-a-chip device 100 may further comprise an on-chip general purpose input/output interface (GPIO) 1005. The on-chip GPIO 1005 may be capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus 180. The on-chip GPIO 1005 may be connected, as shown in FIG. 13, to a parallel input/output device (PIO) 1300, as indicated by the box labeled M in FIGS. 1 and 13.
The system-on-a-chip device 100 may further comprise an on-chip universal asynchronous receiver/transmitter 16550A (UART 16550A) 110. The on-chip universal asynchronous receiver/transmitter 16550A (UART 16550A) 1010 may be capable of communicating with the on-chip expansion bus (E-Bus) input/output (I/O) bus 180. The on-chip universal asynchronous receiver/transmitter 16550A (UART 16550A) 1010 may be connected, as shown in FIG. 14, to a universal asynchronous receiver/transmitter RS232 (UART RS232) device 1400, as indicated by the box labeled N in FIGS. 1 and 14.
The system-on-a-chip device 100 may further comprise an on-chip private flash bus capable of latching configuration options at power-up. For example, the on-chip memory controller 115 may be connected, as shown in FIG. 2, to the programmable read only memory (PROM) device 200, as indicated by the box labeled A in FIGS. 1 and 2.
FIGS. 15–20 schematically illustrate particular embodiments of respective methods 1500–2000 practiced in accordance with the present invention. FIGS. 1–14 schematically illustrate various exemplary particular embodiments with which the methods 1500–2000 may be practiced. For the sake of clarity, and to further an understanding of the invention, the methods 1500–2000 shall be disclosed in the context of the various exemplary particular embodiments shown in FIGS. 1–14. However, the present invention is not so limited and admits wide variation, as is discussed further below.
As shown in FIG. 15, the method 1500 begins, as set forth in box 1520, by providing an on-chip processor for a system-on-a-chip device. For example, as shown in FIG. 1, the on-chip processor 110 may be provided for the system-on-a-chip device 100. In various illustrative embodiments, and as set forth in box 2050 of method 2000, the on-chip processor 110 may be provided comprising a central processing unit (CPU) core 110 having a V8 architecture capable of executing the Sparc V8 instruction set. It will be appreciated, however, that the present invention is not so limited. In alternative embodiments, the central processing unit (CPU) core 110 may have a V9 architecture capable of executing the Sparc V9 instruction set.
The method 1500 proceeds by providing an on-chip dynamic random access memory (DRAM) capable of communicating with the on-chip processor, as set forth in box 1530. For example, as shown in FIG. 1, the on-chip dynamic random access memory (DRAM) 125 may be provided and may comprise an embedded dynamic random access memory (eDRAM) having about 4 megabytes (4 MB) of embedded dynamic random access memory (eDRAM). The on-chip input/output (I/O) bus 140 may be a peripheral component interconnect (PCI) bus 140.
The method 1500 then proceeds, as set forth in box 1540, by providing at least one on-chip input/output (I/O) bus capable of communicating with the on-chip processor and the on-chip dynamic random access memory (DRAM). For example, as shown in FIG. 1, the on-chip input/output (I/O) bus 140 may be provided and may comprise a peripheral component interconnect (PCI) bus 140.
In various illustrative embodiments, as shown in FIG. 16, and as set forth in box 1650 of method 1600, an on-chip memory controller may be provided and may be capable of communicating with the at least one on-chip input/output (I/O) bus, the on-chip processor and the on-chip dynamic random access memory (DRAM). For example, as shown in FIG. 1, the on-chip memory controller 115 may be provided and may be capable of communicating with the on-chip processor 110 and the on-chip dynamic random access memory (DRAM) 125, as indicated by the double arrows in FIG. 1. The on-chip memory controller 115 may enable the on-chip dynamic random access memory (DRAM) 125 to be capable of communicating with the on-chip processor 110. The on-chip peripheral component interconnect (PCI) controller 120 may enable the on-chip dynamic random access memory (DRAM) 125 and/or the on-chip processor 110 to be capable of communicating with the on-chip input/output (I/O) bus 140 by way of the on-chip memory controller 115.
The system-on-a-chip device 100 may further comprise an on-chip peripheral component interconnect (PCI) controller 120. The on-chip input/output (I/O) bus 140 may be connected, as shown in FIG. 3, to a peripheral component interconnect (PCI) device 300, as indicated by the box labeled B in FIGS. 1 and 3.
In various alternative illustrative embodiments, as shown in FIG. 17, and as set forth in box 1760 of method 1700, at least one on-chip peripheral component interconnect (PCI) controller may be provided and may be capable of communicating with the at least one on-chip input/output (I/O) bus, the on-chip memory controller, the on-chip processor and the on-chip dynamic random access memory (DRAM). For example, the on-chip peripheral component interconnect (PCI) controller 120 may be used to talk both on-chip and off-chip. The on-chip peripheral component interconnect (PCI) controller 120 may be capable of communicating with the on-chip memory controller 115 and the on-chip input/output (I/O) bus 140, as indicated by the double arrows in FIG. 1. The on-chip peripheral component interconnect (PCI) controller 120 may enable the on-chip dynamic random access memory (DRAM) 125 and/or the on-chip processor 110 to be capable of communicating with the on-chip input/output (I/O) bus 140 by way of the on-chip memory controller 115.
In various other alternative illustrative embodiments, as shown in FIG. 18, and as set forth in box 1870 of method 1800, a first phase-lock loop (PLL) clock generator may be provided and may be capable of sending a signal to the on-chip processor and a second phase-lock loop (PLL) clock generator may be provided and may be capable of sending a signal to the at least one on-chip peripheral component interconnect (PCI) controller. For example, as shown in FIG. 1, a first phase-lock loop (PLL) clock generator 170 may be provided and may be capable of sending a signal to the on-chip processor 110 and a second phase-lock loop (PLL) clock generator 175 may be provided and may be capable of sending a signal to the on-chip peripheral component interconnect (PCI) controller 120.
In yet other various alternative illustrative embodiments, as shown in FIG. 19, and as set forth in box 1980 of method 1900, an on-chip interrupt controller may be provided and may be capable of communicating with the on-chip processor. For example, as shown in FIG. 1, the on-chip interrupt controller 105 may be provided and may be capable of communicating with the on-chip processor 110.
Any of the above-disclosed embodiments of a method and a device according to the present invention enables a dynamic random access memory (DRAM) device and a processor to be disposed on the same chip. This leads to a decrease in the interconnection lengths connecting the processor and the dynamic random access memory (DRAM) and increases the overall speed of an integrated circuit device comprising the processor and the dynamic random access memory (DRAM).
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. In particular, every range of values (of the form, “from about a to about b”, or, equivalently, “from approximately a to b,” or, equivalently, “from approximately a–b”) disclosed herein is to be understood as referring to the power set (the set of all subsets) of the respective range of values, in the sense of Georg Cantor. Accordingly, the protection sought herein is as set forth in the claims below.
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