Source: http://www.google.com/patents/US8174530?dq=5311516
Timestamp: 2014-07-22 22:52:59
Document Index: 559904021

Matched Legal Cases: ['Application No. 2000', 'Application No. 2000', 'Application No. 2010', 'Application No. 2010', 'Application No. 2000', 'art 8', 'art 8']

Patent US8174530 - Parallel date processing apparatus - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign in<nobr>Advanced Patent Search</nobr>PatentsA data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processi...http://www.google.com/patents/US8174530?utm_source=gb-gplus-sharePatent US8174530 - Parallel date processing apparatusAdvanced Patent SearchPublication numberUS8174530 B2Publication typeGrantApplication numberUS 11/759,205Publication dateMay 8, 2012Filing dateJun 6, 2007Priority dateApr 9, 1999Also published asUS20080010436Publication number11759205, 759205, US 8174530 B2, US 8174530B2, US-B2-8174530, US8174530 B2, US8174530B2InventorsDave Stuttard, Dave Williams, Eamon O'Dea, Gordon Faulds, John Rhoades, Ken Cameron, Phil Atkin, Paul Winser, Russell David, Ray McConnell, Tim Day, Trey GreerOriginal AssigneeRambus Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (105), Non-Patent Citations (214), Classifications (13), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetParallel date processing apparatusUS 8174530 B2Abstract A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.
1. A method of processing data relating to geometrical primitives, each of which has a plurality of vertices, the method using a single instruction multiple data (SIMD) processing apparatus including an array of processing elements, the method comprising the steps of:
assigning data of each different vertex to a different one of the processing elements in the array; and
on each processing element, and in parallel with one another, producing processed vertex data by performing at least one processing step on vertex data assigned to said processing element by said assigning step;
supplying the processed vertex data as feedback data to a mathematical expression evaluator (MEE) through a feedback path,
wherein the MEE is separate from the array of processing elements and evaluates a mathematical expression to produce a data input for each of the processing elements, and
wherein the feedback path includes direct connections to the processing elements and includes a feedback buffer that stores coefficients from the processing elements for the MEE; and
using the feedback path through the feedback buffer and the MEE to communicate data between processing elements, wherein a given data item is communicated as a constant coefficient with other variable coefficients being set to zero.
2. A method as claimed in claim 1, wherein the feedback data are retrieved from a memory store internal to a processing element.
3. A method as claimed in claim 1, wherein the feedback data are retrieved from a register internal to a processing element.
4. A method as claimed in claim 1, wherein the feedback data are buffered before being supplied to the MEE.
5. A method as claimed in claim 1, wherein the feedback data is supplied by one of the processing elements in the array.
6. A method as claimed in claim 1, wherein the feedback data is supplied by a plurality of the processing elements in the array.
7. A method as claimed in claim 1, wherein the array is a SIMD array operable to process a plurality of instruction threads in parallel with one another.
8. A method as claimed in claim 1, wherein the array is arranged in a plurality of SIMD arrays operable to process a plurality of instruction threads in parallel with one another.
9. A method as claimed in claim 1, wherein the at least one processing step is chosen from a group including transformation to screen space, geometry, lighting and shading processing steps.
10. A single instruction multiple data (SIMD) graphical data processing apparatus for processing data relating to geometrical primitives, the apparatus comprising:
an array of processing elements; and
a control device operable to assign data of each different vertex to a different one of the processing elements;
wherein each processing element is operable to produce processed vertex data by performing, in parallel with other processing elements, at least one processing step on vertex data assigned to said processing element by said assignment;
a mathematical expression evaluator (MEE), which is separate from the array of processing elements; and
a feedback bus, wherein the feedback bus is configured to supply the processed vertex data from the array of processing elements to the MEE, wherein the feedback bus includes direct connections to the processing elements and includes a feedback buffer that stores coefficients from the processing elements for the MEE;
wherein the MEE receives the processed vertex data and evaluates a mathematical expression to produce a data input for each of the processing elements; and
wherein the apparatus is configured to use the feedback path through the feedback buffer and the MEE to communicate data between processing elements, wherein a given data item is communicated as a constant coefficient with other variable coefficients being set to zero.
11. An apparatus as claimed in claim 10, wherein the feedback data is retrieved from a memory store internal to a processing element.
12. An apparatus as claimed in claim 10, wherein the feedback data is retrieved from a register internal to a processing element.
13. An apparatus as claimed in claim 10, wherein the control device includes a data buffer operable to buffer the feedback data before that data is supplied to the array.
14. An apparatus as claimed in claim 10, wherein the feedback data is supplied by one of the processing elements.
15. An apparatus as claimed in claim 10, wherein the feedback data is supplied by a plurality of the processing elements.
16. An apparatus as claimed in claim 10, wherein the array is arranged as a plurality of SIMD arrays.
17. An apparatus as claimed in claim 10, wherein the array is a SIMD array, and is operable to process a plurality of instruction threads in parallel with one another.
18. An apparatus as claimed in claim 10, wherein the array is arranged in a plurality of SIMD arrays, the arrays being operable to process a plurality of instruction threads in parallel with one another.
19. An apparatus as claimed in claim 10, comprising direct inter-processing element connections for transfer of processed vertex data therebetween.
20. An apparatus as claimed in claim 10, wherein the at least one processing step is chosen from a group including transformation to screen space, geometry, lighting and shading processing steps.
CROSS REFERENCE TO RELATED APPLICATIONS This Application is a continuation in part of U.S. patent application Ser. No. 09/972,797, filed Oct. 9, 2001, now U.S. Pat. No. 7,363,472 which is a continuation of PCT/GB00/01332, filed Apr. 7, 2000, which documents are incorporated herein in their entirety by this reference thereto.
waiting on an instruction cache miss, waiting on a zero semaphore; waiting on a busy execution unit, or waiting on a HALT instruction. When a thread stops operation, for example because it requires memory access, it can be �yielding� or.�not yielding�. If the thread is yielding, then if another thread is ready, then that other thread can become active. If the thread is not yielding, then other threads are prevented from becoming active, even though ready. A thread may not yield, for example, if that thread merely requires a short pause in operation. This technique avoids the need to swap between active threads unnecessarily, particularly when a high priority thread simply pauses momentarily.
in group can
Instructions from the thread manager 102 are pushed into three separate instruction FIFOs for low priority, high priority, and binner instructions. Each FIFO has its own �full� indication which is sent to the thread manager 102, so that a thread blocked on a full instruction FIFO will not prevent another thread from pushing an instruction into a non-full instruction FIFO.
There are three priorities for channel instructions: Addressed and Strided instructions can be specified as low or high priority. Binning instructions are always treated as very high priority. Lower priority instructions may be interrupted or preempted by higher priority ones. When a transfer instruction is preempted, the contents of the PE page registers are returned to the PE memory pages from which they came. They can then be restarted at a later time when the higher priority instruction has completed.
�Strided� memory accesses are data transfers between PE memory and external memory where the external memory address of each PEs data is generated by the transfer engine. Addresses are stepped from a base register by a predetermined step size, such that the selected PEs send to or receive from spaced external memory addresses. For example, if the step size is set to one, then the selected PEs access consecutive memory addresses. This has the advantage over �Addressed� transfers in that PEs can use all their I/O page register data, instead of using some of it for address information. The base address for the transfer can be specified with a channel controller instruction or written by the EPU.
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