Source: http://www.google.com/patents/US20060023546?dq=6,411,947
Timestamp: 2015-05-07 10:16:52
Document Index: 80449890

Matched Legal Cases: ['art 110', 'art 120', 'art 130', 'art 140', 'art 110', 'art 120', 'art 120', 'art 130', 'art 120', 'art 120', 'art 130', 'art 110', 'art 130', 'art 120', 'art 140', 'art 110', 'art 110', 'art 110', 'art 130', 'art 120', 'art 120', 'art 130', 'art 140']

Patent US20060023546 - Self refresh period control circuits - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsIn a self refresh period control circuit for controlling a refresh period of a semiconductor memory device in response to operating temperature of the device, a temperature sensor part generates a first period control signal in response to a self refresh start signal or self refresh completion signal,...http://www.google.com/patents/US20060023546?utm_source=gb-gplus-sharePatent US20060023546 - Self refresh period control circuitsAdvanced Patent SearchPublication numberUS20060023546 A1Publication typeApplicationApplication numberUS 11/190,430Publication dateFeb 2, 2006Filing dateJul 27, 2005Priority dateJul 29, 2004Also published asUS7248527Publication number11190430, 190430, US 2006/0023546 A1, US 2006/023546 A1, US 20060023546 A1, US 20060023546A1, US 2006023546 A1, US 2006023546A1, US-A1-20060023546, US-A1-2006023546, US2006/0023546A1, US2006/023546A1, US20060023546 A1, US20060023546A1, US2006023546 A1, US2006023546A1InventorsSang-Kyun ParkOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManReferenced by (19), Classifications (7), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSelf refresh period control circuits
US 20060023546 A1Abstract
In a self refresh period control circuit for controlling a refresh period of a semiconductor memory device in response to operating temperature of the device, a temperature sensor part generates a first period control signal in response to a self refresh start signal or self refresh completion signal, senses operating temperature of the semiconductor memory device in response to a clock signal generated by the self refresh start signal, and generates a corresponding second period control signal. A period magnification control part controls a self refresh period in response to the first and second period control signals. Accordingly, a refresh period characteristic change based on operating temperature, which is causable by an initial self refresh, is implemented. Images(9) Claims(12)
DETAILED DESCRIPTION OF THE INVENTION The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Like numbers refer to like elements throughout the specification. FIG. 4 is a block diagram of self refresh period control circuit according to an exemplary embodiment of the invention Referring to FIG. 4, a self refresh period control circuit according to an exemplary embodiment includes a temperature sensor part 110, a period magnification control part 120, a clock generating part 130 and a refresh control part 140. The temperature sensor part 110 generates a first period control signal TS in response to a self refresh start signal SRS or self refresh completion signal SRS, senses the temperature of a semiconductor memory device provided with the installed temperature sensor in response to a clock signal MSB generated by the self refresh start signal SRS, and generates a corresponding second period control signal TS. The period magnification control part 120 controls a self refresh period in response to the first and second period control signals TS. The period magnification control part 120 decides a magnification of period clock signal TCLK applied from the clock generating part 130 and outputs it as a refresh period signal RS, in response to the period control signals TS. In one embodiment, the first and second period control signals Ts are transmitted on the same, common, signal line. In other embodiments, the first and second period control signals Ts are different signals on different lines. The period magnification control part 120 includes a period controller 122 for deciding a period magnification of refresh signal in response to the first period control signal TS and the second period control signal TS; and a period magnification selector 124 for generating a refresh period signal RS corresponding to the refresh period magnification decided by the period controller 122. The period magnification control part 120 selects a signal having a shortest self refresh period in response to the first period control signal TS, and generates a refresh period signal RS having an appropriate period in response to the second period control signal TS. The clock generating part 130 applies a clock signal MSB having a longest period of a most significant bit (MSB) among a plurality of clock signals CLK having individually different periods, to the temperature sensor part 110, in response to a self refresh start signal SRS. Also, the clock generating part 130 selects a clock signal having a predetermined period, and applies the selected period clock signal TCLK to the period magnification control part 120. The clock generating part includes an auto period generator 132 for selecting a clock signal having a predetermined period in response to the self refresh start signal SRS; and a counter generator 134 for generating the period clock signal TCLK selected by the auto period generator 132 and a clock signal MSB having a longest period. The refresh control part 140 controls the performance of a self refresh operation with a predetermined period in response to the refresh period signal RS. FIG. 5 is a detailed block diagram of the temperature sensor part 110 shown in FIG. 4. With reference to FIG. 5, the temperature sensor part 110 includes a sampling clock generator 118, a temperature sensor 112, an amplifier 114, an auto pulse generator 117 and a latch 116. The sampling clock generator 118 generates a sampling clock signal SCLK having a predetermined period in response to clock signal MSB generated by the self refresh start signal SRS. The sampling clock signal SCLK may be, e.g., a clock signal SCLK that has the same period as the clock signal MSB and that has a relatively short low level section as compared with a high level section. The temperature sensor 112 senses the temperature of a semiconductor memory device at which the temperature sensor is installed and generates a temperature signal Ti, in response to the sampling clock signal SCLK. The temperature sensor 112 operates only in a low level section of the sampling clock signal SCLK. The amplifier 114 operates in response to the sampling clock signal SCLK, and amplifies the temperature signal Ti and generates the amplified temperature signal TA. The self refresh start signal SRS or self refresh completion signal SRS may be a pulse signal that has a low level by the self refresh start signal SRS and that has a high level by the self refresh completion signal SRS. The auto pulse generator 117 generates a single pulse SAP in response to the self refresh start signal SRS or self refresh completion signal SRS. The latch 116 generates the first period control signal TS in response to a single pulse SAP of the auto pulse generator 117, and latches output signal TA of the amplifier 114 and generates a second period control signal TS. FIG. 6 is a circuit diagram illustrating in detail an applied example of a latch 116 shown in FIG. 5. The latch 116 includes transmission gates G101 and G102, a plurality of inverters I102, I103, I104 and I105, a NOR circuit NO101 for performing a NOR-operation on a power-up signal VCCHB and an auto pulse SAP, an inverter I106 and an NMOS transistor N101. The latch 116 is configured as shown in FIG. 6. As shown in FIG. 6, the latch 116 may be configured so that temperature signal TA amplified by the amplifier 114 is latched by transmission gates G101 and G102 operating by sampling clock signal SCLK and by a plurality of inverters I102, I103, I104 and I105. The latch 116 is reset by NOR-operating and inverting power-up signal VCCHB and auto pulse SAP and so by operating an NMOS transistor N101. The latch may be determined so that the first and second period control signals TS have a high level at reset. The power-up signal VCCHB is supplied at a high level at initialization when the power source voltage is powered up, and is supplied in a low level after the normal power-up of power source voltage. Further, the auto pulse signal SAP may be a pulse signal having a very short section of high level responding to self refresh start signal SRS or self refresh completion signal SRS. FIG. 7 is a circuit diagram illustrating in detail an applied example of an auto pulse generator 117 shown in FIG. 5. With reference to FIG. 7, the auto pulse generator 117 can include at least one or more odd-number of inverters I108, I109 and I110 for inverting the self refresh completion signal SRS and for outputting the signal delayed by a predetermined time; a NAND circuit NA101 for receiving the self refresh completion signal SRS and the delayed signal and performing a NAND operation on them; and an inverter I111 for inverting an output of the NAND circuit NA and outputting an auto pulse SAP. The auto pulse has a high level by an output of the NAND circuit NA101 and the inverter I111, simultaneously to generate the self refresh completion signal SRS, and then, again has a low level when the self refresh completion signal SRS delayed by the inverters I108, I109 and I110 reaches the NAND circuit NA101 and the inverter I111. In other words, the auto pulse may be a single pulse signal that maintains a high level section only by a delay time of the inverters I108, I109 and I110. In another embodiment, the auto pulse generator 117 may include at least one inverter for inverting the self refresh start signal SRS and outputting the signal delayed by a predetermined time when generating a single pulse in response to the self refresh start signal SRS; and a NOR circuit for receiving the self refresh start signal SRS and the delayed signal, and performing a NOR operation on them and outputting an auto pulse signal SAP. FIG. 8 is a timing diagram illustrating the operation of the temperature sensor part 110 shown in FIG. 5. Referring to FIGS. 4 to 8, the operation of self refresh period control circuit will be described as follows, according to an exemplary embodiment of the invention. The exemplary embodiment will be described for the case where the first period control signal Ts is generated in response to the self refresh completion signal. The other case where the first period control signal Ts is generated in response to the self refresh start signal, will be readily understood by those skilled in the art based on the description of the first case. As shown in FIGS. 4 to 8, clock signals MSB and TCLK having a number of bits used as a clock of controlling a period of refresh are generated in the clock generating part 130, in response to self refresh start signal SRS,enter. The sampling clock generator 118 generates a sampling clock signal SCLK in response to clock signal MSB having a longest period among clock signals MSB and TCLK having a number of bits. The sampling clock signal SCLK has the same period as the clock signal MSB, but is a pulse signal having a short low level section as compared with a high level section. The clock signal MSB having a longest period and the sampling clock signal SCLK are shown as an example in FIG. 8. The temperature sensor 112 operates only in a low level section of the sampling clock signal SCLK, but does not operate in a high level section. The temperature sensor 112 generates a temperature signal Ti indicating an operating temperature of a semiconductor memory device during operation. Herewith, the semiconductor memory device is provided with a self refresh period control circuit according to an exemplary embodiment of the invention. After the start of the refresh operation, the temperature sensor 112 senses an operating temperature of semiconductor memory device, and when higher than a reference temperature, generates the temperature signal Ti in a high level, and when lower than a reference temperature, generates the temperature signal Ti of low level. In one embodiment, the reference temperature is determined as 45� C. The temperature sensor 112 may determine several reference temperatures to generate temperature signal Ti having a number of bits per section on the basis of them. The temperature signal Ti is amplified by the amplifier 114 and generates an amplified temperature signal TA. The latch 116 latches such temperature signal TA changed in level and generates a second period control signal TS. In other words, the latch 116 receives a temperature signal TA and latches a second period control signal TS at a high level when the temperature signal TA has the high level in response to a sampling clock signal SCLK, and then, when the temperature signal TA is lowered to a low level, the second period control signal TS is also lowered to a low level. That is, the latch 116 retains the output of the temperature sensor 112 even if the temperature sensor 112 does not operate. The period control signal TS is applied to the period magnification control part 120. The latch 116 is configured to determine an initial value in a supply of initially supplied power source in a high level. The latch 116 is initialized by single pulse SAP generated by the auto pulse generator 117 that responds to self refresh completion signal SRS,exit. Thus, the latch 116 generates a first period control signal TS at a high level. FIG. 8 illustrates a generation section II of second period control signal TS, a generation section IV of first period control signal TS, and a low temperature section II and a high temperature section III. During section I from a restart of refresh through a re-generation of self refresh start signal SRS,enter after a self refresh completion signal SRS,exit, to before operation of the temperature sensor 112; a refresh is performed with a shortest period on the basis of high temperature. Hence, the present invention resolves the problem of a self refresh operation causable by a temperature change during a section (in this example, Section IV) that corresponds to the onset of a self refresh completion signal SRS,exit to the re-generation of the self refresh start signal SRS,enter. The period magnification control part 120 decides and selects a period magnification of clock signal TCLK applied from the clock generating part 130, and generates a refresh period signal RS, in response to the state of the first and second period control signals Ts. When the first and second period control signals Ts have a high level, the refresh period is determined to be the lowest magnification, and when the first and second period control signals Ts have a low level, the refresh period is determined to be the highest magnification within a range of guaranteeing a refresh characteristic of semiconductor memory device. In the refresh control part 140, the refresh is performed in response to the refresh period signal RS. The self refresh operation is completed by the self refresh completion signal SRS,exit. As described above, according to an exemplary embodiment of the invention, an auto pulse is generated in response to a self refresh start signal or completion signal, then a latch is initialized to generate a first period control signal, thereby a refresh period appropriate to a refresh characteristic based on temperature can be obtained. That is, a self refresh characteristic provided from a start of self refresh to before an operation of the temperature sensor can be provided. While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7349762 *Nov 10, 2005Mar 25, 2008Kabushiki Kaisha ToshibaSystems and methods for thermal managementUS7486583Aug 1, 2006Feb 3, 2009Hynix Semiconductor, Inc.Self-refresh period measurement circuit of semiconductor deviceUS7512027Dec 28, 2006Mar 31, 2009Hynix Semiconductor Inc.Refresh control circuit in semiconductor memory apparatus and method of controlling period of refresh signal using the sameUS7551501Dec 29, 2006Jun 23, 2009Hynix Semiconductor, Inc.Semiconductor memory device with temperature sensing device and operation thereofUS7603249 *Feb 20, 2007Oct 13, 2009Darryl WalkerSemiconductor device having variable parameter selection based on temperature and test methodUS7764561Jan 13, 2009Jul 27, 2010Hynix Semiconductor Inc.Self-refresh period measurement circuit of semiconductor deviceUS7821860 *Oct 16, 2006Oct 26, 2010Samsung Electronics Co., Ltd.Stable temperature adjustment for refresh controlUS7881139May 11, 2009Feb 1, 2011Hynix Semiconductor Inc.Semiconductor memory device with temperature sensing device and operation thereofUS7911868Jan 13, 2009Mar 22, 2011Hynix Semiconductor Inc.Self-refresh period measurement circuit of semiconductor deviceUS7953573Apr 2, 2010May 31, 2011Agersonn Rall Group, L.L.C.Semiconductor device having variable parameter selection based on temperature and test methodUS8005641Aug 13, 2009Aug 23, 2011Agersonn Rall Group, L.L.C.Temperature sensing circuit with hysteresis and time delayUS8040742Dec 10, 2009Oct 18, 2011Agersonn Rall Group, L.L.C.Semiconductor device having variable parameter selection based on temperature and test methodUS8042999 *Dec 28, 2006Oct 25, 2011Hynix Semiconductor Inc.On die thermal sensor of semiconductor memory deviceUS8049145Feb 20, 2007Nov 1, 2011Agerson Rall Group, L.L.C.Semiconductor device having variable parameter selection based on temperature and test methodUS8081532Jun 4, 2010Dec 20, 2011Intellectual Ventures Holding 83 LLCSemiconductor device having variable parameter selection based on temperature and test methodUS8308359Jan 15, 2010Nov 13, 2012Intellectual Ventures Holding 83 LLCSemiconductor device having variable parameter selection based on temperature and test methodUS8462560Feb 1, 2010Jun 11, 2013Elpida Memory, Inc.Semiconductor device, method for controlling the same, and semiconductor systemUS8497453Sep 19, 2011Jul 30, 2013Intellectual Ventures Holding 83 LLCSemiconductor device having variable parameter selection based on temperatureUS8971132May 3, 2013Mar 3, 2015Ps4 Luxco S.A.R.L.Semiconductor device, method for controlling the same, and semiconductor system* Cited by examinerClassifications U.S. Classification365/222International ClassificationG11C7/00Cooperative ClassificationG11C2211/4061, G11C11/40626, G11C11/406European ClassificationG11C11/406T, G11C11/406Legal EventsDateCodeEventDescriptionMar 6, 2015REMIMaintenance fee reminder mailedDec 27, 2010FPAYFee paymentYear of fee payment: 4Jul 27, 2005ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PARK, SANG-KYUN;REEL/FRAME:016821/0386Effective date: 20050726RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services