Source: http://www.google.com.jm/patents/US20100255792
Timestamp: 2017-12-17 13:42:46
Document Index: 158836408

Matched Legal Cases: ['§120', '§119', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US20100255792 - Adaptive radio transceiver with an antenna matching circuit - Google Patents
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com.jm/patents/US20100255792?utm_source=gb-gplus-sharePatent US20100255792 - Adaptive radio transceiver with an antenna matching circuit
Publication number US20100255792 A1
Also published as US6738601, US6917789, US6920311, US6987966, US7116945, US7130579, US7233772, US7349673, US7356310, US7389087, US7697900, US7756472, US8023902, US8116690, US20040195917, US20050153664, US20050186925, US20070049205, US20070285154, US20080182526, US20080191313, US20080290966
Publication number 12751328, 751328, US 2010/0255792 A1, US 2010/255792 A1, US 20100255792 A1, US 20100255792A1, US 2010255792 A1, US 2010255792A1, US-A1-20100255792, US-A1-2010255792, US2010/0255792A1, US2010/255792A1, US20100255792 A1, US20100255792A1, US2010255792 A1, US2010255792A1
Patent Citations (90), Referenced by (8), Classifications (54), Legal Events (6)
US 20100255792 A1
The present application is a continuation of co-pending patent application Ser. No. 09/634,552, filed Aug. 8, 2000, priority of which is hereby claimed under 35 U.S.C. §120. The present application also claims priority under 35 U.S.C. §119(e) to provisional Application No. 60/160,806, filed Oct. 21, 1999; Application No. 60/163,487, filed Nov. 4, 1999; Application No. 60/163,398, filed Nov. 4, 1999; Application No. 60/164,442, filed Nov. 9, 1999; Application No. 60/164,194, filed Nov. 9, 1999; Application No. 60/164,314, filed Nov. 9, 1999; Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; Application No. 60/165,356; filed Nov. 12, 1999; Application No. 60/165,355, filed Nov. 12, 1999; Application No. 60/172,348, filed Dec. 16, 1999; Application No. 60/201,335, filed May 2, 2000; Application No. 60/201,157, filed May 2, 2000; Application No. 60/201,179, filed May 2, 2000; Application No. 60/202,997, filed May 2, 2000; Application No. 60/201,330, filed May 2, 2000. All these applications are expressly incorporated herein by referenced as though fully set forth in full.
V OI = A  ( 1 + jRC   ω )  V II + 2  QV IQ ( 1 + j   RC   ω ) 2 + 4  Q 2   and ( 1 ) V OQ = A  - 2  QV II + ( 1 + j   RC   ω )  V IQ ( 1 + j   RC   ω ) 2 + 4  Q 2 ( 2 )
H  ( j   ω ) = V o V I  ( j   ω ) = A 1 + j   RC   ω - j   2  Q . ( 3 )
H  ( j   ω ) = A 1 + j   RC   ω + j   2  Q ( 4 )
j   ω - j  ( ω - ω 0 ) BW ( 5 )
α i · BW = - 1 RC   and ( 7 ) ω o + β i · BW = 2  Q RC ( 8 )
j   ω - j  ( ω 2 - ω 0 2 ) BW · ω ( 9 )
H  ( j   ω ) = R · Y i 1 + j   RC   ω - j   2  Q ( 10 )
In order to have a zero located at jco axis in the frequency response, Yi should contain a term such as 1−ω/ωz. If Yi is simply made of a resistor Rz in parallel with a capacitor Cz, then the input admittance will be equal to:
Y i = 1 R z + j   ω   C z ( 11 )
Y i = 1 V = 1 R z - C z  ω ( 13 )
H  ( jω ) = A  1 - RC z A  ω 1 + j   RC   ω - j2   Q ( 14 )
H  ( jω ) = n F n A 1 + j   n c  n F  R u  C u  ω - j  n F n Q ( 16 )
Ideal   Dynamic   Range = 20  log  S S A n = 20  log   A n = 20  ( n )  log   A ( 22 )
Dynamic   Range = 20  log  S σ n   σ n = total   noise   rms   σ n = ( BW ) × Noise   Factor ( 23 )
Max   RSSI - Min   RSSI = C   log   A 2  n ( 29 ) Δ   RSSI = C   log   A 2  n ( 30 ) C = Δ   RSSI 2  n   log   A ( 31 ) ( Ideal )   RSSI = Δ   RSSI 2  n   log   A  log   V in 2 ( 32 )
V in   1 = S ( A ) n - m ( 33 ) V in   2 = S ( A ) n - m - 1 ( 34 ) ( Ideal )   RSSI 2 - RSSI 1 = log  ( A ) 2 ( 35 ) ( Approximated )   RSSI 2 - RSSI 1 = β 2  S 2 ( 36 ) Therefore , C   log   A 2 = β 2  S 62 ( 37 )
RSSI = 1 ( A   β ) 2 - 1  ( A   β ) 2  ( n - m )  V in 2 + m  Δ   RSSI n ;   S A n - m < V in  < S A n - m - 1 ( 39 )
Gain   ( A ) = w in w in = 200 6 ≈ 5.8 ( 40 )
if   Δ   I SQM   1 = ( I D   1 + I D   4 ) - ( I D   2 + I D   3 ) = 2  ( I D   C + I SQ ) = 2  k - 1 k + 1  I 0 - 4  k  ( k - 1 )  β N ( k + 1 ) 2  V I 2 ( 41 )
if   Δ   I SQM   1 = O , V i = ± I 0 β N  k + 1 2  k ( 42 )
β 2  S 2 = 4  k  ( k - 1 )  β N ( k + 1 ) 2  V i 2  R L . ( 43 )
Δ   RSSI n = 2  k - 1 k + 1  I 0  R L . ( 44 )
FIG. 23 shows an exemplary analog multiplier 331, 332 with zero higher harmonics in accordance with the present invention. Buffers one 334 and two 335 are added to a Gilbert cell to linearize the voltage levels. Buffers one 334 and two 335 convert the two inputs into two voltage levels for true analog multiplication using a Gilbert cell. The Gilbert cell is comprised of transistors 336, 338, resistors 340; 342 and cross-coupled pairs of transistors 344, 346 and transistors 348, 350.
 H  ( f )  = f Qf 0 [ 1 - ( f f 0 ) 2 ] 2 + ( f Qf 0 ) 2 . ( 49 )
FIG. 33( a) shows a signal passing through a limiting buffer 910 (such as the buffers implemented in the LO generator). When a large signal at a frequency off accompanied with a small interferer at a frequency of Δf 902 away pass through a limiting buffer, at the limiter output the interferer produces two tones ±Δf 914, 916 away from the main signal, each with 6 dB lower amplitude. Therefore, the spur at 2.5f1 will actually be 10+15+15+6=46 dB attenuated when it passes through the buffer, instead of the 40 dB calculated above. It will also produce an image at 0.5f1 which is 10+15+22+6=53 dB lower than the main signal. This will dominate the spur at 0.5f1 because of the third harmonic of the divider mixed with the VCO signal, which is more than 75 dB lower than the main signal.
V out_I = - Sin  ( θ 2 ) · Sin  ( ( ω 1 - ω 2 )  t + θ 2 ) + Cos  ( θ 2 ) · Cos  ( ( ω 1 + ω 2 )  t + θ 2 ) ( 52 )  and V out_Q = - Sin  ( θ 2 ) · Cos  ( ( ω 1 - ω 2 )  t + θ 2 ) + Cos  ( θ 2 ) · Sin  ( ( ω 1 + ω 2 )  t + θ 2 ) ( 53 )
V out_I = - Sin  ( θ 1 - θ 2 2 ) · Sin  ( ( ω 1 - ω 2 )  t + θ 1 - θ 2 2 ) + Cos  ( θ 1 + θ 2 2 ) · Cos  ( ( ω 1 + ω 2 )  t + θ 1 + θ 2 2 ) ( 54 )  and V out_Q = - Sin  ( θ 1 + θ 2 2 ) · Cos  ( ( ω 1 - ω 2 )  t + θ 1 - θ 2 2 ) + Cos  ( θ 1 - θ 2 2 ) · Sin  ( ( ω 1 + ω 2 )  t + θ 1 + θ 2 2 ) ( 55 )
σ A = ( σ θ ) 2 2 ( 57 )
In the transmitter, receiver and LO generator non-silicided polysilicon resistors can be used.
As those skilled in the art will appreciate, other resistor technologies can also be used. Non-silicided polysilicon resistors have a high sheet resistance of 200-Ω/square along with desirable matching properties. A switching resistor array as shown in FIG. 44 can be used to calibrate a resistor. The array includes serial connected resistors 208, 210, 212, 214, 216, which, by way of example, have resistances of 2200Ω, 1100Ω, 550Ω, 275Ω, and 137Ω, respectively. The resistors 210, 212, 214, 216 include a bypass switch for switching the resistors in and out of the array. The switch positions are nominally selected to produce an equivalent of 3025Ω. This resistance value has been chosen as a convenience to match the value used in generating an accurate bandgap reference current. A 4-bit calibration code 206 is used to control the total resistance in this array. As seen in FIG. 44, the resistances are binary-weighted in value and the accurate scaling of each incremental resistance results by placing the largest resistor (2200Ω) 208 in series to generate each value. In the described embodiment, the incremental resistances shown in FIG. 44 are chosen so that the total resistance in the array covers a range 30% above and below its nominal value, with a maximum resistance error of +2% determined by the incremental resistance switched by the LSB. The range of resistance covered by the array is sufficient to cover typical process variations in a semiconductor process. A series resistive array may be desirable opposed to a parallel resistive array because of the smaller area occupied on the wafer.
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International Classification H03H11/12, H04B1/38, H03H21/00
Cooperative Classification H03F2200/318, H03B27/00, H03F3/245, H03H11/1291, H03F2203/45528, H03F2203/45386, H03F3/19, H03B21/01, H04B17/104, H03H2011/0494, H03L7/099, H03F3/45475, H03H11/22, H03H21/0012, H03G11/00, H03H21/0001, H03F2203/45138, H03F3/45179, H03F2203/45526, H03H11/344, H03F2203/45638, H03H7/42, H04B17/14, H03L7/18, H03J2200/10, H04B17/19, H03F1/56, H03F2200/336, H03G3/001, H03F2200/451
European Classification H04B17/00A3S, H04B17/00A2S, H03L7/099, H04B17/00A1T, H03H11/22, H03H11/34D, H03F3/45S1B, H03B27/00, H03B21/01, H03F3/19, H03F3/45S1K, H03G11/00, H03L7/18, H03F1/56, H03F3/24B, H03H7/42, H03G3/00D, H03H21/00A, H03H21/00B, H03H11/12F