Source: http://www.google.com/patents/US6797606?dq=5435091
Timestamp: 2017-10-23 23:19:39
Document Index: 257599254

Matched Legal Cases: ['art 401', 'art 402', 'art 402', 'art 409', 'art 409', 'art 402', 'art 401', 'art 401', 'art 402', 'art 409', 'art 409', 'art 402']

Patent US6797606 - Semiconductor integrated circuit device and manufacturing method of ... - Google Patents
After formation of Cu interconnections 46 a to 46 e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46 a to 46 e is treated with a reducing plasma (ammonia plasma). Then, without...http://www.google.com/patents/US6797606?utm_source=gb-gplus-sharePatent US6797606 - Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
Publication number US6797606 B2
Application number US 10/233,469
Also published as US6716749, US6756679, US6797609, US6815330, US6849535, US6864169, US20020113271, US20020119651, US20020127842, US20020127843, US20020142576, US20030001183, US20030001277, US20030001280, US20030017692, US20030045086, US20080138979
Publication number 10233469, 233469, US 6797606 B2, US 6797606B2, US-B2-6797606, US6797606 B2, US6797606B2
Inventors Junji Noguchi, Naofumi Ohashi, Kenichi Takeda, Tatsuyuki Saito, Hizuru Yamaguchii, Nobuo Owada
Patent Citations (53), Non-Patent Citations (12), Referenced by (3), Classifications (50), Legal Events (5)
Semiconductor integrated circuit device and manufacturing method of semiconductor integrated circuit device
US 6797606 B2
(a) forming a low dielectric constant interlayer insulating film over a first main surface of a wafer;
(b) forming a silicon oxide interlayer insulating film over the low dielectric constant interlayer insulating film constituting a first interlayer insulating film together with the low dielectric constant interlayer insulating film, which silicon oxide interlayer insulating film has a larger dielectric constant as compared with the low dielectric constant interlayer insulating film;
(c) forming a first interconnection groove in the first interlayer insulating film;
(d) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection groove;
(e) forming a first interconnection metal film having copper as a main component over the first barrier metal film both outside and inside the first interconnection groove so as to fill the first interconnection groove;
(f) removing both the first interconnection metal film and the first barrier metal film outside the first interconnection groove by chemical mechanical polishing; and thereafter
(g) performing ammonia plasma treatment over the first main surface so as to reduce and nitride upper surfaces of both the first interlayer insulating film and the first interconnection metal film, which are thereby converted to a nitrided silicon oxide surface and a nitrided copper-containing surface, respectively; and thereafter
(h) forming a copper diffusion barrier insulating film over the first main surface.
2. The method according to claim 1, wherein the low dielectric constant interlayer insulating film is an organic polymer film.
3. The method according to claim 1, wherein the low dielectric constant interlayer insulating film is a silicon oxide insulating film having a specific dielectric constant not greater than 3.0.
4. The method according to claim 3, wherein the low dielectric constant interlayer insulating film is an inorganic SOG film.
5. The method according to claim 3, wherein the low dielectric constant interlayer insulating film is an organic SOG film.
(c) forming a first interconnection region in the first interlayer insulating film;
(d) forming a first barrier metal film over the first interlayer insulating film both outside and inside the first interconnection region;
(e) forming a first interconnection metal film having copper as a main component over the first barrier metal film both outside and inside the first interconnection region so as to fill the first interconnection region;
(f) removing both the first interconnection metal film and the first barrier metal film outside the first interconnection region by chemical mechanical polishing; and thereafter
(g) performing ammonia plasma treatment over the first main surface so as to reduce and nitride upper surfaces of both the first interlayer insulating film and the first interconnection metal film, which are thereby converted to a nitrided silicon oxide surface and nitrided copper-containing surface, respectively; and thereafter
7. The method according to claim 6, wherein the low dielectric constant interlayer insulating film is an organic polymer film.
8. The method according to claim 6, wherein the low dielectric constant interlayer insulating film is a silicon oxide insulating film having a specific dielectric constant not greater than 3.0.
9. The method according to claim 8, wherein the low dielectric constant interlayer insulating film is an inorganic SOG film.
10. The method according to claim 8, wherein the low dielectric constant interlayer insulating film is an organic SOG film.
This application is a division of application Ser. No. 10/128,265 filed Apr. 24, 2002, which is a division of application Ser. No. 09/666,053 filed Sep. 20, 2000, now abandoned, which is a continuation of application Ser. No. 09/621,536 filed Jul. 21, 2000, now abandoned.
3. A manufacturing method according to the item 1, wherein the plasma of reducing atmosphere is mixed gas plasma of ammonia (NH3) and a diluting gas, and the diluting gas contains one or more gases selected from hydrogen (H2), nitrogen (N2), argon (Ar) and helium (He).
16. A manufacturing method according to the item 1, wherein abrasive-grain-free chemical mechanical polishing is employed for the polishing, in the step (c).
17. A manufacturing method according to the item 16, wherein the polishing in the step (c) is conducted in three stages, that is, first polishing by abrasive-grain-free chemical mechanical polishing, second polishing by abrasive-grain-using chemical mechanical polishing and third polishing by selective chemical mechanical polishing at a first conductive film : second conductive film selection ratio of at least 5.
20. A manufacturing method according to the item 19, which further comprises, between the steps (c) and (d), washing the surface of each of the first insulating film and interconnection with an aqueous solution of hydrogen fluoride (HF) or citric acid (C(CH2COOH)2(OH) (COOH).
FIGS. 56(a) to 56(c) illustrate a sample used in the present application for the measurement of TDDB, wherein FIG. 56(a) is a plan view, and FIGS. 56(b) and 56(c) are cross-sections taken along lines B—B′ and C—C′ of FIG. 56(a), respectively;
The term “TDDB” as used herein means time (lifetime) determined by applying a relatively high voltage between electrodes under measuring conditions of a predetermined temperature (ex. 140° C.), drawing a graph wherein time from application of voltage to dielectric breakdown is plotted against applied electric field, and extrapolating the practical electric field strength (ex. 0.2 MV/cm) in the graph. FIG. 56 illustrates a sample used in the present application for the measurement of TDDB, wherein FIG. 56(a) is a plan view, and FIGS. 56(b) and 56(c) are cross-sections taken along lines B—B′ and C—C′ of FIG. 56(a), respectively. This sample can be formed practically in a TEG (Test Equipment Group) region of a wafer. As illustrated in FIG. 56, a pair of comb-like interconnections L are formed in the second interconnection layer M2 and are connected with pats P1, P2 of the uppermost layer. An electric current is measured by applying an electric field between these comb-like interconnections L. The pads 1, 2 are measuring terminals. The width, distance between any two adjacent interconnections and thickness of the comb-like interconnections L are each 0.5 μm. The length of the interconnection is formed to 1.58×105 μm. FIG. 57 is a schematic view illustrating the summary of measurement. The sample is supported on a measuring stage S and a current-voltage measuring apparatus (I/V measuring apparatus) is connected between the pads P1 and P2. The sample stage S is heated by a heater H to adjust the temperature of the sample to 140° C. FIG. 58 shows one example of the measuring results of current-voltage under the conditions of the sample temperature of 140° C. and electric field strength of 5 MV/cm. Although TDDB is measured by either one of the constant voltage stress method and low current stress method, the former one wherein an average electric field applied to an insulating film shows a fixed value is employed in the present application. After application of voltage, the current density decreases with the passage of time and then, a drastic increase in the current (dielectric breakdown) is observed. Here, the time until the leak current density reaches 1 μA/cm2 is designated as TDDB (the TDDB at 5 MV/cm). The term “TDDB” as used herein means the breakdown time (lifetime) at 0.2 MV/cm unless otherwise specifically referred to, but in a broader sense, it is sometimes used as a time until breakdown at a preliminarily designated electric field strength. Unless otherwise specifically described, the TDDB means that at the sample temperature of 140° C. The TDDB is measured using the above-described comb-like interconnections L, but it is needless to say that it reflects the breakdown lifetime between actual interconnections.
The substrate 1, for example, having a size of 8 inches can be subjected to plasma treatment under the conditions of a treating pressure of 5.0 Torr, RF electric power of 600 W, substrate temperature of 400° C. and ammonia flow rate of 200 sccm and treating time of 10 seconds. The distance between any two adjacent electrodes is set at 600 mils. It is needless to say that the plasma treatment conditions are not limited to the above-described ones. According to the study of the present inventors, a reduction in the plasma damage can be attained by a higher pressure and a reduction in the scatter of TDDB and an increase in TDDB can be attained by a higher substrate temperature. It has also been found that hillocks tend to appear on the surface of Cu at a higher substrate temperature, a lager RF electric power or a long treating time. In consideration of these findings and a difference in the conditions depending on the constitution of the apparatus, the plasma treatment conditions can be set within a range of from 0.5 to 6 Torr for treating pressure, 300 to 600W for RF electric power, 350 to 450° C. for substrate temperature, 20 to 500 sccm for ammonia flow rate, 5 to 180 seconds for treating time and 300 to 600 mils for a distance between electrodes.
The silicon nitride film 47 is formed to a film thickness of, for example, 50 nm. Then, a silicon oxide film for the formation of a plug to connect the third interconnection layer with the second interconnection layer (Cu interconnections 46 a to 46 e) and in a similar manner to that described above, the Cu-embedded interconnection of at least the third layer is formed. FIG. 18 is a whole flow chart of the formation process of the above-described Cu interconnections 46 a to 46 e.
FIG. 19 illustrates one example of CMOS-LSI in which the formation of the interconnections of the first to the seventh layers has already been finished. The first interconnection layer (M1) is made of a tungsten film, as described above. The second interconnection (M2) to the fifth interconnection (M5) layers are formed in a similar manner to that employed for the formation of the above-described Cu interconnection. In each of the second (M2) and third interconnection (M3) layers, the width, distance between the adjacent two interconnections and height are each formed to 0.5 μm. In each of the fourth interconnection (M4) and fifth interconnection (M5) layers, on the other hand, the width, distance between adjacent two interconnections and height (thickness) are each formed to 1 μm. The sixth interconnection (M6) is formed to have three layers, that is, tungsten film, aluminum film and tungsten film, while the seventh interconnection layer (M7) is constituted from an aluminum film. A bump or the like is formed on the seventh interconnection layer (M7), but it is not illustrated.
FIGS. 26(a), 26(b) and 26(c) suggest the release of organic matters in each process, while FIGS. 27(a) to 27(d) suggest the existence of a peak which does not result from the release of organic matters. The peaks of FIGS. 27(a) to 27(d) existing within a range of from 300 to 400° C. are presumed to result from Si, SiO, SiH, SiH3, respectively. According to the comparison among these drawings, release of SiO is observed in each of the hydrogen, ammonia and nitrogen plasma treatments, but release of each of SiH and SiH3 is hardly observed in the ammonia plasma treatment. In other words, an Si—O—N bond is formed by the ammonia plasma treatment and release occurs easily at a relatively low energy. The energy necessary for release is the highest in the nitrogen plasma treatment, while it is almost the same in the hydrogen plasma treatment and ammonia plasma treatment.
Downstream of the, polishing treatment part 401, a post-washing part 402 is disposed for scrub washing of the surface of the substrate 1 which has finished preliminary washing. The post-washing part 402 is equipped with a loader 408, first washing part 409A, second washing part 409B, spin drier 410 and unloader 411. The post-washing part 402 is surrounded by a shading wall 430 to prevent the surface of the substrate 1 from being exposed to light during washing and its inside is dark with an illuminance of 180 lux, preferably 100 lux or less. This shading wall is disposed because, if the substrate 1 having a polishing liquid attached to the surface thereof is exposed to light under wet condition, a short-circuit current passes through the pn junction by the photoelectromotive force of silicon, and Cu ions are dissociated from the surface of the Cu interconnection connected to the p side (+side) of the pn junction, which causes corrosion of the interconnection.
As illustrated in FIG. 35, the first disk 403A is turned and driven within a horizontal plane by a driving mechanism 412 disposed below the disk. The first disk 403A has, on the upper surface thereof, a polishing pad 413 which has been formed by uniformly adhering a synthetic resin such as polyurethane having a number of pores. A wafer carrier 415 turned and driven vertically within a horizontal plane by a driving mechanism 414 is disposed above the first disk 403A. The substrate 1 is supported by a wafer chuck 416 and retainer ring 417, each disposed at the lower end of the wafer carrier 415, with its main surface (a surface to be polished) down; and is pressed against the polishing pad 413 under a predetermined load. Between the surface of the polishing pad 413 and the surface of the substrate 1 to be polished, a slurry (polishing liquid) S is fed through a slurry feeding pipe 418, whereby the surface of the substrate 1 to be polished is chemically and mechanically polished. Above the first disk 403A, a dresser 420 turned and driven vertically within a horizontal plane by a driving mechanism 419 is disposed. The dresser 420 has, at the lower end thereof, a base having thereon electrodeposited diamond particles, by which the surface of the polishing pad 413 is periodically shaven in order to prevent clogging with the abrasive grains. The constitution of the second disk 403B is almost similar to that of the first disk 403A except that it has two slurry feeding pipes 418 a, 418 b.
For the formation of the Cu interconnection by the above-described CMP apparatus 400, the substrate 1 accommodated in the loader 406 is transported to the polishing treatment part 401 by the rotary arm 405, followed by chemical mechanical polishing (abrasive-grain-free chemical mechanical polishing) (CMP of the first step) using an abrasive-grain-free slurry, as illustrated in FIG. 36, on the first disk 403A to remove the Cu film 46 outside the interconnection grooves 40 to 44 (FIG. 37).
The TiN film 45 outside the interconnection grooves 40 to 44 and the Cu film 46 which has partially remained thereover are removed by transferring the substrate 1 from the first disk 403A to the second disk 403B and subjecting it to chemical mechanical polishing (abrasive-grain-using chemical mechanical polishing) (CMP of the second step) using an abrasive-grain-containing polishing liquid (slurry). The term “abrasive-grain-using chemical mechanical polishing” as used herein means chemical mechanical polishing with a polishing liquid containing abrasive grains made of powders such as alumina and silica in an amount not less than 0.5 wt. %. In this embodiment, a polishing liquid obtained by mixing 5 vol. % of hydrogen peroxide, 0.03 wt. % of citric acid and 0.5 wt. % of abrasive grains with pure water is used, but it is not limited thereto. This polishing liquid is fed to the polishing pad 413 of the second disk 403B through the above-described slurry feeding pipe 418 a.
In abrasive-grain-using chemical mechanical polishing, the Cu film 46 which has partially remained over the TiN film 45 is removed, followed by the removal of the TiN film 45 outside the interconnection grooves 40 to 44. The polishing of the surface of the Cu film 46 inside of the interconnection grooves 40 to 44 is suppressed by polishing under the conditions to give a polishing selection ratio of the Cu film 46 to the TiN film (barrier layer) not greater than that for the above-described abrasive-grain-free chemical mechanical polishing, for example, not greater than 3.
On the surface of the substrate 1 having Cu-embedded interconnections 46 a to 46 e formed thereon, the slurry residue containing particles such as abrasive grains or metal particles such as Cu oxide has been attached. In order to remove this slurry residue, the substrate 1 is washed with BTA-containing pure water in the clean station 404 as shown in FIG. 34. At this time, megasonic washing wherein high-frequency vibration of 800 kHz or greater is applied to the washing liquid to release the slurry residue from the surface of the substrate 1 may be used in combination. Then, the substrate 1, which is maintained under a wet condition to prevent surface drying, is transported from the polishing treatment part 401 to the post-washing part 402. In the first washing part 409A, the substrate 1 is subjected to scrub washing with a washing liquid containing 0.1 wt. % of NH4 0H, followed by scrub washing with pure water in the second washing part 409B. As described above, the post-washing part 402 is covered with a shading wall 430 to prevent corrosion of the Cu interconnections 46 a to 46 e due to exposure of the surface of the substrate 1 to light during washing.
The steps after the scrub washing are similar to those of Embodiment 1. FIG. 43 illustrates the whole flow chart of the above-described formation process of the Cu interconnections 46 a to 46 e.
According to this embodiment, the TDDB characteristics can be improved more than that of Embodiment 1. FIG. 44 is a graph illustrating TDDB and that of this embodiment is shown by Line E. For reference, TDDB (Line Ref) without treatment and that (Line A) subjected to abrasive-grain-using chemical mechanical polishing (Embodiment 1) are shown together. The TDDB is improved, as shown in Line F, only by the abrasive-grain-free chemical mechanical polishing without ammonia plasma treatment. Such an improvement in TDDB is presumed to occur because damage to the silicon oxide film can be reduced in the case of the abrasive-grain-free CMP. In the case of the abrasive-grain-using CMP, on the other hand, the slurry contains abrasive grains (such as alumina) having a particle size (secondary particle size) of 2 to 3 μm. These abrasive grains make micro scratches and cause a damage to the surface of the silicon oxide film 39. The abrasive-grain-free slurry does not contain abrasive grains or contains, if any, a very small amount of them so that the damage can be lessened to the minimum. The improvement in TDBB is presumed to be brought about because of the above-described reasons.
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U.S. Classification 438/622, 257/E21.577, 257/E21.583, 257/E21.304, 257/E21.588, 438/637, 257/E21.311, 257/E21.582, 257/E21.591, 257/E21.576
International Classification H01L21/3205, H01L21/768, H01L21/70, H01L21/28, H01L23/532, H01L21/321, H01L21/02, H01L21/3213
Cooperative Classification H01L21/76834, H01L21/76826, H01L21/76838, H01L23/53238, H01L21/76882, H01L21/3212, H01L21/76883, H01L21/68792, H01L21/02063, H01L2924/0002, H01L21/7684, H01L21/02074, H01L21/76886, H01L21/76829, H01L21/3185, H01L21/67115, H01L21/32136
European Classification H01L21/687S22, H01L21/768B8P, H01L21/02F4B2, H01L21/768B10S, H01L21/67S2H6, H01L21/768B10, H01L21/318B, H01L21/768C4P, H01L21/321P2, H01L21/768C2, H01L21/768C4E, H01L21/02F4D4, H01L21/768C, H01L21/768C8, H01L23/532M1C4