Source: http://www.google.com/patents/US6738601?dq=6519629
Timestamp: 2017-08-20 04:37:51
Document Index: 388107292

Matched Legal Cases: ['§120', '§119', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

Patent US6738601 - Adaptive radio transceiver with floating MOSFET capacitors - Google Patents
An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com/patents/US6738601?utm_source=gb-gplus-sharePatent US6738601 - Adaptive radio transceiver with floating MOSFET capacitors
Publication number US6738601 B1
Application number US 09/691,630
Also published as US6917789, US6920311, US6987966, US7116945, US7130579, US7233772, US7349673, US7356310, US7389087, US7697900, US7756472, US8023902, US8116690, US20040195917, US20050153664, US20050186925, US20070049205, US20070285154, US20080182526, US20080191313, US20080290966, US20100255792
Publication number 09691630, 691630, US 6738601 B1, US 6738601B1, US-B1-6738601, US6738601 B1, US6738601B1
Inventors Ahmadreza Rofougaran, Maryam Rofougaran, Shahla Khorram
Patent Citations (9), Non-Patent Citations (1), Referenced by (118), Classifications (62), Legal Events (8)
US 6738601 B1
a first node for receiving a signal;
a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node;
a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and
a second node coupled to receive the signal from the at least one other node of the second transistor;
wherein the first transistor and the second transistor provide a capacitance between the first node and the second node.
2. The capacitor of claim 1 wherein the first and second transistors each comprises a metal oxide semiconductor (MOS).
9. The integrated circuit of claim 8 wherein the first and second transistors each comprises a metal oxide semiconductor (MOS).
a plurality of capacitors each of the capacitors comprising:
wherein the first transistor and the second transistor provide a capacitance between the first node and the second node;
the first nodes of the capacitors being coupled together and the second nodes of the capacitors being coupled together; and
a plurality of switches each being positioned between a different one of the capacitors and the respective capacitors first or second node.
16. The tunable capacitor array of claim 15 wherein the first and second transistors for each of the capacitors each comprises a metal oxide semiconductor (MOS).
The present application is a continuation of co-pending patent application Ser. No. 09/634,552, filed Aug. 8, 2000, priority of which is hereby claimed under 35 U.S.C. §120. The present application also claims priority under 35 U.S.C. §119(e) to provisional Application No. 60/160,806, filed Oct. 21, 1999; Application No. 60/163,487, filed Nov. 4, 1999; Application No. 60/163,398, filed Nov. 4, 1999; Application No. 60/164,442, filed Nov. 9, 1999; Application No. 60/164,194, filed Nov. 9, 1999; Application No. 60/164,314, filed Nov. 9, 1999; Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; Application No. 60/165,356; filed Nov. 12, 1999; Application No. 60/165,355, filed Nov. 12, 1999; Application No. 60/172,348, filed Dec. 16, 1999; Application No. 60/201,335, filed May 2, 2000; Application No. 60/201,157, filed May 2, 2000; Application No. 60/201,179, filed May 2, 2000; Application No. 60/202,997, filed May 10, 2000; Application No. 60/201,330, filed May 2, 2000. All these applications are expressly incorporated herein by referenced as though fully set forth in full.
For the resistor values shown in FIG. 6, the biquad stage outputs are: V O1 = A  ( 1 + j   RC   ω )  V II + 2  QV IQ ( 1 + j   RC   ω ) 2 + 4  Q 2 ( 1 ) and V OQ = A  - 2  QV II + ( 1 + j   RC   ω )  V IQ ( 1 + j   RC   ω ) 2 + 4  Q 2 ( 2 )
After the received signal is downconverted, the desired channel in the I path lags the one in the Q path, that is, VII=−jV IQ, and therefore: H  ( j   ω ) = V o V I  ( j   ω ) = A 1 + j   RC   ω - j   2  Q ( 3 )
This shows a passband gain of A 122 at a center frequency of 2Q/RC 124, with a 3-dB bandwidth of 2RC 126. Thus, the quality factor of the second-order stage will be Q. For the image signal however, the signal at the I branch leads, and as a result: H  ( j   ω ) = A 1 + j   R   C   ω + j   2  Q ( 4 )
which shows that the image located at 2Q/RC is rejected by 1 ( 1 + ( 4  Q )  2 .
Therefore, the biquad stage has an asymmetric frequency response, that is, the desired signal may be assigned to positive frequencies, whereas the image is attributed to negative frequencies. In general, the frequency response of the biquad stage is obtained by applying the following complex-domain transformation to a normalized real-domain lowpass filter: j   ω → j  ( ω - ω 0 ) BW ( 5 )
P i,BP =BW·P i,LP +jω 0=αi ·BW+j(ω0 +β i ·BW) (6)
The complex filter is realized by cascading n biquad stages. Therefore, similar to real-domain bandpass filters, an nth order complex filter uses 2×n integrators. Based on equation (3), each biquad stage has a pole equal to −1/RC+j2Q/RC. Thus: α i · BW = - 1 RC ( 7 ) and ω o + β i · BW = 2  Q RC ( 8 )
In addition to image rejection, the complex frequency transformation of the biquad stage (equation (5)) provides for its frequency response to be symmetric around its center frequency as shown in FIG. 7. This is in contrast to regular bandpass filters which use the following real-domain transformation: j   ω → j  ( ω 2 - ω 0 2 ) BW · ω ( 9 )
The described exemplary embodiment of the biquad stage can be modified to obtain a sharper rejection or notch at an undesired signal at a specific frequency. This can be achieved in the biquad stage by adding zeros. Assume that the input resistors at the biquad input (Ri 114 in FIG. 6) is replaced with an admittance Yi. For the received signal, the frequency response of the biquad stage will be equal to: H  ( j   ω ) = R · Y i 1 + j   RC   ω - j   2  Q ( 10 )
In order to have a zero located at jω axis in the frequency response, Yi should contain a term such as 1−-ω/ωz. If Yi is simply made of a resistor Rz in parallel with a capacitor Cz, then the input admittance will be equal to: Y i = 1 R z + j   ω   C z ( 11 )
FIG. 9 shows Yi with the capacitor Cz 132 connected to the Q input 134 and the resistor Rz connected to the I input 136. Now the current I will be equal to: I = V R z + j   C z  ω · ( j   V ) ( 12 )
Therefore, the input admittance will be equal to: Y i = 1 V = 1 R z - C z  ω ( 13 )
FIG. 10 shows a single biquad stage modified to have a zero at the jω axis. The biquad stage includes capacitors 138, 140, 142, 144. The combination of capacitors 138, 140, 142, 148 and resistors 116, 118 determines a complex zero with respect to the center frequency. The transfer function for the received signal will be: H  ( j   ω ) = A  1 - RC z A  ω 1 + j   RC   ω - j   2  Q ( 14 )
ωz,1,2=ω0±ωz,LP ·BW (15)
The center frequency of the complex filter can be adjusted by setting 1/RuCu equal to a reference frequency generated, by way of example, by the crystal oscillator in the controller. The filter is automatically tuned by monotonic successive approximation as described in detail in Section 4.0 herein. Once the value of RuCu is set, the complex filter characteristics depends only on the four-bit code for the capacitors and the five-bit code for the resistors. For example, assume that the value of the resistors in the biquad stage of FIG. 6 is as following: R1=nARu, Rf=nQRu, and Rc=nQRu. Likewise, assume that C=nCCu, where nC is a constant, and that 1/RuCu=ωu. The value of ωu is set to a reference crystal by a successive approximation feedback loop. The filter frequency response for the received signal will be: H  ( j   ω ) = n F n A 1 + j   n c  n F  R u  C u  ω - j  n F n Q ( 16 )
Therefore, the biquad stage gain (A), center frequency (ω0), and bandwidth (BW) will be equal to: A = n F n A ( 17 ) ω 0 = 1 n C  n Q · ω u ( 18 ) BW = 1 n C  n F · ω u ( 19 )
Therefore, the RSSI maximum input level is S, and the ideal RSSI minimum input level is S/An, where A is the gain of each differential amplifier and n is the number of the differential amplifiers. Thus, the ideal dynamic range is calculated as follows: Ideal   Dynamic   Range = 20  log  S S A n = 20   log   A n = 20  ( n )  log   A ( 22 )
However, in the case of a large amount of gain, the input level will be limited with the input noise and the dynamic range will also be limited to: Dynamic   Range = 20  log  S σ n ( 23 ) σ n = total   noise   rms σ n = ( BW ) × Noise   Factor
For an input being in the following range: S A n - m < V i   n < S A n - m - 1 ( 24 )
This is further simplified to: RSSI = ( A   β ) 2 ( A   β ) 2 - 1  V i   n 2  [ ( A   β ) 2  ( n - m - 1 ) - ] + m   β 2  S 2 ( 26 ) RSSI = 1 ( A   β ) 2 - 1  V i   n 2  ( A   β ) 2  ( n - m ) + m   β 2  S 2 ( 27 )
C = Δ   RSSI 2  n   log   A ( 31 ) ( Ideal )   RSSI = Δ   RSSI 2  n   log   A  log   V i   n 2 ( 32 )
To find the relation between the gain of a differential amplifier, the gain of a rectifier, and the maximum input range of the combined differential amplifier and the rectifier, the RSSI will be calculated for the two consecutive differential amplifier and rectifier combinations (see equations (33) and (34)) for both ideal RSSI equations (32) and approximated RSSI equation (27): V i   n1 = S ( A ) n - m ( 33 ) V i   n2 = S ( A ) n - m - 1 ( 34 )
(Ideal) RSSI 2 −RSSI 1=log(A)2 (35)
Using equations (18) and (12), the following expression is achieved: Δ   RSSI n = β 2  S 2 ( 38 )
Plugging equation (19) into (8) results in the following: RSSI = 1 ( A   β ) 2 - 1  ( A   β ) 2  ( n - m )  V i   n 2 + m  Δ   RSSI n ; S A n - m < V i   n < S A n - m - 1 ( 39 )
FIG. 16(a) shows a schematic diagram for an exemplary embodiment of the differential amplifier used in the type II core amplifier. The differential input signal is fed to the gates of transistor amplifiers 955, 957. The amplified differential output signal is provided at the drains of the transistor amplifiers 955, 957. The gain of the transistor amplifiers is set by load transistors 958, 860, each connected between the drain of one of the transistor amplifiers and a power source. More particularly, the gain of the differential amplifier is determined by the ratio of the square root of transistor amplifiers-to-load transistors. Gain  ( A ) = w i   n w i   n = 200 6 ≈ 5.8 ( 40 )
When the transistors 962, 964, 966, and 968 are operating in the saturation region, the following equations are shown for the differential output current DISQBI where k is the ratio of the two unbalanced source-coupled transistors: if   Δ   I SQM1 = ( I D1 + I D4 ) - ( I D2 + I D3 ) = 2  ( I D   C + I SQ ) = 2  k - 1 k + 1  I o - 4  k  ( k - 1 )  β N ( k + 1 ) 2  V I 2 ( 41 )
The input dynamic range of the full rectifier is then: if   Δ   I SQM1 = O , V i = ± I o β N   k + 1 2   k ( 42 )
The square law portion of equation (41) multiplied by the resistance provides the β2S2 of equation (42): β 2  S 2 = 4  k  ( k - 1 )   β N ( k + 1 ) 2  V i 2  R L ( 43 )
By plugging the Vi from equation (42) and replacing β2S2 from equation (38), the following relation is obtained: Δ   RSSI n = 2  k - 1 k + 1  I o  R L ( 44 )
1st:f1 f1 x(1+1/N) f1 x(1 − 3/N) f1 x(1 + 5/N)
3rd:3f1 f1 x(3−1/N) f1 x(3 + 3/N) f1 x(3 − 5/N)
5th:5f1 f1 x(5+1/N) f1 x(5 − 3/N) f1 x(5 + 5/N)
−Cos (ω1 t)·⅓ Cos(3ω1 t)−Sin(ω1 t)·⅓ Sin(3ω1 t)→−⅓ Cos(2ω1 t) (47)
For N=2, the LO generator output will have a frequency of 1.5f1, and the closest spurs will be located ±f1 away from the output. These spurs can be rejected by positioning LC filters (not shown) at the output of each circuit in the LO generator. A second-order LC filter tuned to f0, with a quality factor Q, rejects a signal at a frequency of f as given in the following equation:  H  ( f )  = f Qf 0 [ 1 - ( f f 0 ) 2 ] + ( f Qf 0 ) 2 ( 49 )
The following discussion changes based on the Q value. Considering a Q of about 5 for the inductor, with f0=1.5f1, the spur located at 2.5f1 is rejected by about 15 dB by each LC circuit. This spur is produced at the LO generator output due to the mixing of the VCO third harmonic (at 3f1) with the divider output (at 0.5f1). This signal is attenuated by 10 dB since the third harmonic of a square-wave is one third of the main harmonic, 15 dB at the LC resonator at the mixers output tuned to 1.5f1, and another 15 dB at the output of the buffers (900,902 in FIG. 33). This gives a total rejection of 40 dB. When applied to the mixers in the transmitter, this LO generator output will upconvert the baseband data to 2.5f1. With LC filters (not shown) positioned at the upconversion mixers and PA output in the transmitter, another 15+15=30 dB rejection is obtained (FIG. 33).
FIG. 33(a) shows a signal passing through a limiting buffer 912 (such as the buffers implemented in the LO generator). When a large signal at a frequency of f accompanied with a small interferer at a frequency of Δf 911 away pass through a limiting buffer, at the limiter output the interferer produces two tones±Δf 914, 916 away from the main signal, each with 6 dB lower amplitude. Therefore, the spur at 2.5f1 will actually be 10+15+15+6=46 dB attenuated when it passes through the buffer, instead of the 40 dB calculated above. It will also produce an image at 0.5f1 which is 10+15+22+6=53 dB lower than the main signal. This will dominate the spur at 0.5f1 because of the third harmonic of the divider mixed with the VCO signal, which is more than 75 dB lower than the main signal.
where ω1 is the VCO radian frequency, and ω2 is the divider radian frequency, equal to 0.5ω1. By simplifying equation (25) and equation (26), the signals at the output of mixers will be: V out_I = - Sin  ( θ 2 ) · Sin  ( ( ω 1 - ω 2 )  t + θ 2 ) + Cos  ( θ 2 ) · Cos  ( ( ω 1 + ω 2 )  t + θ 2 )   and ( 52 ) V out_Q = - Sin  ( θ 2 ) · Cos  ( ( ω 1 - ω 2 )  t + θ 2 ) + Cos  ( θ 2 ) · Sin  ( ( ω 1 + ω 2 )  t + θ 2 ) ( 53 )
The above equations show that regardless of the value of θ, the outputs are always in quadrature. However, other effects should be evaluated. First, a spur at ω1−ω2=0.5ω1 is produced at the output. This spur can be attenuated by 2×22=44 dB by the LC filters at the mixer and its buffer outputs. Thus, for 60 dB rejection, the single sideband mixers need to provide an additional 16 dB of rejection ( about 0.158). Based on equation (53), tan(θ/2)=0.158, or θ˜18°, phase accuracy of better than 18° can generally be achieved. Second, phase error at the VCO output lowers the mixer gain (term Cos(θ/2) in equation (52) or (53)). For a phase error of 18°, the gain reduction is, however, only 0.1 dB, which is negligible. For θ=90° (a single-phase VCO), both sidebands are equally upconverted at the mixer output. However, the LC filters reject the lower sideband by about 44 dB. The mixer gain will also be 3 dB lower. This will slightly increase the power consumption of the LO generator. If θ=180° (the VCO I and Q outputs are switched), the lower sideband is selected, and the desired sideband is completely rejected.
Similarly, the LO generator will not be sensitive to the phase imbalance of the divider outputs if the VCO is ideal. However, if there is some phase inaccuracy at both the divider and VCO outputs, the LO generator outputs will no longer be in quadrature. In fact, if the VCO output has a phase error of q1 and the divider output has a phase error of q2, the LO generator outputs will be: V out_I = - Sin  ( θ 1 - θ 2 2 ) · Sin  ( ( ω 1 - ω 2 )  t + θ 1 - θ 2 2 ) + Cos  ( θ 1 + θ 2 2 ) · Cos  ( ( ω 1 + ω 2 )  t + θ 1 + θ 2 2 )   and  ( 54 ) V out_Q = - Sin  ( θ 1 + θ 2 2 ) · Cos  ( ( ω 1 - ω 2 )  t + θ 1 - θ 2 2 ) + Cos  ( θ 1 - θ 2 2 ) · Sin  ( ( ω 1 + ω 2 )  t + θ 1 + θ 2 2 ) ( 55 )
This shows that the outputs still have phases of 0 and 90°, but their amplitudes are not equal. The amplitude imbalance is equal to: Δ   A A = 2   Cos  ( θ 1 + θ 2 2 ) - Cos  ( θ 1 - θ 2 2 ) Cos  ( θ 1 + θ 2 2 ) + Cos  ( θ 1 - θ 2 2 ) = 2   tan  ( θ 1 2 ) × tan   ( θ 2 2 ) ( 56 )
Any amplitude imbalance in the signals at the VCO and divider output will only cause a second order mismatch in the amplitude of the LO generator signals, and the output phase will remain 0 and 90°. If the standard deviation of the amplitude imbalance at the VCO and divider are the same and equal to σa, then the standard deviation of the LO generator output amplitude imbalance (σA) will be: σ A ≈ ( σ α ) 2 2 ( 58 )
With an input dynamic range of 50 dB, the RSSI circuit is designed to detect the levels of rejection provided by the polyphase filtering. The outputs of RSSI block 284 and RSSI block 285 are coupled to a comparator 288 where the level of signal rejection of each polyphase filter is compared by comparator 288. The outputs of the RSSI blocks are also coupled to the control logic 286. The control logic 286 determines from the RSSI outputs which polyphase filter has a lower amount of signal suppression. Then, the control logic 286 adjusts the frequency tuning of that filter in an incremental step via the control logic 286. This is done by either increasing the tuned frequency of the first filter (polyphase A) filter 280, or by decreasing the tuned frequency of the second filter (polyphase B) 282 by changing the appropriate 4-bit control word. This process continues in successive steps until the 4-bit control word in each branch are identical, at which point, the RC values of the two polyphase filters are equal. The 4-bit control word provides a maximum deviation of only ±5%.
Complementary MOS switches or other switches known in the art, can be used in the capacitor array. The capacitor array can include any number of capacitors. In the exemplary embodiment, the capacitor array capacitors 290, 292, 294, 296, 298 are connected in parallel. Switches 300, 302, 304, 306 are used to switch the capacitors 292,294,296,298, respectively, in and out of the capacitor array. In the described embodiment, capacitor 290 is 2.4 pF, capacitor 292 is 2.4 pF, capacitor 294 is 1.2 pF, capacitor 296 is 0.6 pF, capacitor 298 is 0.3 pF. The switch positions are nominally selected to produce an equivalent capacitance equal to 4.8 pF. A code of “0111” means that capacitors 294, 296, 298 are switched out of the capacitor array and capacitors 290, 292 are in parallel.
FIG. 42 shows an exemplary embodiment of the bandgap calibration circuit. The bandgap calibration circuit uses the reference clock provided from the LO generator and a reference resistor RREF 236 to adjust a tunable resistance value RPOLY 238 in a compare-and-increment loop until an optimum value is obtained. In embodiments of the present invention which are integrated into a single IC, the reference resistor RREF 236 can be off-chip to provide improved calibration accuracy. A 4-bit control word is output to accurately calibrate the resistors in the transmitter, receiver and LO generator within ±2%. Transistors 224, 226, 228, 230, 232, 234 form a cascode current with a reference current IREF. The transistors 224, 230 each have their gates tied to their respective sources to set up the reference current IREF. By tying the gates of the transistors 224, 230, respectively to the gates of the transistors 226, 232, the reference current IREF is mirrored to the reference resistor RREF 236. Similarly, by tying the gates of the transistors 228, 234, respectively to the gates of the transistors, the reference current IREF is also mirrored to the tunable resistor RPOLY 238. The voltage generated across the tunable resistor RPOLY 238 is compared, using a latched comparator 240, to the voltage generated across the reference resistor RREF 236. The value of the tunable resistor RPOLY 236 is incremented in successive steps, preferably, every 0.5 μs, through the utilization of control logic 242 that is clocked, by way of example, at 2 MHz. This process continues until the voltage VPOLY across the tunable resistor RPOLY 238 matches the voltage VREF across the off-chip reference resistor RREF 236 causing the output of the comparator to change states and disable the control logic 242. Once the control logic is disabled, the 4-bit control word can be used to accurately calibrate the resistors in the transmitter, receiver and LO generator.
US5945878 * Feb 17, 1998 Aug 31, 1999 Motorola, Inc. Single-ended to differential converter
US6947720 * May 2, 2001 Sep 20, 2005 Rf Micro Devices, Inc. Low noise mixer circuit with improved gain
US6968019 * Sep 21, 2001 Nov 22, 2005 Broadcom Corporation IF FSK receiver
US6999740 * Feb 28, 2002 Feb 14, 2006 Sony Corporation Semiconductor integrated circuit and radio communication apparatus using same
US7437345 * Sep 22, 2004 Oct 14, 2008 Sony Corporation Image rejection mixer and multiband generator
US8120391 * Sep 30, 2009 Feb 21, 2012 Infineon Technologies Ag Circuit arrangement including a voltage supply circuit and semiconductor switching element
US8344764 Jan 26, 2012 Jan 1, 2013 Infineon Technologies Ag Circuit arrangement including voltage supply circuit
US8600315 * May 29, 2007 Dec 3, 2013 Broadcom Corporation Method and system for a configurable front end
US9564856 Jan 9, 2013 Feb 7, 2017 Qualcomm Technologies, Inc. Amplifier circuit with improved accuracy
US20020119762 * Feb 28, 2002 Aug 29, 2002 Takahiro Ogihara Semiconductor integrated circuit and radio communication apparatus using same
US20040142674 * Jan 16, 2003 Jul 22, 2004 Nokia Corporation Direct conversion receiver having a low pass pole implemented with an active low pass filter
US20050159129 * Sep 22, 2004 Jul 21, 2005 Sony Corporation Image rejection mixer and multiband generator
US20060267412 * Jul 5, 2005 Nov 30, 2006 Hung-Yi Kuo Chip with embedded electromagnetic compatibility capacitors and related method
US20100085105 * Sep 30, 2009 Apr 8, 2010 Infineon Technologies Ag Circuit arrangement including a voltage supply circuit and semiconductor switching element
US20120231752 * May 29, 2007 Sep 13, 2012 Razieh Roufoogaran Method and System for a Configurable Front End
WO2013152795A1 * Apr 12, 2012 Oct 17, 2013 Epcos Ag Rssi system and bias method for amplifier stages in rssi systems
WO2014108179A1 * Jan 9, 2013 Jul 17, 2014 Qualcomm Technologies, Inc. Amplifier circuit with improved accuracy
U.S. Classification 455/66.1, 455/78, 361/301.1, 455/86, 327/434, 455/73, 361/281, 361/270, 327/427, 455/76
Cooperative Classification H03H7/42, H03F2200/336, H03F2203/45138, H03F2203/45638, H03F3/45475, H03F2200/451, H04B17/19, H03F2203/45386, H03J2200/10, H03H11/22, H03F1/56, H03H11/344, H03G11/00, H03G3/001, H03B21/01, H03F2200/318, H04B17/104, H03H2011/0494, H03F2203/45528, H03F3/19, H03L7/18, H03H21/0012, H03F3/245, H03B27/00, H03H11/1291, H03H21/0001, H03F2203/45526, H03L7/099, H03F3/45179, H04B17/14
European Classification H04B17/00A2S, H04B17/00A3S, H03H11/22, H03F3/45S1K, H03H7/42, H03G3/00D, H03G11/00, H03H11/34D, H03L7/099, H04B17/00A1T, H03B21/01, H03F3/24B, H03L7/18, H03F3/45S1B, H03F1/56, H03F3/19, H03B27/00, H03H11/12F, H03H21/00B, H03H21/00A
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROFOUGARAN, AHMADREZA;ROFOUGARAN, MARYAM;KHORRAM SHAHLA;REEL/FRAME:011581/0979;SIGNING DATES FROM 20010220 TO 20010221