Source: http://www.google.com/patents/US7266144?dq=6,240,376
Timestamp: 2014-12-20 15:17:21
Document Index: 263536214

Matched Legal Cases: ['ART1', 'ART20', 'ART1', 'ART2', 'ART20', 'ART1', 'ART20', 'ART1', 'ART20', 'ART3', 'ART3']

Patent US7266144 - Data bit transition determination method and apparatus for spread spectrum ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsApparatus and methods for determining the timing of the data bit transitions. �N� assumptions of data bit transitions are used for determining N integrations of an incoming spread signal for data bit time periods where N is the data bit time period divided by the code time period. In a first variation,...http://www.google.com/patents/US7266144?utm_source=gb-gplus-sharePatent US7266144 - Data bit transition determination method and apparatus for spread spectrum signalsAdvanced Patent SearchPublication numberUS7266144 B1Publication typeGrantApplication numberUS 11/199,407Publication dateSep 4, 2007Filing dateAug 8, 2005Priority dateJul 31, 2001Fee statusPaidAlso published asUS6970500Publication number11199407, 199407, US 7266144 B1, US 7266144B1, US-B1-7266144, US7266144 B1, US7266144B1InventorsJeffrey D. SandersOriginal AssigneeSanders Jeffrey DExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (7), Classifications (8), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetData bit transition determination method and apparatus for spread spectrum signalsUS 7266144 B1Abstract Apparatus and methods for determining the timing of the data bit transitions. �N� assumptions of data bit transitions are used for determining N integrations of an incoming spread signal for data bit time periods where N is the data bit time period divided by the code time period. In a first variation, the N assumptions use N start times separated by code time periods. In a second variation, the N assumptions use N sign inversion times separated by code time periods. In either variation the unsigned values of the N integrations, respectively, may be combined for several data bit time periods. The assumed transition timing that results in the strongest of the N integrations is indicative of the timing of the data bit transitions.
1. A method for determining a data bit transition time for an incoming signal, comprising:
integrating an incoming signal using staggered first through Nth assumed data bit transition times for determining first through Nth integrations, respectively, said N at least two, using integration time periods about equal to a data bit time period for said incoming signal;
combining at least two said first integrations for providing a first combined integration and so on through combining at least two said Nth integrations for providing an Nth combined integration;
identifying said data bit transition time based on said combined integrations; and wherein:
identifying said data bit transition time includes determining said data bit transition time from a certain one of said first through Nth assumed data bit transition times corresponding to a largest one of said first through Nth combined integrations.
2. A method for determining a data bit transition time for an incoming signal, comprising:
said N is in a range of two to a number that is a data bit time period divided by a code time period for said incoming signal.
3. A method for determining a data bit transition time for an incoming signal comprising:
identifying said data bit transition time based on said combined integrations; and further comprising:
using said data bit transition time for calculating a pseudorange, wherein said incoming signal is a global positioning system (GPS) signal.
said staggered first through Nth assumed data bit transition times are separated by a time period of a code epoch for said incoming signal.
using said data bit transition time for acquiring said incoming signal.
using said data bit transition time for determining senses of data bits of said incoming signal.
using said pseudorange for determining a location.
8. A method for determining a data bit transition time for an incoming signal, comprising:
using said data bit transition time for calculating a pseudorange, wherein said incoming signal is a global orbiting navigation system (GLONASS) signal.
9. A method for determining a data bit transition time for an incoming signal, comprising:
using said data bit transition time for calculating a pseudorange, wherein said incoming signal is a Galileo satellite system signal.
10. A method for determining a data bit transition time for an incoming signal, comprising:
integrating said incoming signal using staggered first through Nth inversions for providing first through Nth integrations, respectively; and
identifying said data bit transition time based on said integrations; wherein:
integrating includes accumulating one of (i) positive or (ii) negative accumulations before said first through Nth inversions and the other of (i) positive or (ii) negative accumulations after said first through Nth inversions for providing said first through Nth integrations.
11. An apparatus for a determining data bit transition time for an incoming signal, comprising:
a correlation machine for integrating said incoming signal using staggered first through Nth assumed said data bit transition times for determining first through Nth integrations, respectively; and combining at least two said first integrations for providing a first combined integration and so on through combining at least two said Nth integrations for providing an Nth combined integration, said N at least two, using integration time periods about equal to a data bit time period for said incoming signal for providing said first through said Nth integrations; and
a data bit transition detector for using said combined integrations for identifying an actual said data bit transition time; wherein:
the data bit transition detector identifies said data bit transition time by determining said data bit transition time from a certain one of said first through Nth assumed data bit transition times corresponding to a largest one of said first through Nth combined integrations.
12. An apparatus for a determining data bit transition time for an incoming signal, comprising:
13. An apparatus for a determining data bit transition time for an incoming signal, comprising:
a correlation machine for integrating said incoming signal using staggered first through Nth assumed said data bit transition times for determining first through Nth integrations, respectively; and combining at least two said first integrations for providing a first combined integration and so on through combining at least two said Nth integrations for providing an Nth combined integration, said N at least two, using integration time periods about equal to a data bit time period for said incoming signal for providing said first through said Nth integrations;
a data bit transition detector for using said combined integrations for identifying an actual said data bit transition time; and
a navigation processor for using said data bit transition time for calculating a pseudorange, wherein said incoming signal is a global positioning system (GPS) signal.
14. The apparatus of claim 13; wherein:
said staggered first through Nth assumed data bit transition times are separated by a code time period for said incoming signal.
using said data bit transition times for acquiring said incoming signal.
18. An apparatus for a determining data bit transition time for an incoming signal, comprising:
a navigation processor for using said data bit transition time for calculating a pseudorange, wherein said incoming signal is a global orbiting navigation system (GLONASS) signal.
19. An apparatus for a determining data bit transition time for an incoming signal, comprising:
a correlation machine for integrating said incoming signal using staggered first through Nth assumed said data bit transition times for determining first through Nth integrations; respectively; and combining at least two said first integrations for providing a first combined integration and so on through combining at least two said Nth integrations for providing an Nth combined integration, said N at least two, using integration time periods about equal to a data bit time period for said incoming signal for providing said first through said Nth integrations;
a navigation processor for using said data bit transition time for calculating a pseudorange, wherein said incoming signal is a Galileo satellite system signal.
20. An apparatus for determining a data bit transition time for an incoming signal, comprising:
a correlation machine including a sign inverter for generating staggered first through Nth inversions and an inverting accumulator for using said first through Nth inversions for integrating said incoming signal for providing first through Nth integrations, respectively; and
a data bit transition detector for using said integrations for identifying said data bit transition time; wherein:
the data bit transition detector identifies said data bit transition time by accumulating one of (i) positive and (ii) negative accumulations before said first through Nth inversions or the other of (i) positive or (ii) negative accumulations after said first through Nth inversions for providing said first through Nth integrations.
21. A memory having computer-readable instructions for reading by a computer for carrying out the following steps:
identifying said data bit transition time based on said combined integrations; and
CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of application Ser. No. 09/919,217 filed Jul. 31, 2001 now U.S. Pat. No. 6,970,500 by the same inventor and assigned to the same assignee.
Direct sequence spread spectrum signals are used for code division multiple access (CDMA) radio communication, and global positioning (GPS) and global navigation satellite (GLONASS) location systems. As an example, the global positioning system is a system using GPS satellites for broadcasting GPS signals having information for determining location and time. Each GPS satellite broadcasts a GPS signal having 20 milliseconds (ms) GPS data bits modulated by a repeating 1 ms pseudorandom noise (PRN) code having 1023 bits or chips. The PRN code for each GPS satellite is distinct, thereby enabling a GPS receiver to distinguish the GPS signal from one GPS satellite from the GPS signal from another GPS satellite. The 20 ms GPS data bits are organized into frames of fifteen hundred bits. Each frame is subdivided into five subframes of three hundred bits each.
SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method and apparatus for determining timing of data bit transitions in a direct sequence spread spectrum signal after frequency and code phase of the signal are known.
Briefly, in a preferred embodiment, a signal receiver of the present invention uses �N� assumptions for data bit transitions for determining N separate integrations, respectively, of an incoming spread spectrum signal, where N is the data bit time period of the signal divided by the time period of the spreading code. For an example case of a GPS signal receiver, the data bit time period is 20 milliseconds (ms), the spread code time period is 1 ms, and N is 20. In a first variation, the receiver uses N start times separated by time lengths equal to the time period of the code for integrating the incoming signal over time periods equal to the data bits. In a second variation, the signal receiver uses N sign inversion times separated by time lengths equal to the time period of the code for inverting the accumulation of the incoming signal during time periods equal to the data bits. In either variation the absolute (unsigned) values of the N integrations may be combined for several data bit time periods for providing N multibit integrations, respectively. The assumed transition timing that results in the largest of the N integrations is indicative of the timing of the data bit transitions. The data bit transition timing is then used for integrating the incoming signal over time lengths of a data bit for determining the sense of the data bit and integrating the incoming signal for up to several data bit time periods for acquiring and tracking the signal without having the nullifying effect of inversions of the data bits.
IN THE DRAWINGS FIG. 1 is a block diagram of a spread spectrum signal receiver of the present invention;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 illustrates a block diagram of a spread spectrum signal receiver of the present invention referred to by a general reference number 10 for receiving an incoming spread spectrum signal. The spread spectrum signal has a carrier frequency modulated by data bits that are modulated by a spreading code that repeats several times for each data bit. As described below, the receiver 10 is adapted for receiving the coarse/acquisition (C/)A code GPS signal. However, it will be apparent to those skilled in the art that the present invention can be applied for receiving other direct sequence spread spectrum signals for two way and CDMA radio communication, P or P(Y) code GPS, GLONASS, and the like.
The local generator 22 generates a local spread spectrum signal in the same format as the I and Q samples of the incoming spread spectrum signal. The correlation machine 20 includes a data bit accumulator 30 for providing integrations for the correlation and accumulation of the incoming I and Q samples with respect to the local signal for time lengths equal to the data bit time period as diagrammed in the time charts of FIGS. 3A-B and described in the accompanying detailed descriptions below. In a preferred embodiment the data bit accumulator 30 provides �N� separate integrations of an incoming spread spectrum signal in parallel. In an alternative embodiment, the N separate integrations are provided serially using N sequential time periods, each equal to the data bit time period. Preferably, N is equal to the data bit time period of the signal divided by the time period of the spreading code. However, in alternative embodiments N may be another number as low as two.
For the C/A code GPS signal, a preferred �N� is twenty (20) for the 20 ms of the data bit time period divided by the 1 ms of the code time period. In alternative embodiments, N may be another number such as ten (10) for the 20 ms of the GPS data bit time period divided by 2 ms for two of the 1 ms code time periods or five (5) for the 20 ms of the GPS data bit time period divided by 4 ms for four of the 1 ms code time periods or four (4) for the 20 ms of the GPS data bit time period divided by 5 ms for five of the 1 ms code time periods or two (2) for the 20 ms of the GPS data bit time period divided by 10 ms for ten of the 1 ms code time periods.
The memory 24 includes a signal processor 32, a multibit accumulator 34, a data bit transition detector 36, and a navigation processor 38. The microprocessor 26 including accessory hardware reads the programmed instructions and data, and writes data to the memory 24 in a conventional manner for controlling the elements of the receiver 10. The signal processor 32 includes data and programming instructions for closing carrier and code loops with the correlation machine 20 and local generator 22 for acquiring and tracking the incoming signal. The multibit accumulator 34 is a part of the correlation machine 20 having data and programmed instructions using information from the data bit accumulator 30 for determining integrations, denoted INT1 through INTN in FIGS. 3A-B, for one or more data bit time periods.
FIG. 2A is a block diagram of an embodiment of the data bit accumulator 30 of the present invention referred to with a reference identifier 30A for providing absolute values (unsigned values) of I and Q accumulations for accumulation time periods equal to the data bit time period. The unsigned values are then processed according to instructions in the multibit accumulator 34 for determining integrations INT1 through INTN (FIG. 3A). The data bit accumulator 30A includes a code time period accumulator 42, start time delayer 44, and staggered data bit period accumulators1-N 46. A time chart of the operation of the receiver 10 for N equals twenty with the data bit accumulator 30A is shown in FIG. 3A and described in the accompanying detailed description.
The code accumulated I and Q are delayed by one through N code accumulation time periods by the start time delayer 44 for providing one through N delayed I and Q code accumulations, respectively, to the one through N staggered accumulators1-N 46, respectively. In other words, the code accumulated I and Q is delayed by one code accumulation time period and passed to the first staggered accumulator1 46, the code accumulated I and Q is delayed by two code accumulation time periods and passed to the second staggered accumulator2 46, and so on until the code accumulated I and Q is delayed by N code accumulation time periods and passed to the Nth staggered accumulatorN 46. In a first embodiment the code accumulation time period is one code time period (N=20 for C/A GPS); in a second embodiment the code accumulation time period is two code time periods (N=10 for C/A GPS); and so on.
The staggered accumulators1-N 46 accumulate the one through N delayed I and Q code accumulations for a data bit time period for determining one through N I and Q data bit accumulations, respectively. Continuing the numerical example above for N=20, each of the one through 20 I data bit accumulations includes 20 times 2500=50,000 I correlations and each of the one through 20 Q data bit accumulations includes 20 times 2500=50,000 Q correlations. Then, the one through N staggered accumulators1-N 46 ignore the sign (take absolute values) of the one through N I and Q data bit accumulations for providing one through N sets of |I| and |Q| unsigned accumulation values, respectively. The one through N sets of |I| and |Q| unsigned accumulation values are processed by the multibit accumulator 34 for determining INT1 to INTN, respectively.
FIG. 2B is a block diagram of an embodiment of the data bit accumulator 30 of the present invention referred to with a reference identifier 30B for providing absolute values (unsigned values) of I and Q correlations for accumulation time periods equal to the data bit time period. The unsigned values are then processed according to instructions in the multibit accumulator 34 for determining integrations INT1 through INTN (FIG. 3B). The data bit accumulator 30B includes the code time period accumulator 42, a sign inverter 54, and inverting data bit period accumulators1-N 56. A time chart of the operation of the receiver 10 for N equals twenty with the data bit accumulator 30B is shown in FIG. 3B and described in the accompanying detailed description. The code time period accumulator 42 operates as described above in the description accompanying FIG. 2A.
The sign inverter 54 provides one through N sign invert signals at one through N code accumulation time periods, respectively, after a start time. The one through N sign invert signals are received by the one through N inverting accumulators1-N 56, respectively. In other words, the first sign invert signal is passed to the first inverting accumulator1 56 at a delay of one code accumulation time period from the start time, the second sign invert signal is passed to the second inverting accumulator2 56 at a delay of two code accumulation time periods from the start time, and so on until the Nth sign invert signal is passed to the Nth inverting accumulatorN 56 at a delay of N code accumulation time periods from the start time. Because the data bit period actually is N code accumulation time periods, the Nth signal invert signal is not required.
The one through N inverting accumulators1-N 56 accumulate the one through N code accumulated I and Q, respectively, in a positive way before receiving the sign invert signal and in a negative way after receiving the signal invert signal for a data bit time period for measuring the one through N I and Q data bit accumulations, respectively. In other words the first inverting accumulator1 56 adds positive code accumulated I and Q before receiving the first data invert signal to negative code accumulated I and Q after receiving the first data invert signal; the second inverting accumulator2 56 adds positive code accumulated I and Q before receiving the second data invert signal to negative code accumulated I and Q after receiving the first data invert signal; and the Nth inverting accumulatorN 56 adds all positive code accumulated I and Q.
Then, the inverting accumulators1-N 56 ignore the sign (take absolute values) of the one through N I and Q data bit accumulations for providing one through N sets of |I| and |Q| unsigned accumulation values, respectively. The one through N sets of |I| and |Q| unsigned accumulation values are processed by the multibit accumulator 34 for determining INT1 to INTN, respectively.
For processing multiple data bit time periods the multibit accumulator 34 preferably combines the first through Nth unsigned accumulation values for all of the data bit periods for providing first through Nth multibit unsigned accumulation values, respectively. In other words, the first |I| unsigned accumulation values for all of the data bit time periods are accumulated or summed to determine the first |I| multibit unsigned accumulation value, the second |I| multibit unsigned accumulation values for all of the data bit time periods are accumulated or summed to determine the second |I| multiple unsigned accumulation value, and so on through the Nth |I| unsigned accumulation values. Similarly, the first |Q| unsigned accumulation values for all of the data bit time periods are accumulated or summed to determine the first |Q| multibit unsigned accumulation value, the second |Q| multibit unsigned accumulation values for all of the data bit time periods are accumulated or summed to determine the second |Q| multibit unsigned accumulation value, and so on through the Nth |Q| unsigned accumulation values.
For K data bit time periods, all K first |I1| unsigned accumulation values are summed for forming a summed first |I1| unsigned accumulation value denoted as Σ1-K|I1|, and all K first |Q1| unsigned accumulation values are summed for forming a summed first |Q1| unsigned accumulation value denoted as Σ1-K|Q1|, and so on until all K Nth |IN| unsigned accumulation values are summed for forming a summed Nth |IN| unsigned accumulation value denoted as Σ1-K|IN|; and all K Nth |QN| unsigned accumulation values are summed for forming a summed Nth |QN| unsigned accumulation value denoted as Σ1-K|QN|. The one through N integrations INT1 through INTN are [(Σ1-K|I1|)2+(Σ1-K|Q1|)2] through [(Σ1-K|IN|)2+(Σ1-K|QN|)2], respectively. Although the one through N integrations INT1 to INTN are preferred as squared functions as described above, alternative embodiments for the first through Nth integrations INT1 through INTN can be squared functions [Σ1-K(|I1|+|Q1|)2] through [Σ1-K(|IN|+|QN|)2]; linear functions of |I| and |Q| such as [Σ1-K(|I1|+|Q1|)] through [Σ1-K(|IN|+|QN|)], or [Σ1-K|I1|+Σ1-K|Q1|] through [Σ1-K|IN|+Σ1-K|QN|], or [Σ1-K|I1+Q1|] through [Σ1-K|IN+QN|]; and square roots of the sum of the squared functions [((Σ1-K|I1|)2+(Σ1-K|Q1|)2)+(�)] through [((Σ1-K|IN|)2+(Σ1-K|QN|)2)+(�)].
FIG. 3A is a time line showing the operation of the receiver 10 using the correlation machine 20 having the data bit accumulator 30A. The incoming signal may or may not have data bit transitions separating data bit time periods depending upon whether the polarity of the data bit changes. The repetitive data bit time period can be segmented into N repetitive code accumulation time periods. For the C/A GPS and N equals 20, the data bit accumulator 30A accumulates in data bit time periods having 20 staggered start times START1 through START20 and the first start time START1 is delayed by one code time period from t=0 start time and each start time START2 through START20 after that is progressively delayed by one or more code time period.
The relative strengths of the integrations INT1 to INT20 show the relative alignments corresponding to the START1 to START20, respectively. For example for the START1 two units of positive polarity combine with 18 units of negative polarity for the integrations INT1 equal to |−16| or 16 units. For the START20 three units of negative polarity combine with 17 units of positive polarity for the integrations INT20 equal to 14 units. The integration INT3 associated with the START3 is the strongest at |−20| or 20 units, thereby indicating that the START3 is aligned with the data bit transition.
For only one or a small number of data bit periods a test is made in the step 106 to verify the strongest integration INTS is a result of signal. Preferably, the general shape of a graph of the amplitudes of the first through Nth integrations INT1 to INTN is reviewed to see that the integrations before and after the strongest integration INTS show a pattern increasing to the strongest integration INTS. For example, the strongest integration INTS should be larger than the integrations further before and after the strongest integration INTS, (INTS−1>INTS−2 and INTS+1>INTS+2), where the integration INTS−1 starts one code time period before and the integration INTS−2 starts two code time periods before the integration INTS; and the integration INTS+1 starts one code time period after and the integration INTS+2 starts two code time periods after the integration INTS.
FIG. 4B is a flow chart of the operation of the receiver 10 using the correlation machine 20 having the data bit accumulator 30B. In a step 100, the receiver 10 determines the Doppler modified frequency and PRN code phase for a GPS signal source. Most commonly the GPS signal source is a GPS satellite, however, the GPS signal source can also be a GPS pseudolite. Then, in steps 132 1 to 132 N the receiver 10 determines first through Nth integrations INT1 to INTN, respectively, as illustrated in FIGS. 2B and 3B described above in the accompanying detailed descriptions.
Returning to FIG. 4B, in a step 136 the strongest integration INTS is tested to determine that it is a result of signal and not noise. This step is normally not required when the number of data bit time periods in a multibit accumulation is much greater than the number of consecutive ones or zeros allowable for the incoming signal. For only one or a small number of data bit periods a test is made in the step 136 to verify the strongest integration INTS is a result of signal. Preferably, the general shape of a graph of the amplitudes of the first through Nth integrations INT1 to INTN is reviewed to see that the integrations before and after the strongest integration INTS show a pattern increasing to the strongest integration INTS. For example, the strongest integration INTS should be larger than the integrations further before and after the strongest integration INTS, (INTS−1>INTS−2 and INTS+1>INTS+2), where the integration INTS−1 starts one code time period before and the integration INTS−2 starts two code time periods before the integration INTS; and the integration INTS+1 starts one code time period after and the integration INTS+2 starts two code time periods after the integration INTS.
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