Source: https://patents.google.com/patent/JP2008311599A/en
Timestamp: 2019-12-12 00:31:25
Document Index: 377987365

Matched Legal Cases: ['art 440', 'art 440', 'art 440', 'art 440', 'art 540', 'art 450']

JP2008311599A - Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package - Google Patents
JP2008311599A
JP2008311599A JP2007182624A JP2007182624A JP2008311599A JP 2008311599 A JP2008311599 A JP 2008311599A JP 2007182624 A JP2007182624 A JP 2007182624A JP 2007182624 A JP2007182624 A JP 2007182624A JP 2008311599 A JP2008311599 A JP 2008311599A
JP2007182624A
鍾 薫 金
2007-07-11 Application filed by Hynix Semiconductor Inc, 株式会社ハイニックスセミコンダクターＨｙｎｉｘ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｉｎｃ． filed Critical Hynix Semiconductor Inc
2008-12-25 Publication of JP2008311599A publication Critical patent/JP2008311599A/en
<P>PROBLEM TO BE SOLVED: To provide a molded reconfigured wafer, capable of simplifying a manufacturing process and decreasing a manufacturing cost, and a stack package using the wafer, and a method for manufacturing the stack package. <P>SOLUTION: The stack package includes at least two stack package units. Each package unit comprises semiconductor chips having bonding pads on upper surfaces thereof; a molding part formed to surround side surfaces of the semiconductor chips; through-electrodes formed in the molding part; and re-distribution lines formed to connect the through-electrodes and adjacent bonding pads with each other. <P>COPYRIGHT: (C)2009,JPO&INPIT
The present invention relates to a stack package, and more particularly to a mold reconfigurable wafer that has a simple manufacturing process and can reduce manufacturing costs, a stack package using the same, and a manufacturing method thereof.
Packaging technology for semiconductor integrated devices has been continuously developed in response to demands for miniaturization and high capacity, and recently, a variety of stack packages capable of satisfying miniaturization and high capacity and mounting efficiency. Technology has been developed.
In the semiconductor industry, “stack” is a technology in which at least two semiconductor chips or packages are stacked vertically, and in the case of a memory element, it has a memory capacity larger than the memory capacity that can be realized in the semiconductor integration process. The product can be embodied, and the efficiency of using the mounting area can be improved.
Stacked packages can be classified into a method of stacking individual semiconductor chips after they are stacked by a manufacturing technique, and a method of stacking and forming packaged individual semiconductor chips. . The stack packages are electrically connected through metal wires or through silicone vias.
FIG. 1 is a cross-sectional view illustrating a stack package using a conventional metal wire.
As shown in FIG. 1, in the stack package 100 using metal wires, at least two semiconductor chips 110 are stacked on a substrate 120 with an adhesive 114 as a medium, and the chips 110 and the substrate 120 are made of metal. It is electrically connected through the wire 116.
In FIG. 1, 112 is a bonding pad, 122 is a connection pad, 124 is a ball land, 126 is a circuit wiring, 170 is an external connection terminal, and 190 is a sealing agent. .
However, the conventional stack package using metal wires exchanges electrical signals through the metal wires, so the speed is low, and a large number of wires are used, and the electrical characteristics deteriorate in each chip. Will occur. Furthermore, an additional area is required for the substrate to form the metal wire, the size of the package increases, and a gap (Gap) for wire bonding is required for the bonding pad of each chip. The overall height of the package is increased.
Therefore, a stack package using a through silicon via (Through silicon via) to solve the problem of the stack package using a metal wire and to prevent the electrical characteristics of the stack package from being deteriorated and miniaturized. A structure was proposed.
FIG. 2 is a cross-sectional view showing a stack package using a conventional through silicone via.
As shown in FIG. 2, in the stack package 200 using the through silicone via, the semiconductor chip 210 having the through silicone via 230 formed on the substrate 220 is connected to the through silicone via 230 at the corresponding position. Will be stacked.
In FIG. 2, reference numeral 212, which has not been described, is a bonding pad, 222 is a connection pad, 224 is a ball land, 226 is a circuit wiring, and 270 is an external connection terminal.
The stack package using the penetrating silicone via is electrically connected through the penetrating silicone via, so that electrical deterioration is prevented and the operation speed of the semiconductor chip can be improved, and the size can be reduced. It is.
However, in the case of a stack package using conventional through silicone vias, a through silicone via that penetrates the inside of the chip must be formed, and a circuit cannot be formed in the through silicone via forming portion in the semiconductor chip. . Therefore, the manufacturing process is difficult, and a wafer on which a semiconductor chip is designed in consideration of the penetrating silicone via must be manufactured separately. Therefore, a wafer including a general-purpose semiconductor chip cannot be used, and the process cost increases.
The present invention provides a mold reconfigurable wafer that has a simple manufacturing process and can reduce manufacturing costs, a stack package using the same, and a manufacturing method thereof.
In one embodiment, the mold reconfigurable wafer is formed in a mold part formed so as to surround a side surface and a lower surface of a plurality of semiconductor chips each having a bonding pad on an upper surface, and a side mold part of each semiconductor chip. And a rewiring formed to interconnect the through electrode and a bonding pad adjacent thereto.
The through electrode is formed at a depth deeper than a lower surface of the semiconductor chip.
The through electrode and the rewiring are integrally formed.
In another embodiment, the stack package includes at least two package units stacked, and the package unit includes a semiconductor chip having a bonding pad on an upper surface and a mold formed to surround a side surface of the semiconductor chip. And a rewiring formed so as to interconnect the through electrode and a bonding pad adjacent to the through electrode.
The bottom surface of the through electrode protrudes from the bottom surface of the package unit.
The semiconductor chips provided in the stacked package units have different sizes.
Each package unit including the semiconductor chips having different sizes has the same size.
The circuit board further includes a substrate to which the stacked package units are attached, and an external connection terminal attached to the lower surface of the substrate.
It further includes a landfill material provided between the stacked package units and between the stacked lowermost package unit and the substrate.
The semiconductor device further includes a capping film formed on the top surface of the stacked uppermost package unit.
And a sealing unit formed between the stacked package units, between the stacked lowermost package unit and the substrate, and including an upper part of the stacked uppermost package unit so as to cover the upper surface of the substrate. .
The stacked package units are stacked on a substrate in a face-down type.
The semiconductor chip further includes a semiconductor chip that is stacked on the stacked uppermost package unit and does not include a through electrode and a rewiring.
The semiconductor chip that does not include the through electrode and the rewiring further includes a bonding pad that is formed and rewired to correspond to the through electrode of the stacked uppermost package unit.
In another embodiment, a method for manufacturing a stack package includes a mold reconfigurable wafer including a plurality of semiconductor chips each having a bonding pad on an upper surface, and a mold part formed so as to surround a side surface and a lower surface of the semiconductor chip. Forming a groove in a portion of the mold part adjacent to each of the bonding pads, forming a through electrode in the groove, and forming a rewiring that connects between the adjacent through electrode and the bonding pad. Removing the lower surface of the mold reconfigurable wafer so that the bottom surface of the through electrode is exposed and a plurality of package units are configured, and the mold reconfigurable wafer including the plurality of package units is the same. The stacking electrodes included in the package unit are connected to each other so that they The method comprising, a molded reconfigured wafer including a plurality of package units which are stacked in the wafer level and a step of sawing the chip level.
The groove is formed deeper than the lower surface of the semiconductor chip.
Forming the through electrode and the rewiring includes forming a metal seed film on an upper surface of the mold reconfigurable wafer including the groove, and forming a metal film so as to fill the groove on the metal seed film. And patterning the metal film and the metal seed film.
The method may further include etching back the metal film to reduce the thickness of the metal film after forming the metal film and before patterning the metal film and the metal seed film.
The lower surface of the mold reconstructed wafer is removed by at least one of a grinding process and an etching process so that the lower surface mold part of the mold reconstructed wafer is removed.
After stacking the mold reconfigurable wafer, the method further includes forming a landfill material and a capping film between the stacked mold reconfigurable wafers and on the stacked uppermost mold reconfigurable wafer, respectively.
The stacked package units are formed of semiconductor chips having different sizes.
After sawing the mold reconfigurable wafer to a chip level, the method further includes attaching a package unit having the through electrode formed thereon and stacked thereon.
The method further includes forming a landfill material between the stacked lowermost package unit attached on the substrate and the substrate.
After depositing the stacked package units on a substrate, the substrate is placed between the stacked package units, between the stacked bottom package unit and the substrate, and above the stacked top package unit. The method further includes forming a sealing portion so as to cover the upper surface.
After attaching the stacked package units on the substrate, the method further includes attaching external connection terminals to the lower surface of the substrate.
The present invention considers a through electrode to form a stack package by embodying a stack package using a mold reconfigurable wafer having a mold part surrounding the semiconductor chip and having a through electrode formed therein. A general-purpose semiconductor chip can be used without the need to separately manufacture a wafer on which a separate device design has been made, so that the process can be simplified and the manufacturing cost can be reduced.
In addition, the present invention can solve the defect problem of the whole stack package by one defective semiconductor chip by forming a stack package using a mold reconfigurable wafer that uses only good semiconductor chips. Rate loss can be minimized.
According to the present invention, a mold part is formed on a side surface and a lower part of a semiconductor chip on which a bonding pad is disposed, a through electrode is provided in the side surface mold part, and a rewiring for connecting the through electrode and the bonding pad is provided. A mold reconfigured wafer is manufactured, and a stack package is configured using the wafer.
Specifically, the present invention relates to a general non-defective semiconductor chip having bonding pads rearranged at regular intervals, a mold part formed so as to surround a side surface and a lower part of each semiconductor chip, and a side surface of the semiconductor chip. At least two mold reconfigurable wafers formed with through-electrodes formed in the mold part, and rewirings electrically connecting the bonding pads of the semiconductor chip and the through-electrodes of the mold part, After using and stacking, the stack package is formed by separating at the chip level.
Therefore, the present invention forms a stack package by stacking and forming a mold reconfigurable wafer having a through electrode formed in the mold portion so that the through electrodes provided in each wafer are electrically connected. Therefore, it is possible to use a general-purpose semiconductor chip without the need to manufacture a wafer in which a semiconductor chip is designed in consideration of the through electrode, thereby simplifying the process and reducing the manufacturing cost. be able to. In addition, the present invention can solve the defect problem of the entire stack package by one defective semiconductor chip by forming a stack package using a mold reconfigurable wafer that uses only good semiconductor chips, Yield loss can be minimized.
Hereinafter, a general mold reconfigurable wafer according to an embodiment of the present invention, a stack package using the mold reconfigurable wafer according to the present invention, and a manufacturing method thereof will be described in detail.
3A and 3B are drawings and photographs for explaining a general mold reconfigurable wafer, and FIG. 4 is a cross-sectional view for explaining a mold reconfigurable wafer according to an embodiment of the present invention.
Referring to FIGS. 3A and 3B, a general mold reconfigurable wafer 350a includes a plurality of non-defective semiconductor chips 310 disposed at required positions on a carrier 390 having a double-sided adhesive tape 392 attached to an upper surface thereof. After forming a mold part on the double-sided adhesive tape 392 so as to surround the chip 310, the carrier 390 and the double-sided adhesive tape 392 are removed and formed.
The mold reconstructed wafer is manufactured by a technique in which only a good semiconductor chip is separated from a wafer after the chip manufacturing process is completed and placed on a carrier, and then a new wafer is manufactured through a molding operation. "M. Brunnbauer et al.," An Embedded Device Technology Based on a Molded Reconfigured Wafer ", ECTC 2006, pp. 547 to 551", the manufacturing method is disclosed.
The present invention is configured such that a stack package can be realized by forming a through electrode and a rewiring on such a general mold reconfigurable wafer.
Referring to FIG. 4, a mold reconfigurable wafer according to the present invention includes a semiconductor chip 410 in a side mold portion 440 adjacent to a bonding pad 412 provided on each semiconductor chip 410 of a general mold reconfigurable wafer. A rewiring having a depth deeper than that of the lower surface of the substrate and having a depth not penetrating the mold portion 440 to electrically connect each bonding pad 412 to the adjacent through electrode 430. This is a structure in which 432 is formed.
The through electrode 430 and the rewiring 432 are preferably formed integrally and formed through metal film deposition using the metal seed film 434 and patterning thereof. The through electrode 430, the rewiring 432, and the metal seed film 434 may be any one of tin (Sn), nickel (Ni), copper (Cu), gold (Au), and aluminum (Al), or an alloy thereof. It is formed by comprising.
On the other hand, a stack package using the above-described mold reconstructed wafer according to the present invention is as follows.
FIG. 5 is a cross-sectional view illustrating a stack package according to a first embodiment of the present invention.
As shown in FIG. 5, the stack package 400 according to the present invention includes at least two package units 450 formed on a substrate 420 using a mold reconfigurable wafer 450 having a through electrode 430 and a rewiring 432. , Stacked and formed.
The package unit 450 includes a semiconductor chip 410 having bonding pads 412 arranged on both sides of the upper surface, a mold part 440 formed so as to surround a side surface of the semiconductor chip 410, and a mold part 440 adjacent to the bonding pad 412. And a rewiring 432 that electrically connects the bonding pad 412 and the through electrode 430 formed adjacent thereto.
The through electrode 430 protrudes from the lower surface of the package unit 450 to facilitate the formation of the stack package 400, and the stacked package units 450 are connected to the corresponding through electrodes 430.
In order to electrically connect the stacked package unit 450 to the outside, the stacked package unit 450 includes a plurality of connection pads 422 on the upper surface and a ball land 424 having external connection terminals 470 attached to the lower surface. Is mounted on a substrate 420 having circuit wiring 426 therein. At this time, the through electrode 430 of the stacked lowermost package unit 450 is electrically connected to the connection pad 422 of the substrate 420.
Between the stacked package units 450, between the lowermost package unit and the substrate 420 in the stacked package units, and on the uppermost package unit 450 stacked for insulation and chip protection. The first landfill material 460, the second landfill material 462, and the capping film 464 are formed.
As described above, when the stack package according to the present invention is formed by using the mold reconfigurable wafer in which the through electrode is formed in the mold portion, even when the stack package is formed at the wafer level, the defective chip can be used as a non-defective semiconductor chip. It is possible to prevent the situation where it cannot be performed, improve the yield, and also realize a stack package with a general-purpose semiconductor chip, simplifying the process and reducing the manufacturing cost. Can be made.
6A to 6F are cross-sectional views showing processes for explaining a method of manufacturing a stack package according to the first embodiment of the present invention.
Referring to FIG. 6A, a mold reconfigurable wafer 450a including a semiconductor chip 410 having a plurality of bonding pads 412 on the upper surface and including a mold part 440 formed to surround the side surface and the lower surface of the semiconductor chip 410 is prepared. . Thereafter, a groove having a depth deeper than that of the semiconductor chip 410 while not deeply penetrating the mold portion 440 in a portion of the side surface mold portion 440 adjacent to the bonding pads 412 of the mold reconfigurable wafer 450a. T is formed.
Referring to FIG. 6B, after forming a metal seed film 434 on the mold reconfigurable wafer 450a including the surface of the groove T, a plating process is performed on the mold reconfigurable wafer 450a to form the metal seed film 434 on the metal seed film 434. A metal film 432a is formed so that the inside of the trench T is buried. The metal seed film 434 and the metal film 432a are formed of any one of tin (Sn), nickel (Ni), copper (Cu), gold (Au), and aluminum (Al), or an alloy thereof. . The metal layer 432a may be etched to a certain thickness through an etch back process so that the overall height of the stack package is reduced.
Referring to FIG. 6C, the metal film formed on the mold reconfigurable wafer 450a is patterned to penetrate the mold reconfigurable wafer 450a adjacent to the through electrode 430 and the bonding pad 412 of each semiconductor chip 410. A rewiring 432 is formed so as to be electrically connected to the electrode 430. At this time, the metal film is etched by a wet etching process.
Referring to FIG. 6D, at least one of a grinding process and an etching process removes the lower part of the mold reconfigurable wafer, exposes the lower part of the through electrode 430 to the outside, and A mold reconfigurable wafer 450b including the package unit 450 is formed. The lower part of the mold reconfigurable wafer is preferably removed such that the lower part of the through electrode 430 protrudes from the mold part 440 of the mold reconfigurable wafer 450b for stable electrical connection when forming a stack package.
Referring to FIG. 6E, at least two mold reconfigurable wafers 450b including a plurality of package units 450 described above are connected to through electrodes 430 formed in the package units 450 of the mold reconfigurable wafers 450b. Stack like so. Thereafter, between the stacked mold reconfigurable wafers 450b and on the stacked uppermost mold reconfigurable wafer 450b, a first landfill 460 and a capping film 464 are provided for electrical insulation and protection of semiconductor chips, respectively. Form.
Referring to FIG. 6F, the mold reconstructed wafer 450b stacked at the wafer level is sawed at the chip level to obtain a structure in which the package unit 450 is stacked. Thereafter, the stacked package unit 450 is mounted on a substrate 420 having a plurality of connection pads 422 on the upper surface, a ball land 424 on the lower surface, and a circuit wiring 426 therein, and the ball land 424. The external connection terminal 470 is attached to the substrate. At this time, the through electrode 430 of the lowermost package unit 450 of the stacked package units 450 is attached to correspond to the connection pads 422 of the substrate 420. A second landfill 462 is provided between the stacked lowermost package unit 450 and the substrate 420 in order to improve the reliability of the joint portion.
FIG. 7 is a cross-sectional view illustrating a stack package according to a second embodiment of the present invention.
As shown in FIG. 7, the stack package 400 stacks the package unit 450 as shown in FIG. 5 described above, but is stacked instead of the first landfill material 460, the second landfill material 462, and the capping film 464. Sealing is performed so as to cover the upper surface of the substrate 420 including at least two or more package units 450, between the stacked lowermost package unit 450 and the substrate 420, and an upper portion of the stacked uppermost package unit 450. A stop 480 is formed.
In the stack package, the package units 450 are stacked in the same manner as before the first landfill 460 and the capping film 464 of FIGS. 6A to 6E are formed, and the package units 450 stacked on the substrate 420 are stacked. In order to improve electrical insulation and reliability of the joint portion, the stacked package units 450, the top package unit 450 and the bottom package unit 450 and the substrate 420 are stacked. In this process, a sealing portion 480 is formed so as to cover the upper surface of the substrate.
On the other hand, as shown in FIG. 8, a stack package 500 according to the present invention can be configured by stacking package units 550 having semiconductor chips 510 having different sizes. The package unit 550 is formed to have the same size, that is, when the size of the semiconductor chip 510 constituting the package unit 550 is relatively small, the side mold part 540 is formed large, The stacked package units 550 have the same size.
The rewiring 532 connecting the bonding pad 512 and the through electrode 530 provided in each package unit 550 is formed with an equal length. This is because, even if the package unit 550 is formed with the semiconductor chip 510 having a different size, the rewiring 532 is easily formed in the patterning process using the same mask pattern, and the rewiring 532 has the longest length. The semiconductor chip 510 having a small size is used as a reference.
The remaining configuration excluding the rewiring 532 and the semiconductor chip 510 of the stack package 500 is the same as that in FIG. 5 described above, and the manufacturing method is the same as that in FIGS. 6A to 6F described above.
Further, as shown in FIG. 9, a stack package 600 according to the present invention has a package unit 650 having the same configuration as that of FIG. 5 described above stacked on a substrate 620. The package units 650 may be stacked in a face-down manner so that the wiring 632 adheres to the substrate 620, that is, the upper surface of the package unit 650 faces the substrate 620. Further, the through electrode 630 and the rewiring 632 are not formed on the stacked uppermost package unit 650, and the bonding pads 612 a redistributed at positions corresponding to the through electrodes 630 of the uppermost package unit 650 are provided. A semiconductor chip 610a having a general structure is disposed.
The configuration of the package unit 650 constituting the stack package 600 is the same as that of FIG. 5 described above, and the manufacturing method of the package unit 650 is the same as that of FIGS. 6A to 6F described above.
Further, although not shown in the drawings, the present invention stacks the package units so as to have the same structure as the above-described stacked package, but does not use a substrate for electrical connection with the outside, and stacks the lowermost package units. After forming a rearrangement layer on the lower surface of the stack, a stack package can be formed by a method of attaching external connection terminals to the rearrangement layer.
Although the present invention has been illustrated and described herein with reference to specific embodiments, the present invention is not limited thereto but is within the limits of the spirit and field of the invention as defined in the claims. Those having ordinary skill in the art can easily understand that the invention can be variously modified and modified.
It is sectional drawing which shows the stack package using the conventional metal wire. It is sectional drawing which shows the stack package using the conventional penetration silicone via. It is drawing for demonstrating a general mold reconstruction wafer. It is a photograph for explaining a general mold reconstruction wafer. It is sectional drawing for demonstrating the mold reconstruction wafer by the Example of this invention. 1 is a cross-sectional view illustrating a stack package according to a first embodiment of the present invention. It is sectional drawing in the initial stage explaining the manufacturing method of the stack package by 1st Example of this invention. It is sectional drawing in the process following FIG. 6A explaining the manufacturing method of the stack package by 1st Example of this invention. FIG. 6B is a cross-sectional view in the process following FIG. 6B, which illustrates the stack package manufacturing method according to the first example of the present invention. FIG. 6D is a cross-sectional view illustrating a method for manufacturing the stack package according to the first embodiment of the invention, following the step of FIG. 6C. FIG. 6D is a cross-sectional view illustrating a method for manufacturing the stack package according to the first embodiment of the invention, following the step shown in FIG. 6D. FIG. 6D is a cross-sectional view in the step following FIG. 6E, which illustrates the stack package manufacturing method according to the first example of the present invention. FIG. 6 is a cross-sectional view illustrating a stack package according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a stack package according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a stack package according to a fourth embodiment of the present invention.
400 Stack Package 410 Semiconductor Chip 412 Bonding Pad 420 Substrate 422 Connection Pad 424 Ball Land 426 Circuit Wiring 430 Through Electrode 432 Rewiring 434 Metal Seed Film 440 Mold Part 450 Package Unit 460 First Landing Material 462 Second Landing Material 464 Capping Film 470 External connection terminal 480 Sealing part
A mold part formed so as to surround a side surface and a lower surface of a plurality of semiconductor chips each having a bonding pad on the upper surface;
A through electrode formed in a side mold part of each semiconductor chip;
A mold reconfigurable wafer comprising: a rewiring formed to interconnect the through electrode and a bonding pad adjacent thereto.
The mold reconfigurable wafer according to claim 1, wherein the through electrode is formed at a depth deeper than a lower surface of the semiconductor chip.
The mold reconfigurable wafer according to claim 1, wherein the through electrode and the rewiring are integrally formed.
In a stacked package in which at least two package units are stacked,
The package unit is
A semiconductor chip having a bonding pad on the upper surface;
A mold part formed so as to surround a side surface of the semiconductor chip;
A through electrode formed in the mold part;
A stack package comprising: a rewiring formed to interconnect the through electrode and a bonding pad adjacent thereto.
The stack package according to claim 4, wherein a lower surface of the through electrode protrudes from a lower surface of the package unit.
The stack package according to claim 4, wherein the through electrode and the rewiring are integrally formed.
The stack package according to claim 4, wherein the semiconductor chips included in the stacked package units have different sizes.
8. The stack package according to claim 7, wherein the package units including the semiconductor chips having different sizes have the same size.
The stack package according to claim 4, further comprising a substrate to which the stacked package unit is attached, and an external connection terminal attached to a lower surface of the substrate.
The stack package according to claim 9, further comprising a landfill material provided between the stacked package units and between the stacked lowermost package unit and the substrate.
The stack package according to claim 9, further comprising a capping film formed on an upper surface of the stacked uppermost package unit.
And a sealing unit formed between the stacked package units, between the stacked lowermost package unit and the substrate, and including an upper part of the stacked uppermost package unit so as to cover the upper surface of the substrate. The stack package according to claim 9.
The stack package according to claim 9, wherein the stacked package units are stacked on a substrate of a face-down type.
14. The stack package according to claim 13, further comprising a through-hole electrode stacked on the stacked uppermost package unit and a semiconductor chip having no rewiring.
15. The semiconductor chip having no through electrode and rewiring further includes a bonding pad formed and rewired to correspond to the through electrode of the stacked uppermost package unit. Stack package.
A plurality of semiconductor chips each having a bonding pad on the upper surface, and a mold portion adjacent to each bonding pad of the mold reconfigurable wafer, each including a mold portion formed so as to surround the side surface and the lower surface of the semiconductor chip. Forming a groove;
Forming a through electrode in the groove, and forming a rewiring that connects between the adjacent through electrode and the bonding pad;
Removing the bottom surface of the mold reconfigurable wafer so that the bottom surface of the through electrode is exposed and a plurality of package units are configured;
Stacking the mold reconfigurable wafer including the plurality of package units such that the through electrodes included in the same package unit are connected to each other;
Sawing a mold reconstructed wafer including a plurality of package units stacked at the wafer level to a chip level.
17. The method of manufacturing a stack package according to claim 16, wherein the groove is formed at a depth deeper than a lower surface of the semiconductor chip.
The step of forming the through electrode and the rewiring includes:
Forming a metal seed film on the upper surface of the mold reconfigurable wafer including the groove;
Forming a metal film so as to fill a groove on the metal seed film;
Patterning the metal film and the metal seed film;
The manufacturing method of the stack package of Claim 16 characterized by the above-mentioned.
Etching back the metal film to reduce the thickness of the metal film after forming the metal film and before patterning the metal film and the metal seed film. The method for manufacturing a stack package according to claim 16.
17. The lower surface of the mold reconfigurable wafer is removed by at least one of a grinding process and an etching process so that the lower surface mold portion of the mold reconfigured wafer is removed. The manufacturing method of the stack package as described in 2.
After stacking the mold reconfigurable wafer, the method further includes forming a landfill material and a capping film between the stacked mold reconfigurable wafers and on the stacked uppermost mold reconfigurable wafer, respectively. The method for manufacturing a stack package according to claim 16.
17. The method of manufacturing a stacked package according to claim 16, wherein the stacked package units are formed of semiconductor chips having different sizes.
The method of claim 16, further comprising the step of: depositing a package unit on which the through electrodes are formed and stacked after the step of sawing the mold reconfigurable wafer at a chip level. Method.
24. The method of claim 23, further comprising forming a landfill material between the lowermost package unit attached and stacked on the substrate and the substrate.
After depositing the stacked package units on a substrate, the top surface of the substrate is placed between the stacked package units, between the stacked bottom package unit and the substrate, and above the stacked top package unit. The method for manufacturing a stack package according to claim 23, further comprising: forming a sealing portion so as to cover the substrate.
The method of claim 23, further comprising attaching an external connection terminal to a lower surface of the substrate after attaching the stacked package unit on the substrate.
JP2007182624A 2007-06-18 2007-07-11 Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package Pending JP2008311599A (en)
JP2008311599A true JP2008311599A (en) 2008-12-25
JP2007182624A Pending JP2008311599A (en) 2007-06-18 2007-07-11 Molded reconfigured wafer, stack package using the same, and method for manufacturing the stack package
JP2012211732A Pending JP2012253392A (en) 2007-06-18 2012-09-26 Stack package manufactured using molded reconfigured wafer, and method for manufacturing the same
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2012-02-28 RD01 Notification of change of attorney