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Matched Legal Cases: ['Application No. 07018026', 'Application No. 05731252', 'Application No. 2005246697', 'Application No. 04', 'Application No. 200480032782', 'Application No. 200580015278', 'Application No. 07018026', 'Application No. 200580014868', 'Application No. 2003', 'Application No. 2003', 'Application No. 05756258', 'Application No. 2006', 'Application No. 200580015278', 'Application No. 200480032782', 'Application No. 200580014866', 'Application No. 200580015278']

Patent US7915644 - Wide bandgap HEMTs with source connected field plates - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA HEMT comprising an active region comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the active region. A spacer layer is formed on at least a portion of a surface of said active region and covering...http://www.google.com/patents/US7915644?utm_source=gb-gplus-sharePatent US7915644 - Wide bandgap HEMTs with source connected field platesAdvanced Patent SearchPublication numberUS7915644 B2Publication typeGrantApplication numberUS 12/437,505Publication dateMar 29, 2011Filing dateMay 7, 2009Priority dateMay 11, 2004Also published asCA2566756A1, CN1954440A, CN100580954C, EP1751803A2, EP2270870A1, EP2270871A1, US7550783, US8592867, US20060006415, US20090236635, US20110169054, WO2005114744A2, WO2005114744A3Publication number12437505, 437505, US 7915644 B2, US 7915644B2, US-B2-7915644, US7915644 B2, US7915644B2InventorsYifeng Wu, Primit Parikh, Umesh Mishra, Marcia MooreOriginal AssigneeCree, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (68), Non-Patent Citations (74), Referenced by (14), Classifications (21) External Links: USPTO, USPTO Assignment, EspacenetWide bandgap HEMTs with source connected field platesUS 7915644 B2Abstract A HEMT comprising an active region comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the active region. A spacer layer is formed on at least a portion of a surface of said active region and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.
RELATED APPLICATION DATA This application is a divisional of and claims the benefit of U.S. patent application Ser. No. 10/958,970 filed on Oct. 4, 2004 now U.S. Pat. No. 7,550,783, which claims the benefit of U.S. Provisional patent application Ser. No. 60/570,519 filed May 11, 2004.
STATEMENT AS TO FEDERALLY SPONSORED RESEARCH This invention was made with Government support under ONR/DARPA Government Contract No. N00014-02-0306. The Government has certain rights in this invention.
Improvements in the manufacturing of AlGaN/GaN semiconductor materials have helped advance the development of AlGaN/GaN transistors, such as high electron mobility transistors (HEMTs) for high frequency, high temperature and high power applications. AlGaN/GaN has large bandgaps, high peak and saturation electron velocity values [B. Gelmont, K. Kim and M. Shur, Monte Carlo Simulation of Electron Transport in Gallium Nitride, J. Appl. Phys. 74, (1993), pp. 1818-1821]. AlGaN/GaN HEMTs can also have 2 DEG sheet densities in excess of 1013cm−2 and relatively high electron mobility (up to 2019 cm2/Vs) [R. Gaska, et al., Electron Transport in AlGaN�GaN Heterostructures Grown on 6H�SiC Substrates, Appl. Phys. Lett. 72, (1998), pp. 707-709]. These characteristics allow AlGaN/GaN HEMTs to provide very high voltage and high power operation at RF, microwave and millimeter wave frequencies.
SUMMARY OF THE INVENTION The present invention provides transistors with a field plate connected to the source electrode, with typical transistors utilizing the invention being HEMTs. One embodiment of a HEMT according to the present invention comprises a plurality of active semiconductor layers formed on a substrate with a two dimensional electron gas (2 DEG) at the heterointerface between two of said plurality of active layers. Source and drain electrodes are formed in contact with the 2 DEG and a gate is formed between the source and drain electrodes and on the plurality of active layers. A spacer layer is formed on at least part of the surface of the plurality of active layers between the gate and the drain electrode. A field plate is formed on the spacer layer with at least one conductive path electrically connecting the field plate to the source electrode, the at least one conductive path covering less than all of the topmost surface between gate and source electrode.
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New York, US, vol. 9, Sep. 2000, p. 373-375, XP000954354, ISSN: 0741-3106.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS7999287 *Oct 26, 2009Aug 16, 2011Infineon Technologies Austria AgLateral HEMT and method for the production of a lateral HEMTUS8237198Jan 18, 2011Aug 7, 2012Transphorm Inc.Semiconductor heterostructure diodesUS8289065Sep 9, 2009Oct 16, 2012Transphorm Inc.Inductive load power switching circuitsUS8389977Dec 10, 2009Mar 5, 2013Transphorm Inc.Reverse side engineered III-nitride devicesUS8390000Aug 28, 2009Mar 5, 2013Transphorm Inc.Semiconductor devices with field platesUS8493129Sep 14, 2012Jul 23, 2013Transphorm Inc.Inductive load power switching circuitsUS8519438Apr 23, 2008Aug 27, 2013Transphorm Inc.Enhancement mode III-N HEMTsUS8541818Jun 26, 2012Sep 24, 2013Transphorm Inc.Semiconductor heterostructure diodesUS8592867 *Mar 25, 2011Nov 26, 2013Cree, Inc.Wide bandgap HEMTS with source connected field platesUS8598937Oct 7, 2011Dec 3, 2013Transphorm Inc.High power semiconductor electronic components with increased reliabilityUS8643062Feb 2, 2011Feb 4, 2014Transphorm Inc.III-N device structures and methodsUS20110169054 *Mar 25, 2011Jul 14, 2011Cree, Inc.Wide bandgap hemts with source connected field platesUS20130228788 *Feb 26, 2013Sep 5, 2013Kabushiki Kaisha ToshibaSemiconductor deviceUS20130228789 *Feb 26, 2013Sep 5, 2013Kabushiki Kaisha ToshibaSemiconductor device* Cited by examinerClassifications U.S. Classification257/194, 257/E29.017, 438/454, 257/E29.246, 257/E29.009, 438/140, 257/E21.407, 438/172, 257/E21.403, 257/488International ClassificationH01L29/20, H01L29/778, H01L29/40, H01L29/02, H01L29/66, H01L29/06Cooperative ClassificationH01L29/402, H01L29/7787, H01L29/2003European ClassificationH01L29/778E2, H01L29/40PRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google