Source: http://www.google.de/patents/US8135999
Timestamp: 2013-05-22 10:53:01
Document Index: 275720506

Matched Legal Cases: ['Application No. 4319', 'Application No. 200480015427', 'Application No. 4', 'Application No. 4', 'Application No. 2006', 'Application No. 2006', 'Application No. 200480015427']

Patent US8135999 - Disabling outbound drivers for a last memory buffer on a memory channel - Google PatenteSuche Bilder Maps Play YouTube News Gmail Drive Mehr » Erweiterte Patentsuche | Webprotokoll | Anmelden Erweiterte Patentsuche PatenteMemory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device...http://www.google.de/patents/US8135999?utm_source=gb-gplus-sharePatent US8135999 - Disabling outbound drivers for a last memory buffer on a memory channel Ver�ffentlichungsnummerUS8135999 B2PublikationstypErteilung Anmeldenummer12/977,395 Ver�ffentlichungsdatum13. M�rz 2012Eingetragen23. Dez. 2010 Priorit�tsdatum5. Juni 2003Auch ver�ffentlicht unterCN1799035ACN100511192CEP1629389A2US7386768US7761753US8020056US8286039US20040250181US20090013211US20100281315US20110131370US20120102256US20120331356WO2004109526A2WO2004109526A3 ErfinderDennis BrzezinskiWarren MorrowPete VogtUrspr�nglich Bevollm�chtigterIntel Corporation US-Klassifikation714/716710/200714/4.5714/54711/100714/6.1714/4.2711/5719/328714/710711/115710/100365/51711/152714/4.3714/718714/6.21711/170Internationale KlassifikationG01R31/28G06F13/16 UnternehmensklassifikationG06F13/4256G06F13/4243 Europ�ische KlassifikationG06F13/42C3SG06F13/42D4ReferenzenPatentzitate (73)Nichtpatentzitate (27) Referenziert von (2)Externe LinksUSPTO USPTO-Zuordnung EspacenetDisabling outbound drivers for a last memory buffer on a memory channelUS 8135999 B2 Zusammenfassung Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
1. A first memory module device, comprising:
a first memory buffer to detect whether the first memory buffer device is a last memory buffer device on a memory channel, wherein the memory channel couples a host to one or more memory buffer devices including the first memory buffer device;
the first memory buffer to disable at least one outbound buffer driver in the first memory buffer device in response to detecting the first memory buffer device is the last memory buffer device on the memory channel;
the first memory buffer to receive an outbound frame from the memory channel; and
the at least one outbound buffer driver configurable to drive the outbound frame to a second memory buffer device of the one or more memory buffer devices on the memory channel in response to receiving the outbound frame and the first memory buffer device not being the last memory buffer device on the memory channel.
FIG. 2 illustrates a prior art RamLink slave interface circuit. In the circuit of FIG. 2, source-synchronous strobing is use to clock the incoming data signals. That is, a strobe signal, which accompanies the incoming data signals, is used to sample the incoming data.
The circuit of FIG. 2 uses a phase-locked loop (PLL) to generate a stable local clock signal from a reference clock signal that is distributed to other slave interface circuits. The local clock signal is used to reclock the outgoing data signal so as to avoid cumulative jitter as the data is passed along downstream.
The memory interface is not limited to any particular arrangement, and it may be compatible with standard memory devices, particularly commodity memory devices such as DDR2 DRAM. The entire memory buffer may be integrated on a single integrated circuit, it may be integrated into one or more memory devices, its constituent elements may be integrated. onto separate components, or any other mechanical arrangement may be employed. The embodiment shown in FIG. 7 is exemplary only, and other embodiments are possible in accordance with the inventive principles of this patent. For example, the embodiment of FIG. 7 is shown with unidirectional data flowing from the outbound redrive circuit to the memory interface and from the memory interface to the inbound redrive circuit. This data flow, however, may be bi-directional, and other arrangements are contemplated. Even if the embodiment of FIG. 7 is to be used in a charnel system in which data for the memory interface only needs to flow as shown in FIG. 7, it may still be realized with redrive circuits having full bi-directional data access as this may facilitate, for example, implementation of built-in self-test (BIST) functions, in which case a second deskew circuit for deskewing data from the inbound path may be helpful.
FIG. 10 illustrates another embodiment of an I/O cell according to the inventive principles of this patent. In the embodiment of FIG. 10, the sampling clock generator 88 is implemented with an interpolator 90 mid a receiver tracking unit (RTU) 92. The interpolator generates the sampling clock signal by interpolating between a number of phase clock signals PCX (in this case four signals that are 90 degrees out of phase) in response to a tracking signal from the receiver tracking unit. The receiver tracking unit observes the data signal RX and adjusts the tracking signal so that the sampling clock signal causes the receiver to sample and redrive the data signal at an appropriate time. Thus, the sampling clock signal may dynamically track the data signal.
FIG. 12 illustrates another embodiment of an I/0 cell according to the inventive principles of this patent. In the embodiment of FIG. 12, the received and transmitted data signals RX and TX are differential signals and are shown traversing the edge of an integrated circuit die on which the I/O cell may be fabricated. The receiver 86 includes a sampling unit 96 and a termination unit 98. The sampling unit samples the incoming data signal in response to a sampling clock signal SC which is generated by interpolator 90 in response to phase clock signals from a the sampling clock generator. The termination unit provides differential termination and converts the differential data signal into a single-ended signal. A jitter avoidance or drift compensation buffer 94 clocks data in response to either the sampling clock signal SC or a stable transmit clock signal TC. A multiplexer 100 selectively couples data sisals from either the buffer 94 or a serializer 102 to a transmit latch 104. Read data signals RDX[0 . . . n] are received at the I/O cell at serializer 102. Another multiplexer may be disposed between buffer 94 and transmit latch 104 with one input connected to the buffer and another input connected to an output of the interpolator.
During a normal mode of operation, each of the switches directs the signal from its first input to its output as shown in FIG. 14 so that write data signals WD0, WD1, WD2, WD3, WD4, and WD5 are directed to outputs OUT0, OUT1, 0UT2, OUT3, OUT4, and OUT5, respectively. In such an embodiment, one of the bit lanes, for example, the bit lane corresponding to WD5, may be used for error checking the data on the other bit lanes.
If a bad bit lane is detected, the multiplexer may operate in a fail-over mode in which one or more of the switches are manipulated to map out the bad bit lane. For example, if the bit lane associated with WD3 does not operate properly, the multiplexer switches may redirect write data signals WD4 and WD5 to outputs OUT3 and OUT4, respectively as shown in FIG. 15. In this mode, one bit lane worth of signal capacity is lost. If one of the bit lanes had been desipated for error checking, signals originally intended for the bad bit lane may be rerouted over the error checking lane, and the error checking function may be disabled.
The outputs of the fail-over circuit may be coupled to a memory interface, to a tummy device, or to other circuitry. In the embodiment of FIG. 13, the fail-over circuit is shown separate from the redrive circuit, but it may also be integrated into the redrive circuit. A fail-over circuit according to the inventive principles of this patent may be realized with simple multiplexers as shown, but other arrangements such as a full crossbar switch are also possible.
The exemplary system includes an embodiment of a host having fail-over capabilities such as those described with reference to FIG. 17 and embodiments of one or more memory modules having buffers with fail-over capabilities such as those described with reference to FIG. 16. Iii this example, the host and modules are arranged in a channel configuration having outbound and inbound paths such as that shown in FIG. 7, although the system may only include one module.
Failed bit lanes are reported by sending results to the host through the SMBus and/or by transmitting a results frame over the charnel to the host. Such a results frame may be initiated on the inbound path by the outermost module, and the other modules, if any. may merge their results information into the data in the inbound path. If the results from each module are transmitted redundantly on more than one bit lane, a failed bit lane is unlikely to interfere with reporting the results.
Some of the inventive principles of this patent relate to permuting status patterns. In memory systems such as those described above with reference to FIGS. 1 and 3 where memory, read and write data is transferred between memory agents, it may also be useful to send status information such as idle patterns, alert patterns, and other status information between memory agents. This may be accomplished by sending data patterns and status patterns on the same link or links that connect the memory agents. According to the inventive principles of this patent, the status patterns may be permuted over time.
According to the inventive principles of this patent, the memory controller and one or more modules may both be capable of permuting the idle pattern in a predictable manner so that the idle pattern changes over time. For example, the memory controller and modules may change the idle pattern according to a predetermined sequence each time an idle frame is sent and/or received. An embodiment of such a method according to the inventive principles of this patent is illustrated in FIG. 18. Thus, if the memory controller sends a read command frame (158) and receives a response frame (160) having the current idle pattern (162), it may resend the same read command (164). If the second response frame (166) contains the same pattern as the first (168) , it interprets the pattern as actual read data (170). If, however, the pattern in the second response frame matches the permuted idle pattern (168), the memory controller knows that the first response frame was an idle frame (172).
Although the principles of status pattern permuting and handling according to the inventive principles of this patent are applicable to any type of memory agent, and are independent of other inventive principles of this patent, some additional aspects will be described with respect to a memory buffer such as the embodiment shown in FIG. 7 and in the context of a system such as the embodiment shown in FIG. 6. Referring to FIG. 6, if the memory buffer 64 is the outermost agent on a memory channel, it may be capable of constantly transmitting permuting, idle status frames on the inbound link 56B whenever it is not sending data that the host has requested from any memory devices attached to the memory interface 68.
FIG. 19 illustrates an embodiment of a permuting pattern generator in accordance with the inventive principles of this patent. The embodiment of FIG. 19 is a 12-bit linear-feedback shift register (LFSR) with a polynomial of x12+x7+x4+x3 1. The initial state may be set to 000000000001, and the LFSR cycles through 2121 states (4095 frames) before the pattern is repeated. Each bit of the LFSR may be mapped to a bit lane in a link on a data path, and each bit may be used for all of the transfers that occur on the corresponding bit lane during an entire frame. For example, in a system having a data path with 12 bit lanes in each link, the output from each stage of the LFSR may be mapped to one of the bit lanes. Additional lanes, for example, a 13th bit lane, may be accommodated by utilizing the value from the least significant bit of the LFSR delayed by one frame.
FIG. 20 illustrates an example of the first status pattern generated by the permuting pattern generator of FIG. 19. In this example, a frame is 12 transfers long. FIGS. 21-22 illustrate the second, third and forth status patterns, respectively. By using the same value on each bit lane dining an entire frame, electromagnetic interference (EMI or noise) may be reduced.
The 13 bit lane by 12 bit transfer frame illustrated here is by way of example, and the inventive principles of this patent are not limited to these details, nor to the specific embodiment of a permuting pattern generator described above. For example, a permuting pattern generator according to the inventive principles of this patent need not be implemented with dedicated logic circuitry-such as the LFSR described above. Alternatively it may be implemented with programmable logic, or as an algorithm in a processor or other programmable state machine that may be used to oversee and/or implement the logic in the memory interface or other functionality of a buffer or other memory agent that utilizes permuting status patterns.
If the inner agent detects the presence detect logic level on two of the three bit lanes, it blows that the outer agent is present and it may leave all or a portion of its outer port enabled. (In this example, the outer port includes the link interface for the outbound link 54B and the link interface for the inbound link 56A.) If the inner agent fails to detect the presence detect logic level on at least two of the three bit lanes, it may decide that an outer agent is not present and it may disable all or a portion of its outer port. The inner agent may be capable of reporting the presence or absence of an outer agent to another agent; for example to a memory controller in response to a status check command.
Some additional inventive principles according to this patent relate, to hot insertion and/or removal of components from a memory channel�that is, adding and/or removing components while the memory channel is operating. FIG. 24 illustrates an embodiment of a memory agent 134 according to the inventive principles of this patent. The embodiment of FIG. 24 may be a memory module, memory buffer, memory controller, etc. The agent includes a first port 136 and a second port 138. If the agent is assumed, for purposes of illustration only, to be a memory module such as one of modules 52 in the embodiment of FIG. 6, the first port may be designated as an inner port since it may be arranged to communicate with other agents on the memory channel that are located closer to the memory controller. Likewise, the second port may be designated as an outer port since it may be arranged to communicated with agents on the memory channel that are located further away from the memory controller. These designations are for purposes of illustration only, and the inventive principles are not limited to these details of the memory agent nor to the particulars of the memory channel shown in FIG. 6. These principles may also be applicable to other memory channel architectures such as the RamLink architecture shown in FIG. 1.
Some additional inventive principles which may facilitate hot add/removal in accordance with this patent application will be described in the context of an example embodiment of a memory system. The example embodiment will be described with reference to the memory agent of FIG. 24 in the context of a memory system such as the embodiment of FIG. 6. In this example embodiment, it will be assumed that the memory agent of FIG. 24 is used to embody one or more of the buffers in FIG. 6, which in nun are part of modules having memory devices. All of these details, however, are for purposes of explanation only, and the inventive principles are not limited to these details.
A hot removal sequence according to the inventive principles of this patent may begin when a user informs the system that a specific agent on a memory channel is to be removed. The system may remove a corresponding host address range from a system map. If the system uses mirroring, the system may remap the host address ranges to agent mirrors. The system may then copy or move data from the host address range to other locations if not already minored. The system may then poll until all outstanding transactions are completed. The system may then cause the host to send a command to the agent just inside of the agent to be removed that causes this agent to assume it is the outermost agent on the channel, thereby causing it to disable its outer port and assume the functions of the outermost agent during subsequent fast resets. (A full reset would override this command.) The system may then initiate a fast reset to shut down the selected agent and any channel interfaces for components attached to the selected agent. The system may then disconnect power to the selected agent and notify the user that the agent may be removed.
A hot replace sequence according to the inventive principles of this patent may begin when the hot remove sequence described above is completed. The user may add a new agent in place of the one removed and then inform the system firmware that the new agent has been added. The riming system may then prepare the host for the newly replaced component and supply power to the new component. System firmware may then cause the host to send a command to the previous outermost agent to let is know that it should no longer assume that it is the outermost agent. This may cause the previous outermost agent to enable its outer port in response to the next reset, and wait for a poll command. Firmware may then instruct the host to send a poll command to the previous outermost agent which may then perform a polling operation such as the one described above with reference to FIG. 25, thereby initialising the new agent. The previous outermost agent may then report the presence of a new outer agent. The host may then detect the presence of the new agent and issue a fast reset command to bring the new agent into operation and retime the entire channel. After the new agent is operational, the host may interrupt the system firmware to report that the new agent is operational. Alternatively, the host may wait for the system firmware to query the host to determine if the new agent is operational.
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