Source: https://patents.google.com/patent/US20090146940A1/en
Timestamp: 2020-03-29 20:25:41
Document Index: 57241215

Matched Legal Cases: ['art 36', 'art 134', 'art 134', 'art 136', 'art 136', 'art 136', 'art 136', 'art 140', 'art 142', 'art 136', 'art 144', 'art 140', 'art 142', 'art 334']

US20090146940A1 - Liquid crystal display device - Google Patents
US20090146940A1
US20090146940A1 US12/320,894 US32089409A US2009146940A1 US 20090146940 A1 US20090146940 A1 US 20090146940A1 US 32089409 A US32089409 A US 32089409A US 2009146940 A1 US2009146940 A1 US 2009146940A1
US12/320,894
US9305480B2 (en
2003-12-11 Priority to KR10-2003-0090301 priority
2004-04-28 Priority to KR10-2004-0029612 priority
2004-04-28 Priority to KR10-2004-0029611 priority
2004-10-15 Priority to US10/964,779 priority patent/US7495648B2/en
2009-02-06 Priority to US12/320,894 priority patent/US9305480B2/en
2009-02-06 Assigned to LG.PHILIPS LCD CO., LTD LTD. reassignment LG.PHILIPS LCD CO., LTD LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HONG, JIN CHEOL, KANG, SIN HO, SONG, HONG SUNG
2009-02-06 Application filed by LG Display Co Ltd filed Critical LG Display Co Ltd
2009-06-11 Publication of US20090146940A1 publication Critical patent/US20090146940A1/en
2016-04-05 Publication of US9305480B2 publication Critical patent/US9305480B2/en
A display having a data driving integrated circuit includes N number of output channels (where N is an integer) having at least two regions including a first output channel and an Nth output channel, a data output channel group including M data output channels (where M is an integer less than N), the M data output channels supplying pixel data to a corresponding number of the data lines in accordance with a desired resolution of the display, wherein (N−M) output channels are not supplied with pixel data, and the (N−M) output channels are located between the first output channel and the Nth output channel, and a channel selector selecting the M data output channels.
The latch part 36 restores pixel data VD modulated such that the transition bit number is reduced in response to a data inversion selection signal REV to output them. The timing controller 8 modulates the pixel data VD such that the number of transition bits are minimized using a reference value to determine whether the bits should be inverted or not. This minimizes an electro-magnetic interference (EMI) upon data transmission due to a minimal number of bit transactions from LOW to HIGH or HIGH to LOW.
TABLE 1 Pixel number The number of data IC's according Data Gate to output channels of data IC's Resolution line line 600CH 618CH 630CH 642CH XGA 3072 768 5.12 4.97 4.88 4.79 SXGA+ 4200 1050 7.00 6.80 6.67 6.54 UXGA 4800 1200 8.00 7.77 7.62 7.48 WXGA 3840 800 6.40 6.21 6.10 5.98 WSXGA− 4320 900 7.20 6.99 6.86 6.73 WSXGA 5040 1050 8.40 8.16 8.00 7.85 WUXGA 5760 1200 9.60 9.32 9.14 8.97
More specifically, when the first output control signal CS1 is applied from the channel selector 130, the shift register part 134 sequentially shifts a source start pulse SSP signal from the signal controller 120 in response to a source sampling clock signal SSC using the 1st to 600th shift registers SR1 to SR600, and outputs them as sampling signals. In this case, an output signal (i.e., a carry signal) of the 600th shift register SR600 is applied to the 1st shift register SR1 of the next stage data IC 116 for a daisy chain connection. Thus, the 601st to 642nd shift registers SR601 to SR642 do not output sampling signals. If the shift registers are driven in a bilateral direction, then it becomes possible to more advantageously use them by using a dummy treatment without employing the 42 middle channels.
When the third output control signal CS3 is applied from the channel selector 130, the shift register part 134 sequentially shifts a source start pulse SSP signal from the signal controller 120 in response to a source sampling clock signal SSC using the 1st to 630th shift registers SR1 to SR630, and outputs them as sampling signals. In this case, an output signal (i.e., a carry signal) of the 630th shift register SR630 is applied to the 1st shift register SR1 of the next stage data IC 116. Thus, the 631 st to 642nd shift registers SR631 to SR642 do not output sampling signals. Herein, if the shift registers are driven in a bilateral direction, then it is possible to more advantageously use the shift registers by using a dummy treatment without employing the 12 middle channels.
The latch part 136 simultaneously latches the even pixel data VDeven and the odd pixel data VDodd supplied via the signal controller 120 for each sampling signal. Then, the latch part 136 simultaneously outputs the pixel data VD through the selected number of output channels, (600, 618, 630 or 642 data output channels) in response to a source output enable signal SOE from the signal controller 120. The latch part 136 restores pixel data VD which have been modulated such that the transition bit number is reduced in response to a data inversion selection signal REV. This is because the timing controller 108 modulates the pixel data VD, in which the transited bit number goes beyond a reference value, such that the transition bit number is reduced so as to minimize an electro-magnetic interference (EMI) upon data transmission.
The DAC 138 simultaneously converts the pixel data VD from the latch part 136 to positive and negative pixel voltage signals. The DAC 138 includes a positive (P) decoding part 140 and a negative (N) decoding part 142 commonly connected to the latch part 136, and a multiplexer (MUX) part 144 for selecting output signals of the P decoding part 140 and the N decoding part 142.
Accordingly, the LCD according to the second embodiment of the present invention may set output channels of the data IC's 216, for example, to any one of 600 channels, 618 channels, 630 channels and 642 channels in response to the first and second channel selection signals P1 and P2, thereby configuring multiple resolutions of the liquid crystal display panel 102. In other words, the data IC 216 of the LCD according to the second embodiment of the present invention may be set to have 642 data output channels that are set in response to the first and second channel selection signals P1 and P2 from the first and second option pins OP1 and OP2, so that the data IC 216 can be compatibly used for all resolutions of the liquid crystal display panel 102. Further, in the LCD according to the second embodiment, the dummy data output channel group 264 of the data IC 216 is arranged according to a determination of the output channel at the middle portion of data output channels of the data IC 216. In other words, first and second data output channel groups 260 and 262 of the data IC 216 have the same output channels, with the dummy data output channel group 264 therebetween. Thus, the LCD according to the second embodiment of the present invention equalizes the output channels of each of the first and second data output channel groups 260 and 262 of the data IC 216, which reduces an electro-magnetic interference upon output of the pixel data.
When a value of the first and second channel selection signals P1 and P2 applied to the data IC 216 is ‘00’, by connecting each of the first and second option pins OP1 and OP2 to the ground voltage source GND, the data IC 216 outputs pixel data via the first data output channel group 260 having the 1st to 300th output channels. From the 642 data output channels available and the second data output channel group 262 having the 343rd from the 642nd output channels available as shown in FIG. 11. The dummy data output channel group 264 has the 301 st to 342nd output channels which are treated as dummy lines.
First, as shown in FIG. 11, when the 1st to 300th output channels, of the output channels of the data IC 216, are selected as a first output channel group 260, the 301st to 342nd output channels are selected as a dummy output channel group 264, and the 343rd to 642nd output channels are selected as a second output channel group 262. The channel selector 318 of the data IC 316 is supplied with the first and second channel selection signals P1 and P2 having a logical value of “00”. Thus, the shift register part 334 sequentially shifts the source start pulse SSP signal in response to the source sampling clock signal SSC using the 1st to 600th shift registers SR1 to SR600 to thereby output them as sampling signals. At this time, an output signal of the 300th shift register. SR300 is applied, via the first multiplexer 350, the demultiplexer 352 and the fourth multiplexer 358, to the 343rd shift register SR343. Further, an output signal of the 642nd shift register SR642 is applied to the 1st shift register SR1 of the next stage data IC 316. Thus, the 1st to 300th shift registers SR1 to SR300 and the 343rd to 642nd shift registers, SR343 and SR642, apply the sampling signals to the latch part. At this time, the 301st to 342nd shift registers SR301 to SR342 also substantially apply the sampling signals to the latch part.
Furthermore, the LCD according to the present invention includes the data integrated circuit having the dummy data output channel group provided between the first and second data output channel groups for applying data to the data lines, and varies channels of the data integrated circuit based upon a resolution type of the liquid crystal display panel using the channel selection signals, thereby driving all resolutions of the liquid crystal display panel using one-type of data integrated circuit.
64. A display having a data driving integrated circuit, comprising:
N number of output channels where N is an integer including a first to Nth output channel;
a first and second data output channel groups having data output channels which supply pixel data to a corresponding number of data lines in accordance with a desired resolution of the display;
a dummy output channel group provided between the first and second data output channel groups and having dummy output channels wherein the dummy output channels are not supplied with pixel data;
a shift register part including a sequence of N shift registers for shifting a source start pulse, wherein the Nth shift register output a carry signal to 1st shift register of next data driving integrated circuit; and
a channel selector setting the data output channels corresponding to a channel selection signal.
65. The display according to claim 64, wherein the channel selection signal applied into first and second selection terminals selectively connected to a voltage source and ground voltage source.
66. The display according to claim 64, further comprising:
a selection signal generator for generating and applying the channel selection signal to select the data output channels; and
a timing controller controlling the data driving integrated circuit and supplying the pixel data to the data output channels.
67. The display according to claim 66, wherein the selection signal generator includes first and second selection terminals, each of the first and second selection terminals being connected to one of a voltage source and a ground voltage source to generate and supply the channel selection signal.
US12/320,894 2003-12-11 2009-02-06 Liquid crystal display device Active 2026-03-24 US9305480B2 (en)
KR10-2003-0090301 2003-12-11
KR10-2004-0029611 2004-04-28
KR10-2004-0029612 2004-04-28
US10/964,779 US7495648B2 (en) 2003-12-11 2004-10-15 Liquid crystal display device
US10/964,779 Continuation US7495648B2 (en) 2003-12-11 2004-10-15 Liquid crystal display device
US20090146940A1 true US20090146940A1 (en) 2009-06-11
US9305480B2 US9305480B2 (en) 2016-04-05
KR (4) KR100598740B1 (en)
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2004-11-25 TW TW93136310A patent/TWI253623B/en active
2004-12-08 DE DE200410059157 patent/DE102004059157B4/en active Active
2004-12-08 CN CN 200410100118 patent/CN100428004C/en active IP Right Grant
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US7495648B2 (en) 2009-02-24
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US7649521B2 (en) 2010-01-19 Image display apparatus
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KANG, SIN HO;SONG, HONG SUNG;HONG, JIN CHEOL;REEL/FRAME:022278/0628