Source: http://www.google.com/patents/US6818974?dq=6,034,652
Timestamp: 2013-12-11 06:45:20
Document Index: 491316320

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Patent US6818974 - Semiconductor device - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsA semiconductor device which has a preferable construction for downsizing, in which chip part(s) and a cap are not short-circuited, is provided. The semiconductor device includes: a substrate having a first surface with a cavity and a second surface opposite to the first surface; a semiconductor chip...http://www.google.com/patents/US6818974?utm_source=gb-gplus-sharePatent US6818974 - Semiconductor devicePublication numberUS6818974 B2Publication typeGrantApplication numberUS 10/353,950Publication dateNov 16, 2004Filing dateJan 30, 2003Priority dateAug 8, 2002Fee statusPaidAlso published asUS20040026777Publication number10353950, 353950, US 6818974 B2, US 6818974B2, US-B2-6818974, US6818974 B2, US6818974B2InventorsKazuo Yokoyama, Shigeki Kageyama, Jun OtsujiOriginal AssigneeMitsubishi Denki Kabushiki KaishaExport CitationBiBTeX, EndNote, RefManPatent Citations (6), Non-Patent Citations (1), Referenced by (3), Classifications (25), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor deviceUS 6818974 B2Abstract A semiconductor device which has a preferable construction for downsizing, in which chip part(s) and a cap are not short-circuited, is provided. The semiconductor device includes: a substrate having a first surface with a cavity and a second surface opposite to the first surface; a semiconductor chip arranged in the cavity; a chip part mounted on the second surface of the substrate; a heat sink which is mounted on the second surface of the substrate and transfers heat liberated from the chip; a cap which is fitted to the substrate, covers the second surface of the substrate, and is joined to the heat sink; and an insulator provided between the cap and the chip part. By providing the insulator, short-circuiting of the chip part and the cap is prevented. Consequently, a distance between the cap and chip part can be shortened to downsize the size of semiconductor device.
a substrate having a first surface with a cavity and a second surface, opposite the first surface; a semiconductor chip in the cavity and electrically connected to the substrate; at least one passive electrical component chip mounted on the second surface of the substrate and electrically connected to the substrate; a heat sink mounted on the second surface of the substrate and transferring heat liberated from the semiconductor chip; a cap fitted on the substrate, covering the second surface of the substrate, having an inside surface, part of which is opposite the second surface, and joined to the heat sink; and an insulator disposed on at least part of the inside surface of the cap, between the inside surface of the can and the at least one passive electrical component chip. 2. The semiconductor device according to claim 1, wherein the insulator comprises stripes disposed on the inside surface of the cap.
3. The semiconductor device according to claim 1, wherein the insulator covers all of the inside surface of the cap, other than a region of the inside surface of the cap to which the heat sink is joined.
4. The semiconductor device according to claim 1, wherein the insulator covers all of the inside surface of the cap.
5. The semiconductor device according to claim 1, wherein the cap has at least one fitting pawl that secures the cap to the substrate, and the insulator does not cover the at least one fitting pawl.
6. The semiconductor device according to claim 1, wherein the cap has at least one fitting pawl that secures the cap to the substrate, and the insulator covers the at least one fitting pawl.
7. The semiconductor device according to claim 1, wherein the insulator is a thermosetting resin.
a substrate having a first surface with a cavity and a second surface, opposite the first surface; a semiconductor chip in the cavity and electrically connected to the substrate; at least one passive electrical component chip mounted on the second surface of the substrate and electrically connected to the substrate; a heat sink mounted on the second surface of the substrate and transferring heat liberated from the semiconductor chip; and a cap fitted on the substrate, covering the second surface of the substrate, having an inside surface, part of which is opposite the second surface, and joined to the heat sink, wherein the cap is bent toward the second surface of the substrate at an outer edge of a region of the cap that is joined to the heat sink. 9. The semiconductor device according to claim 8, including a hole in the region of the cap, and including an adhesive material for transferring heat filling the hole.
The present invention relates to a semiconductor device with parts mounted on a surface of a substrate and with a cap for radiating heat provided over the parts.
Conventionally, semiconductor modules with parts mounted on surfaces of respective multi-layer substrates have been known. For this kind of semiconductor modules, a requirement exists that parts are mounted in an efficient mounting area. Therefore, some of semiconductor modules have cavities provided on rear surfaces of respective multi-layer substrates so that semiconductor chips can be arranged in the cavities. This kind of semiconductor module has a heat sink located on another surface of the multi-layer substrate opposite to the surface where the semiconductor chip is provided. The heat sink is joined to the cap of semiconductor module. Because the cap is formed by metal with high thermal conductivity, heat liberated from the semiconductor chip is radiated via the heat sink and the cap. According to this arrangement, the semiconductor module stably operates.
In recent years, requests for downsizing products such as cellular phones have increased, and as a result, a need to still further downsizing semiconductor modules such as power amplifier modules arises.
In the arrangement of the conventional semiconductor module, the module cannot be downsized because the size of heat sink is respectively large. The reason is that a fear of short-circuiting the cap and chip parts arises, when the heat sink and the cap are downsized to suppress size of the module.
For example, consider the case to change the heat sink from type 1608 (1.6 mm�0.8 mm) to type 1005 (1.0 mm�0.5 mm) that bulk feeders can operate. Level of the heat sink reaches the same as that of other 1005 chip parts (for example, L, C, R). Depending on tolerances of chip parts, the cap and chip parts may electrically short-circuiting. Note that the term �tolerances� means a difference in size between maximum and minimum values allowed from the viewpoint of specifications.
Although it is possible to change all the chip parts to type 0603 (0.6 mm�0.3 mm), some of the parts of type 0603 do not satisfy necessary characteristics. Thus, cost increases as a result. In addition, in the case caps are not used and heat is radiated through, for example, molds, shielding capability for preventing leakage of electric power as well as influence on peripheral parts is required for current products. To provide shielding capability, further different configuration is required, and as a result, downsizing is unable to be achieved and the cost increases.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device of an arrangement in which chip parts and caps are not short-circuited and at the same time which achieves downsizing.
The first semiconductor device according to the present invention includes a substrate, a semiconductor chip, at least one chip part, a heat sink, a cap and an insulator. The substrate has a first surface with a cavity and a second surface on the opposite side of the first surface. The semiconductor chip is arranged in the cavity and electrically connected to the substrate. The at least one chip part is mounted on the second surface of the substrate and electrically connected to the substrate. The heat sink is mounted on the second surface of the substrate and transfers heat liberated from the semiconductor chip. The cap is fitted to the substrate, covers the second surface of the substrate, and is joined to the heat sink. The insulator is provided between the cap and the at least one chip part.
By providing the insulator, for example, thermoplastic resin, short-circuiting of the chip part and the cap is prevented. Consequently, a distance between the cap and chip part can be shortened to downsize the size of semiconductor device. The size of the semiconductor device can be further and more effectively downsized by reducing size of the heat sink.
The second semiconductor device according to the present invention includes a substrate, a semiconductor chip, at least one chip part, a heat sink and a cap. The substrate has a first surface with a cavity and a second surface on the opposite side of the first surface. The semiconductor chip is arranged in the cavity and electrically connected to the substrate. The at least one chip part mounted on the second surface of the substrate and electrically connected to the substrate. The heat sink is mounted on the second surface of the substrate and transfers heat liberated from the semiconductor chip. The cap is fitted to the substrate, covers the second surface of the substrate, and is joined to the heat sink. Further, the cap is bent in the substrate direction at an outer edge of a region where the cap is joined to the heat sink. According to the above arrangement, short-circuiting between the cap and chip parts can be avoided without providing insulation film between the cap and chip parts.
FIG. 1 is a perspective view of a semiconductor module according to embodiment 1;
FIG. 2 is a cross-sectional view of the semiconductor module cut along line A�A′ of FIG. 1;
FIG. 3 is a development of a cap;
FIG. 4 is a development of a cap by the second example with insulation film affixed;
FIG. 5 is a cross-sectional view of a semiconductor module by the second example with insulation film affixed;
FIG. 6 is a development of a cap by the third example with insulation film affixed;
FIG. 7 is a development of semiconductor module with insulation film affixed over the whole surface;
FIG. 8 is a cross-sectional view of semiconductor module according to embodiment 2;
FIG. 9 is a development of a cap with insulation film affixed over the whole surface except fitting pawls;
FIG. 10 is a perspective view of semiconductor module according to embodiment 3;
FIG. 11 is a cross-sectional view of semiconductor module cut on line A�A′ of FIG. 10;
FIG. 12 is a perspective view of semiconductor module according to another example of embodiment 3;
FIG. 13 is a cross-sectional view of semiconductor module cut on line A�A′ of FIG. 12;
FIG. 14 is a cross-sectional view of semiconductor module related to a modified example of embodiments 1 and 2; and
FIG. 15 is a view showing a semiconductor module using filletless chip parts.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the attached drawings, preferred embodiments 1 through 3 of the present invention will be described as follows. In the drawings, the same reference characters are designated to elements with same or similar functions. Semiconductor modules described in the following embodiments are intended such as power amplifier modules and small-size high-frequency modules.
FIG. 1 is a perspective view of semiconductor module 100 according to embodiment 1. Semiconductor module 100 is formed with cap 10 fitted over multi-layer substrate 30. As described later, on a rear surface of multi-layer substrate 30, a cavity, that is, a hollow section, or a recessed section from the rear surface of the substrate is provided, in which one or more semiconductor chips (not illustrated) are mounted. On the other hand, on the opposite side of multi-layer substrate 30 of the semiconductor chip, heat sink 20 is provided. Cap soldering material 40 is applied to heat sink 20, by which heat sink 20 and cap 10 are physically fixed. As a result, heat liberated from the semiconductor chip is transmitted to the surface of multi-layer substrate 30 and radiated to outside via heat sink 20, cap soldering material 40, and cap 10.
One of primary features of semiconductor module 100 is that insulation film 11 is affixed to the surface of the rear side (opposite side of outer surface) of cap 10. To explain more in detail, cap 10 is formed with metal with high thermal conductivity, such as copper, aluminum, etc., in order to function as a shield for preventing leakage of electric power and influence on peripheral parts to improve heat radiation performance. Consequently, if cap 10 is short-circuited with one or more chip parts (hereinafter referred to as �chip parts�) on multi-layer substrate 30, element destruction and overheat would occur, causing danger and at the same time preventing them from exhibiting their originally intended performance.
Because of the above reason, insulation film 11 is affixed to the rear surface of cap 10 facing multi-layer substrate 30 so that short-circuiting between chip parts (not illustrated) and cap 10 is prevented. Film 11 is affixed to, for example, a strip-form section including one or more regions facing chip parts 80. Insulation film 11 may be made of publicly known materials, such as epoxy resin (for example, Obi-One Coat) as thermosetting resin, polyimide resin (for example, PIMET of Sumitomo Electric Industries), etc. However, because cap soldering material 40 on heat sink 20 must come in direct contact with cap 10, no insulation film is affixed to a strip-form region at the upper part of heat sink 20. The thickness of heat insulation film is, for example, 50-200 μm.
FIG. 2 is a cross-sectional semiconductor module 100 cut along line A�A′ in FIG. 1. As clear from the figure, semiconductor module 100 has parts (Surface Mounted Device; SMD) mounted on multi-layer substrate 30, and is formed by fitting cap 10 into multi-layer substrate 30 as a shield. In addition, a cavity is provided on the rear side of multi-layer substrate 30, and semiconductor chip 50 is electrically connected to multi-layer substrate 30 by bonding wire 60. When connection is secured by bonding wire 60, the cavity is filled with potting material 70 and semiconductor chip 50 is sealed.
Insulation film 11 lies between cap 10 and chip parts 80 which are mounted on multi-layer substrate 30. According to this configuration, short-circuiting can be prevented. In addition, it is understood that no insulation film 11 is affixed at the upper part of region 20 and cap soldering material 40 is fixed directly in contact with cap 10. To spaces where no insulation film 11 is affixed, chip parts 80 may be mounted if levels of chip parts 80 are lower than heat sink 20. Note that chip parts with the same levels as the heat sink 20 or with levels higher than heat sink 20 cannot be mounted on the spaces depending on parts tolerances. Further note that soldering material 41 is used to connect multi-layer substrate 30 and heat sink 20, and to connect multi-layer substrate 30 and chip parts 80 parts.
In the case that size of heat sink 20 is reduced from type 1608 (1.6 mm�0.8 mm) to type 1005 (1.0 mm�0.5 mm, height 0.5 mm�0.05 mm), inductors of type 1005 (height 0.45 mm�0.05 mm) can be used. This is because short-circuiting may not occur because of presence of insulation film 11. Accordingly, the distance between chip parts 80 and cap 10 can be reduced. At the same time, since the mounting area of heat sink 20 and its size in the height direction can be reduced, height of semiconductor module 100 in the direction vertical to multi-layer substrate 30 can also be reduced. Consequently, the whole size of semiconductor module 100 can be reduced.
FIG. 3 is a development of cap 10. By folding in the same direction at a dotted line, cap 10 of FIG. 2 can be obtained. Insulation film 11 is affixed to both sides of cap 10. Cap soldering material 40 is connected to cap 10 in strip-form portion 9 between insulation films 11. That is, on the rear surface of cap 10, insulation film 11 is affixed on stripes. Affixing insulation film 11 in the form of stripe is extremely convenient and consequently, it can be achieved at a low cost. Note that, in this example, insulation film 11 is not affixed to fitting pawl 12 of cap 10 for fitting cap 10 into multi-layer substrate 30. This allows solder to climb up a rear surface of cap fitting pawl to enhance mounting strength when customers mounts the semiconductor module.
FIG. 4 is a development of cap 10 according to the second affixing example of insulation film 11. The difference from FIG. 3 lies in that insulation film 11 is affixed even to fitting-pawl 12 of cap 10. According to this configuration, the same advantages as an example shown in FIG. 3 are obtained. What is more advantageous as compared to the case in which insulation film 11 is affixed except for the portion of fitting pawl 12 is that it is no longer necessary to be aware of the accuracy of the outer periphery of stripe. Consequently, insulation film 11 can be affixed at still lower cost and therefore, the cap can be manufactured at lower cost.
FIG. 5 is a cross-sectional view of semiconductor module 100 according to the second affixing example of insulation film 11. Although Insulation film 11 is affixed even to fitting pawl 12 of cap 10, such configuration affects no influence on operations of semiconductor module 100. Note that, since multi-layer substrate 30, soldering material 41, semiconductor chip 50, bonding wire 60, potting material. 70, and chip parts 80 are exactly same as those of FIG. 2. Therefore, explanations on these elements will be omitted.
FIG. 6 is a development of cap 10 according to the third affixing example of insulation film 11. Insulation film 11 is affixed to cap 10 in all the area except for region 9 where cap soldering material 40 and cap 10 come into contact. In other words, insulation film 11 with the portion of region 9 removed (cut away) is affixed. According to this configuration, not only the same advantages as those shown in FIG. 3 are obtained but also a wider insulated portion can be obtained, and the degree of design freedom can be increased. Note that region 9 may not be exactly the region where cap soldering material 40 and cap 10 come in contact and may be varied as necessary if changes are required from the viewpoint of manufacturing.
In embodiment 2, a semiconductor module will be described, in which cap soldering material on a heat sink comes in contact with a cap via insulation film to radiate heat.
FIG. 7 is a development of cap 10 to which insulation film 11 is affixed to the whole surface. Region 9 is the position corresponding to the upper part of heat sink. In this example, insulation film 11 is affixed to region 9. In addition, to fitting pawl 12 of cap 10, insulation film 11 is affixed.
FIG. 8 is a cross-sectional view of semiconductor module 102 according to embodiment 2. Semiconductor module 102 differs from that in FIG. 2 in the arrangement of the portion between cap 10 and heat sink 20. Description will be primarily made on the relevant different portion. Note that, since multi-layer substrate 30, soldering material 41, semiconductor chip 50, bonding wire 60, potting material 70, and chip parts 80 are exactly the same as those of FIG. 2, explanations on these elements will be omitted.
In embodiment 2, between cap 10 and heat sink 20, insulation 11 and thermoplastic resin 40 are provided in this order from the side of cap 10. Thermosetting resin 40 is provided in place of cap soldering material. Thermosetting resin 40 also provides high thermal performance and is sufficient to transfer heat liberated from heat sink 20 to cap 10. In this example, since insulation film 11 is affixed to the whole surface of cap 10, as compared to the case in which insulation film 11 is affixed except for the upper position of heat sink, a trimming process of insulation film 11 can be omitted. Consequently, cap 10 can be manufactured conveniently and inexpensively. In addition, reduction of parts contact, heat radiation performance, and parts size can be achieved similar to embodiment 1.
Note that, in this example, since insulation film 11 is affixed to fitting pawl 12 of cap 10, the insulation film affixing accuracy is no longer required to be intentionally improved, and cap 10 can be manufactured more conveniently and inexpensively. However, needless to say, even if insulation film 11 is not affixed to fitting pawl 12, reduction of parts contact, heat radiation performance, and parts size can be achieved. FIG. 9 is a development of cap 10 with insulation film 11 affixed to all the surfaces except fitting pawl 12. In order to affix insulation film 11 as illustrated, an affixing accuracy of insulation film 11 must be improved. However, since no insulation film 11 exists, solder climbs up the rear surface of cap fitting pawl 12 at the time of mounting at customers and increase of mounting strength can be expected.
In embodiment 3, a semiconductor module that has a cap with a portion joined to a heat sink recessed will be described. By recessing a part of the cap, it is no longer necessary to provide the insulation film described in embodiments 1 and 2.
FIG. 10 is a perspective view of semiconductor module 110 according to embodiment 3. As shown in the figure, recess 13 folded and set back from the periphery to the multi-layer substrate 30 side is provided to cap 10. The recess designated as cap recess 13 will be discussed hereinafter. Cap recess 13 is located at the upper part of a heat sink (not illustrated).
FIG. 11 shows a cross-sectional view of semiconductor module 110 cut along line A�A′ of FIG. 10. Semiconductor module 110 differs from the semiconductor module of FIG. 2 in configuration of cap 10 as well as in that no insulation film 11 is affixed to cap 10 of semiconductor module 110. In the following section, description will be primarily made on the relevant different portion. Note that, since multi-layer substrate 30, soldering material 41, semiconductor chip 50, bonding wire 60, potting material 70, and chip parts 80 are exactly the same as those in FIG. 2, explanations on these elements will be omitted.
As clear from the figure, cap 10 has cap recess 13 at the upper part of heat sink 20. In other words, cap recess 13 is provided to be bent in the substrate direction of cap 10 at the outer edge of the region joined to the heat sink. Depending on set back amount (i.e. bent amount) from the surface of cap 10, clearance at the upper part of heat sink 20 can be adjusted. For example, assume that the set back amount of cap recess 13 is 0.05 mm from the surface of cap 10. Then, it is possible to gain clearance of at least 0.05 mm in the case height of heat sink 20 is 0.5�0.05 mm and inductor height which is one of peripheral chip parts 80 is 0.45�0.05 mm. Conversely, if the set back amount from the surface of cap recess 13 is increased, the height of heat sink 20 can be lowered in accordance with the increase. Therefore, heat sink 20 can be downsized and at the same time, short-circuiting of cap 10 and chip parts 80 can be avoided. The use of cap 10 described in this embodiment can eliminate a need to affix insulation film 11 as shown in FIG. 2, semiconductor modules can be manufactured at still lower cost.
FIG. 12 is a perspective view of semiconductor module 120 according to another example of embodiment 3. Unlike the preceding cap recess 13 (FIG. 10), a hole is provided in cap 10 of semiconductor module 120. The figure illustrates a condition in which adhesive 40 is injected in the hole to the surface of cap 10.
FIG. 13 shows a cross-sectional view of semiconductor module 120 cut at line A�A′ of FIG. 12. Semiconductor module 120 differs from the semiconductor module of FIG. 11 in the arrangement of cap 10. In the following section, description will be primarily made on the relevant different portion. Note that, since multi-layer substrate 30, soldering material 41, semiconductor chip 50, bonding wire 60, potting material 70, and chip parts 80 are exactly the same as those in FIG. 11, explanations on these elements will be omitted.
As illustrated in FIG. 13, cap 10 of semiconductor module 120 has a hole provided in the region corresponding to the upper part of heat sink 20. This hole is obtained by removing the bottom section of cap recess 13 (FIG. 11) and passes through from the top surface of heat sink 20 to the surface of cap 10. By providing the hole, it becomes possible to dispense adhesives 40 from the top surface of the cap 10 to fill the hole with the adhesive, manufacturing efficiency can be improved. Furthermore, even when adhesive 40 is dispensed in excess, a predetermined volume of adhesive 40 is easily scraped away from the hole. Therefore, operating efficiency can be improved and the manufacturing efficiency can be further improved. Note that, because cap 10 in this modified example is obtained only by removing the bottom of cap recess 13 (FIG. 11), the advantages explained for cap 10 in FIG. 11 can be obtained as advantages of this example as they are.
Now, embodiments of the present invention have been described. In embodiments 1 and 2, in order to avoid short-circuiting between the cap and the chip parts, insulation film is provided to the surface of the cap facing the chip parts. However, if short-circuiting can be avoided, it is not necessary to restrict to this configuration. For example, thermosetting resin with nonconductive and heat transferring characteristics is applied on the substrate (on chip parts) and a cap may be affixed. Furthermore, such resin can be filled between cap 10 and multi-layer substrate 30 instead of or at the same time in applying on the chip parts. The resin also functions as an adhesive to affix cap 10 and multi-layer substrate 30.
FIG. 14 is a cross-sectional view of semiconductor module 140 related to a modified example of embodiments 1 and 2. Semiconductor module 140 is formed by filling a space defined between facing surfaces of cap 10 and multi-layer substrate 30, or surfaces of cap 10 and chip parts 80, with nonconductive resin (adhesive agent) 42. The adhesive agent is, for example, thermosetting resin such as epoxy resin. Cap 10 is brought in direct contact with nonconductive resin and fixed. According to this arrangement, electrical short-circuiting may not occur, since nonconductive resin is inserted between cap 10 and chip parts 80. In addition, because heat generated at semiconductor chip 50 is transmitted directly to cap through nonconductive resin, the heat sink can be eliminated. Consequently, the physical dimensions of semiconductor module 140 can be extremely reduced.
In addition, by using one or more filletless parts for all the chip parts 80, the semiconductor module can be downsized. �Fillet� referred to here means a solder-buildup or a shape the solder-buildup that expands from top to bottom when electrode terminal of element and mounting land are soldered. Consequently, �filletless parts� means parts free of such solder-buildup. FIG. 15 is a diagram showing semiconductor module 130 using filletless chip parts 81. In this figure, multi-layer substrate 30, soldering material 41, semiconductor chip 50, bonding wire 60, and potting material 70 are exactly the same as those in FIG. 2, and explanations on these elements will be omitted. The use of filletless parts can lower the cap and can prevent short-circuiting because electrode terminals and the cap will not be brought into contact and no unwanted solder buildup exists. In addition, since the land width or land area can be made smaller, the mounting area of chip parts 80 can be reduced. As a result, simply downsizing conventional caps and heat sinks enables downsizing semiconductor modules without providing insulation film to the cap. If filletless parts are used in semiconductor modules of embodiments 1 through 3, advantages of each of embodiments 1 through 3 can be obtained and further downsizing can be promoted.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS5757031Nov 22, 1996May 26, 1998Nec CorporationSemiconductor static memory device having a TFT loadUS5757081Feb 20, 1996May 26, 1998Siliconix IncorporatedSurface mount and flip chip technology for total integrated circuit isolationUS6207354 *Apr 7, 1999Mar 27, 2001International Business Machines CoporationMethod of making an organic chip carrier packageUS6246115 *Oct 21, 1999Jun 12, 2001Siliconware Precision Industries Co., Ltd.Semiconductor package having a heat sink with an exposed surfaceUS6472741 *Jul 14, 2001Oct 29, 2002Siliconware Precision Industries Co., Ltd.Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the sameJPH07106471A Title not available* Cited by examinerNon-Patent CitationsReference1"Starting Delivery of GaAsFET Power Amblifier Modules of PDC", http://www.mitsubishielectric.co.jp/news/2001/0314-b.htm.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8018739 *Mar 8, 2010Sep 13, 2011Maxwell Technologies, LLCApparatus for shielding integrated circuit devicesUS8089146Jan 29, 2010Jan 3, 2012Fujitsu LimitedSemiconductor device and heat radiation memberUS20120153448 *Sep 23, 2011Jun 21, 2012c/o FUJITSU SEMICONDUCTOR LIMITEDSemiconductor device and manufacturing method of semiconductor device* Cited by examinerClassifications U.S. Classification257/676, 257/712, 361/704, 257/E23.9, 257/200, 257/E25.31, 257/E23.181, 257/706, 361/699International ClassificationH01L23/04, H01L23/433, H01L23/34, H01L25/00, H01L25/16Cooperative ClassificationH01L23/552, H01L23/433, H01L23/04, H01L25/165, H01L2924/1532, H01L2924/19106, H01L2924/15153, H01L2224/48227European ClassificationH01L23/04, H01L23/433, H01L25/16HLegal EventsDateCodeEventDescriptionApr 25, 2012FPAYFee paymentYear of fee payment: 8May 2, 2008FPAYFee paymentYear of fee payment: 4Jan 30, 2003ASAssignmentOwner name: MITSUBISHI DENKI KABUSHIKI KAISHA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOKOYAMA, KAZUO;KAGEYAMA, SHIGEKI;OTSUJI, JUN;REEL/FRAME:013731/0986Effective date: 20021225Owner name: MITSUBISHI DENKI KABUSHIKI KAISHA 2-3, MARUNOUCHIFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOKOYAMA, KAZUO /AR;REEL/FRAME:013731/0986RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google