Source: http://www.google.com/patents/US20020096781?ie=ISO-8859-1
Timestamp: 2015-05-25 05:59:11
Document Index: 428421309

Matched Legal Cases: ['arts 2', 'art 2', 'art 2', 'arts 2', 'arts 12', 'art 12', 'art 12', 'arts 12']

Patent US20020096781 - Semiconductor device and liquid crystal module using the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device in accordance with the present invention is a semiconductor device using TCP structure, including a first semiconductor chip mounted on a tape carrier by ILB and a second semiconductor chip mounted on the tape carrier via the first semiconductor chip. The first semiconductor chip...http://www.google.com/patents/US20020096781?utm_source=gb-gplus-sharePatent US20020096781 - Semiconductor device and liquid crystal module using the sameAdvanced Patent SearchPublication numberUS20020096781 A1Publication typeApplicationApplication numberUS 10/022,498Publication dateJul 25, 2002Filing dateDec 20, 2001Priority dateJan 25, 2001Also published asUS6552419Publication number022498, 10022498, US 2002/0096781 A1, US 2002/096781 A1, US 20020096781 A1, US 20020096781A1, US 2002096781 A1, US 2002096781A1, US-A1-20020096781, US-A1-2002096781, US2002/0096781A1, US2002/096781A1, US20020096781 A1, US20020096781A1, US2002096781 A1, US2002096781A1InventorsKenji ToyosawaOriginal AssigneeKenji ToyosawaExport CitationBiBTeX, EndNote, RefManReferenced by (11), Classifications (58), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device and liquid crystal module using the same
US 20020096781 A1Abstract
A semiconductor device in accordance with the present invention is a semiconductor device using TCP structure, including a first semiconductor chip mounted on a tape carrier by ILB and a second semiconductor chip mounted on the tape carrier via the first semiconductor chip. The first semiconductor chip is arranged so that a first electrode, formed on a surface of the first semiconductor chip for an electrode, is connected to an inner lead via a gold bump, whereas the second semiconductor chip is arranged so that an electrode thereof is connected to a second electrode formed on that surface via a gold bump. On this account, it is possible to reduce a terminal pitch of the semiconductor device on which more than one semiconductor chip are mounted. Images(13) Claims(13)
What is claimed is: 1. A semiconductor device, comprising: a tape carrier including: a wiring pattern formed on an organic base having an opening; and an inner lead which is a part of the wiring pattern jutting into the opening; a semiconductor chip mounted on the tape carrier by fitting in the opening thereof and connecting a first electrode formed on a surface of the semiconductor chip for an electrode to the inner lead via a gold bump; and an electronic component, mounted on the tape carrier via the semiconductor chip, and including an electrode connected via a gold bump to a second electrode formed on the surface. 2. The semiconductor device as set forth in claim 1, wherein the electronic component is narrower than the semiconductor chip. 3. The semiconductor device as set forth in claim 1, wherein the inner lead is plated with tin or gold. 4. The semiconductor device as set forth in claim 1, wherein the gold bump, which can connect the second electrode of the semiconductor chip to the electrode of the electronic component, is formed on either the second electrode or the electrode of the electronic component. 5. The semiconductor device as set forth in claim 1, further comprising a resin for sealing the semiconductor chip and the electronic component, wherein the resin is not provided on a back surface of the electronic component, which surface is opposite to a surface of the electronic component for an electrode. 6. The semiconductor device as set forth in claim 1, wherein the semiconductor chip is a liquid crystal driver IC, and the electronic component is an SRAM. 7. A liquid crystal module comprising the semiconductor device as set forth in claim 6, wherein the semiconductor device is connected to a liquid crystal panel. 8. A semiconductor device, comprising: a tape carrier including; a wiring pattern formed on an organic base having an opening; and an inner lead which is a part of the wiring pattern jutting into the opening; a semiconductor chip mounted on the tape carrier by fitting in the opening thereof and connecting a first electrode formed on a surface of the semiconductor chip for an electrode to the inner lead via a gold bump; an electronic component, mounted on the tape carrier via the semiconductor chip, including an electrode connected to a second electrode formed on the surface; and a second electronic component, stacked on the electronic component with back surfaces thereof facing each other, and mounted on the tape carrier by wire-bonding. 9. The semiconductor device as set forth in claim 8, wherein an electrode of the second electronic component is connected to the inner lead by wire-bonding. 10. The semiconductor device as set forth in claim 8, wherein an electrode of the second electronic component is connected to the wiring pattern by wire-bonding. 11. The semiconductor device as set forth in claim 8, wherein the electronic component is narrower than the semiconductor chip. 12. The semiconductor device as set forth in claim 8, wherein a third electronic component is further stacked on the second electronic component. 13. A semiconductor device in which: a semiconductor chip is mounted on a tape carrier including a wiring pattern formed on an organic substrate having an opening in which the semiconductor chip is inserted, by connecting the semiconductor chip to an inner lead that is a part of the wiring pattern jutting into the opening; a first electrode made by a gold bump and connected to the inner lead and a second electrode made by a gold bump are formed on a surface of the semiconductor chip for an electrode that faces the inner lead; and another electronic component is mounted on the tape carrier via the semiconductor chip by connecting the second electrode to an electrode of the electronic component, which is made of a gold bump. Description
FIELD OF THE INVENTION [0001] The present invention relates to package structure of a semiconductor device using a tape to mount a semiconductor chip, and a liquid crystal module using the semiconductor device. BACKGROUND OF THE INVENTION [0002] TAB (Tape Automated Bonding), which is a technique to mount a semiconductor chip on a tape made of an organic base material, is used for a liquid crystal display unit employed as a monitor of a personal computer, mobile devices such as a mobile phone and a pocket game machine, and so forth. These devices are mounted using package structure such as a TCP (Tape Carrier Package) and a COF (Chip on Film), and especially the TCP structure is preferable to package devices thinly so that the structure has widely been used in the aforementioned devices. [0003]FIG. 12 is a cross-sectional view describing a typical mounting method using the TCP structure, which has been conventionally known. A tape (tape carrier) 3 is formed by creating a copper wiring pattern 2 on a base 1 made of organic materials such as polyimide. Extending parts 2 a and 2 b of the copper wiring pattern 2 extend from the periphery of the base 1 to be in parallel with each other. The extending part 2 a is connected to, for instance, a pad of a liquid crystal panel, whereas the extending part 2 b is connected to, for instance, a power source and a pad of a printed board to which an image data signal is transmitted. The parts are electrically connected via an anisotropic conductive film etc. [0004] A device hole 5 is formed through the base 1 in accordance with a semiconductor chip 4 to be mounted. The copper wiring pattern 2 jut into the device hole 5 to form inner leads 2 c. The inner lead 2 c and the extending parts 2 a and 2 b of the copper wiring pattern 2 are plated with tin (not illustrated). To be connected with gold bumps 6 provided in all four sides of the rectangle semiconductor chip 4, the inner leads 2 c jut into the device hole 5 from the four directions. [0005] In the semiconductor chip 4 manufactured by dicing a wafer, as eutectic, the gold bump 6 thereof is bonded with the tin which electroless-plates the inner lead 2 c, and this arrangement is termed ILB (Inner Lead Bonding). [0006] An element surface of the mounted semiconductor chip 4 and surroundings of the inner lead 2 c are sealed by potting a resin 7, so that mechanical strength of the device is retained and the same is protected from the environment. Incidentally, other parts of the tape 3 than the electrode parts such as the inner lead 2 c are protected with a coating with a solder resist 8. These processes above are successively done on the tape 3 so that the mounting operation is efficiently done. [0007] In the meantime, rapid development of electronic devices in recent years has demanded an arrangement of multiple chips instead of one being mounted on one tape. As an example of this, a liquid crystal module, mounted on small devices such as the aforementioned mobile phone and pocket game machine, will be described. [0008] To keep up with an increase of the number of wires in the liquid crystal panel, the liquid crystal module has been arranged so that a memory is provided in a driver IC to boost efficiency of driver operation. However, as a result memory capacity has been increased due to further growth of the number of pixel and employment of a color display. For instance, an SRAM occupies 60% of the surface of a semiconductor chip when the SRAM is manufactured along with common and segment drivers in a process necessary to manufacture the common and segment drivers. [0009] Meanwhile, a driver part is required to withstand high voltage to control pixel contrast of a liquid crystal panel and hence a fine process is unsuitable for manufacturing the driver part. However, the fine process can be applied to manufacturing of a memory part since the same does not necessarily withstand high voltage. That is, although unapplicable to the driver part, the fine process can be applied to a memory part since the same is not under the constraint of voltage, and thus the liquid crystal module can meet the required level of integration in accordance with the number of wires of the liquid crystal panel. [0010] Accordingly, it has been researched to form the driver part and the memory part separately in each optimized process, and then mount the manufactured two semiconductor chips, i.e. a driver chip and a SRAM chip, on one tape. [0011] As a conventional technique to mount two semiconductor chips, for instance, Japanese Laid-Open Patent Publication No. 11-54695/1999 (Tokukaihei 11-54695; published on Feb. 26, 1999) discloses an arrangement as below. [0012] In this arrangement, although not using the ILB, a second semiconductor chip is stacked on a first semiconductor chip bonded on a lead frame. When stacked, the second semiconductor chip is provided with its face down and a melting point of a solder ball of the upper second semiconductor chip is arranged to be higher than that of a solder ball of the lower first semiconductor chip, so as to prevent the solder ball from dropping when soldering. On this account, the stacking can be fulfilled without using wire-bonding and the height of the package can be held low. Also, the Publication discloses an arrangement so that the lead frame is omitted by forming the second semiconductor chip to be smaller than the first chip and supporting the unoverlapped part with a supporting lead, so as to lower the chip by the same height. [0013] However, it is possible to point out that the conventional technique as above cannot reduce a terminal pitch smaller than 100 μm due to the use of the solder joint, and hence the arrangement cannot meet the requirement to produce a finer liquid crystal panel. SUMMERY OF THE INVENTION [0014] The present invention aims at providing a semiconductor device in which a terminal pitch can be shortened and a liquid crystal module using the same, when the semiconductor device is arranged so that multiple numbers of chips are stacked. [0015] To achieve the aim above, the semiconductor device of the present invention includes: [0016] a tape carrier including: a wiring pattern formed on an organic base having an opening; and an inner lead which is a part of the wiring pattern jutting into the opening; [0017] a semiconductor chip mounted on the tape carrier by fitting in the opening thereof and connecting a first electrode formed on a surface of the semiconductor chip for an electrode to the inner lead via a gold bump; and [0018] an electronic component, mounted on the tape carrier via the semiconductor chip, and including an electrode connected via a gold bump to a second electrode formed on the surface. [0019] According to this arrangement, the semiconductor chip and the inner lead and also the semiconductor chip and the electronic component are connected via the gold bumps, when the semiconductor device using TCP structure is arranged so that multiple numbers of chips are stacked, namely the semiconductor chip is mounted by ILB and another electronic component is further mounted thereon. [0020] On this account, the gold bump is less deformed when connected than soft solder bumps which is softer than the gold bump, and hence the terminal pitch can be shortened to, for instance, around 45 μm so that not less than 450 terminals can be provided on a chip which is around 20mm long. As a result, the arrangement can meet the requirement to produce a finer liquid crystal panel. [0021] For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS [0022]FIG. 1 is a cross-sectional view of a semiconductor device in accordance with a first embodiment of the present invention. [0023]FIG. 2 is a plan view of FIG. 1 showing a manufacturing process of the semiconductor device. [0024]FIG. 3 is a plan view of FIG. 1 showing a manufacturing process of the semiconductor device. [0025]FIG. 4 is a plan view of FIG. 1 showing a manufacturing process of the semiconductor device. [0026]FIG. 5 is a cross-sectional view showing another arrangement of FIG. 1. [0027]FIG. 6 is a cross-sectional view showing a further arrangement of FIG. 1. [0028]FIG. 7 is a cross-sectional view showing yet another arrangement of FIG. 1. [0029]FIG. 8 is a cross-sectional view of a semiconductor device in accordance with a second embodiment of the present invention. [0030]FIG. 9 is a cross-sectional view of a semiconductor device in accordance with the second embodiment of the present invention. [0031]FIG. 10 is a cross-sectional view of a semiconductor device in accordance with a third embodiment of the present invention. [0032]FIG. 11 is a cross-sectional view of a semiconductor device in accordance with the third embodiment of the present invention. [0033]FIG. 12 is a cross-sectional view describing a typical semiconductor device using TCP, which has been conventionally known.
DESCRIPTION OF THE EMBODIMENTS [0034] The following description will discuss a first embodiment in accordance with the present invention in reference to FIGS. 1 to 7. [0035]FIG. 1 is a cross-sectional view of a semiconductor device in accordance with a first embodiment of the present invention. FIGS. 2 to 4 are plan views of FIG. 1, and FIG. 4 indicates a cutting plane of FIG. 1 with referential signs A-A. [0036] A tape (tape carrier) 13 is arranged by providing a copper wiring pattern 12 on a base 11 made of organic materials such as polyimide. Extending parts 12 a and 12 b of the copper wiring pattern 12 extend from the periphery of the base 11 to be in parallel with each other. The extending part 12 a is connected to, for instance, a pad of a liquid crystal panel via an anisotropic conductive film etc., whereas the extending part 12 b is connected to, for instance, a power source and a pad of a printed board to which an image data signal is transmitted. The parts are electrically and mechanically connected. A liquid crystal module contains a liquid crystal panel, a printed board, and a semiconductor device connecting these two. [0037] The connection of the semiconductor device on the liquid crystal panel is done, for instance, by compress-bonding an ACF (Anisotropic Conductive Film) on a connecting part of the liquid crystal panel and then connecting the semiconductor device thereon using a panel mounting machine. Conditions of the connection are, for instance, at a temperature of 200� C., for 2 seconds, and under a pressure of 3 MPa. [0038] A device hole 15 is formed through the base 11 in accordance with a semiconductor chip 14 mounted by ILB. The copper wiring pattern 12 jut into the device hole 15 to form inner leads 12 c. The inner lead 12 c and the extending parts 12 a and 12 b of the copper wiring pattern 12 are plated with tin (not illustrated). To be connected with gold bumps 16 provided in all four sides of the rectangle semiconductor chip 14, the inner leads 12 c jut into the device hole 15 from the four directions, as FIG. 2 shows. [0039] In the semiconductor chip 14 manufactured by dicing a wafer, as eutectic, the gold bump 16 thereof is bonded with tin which electroless-plates the inner lead 12 c so that the semiconductor chip 14 is mounted by ILB. The thickness of the tin plating is, for instance, around 0.5 μm. The tin plating is alloyed into the copper of the inner lead 12 c to form an alloy layer so that a pure tin layer thereof is around 0.15 μm. The inner lead 12 c may be plated with gold. [0040] It is significant that in the present invention, the gold bumps 16 for the ILB are formed along the edge of the semiconductor chip 14 while gold bumps 17 are formed inside the row of the gold bumps 16, and a semiconductor chip 18 is further mounted on the semiconductor chip 14, as FIGS. 1 and 3 show. [0041] An element surface of the mounted semiconductor chip 14 and surroundings of the inner lead 12 c are, as FIG. 4 shows, sealed by potting a resin 20, so that mechanical strength of the device is retained and the same is protected from the environment. Incidentally, other parts of the tape 13 than the electrode parts such as the inner lead 12 c are protected with a coating with a solder resist 21. These processes above are successively done on the tape 13 so that the mounting operation is efficiently done. [0042] The semiconductor chip 14 is a liquid crystal driver IC that drives common and segment electrodes of the liquid crystal panel. The semiconductor chip 14 is arranged to have a 0.6 to 0.65 μm width wire, and a terminal pitch thereof is reduced to 50 μm due to gold bumps 17 and 19 even if the chip 14 is sized 17�1.6 mm. The semiconductor chip 14 also includes 96 output terminals on the common side and 308 output terminals on the segment side. The gold bumps 16 and 17 are formed, for instance, to measure 85�40 μm. The semiconductor chip 18 is an SRAM having a 0.35 to 0.355 μm width wire, and sized 14�1.0 mm. [0043] The gold bumps 17 and 19 are formed to have the height of 10 μm in average, and it is sufficient if at least either of them is formed. The backs of the semiconductor chips 14 and 18 are ground to reduce the thicknesses thereof to 400 μm. On this account, the total thickness of the semiconductor device is not more than 1.1 mm, so as to be substantially equal to that of a TCP semiconductor device with one chip. The grinding of the backs, which is not always necessary, is done to make the chips thinner, and the thicknesses of the chips are preferably not less than 50 μm considering the possibility Of breakage of the chips and the handling thereof. [0044] The gold bump 16 of the semiconductor chip 14 is connected to the inner lead 12 c using an inner lead bonder. The gold bump 17 of the semiconductor chips 14 and the gold bump 19 of the semiconductor chip 18 are connected using a flip chip bonder, and the bonding condition thereof is, for instance, at a temperature of 500� C., for 2 seconds and under a pressure of 20 to 30 gf in each of the gold bumps 17 and 19. [0045] After the bonding, the gap between the semiconductor chips 14 and 18 is only around 20 μm, and an underfill resin is inserted therein. Then a liquid resin, for instance an amount of 30 mg, is potted, and in a cure furnace, for instance, the semiconductor device is pre-cured for around 20 minutes at a temperature of 125� C. and further post-cured for around three hours at the same temperature. When only either of the gold bumps 17 or 19 is formed as described above, the gap has only a 10 μm width and the viscosity of the underfill resin is as low as around 2Pa�S. [0046] This arrangement enables the gold bump 17 to be formed simultaneously with forming the gold bump 16 necessary for the ILB, and at the same time the terminal pitch is reduced as described above, since the relatively hard gold bumps 17 and 19 are less deformed than relatively soft solder bumps, when two semiconductor chips 14 and 18 of the semiconductor device using the TCP structure are stacked. [0047] In the arrangement above, the semiconductor chip 18 is provided to fit in a dent formed in the device hole 15. This dent is formed by pushing the inner lead 12 a into the device hole 15 when the semiconductor chip 14 is connected to the inner lead 12 c using the inner lead bonder. This arrangement can make the thickness of the whole semiconductor device thinner than a device in which the semiconductor chips 14 and 18 are simply stacked. [0048] In the arrangement above, the semiconductor chip 14 is a liquid crystal driver IC, and the semiconductor chip 18 is an SRAM (Static RAM) which is preferable to be provided in proximity to the liquid crystal driver IC due to its low power consumption, despite that the number of required components is greater than the number in the case of using DRAM (Dynamic RAM) etc. So even if two chips are used, the chips can be provided as thick as one chip by stacking them as above, and each of the chips can be manufactured in the most suitable process. [0049] Incidentally, although the whole semiconductor chip 18 is coated with the resin 20 in the example shown in FIG. 1, as FIG. 5 shows, it is possible to coat only the element surface thereof as in the semiconductor chip 14, to make the semiconductor device further thinner. [0050] Also, instead of using the underfill resin, it is possible to pot an NCP (Non Conductive Paste) 25 in an area of the semiconductor chip 14 on which the semiconductor chip 18 is mounted, and then connect the semiconductor 14 to the semiconductor chip 18 using the flip chip bonder, as FIG. 7 shows. In this case, the bonding condition is, for instance, at a temperature of 200� C. and for 2 seconds. The resin 20 made of, for instance, an epoxyresin is potted from the side of the semiconductor 18 so as to cover thereof, then the resin is pre-cured for around 20 minutes at a temperature of 125� C. and further post-cured for three hours at the same temperature. [0051] The following description will discuss a second embodiment in accordance with the present invention in reference to FIGS. 8 and 9. [0052]FIGS. 8 and 9 are cross-sectional view showing semiconductor devices of the second embodiment of the present invention. These semiconductor devices are similar to the aforementioned device so that members equivalent to the aforementioned ones have the same signs and the definitions are omitted. [0053] It is noted that in the semiconductor device shown in FIGS. 8 and 9, a semiconductor chip 31 mounted on a tape 13 by ILB is a liquid crystal driver IC for driving a segment electrode of a liquid crystal panel, and a semiconductor chip 32, which is a liquid crystal driver IC for driving a common electrode, is bonded on the semiconductor chip 31, and further a semiconductor chip 33, which is an SRAM, is bonded on the semiconductor chip 32. [0054] On this account, as in the case above, a gold bump 16 of the semiconductor chip 31 is connected to an inner lead 12 c by inner lead bonding, and then gold bumps 17 and 19 of the semiconductor chips 31 and 32 are connected with each other by flip chip bonding. Then the semiconductor chip 33 is pasted to the back surface of the semiconductor chip 32, since a dicing sheet 34 used when dicing, adhered to the back surface of the semiconductor chip 33 in advance, acts as an adhesive. Then via a gold wire 36, an unprotected aluminum pad 35 of the semiconductor chip 33 is bonded either to the inner lead 12 c as shown in FIG. 8 or to a copper wiring pattern 12 as shown in FIG. 9. [0055] When the gold wire 36 is bonded to the inner lead 12 c, as FIG. 8 shows, a gold ball 37 having a diameter around 100 μm is connected to the aluminum pad 35 in advance, using a bonding tool used for the gold wire 36. The gold wire 36 has a diameter of, for instance, 20 μm to 25 μm, and the wire 36 is bonded with the gold ball 37 after the gold ball 38 is bonded with the inner lead 12 c. This can prevent a leakage etc. due to the gold wire 36 coming into contact with the edge of the semiconductor chip 33. The semiconductor chip 32 is formed to be narrower than the semiconductor chip 31. On this account, it is possible to reduce interference between the bonding tool and the semiconductor chip 32 when the chip 32 is bonded to the inner lead 12 c as described above. [0056] In the meantime, as FIG. 9 shows, initially the gold ball 37 is formed on the aluminum pad 35 and then the gold wire 36 is bonded to the copper wiring pattern 12, when the gold wire 36 is bonded to the copper wiring pattern 12. In this case the copper wiring pattern 12 becomes thicker than the pattern 12 before the operation by an amount of around 110 μm because of the looped gold wire 36. [0057] The semiconductor chip 33 can be wire-bonded even if the same is bigger than the semiconductor chip 32 to an extent. This arrangement makes it possible to mount the semiconductor chips 31 to 33 having mutually different functions, without changing an amount of area required for mounting, so as to improve the yields of the semiconductor chips. [0058] The following description will discuss a third embodiment in accordance with the present invention in reference to FIGS. 10 and 11. [0059]FIGS. 10 and 11 are cross-sectional views showing semiconductor devices of the third embodiment of the present invention. These semiconductor devices are similar to the device shown in FIGS. 8 and 9 so that members equivalent to the aforementioned ones have the same sign and the definitions are omitted. [0060] It is noted that in the semiconductor device shown in FIGS. 10 and 11, a semiconductor chip 41, which is a controller IC, is further bonded on a semiconductor chip 33. [0061] Similarly to the semiconductor chip 33, by a dicing sheet 42, the back surface of the semiconductor chip 41 is, as shown in FIG. 10, bonded to an area on the semiconductor chip 33, which is surrounded by aluminum pads 35. The aluminum pad 43 is bonded with an inner lead 12 c via a gold wire 44. [0062] In the arrangement shown in FIG. 11, meanwhile, similarly to the semiconductor chip 32, the element surface of the semiconductor chip 41 faces the equivalent of the semiconductor chip 33, and gold bumps 45 and 46 of these two chips are connected by flip chip bonding. In this manner, the number of layered semiconductor devices can be further increased. [0063] As described above, a semiconductor device of the present invention includes: [0064] a tape carrier including: a wiring pattern formed on an organic base having an opening; and an inner lead which is a part of the wiring pattern jutting into the opening; [0065] a semiconductor chip (semiconductor chip 14) mounted on the tape carrier by fitting in the opening thereof and connecting a first electrode formed on a surface of the semiconductor chip for an electrode to the inner lead via a gold bump; and [0066] an electronic component (semiconductor chip 18) mounted on the tape carrier via the semiconductor chip, and including an electrode connected via a gold bump to a second electrode formed on the surface. [0067] On this account, the arrangement can meet the requirement to produce a finer liquid crystal panel. [0068] The semiconductor device of the present invention is preferably arranged so that another electronic component is stacked on the electronic component with back surfaces thereof facing each other, and an electrode of the upper electronic component is connected to the inner lead or the wiring pattern on the tape carrier by wire-bonding. [0069] In this case, the electrode of the upper electronic component is connected to the inner lead or the wiring pattern on the tape carrier by wire-bonding, to stack one or more electronic components on the two stacked electronic components. On this account, not less than three chips can be mounted. [0070] Moreover, the semiconductor device of the present invention is preferably arranged so that the electronic component is narrower than the semiconductor chip. [0071] On this account, it is possible to reduce interference between a bonding tool and the electronic component when not less than three chips are stacked and the electrode of the upper electronic component is connected to the inner lead by wire-bonding. [0072] Furthermore, the semiconductor device of the present invention is preferably arranged so that the semiconductor chip is a liquid crystal driver IC and the electronic component is an SRAM. [0073] On this account, the semiconductor device includes two chips, i.e. the liquid crystal driver IC and the SRAM (Static RAM) which is preferable to be provided in proximity to the liquid crystal driver IC due to its low power consumption, despite that the number of required components is greater than the number in the case of using DRAM (Dynamic RAM) etc., and each of the chips can be manufactured in the most suitable process. [0074] Moreover, the semiconductor device of the present invention is preferably connected to a liquid crystal panel so as to constitute a liquid crystal module. [0075] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art intended to be included within the scope of the following claims. Referenced byCiting PatentFiling datePublication dateApplicantTitleUS6791192 *Feb 21, 2003Sep 14, 2004Megic CorporationMultiple chips bonded to packaging structure with low noise and multiple selectable functionsUS7045901 *Feb 21, 2003May 16, 2006Megic CorporationChip-on-chip connection with second chip located in rectangular open window hole in printed circuit boardUS7224062 *Jun 8, 2005May 29, 2007Via Technologies, Inc.Chip package with embedded panel-shaped componentUS7450393Jun 30, 2004Nov 11, 2008Samsung Electronics Co., Ltd.Driver chip and display apparatus including the sameUS7557454 *Jul 15, 2005Jul 7, 2009Micron Technology, Inc.Assemblies with bond pads of two or more semiconductor devices electrically connected to the same surface of a plurality of leadsUS8258614 *Nov 12, 2007Sep 4, 2012Stats Chippac Ltd.Integrated circuit package system with package integrationUS8299631 *Jun 11, 2009Oct 30, 2012Sharp Kabushiki KaishaSemiconductor element and display device provided with the sameUS20090121335 *Nov 12, 2007May 14, 2009Zigmund Ramirez CamachoIntegrated circuit package system with package integrationUS20100102458 *Oct 28, 2008Apr 29, 2010Seng Guan ChowSemiconductor package system with cavity substrate and manufacturing method thereforUS20110193239 *Jun 11, 2009Aug 11, 2011Sharp Kabushiki KaishaSemiconductor element and display device provided with the sameWO2005067398A2 *Jun 11, 2004Jul 28, 2005Samsung Electronics Co LtdDriver chip and display apparatus* Cited by examinerClassifications U.S. Classification257/777, 257/E25.013, 257/E23.055International ClassificationH01L23/495, H01L25/18, H01L21/60, G09F9/00, G02F1/1345, H01L21/56, H01L25/065, H01L25/07, H01L23/12Cooperative ClassificationH01L2924/01078, H01L2225/06513, H01L2924/01002, H01L24/48, H01L2924/01013, H01L2224/48145, H01L25/0657, H01L2224/73265, H01L2224/48247, H01L24/73, H01L2224/85986, H01L2224/48479, H01L2924/20752, H01L2225/0651, H01L2224/48091, H01L2924/01004, H01L2224/48471, H01L24/45, H01L2224/45015, H01L2225/06579, H01L2924/014, H01L23/49572, H01L2224/45144, H01L2924/01033, H01L2224/49, H01L2224/16145, H01L2924/0105, H01L2224/85051, H01L2225/06582, H01L2924/01012, H01L2924/01006, H01L2924/01082, H01L2924/01029, H01L2924/01079, H01L2924/01322, H01L2224/48599, H01L24/49, H01L24/50, H01L2225/06506, H01L2224/32145European ClassificationH01L24/50, H01L24/48, H01L24/49, H01L24/73, H01L23/495J, H01L25/065SLegal EventsDateCodeEventDescriptionNov 28, 2014REMIMaintenance fee reminder mailedSep 22, 2010FPAYFee paymentYear of fee payment: 8Sep 29, 2006FPAYFee paymentYear of fee payment: 4Dec 20, 2001ASAssignmentOwner name: SHARP KABUSHIKI KAISHA, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TOYOSAWA, KENJI;REEL/FRAME:012395/0689Effective date: 20011203Owner name: SHARP KABUSHIKI KAISHA 22-22 NAGAIKE-CHO ABENO-KUOwner name: SHARP KABUSHIKI KAISHA 22-22 NAGAIKE-CHO ABENO-KUOFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TOYOSAWA, KENJI /AR;REEL/FRAME:012395/0689Owner name: SHARP KABUSHIKI KAISHA 22-22 NAGAIKE-CHO ABENO-KUFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TOYOSAWA, KENJI;REEL/FRAME:012395/0689Effective date: 20011203Owner name: SHARP KABUSHIKI KAISHA 22-22 NAGAIKE-CHO ABENO-KUOFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TOYOSAWA, KENJI /AR;REEL/FRAME:012395/0689Effective date: 20011203RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services