Source: http://www.google.com/patents/US7924626?dq=6,959,293
Timestamp: 2017-05-25 14:55:11
Document Index: 155041836

Matched Legal Cases: ['art 2', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093', 'Application No. 06000064', 'Application No. 06000093']

Patent US7924626 - Efficient erase algorithm for SONOS-type NAND flash - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of...http://www.google.com/patents/US7924626?utm_source=gb-gplus-sharePatent US7924626 - Efficient erase algorithm for SONOS-type NAND flashAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7924626 B2Publication typeGrantApplication numberUS 12/625,438Publication dateApr 12, 2011Filing dateNov 24, 2009Priority dateOct 18, 2007Fee statusPaidAlso published asCN101692350A, CN101692350B, US7643349, US20090103370, US20100067309Publication number12625438, 625438, US 7924626 B2, US 7924626B2, US-B2-7924626, US7924626 B2, US7924626B2InventorsHang-Ting LueOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (78), Non-Patent Citations (43), Classifications (6), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetEfficient erase algorithm for SONOS-type NAND flash
US 7924626 B2Abstract
a memory cell having a threshold voltage and comprising a substrate, a first dielectric structure overlying the substrate, a charge trapping structure overlying the first dielectric structure, a second dielectric structure overlying the charge trapping structure, and a gate overlying the second dielectric structure; and
a bias arrangement state machine to apply a bias arrangement to the memory cell to change the threshold voltage of the memory cell from a first threshold state to a second threshold state, the bias arrangement comprising:
a first voltage applied from the gate to the substrate to change the threshold voltage of the memory cell from the first threshold state; and
a second voltage applied from the gate to the substrate after the first voltage, to change the threshold voltage of the memory to the second threshold state, wherein the second voltage has a lower magnitude from the gate to the substrate than that of the first voltage.
2. The memory device of claim 1, wherein the bias arrangement comprises a voltage applied to the substrate being increased and a voltage applied to the gate being maintained between the first and second voltages.
3. The memory device of claim 1, wherein the bias arrangement comprises a voltage applied to the substrate being maintained and a voltage applied to the gate being reduced between the first and second voltages.
4. The memory device of claim 1, wherein the bias arrangement induces charge tunneling from the substrate to the charge trapping structure to reduce the threshold voltage of the memory cell.
5. The memory device of claim 1, wherein the bias arrangement induces charge tunneling from the gate to the charge trapping structure to reduce the threshold voltage of the memory cell.
6. The memory device of claim 1, wherein the first dielectric structure comprises:
a nitride layer on the first oxide layer; and
a second oxide layer on the nitride layer, wherein the charge trapping structure is on the second oxide layer.
7. The memory device of claim 1, wherein the second dielectric structure comprises:
a first oxide layer on the charge trapping structure;
a second oxide layer on the nitride layer, wherein the gate is on the second oxide layer.
a memory cell including a charge storage element; and
a bias arrangement state machine to apply a bias arrangement to the memory cell to change the charge storage element from a first charge storage state to a second charge storage state, the bias arrangement comprising:
a first voltage applied across the charge storage element to change the charge storage element from the first charge storage state to an intermediate charge storage state; and
a second voltage applied across the charge storage element to change the charge storage element from the intermediate charge storage state to the second charge storage state, wherein the second voltage has a lower magnitude across the charge storage element than that of the first voltage.
a bias arrangement state machine to apply a bias arrangement for adjusting the memory cell from a first storage state to a second storage state, the bias arrangement comprising a sequence of voltages, wherein a preceding voltage in the sequence of voltages has a larger magnitude than that of a subsequent voltage in the sequence of voltages. Description
This application is a continuation of copending U.S. patent application Ser. No. 12/052,276 filed 20 Mar. 2008; which application claims the benefit of U.S. Provisional Application 60/980,793, filed 18 Oct. 2007, entitled Efficient Erase Algorism for SONOS-Type NAND Flash, which applications are incorporated by reference herein.
V G=−(18.5−Step·0.5)Volts (1)
Erase Time=(1+1·Step)msec (2)
FIG. 11 is a simplified block diagram of an integrated circuit 1100 in which the present invention may be implemented. The integrated circuit 1100 includes a memory array 1112 implemented using dielectric charge trapping memory cells on a semiconductor substrate. A word line (or row) and block select decoder 1114 is coupled to, and in electrical communication with, a plurality 1116 of word lines and string select lines, and arranged along rows in the memory array 1112. A bit line (column) decoder and drivers 1118 are coupled to and in electrical communication with a plurality of bit lines 1120 arranged along columns in the memory array 1112 for reading data from, and writing data to, the memory cells in the memory array 1112. Addresses are supplied on bus 1122 to the word line decoder and drivers 1114 and to the bit line decoder 1118. Sense amplifiers and data-in structures in block 1124, including current sources for the read, program and erase modes, are coupled to the bit line decoder 1118 via the bus 1126. Data is supplied via the data-in line 1128 from input/output ports on the integrated circuit 1110, to the data-in structures in block 1124. In the illustrated embodiment, other circuitry 1130 is included on the integrated circuit 1100, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the memory cell array. Data is supplied via the data-out line 1132 from the sense amplifiers in block 1124 to input/output ports on the integrated circuit 1100, or to other data destinations internal or external to the integrated circuit 1100.
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