Source: http://www.google.com/patents/US5519546?dq=6106459
Timestamp: 2016-09-28 19:35:02
Document Index: 223857225

Matched Legal Cases: ['art 1', 'art 1', 'art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2']

Patent US5519546 - Apparatus for, and methods of, recording signals in tracks on a memory ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA head records a track (e.g. a servo track) in a memory member outside of a clean room without using reference indices. In each of a plurality of cyclical movements (e.g. revolutions), signals (e.g. servo signals) are recorded in the track in an individual number of frames. Thereafter the distance of...http://www.google.com/patents/US5519546?utm_source=gb-gplus-sharePatent US5519546 - Apparatus for, and methods of, recording signals in tracks on a memory member without using reference indices such as clock signalsAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS5519546 APublication typeGrantApplication numberUS 08/102,587Publication dateMay 21, 1996Filing dateAug 5, 1993Priority dateOct 12, 1990Fee statusPaidAlso published asUS5416652, WO1992007355A1Publication number08102587, 102587, US 5519546 A, US 5519546A, US-A-5519546, US5519546 A, US5519546AInventorsMartyn A. LewisOriginal AssigneeServo Track Writer CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Referenced by (27), Classifications (19), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetApparatus for, and methods of, recording signals in tracks on a memory member without using reference indices such as clock signals
US 5519546 AAbstract
A head records a track (e.g. a servo track) in a memory member outside of a clean room without using reference indices. In each of a plurality of cyclical movements (e.g. revolutions), signals (e.g. servo signals) are recorded in the track in an individual number of frames. Thereafter the distance of the unrecorded portion of the track is determined. In the next cyclical movement, the head records signals in an individual number of frames contiguous to the frames previously recorded, in a track distance dependent upon such individual number relative to the number of frames still unrecorded and upon the distance determined for the unrecorded track portion. In a last cyclical movement, the head records a single frame in a particular spatial relationship with the first and last frames. In a specific embodiment, 2N-K frames may be recorded in the K cyclical movement. Additional signals may thereafter be recorded by the head in tracks in a single cyclical movement. In another embodiment, each individual number of frames continue to be recorded in the first track in each cyclical movement until the frames occupy a distance, within particular limits, dependent upon the unrecorded length of the track and upon the individual number of frames relative to the number of frames still unrecorded. In a further embodiment, sectors and data sectors following the sectors are recorded with signals in progressive cyclical movements in a manner similar to the recording of the sectors in such revolutions in the first embodiment.
1. In a method of recording signals in a particular number of frames in a track on a memory member without the use of any prior reference index, including the following steps:(a) recording signals in half of the particular number of the frames in the track in a first operation, (b) determining the space in the track where signals have not yet been recorded, (c) recording signals in a second recording in a quarter of the particular number of frames in half of the space in the track where signals have not yet been recorded, (d) determining, after each successive recording of frames, the space in the track where signals have not yet been recorded, and (e) recording in each such successive recording signals in half of the number of frames recorded in the track in an immediately previous recording, such frames being recorded in each recording in half of the space in the track where signals have not yet been recorded. 2. In a method as set forth in claim 1, further including the following steps:determining that only a single frame is unrecorded, and when only the single frame is unrecorded, recording signals in such single frame in the remaining space where signals have not yet been recorded. 3. In a method as set forth in claim 1 whereinthe recording of signals in the frames in each operation is contiguous in the track to the recording of signals in the frames in the immediately previous recording. 4. In a method as set forth in claim 3 whereinthe track constitutes a first track and wherein successive tracks are provided in the memory member adjacent to the first track and wherein signals are recorded in each frame in the first track by a head and wherein the head is shifted in a direction relative to the memory member to record signals in the frames in the successive tracks on the memory member and wherein signals are recorded in the frames in each individual one of the successive tracks on the memory member in accordance with the recording of the signals in each frame in the track immediately previous to the individual track. 5. In a method as set forth in claim 4 whereinthe signals recorded in the frames in each individual one of the successive tracks are different from the signals recorded in the frames in the tracks adjacent to such individual tracks and wherein one of the signals in the frames in each individual track is used as a reference index to record the signals in the frames in the next one of the successive tracks. 6. In a method as set forth in claim 1 whereina reference signal is initially provided in the track and wherein the signals are recorded in the frames in the first recording at a particular position relative to the reference signal. 7. In a method of recording signals in a track on a memory member, including the steps of:recording signals in each of 2N-K frames in the track on the memory member in each of K successive recordings, N being any preselected positive number greater than 0 and K being any number between 0 and N, thereafter determining the distance of the track on the memory member after the K successive recordings where signals have not been recorded in the K successive recordings, and subsequently recording each of 2N-(K+1) frames with a distance for each of such frames in accordance with the determination of the distance of the track on the memory member after the K recording where signals have not been recorded on the track in the K successive recordings. 8. In a method as set forth in claim 7, further including the step of:recording a single frame with signals, in the recording after the K=N operation, in the distance in the track on the memory member where signals have not yet been recorded in the K=N recordings so that a particular spatial relationship exists between this single frame and the adjacent frames. 9. In a method as set forth in claim 8 further including the step of:disposing the signals in the first of the frames in the (K+1) recording in a particular spatial relationship with the signals in the last of the frames recorded with signals in the K recording by using as a reference a particular one of the signals in the frames recorded in the K recording. 10. In a method as set forth in claim 7, further including the step of:disposing the signals in the first of the frames recorded in the (K+1) recording in a particular spatial relationship with the signals recorded in the last of the frames in the K recording. 11. In a method of recording signals in a particular number of frames in a track on a memory member without the use of any prior reference indices, including the steps of:recording signals in each of a first number of frames less than the particular number in a first particular portion of the track substantially corresponding to the proportion between the first number and the particular number, thereafter determining the portion of the track where signals have not yet been recorded in the first recording, subsequently recording signals in each of a second number of frames, less than the particular number, in a second particular portion of the track where signals have not yet been recorded in the first recording, such second particular portion being dependent upon the portion of the track where signals have not yet been recorded in the first recording and being dependent upon the proportion between the second number and the number of unrecorded frames in the track where signals have not yet been recorded in the first recording, thereafter determining, after the recording of the first and second numbers of frames in the track, the portion of the track where signals have not yet been recorded in the first and second recordings, and subsequently recording signals in each of a third number of frames, less than the second particular number, in a third particular portion of the track where signals have not been recorded in the first and second recordings, such third particular portion being dependent upon the portion of the track where signals have not yet been recorded in the first and second recordings and being dependent upon the proportion between the third number of frames and the number of frames in the track where signals have not yet been recorded in the first and second recordings. 12. In a method as set forth in claim 11, further including the steps of:determining, after each recording of frames in the track, the portion of the track where signals still have not been recorded in the previous recordings, and recording, after each such determination, signals in each of an individual number of frames in a portion of the track where signals have still not been recorded in the previous recordings, such portion being dependent upon the portion of the track where signals have not been recorded in the previous recordings and being dependent upon the proportion between such individual number of frames and the number of frames where signals have still not been recorded in the previous recordings. 13. In a method as set forth in claim 12, further including the steps of:providing a reference signal, using this reference signal as a positioning index for locating the recording of signals in the first number of frames on the track, and erasing the reference signal before the recording of the signals in the first number of frames on the track. 14. In a method as set forth in claim 13 whereinthe signals recorded in the frames on the track in each recording are contiguous to the signals recorded on the frames in the track in the immediately previous recording and wherein a single frame is recorded in the last recording without any splicing between this frame and the adjacent frames previously recorded in the track. 15. In a method as set forth in claim 11, further including the steps of:providing a reference signal, and using this reference signal as a positioning index for locating the recording of the signals in the first number of frames in the track. 16. In a method of recording signals in a particular number of frames in a track on a cyclically movable memory member without the use of any prior reference index, including the steps of:recording signals in a first number of frames in the track on the memory member in successive cyclical movements of the memory member until the first number of frames occupies a first particular length within first particular limits relative to the length of the first frames on the track, the first particular length being dependent upon the first number of frames relative to the particular number of frames and being dependent upon the length traversed by the track in each cyclical movement of the track, thereafter determining the length of the track where signals have not yet been recorded in the first number of frames in the track after the recording of the first number of frames, subsequently recording signals in a second number of frames in the track on the memory member in successive cyclical movements of the memory member until the second number of frames occupies a second particular length of the track within second particular limits relative to the unrecorded length of the track, the second particular length being dependent upon the second number of frames and the number of frames where signals have not been recorded in the first recording on the track and being dependent upon the length of the track where signals have not been recorded in the first recording on the track, thereafter determining the length of the track where signals have not yet been recorded in the first and second recordings in the track, and subsequently recording signals in a third number of frames in a length of the track on the memory member in successive cyclical movements of the track where signals have not been recorded in the first and second recordings and until the third number of frames occupies a third particular length of the track within third particular limits relative to the unrecorded length of the track, the third particular length being dependent upon the third number of frames and the number of frames where signals have not been recorded in the first and second recordings on the track and being dependent upon the portion of the track where signals have not yet been recorded in the first and second recordings on the track. 17. In a method as set forth in claim 16 whereinsignals are recorded in an individual number of frames in the track in each of a plurality of successive recordings in the track until the individual number of frames occupies an individual length of the track within individual limits relative to the unrecorded length of the track, the individual number of frames in the track in each successive recording being disposed in the length of the track not having any previous recordings and being dependent upon the individual number of frames and the number of frames where signals have not been recorded in the previous recordings on the track and being dependent upon the length of the track where signals have not been recorded in the previous recordings on the track, and determining the length of the track where signals have not yet been recorded after the signals have been recorded in the individual number of frames in the immediately previous cyclical movement of the memory member. 18. In a method as set forth in claim 17 whereinthe signals in each recording of the frames in the track are contiguous to the signals in the frames previously recorded in the track and wherein the signals are recorded in a single frame in the track, in a last cyclical movement of the memory member, in contiguous relationship to the signals in the first and last frames previously recorded in the track. 19. In a method as set forth in claim 16 whereina reference signal is initially recorded in the track and is subsequently erased and wherein the signals are recorded in the first number of frames in the track from a particular position relative to the location of the erased reference signal in the track and wherein the signals in the second number of frames are recorded in the track in contiguous relationship to the signals in the first number of frames in the track and the signals in the third number of frames are recorded in the track in contiguous relationship to the signals in the second number of frames in the track. 20. In a method of recording signals in a particular number of frames in a plurality of tracks on a cyclically movable memory member without the use of any reference indices, including the steps of:using a single head to record signals in each of an individual number of frames in a first one of the tracks on the memory member in each of a plurality of successive cyclical movements of the memory member, the portion of the first track recording the individual number of frames in each successive cyclical movement of the memory member being dependent upon the individual number of frames and the number of frames where the frames have still not yet been recorded in the first track in the previous cyclical movements of the memory member and also being dependent upon the portion of the first track where signals have still not yet been recorded in the previous cyclical movements of the memory member, and using the single head and the signals in the frames in the first track to record signals in each of the particular number of frames in a second track adjacent to the first track. 21. In a method as set forth in claim 20 whereina single frame is recorded in the first track on the memory member in the last one of the successive cyclical movements of the memory member for the recording of signals in the first track on the memory member and wherein the single frame is recorded with a particular spatial relationship between the first and last frames previously recorded in the first track and wherein the signals recorded in the individual number of frames in the first track on the memory member in each successive cyclical movement of the memory member is less than the individual number of frames recorded in the first track on the memory member in the immediately previous one of the successive cyclical movements of the memory member. 22. In a method of recording signals in a plurality of identifying sectors in a track on a memory member and in data sectors following the identifying sectors, including the steps of:recording signals in a first particular number of the identifying sectors and in the data sectors following the first particular number of identifying sectors, thereafter determining the portion of the track after such recording where signals have not yet been recorded in the first particular number of the identifying sectors and the following data sectors, and subsequently recording signals in a second particular number of the identifying sectors and the following data sectors, the second particular number of the identifying sectors and the following data sectors being recorded in a portion of the track dependent upon the second particular number of identifying sectors and the number of identifying sectors where signals have not yet been recorded in the previous recording and being dependent upon the portion of the track where signals have not yet been recorded in the track in the first recording. 23. In a method as set forth in claim 22, further including the steps of:determining, in each of a plurality of successive cyclical movements of the memory member, the portion of the track where signals have not yet been recorded in the previous recordings, and recording after each such determination signals in an individual number of the identifying sectors and the following data sectors in the portion of the track where signals have not yet been recorded in the previous cyclical recordings, the individual number of the identifying sectors and the following data sectors being recorded in a portion of the track dependent upon the determination of the portion of the track where signals have not yet been recorded in the previous and being dependent upon the individual number of the identifying sectors and the number of the identifying sectors where signals have not yet been recorded in the previous recordings. 24. In a method as set forth in claim 23 whereineach of the identifying sectors in the track includes a plurality of cells having signals recorded in a first pattern and further includes a plurality of signals recorded at a particular frequency at an individual position in the identifying sector and wherein a gap is provided between a first one of the identifying sectors and the last data sector in the track to provide a reference index in the track. 25. In a method as set forth in claim 22 whereinthe second particular number of the identifying sectors and the following data sectors are recorded in contiguous relationship to the first particular number of the identifying sectors and the following data sectors and wherein signals are recorded in the identifying sectors and the following data sectors of a second track contiguous to the first track after the recording of the signals in all of the identifying sectors and data sectors in the first track. 26. In a method of recording signals in a plurality of identifying sectors in a track on a memory member and in data sectors following the identifying sectors, including the steps of:(a) recording signals in half of the identifying sectors in the track and the following data sectors in the track in a first recording, (b) determining the portion of the track where signals have not been recorded, (c) recording signals in a quarter of the identifying sectors in the track and the following data sectors in half of the portion of the track where signals have not been recorded in step (a), (d) determining, after each successive cycle of recording signals in identifying sectors and the following data sectors, the portion of the track where signals have not been recorded in the previous recording steps, and (e) recording in each successive recording signals in half of the number of identifying sectors and the following data sectors where signals have not been previously recorded, such signals being recorded in each recording in substantially half of the portion of the track where signals have not been recorded in the previous recording steps. 27. In a method as set forth in claim 26 whereinthe signals are recorded in each successive recording in contiguous relationship to the signals recorded in the immediately previous recording. 28. In a method as set forth in claim 27 whereinthe track constitutes a first track and wherein successive tracks are disposed on the memory member adjacent to the first track and to one another and wherein signals are recorded in identifying sectors and following data sectors in each of the successive tracks in a single cyclical movement of the memory member and wherein the signals recorded in each track have a pattern different from the pattern of signals recorded in the adjacent tracks. 29. In a method as set forth in claim 28 whereinthe signals are recorded in each successive track in contiguous relationship to one another and wherein a particular relationship is provided between the signals in a first one of the identifying sectors in each track and the last one of the data sectors in that track to define an indexing position for the track. 30. In combination for recording signals in frames in a track on a memory member, includingmeans for recording signals in 2N-1 frames in the track, N being any preselected positive number greater than 0, means for determining the portion of the track after the recording of the 2N-1 frames in the track where signals have not yet been recorded in the track, and means for recording signals in 2N-2 frames in a particular portion of the track where signals have not yet been previously recorded in the 2N-1 recording, such particular portion being dependent upon the portion of the track where signals have not yet been recorded in the 2N-1 recording and being disposed in contiguous relationship to the 2N-1 frames previously recorded in the track. 31. In a combination as set forth in claim 30, further includingmeans for determining the portion of the track after each recording of frames in the track where signals have not yet been recorded in the previous recordings in the track, means for recording signals in 2N-K frames in a particular portion of the track where signals have not yet been previously recorded in the previous recordings, the particular portion being dependent upon the portion of the track where signals have not yet recorded in the previous recordings and being disposed in contiguous relationship to the 2N-(K+1) frames previously recorded in the track, and K being any number between 0 and N. 32. In a combination as set forth in claim 31, further includingmeans for recording signals in an individual pattern in the track to establish a reference index for the frames in the track. 33. In a combination as set forth in claim 31, further includingthird means for providing signals in a first pattern in a plurality of frames in the first track to provide a reference index for the successive cyclical movements of the memory member, fourth means for obtaining a recording by the first means of the signals in the first pattern in the first track in the plurality of successive cyclical movements of the memory member, and fifth means responsive to the signals in the first pattern in the first track for obtaining a recording by the second means of signals in a second pattern in the second track in the single cyclical movement of the memory member. 34. In a combination as set forth in claim 33, futher includingthe fifth means including means responsive to individual ones of the signals in the frames in the first track for obtaining the recording by the second means of the signals in the second pattern in the frames in the second track and further including means for eliminating, from the recordings in the frames in the second track, any unwanted vestiges of the patterns of the signals in the frames in the first track. 35. In a combination as set forth in claim 32, further includingthe track constituting a first track, and means for recording signals in frames in a second track adjacent to the first track in accordance with the positioning of the frames in the first track. 36. In combination for recording signals in at least first and second adjacent tracks on a memory member, includingfirst means for sequentially recording signals in progressive portions of the first track dependent upon the portion of the first track, before each such recording, where signals have not been recorded on the first track in the previous sequential recordings and also dependent upon the number of frames in each such sequential recording and the number of frames to be recorded in subsequent sequential recordings in the first track, and second means for subsequently recording signals in frames in the second track at positions related to the positions of the frames previously recorded in the first track in the sequential recordings. 37. In a combination as set forth in claim 36, further includingmeans for moving the memory member cyclically, the first means being operative in a plurality of cyclical movements of the memory member to record the signals sequentially in the frames in the first track in the successive cyclical movements, and the second means being operative in a single cyclical movement of the memory member to record the signals in the frames in the second track after the recording of the signals in the frames in the first track in the successive cyclical movements of the memory member. 38. In a combination as set forth in claim 36, further includinga single head, the first means including the single head, and the second means including the single head, the first means being operative to record signals in a number of frames in each sequential recording less than the number of frames recorded with signals in the previous sequential recordings. 39. In combination for recording signals in a plurality of frames in a track on a memory member, including,first means for obtaining cyclical movements of the memory member, second means for recording signals in a first particular number of frames in the track in the memory member until the frames occupy a first particular portion, within first particular limits, of the length of the track, the first particular portion being dependent upon the first particular number and the number constituting the plurality of frames and being less than the number of the frames in the plurality, and third means for thereafter obtaining a recording by the second means of signals in a second particular number of additional frames, in a portion of the track in the memory member where signals have not been previously recorded in such track by the second means, until such additional frames occupy a second particular portion, within second particular limits, of the length of the track, the second particular portion being dependent upon the second particular number and the number of frames in the track where signals have not been recorded by the second means and being dependent upon the portion of the track where signals have not been previously recorded by the second means. 40. In a combination as set forth in claim 39, further includingfourth means for determining the portion in the track in the memory member, after the recording of signals by the second means, where signals have not been recorded, the second particular portion being dependent upon the portion of the track determined by the fourth means. 41. In combination for recording signals in a plurality of frames in a track on a memory member, includingfirst means for obtaining cyclical movements of the memory member, second means for recording signals in a first particular number of frames in the track in the memory member until the frames occupy a first particular portion, within first particular limits, of the length of the track, the first particular portion being dependent upon the first particular number and the number constituting the plurality of frames, and third means for thereafter obtaining a recording by the second means of signals in a second particular number of frames, in a portion of the track in the memory member where signals have not been previously recorded in such track by the second means, until such frames occupy a second particular portion, within second particular limits, of the length of the track, the second particular portion being dependent upon the second particular number and the number of frames in the track where signals have not been recorded by the second means and being dependent upon the portion of the track where signals have not been previously recorded by the second means, the third means including means for determining, after each recording of signals in frames in the memory member by the second means, the portion of the track in the memory member where signals have not been recorded by the second means, and fourth means for obtaining a recording by the second means of signals in an individual number of frames in the track in the memory member until such frames occupy a portion of the track, within limits dependent upon the portion of the length of the track where signals have not yet been recorded by the second means, dependent upon the individual number and the number of frames in the track where signals have not yet been recorded by the second means. 42. In a combination as set forth in claim 41, further includingmeans for providing a reference index in the track to identify the frames in the track, the track constituting a first track and there being in the memory member a second track adjacent to the first track and there being frames in the second track, and means responsive to the recording of signals in the frames in the first track for recording signals in the second track in a single cyclical movement of the memory member. 43. In a combination as set forth in claim 41, further includingthe track constituting a first track and there being in the memory member a second track adjacent to the first track and the signals in the first track being recorded in a first pattern, and means responsive to the recording of the signals in the frames in the first track in the first pattern for recording signals in the second track in a single cyclical movement of the memory member and in time coincidence with the frames in the first track and in a second pattern different than the first pattern of the signals recorded in the first track. 44. In a combination as set forth in claim 43, further includingmeans for eliminating, after the recording of the signals in the second pattern in the second track, any unwanted vestige of signals recorded in the second track from the first pattern in the first track. 45. In combination for recording signals in a track on a memory member, the track including identifying sectors and data sectors following the identifying sectors, includingfirst means for recording signals in a first particular number of the identifying sectors and the data sectors following the identifying sectors, second means for determining the portion of the track where signals have not been recorded by the first means, and third means for thereafter obtaining recording signals in a second particular number of identifying sectors and data sectors in a particular portion of the track where signals have not been previously recorded, the particular portion being dependent upon the portion of the track where signals have not been previously recorded and being dependent upon the second particular number and the number of identifying sectors and data sectors in the track where signals have not been previously recorded, the second particular number of identifying sectors and data sectors being in addition to the first particular number of identifying sectors and data sectors. 46. In combination for recording signals in a track on a memory member, the track including identifying sectors and data sectors following the identifying sectors, includingfirst means for recording signals in a first particular number of the identifying sectors and the data sectors following the identifying sectors, second means for determining the portion of the track where signals have not been recorded by the first means, and third means for thereafter obtaining recording signals in a second particular number of identifying sectors and data sectors in a particular portion of the track where signals have not been previously recorded, the particular portion being dependent upon the portion of the track where signals have not been previously recorded and being dependent upon the second particular number and the number of identifying sectors and data sectors in the track where signals have not been previously recorded, fourth means for moving the memory member cyclically, fifth means including the second means, the fifth means being operative in progressive cyclical movements of the memory member for determining the portion of the track in the memory member where signals have not been previously recorded, and sixth means operative in progressive cyclical movements of the memory member, after the determination by the fifth means in the previous cyclical movements of the memory member, for recording signals in an individual number of identifying sectors and data sectors in progressive portions of the track where signals have not previously been recorded in the previous cyclical movements of the memory member, the progressive portions being dependent upon the portion of the track where signals have not been previously recorded in the previous cyclical movements of the memory member and being dependent upon the individual number and the number of the identifying sectors and data sectors in the track where signals have not been previously recorded in the previous cyclical movements of the memory member. 47. In a combination as set forth in claim 46, further includingmeans for providing signals in the track in an individual pattern to provide a reference index for identifying the cyclical movements of the memory member and for identifying the identifying sectors and data sectors in the track. 48. In a combination as set forth in claim 46, further includingthe track constituting a first track and there being a second track in the memory member adjacent to the first track and there being identifying sectors and data sectors in the second track, and means operative upon the recording of signals in the identifying sectors and the data sectors in the first track for recording signals in the identifying sectors and data sectors in the second track, the signals being recorded in a first individual pattern in the identifying sectors and data sectors in the first track and being recorded in the identifying sectors and data sectors in the second track in a second individual pattern different from the first individual pattern. 49. In combination for recording signals in a particular number of frames in a track on a memory member, including,transducer means for recording signals in the track on the memory member and for reading the signals recorded in the track on the memory member, means for obtaining a recording by the transducer means of a pattern of signals in each of a first particular number of frames in a first portion of the track on the memory member, means including the transducer means for determining the portion of the track on the memory member where signals have not been recorded by the transducer means in the previous recording, means for obtaining a recording by the transducer means of signals in a second particular number of frames in a particular portion of the track on the memory member where signals have not been recorded by the transducer means in the previous recording, the particular portion of the track being dependent upon the portion of the track where signals have not been recorded by the transducer means in the previous recording and also being dependent upon the second particular number relative to the number of frames in the track where signals have not been recorded by the transducer means in the previous recording, the second particular number of frames being in addition to the first particular number of frames. 50. In combination for recording signals in a particular number of frames in a track on a memory member, including,transducer means for recording signals in the track on the memory member and for reading the signals recorded in the track on the memory member, means for obtaining a recording by the transducer means of a pattern of signals in each of a first particular number of frames in a first portion of the track on the memory member, means including the transducer means for determining the portion of the track on the memory member where signals have not been recorded by the transducer means in the previous recording, means for obtaining a recording by the transducer means of signals in a second particular number of frames in a particular portion of the track on the memory member where signals have not been recorded by the transducer means in the previous recording, the particular portion of the track being dependent upon the portion of the track where signals have not been recorded by the transducer means in the previous recording and also being dependent upon the second particular number relative to the number of frames in the track where signals have not been recorded by the transducer means in the previous recording, means including the transducer means for determining the portion of the track, after each recording of signals in frames in the track by the transducer means, where signals have not been recorded by the transducer means in the previous recordings, and means for obtaining a recording of an individual number of frames by the transducer means in an individual portion of the track where signals have not been previously recorded by the transducer means in previous recordings, such individual number of frames being recorded, after each determination of the portion of the track where signals have not been recorded by the transducer means in the previous recordings, the individual portion of the track being dependent upon the portion of the track where signals have not been recorded by the transducer means in the previous recordings and also being dependent upon the individual number of frames relative to the number of frames where signals have not been previously recorded by the transducer means in the previous recordings. 51. In a combination as set forth in claim 50, further includingthe individual number of frames in each successive recording being less than the number of frames recorded by the transducer means in the track in the previous recording, a single frame being recorded by the transducer means in the track in the last cycle of recording. 52. In a combination as set forth in claim 50, further includingthe track constituting a first track and there being a second track on the memory member in adjacent relationship to the first track and there being a number of frames in the second track corresponding to the number of frames in the first track, the frames in the second track having a positioning corresponding to the positioning of the frames in the first track, the transducer means constituting a single head, and means for obtaining a recording by the single head of signals in a single revolution in the frames in the second track, corresponding to the number of frames in the first track and having a position in the second track corresponding to the positioning of the frames in the first track, the signals recorded in each of the frames in the second track being different from the signals recorded in the frames in the first track. Description
This is a continuation of application Ser. No. 07/596,722 filed Oct. 12, 1990 now abandoned.
A clock track is written with the clock head using a trial and error process. The clock track is preferably "splice free". Usually a tolerance of some �30 nanoseconds discontinuity is allowed at the splice point. Since spindle motor speed variations are usually �0.05% and the nominal revolution period is 16.67 milliseconds, the period of one revolution varies by about �8 microseconds. An index available from the motor or from a "scratch" transition pair written with the head is used to drive a phase lock loop (PLL) which multiplies this approximately 60 Hz clock to a much higher frequency. A successful clock is written only when the correct number of the said high frequency clocks has elapsed between successive indices and the time discrepancy of the last clock time is less than 30 nanoseconds. This process takes up to a minute because of the large discrepancy between the splice error permitted and the spindle speed tolerance. The invention avoids the use of a clock head and also avoids the need for a clock track. The clock track is replaced by a "Master Track" which is written in about 20 revolutions or 0.33 seconds.
Various methods are described, one of which can write this first track in as little as 20 revolutions. Other methods take longer (up to 150 revolutions) but achieve greater accuracy. The head is then moved a distance approximately one half of the head width. This distance will either be equal to the desired data track pitch or one half of the desired data track pitch. Now, by multiplexing between reading the vestige of a preceding track and writing the present track, the present track may be made phase synchronous with the first track. While still located at the present track, a further revolution is used selectively to erase the vestige of the unwanted transitions of the prior track. This process continues until all tracks are written.
One such positioning means is disclosed and claimed in a patent application filed by Robert Hazel, Gajus Michelson and William Valliant on Oct. 12, 1990, for a system for positioning a head arcuately relative to a memory member such as a disc. Another such means is provided by units manufactured and used by International Business Machines (IBM), which extends the shaft for moving the head arcuately relative to the disc so that the shaft extends outside of the head disc assembly, and an optical encoder is temporarily attached to the shaft for the purpose of servo track writing.
FIG. 3A is a detailed block diagram of a system constituting one embodiment of this invention for using a single head to record a track on a memory member such as a disc outside of a clean room in a plurality of revolutions of the memory member without the use of reference indices such as clock signals;
FIG. 4 is a flow chart of the steps included in a method of this invention of using a single head to record a track on a memory member such as a disc;
FIG. 5 constitutes time charts illustrating the relative times at which signals are recorded in a particular pattern in the track in successive revolutions of the track and in which signals recorded in the track are read from the track;
FIGS. 6(a)-6(b) constitute time charts illustrating how the signals are recorded on a trial basis in a particular pattern in one frame of the track, after the recording of the particular pattern in a particular portion (such as half) of the track, to determine the corrections which have to be made in the timing of the signals before the particular pattern of the signals is recorded in the remainder of the track;
FIGS. 7(a)-7(b) constitute a time chart illustrating how signals are recorded on a trial basis in a frame in a second track adjacent to the first track, after the recording of the signals in the complete periphery of the first track, to determine the corrections which have to be made in the timing of the signals in the second track before signals are recorded in the second track with the desired timing;
FIGS. 8(a)-8(b) constitute a time chart illustrating how the signals are recorded in a frame in the second track in a single revolution of the track after the proper corrections have been made in the timing of such signals in accordance with the time chart shown in FIG. 7, the pattern of the signals in the second track being different from the pattern of the signals in the first track;
FIGS. 9(a)-9(b) constitutes a time chart illustrating how the signals recorded in accordance with the timing chart shown in FIG. 8 are modified to eliminate signals which are recorded from the first track but which are not desired in the second track;
FIGS. 10(a)-10(b) constitute a time chart illustrating how signals are recorded in a frame in a third track in a single revolution of the track after the signals have been recorded in the second track, the pattern of the signals recorded in each frame in the third track being different from the patterns of the signals recorded in each frame in the first and second tracks;
FIGS. 11(a)-11(b) constitute a time chart illustrating how the signals recorded in accordance with the timing chart shown in FIG. 9 are modified to eliminate signals which are recorded from the second track but which are not desired in the third track;
FIGS. 13(a)-13(c) constitute a chart illustrating the sequence of operation of the system shown in FIGS. 1-12 in recording signals in the different frames in a first track in a plurality of successive cyclical movements of a memory such as a disc;
FIGS. 14(a)-14(b) constitute a chart illustrating the sequence of operation of the system shown in FIGS. 1-13 in recording signals in the different frames in second through fifth tracks adjacent to the first track in successive cyclical movements of the memory member after the recording of signals in the frames in the first track on the memory member;
FIGS. 15(a)-15(b) are schematic diagrams illustrating the patterns of signals in a sector in each of a plurality of contiguous tracks which are used in the second embodiment of the invention; and
Transition 1:) Data Transitions,SD
Transition 2:)
Transition 3:) Sync Transitions,SS
Transition 4:)
Transition 5:) Position Transitions,N+ or N-
Transition 6:)
Transition 7:) Position Transitions,Q+ or Q-
Transition 8:)
The head usually decodes index, outer zone, and inner zone patterns even as the head moves between tracks. Therefore, corresponding transitions on adjacent tracks should be well aligned.
An example of transition timing (in nanoseconds) for normal frames of A,B,C,D tracks is tabulated below:
______________________________________Transition #       A       B         C     D______________________________________1             0       0         0     02            500     500       500   5003           1000    1000      1000  10004           1500    1500      1500  15005           4000    4000      7000  70006           4500    4500      7500  75007           13000   10000     10000 130008           13500   10500     10500 13500______________________________________
When a disc whose magnetic layer (the medium) is magnetized in a positive direction is exposed to a positive direction magnetic field greater than the coercive force of the disk coating, the direction of the disk magnetization is changed to the negative direction after removal of the external field. A magnetic head typically consists of a ring of soft iron with a gap. Windings are threaded through the ring. Current in the windings induces a magnetic field across the gap. When the gap is small and is close to the magnetic disk it can create a highly localized field. If a head with no gap field is placed near a spinning medium of +magnetization, no change is induced in the medium. If a negative field is induced across the head gap by passing an appropriate polarity current through the head there is still no change in the state of the medium. Only a gap field of like direction to the medium magnetization, i.e. positive in this example, changes the state of magnetization in the medium. Collapsing this gap field to zero, either by reducing he head current to zero, or by removing the medium from the vicinity of the gap field leaves the affected region of the medium in the changed state.
A wide variety of integrated circuits (chips) are available which can be controlled to introduce either positive, negative, or zero current into the head windings. These chips can operate in at least 2 modes: Write, and Read. It is not possible to read and write simultaneously. The circuits are mounted very close to the heads. At any given time, the circuits can address only one of a number of heads. The magnitude of the write current, Iw, can be programmed by means external to the chip. The chip delivers a bipolar current of value Iw or -Iw in response to Write Data transitions fed to the chip. An example of such a chip for use with ferrite heads is manufactured by Silicon Systems Inc., Tustin, Calif. with Part Number 32R566R. For thin film heads, part number 32H523R, and also by Silicon Systems may be used. It is desirable to use this chip to write tracks since it is already mounted in the disc drive assembly at the time writing is to commence. The invention can deal with either kind of chip.
In view of the fact that the recorded transitions depend on the prior magnetic state of the medium, it is desirable that the medium be in an erased state prior to writing data. There are 3 possible erased states: (a) with the entire medium magnetized in a clockwise direction around the track (b) the medium magnetized in a counter clockwise around a track or, (c) with the medium entirely demagnetized. By the following sequence an erase condition with the medium magnetized either Clockwise (CW) or Counter Clockwise (CCW) will be created:
To write, the Write Mode is selected by asserting 14 Write Gate. At a predetermined time, tf, after assertion of Write Gate, High to Low write data transitions may be fed to the chip. The time tf is made larger than the worst case expected value of Read to Write recovery time, trw. The chip contains a flip flop which changes state on each High to Low write data transition. At each change of state the flip flop in the chip changes the polarity of the current delivered to the head. Transitions can be read back by selection of the Read Mode. This is done by asserting Read Gate. The play back signal from an isolated recorded transition is approximately Lorentzian in shape (resembling somewhat a triangle with blended vertices) and has a pulse width, PW50, at the 50% of peak amplitude level which is related to head gap dimensions, flying height, write current magnitude, write current polarity, write current rise time, previous magnetization state of the magnetic medium, coercivity of the medium etc. The peak amplitude is also related to the same factors in a complicated way. A discussion of these factors is given in a tutorial paper entitled "Fundamentals Of The Magnetic Recording Process" by H. Neal Bertram, published Proceedings of the IEEE, November 1986, pp 1494 to 1512.
FIG. 2 depicts a typical write sequence. When Write Gate is asserted, after a delay, trw, the write current will change from 0 to some value Iw. The Write Data Flip Flop inside the 32H566R (or 32H523R) is initialized on power on, with the disc stationary, by keeping the Write Data input low while commanding a read mode (i.e. WRITE GATE low). This will then cause current to flow through the X-side of the head on the first high to low WRITE DATA transition. The actual polarity is determined by the design of the chip. In all future write operations, the WRITE DATA signal is kept low when the previous read mode was commanded. This is in accordance with the specification for 32H566R and results in the same write current polarity on each assertion of WRITE GATE. This polarity is arbitrarily designated as positive. The magnitude of the current is set by means external to the chip. The rise time of the current in the head is quite rapid. The first High to Low Write Data transition after Write Gate is asserted will, after a delay tw1, change the head current from Iw to -Iw since the chip delivers alternate symmetrical bipolar current levels to the head. On receipt of the next High to Low write data transition, after a short delay, tw2, the write current in the head changes from -Iw back to Iw. Delays tw1 and tw2 are almost identical, and assumed to be equal to tw. The closer these write data transitions are, the lower the amplitude of the signal on playback. When Read Gate is asserted, the write current returns, after a short delay, to zero. This change in current is quite rapid. These delay times will vary from sample to sample of chip, head and connecting cable. FIG. 2 also depicts the state of medium magnetization after experiencing this sequence of Write currents, and the read back signal which results. Note that the only changes in state of magnetization occur at the Write Data transitions. The current which flows when Write Gate is asserted has no effect on the medium since the medium was erased with the same polarity of write current which exists when Write Gate is first asserted. In addition, removal of the write current has an insignificant effect on the medium.
FIGS. 3A and 3B are block diagrams of the apparatus proposed for the invention. FIG. 3B shows how a multiplicity of HDA's are connected to corresponding electronic units (EU's) and to one system control unit (SCU). FIG. 3A is a detailed block diagram depicting only one EU and one HDA.
(a) An IBM Compatible Personal Computer (PC), 8, which is made up of a central processing unit (CPU) (preferably of the 80386 type manufactured by INTEL Corporation, Santa Clara, Calif.), 1 or more Megabytes of Random Access Memory, (RAM) a floppy disk drive of at least 1.2M Byte capacity, a display unit, and a printer. The lines from the computer include an IEEE 488 bus for instrument control, a general purpose 16 bit bus, Direct Memory Access (DMA) Bus, and miscellaneous control lines.
(b) A latchable Multiplexor (MUX), 7, which is controlled by the PC, 8, to develop an output "TRIGGER WORD" from one of three sources: the END COUNT of the Read Counter, 3, the output of the Presettable and Programmable Divider, 1, or a STIMULUS from the PC itself.
(g) An SCU State Machine, 2, which takes as inputs the signals READ DATA and SDW (Windowed READ DATA) from the EU, 36, and signals RECNT and WECNT from Down Counter, 3 and WRITE GATE and CLOCK IN from Pattern Generator, 6, and an advance spindle reference pulse, ASPR, from the Divider, 1, such that ASPR precedes the SPINDLE REFERENCE pulse by slightly more than the worst case jitter of the Spindle Phase Lock. The mode of the State Machine is controlled by the PC using the MODE signal input. The outputs of the State Machine are signals to the A and B inputs of the Timer, 4; a reset signal, ERESET, which resets the REV. COUNTER, 9 and the EU State Machine, 16, in the EU; spindle feedback pulses (labelled "SPDL FDBK PULSES") which are fed to the IX MUX, 21 in the EU; a TC INCR signal which is fed to the MUX, 7; an SVCK pulse used to increment the SVDCP counter, 40; and RCLK and WCLK signals which are used to decrement the Read and Write Counters respectively. Preferably, the SCU State Machine is designed using one or more Field Programmable Logic Arrays (FPGA's). As an example, a state machine with a 20 MHz clock rate can be achieved using the Xilinx 2020 manufactured by Xilinx, Inc., San Jose, Calif. Even higher clock rates--up to 70 MHz--are attainable with part # Act-2 from Actel Corp., Sunnyvale, Calif. For details, refer to an article in Electronic Engineering Times, Sep. 17, 1990, pp 45 and 48. It may even be possible to contemplate a Digital Signal Processor (DSP), such as part number TMS320C30 manufactured by Texas Instruments, Dallas, Tex. for use as a State Machine if the Pattern is not demanding.
(j) A Trigger Decoder, 39, which decodes the Trigger Counter state into TRIGGER WORDS which initiate the output of various pattern segments from the Pattern Generator, 6. The Trigger Decoder is programmed with a sequence of TRIGGER WORDS by the PC via the line TPGM. The Decoder is preferably a Random Access Memory whose address is provided by the Trigger Counter States and whose contents are determined by the desired sequence of Trigger Words which initiate various patterns from the Pattern Generator.
(p) A latchable multiplexor, PC MUX, 46, which allows the PC to have direct control over the WRITE DATA, WRITE GATE, READ WINDOW, and CLOCK IN lines. The state of the MUX is selected by the PC via the line MUXSLCT and can be set either to pass the 4 signals, PG STIM, directly from the PC or from PG MUX (3 lines) and the bi-directional monostable, MS, (1 line WRITE DATA).
(c) A Data PLL, 13, which is a phase lock loop whose operating data rate can be set by the microcontroller via the lines "PROGRAM DATA RATE". The input to the PLL is the "SDW" Line. The PLL is programmed in loop acquisition mode by the "ACQUIRE" line from the microcontroller. The output of the PLL is the clock on line "SCLK". Once in lock the loop remains in lock so long as the incoming SDW line has transitions near the clock transitions of SCLK. The general principles of operation of such a PLL are described in detail in the description of the model 8459 integrated circuit data separator manufactured by National Semiconductor Corp. of Santa Clara, Calif. This description may be found in the "Mass Storage Handbook", published in 1989 by National Semiconductor, on pages 2-29 through 2-63, and 2-163 through 2-173. The operation of the data PLL proposed in this apparatus will differ only in some details from the operation of the 8459 chip.
(e) The three FIFO's, 15, 17 and 18 operate to buffer the WRITE DATA, WRITE GATE, and READ WINDOW signals respectively. This buffer is provided because the disc speed may not be in instantaneous synchronism with the Pattern Generator clock. The FIFO's clock in the data with the signal CLOCK IN, comprised of M pulses per frame, obtained directly from the fourth channel of the Pattern Generator. The data are clocked out of the FIFO's by a burst of M pulses from the state machine, 16, placed on the "CLOCK OUT" line. The value of M is programmable and may even change from frame to frame, and from revolution to revolution.
(f) The EU State Machine, 16, is programmed by down loading data from the microcontroller, 14, on lines labelled "VARIOUS PARAMETERS". The data which is down loaded includes the relationship between M, the number of clock pulses to be output, and the frame number, and the relationship between the timings of the first of the M pulses and the frame number. The EU State Machine is resettable on lines ERESET from than output of the SCU State Machine, 2, when armed to accept a reset by the microcontroller using one of the lines labelled "VARIOUS PARAMETERS". The clock into the EU State Machine is the SCLK delayed by the Programmable Delay Unit, 11. The EU State Machine contains sufficient storage to accept the parameters loaded from the microcontroller. Also in the EU State Machine are frame and revolution counters which, after a Reset by the ERESET line or by the output of the Rev Counter, keep continuous track of frame # and rev #.
(i) A latchable IX MUX, 21, which can be used to select either of the two lines: the Rev. Counter output, "DERIVED SPDL FDBK PULSES", or the "SPDL FDBK PULSES", or inhibit them.
(k) A Read Pulse Detector (RDP), 25, preferably comprised of part numbers 32P547 and 32F8010 manufactured by Silicon Systems, Inc. of Tustin, Calif., which amplifies and processes the analog signals on the "READ DATA" line from the preamplifier chip, 33, in the HDA, 37. The output of the RDP chip is a short positive pulse for each input positive or negative peak which exceeds a predetermined threshold. In this application the pulse length may be set at 20 nanoseconds. A complete description of the operation of the RDP is given in the Silicon Systems 1990 Data Book (published by Silicon Systems, Inc.) on pages 2-97 through 2-114. When used in conjunction with the programmable filter, 32F8010, the bandwidth of the RDP function can be tailored to the bandwidth of the incoming signal. Note that the RDP is disabled whenever WRITE GATE is high by the signal "DISABLE ON HI".
(m) A positioner system, 27, preferably of the type described in a patent application filed on Oct. 12, 1990, in the names of Robert Hazel, Gajus Michaelson and William Valliant as joint inventors. The positioner system moves the Positioner Motor and Transducer assembly, 29, in the HDA, 34 under the control of the "STEP and DIRECTION" command lines to the input of Positioner, 27.
(e) A Read/Write chip, 33, preferably part number 32H523R in case head, 34, is a thin film head or 32H566 in case head, 34, is a ferrite head. This chip is controlled by the "WRITE GATE" line from WG MUX, 23, to be either in the Write mode or Read Mode (when WRITE GATE is FALSE). In the Write Mode, the chip will deliver either positive or negative current to the head, 34, under the control of the WRITE DATA line. In the Read Mode, low level signals from the head, 34, are amplified and delivered to the RDP, 25.
The method applied to a dedicated system can be followed by reference to the Flow Chart of FIG. 4 and the timing diagrams of FIGS. 5 to 10, and the block diagrams of FIGS. 3A and 3B.
The PC, 8, in the SCU latches MUX's 22, 23, 24 all EU's to bypass the FIFO's. The PC also instructs the Microcontrollers, 14, in each EU to ENABLE their respective 2H523R chips, 33, simultaneously.
Now, using the PC to control the PC MUX, 46, and to output PC STIM signals, similar techniques to those described above are used to simultaneously write a single scratch pair of dibits on the first track of each HDA. The locations of, and the time between, transitions are not critical. The time can be made equal to or greater than the time between the first two transitions of a normal frame. For the example pattern, this spacing could be several microseconds, as determined by the speed at which the PC, 8, can toggle an output port. Since the disc speed can be in error by as much as 20% during the recording of the dibit, when the transitions are read back from the scratch head at normal disc speed, the time between transitions on playback will have a tolerance of 20%. This is of no consequence because only the positive pulse of the dibit will be used. After the scratch transitions are written, the PC, 8, is programmed in the now familiar manner to produce a LOW WRITE GATE. All EU's are now in the read mode. The peak of the positive pulse can be used as a circumferential fiduciary. Using the DIV BY 2 circuit, 42, the READ DATA pulses are conditioned to produce one pulse per dibit, corresponding to the either positive or negative peaks. These pulses are fed to the IX MUX, 21. The PC, 8, controls and latches the IX MUX, 21, to allow these pulses to be used as feedback for the Spindle Motor Phase Lock (PLS). Using this fiduciary as a feedback signal, all HDA spindles are phase locked to the signal SPINDLE REFERENCE, a frequency, Fsp, derived from the 1 MHz fixed frequency clock from the Synthesizer, 5, in the SCU. After phase lock has been established the average disc speed of all HDA's are exactly controlled by the spindle reference frequency, set at 60 Hz for a typical spindle speed of 3600 RPM. The disc will rotate with an average period of exactly T=1/Fsp, or 1/60 second in the case of Fsp=60 Hz. This ends STEP #1 of the flow chart. Now the process of writing the first track (the "Master Track") may begin.
In the following manner, a nominal frequency, F, for the clock input to the Pattern Generator, 6, has been predetermined as a result of selecting the sequence. If the time between transitions in a dibit is Ttdb, and the time between frames is Tfr, then the largest common factor, Tlcf, of Tdb and Tfr is calculated. If Tlcf is greater than 50 nanoseconds then no change will be made to Tdb. If Tlcf is less than 50 nanoseconds then Tdb must be modified slightly to ensure that Tlcf is greater than 50 nanoseconds. The maximum transition rate is Flcf=1/Tlcf transitions per second, and the reason that 50 nanoseconds is chosen as a lower limit for Tlcf is to limit the maximum Data transition rate, Flcf, to 20 MHz so that processing electronics for writing and reading Patterns are reasonably available and economical. In future this limit could be changed as higher frequency electronics become available. In the example chosen, Tdb=500 nanoseconds, and Tfr 16000 nanoseconds, leading to Tlcf=500 nanoseconds and Flcf=2 MHz, a reasonable result. It will be shown later that a "READ WINDOW" is opened prior to the expected location of the SS negative peak but after the expected location of the SS positive peak. It is a natural choice to open the READ WINDOW half way between these expected locations. This means that the minimum time duration between events is 50% of the time between the SS positive peak and the SS negative peak; in this case the minimum time duration will be 50% of 500 nanoseconds, or 250 nanoseconds. This implies that the synthesizer clock frequency, F, should be set at least twice as high as the value calculated on the basis of transition locations alone. There is however, an additional requirement placed on F. This is due to the response time of the Pattern Generator to external TRIGGER WORDS corresponding to START, JMPA and JMPB commands. The response time is 9 F clock periods plus 170 nanoseconds plus another 20 nanoseconds for the TRIGGER WORD to stabilize. To minimize this time, the period, Tc, of F is minimized by setting F as high as possible. Therefore F is made the highest integer multiple of Flcf which is nevertheless at least 1% less than the highest frequency, 50 MHz, at which the combination of the Synthesizer, 5, and the Pattern Generator, 6, can operate. Therefore, since Flcf=2 MHz, F is chosen at 48 MHz. The 1% margin allows for variations in disc speed considerably in excess of those expected in practice, to be readily accommodated. With F set at 48 MHz, Tc=1/48e6 and the total delay in response to START or JMPA or JMPB commands is then 170e-9+20e-9+9/48e6=377.5 nanoseconds. With the STEL 2172 synthesizer, the available frequency will never be in error by more than 50% of the STEL 2172 resolution when operating with an input clock of 200 MHz. This corresponds to a frequency error of 0.3726 Hz, which is an insignificant percentage of the desired frequency, F, which is close to 50 MHz. As an example of an inappropriate initial choice of Tdb consider Tdb=440 nanoseconds with Tfr=16000 nanoseconds, then Tlcf=40 nanoseconds, violating the desirable constraint of Tlcf=50 nanoseconds minimum. This impasse could be resolved by changing Tdb to 480 nanoseconds, resulting in a safe Tlcf=160 nanoseconds. The change from 440 nanoseconds to 480 nanoseconds for Tdb is not usually critical for servo-writing. As an alternative Tdb could be changed to 400 nanoseconds resulting in a safe value of Tlcf=400 nanoseconds.
The first track written is called the Master Track. FIG. 5 shows the timing diagram for the first 8 revolutions of writing the master track. For this example, assume, without loss of generality, that the master track is of type A, with an outer guard zone sequence of normal and mark frames and also containing an Index sequence of normal and mark frames. Also assume, without loss of generality, that the first frame is a normal frame in which the SD dibit is present. First the time for one revolution, T0, is measured using the timer, 1, in the SCU. To do this, the SCU State Machine, 2, is set by the PC, 8, using the MODE line, to condition the READ DATA signal so that the first positive dibit peak is sent to input A of the Timer, 4, and the next positive dibit peak is sent to input B of the Timer, 4. At the same time the PC, 8, arms the timer to accept A and B inputs for a period of more than one revolution, but less than two revolutions. The timer measures the time between the pulse on the A input and the pulse on the B input and this time is the time for one revolution of the Spindle Motor, 30. If desired, the average of several successive periods can be measured by arranging for the PC, 8, to arm the Timer to accept A and B pulses for several revolutions instead of for just 1 revolution. Now the fractional error, Db=(T0-T)/T, in the period is calculated by the PC, 8, and the frequency synthesizer, 4, is set to a frequency of F0=F/(1+D0), where F is the nominal frequency predetermined by the sequence as described above. Note that positive period errors require negative changes to the frequency synthesizer. The time taken for the PC to acquire the Timer Data, plus the time for the PC to calculate the new frequency plus the time for the Frequency Synthesizer to settle at the new frequency must be less than half a revolution. This is not a demanding specification, and is easily met by the Stanford Telecommunications Inc. Part. # STEL-2172, together with the HP5334B Timer, 4. Now the scratch dibit has served its purpose and is erased. At the same time, a new source of spindle feedback is arranged for the spindle PLS. To achieve this, wait for 75% of a revolution (768 frames in this example), as measured by the PC, 8, and use the PC to adjust the SPINDLE REFERENCE frequency phase (from the SCU) to advance 25% of a revolution (256 frames in this example) by presetting the Divider, 1. Also using the PC, by keeping the PRST line to the Divider, 1, HIGH, suppress the first of the new SPINDLE REFERENCE pulses and disable IX MUX, 21, since there will be no reliable spindle feedback pulse available at this time.
The PC, 8, sets the MUX, 7, to pass the TC INCR signal from the SCU State Machine, 2, to the Trigger Counter, 38; loads the Trigger Decoder and Mux Decoder with the word sequences appropriate to the reminder of Step 4 and a1; of Step 5; the PC MUX, 43, to receive channels 20, 21, 22 and 23 from the Pattern Generator, 6, and the PC MUX, 46, to receive the output signals from the PG MUX, 43. This activity can take place any time between the ending of Step 2 and the expected time of the appearance of the first READ DATA pulse (SRDP1) of the revolution. The PC informs the 80C196 microcontroller, 14, in the EU to set up the Programmable Delay Units, 11, 12, and 13 in the middle of their range.
This involves looking for SRDP1- and opening a READ WINDOW and is identical to the activity in 4(a1). 4(b2) Execution of Trigger Counts 01030/03588
This activity is similar to that described in 4(a2) except that the frame pattern is different (it involves no writing) so that the only difference is that all Trigger Counts in this range are decoded in the MUX Decoder to select channel assignment 8, 9, 10, 11 which contain the RW sequence appropriate for measurement of timing errors. This RW sequence is simply that which opens two windows within a frame: one at the expected location of the negative SS peak, the other at the expected location of the negative N+ peak. In addition a WD pulse positive edge (WD+) is programmed to signify the end of the frame. SDW+cannot be used for this purpose as it was in 4(a2) since there are two SDW+'s per frame. Since there are two SDW pulses per frame, there will be five Trigger Counts per frame: two for each SDW+ and two for each SDW-, and one for WD+. Therefore, 512 frames having been recorded and since the first SS negative peak (SDW+) has already incremented the Trigger Counter to 1029 during 4(a1), the Trigger Count will advance by (5�512)-1=2559 in this stage. The PC is arranged to arm the Timer, 4, for a period beginning shortly after a SPINDLE REFERENCE pulse, and ending somewhat less than half a revolution later. This ensures that the Timer measures the average of several hundred A & B periods, thereby increasing the accuracy of the estimate of the time between successive SDW pulses.
Step #5: Write Remainder of Master Track Segments.
The PC also conditions, via the MODE line, the SCU State Machine, 2, to produce a TC INCR pulse on receipt of the SRDP1- edge and additional TC INCR pulses for each SDW-, SDW+, and the edges produced by both the terminal counts (i.e. zero) of the Read and Write Down Counters, 3, respectively. The SCU is also conditioned to output A and B pulses to the Timer, 4, on receipt of SDW+ and SRDP+ respectively, and to output RCLK pulses on receipt of SDW- edges or SRDP1- edges and WCLK pulses on receipt of CK+ edges. The PC sets the timer to make "single shot" measurements each time it is armed.
On receipt of the SDW- edge, the Trigger Counter increments from 04614 to 04615 and the Trigger Decoder outputs a TRIGGER WORD to START the Pattern Generator. Trigger Counts 04615 to 04616 are both decoded by the MUX Decoder, 44, to select Channel Assignments 12, 13, 14, 15. The pattern opens a READ WINDOW at the expected location of the next SS negative peak. The resulting SDW+ edge increments the Trigger Counter to 03596 and the corresponding TRIGGER WORD STOP's the outputting of signals from the Pattern Generator. The SDW+ pulse is also used, via the SCU State Machine, to decrement the Read Down Counter, 3, from 511 to 510, indicating that the second frame has been read.
The next SDW- will initiate a repeat of the above cycle which continues until 512 SS negative peaks have been read, and an end count RECNT=0 of the Read Down Counter produces an edge. The PC arms the timer just short of the end of the recorded portion. Since the spindle PLS has, in this example, a worst case jitter of �50 microseconds, the PC, which bases its timing on the SPINDLE REFERENCE pulses, should arm the Timer, 4, at least 50 microseconds early. If the disc speed is 3600 RPM, as in this example, the recorded segment will occupy at least 8.3 milliseconds.
Therefore, the Timer 4, should be armed no later than 8.25 milliseconds from SPINDLE REFERENCE, to allow for a possible 50 microseconds early appearance of the last SDW pulse. The Timer is disarmed by the PC for a brief interval, say 100 microseconds, prior to every Arm command by the PC. The Timer, 4, "A" input will be retriggered on each SDW+ edge.
The first SRDP1+ edge into the "B" input of the Timer will be that occurring at the end of the revolution. The time between A and B triggers will be slighter longer than half a revolution since the last SDW+ occurs on the SS negative peak at the beginning of the 512'th frame recorded in the prior step and the SRDP1+ signal occurs at the first SD positive peak of the revolution. This time will be slightly in error from the nominal time expected because of small instantaneous speed variations. The PC will begin accessing the Timer measurement no sooner than 50 microseconds after SPINDLE REFERENCE. This allows for the worst case spindle PLS jitter of �50 microseconds. Therefore, it is safe to begin accessing the Timer measurement 100 microseconds after SPINDLE REFERENCE. According to the specification of the HP5234B Timer, the time to access this measurement is 1/140 seconds, or 7.143 milliseconds. With some safety margin, the PC can disarm the Timer 7.2 milliseconds after it begins accessing the Timer Measurement. This is 7.2+0.1=7.3 milliseconds after the SPINDLE REFERENCE pulse.
The PC must now calculate the fractional error in time D1, and reprogram the Frequency Synthesizer, 5, to operate at F/(1+D1). The calculation will take less than 0.5 milliseconds and the Synthesizer settles at its new frequency in less than a 0.1 millisecond. This means that the new frequency, Fs, is set in less than 7.3+0.5+0.1=7.9 milliseconds from the SPINDLE REFERENCE pulse. This is more than 250 microseconds earlier than the earliest possible occurrence of the last frame counted which is at 8.3 milliseconds less 0.005 milliseconds less one frame time, or about 8.24 milliseconds. Note that D1, although related to the fractional speed error, is not equal to the fractional speed error. See the APPENDIX for details. Note particularly that d1 in the APPENDIX denotes speed error.
On receipt of SDW-, the Trigger Counter increments from 05640 to 05641 and the Trigger Decoder outputs a TRIGGER WORD to START the Pattern Generator. Trigger counts of both 05641 and 05642 are decoded by the MUX Decoder to select Channel Assignment 12, 13, 14, and 15. As in 5(a2), the Read Down Counter has been preset to 512 and this counter is decremented on each SDW+ pulse until RECNT is zero and the Trigger Count has reached 06664. This count is reached at the SS negative peak of the last frame previously recorded. 0n this count the MUX Decoder selects channels 16, 17, 18 and 19 which contain the WRITE DATA information for the next 256 frames, including the delay (denoted by DL in Table 1) between the sensing of the last SS negative peak and the writing of the first SD positive peak of the next segment. The Trigger Count of 06664 is decoded to produce a TRIGGER WORD which invokes a JMPA command to the Pattern Generator which initiates the outputting of the next 256 frames of WRITE DATA. Accompanying the WRITE DATA, the CK channel, 19, is programmed to produce a CK+ edge at every frame end. At the end of 256 frames of WRITE DATA the CK+ edge decrements the Write Down Counter from the beginning value of 255 to 0. In order to capture the time measurement of the unrecorded portion, the PC arms the timer shortly before the WECNT pulse is expected (with due allowance for speed jitter), begins to access the Timer data soon after the SPINDLE REFERENCE pulse, disarms the Timer for a brief interval prior to re-arming it shortly before the WECNT pulse is expected. The PC accesses the Timer measurement shortly after the SPINDLE REFERENCE pulse, computes the fractional time error D21 and reprograms the Frequency Synthesizer to operate at F/(1+D2). CK+ also increments the Trigger Counter to 06666 which is decoded by the Trigger Decoder to produce a TRIGGER WORD which now invokes Row 13.
The PC, 8, has been used to count SPINDLE REFERENCE PULSES during the steps 2 to 5. Since then steps occur over a predetermined number of revolutions, the PC will know when the last revolution of Step 5 is about to begin within a worst case timing tolerance of about �50 microseconds, this tolerance resulting from the phase jitter of the Spindle PLS. At the beginning of the last revolution of Step 5, the PC will so inform the microcontroller, 14, and the microcontroller will program the VCO frequency, SCLK, of the Data PLL, 13, to F using the PROGRAM DATA RATE lines, and assert an ACQUIRE command after a delay of somewhat greater than 200 microseconds. The PLL, 13, will then be exposed to a constant frequency equal to the frame rate as a result of the READ WINDOW action on the Dibit Select Gate, 19. The acquisition time is far less than one revolution and the ACQUIRE signal to the PLL is de-asserted after a few milliseconds. Now the PLL can accept random SDW signals so long as the transitions are in increments of Tlcf. At the end of the last revolution in Step 5, the SCU State Machine is conditioned to force ERESET low at the Programmable Revolution Counter, 9, and shortly prior to this, the IX MUX, 21, has been latched by the PC to select the DERIVED SPDL FDBK PULSES. Also prior to this, the microcontroller will program the divide ratio of the Programmable Revolution Counter, 9, using the lines "SCLK CLOCKS PER REV". When the ERESET line goes low the Programmable Revolution Counter, 9, begins to count SCLK pulses from the PLL, 13. ERESET is also used to reset the counters in the EU State Machine, 16, and said counters are now clocked with a delayed version of SCLK, beginning their counts on an SCLK transition which is synchronized with the first SS negative peak in a revolution.
In Steps 7 and 8, the Pattern Generator will operate in synchronism with the ASRP pulses and therefore its timing will differ from that of the disc speed by the jitter of the spindle PLS. In the example chosen, this is assumed to be �50 microseconds.
As in the case of Master Track writing, delays can contaminate the timing accuracy with which subsequent tracks are written. Since all subsequent tracks will be written simultaneously their accuracy will depend on correcting for timing delays internal to each EU and HDA combination. This step concerns itself with measuring this characteristic delay for each EU and HDA pair. This delay is different from the delay determined during Step 4, because none of the SCU electronics is involved in this delay.
Table 2 is the Pattern Generator planning sheet for Steps 7 and 8. The terminology is now familiar, having been discussed in detail in Steps 4 and 5. The major difference in the Pattern Generator operation for Step 7 is that it will output an entire revolution (or two revolutions) of WRITE DATA, READ WINDOW, WRITE GATE, and CLOCK IN upon initiation with an ASPR pulse negative edge, ASPR-. For example, directly on receipt of the first ASPR-, the Pattern Generator outputs the entire signal sequence for Part 1 of Track Type B. The intimate connection between signals read from the disc and the outputting from the Pattern Generator is broken and replaced by the indirect link between ASRP and SRDP1. As has been mentioned, this indirect link experiences a timing uncertainty of �50 microseconds due to the jitter in the Spindle PLS. This timing jitter will be absorbed by the FIFO's, 15, 17, and 18 with the aid of the EU State Machine, 16.
First, examination of FIG. 7 reveals that the beginning of a frame is at the negative edge of the delayed frame clock, DFCK- (a signal internal to the EU State Machine) and the end of the frame is at the next positive edge of DFCK+. Now the DFCK pulse is made very short, say 20 nanoseconds. Second, it is observed that the instantaneous speed variation of the disc �0.05% in this example, can cause the recorded frames to expand or contract by this amount. This produces an insignificant error in frame timing, but the error must not be allowed to accumulate. If the Frequency, F, is designated as the Master Clock, then each Master Clock has a duration of 1/48E6=20.833 nanoseconds. If the frame duration is normally 16 nanoseconds, then it may vary in length by �0.05% or �8 nanoseconds. Therefore, the frame is potentially foreshortened by two factors: (a) a fixed amount of 20 nanoseconds due to the width of the DFCK pulse and (b) up to 8 nanoseconds due to instantaneous speed variations.
The PC, 8, loads the Pattern Generator, 6, with all of the data prescribed in Table 2, and resets Trigger Counter, 38. The PC conditions the SCU State Machine to receive ASRP signals from the Divider, 1, and to increment the Trigger Counter, 38, on each positive ASRP edge (ASRP+) and negative ASRP edge (ASRP-). The PC instructs the microcontroller, 14, to enable FIFO's, 15, 17 and 18 by appropriate selection of the SWD MUX, 22, WG MUX, 23, and RS MUX, 24; to initialize the Programmable Delay Units, 10, 11 and 12, in the middle of their range; and to load various parameters into the EU State Machine so that it can control CLOCK OUT signals in accordance with Track Type. The EU State Machine contains counters which are reset by the ERESET line from the PC. One of the counters in the EU State Machine accumulates the current revolution number by counting the DERIVED SPDL FDBK PULSES. By virtue of this count value, the EU State Machine is knowledgeable about the current mode of operation and the Track Type. Another counter in the EU is the CLOCK OUT counter. This counter is arranged to output a fixed number, M, of clock pulses in each frame.
7(a1). Execution of Trigger Counts 00001/00002.
Now the trial write of track type B, according to the timing diagram of FIG. 7, will begin on the receipt of the next ASPR-. This will increment the Trigger Counter to the value 00001, thereby, via the Trigger Decoder and MUX Decoder respectively, invoking the complete patterns for writing Part 1 of Track Type B from channel assignments 0, 1, 2, 3. These patterns include WRITE DATA, WRITE GATE, READ WINDOW, and CLOCK IN. On receipt of ASPR+, the Trigger Counter increments to 00002, thereby resulting in a STOP TRIGGER WORD. The signal CK is a burst of M pulses in each frame, the burst lasting for slightly less than the duration of a frame.
On receipt of ASRP-, the Trigger Counter increments to 00003 which, via the Trigger Decoder invokes a START command to the Pattern Generator, while simultaneously, the MUX Decoder assigns Channels 4, 5, 6, and 7. The Pattern for measuring the timing discrepancy occurring during the trial write of 7(a1) is outputted for a revolution. This pattern opens READ WINDOWS's at the expected locations of Q- and N+ respectively, in each frame. The Timer is armed by the PC somewhat more than 100 microseconds after SPINDLE REFERENCE and remains armed for a substantial portion of a revolution.
The READ WINDOW pattern is buffered by FIFO, 18, which is clocked out at M pulses per frame by the EU State Machine, where M is fixed in this example, but in general may vary from frame to frame by preloading the EU State Machine with the appropriate information. The READ WINDOW opens the Dibit Select Gate at the expected locations of the Q+ and Q- negative peaks. In this way the Timer reads the average time interval between these peaks over the period for which it is armed. This measurement reveals the timing error incurred during the trial write of track type B. This error, Dtq, is stored so that track type B can be re-written (in the same manner in which the trial write of track type B took place) and all subsequent tracks written with a delay programmed at P=Pmid-Dtq delay units.
The SCU issues the pattern for two entire revolutions to all HDA's simultaneously. It must initiate the loading of the pattern into all the FIFO's in advance of the spindle reference pulse by at least the worst case expected spindle phase jitter, but not so far in advance that the FIFO's capacities are exhausted. This is the reason that the ASRP-Pulse is used to initiate the Pattern Output (via the SCU State Machine, Trigger Counter, Trigger Decoder and MUX Decoder).
The pattern is clocked into the FIFO's from the Pattern Generator by M bursts of CLOCK IN's per frame. The FIFO's are clocked out by M bursts of CLOCK OUT pulses initiated by the State Machine, 16, of each individual EU. If the short term speed variations were about �0.02% over a frame interval, for example, then the timing error would �0.02% of 16 microseconds, or �3.2 nanoseconds.
______________________________________      Frame Count on SCLK pulseTrack Type corresponding to peak of:______________________________________A, Part 1  N-A, Part 2  SSB, Part 1  Q-B, Part 2  SSC, Part 1  N+C, Part 2  SSD, Part 1  Q+D, Part 2  SS______________________________________
The next line indicates the frame count values while positioned over track type B and recording track type C from timing generated from the SCLK pulse corresponding to the Q- negative peaks available from track type A.
The first step in planning the program for the Pattern Generator is to determine how many addresses are required in a segment. This is simply 1+the number of possible level changes in a segment. During the Writing of the Master Track, the READ WINDOW occurs only at the SS negative peak, involving two level changes. As will be explained in the following paragraphs, there are four frames in a segment for a total of eight level changes, therefore requiring nine addresses. For the same reason WRITE GATE also requires nine addresses. WRITE DATA can occur in any one or more of six different dibit locations. Since the Pattern Generator is programmed to output NRZ(I) WRITE DATA, and since there are four frames per segment, this involves 24+1=25 addresses. Therefore the total number of addresses per segment during writing of the Master Track is 9+9+25=43 addresses. It will be shown later that two segments are required for maximum Track Writing. Therefore, the total number of addresses required is 2�107=214, comfortably less than the 1024 maximum allowed.
It will be shown later that four segments are provided for writing the subsequent tracks. During the writing of subsequent tracks, READ WINDOW can occur in one fewer locations than there are dibits i.e. 5. Since there are four frames in segment #1, this requires (4�2�5)+1=41 addresses. Similarly for WRITE GATE, which therefore also requires 41 addresses. WRITE DATA provides 25 addresses as in the case of Master Track writing. The total number of addresses in the first segment is therefore 41+41+25=107 addresses.
In the second segment there are ten frames. Consequently, there are (10�2�5)+1=101 addresses for READ WINDOW, (10�2�5)+1=101 addresses for WRITE GATE and (10�1�6)+1=61 addresses for WRITE DATA. Therefore, the total number of addresses in segment #2 IS 101+101+61=263.
Examining the headings for each column in Table #1, the Trigger Count column is intended to indicate the state of the Trigger Counter, 38. The Activity column describes the current mode of operation of the writer. The FIG. # column references the activity in question to a timing diagram. The column headed "Contents of Segments" is divided into two parts: segment #1 and segment #2. These column entries contain a brief description of the nature of the pattern contained in segments 1 and 2. The column "Address" denotes the address range to be occupied by the pattern in Segments 1 and 2. Although the Mark Frame contains two less actual transitions than the Normal Frame, the number of addresses is chosen to include the two missing transitions as if they were present. Similarly, although N- and Q+ transitions are absent from a type A frame, the number of addresses chosen include the transitions at N- and Q+. The total number of addresses does not exceed 1024. The column headed "#of Segs" indicates the total number of segments occupied by the pattern. For example, if segment #1 repeats three times and segment #2 repeats eight times, then the entry in this column would be 11. This number should not exceed 255. The column headed START indicates the condition under which the Pattern Generator should initiate its output. The column headed JMPA indicates the condition under which the JMPA command is invoked and allows for an alternative "START" for a pattern sequence. The column headed STOP indicates the condition under which the Pattern Generator is to cease outputting and freeze at the current 24 bit pattern. This may occur when the programmed pattern is exhausted (indicated by an "END" designation) or when an event happens e.g. some external pulse or signal edge. The column headed Channel Assignment indicates the group of four channels which are to be selected by the PC MUX, 43, for use by the system.
Now reading the entries in Row 1 in FIG. 13, the Trigger Count 00001/00002 indicates that the designated pattern is to START on receipt of a PC command on the PG STIM line and to stop when Write Gate goes low (WG-). The sequence to be output is comprised of two segments, the first of which has the general form of Normal, Mark, Normal, Normal, hence the shorthand designation NM2N. The first segment contains 43 addresses. The second segment contains four Normal frames (hence the designation 4N) repeated 127 times; hence the shorthand notation 127*(4N). The aggregate number of segments is 1+127=128 since the second segment repeats 127 times. Although the second segment is repeated 127 times, it nevertheless contains the same number of addresses as the first segment i.e. 43. The total number of addresses is 2�43=86 and the address range is 0 to 85.
Since there are only three decodes for the TRIGGER decoder, they can be represented with two signals. Trigger Count goes up to 25,111 in FIG. 13. Therefore, for complete flexibility in the Trigger Decoder, 39, it should be a 64K�2 Static Random Access Memory (SRAM). By the same reasoning, the MUX Decoder, 44, with only 5 states, can be a 64K�3 Static Random Access Memory. The SRAM must have an access time commensurate with the system speeds. SRAM's with 20 nanoseconds access time are available and should be chosen.
or (b) If the chip timing is substantially longer than the required pattern timing, the pattern may be recorded in 2 successive revolutions, during the first of which even frames are written triggered by reading of odd frames, and vice versa on the second revolution. In this case the chip timing can be as long as slightly greater than 1 frame time; or
(c) By improving the Read after Write recovery of the RDP chip with external components. This technique helps because the RDP recovery is longer than the recovery of the head chip. The head chip recovery can be as short as 600 nanoseconds worst case (e.g. SSI Part # SSI 32H523R) and this is the limiting factor if the RDP recovery is sufficiently improved.
In the example above, the number of frames was assumed to be a power of 2. The method will, however, work equally well with any number of frames, including prime numbers. This is accomplished by subtracting from the total number of frames, Nf, the largest power of 2, say 2n, which is less than Nf. The first revolution of the Master Track is then written with Nf-2n frames and all subsequent revolutions are written with a number of frames which is a power of 2. Equally obvious is that the method does not depend on the nominal period of a revolution being a power of 2 as was assumed in the example.
The procedure for writing a disc drive with sector information will be described in the case of a typical sector pattern. Although there are a wide variety of sector patterns in use (e.g. U.S. Pat. No. 4,032,984 by Kaser et al, U.S. Pat. No. 4,424,543 etc.), the general techniques proposed for the example sector pattern selected can usually be adapted for use with other sector patterns. In this example, it is envisaged that all disc surfaces are to be written with the same pattern and the process of writing the first surface will be described. U.S. Pat. Nos. 4,032,984 and 4,424,543 emphasize the value of Gray encoded patterns to indicate "coarse" head position. In addition to the Gray encoded pattern, there is a requirement for "fine" (i.e. with resolutions to very small fractions of a track) information.
Denoting the transition pairs in cell 0 as C0.1 and C0.0, and using a similar nomenclature for the other cells, if this master track is type A, then the transitions recorded will be SD, SS, C0.0, C1.0, C2.0, and the Q+ BURST.
Subsequent tracks are written by using the EU State Machine and the pattern generator in a manner similar in principle but different in detail to the dedicated example previously described. Depending on the mode, the frame counter in the EU State Machine is synchronized to an SCLK clock corresponding either to the last pulse of SS, C0.1, C0.0, C1.1, C1.0, C2.1, C2.0, last N+ transition, last N- transition, last Q+ transition or last Q- transition. The EU State Machine will be used to switch from one trigger to another as writing proceeds around a track.
If disc speed changes slowly from revolution to revolution, the timing accuracy is better than the worst case calculated in the Appendix. Even further improvement can be obtained if a profile of the speed error is taken over several revolutions before writing the Master Track. To the degree that the profile is repeatable, the history of speed errors up to and including revolution n-1 can be used to predict the speed error in the upcoming revolution n. The frequency synthesizer can be set in accordance with the extrapolated speed error instead of the somewhat stale speed error measured during revolution n-1. This method will add about 20 revolutions, or 0.32 seconds, to writing a Master Track.
If speed changes rapidly, improved timing accuracy can easily be achieved as follows. In the first revolution after writing 50% of the track using the nominal clock, F, the time remaining unrecorded is measured as before. If this time exceeds a desired tolerance level then, after erasing the track, the 50% of a track is re-written with the clock to the Pattern Generator still set at F, until the desired tolerance level is achieved. (Note that only a fixed clock frequency rather than a fine resolution frequency synthesizer is required for this method). For example with the values chosen, t1 may be in error by �8 microseconds, or 0.1%. However, if this error varies from revolution to revolution with approximately a uniform probability distribution (and is uncorrelated from revolution to revolution), the following statistical method yields a superior Master Track at the expense of throughput. Assuming the distribution is between -0.1% and +0.1%, if the desired tolerance level is �0.025%, then the probability of achieving this in the first revolution is 0.025/0.1 or 25%. The probability of achieving this in n revolutions is 1-(0.75)n. If n=10, then the probability is 0.94, or 94%. If the probability distribution is Gaussian (which is more likely in practice), the probability is even higher than 94%. Once the time t1 is within the desired tolerance, the next step of writing 50% of the remainder takes place. Once again this is repeated until the desired tolerance is achieved. For the 11 segments to be written, the probability of achieving a 0.05% closure in 10*11=110 revolutions is simply (0.94) 11=0.528, or 52.8%. This means that more than 50% of the time the master track will be written in 110 revolutions or about 1.8 seconds. In extreme cases the time may extend to about 5 seconds. If the timing jitter distribution is Gaussian instead of uniform, (as is likely in practice), more than 50% of the time the master track will be written in considerably less than 1.8 seconds.
Speed Error during revolution n=dn Unwritten Segment in revolution n=tn Assumptions
(1) dn is so small that product terms dn dm are negligible.
Revolution 1, Speed Error d1 Write Time t1w =t0 /2=(T/2)(1-d0) ##EQU1## Revolution 2, Speed Error d2 Write Time, t2w,=t1 /2=(T/22)(1-2d1 +d0) ##EQU2## Revolution n, Speed Error dn Write Time, t2w,=tn-1 /2=(T/2n)(1-2dn-1 +d0)
Time for unwritten segment=(T/2n)(1-2dn +d0)
If last frame is to be written at revolution N, then: Measured time left for last frame, tN =[T/(2.sup.(N-1))](1-2dN-1 +d0) ##EQU3##
This segment is recorded when the speed is actually in error by dn. If dn =dn-1, the arc length of the segment is correct. The length of the segment is only incorrect to the degree that dn differs from dn-1. If the speed error is 0.1%, the maximum difference is 0.2%, and the maximum possible error in the arc occupied by any segment is 0.2% of the arc length. This results in worst case frequency modulation of �0.2% on playback.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3531787 *Jun 20, 1967Sep 29, 1970Us NavyAutomatic magnetic drum clock track recorderUS3540022 *Mar 15, 1968Nov 10, 1970Singer General PrecisionRotating memory clock recorderUS3893172 *Sep 9, 1974Jul 1, 1975Gte Automatic Electric Lab IncAutomatic master clock track writerUS4068268 *Jan 8, 1976Jan 10, 1978Idemoto Tom YMethod and apparatus for writing servo-tracks on rotating magnetic memory surfacesUS4131920 *Oct 19, 1977Dec 26, 1978Pioneer MagneticsClosed-clock writing system for a rotating magnetic memoryUS4371902 *Jun 30, 1980Feb 1, 1983International Business Machines CorporationDisk initialization methodUS5153788 *Mar 28, 1990Oct 6, 1992Mitsubishi Denki Kabushiki KaishaMethod of recording and detecting servo information for positioning magnetic headUS5164863 *Aug 29, 1991Nov 17, 1992Seagate Technology, Inc.Method for writing servo patterns to a disc of a hard disc driveUS5164866 *Aug 8, 1991Nov 17, 1992Victor Company Of Japan, Ltd.Timing signal recording system of a magnetic disk apparatus* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS5946157 *Jul 21, 1997Aug 31, 1999Western Digital CorporationMethod of seamlessly recording circumferentially successive servo bursts that overlap one anotherUS5973758 *Jan 14, 1998Oct 26, 1999C-Cube Microsystems, Inc.Video synchronizationUS6108156 *May 27, 1998Aug 22, 2000Samsung Electronics Co., Ltd.Method for recording a port number of a servo track writerUS6259576Nov 26, 1996Jul 10, 2001Samsung Electronics Co., Ltd.Method and apparatus for hard disk drive with self-servowriting capabilityUS6628471Mar 2, 2001Sep 30, 2003Seagate Technology LlcDetection and cancellation of cage frequency using the clock head in a servowriterUS6865041Feb 29, 2000Mar 8, 2005Hitachi Global Storage Technologies Netherlands B.V.Method and apparatus for servowriting using a unipolar write currentUS7023645May 5, 2003Apr 4, 2006Maxtor CorporationRead error recovery method and apparatusUS7027251Jan 6, 2003Apr 11, 2006Maxtor CorporationMethod and apparatus to control pole tip protrusionUS7092185 *Jul 8, 2004Aug 15, 2006Agere Systems Inc.Write gate timing for a servo bankUS7106020Aug 30, 2005Sep 12, 2006Honeywell International Inc.Method of operating a brushless DC motorUS7116509Aug 13, 2003Oct 3, 2006Hitachi Global Storage Technologies Japan, Ltd.Magnetic disk apparatus and servo signal recording methodUS7133239Feb 26, 2004Nov 7, 2006Maxtor CorporationMethods and apparatuses for writing spiral servo patterns onto a disk surfaceUS7139144Aug 6, 2001Nov 21, 2006Maxtor CorporationMethod and apparatus for writing spiral servo information by modifying existing servo track writing equipmentUS7167333Apr 19, 2002Jan 23, 2007Maxtor CorporationMethod and apparatus for writing and reading servo information written in a spiral fashionUS7224548 *Jan 6, 2003May 29, 2007Maxtor CorporationDetermining contact write current in disk drive using position error signal varianceUS7248427Jun 2, 2004Jul 24, 2007Maxtor CorporagionMethod and apparatus for reducing velocity errors when writing spiral servo information onto a disk surfaceUS7265512Aug 30, 2005Sep 4, 2007Honeywell International Inc.Actuator with feedback for end stop positioningUS7266567 *Oct 24, 2002Sep 4, 2007Kabushiki Kaisha Yasakawa DenkiAbsolute encoder and absolute value signal generation methodUS7586279Nov 9, 2006Sep 8, 2009Honeywell International Inc.Actuator position switchUS7623313Nov 24, 2009Maxtor CorporationMethod and apparatus for performing a self-servo write operation in a disk driveUS8084980Dec 27, 2011Honeywell International Inc.HVAC actuator with internal heatingUS8084982Nov 18, 2008Dec 27, 2011Honeywell International Inc.HVAC actuator with output torque compensationUS20040190184 *Aug 13, 2003Sep 30, 2004Kei YasunaMagnetic disk apparatus and servo signal recording methodUS20050122242 *Oct 24, 2002Jun 9, 2005Kabushiki Kaisha Yaskawa DenkiAbsolute encoder and absolute value signal generation methodUS20060007580 *Jul 8, 2004Jan 12, 2006Tianyang DingWrite gate timing for a servo bankUS20080111512 *Nov 9, 2006May 15, 2008Honeywell International Inc.Actuator position switchUS20100194326 *Aug 5, 2010Honeywell International Inc.Hvac actuator with internal heating* Cited by examinerClassifications U.S. Classification360/48, G9B/27.033, G9B/20.03, G9B/5.225, 360/75, 360/51International ClassificationG11B27/30, G11B5/00, G11B21/10, G11B5/596, G11B20/12Cooperative ClassificationG11B5/59655, G11B27/3027, G11B2005/0013, G11B20/1252, G11B2220/20European ClassificationG11B20/12D6, G11B27/30C, G11B5/596F5Legal EventsDateCodeEventDescriptionNov 19, 1999FPAYFee paymentYear of fee payment: 4Nov 21, 2003FPAYFee paymentYear of fee payment: 8Nov 21, 2007FPAYFee paymentYear of fee payment: 12Nov 26, 2007REMIMaintenance fee reminder mailedRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services