Source: http://www.google.com/patents/US6738601?dq=6,587,403
Timestamp: 2014-12-18 10:15:28
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Patent US6738601 - Adaptive radio transceiver with floating MOSFET capacitors - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including...http://www.google.com/patents/US6738601?utm_source=gb-gplus-sharePatent US6738601 - Adaptive radio transceiver with floating MOSFET capacitorsAdvanced Patent SearchPublication numberUS6738601 B1Publication typeGrantApplication numberUS 09/691,630Publication dateMay 18, 2004Filing dateOct 18, 2000Priority dateOct 21, 1999Fee statusPaidAlso published asUS6917789, US6920311, US6987966, US7116945, US7130579, US7233772, US7349673, US7356310, US7389087, US7697900, US7756472, US8023902, US8116690, US20040195917, US20050153664, US20050186925, US20070049205, US20070285154, US20080182526, US20080191313, US20080290966, US20100255792Publication number09691630, 691630, US 6738601 B1, US 6738601B1, US-B1-6738601, US6738601 B1, US6738601B1InventorsAhmadreza Rofougaran, Maryam Rofougaran, Shahla KhorramOriginal AssigneeBroadcom CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (9), Non-Patent Citations (1), Referenced by (65), Classifications (62), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetAdaptive radio transceiver with floating MOSFET capacitorsUS 6738601 B1Abstract An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.
a first node for receiving a signal; a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node; a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and a second node coupled to receive the signal from the at least one other node of the second transistor; wherein the first transistor and the second transistor provide a capacitance between the first node and the second node. 2. The capacitor of claim 1 wherein the first and second transistors each comprises a metal oxide semiconductor (MOS).
3. The capacitor of claim 2 wherein the capacitor is a floating capacitor.
4. The capacitor of claim 3 wherein each of the at least one other node of the first and second transistors comprises a, drain and a source, the drain and the source of the first transistor being coupled to the first node, and the drain and the source of the second transistor being coupled to the second node.
5. The capacitor of claim 2 further comprising a bias resistor coupled to the gate nodes of the first and second transistors.
6. The capacitor of claim 2 wherein each of the at least one other node of the first and second transistors comprises a drain and a source, the drain and the source of the first transistor being coupled to the first node and the drain and the source of the second transistor being coupled to the second node.
7. The capacitor of claim 6 further comprising a bias resistor coupled to the gate nodes of the first and second transistors.
a first node for receiving a signal; a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node; a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and a second node coupled to receive the signal from the at least one other node of the second transistor; wherein the first transistor and the second transistor provide a capacitance between the first node and the second node. 9. The integrated circuit of claim 8 wherein the first and second transistors each comprises a metal oxide semiconductor (MOS).
10. The integrated circuit of claim 9 wherein the integrated circuit comprises a floating capacitor.
11. The integrated circuit of claim 10 wherein each of the at least one other node of the first and second transistors comprises a drain and a source, the drain and the source of the first transistor being coupled to the first node, and the drain and the source of the second transistor being coupled to the second node.
12. The integrated circuit of claim 9 further comprising a bias resistor coupled to the gate nodes of the first and second transistors.
13. The integrated circuit of claim 9 wherein each of the at least one other node of the first and second transistors comprises a drain and a source, the drain and the source of the first transistor being coupled to the first node and the drain and the source of the second transistor being coupled to the second node.
14. The integrated circuit of claim 13 further comprising a bias resistor coupled to the gate nodes of the first and second transistors.
15. A tunable capacitor array, comprising:
a plurality of capacitors each of the capacitors comprising: a first node for receiving a signal; a first transistor comprising a gate node and at least one other node, the at least one other node coupled to receive the signal from the first node; a second transistor comprising a gate node and at least one other node, the gate node of the second transistor coupled to receive the signal from the gate node of the first transistor; and a second node coupled to receive the signal from the at least one other node of the second transistor; wherein the first transistor and the second transistor provide a capacitance between the first node and the second node; the first nodes of the capacitors being coupled together and the second nodes of the capacitors being coupled together; and a plurality of switches each being positioned between a different one of the capacitors and the respective capacitors first or second node. 16. The tunable capacitor array of claim 15 wherein the first and second transistors for each of the capacitors each comprises a metal oxide semiconductor (MOS).
17. The tunable capacitor array of claim 16 wherein the capacitors comprise floating capacitors.
18. The tunable capacitor array of claim 17 wherein each of the at least one other node of the first and second transistors for each of the capacitors comprises a drain and a source, the drain and the source of the first transistors each being coupled to the first nodes, and the drain and the source of the second transistors each being coupled to the second nodes.
19. The tunable capacitor array of claim 16 wherein the capacitors each comprises a bias resistor coupled to the gate nodes of the respective capacitors first and second transistors.
20. The tunable capacitor array of claim 16 wherein each of the at least one other node of the first and second transistors for each of the capacitors comprises a drain and a source, the drain and the source of the first transistors each being coupled to the first nodes, and the drain and the source of the second transistors each being coupled to the second nodes.
21. The tunable capacitor array of claim 20 wherein the capacitors each comprises a bias resistor coupled to the gate nodes of its respective first and second transistors.
CROSS-REFERENCE TO RELATED APPLICATION The present application is a continuation of co-pending patent application Ser. No. 09/634,552, filed Aug. 8, 2000, priority of which is hereby claimed under 35 U.S.C. �120. The present application also claims priority under 35 U.S.C. �119(e) to provisional Application No. 60/160,806, filed Oct. 21, 1999; Application No. 60/163,487, filed Nov. 4, 1999; Application No. 60/163,398, filed Nov. 4, 1999; Application No. 60/164,442, filed Nov. 9, 1999; Application No. 60/164,194, filed Nov. 9, 1999; Application No. 60/164,314, filed Nov. 9, 1999; Application No. 60/165,234, filed Nov. 11, 1999; Application No. 60/165,239, filed Nov. 11, 1999; Application No. 60/165,356; filed Nov. 12, 1999; Application No. 60/165,355, filed Nov. 12, 1999; Application No. 60/172,348, filed Dec. 16, 1999; Application No. 60/201,335, filed May 2, 2000; Application No. 60/201,157, filed May 2, 2000; Application No. 60/201,179, filed May 2, 2000; Application No. 60/202,997, filed May 10, 2000; Application No. 60/201,330, filed May 2, 2000. All these applications are expressly incorporated herein by referenced as though fully set forth in full.
FIG. 19(b) is a graphical depiction of a signal spectrum at the output of two stage polyphase filter of the clock generator of FIG. 18 in accordance with an exemplary embodiment of the present invention;
In the described exemplary embodiment, the RF clocks are generated in the LO generator 14. This can be accomplished in various fashions including, by way of example, either generating the RF clocks in the VCO or using a polyphase circuit to generate the RF clocks. Regardless of the manner in which the RF clocks are generated, the mixer 52 will produce a spectrum of frequencies including the sum and difference frequencies, specifically, fVCO�(1+(1/N)) and its image fVCO�(1−(1/N)). To reject the image, the mixer 52 can be configured as a double quadrature mixer as depicted in FIG. 3. The double quadrature mixer includes one pair of mixers 55, 57 to generate the Q-clock and a second pair of mixers 59, 61 to generate the I-clock. The Q-clock mixers utilizes a first mixer 55 to mix the I output of the VCO 48 (see FIG. 2) with the Q output of the divider 40 and a second mixer 57 to mix the Q output of the VCO with the I output of the divider. The outputs of the first and second mixers are connected together to generate the Q-clock. Similarly, the I-clock mixers utilizes a first mixer 59 to mix the I output of the divider with the I output of the VCO and a second mixer 61 to mix the Q output of the divider with the Q output of the VCO. The outputs of the first and second mixers are connected together to generate the I-clock. This technique provides very accurate I-Q clocks by combination of quadrature VCO and filtering. Because of the quadrature mixing, the accuracy of the I-Q clocks is not affected by the VCO inaccuracy, provided that the divide by N circuit generates quadrature outputs. This happens for even divide ratios, such as N=2.
Turning back to FIG. 2, the transmitter 12 includes a complex buffer 54 for coupling incoming I-Q modulated baseband signals to a programmable low-pass filter 56. The low-pass filter 56 can be programmed by the controller through the select input. The output of the low-pass filter 56 is coupled to complex mixers 58. The complex mixers 58 mixes the I-Q modulated baseband signals with the RF clocks from the LO generator to directly upconvert the baseband signals to the transmitting frequency. The upconverted signal is then coupled to an amplifier 60 and eventually a power amplifier (PA) 62 for transmission into free space through the antenna. A bandpass filter (not shown) maybe disposed after the PA 62 to filter out unwanted frequencies before transmission through the antenna.
In the case of transceiver chip integration, an off chip coupler (not shown) can be used to split the single-ended output from the antenna into a differential output with each output being 180� out of phase. The LNA input can be matched to the coupler, i.e., a 50 ohm source, by LC circuits. A shunt capacitor 463 in combination with a series inductor 465 provides a matching circuit for one output of the coupler, and a shunt capacitor 467 in combination with a series inductor 469 provides a matching circuit for the other output of the coupler. At 2.4 GHz., each LC circuit maybe replaced by a shunt capacitor and transmission line. In the described exemplary embodiment, the LC circuits are off-chip for improved noise figure performance. Alternatively, the LC circuits could be integrated on chip. However, due to the high loss of on chip inductors, the noise figure, as well as gain, could suffer.
For the resistor values shown in FIG. 6, the biquad stage outputs are: V O1 = A  ( 1 + j   RC   ω )  V II + 2  QV IQ ( 1 + j   RC   ω ) 2 + 4  Q 2 ( 1 ) and V OQ = A  - 2  QV II + ( 1 + j   RC   ω )  V IQ ( 1 + j   RC   ω ) 2 + 4  Q 2 ( 2 ) FIG. 7 shows the frequency response for the complex biquad filter.
After the received signal is downconverted, the desired channel in the I path lags the one in the Q path, that is, VII=−jV IQ, and therefore: H  ( j   ω ) = V o V I  ( j   ω ) = A 1 + j   RC   ω - j   2  Q ( 3 ) This shows a passband gain of A 122 at a center frequency of 2Q/RC 124, with a 3-dB bandwidth of 2RC 126. Thus, the quality factor of the second-order stage will be Q. For the image signal however, the signal at the I branch leads, and as a result: H  ( j   ω ) = A 1 + j   R   C   ω + j   2  Q ( 4 ) which shows that the image located at 2Q/RC is rejected by 1 ( 1 + ( 4  Q )  2 . Therefore, the biquad stage has an asymmetric frequency response, that is, the desired signal may be assigned to positive frequencies, whereas the image is attributed to negative frequencies. In general, the frequency response of the biquad stage is obtained by applying the following complex-domain transformation to a normalized real-domain lowpass filter: j   ω → j  ( ω - ω 0 ) BW ( 5 ) where ω0 is the bandpass (BP) center frequency, and BW is the lowpass (LP) equivalent bandwidth, equal to half of the bandpass filter bandwidth. For instance, for a second-order biquad stage (as shown in FIG. 6), ω0=2Q/RC, and BW=1/RC. The biquad stage is designed by finding its LP equivalent frequency response using equation (5). Once the LP poles are known, the BP poles are calculated based on equation (5). Assume that the LP equivalent has n poles, and Pi,LP=αi+jβi is the ith pole. From equation (5), the BP pole will be:
P i,BP =BW�P i,LP +jω 0=αi �BW+j(ω0 +β i �BW) (6) The complex filter is realized by cascading n biquad stages. Therefore, similar to real-domain bandpass filters, an nth order complex filter uses 2�n integrators. Based on equation (3), each biquad stage has a pole equal to −1/RC+j2Q/RC. Thus: α i � BW = - 1 RC ( 7 ) and ω o + β i � BW = 2  Q RC ( 8 ) Since the LP equivalent poles are located in the left-half plane, ai is always negative. The above equations set the value of Q and RC in each stage. The gain of each biquad stage can be adjusted based on the desired gain in the complex filter, and noise-linearity trade-off: increasing the gain of one biquad stage lowers the noise contributed by the following biquad stages, but it also degrades the linearity of the complex filter.
The described exemplary embodiment of the biquad stage can be modified to obtain a sharper rejection or notch at an undesired signal at a specific frequency. This can be achieved in the biquad stage by adding zeros. Assume that the input resistors at the biquad input (Ri 114 in FIG. 6) is replaced with an admittance Yi. For the received signal, the frequency response of the biquad stage will be equal to: H  ( j   ω ) = R � Y i 1 + j   RC   ω - j   2  Q ( 10 ) FIG. 8 shows Yi having resistor Rz 128 and capacitor Cz 130.
In order to have a zero located at jω axis in the frequency response, Yi should contain a term such as 1−-ω/ωz. If Yi is simply made of a resistor Rz in parallel with a capacitor Cz, then the input admittance will be equal to: Y i = 1 R z + j   ω   C z ( 11 ) which is not desirable, since the zero will be in the left-half plane, rather than the jω axis.
FIG. 9 shows Yi with the capacitor Cz 132 connected to the Q input 134 and the resistor Rz connected to the I input 136. Now the current I will be equal to: I = V R z + j   C z  ω � ( j   V ) ( 12 ) Therefore, the input admittance will be equal to: Y i = 1 V = 1 R z - C z  ω ( 13 ) which indicates that the filter will have a zero equal to 1/RzCz at the jω axis.
FIG. 10 shows a single biquad stage modified to have a zero at the jω axis. The biquad stage includes capacitors 138, 140, 142, 144. The combination of capacitors 138, 140, 142, 148 and resistors 116, 118 determines a complex zero with respect to the center frequency. The transfer function for the received signal will be: H  ( j   ω ) = A  1 - RC z A  ω 1 + j   RC   ω - j   2  Q ( 14 ) Equation (14) is analogous to equation (3), with the difference that now a zero at A/RCz is added to the biquad stage of the complex filter. By knowing the LP equivalent characteristics of the biquad stage, the poles are calculated based on equation (6). The value of Q and RC in each biquad stage is designed by using equation (7) and equation (8). If the normalized LP zeros are at �ωz,LP, then the biquad stage should be realized with two biquad stages cascoded, and the frequency of zeros in the biquad stages will be (equation (5)):
ωz,1,2=ω0�ωz,LP �BW (15) If the differential I and Q inputs connected to the zero capacitors are switched, the biquad stage will have zeros at negative frequencies (image response). This property may be exploited to notch the image signal.
The center frequency of the complex filter can be adjusted by setting 1/RuCu equal to a reference frequency generated, by way of example, by the crystal oscillator in the controller. The filter is automatically tuned by monotonic successive approximation as described in detail in Section 4.0 herein. Once the value of RuCu is set, the complex filter characteristics depends only on the four-bit code for the capacitors and the five-bit code for the resistors. For example, assume that the value of the resistors in the biquad stage of FIG. 6 is as following: R1=nARu, Rf=nQRu, and Rc=nQRu. Likewise, assume that C=nCCu, where nC is a constant, and that 1/RuCu=ωu. The value of ωu is set to a reference crystal by a successive approximation feedback loop. The filter frequency response for the received signal will be: H  ( j   ω ) = n F n A 1 + j   n c  n F  R u  C u  ω - j  n F n Q ( 16 ) Therefore, the biquad stage gain (A), center frequency (ω0), and bandwidth (BW) will be equal to: A = n F n A ( 17 ) ω 0 = 1 n C  n Q � ω u ( 18 ) BW = 1 n C  n F � ω u ( 19 ) The above equations show that the characteristics of the biquad stage is independently programmed by varying nA, nF, and nQ. For instance, by setting nF, the gain of the biquad stage changes from nF/31 to nF by changing nA from 1 to 31.
S=min(V i ,V L) (21) Therefore, the RSSI maximum input level is S, and the ideal RSSI minimum input level is S/An, where A is the gain of each differential amplifier and n is the number of the differential amplifiers. Thus, the ideal dynamic range is calculated as follows: Ideal   Dynamic   Range = 20  log  S S A n = 20   log   A n = 20  ( n )  log   A ( 22 ) However, in the case of a large amount of gain, the input level will be limited with the input noise and the dynamic range will also be limited to: Dynamic   Range = 20  log  S σ n ( 23 ) σ n = total   noise   rms σ n = ( BW ) � Noise   Factor If each differential amplifier has the same input dynamic range VL and each full-wave rectifier has similar input dynamic range Vi, then the dynamic range of the logarithmic differential amplifier and the total RSSI circuitry are the same.
For an input being in the following range: S A n - m < V i   n < S A n - m - 1 ( 24 ) up to the last m stages of the differential amplifier are all being limited and the rest of the differential amplifiers are in the linear gain region. Therefore, the RSSI is shown to be:
A 2β2νin 2 +A 4β4νin 4 + . . . +A 2(n−m)β2(n−m)νin 2(n−m) +mβ 2 S 2 =RSSI (25) This is further simplified to: RSSI = ( A   β ) 2 ( A   β ) 2 - 1  V i   n 2  [ ( A   β ) 2  ( n - m - 1 ) - ] + m   β 2  S 2 ( 26 ) RSSI = 1 ( A   β ) 2 - 1  V i   n 2  ( A   β ) 2  ( n - m ) + m   β 2  S 2 ( 27 ) The above equation is a first order approximation to the logarithmic function shown in equation (28) according to the first two terms of the Taylor expansion at a given operating point.
Max RSSI−Min RSSI=C log A 2n (29) ΔRSSI=C log A 2n (30) C = Δ   RSSI 2  n   log   A ( 31 ) ( Ideal )   RSSI = Δ   RSSI 2  n   log   A  log   V i   n 2 ( 32 ) To find the relation between the gain of a differential amplifier, the gain of a rectifier, and the maximum input range of the combined differential amplifier and the rectifier, the RSSI will be calculated for the two consecutive differential amplifier and rectifier combinations (see equations (33) and (34)) for both ideal RSSI equations (32) and approximated RSSI equation (27): V i   n1 = S ( A ) n - m ( 33 ) V i   n2 = S ( A ) n - m - 1 ( 34 ) (Ideal) RSSI 2 −RSSI 1=log(A)2 (35)
(Approximated) RSSI 2 =RSSI 1=log(A)2 (35) Therefore,
Clog(A)2=β2 S 62 (37) Using equations (18) and (12), the following expression is achieved: Δ   RSSI n = β 2  S 2 ( 38 ) Plugging equation (19) into (8) results in the following: RSSI = 1 ( A   β ) 2 - 1  ( A   β ) 2  ( n - m )  V i   n 2 + m  Δ   RSSI n ; S A n - m < V i   n < S A n - m - 1 ( 39 ) FIG. 16(a) shows a schematic diagram for an exemplary embodiment of the differential amplifier used in the type II core amplifier. The differential input signal is fed to the gates of transistor amplifiers 955, 957. The amplified differential output signal is provided at the drains of the transistor amplifiers 955, 957. The gain of the transistor amplifiers is set by load transistors 958, 860, each connected between the drain of one of the transistor amplifiers and a power source. More particularly, the gain of the differential amplifier is determined by the ratio of the square root of transistor amplifiers-to-load transistors. Gain  ( A ) = w i   n w i   n = 200 6 ≈ 5.8 ( 40 ) The sources of the transistor amplifiers 955, 957 are connected in common and coupled to a constant current source transistor 952. In the described exemplary embodiment, the controller provides the bias to the gate of the transistor 952 to set the current.
When the transistors 962, 964, 966, and 968 are operating in the saturation region, the following equations are shown for the differential output current DISQBI where k is the ratio of the two unbalanced source-coupled transistors: if   Δ   I SQM1 = ( I D1 + I D4 ) - ( I D2 + I D3 ) = 2  ( I D   C + I SQ ) = 2  k - 1 k + 1  I o - 4  k  ( k - 1 )  β N ( k + 1 ) 2  V I 2 ( 41 ) The input dynamic range of the full rectifier is then: if   Δ   I SQM1 = O , V i = � I o β N   k + 1 2   k ( 42 ) The full-wave rectifier includes two unbalanced differential pairs with a unidirectional current output. One rectifier 976 taps each differential pair and sums their currents into a 10 kW resistor RL.
The square law portion of equation (41) multiplied by the resistance provides the β2S2 of equation (42): β 2  S 2 = 4  k  ( k - 1 )   β N ( k + 1 ) 2  V i 2  R L ( 43 ) By plugging the Vi from equation (42) and replacing β2S2 from equation (38), the following relation is obtained: Δ   RSSI n = 2  k - 1 k + 1  I o  R L ( 44 ) For ΔRSSI=1V, n=7 stages, RL=10000Ω, and k=4, from the above equation Io is calculated to be 12 mA. Therefore, each rectifier will be biased with two 12 mA current sources (one 12 ma current source for the I signal and a second 12 ma current source for the Q channel). This results in an approximately logarithmic voltage, which indicates the received signal-strength (RSSI).
The outputs of the limiters are coupled to the quadrature clocks of the IF mixers (I_in for mixer 322, Q_in for mixer 323, I_in for mixer 324, Q_in for mixer 325) and the IF clocks are coupled to the data input of the IF mixers. This configuration minimizes spurs at the output of the IF mixers because the signal being mixed is the IF clocks which is a clean sine wave, and therefore, has minimal harmonics. The limiting action of the programmable multiple stage amplifier on the I and Q data will have essentially no effect on the spurs at the output of the IF mixers. FIG. 17b shows the IF mixer clock signal spectrum which contains only odd harmonics. The IF signals do not have even harmonics in embodiments of the present invention using a fully differential configuration. The bandwidth of the m′th(=2n+1) harmonic is directly proportional to mfs, whereas its amplitude is inversely proportional to mfs. FIG. 17c shows the sinusoidal input spectrum of the IF clocks. FIG. 17d shows the IF mixer output spectrum.
A clock generator can be used to generate a quadrature sinusoidal signal with controlled amplitude. The clock generator can be located in the receiver, or alternatively the LO Generator, and provides a clean sinusoidal IF from the square wave output of the divider in the LO Generator for downconverting the IF signal in the receiver path to baseband. FIG. 18 shows a block diagram and signal spectrum of a clock generator. A sinusoidal signal is generated from a square-wave using cascaded polyphase. FIG. 18 shows a clock generator block diagram. The clock generator outputs clk_I and clk_Q for the IF mixer buffer (see FIG. 17). The clock generator includes a polyphase filter at 3 fs 360, a polyphase filter at 5 fs 362, and a low pass filter 364. FIG. 19a shows the input clock signal spectrum. FIG. 19b shows the spectrum after 3 fs 366 and 5 fs 368 polyphase. FIG. 19c shows the sinusoidal signal generation after the low pass filter 364.
The controller provides RC calibration to keep the differentiation gain process invariant. In order to reduce the effect of any high frequency coupling to the differentiator input, the differentiator gain is flattened out for frequencies beyond the band of interest. In addition to frequency discrimination, the differentiation process adds a 90 degrees phase shift to the incoming signal. This phase shift is inherent to the differentiation process. Since the output is in quadrature phase with the input (except for differing amplitude), cross multiplication of the input and output results in frequency information.
The input stage or pre-amplifier of the power amplifier includes an input differential pair comprising amplifying transistors 612, 614. Transistor 616 is a current source that biases the input differential pair. The presence of a current source provides many positive aspects including common mode rejection. The current is controlled by the voltage applied to the gate of transistor 616. The gate voltage should be chosen to prevent the transistor 616 from operating in the triode region. Triode operation of transistor 616 has a number of drawbacks. Primarily, since transistor 616 is supposed to act as a current source, its operation in the triode region can cause distortion in the current flowing into the transistor 612 and the transistor 614, and consequently gives rise to nonlinearity in the signal. Secondly, the triode behavior of transistor 616 will depend on temperature and process variations. Therefore, the circuit operation will vary over different process and temperature caners.
Capacitances associated with bias resistors may also be addressed. Consider a typical distributed model for a polysilicon (�poly� for short) resistor. Around 4 fF to substrate can be associated with every kilo-ohm of resistance in a poly resistor. This means that, for example in a 20 Kohm resistor, around 80 fF of distributed capacitance to the substrate exists. This can contribute to power loss because part of the power will be drained into the substrate. One way of biasing the input stage and the output stage is through a resistive voltage divider as shown in FIG. 26(a). The biasing of the input stage is shown for the transistor 616 in FIG. 25, however, those skilled in the art will readily appreciate that the same biasing circuit can be used for the transistor 614 (FIG. 25). One drawback from this approach, however, is that the gate of the transistor will see the capacitance from the two resistors 658, 660 of the voltage divider. Capacitor 662 is a coupling capacitor, which couples the previous stage to the voltage divider. Switch 664 is for powering down the stage of the power amplifier that is connected to the voltage divider. The switch 664 is on in normal operation and is off in power down mode.
FIG. 27 shows an exemplary bias circuit for the current source transistor 616 of FIG. 25. To fix the bias current of the circuit over temperature and process variation, a diode-connected switch transistor 672 may be used with a well-regulated current 670. The voltage generated across the diode-connected transistor 672 is applied to the gate of the current source transistor 616. Because of the mirroring effect of this connection and since all transistors move in the same direction over temperature and process caners, the mirrored current will be almost constant. The reference current is obtained by calibration of a resistor by the controller. The calibrated resistor can be isolated from the rest of the PA to prevent high frequency coupling through the resistor to other transceiver circuits. As those skilled in the art will appreciate, the exemplary bias circuit is not limited to the current source transistor of the PA and maybe applied to other transistors requiring accurate biasing currents.
As described above, the output of the PA can be independently matched to a 500 hm load. The matching circuit (inductors 646,650 and capacitors 648,652) is connected to the balun. Any non-ideality of the balun, bond wire impedance, pin/PCB capacitance, and other parasitics can be absorbed by the matching circuits. High-Q inductors can be used where possible. The loss in efficiency may also be tolerable with low power applications.
1st:f1 f1 x(1+1/N) f1 x(1 − 3/N)
f1 x(1 + 5/N)
3rd:3f1 f1 x(3−1/N) f1 x(3 + 3/N)
f1 x(3 − 5/N)
5th:5f1 f1 x(5+1/N) f1 x(5 − 3/N)
f1 x(5 + 5/N)
The maximum filtering is obtained by choosing N=1. Moreover, in this case, the frequency divider is eliminated. This lowers the power consumption and reduces the system complexity of the LO generator. However, the choice of N=1 may not be practical for certain embodiments of the present invention employing a low-IF receiver architecture with quadrature LO signals. The problem arises from the fact that the third harmonic of the VCO (at 3fi) mixed with the divider output (at f1) also produces a signal at 2f1 which has the same frequency as the main component of the RF clock output from the LO generator. With the configuration shown in FIG. 33, the following relations hold for the main harmonics:
−Cos (ω1 t)�⅓ Cos(3ω1 t)−Sin(ω1 t)�⅓ Sin(3ω1 t)→−⅓ Cos(2ω1 t) (47) and
For N=2, the LO generator output will have a frequency of 1.5f1, and the closest spurs will be located �f1 away from the output. These spurs can be rejected by positioning LC filters (not shown) at the output of each circuit in the LO generator. A second-order LC filter tuned to f0, with a quality factor Q, rejects a signal at a frequency of f as given in the following equation:  H  ( f )  = f Qf 0 [ 1 - ( f f 0 ) 2 ] + ( f Qf 0 ) 2 ( 49 ) The following discussion changes based on the Q value. Considering a Q of about 5 for the inductor, with f0=1.5f1, the spur located at 2.5f1 is rejected by about 15 dB by each LC circuit. This spur is produced at the LO generator output due to the mixing of the VCO third harmonic (at 3f1) with the divider output (at 0.5f1). This signal is attenuated by 10 dB since the third harmonic of a square-wave is one third of the main harmonic, 15 dB at the LC resonator at the mixers output tuned to 1.5f1, and another 15 dB at the output of the buffers (900,902 in FIG. 33). This gives a total rejection of 40 dB. When applied to the mixers in the transmitter, this LO generator output will upconvert the baseband data to 2.5f1. With LC filters (not shown) positioned at the upconversion mixers and PA output in the transmitter, another 15+15=30 dB rejection is obtained (FIG. 33).
FIG. 33(a) shows a signal passing through a limiting buffer 912 (such as the buffers implemented in the LO generator). When a large signal at a frequency of f accompanied with a small interferer at a frequency of Δf 911 away pass through a limiting buffer, at the limiter output the interferer produces two tones�Δf 914, 916 away from the main signal, each with 6 dB lower amplitude. Therefore, the spur at 2.5f1 will actually be 10+15+15+6=46 dB attenuated when it passes through the buffer, instead of the 40 dB calculated above. It will also produce an image at 0.5f1 which is 10+15+22+6=53 dB lower than the main signal. This will dominate the spur at 0.5f1 because of the third harmonic of the divider mixed with the VCO signal, which is more than 75 dB lower than the main signal.
Since the buffer is nonlinear, another major spur at the LO generator output is the third harmonic of the main signal located at 3�1.5f1. This signal will be 10+22=32 dB lower than the main harmonic. The 22 dB rejection results from an LC circuit (not shown) tuned to 1.5f1 (equation (49)) in the buffer. This undesired signal will not degrade the LO generator performance, since even if a perfect sinewave is applied to upconversion (or downconversion) mixers, due to hard switching action of the buffer, the mixer is actually switched by a square-wave whose third harmonic is only 10 dB lower. Thus, if a nonlinear PA is used in the transmitter, even with a perfect input to the PA, the third harmonic at the transmitter output will be 10+22+10=42 dB lower. The first 10 dB is because the third harmonic of a square-wave is one third of the main one, the 22 dB is due to the LC filter at the PA output, and the last 10 dB is because the data is spread in the frequency domain by three times. Any DC offset at the mixer input in the transmitter is upconverted by the LO, and produces a spur at f1. This spur can be attenuated by 13 dB for each LC circuit used (equation (49)). In addition, the signal at the mixer input in the transmitter is considerably larger (about 10-20 times) than the DC offset. Thus the spur at f1 will be about 13+13+26=52 dB lower than the main signal. All other spurs given in Table 1 are more than 55 dB lower at the LO generator output. The dominant spur is the one at 2.5f1 which is about 46 dB lower than the main signal.
V out � I=Cos(ω2 t)�Cos(ω1 t+θ)−Sin(ω2 t)�Sin(ω1 t) (50) and
V out � Q=Cos(ω2 t)�Sin(ω1 t)+Sin(ω2 t)�Cos(ω1 t+θ) (51) where ω1 is the VCO radian frequency, and ω2 is the divider radian frequency, equal to 0.5ω1. By simplifying equation (25) and equation (26), the signals at the output of mixers will be: V out_I = - Sin  ( θ 2 ) � Sin  ( ( ω 1 - ω 2 )  t + θ 2 ) + Cos  ( θ 2 ) � Cos  ( ( ω 1 + ω 2 )  t + θ 2 )   and ( 52 ) V out_Q = - Sin  ( θ 2 ) � Cos  ( ( ω 1 - ω 2 )  t + θ 2 ) + Cos  ( θ 2 ) � Sin  ( ( ω 1 + ω 2 )  t + θ 2 ) ( 53 ) The above equations show that regardless of the value of θ, the outputs are always in quadrature. However, other effects should be evaluated. First, a spur at ω1−ω2=0.5ω1 is produced at the output. This spur can be attenuated by 2�22=44 dB by the LC filters at the mixer and its buffer outputs. Thus, for 60 dB rejection, the single sideband mixers need to provide an additional 16 dB of rejection ( about 0.158). Based on equation (53), tan(θ/2)=0.158, or θ�18�, phase accuracy of better than 18� can generally be achieved. Second, phase error at the VCO output lowers the mixer gain (term Cos(θ/2) in equation (52) or (53)). For a phase error of 18�, the gain reduction is, however, only 0.1 dB, which is negligible. For θ=90� (a single-phase VCO), both sidebands are equally upconverted at the mixer output. However, the LC filters reject the lower sideband by about 44 dB. The mixer gain will also be 3 dB lower. This will slightly increase the power consumption of the LO generator. If θ=180� (the VCO I and Q outputs are switched), the lower sideband is selected, and the desired sideband is completely rejected.
Similarly, the LO generator will not be sensitive to the phase imbalance of the divider outputs if the VCO is ideal. However, if there is some phase inaccuracy at both the divider and VCO outputs, the LO generator outputs will no longer be in quadrature. In fact, if the VCO output has a phase error of q1 and the divider output has a phase error of q2, the LO generator outputs will be: V out_I = - Sin  ( θ 1 - θ 2 2 ) � Sin  ( ( ω 1 - ω 2 )  t + θ 1 - θ 2 2 ) + Cos  ( θ 1 + θ 2 2 ) � Cos  ( ( ω 1 + ω 2 )  t + θ 1 + θ 2 2 )   and  ( 54 ) V out_Q = - Sin  ( θ 1 + θ 2 2 ) � Cos  ( ( ω 1 - ω 2 )  t + θ 1 - θ 2 2 ) + Cos  ( θ 1 - θ 2 2 ) � Sin  ( ( ω 1 + ω 2 )  t + θ 1 + θ 2 2 ) ( 55 ) This shows that the outputs still have phases of 0 and 90�, but their amplitudes are not equal. The amplitude imbalance is equal to: Δ   A A = 2   Cos  ( θ 1 + θ 2 2 ) - Cos  ( θ 1 - θ 2 2 ) Cos  ( θ 1 + θ 2 2 ) + Cos  ( θ 1 - θ 2 2 ) = 2   tan  ( θ 1 2 ) � tan   ( θ 2 2 ) ( 56 ) If θ1 and θ2 are small and have an equal standard deviation, that is, the phase errors in the VCO and divider are the same in nature, then the output amplitude standard deviation will be: σ A ≈ ( σ θ ) 2 2 ( 57 ) where σA is the standard deviation of the output amplitude, and σθ is the phase standard deviation in radians. Equation (57) denotes that the phase inaccuracy in the VCO and divider has a second order effect on the LO generator. For instance, if θ1 and θ2 are on the same order and about 10�, the amplitude imbalance of the output signals will be only about 1.5%. In this case, the lower sideband will be about 15 dB rejected by the mixers, which will lead to a total attenuation of about 22+22+15=59 dB. This shows that the LO generator is robust to phase errors at the VCO or divider outputs, since typically phase errors of less than 5� can be obtained on chip.
Transistors 818 and 820 form a cross-coupled pair that injects a current into tank #1 in which the current through the transistor 818 is exactly 180 degrees out of phase with the current in the transistor 820. Likewise, transistors 822 and 824 form a cross-coupled pair that injects a current into tank #2 in which the current through the transistor 822 is exactly 180 degrees out of phase with the current in the transistor 824. The first set of coupling devices 834, 836 injects a current into tank #1 that is 90 degrees out of phase with current injected respectively by the transistors 818, 820. The second set of coupling devices 838, 840 injects a current into tank #2 that is 90 degrees out of phase with the current injected respectively by the transistors 822, 824. The tank impedances cause a frequency dependent phase shift. By varying the amplitude of the coupled signals, the frequency of oscillation changes until the phase shift through the tanks results in a steady-state solution. Varying the bias of the current source controls the gm of the coupling devices. Current sources 812, 816 provide control of VCO tuning. Current sources 810, 814 provide segmentation of the VCO tuning range.
FIG. 36(a) shows the typical tuning curve of the wide tuning range VCO before and after segmentation. The horizontal axis is voltage. The vertical axis is frequency. FIG. 36(b) shows how segmentation is used to divide the tuning range and linearize the tuning curve. The linear tuning curves correspond to different VCO segments. The slope of the linear tuning curves is a result of VCO tuning. The horizontal axis is voltage. The vertical axis is frequency.
FIG. 40 shows an exemplary embodiment of the RC calibration circuit using polyphase filtering. The RC calibration circuit uses the reference clock from the LO generator to adjust the RC value in two polyphase filters 280, 282 in successive steps until an optimum value has been selected. In this process, the two polyphase filters 280, 282 provide signal rejection that is dependent upon the value of w=(RC)−1 to which they are tuned by control logic 286. Initially, the first filter (Polyphase A) 280 is tuned to a frequency less than the frequency of the reference clock (reference frequency), and the second filter (Polyphase B) 282 is tuned to a frequency greater than the reference frequency by control logic 286. The signals at the outputs of the polyphase filters are detected with a received-signal-strength-indicator (RSSI) block 284, 285 in each path. The polyphase A filter is coupled to RSSI block 284 and the polyphase B filter is coupled to RSSI block 285.
With an input dynamic range of 50 dB, the RSSI circuit is designed to detect the levels of rejection provided by the polyphase filtering. The outputs of RSSI block 284 and RSSI block 285 are coupled to a comparator 288 where the level of signal rejection of each polyphase filter is compared by comparator 288. The outputs of the RSSI blocks are also coupled to the control logic 286. The control logic 286 determines from the RSSI outputs which polyphase filter has a lower amount of signal suppression. Then, the control logic 286 adjusts the frequency tuning of that filter in an incremental step via the control logic 286. This is done by either increasing the tuned frequency of the first filter (polyphase A) filter 280, or by decreasing the tuned frequency of the second filter (polyphase B) 282 by changing the appropriate 4-bit control word. This process continues in successive steps until the 4-bit control word in each branch are identical, at which point, the RC values of the two polyphase filters are equal. The 4-bit control word provides a maximum deviation of only �5%.
Complementary MOS switches or other switches known in the art, can be used in the capacitor array. The capacitor array can include any number of capacitors. In the exemplary embodiment, the capacitor array capacitors 290, 292, 294, 296, 298 are connected in parallel. Switches 300, 302, 304, 306 are used to switch the capacitors 292,294,296,298, respectively, in and out of the capacitor array. In the described embodiment, capacitor 290 is 2.4 pF, capacitor 292 is 2.4 pF, capacitor 294 is 1.2 pF, capacitor 296 is 0.6 pF, capacitor 298 is 0.3 pF. The switch positions are nominally selected to produce an equivalent capacitance equal to 4.8 pF. A code of �0111� means that capacitors 294, 296, 298 are switched out of the capacitor array and capacitors 290, 292 are in parallel.
The switches can be binary-weighted in size and the switch sizes can be chosen according to tradeoffs regarding parasitic capacitances and frequency limitations based on the on-resistance of the CMOS switches. The capacitive error resulting from the parasitic capacitance in each capacitive array does not result in frequency error between the three polyphase stages of the RC calibration circuit in the controller. This is achieved by using the same capacitor array in each filter, and by scaling the resistance accordingly in each case. Scalling resistances, relative to those in the fundamental polyphase filter, by factors of ⅓ and ⅕ in the 3rd and 5th harmonic filters respectively, are achieved with a high degree of accuracy with proper layout. Similarly, RC tuning in all other blocks utilizing the calibrated code is optimized when an identical capacitive array is used, scaling only the resistance value in tuning to the desired frequency. The capacitors in the capacitive arrays are laid out in 100 fF increments, to improve the matching and parasitic fringing effects.
FIG. 42 shows an exemplary embodiment of the bandgap calibration circuit. The bandgap calibration circuit uses the reference clock provided from the LO generator and a reference resistor RREF 236 to adjust a tunable resistance value RPOLY 238 in a compare-and-increment loop until an optimum value is obtained. In embodiments of the present invention which are integrated into a single IC, the reference resistor RREF 236 can be off-chip to provide improved calibration accuracy. A 4-bit control word is output to accurately calibrate the resistors in the transmitter, receiver and LO generator within �2%. Transistors 224, 226, 228, 230, 232, 234 form a cascode current with a reference current IREF. The transistors 224, 230 each have their gates tied to their respective sources to set up the reference current IREF. By tying the gates of the transistors 224, 230, respectively to the gates of the transistors 226, 232, the reference current IREF is mirrored to the reference resistor RREF 236. Similarly, by tying the gates of the transistors 228, 234, respectively to the gates of the transistors, the reference current IREF is also mirrored to the tunable resistor RPOLY 238. The voltage generated across the tunable resistor RPOLY 238 is compared, using a latched comparator 240, to the voltage generated across the reference resistor RREF 236. The value of the tunable resistor RPOLY 236 is incremented in successive steps, preferably, every 0.5 μs, through the utilization of control logic 242 that is clocked, by way of example, at 2 MHz. This process continues until the voltage VPOLY across the tunable resistor RPOLY 238 matches the voltage VREF across the off-chip reference resistor RREF 236 causing the output of the comparator to change states and disable the control logic 242. Once the control logic is disabled, the 4-bit control word can be used to accurately calibrate the resistors in the transmitter, receiver and LO generator.
In the transmitter, receiver and LO generator non-silicided polysilicon resistors can be used. As those skilled in the art will appreciate, other resistor technologies can also be used. Non-silicided polysilicon resistors have a high sheet resistance of 200-Ω/square along with desirable matching properties. A switching resistor array as shown in FIG. 44 can be used to calibrate a resistor. The array includes serial connected resistors 208, 210, 212, 214, 216, which, by way of example, have resistances of 2200Ω, 1100Ω, 550Ω, 275Ω, and 137Ω, respectively. The resistors 210, 212, 214, 216 include a bypass switch for switching the resistors in and out of the array. The switch positions are nominally selected to produce an equivalent of 3025Ω. This resistance value has been chosen as a convenience to match the value used in generating an accurate bandgap reference current. A 4-bit calibration code 206 is used to control the total resistance in this array. As seen in FIG. 44, the resistances are binary-weighted in value and the accurate scaling of each incremental resistance results by placing the largest resistor (2200Ω) 208 in series to generate each value. In the described embodiment, the incremental resistances shown in FIG. 44 are chosen so that the total resistance in the array covers a range 30% above and below its nominal value, with a maximum resistance error of +2% determined by the incremental resistance switched by the LSB. The range of resistance covered by the array is sufficient to cover typical process variations in a semiconductor process. A series resistive array may be desirable as opposed to a parallel resistive array because of the smaller area occupied on the wafer.
Since the antenna is usually single-ended, differential applications generally require a mechanism to convert the antenna signal from single-ended to differential for connection to the differential low noise amplifier (LNA) or the differential PA. The circuit implementation for a single-ended to differential LNA is shown in FIGS. 46 and 47. LC circuit, 646, 648 and the CL circuit 652, 650 matches the PA to the antenna when the PA is on and the LNA is off (as shown in FIG. 46), and matches the LNA to the antenna when the LNA is on and the PA is off (as shown in FIG. 47). When the LNA is off it only introduces a capacitive loading to the PA. The matching circuit can be designed to compensate for this additional capacitance.
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*Feb 28, 2007Aug 28, 2008Ahmadreza RofougaranMethod and System for Using a Phase Locked Loop for Upconversion in a Wideband Polar TransmitterUS20120231752 *May 29, 2007Sep 13, 2012Razieh RoufoogaranMethod and System for a Configurable Front EndWO2013152795A1 *Apr 12, 2012Oct 17, 2013Epcos AgRssi system and bias method for amplifier stages in rssi systemsWO2014108179A1 *Jan 9, 2013Jul 17, 2014Qualcomm Technologies, Inc.Amplifier circuit with improved accuracy* Cited by examinerClassifications U.S. Classification455/66.1, 455/78, 361/301.1, 455/86, 327/434, 455/73, 361/281, 361/270, 327/427, 455/76International ClassificationH03H21/00, H03H11/12Cooperative ClassificationH03F3/45475, H03F2203/45528, H03F3/245, H03H11/22, H03F1/56, H03H11/1291, H03H7/42, H03F2200/451, H03H2011/0494, H03F2203/45138, H03F2203/45638, H03G3/001, H03L7/099, H03F3/19, H03B27/00, H03H11/344, H03F2203/45386, H03F2200/336, H03H21/0012, H03B21/01, H03G11/00, H03F3/45179, H04B17/0037, H04B17/0027, H03L7/18, H04B17/0012, H03H21/0001, H03J2200/10, H03F2200/318, H03F2203/45526European ClassificationH04B17/00A2S, H04B17/00A3S, H03H11/22, H03F3/45S1K, H03H7/42, H03G3/00D, H03G11/00, H03H11/34D, H03L7/099, H04B17/00A1T, H03B21/01, H03F3/24B, H03L7/18, H03F3/45S1B, H03F1/56, H03F3/19, H03B27/00, H03H11/12F, H03H21/00B, H03H21/00ALegal EventsDateCodeEventDescriptionSep 24, 2011FPAYFee paymentYear of fee payment: 8Sep 25, 2007FPAYFee paymentYear of fee payment: 4Mar 6, 2001ASAssignmentOwner name: BROADCOM CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROFOUGARAN, AHMADREZA;ROFOUGARAN, MARYAM;KHORRAM SHAHLA;REEL/FRAME:011581/0979;SIGNING DATES FROM 20010220 TO 20010221Owner name: BROADCOM CORPORATION 16215 ALTON PARKWAYIRVINE, CAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROFOUGARAN, AHMADREZA /AR;REEL/FRAME:011581/0979;SIGNINGDATES FROM 20010220 TO 20010221RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms 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