Source: http://www.google.com/patents/US20020174278?dq=6978253
Timestamp: 2016-05-06 19:13:35
Document Index: 6764702

Matched Legal Cases: ['art 14', 'art 14', 'art 14', 'art 23', 'art 24', 'art 25', 'art 24', 'art 23', 'art 23', 'art 23', 'art 23', 'art 23', 'art 24', 'art 24', 'art 23', 'art 24', 'art 24', 'art 24', 'art 43', 'art 25', 'art 23', 'art 25', 'art 25', 'art 25', 'art 23', 'art 23', 'art 25', 'art 23', 'art 25', 'art 23', 'art 25', 'art 43', 'art 43', 'art 14', 'art 23', 'art 25', 'art 43', 'art 43', 'art 43', 'art 43', 'art 23', 'art 43', 'art 14', 'art 23', 'art 25', 'art 23', 'art 23', 'art 23', 'art 23', 'art 23', 'art 23', 'art 23', 'art 23', 'art 24', 'art 24', 'application No. 2001']

Patent US20020174278 - Information processing apparatus and method of controlling an access level - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn information processing apparatus includes a process part implementing an access to a designated address having an access level, an access detector detecting the access, and an access part being capable of changing the access level of the designated address when the access is detected by the access...http://www.google.com/patents/US20020174278?utm_source=gb-gplus-sharePatent US20020174278 - Information processing apparatus and method of controlling an access levelAdvanced Patent SearchPublication numberUS20020174278 A1Publication typeApplicationApplication numberUS 10/095,091Publication dateNov 21, 2002Filing dateMar 12, 2002Priority dateMay 15, 2001Also published asDE60211801D1, DE60211801T2, EP1262857A2, EP1262857A3, EP1262857B1, US7107377Publication number095091, 10095091, US 2002/0174278 A1, US 2002/174278 A1, US 20020174278 A1, US 20020174278A1, US 2002174278 A1, US 2002174278A1, US-A1-20020174278, US-A1-2002174278, US2002/0174278A1, US2002/174278A1, US20020174278 A1, US20020174278A1, US2002174278 A1, US2002174278A1InventorsShimpei Komatsu, Yusuke KawasakiOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (1), Classifications (25), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetInformation processing apparatus and method of controlling an access level
US 20020174278 A1Abstract
An information processing apparatus includes a process part implementing an access to a designated address having an access level, an access detector detecting the access, and an access part being capable of changing the access level of the designated address when the access is detected by the access detector. Images(11) Claims(12)
What is claimed is: 1. An information processing apparatus, comprising: a process part implementing an access to a designated address having an access level; an access detector detecting the access; and an access part being capable of changing the access level of the designated address when the access is detected by the access detector. 2. The information processing apparatus as claimed in claim 1, wherein the access part includes a level holding part outputting an access level which is pre-set at the designated address when the access to the designated address is detected by the access detector, an access allowance setting part in which an access allowance address for every access level is set, an access control part selecting the access allowance address which is set at the access allowance setting part and which corresponds to the access level output from the level holding part, and thereby the access by the process part is allowed when the designated address accessed by the process part agrees with the access allowance address. 3. The information processing apparatus as claimed in claim 1, wherein the access detector includes a first comparator detecting whether the address accessed by the process part agrees or disagrees with an address whose access level is changed, a second comparator detecting whether or not an access control signal output from the process part indicates an instruction fetch, and a determination part determining that the first comparator detects the address accessed by the process part agrees with the address whose access level is changed and the second comparator detects the access control signal indicating the instruction fetch. 4. The information processing apparatus as claimed in claim 1, wherein the access level of the designated address is controlled to change from a first level where an access to a limited address is allowed to a second level where an access to all addresses is allowed. 5. The information processing apparatus as claimed in claim 2, wherein the access control part includes a select part selecting the access allowance address corresponding to the access level, a comparison part comparing the access allowance address selected by the select part and the designated address, and a control part allowing the process part to access the designated address when the designated address agrees with the access allowance address. 6. The information processing apparatus as claimed in claim 2, wherein the access level of the designated address is changed from a second level where an access to all addresses is allowed to a first level where an access to a limited address is allowed, and the access level set at the level holding part is changed to the first level. 7. A method of controlling an access level of a designated address accessed by a process part of an information processing apparatus, comprising: a) detecting the access by the process part to the designated address; and b) being capable of changing the access level of the designated address when the access is detected. 8. The method of controlling the access level of the designated address accessed by the process part of the information processing apparatus, as claimed in claim 7, wherein the access level of the designated address is changed when an instruction fetch is detected. 9. The method of controlling the access level of the designated address accessed by the process part of the information processing apparatus, as claimed in claim 7, wherein the access level of the designated address is changed when the address accessed by the process part agrees with an address whose access level is changed. 10. The method of controlling the access level of the designated address accessed by the process part of the information processing apparatus, as claimed in claim 7, wherein the access to the designated address can be implemented when the designated address agrees with a pre-set access allowance address. 11. The method of controlling the access level of the designated address accessed by a process part of the information processing apparatus, as claimed in claim 7, wherein the access level of the designated address is limited to change from a first level where an access to a limited address is allowed to a second level where an access to all addresses is allowed. 12. The method of controlling the access level of the designated address accessed by the process part of the information processing apparatus, as claimed in claim 7, wherein the access level of the designated address is changed from a second level where an access to all addresses is allowed to a first level where an access to a limited address is allowed.
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to information processing apparatuses and methods of controlling an access level, and more particularly, to an information processing apparatus and a method of controlling an access level by which it is possible to change an access level in every process. [0003] 2. Description of the Related Art [0004] An access allowance area including a device is set for every execution unit of a program such as a task, in a system including a central processing unit (CPU). It is controlled to set the access allowance at a level that is provided for every task. Plural tasks are executed by a manager administrative program. The manager administrative program has a privileged level in which it is allowed to access all areas, in order to manage respective tasks. The CPU makes the manager administrative program execute a change of the task based on an interrupt caused by hardware or software. [0005] According to a related art information processing apparatus, it executes to change a level of the task to the level of the manager administrative program by detecting the interrupt. [0006] However, according to the related art information processing apparatus, if a process to prohibit interrupting to the CPU is implemented, for example, it may be possible to execute the task at the privileged level. Hence, the related art information processing apparatus may have a problem in that it may be possible to alter a program of another task or read out highly secret data such as an encryption key. SUMMARY OF THE INVENTION [0007] Accordingly, it is a general object of the present invention to provide a novel and useful information processing apparatus and method of controlling an access level, the information apparatus having a high security level, in which one or more of the problems described above are eliminated. [0008] Another and more specific object of the present invention is to provide an information processing apparatus, including a process part implementing an access to a designated address having an access level, an access detector detecting the access, and an access part being capable of changing the access level of the designated address when the access is detected by the access detector. [0009] The above objects of the present invention are also achieved by a method of controlling an access level of a designated address accessed by a process part of an information processing apparatus, including a) detecting the access by the process part to the designated address, and b) being capable of changing the access level of the designated address when the access is detected. [0010] According to the above invention, it is possible to limit the ability to change the access level of tasks other than a privileged task. It is possible to avoid generating a bug in each of tasks or to prevent a memory from being destroyed intentionally or information from leaking out by limiting the ability to change the access level. As a result, it is possible to realize a high security level of the information processing apparatus. [0011] For example, the access part may include a level holding part outputting an access level which is pre-set at the designated address when the access to the designated address is detected by the access detector, an access allowance setting part in which an access allowance address for every access level is set, an access control part selecting the access allowance address which is set at the access allowance setting part and which corresponds to the access level output from the level holding part, and thereby the access by the process part is allowed when the designated address accessed by the process part agrees with the access allowance address. The access control part may include a select part selecting the access allowance address corresponding to the access level, a comparison part comparing the access allowance address selected by the select part and the designated address, and a control part allowing the process part to access the designated address when the designated address agrees with the access allowance address. The access detector may include a first comparator detecting whether the address accessed by the process part agrees or disagrees with an address whose access level is changed, a second comparator detecting whether or not an access control signal output from the process part indicates an instruction fetch, and a determination part determining that the first comparator detects the address accessed by the process part agrees with the address whose access level is changed and the second comparator detects the access control signal indicating the instruction fetch. [0012] In addition, the access level of the designated address may be changed when an instruction fetch is detected. The access level of the designated address may be changed when the address accessed by the process part agrees with an address whose access level is changed. The access to the designated address may be implemented when the designated address agrees with a pre-set access allowance address. [0013] Other objects, features, and advantages of the present invention will be come more apparent from the following detailed description when read in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS [0014] [0014]FIG. 1 is a block diagram of an embodiment according to the present invention; [0015] [0015]FIG. 2 is a data structure chart of an external read-only memory (ROM) of the embodiment according to the present invention; [0016] [0016]FIG. 3 is a data structure chart of a random access memory (RAM) of the embodiment according to the present invention; [0017] [0017]FIG. 4 is a data structure chart of an internal ROM of the embodiment according to the present invention; [0018] [0018]FIG. 5 is a chart for explaining an access level of the embodiment according to the present invention; [0019] [0019]FIG. 6 is a block diagram of an access detector of the embodiment according to the present invention; [0020] [0020]FIG. 7 is a block diagram of an access control part of the embodiment according to the present invention; [0021] [0021]FIG. 8 is a block diagram of an access allowance setting part of the embodiment according to the present invention; [0022] [0022]FIG. 9 is a flow chart of a process of a manager administrative program of the embodiment according to the present invention; [0023] [0023]FIG. 10 is a flow chart of a process of a level change routine of the embodiment according to the present invention; [0024] [0024]FIG. 11 is a flow chart of a process of a level change routine of the embodiment according to the present invention.
DETAILED DESCRIPTION OF THE PREFERED EMBODIMENTS [0025] A description will now be given, with reference to the drawings, of embodiments of the present invention. [0026] [0026]FIG. 1 is a block diagram of an embodiment according to the present invention. [0027] Referring to FIG. 1, an information processing system 1 includes an information processing apparatus 11, an external ROM 12, a RAM 13, an interface part 14, and peripheral equipment 15. [0028] The information processing apparatus 11 exchanges a program and data with the external ROM 12, the RAM 13, and with the peripheral equipment 15 through the interface part 14. The information processing apparatus 11 executes data processing based on the program. The program executed by the information processing apparatus 11 and fixed data used for the program are stored in the external ROM 12. [0029] [0029]FIG. 2 is a data structure chart of the external ROM 12 of the embodiment according to the present invention. [0030] Referring to FIG. 2, each of instructions (data) ppt111 through ppt11 e, of which a task program Pt1 is comprised, is stored in a respective address add51 through add5 e of the external ROM 12. Each of instructions ppt211 through ppt21 f, of which a task program Pt2 is comprised, is stored in a respective address add61 through add6 f of the external ROM 12. Each of instructions ppt311 through ppt31 g, of which a task program Pt3 is comprised, is stored in a respective address add71 through add7 g of the external ROM 12. Each of data d11 through d1 h, of which the fixed data D is comprised, is stored in a respective address add81 through add8 h of the external ROM 12. The task programs Pt1 through Pt3 and the data D are read out by an access from the CPU 21 and supplied to the CPU 21. [0031] The RAM 13 is used as a storage area for jobs of a process by the information processing apparatus 11. [0032] [0032]FIG. 3 is a data structure chart of the RAM 13 of the embodiment according to the present invention. [0033] Referring to FIG. 3, each of data Dt111 through Dt11 i, of which task data Dt1 are comprised and which is used in the task program Pt1, is stored in a respective address add91 through add9 i of the RAM 13. Each of data Dt211 through Dt21 j, of which task data Dt2 are comprised and which is used in the task program Pt2, is stored in a respective address add101 through add10 j of the RAM 13. Each of data Dt311 through Dt31 k, of which task data Dt3 are comprised and which is used in the task program Pt3, is stored in a respective address add111 through add11 k of the RAM 13. Each of addresses add121 through add121 is used as a work area W. [0034] The interference part 14 exchanges data between the information processing apparatus 11 and the peripheral equipment 15. [0035] The information processing apparatus 11 is, for example, comprised of one chip of a large scale integration circuit (LSI). The information processing apparatus 11 includes the CPU 21, an access detector 22, a level holding part 23, an access control part 24, an access allowance setting part 25, and an internal ROM 26. [0036] The CPU 21 executes an operation process. The CPU 21 can access and exchange data with the internal ROM 26, the external ROM 12, the RAM 13 and the peripheral equipment 15, through the access control part 24. In addition, the CPU 21 manages the manager administrative program stored in the internal ROM 26 and a change of an access level by level change routines RA and RB. [0037] [0037]FIG. 4 is a data structure chart of the internal ROM 26 of the embodiment according to the present invention. [0038] Referring to FIG. 4, each of instructions pRA11 through pRA1 a, of which the level change routine RA is comprised, is stored in a respective address add11 through add1 a of the internal ROM 26. Each of instructions pRB11 through pRB1 b, of which the level change routine RB is comprised, is stored in a respective address add21 through add2 b of the internal ROM 26. Each of instructions ppa11 through ppa1 c, of which a manager administrative program PA is comprised, is stored in a respective address add31 through add3 c of the internal ROM 26. Each of data ds11 through ds1 d, of which a system data Ds is comprised, is stored in a respective address add41 through add4 d of the internal ROM 26. The level change routines RA and RB and the system data Ds are read out by an access requirement of the CPU 21 and supplied to the CPU 21. [0039] Here, the access level will be described. [0040] The access level is information for determining an area where an access from the CPU 21 to the external ROM 12, the RAM 13, the peripheral equipment 15, and the internal ROM 26 is allowed. The access level is comprised of four levels of L0 through L3. [0041] [0041]FIG. 5 is a chart for explaining an access level of the embodiment according to the present invention. FIG. 5-(A) is a chart for explaining an access level with regard to an access to the internal ROM 26. FIG. 5-(B) is a chart for explaining an access level with regard to an access to the external ROM 12. FIG. 5-(C) is a chart for explaining an access level with regard to an access to the RAM 13. [0042] The level L0 is an access level where an access to all addresses is allowed. [0043] Referring to FIG. 5, the level L1 is an access level where an access to the task program Pt1 and the task data Dt1 used in the task program Pt1 is allowed. The level L2 is an access level where an access to the task program Pt2 and the task data Dt2 used in the task program Pt2 is allowed. The level L3 is an access level where an access to the task program Pt3 and the task data Dt3 used in the task program Pt3 is allowed. The access level can be changed for every process of the CPU 21. [0044] When the access level is changed from a lower access level to an upper access level, for example from the access level L1 through L3 to the access level L0, the level change routine RA is executed by the CPU 21. When the access level is changed from the upper access level to the lower access level, for example from the access level L0 to the access level L1 through L3, the level change routine RB is executed by the CPU 21. [0045] Here, the access detector 22 will be described with reference to FIG. 6. [0046] [0046]FIG. 6 is a block diagram of the access detector 22 of the embodiment according to the present invention. [0047] Referring to FIG. 6, the access detector 22 includes comparators 31 and 32 and a NOT-AND (NAND) gate 33. [0048] A first address ADD1 and a second address ADD2 are supplied from the CPU 21 to the comparator 31. The first address ADD1 is an address for data to access next. The second address ADD2 is an address for data after the change of the level of an access right is implemented. When the first address ADD1 agrees with the second address ADD2, the comparator 31 outputs “1”. When the first address ADD1 disagrees with the second address ADD2, the comparator 31 outputs “0”. [0049] An access control signal ACS and another access control signal indicating an instruction fetch IF are supplied from the CPU 21 to the comparator 32. When the ACS agrees with the IF, the comparator 32 outputs “1”. When the ACS disagrees with the IF, the comparator 32 outputs “0”. [0050] Outputs of the comparators 31 and 32 are supplied to the NAND gate 33. The NAND gate 33 outputs NAND logic of the output of the comparators 31 and the output of the comparators 32. When both outputs of the comparators 31 and 32 are “1”, the output of the NAND gate 33 is “0”. When the output of at least either of the comparators 31 and 32 is “0”, the output of the NAND gate 33 is “1”. [0051] Thus, the NAND gate 33 outputs “0”, when the address to access next agrees with the address of the level change routine RA and the access control signal indicates the instruction fetch. It is possible to recognize whether an access to the address of the level change routine RA is implemented, based on the output of the NAND gate 33. [0052] The output of the access detector 22 is supplied to the level holding part 23. When the output of the access detector 22 is “0”, the access level L0 is set at the level holding part 23. That is, when the level change routine RA is implemented, the access level L0 is held at the level holding part 23. [0053] The access level that is pre-set for every task program Pt1, Pt2, and Pt3 is held at the level holding part 23 by the level change routine RB. The access level held at the level holding part 23 is supplied to the access control part 24. [0054] The access control part 24 implements an access control to an address of the access requirement of the CPU 21, based on the access level held at the level holding part 23. [0055] Here, the access control part 24 will be described with reference to FIG. 7. [0056] [0056]FIG. 7 is a block diagram of the access control part 24 of the embodiment according to the present invention. [0057] Referring to FIG. 7, the access control part 24 includes a selector 41, a comparator 42, and a control part 43. [0058] A first access allowance address Aal1 through a third access allowance address Aal3 are supplied from the access allowance setting part 25 to the selector 41. In addition, the access levels L0 through L3 held at the level holding part 23 are supplied to the selector 41. [0059] Here, the access allowance setting part 25 will be described with reference to FIG. 8. [0060] [0060]FIG. 8 is a block diagram of the access allowance setting part 25 of the embodiment according to the present invention. [0061] Referring to FIG. 8, the first access allowance address Aal1 through the third access allowance address Aal3 are stored at the access allowance setting part 25, containing access levels L1 through L3 respectively. [0062] Referring back to FIG. 7, an access allowance address corresponding to an access level held at the level holding part 23 is selected and supplied to the comparator 42 by the selector 41. For example, if the access level L1 is held at the level holding part 23, the first access allowance address Aal1 is selected from the first access allowance address Aal1 through the third access allowance address Aal3 supplied from the access allowance setting part 25, and supplied to the comparator 42 by the selector 41. Furthermore, if the access level L2 is held at the level holding part 23, the second access allowance address Aal2 is selected from the first access allowance address Aal1 through the third access allowance address Aal3 supplied from the access allowance setting part 25, and supplied to the comparator 42 by the selector 41. In addition, if the access level L3 is held at the level holding part 23, the third access allowance address Aal3 is selected from the first access allowance address Aal1 through the third access allowance address Aal3 supplied from the access allowance setting part 25, and supplied to the comparator 42 by the selector 41. [0063] The comparator 42 compares an address supplied from the CPU 21 and the address supplied from the selector 41. When the address supplied from the CPU 21 agrees with the address supplied from the selector 41, the comparator 42 outputs “0” indicating allowance. When the address supplied from the CPU 21 disagrees with the address supplied from the selector 41, the comparator 42 outputs “1” indicating disallowance. The output of the comparator 42 is supplied to the control part 43. [0064] An address line, a data line, and an access control line of the CPU 21 are connected with one end of the control part 43. The other address line, the other data line, and the other access control line, which are on a bus side and are connected with the external ROM 12, the RAM 13, the interface part 14, the level holding part 23, the access allowance setting part 25, and the internal ROM 26, are connected with the other end of the control part 43. The control part 43 controls the exchange of data and signals between the address line, the data line, and the access control line of the CPU 21 and the address line, the data line, and the access control line of the bus side, based on the outputs of the comparator 42. [0065] For example, when “0” indicating allowance is supplied from the comparator 42 to the control part 43, it is possible to control to exchange the data and signals between the address line, the data line, and the access control line of the CPU 21 and the address line, the data line, and the access control line of the bus side, based on the outputs of the comparator 42. In addition, for example, when “1” indicating disallowance is supplied from the comparator 42 to the control part 43, it is impossible to control to exchange the data and signals between the address line, the data line, and the access control line of the CPU 21 and the address line, the data line, and the access control line of the bus side, based on the outputs of the comparator 42. [0066] When the access level L0 is held at the level holding part 23, the selector 41 outputs an address causing the comparator 42 to output “0” indicating allowance in a case where any address is supplied from the CPU 21 to the selector 41. [0067] As described above, the control part 43 controls to exchange the address, the data, and the access control signal between the side of the CPU 21 and the bus side. As a result, it is possible to control the access from the CPU 21 to the external ROM 12, the RAM 13, the interface part 14, the level holding part 23, the access allowance setting part 25, and the internal ROM 26. For example, when the access level L1 is held at the level holding part 23, it is possible to access an address corresponding to the first access allowance address Aal1. That is, it is possible to access only the first task program Pt1 and the first task data Dt1 but impossible to access the second task program Pt2, the second task data Dt2, the third task program Pt3, and the third task data Dt3. In addition, when the access level L2 is held at the level holding part 23, it is possible to access an address corresponding to the second access allowance address Aal2. That is, it is possible to access only the second task program Pt2 and the second task data Dt2 but impossible to access the first task program Pt1, the first task data Dt1, the third task program Pt3, and the third task data Dt3. Furthermore, when the access level L3 is held at the level holding part 23, it is possible to access an address corresponding to the third access allowance address Aal3. That is, it is possible to access only the third task program Pt3 and the third task data Dt3 but impossible to access the first task program Pt1, the first task data Dt1, the second task program Pt2, and the second task data Dt2. [0068] Next a process of the CPU 21 will be described with reference to FIG. 9. [0069] [0069]FIG. 9 is a flow chart of a process of the manager administrative program of the embodiment according to the present invention. [0070] In step S1-1, the CPU 21 implements a managing process for managing an execution of the program. Since the managing process is implemented for all controlling, the access level L0 is set as an access level of the managing process so that it is possible to access all devices. [0071] In step S1-2, it is determined whether or not another program such as the first task program Pt1 is required to be executed. If it is determined that another program is required to be executed in step S1-2, the level change routine RB is executed in step S1-3. [0072] The level change routine RB is a process for changing the access level from the upper access level to the lower access level. That is, the level change routine RB is a process for changing the access level L0 set by the managing process to the access level L1 pre-set in the first task program Pt1. [0073] [0073]FIG. 10 is a flow chart of a process of the level change routine of the embodiment according to the present invention. [0074] The CPU 21 accesses the level holding part 23 in step S2-1. In step S2-2, the access level which is pre-set at another program is written in the level holding part 23. In a case of the first task program Pt1, the access level L1 is held at the level holding part 23. [0075] Referring back to FIG. 9, after the level change routine RB is determined to be completed in step S1-4, namely after the access level is changed from the level L0 to the level L1, the other program that is the first task program Pt1 is executed in step S1-5. The first task program Pt1 can access the device when the access level is L1. That is, the first task program Pt1 can access the level change routines RA and RB of the internal ROM 26, the first task program Pt1 and the data D of the external ROM 12, and the first task data Dt1 and the work area W of the RAM 13. [0076] After the other program is terminated in step S1-6, the level change routine RA is executed in step S1-7. The level change routine RA is a process for changing the access level from the lower access level to the upper access level. That is, the level change routine RA is a process for changing the access level of the other program to the access level L0 of the manager administrative program. [0077] [0077]FIG. 11 is a flow chart of a process of a level change routine of the embodiment according to the present invention. [0078] After the level change routine RA is executed, the CPU 21 supplies the address of the level change routine to the comparator 31. In addition, the CPU 21 supplies an access control signal indicating the instruction fetch to the comparator 32. [0079] When the access control signal indicates the instruction fetch, the comparator 32 outputs “1”. [0080] When an address to access corresponds to the pre-set address of the level change routine RA, the comparator 31 outputs “1”. When both of the comparators 31 and 32 output “1”, the NAND gate 33 outputs “0”, and thereby the access level held at the level holding part 23 becomes L0. When the access level held at the level holding part 23 is L0, the access to all of the devices is allowed by the access control part 24. [0081] When the access to all of the devices can be allowed by the access control part 24, the level change routine RA is terminated in step S1-8. After the level change routine RA is terminated, the process goes back to the step S1-1 and the managing process is executed. [0082] Thus, in this embodiment, when the first through third task programs Pt1 through Pt3 are executed, the manager administrative program and the level change routines RA and RB are also executed. As a result, the access level is changed. Accordingly, it is not possible to alter the access level and the manager administrative program. Furthermore, it is possible to prevent an illegal code from invading the manager administrative program. [0083] In addition, in this embodiment, it is necessary to change the access level to the access level L0 being the privileged level by a specific routine namely the level change routine. Hence, it is not possible to execute the task in other levels. Since it is guaranteed that the levels other than a level in which the task is provided are not used, it is guaranteed that the data in an area other than the access allowance area are not destroyed and do not leak out. As a result, it is possible to realize a high security level of the information processing apparatus. [0084] The present invention is not limited to these embodiments, but variations and modifications may be made without departing from the scope of the present invention. [0085] This patent application is based on Japanese priority patent application No. 2001-145176 filed on May 15, 2001, the entire contents of which are hereby incorporated by reference. Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4766537 *Jan 2, 1986Aug 23, 1988Motorola, Inc.Paged memory management unit having stack change control registerUS5305460 *Oct 5, 1988Apr 19, 1994Hitachi, Ltd.Data processorUS5390310 *Sep 30, 1991Feb 14, 1995Apple Computer, Inc.Memory management unit having cross-domain controlUS5845129 *Mar 22, 1996Dec 1, 1998Philips Electronics North America CorporationProtection domains in a single address space* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleWO2014125324A1 *Feb 12, 2013Aug 21, 2014Freescale Semiconductor, Inc.A method of and circuitry for controlling access by a master to a peripheral, a method of configuring such circuitry, and associated computer program products* Cited by examinerClassifications U.S. Classification710/107, 711/E12.097International ClassificationG06F13/00, G06F12/14, G06F21/24, G06F9/46, G06F1/00, G06F21/00Cooperative ClassificationG06F21/79, G06F21/6218, G06F12/1491, G06F9/468, G06F2221/2149, G06F21/556, G06F21/71, G06F2221/2141, G06F21/85, G06F2221/2101European ClassificationG06F9/46V, G06F21/71, G06F21/79, G06F21/62B, G06F21/55C, G06F21/85, G06F12/14D3Legal EventsDateCodeEventDescriptionMar 12, 2002ASAssignmentOwner name: FUJITSU LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOMATSU, SHIMPEI;KAWASAKI, YUSUKE;REEL/FRAME:012693/0414Effective date: 20020304Apr 3, 2007CCCertificate of correctionJan 29, 2010FPAYFee paymentYear of fee payment: 4Feb 12, 2014FPAYFee paymentYear of fee payment: 8RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services