Source: http://www.google.com/patents/US20030074036?dq=inassignee:integral+inassignee:peripherals
Timestamp: 2017-06-26 20:26:47
Document Index: 688784782

Matched Legal Cases: ['art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24', 'art 24']

Patent US20030074036 - Implantable device with digital waveform telemetry - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA technique for acquiring and accessing information from a medical implantable device is provided. Analog waveforms of interest are sensed and processed by signal acquisition circuitry. Analog parameters of interest are applied to selector switches which are controlled by a logic circuit. The logic circuit...http://www.google.com/patents/US20030074036?utm_source=gb-gplus-sharePatent US20030074036 - Implantable device with digital waveform telemetryAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20030074036 A1Publication typeApplicationApplication numberUS 10/302,587Publication dateApr 17, 2003Filing dateNov 21, 2002Priority dateFeb 6, 1998Also published asCA2320279A1, EP1053045A1, US5978713, US6507759, US6959213, WO1999039768A1Publication number10302587, 302587, US 2003/0074036 A1, US 2003/074036 A1, US 20030074036 A1, US 20030074036A1, US 2003074036 A1, US 2003074036A1, US-A1-20030074036, US-A1-2003074036, US2003/0074036A1, US2003/074036A1, US20030074036 A1, US20030074036A1, US2003074036 A1, US2003074036A1InventorsDavid Prutchi, Patrick PaulOriginal AssigneeIntermedics Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (57), Referenced by (27), Classifications (5), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetImplantable device with digital waveform telemetry
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS [0026] Turning now to the drawings, and referring first to FIG. 1, an implantable device is illustrated diagrammatically and designated generally by the reference numeral 10. The implantable device is configured for collecting data and for transmitting and receiving data based upon data requests. The implantable device exchanges the data with an external device, designated generally by the reference numeral 12. In the illustrated embodiment, implantable device 10 is a cardiac stimulator which is implanted in the body 14 of a patient in accordance with generally known techniques. The cardiac stimulator collects and transmits data regarding both its function and that of the body, and transmits data upon request to external device 12 through tissues, represented diagrammatically at reference numeral 16. The advantageous manner in which data is collected, processed and transmitted between implantable device 10 and external device 12 is summarized in greater detail below. [0027] Implantable device 10 includes data acquisition, processing and telemetry circuitry housed within a case or enclosure 18. Enclosure 18 is sealed to isolate the circuitry from surrounding tissues and body fluids following implantation. Leads 20 and 22 are interconnected with the circuitry within enclosure 18 and extend to sensing points within body 14. In the case of the cardiac stimulator illustrated in the Figures, leads 20 and 22 are coupled to desired points within the heart 24 of the patient. In particular, a terminal end 26 of lead 22 is secured within the right atrium 28 of the patient's heart, while a terminal end 30 of lead 20 is secured within the right ventricle 32 of the patient's heart. As will be appreciated by those skilled in the art, leads 20 and 22 are generally flexible assemblies including an electrically conductive core surrounded by a protected sheath. For example, the internal core may be coiled titanium wire, and the protective sheath may be a coating of polyurethane. Once secured within the respective portions of the patient's heart, tips 26 and 30 permit parameters representative of cardiac function to be sensed via signals transmitted through the leads to circuitry within enclosure 18. Moreover, circuitry is provided within device 10 for stimulating portions of the heart via leads 20 and 22 in a manner generally known in the art. [0028] It should be noted that, while throughout the present discussion reference is made to data acquisition, processing and telemetry techniques as applied to a cardiac stimulator, the techniques may find application outside the realm of cardiac devices. In particular, signals monitored, processed and telemetered by implantable device 10 could be related to the state and function of other biological systems within body 14, including organs and tissue other than the heart. [0029] Once implanted within body 14, device 10 executes predetermined monitoring and control functions as required by the particular condition of the patient. Signals monitored by device 10 may be accessed by external device 12 via an antenna 34. For monitoring, antenna 34 is placed adjacent to the patient's body in the general vicinity of enclosure 18. Antenna 34 is coupled via flexible conductors 36 to a base unit 38, commonly referred to as a programmer. Programmer 38 permits a user, typically an attending physician, to access information sensed and processed by implantable device 10 via antenna 34 and conductors 36. [0030] The functions executed by implantable device 10 are accomplished via electronic circuitry housed within enclosure 18. FIG. 2 is a diagrammatical representation of exemplary circuitry for carrying out the processes of the cardiac stimulator of FIG. 1. As shown in FIG. 2, circuitry within enclosure 18 is coupled to heart 24 via leads 20 and 22. In particular, lead 22 includes an atrial tip conductor 40 and an atrial ring conductor 42. Similarly, lead 20 includes a ventricular tip conductor 44 and a ventricular ring conductor 46. As will be appreciated by those skilled in the art, the tip and ring conductors of leads 20 and 22 supply signals for stimulating portions of heart 24, as well as convey feedback or detected parameter signals to the circuitry from points at or adjacent to the ends of leads 20 and 22. [0031] Referring now more particularly to the functional electronic circuitry illustrated in FIG. 2, signals transmitted along conductors 40, 42, 44 and 46 are interfaced with electronic circuitry as follows. Conductors 40 and 42 of lead 22 are coupled to an atrial stimulus generator 48. Similarly, conductors 44 and 46 of lead 20 are coupled to a ventricular stimulus generator 50. Atrial and ventricular stimulus generators 48 and 50 are configured to transmit electrical pulses for stimulating tissues within the heart 24, in a manner generally known in the art. Moreover, signals transmitted along conductors 40, 42, 44 and 46 are tapped and applied to a data acquisition and processing circuit 52. As described more fully below, circuit 52 is configured to analyze signals representative of the function of heart 24 (and more generally of body 14), as well as of implantable device 10. In the illustrated embodiment, data acquisition and processing circuit 52 is particularly suited for monitoring fast-changing analog waveforms by means of comparison, filtering and amplification circuitry. [0032] Signals processed by circuit 52 are available for further processing and telemetry to external device 12 as follows. Signals of interest processed by circuit 52 are applied to a switching circuit 54. Switching circuit 54 includes a plurality of solid state switching devices, the conductive state of which is controlled by a telemetry and analog-to-digital (A/D) logic circuit 56. Circuit 56 configures switching circuit 54 to open and close switches within circuit 54 to apply desired signals from data acquisition and processing circuit 52 to an A/D conversion circuit 58. Analog signals from circuit 52 applied to A/D conversion circuit 58 are converted to corresponding digital values. These corresponding digital values are stored in a memory circuit 60. As described below, the advantageous configuration of circuit 52, 54, 56, 58 and 60 permits specific analog signals of interest to be converted from monitored analog waveforms to digital values so as to update memory locations within circuit 60 in response to information requests received from external device 12. [0033] Digitized values stored within memory circuit 60 are available for transmission to external device 12 via a telemetry circuit 62. Telemetry circuit 62 receives command signals from a microprocessor 64. In addition to commanding operation of telemetry circuit 62, microprocessor 64 receives and processes various signals from other functional circuitry related to the continuous monitoring and stimulating functions of implantable device 10. In particular, in the illustrated embodiment microprocessor 64 is coupled to an activity sensor 66, a ventricular-to-atrial interval timer circuit 68, an atrial-to-ventricular interval timer circuit 70, a memory circuit 72, and a general purpose A/D circuit 74. The configuration and operation of circuits 66 through 74 are generally known in the art. For example, activity sensor 66 may include an accelerometer which detects movement of the patient in which implantable device 10 is disposed. Signals from activity sensor 66 are typically used by microprocessor 64 as a rate-responsive input, allowing microprocessor 64 to adapt its monitoring and stimulation functions in accordance with the patient's changing activity level. Timer circuits 68 and 70 receive clock pulses from microprocessor 64 and serve to count or indicate intervals between contractions of tissues within heart 24. Memory circuit 72 serves to store the control routine executed by microprocessor 64, as well as data acquired by or processed by microprocessor 64. In particular, memory circuit 72 may store diagnostic and programming data which may be preconfigured prior to implantation of device 10, or which may be conveyed to device 10 by telemetry after implantation. Finally, general purpose A/D circuit 74 permits microprocessor 64 to obtain digital values of various functional parameters in the execution of its monitoring and control routines. In general, A/D circuit 74 is employed for more slowly changing parameter values, such as lead impedance, battery condition, and so forth. [0034] It should be noted that implantable device 10 may include circuitry which is different from or complimentary to the circuitry illustrated in FIG. 2 and described above. In particular, as will be appreciated by those skilled in the art, device 10 includes a power supply (not shown) which furnishes a continuous source of electrical energy needed for operation of the functional circuitry. The power supply will typically include a power storage battery, such as a lithium iodide or lithium carbon monofloride battery. Where desired, the power supply circuitry may also include a voltage regulator for converting the voltage from the battery to a desired level as required by the functional circuitry. [0035] In operation, implantable device 10 is configured to detect analog waveforms via leads 20 and 22 on a continual basis. The analog waveforms are applied to signal acquisition and processing circuit 52, and therethrough to switching circuit 54. Certain of the signals processed by circuit 52 may be applied directly to microprocessor 64. For example, in the illustrated embodiment, single-bit digitized signals are applied to microprocessor 64 directly from circuit 52 to indicate to the microprocessor that a chamber signal (typically corresponding to a tissue contraction), has been detected. Microprocessor 64 functions to monitor these signals as well as signals from circuits 66, 68, 70, 72 and 74. As a function of these signals and of the routine stored within memory circuit 72, microprocessor 64 triggers atrial and ventricular stimulus generator circuits 48 and 50 to provide pulses to heart 24 as needed to regulate its function. [0036] As mentioned above, circuitry within implantable device 10 permits signals monitored by the device to be accessed and telemetered to external device 12 upon demand. FIG. 3 represents in greater detail certain of the circuitry comprising signal acquisition circuit 52 and switching circuit 54 which facilitates this feature of the device. In particular, in the embodiment illustrated in FIG. 3, signal acquisition and processing circuit 52 includes an atrial sense amplifier 76, a ventricular sense amplifier 78, an atrial ring-to-can intracardiac electrogram (IEGM) amplifier 80, a ventricular ring-to-can IEGM amplifier 82, and an impedance sensor 84. Sense amplifier circuits 76 and 78 process signals transmitted over the conductors of leads 20 and 22 to obtain filtered waveforms defined by the signals. IEGM amplifiers 80 and 82 are coupled to conductors of leads 20 and 22, respectively, which conduct signals from ring electrodes of the lead tips. These circuits are also coupled to enclosure 18, as indicated by the ground potential symbol in FIG. 3. Circuits 80 and 82 reference the signals they receive to the potential of enclosure 18, filter the resulting signals and amplify them for further processing. Impedance sensor 84 detects waveforms representative of heart impedance, in a manner generally known in the art. [0037] Signals produced by circuits 76, 78, 80, 82 and 84 are further processed in signal acquisition and processing circuit 52, and made available for conversion to digitized values. In particular, signals from atrial sense amplifier 76 and ventricular sense amplifier 78 are applied to a switch bank 86 which includes a plurality of solid state switching devices. The switching devices of switch bank 86 may be opened and closed to apply signals available from circuits 76 and 78 to programmable gain amplifiers 88 and 90. As described more fully below, the conductive states of the switches of switch bank 86, and the gains of amplifiers 88 and 90 are defined by microprocessor 64 (see FIG. 2). [0038] Signals produced by IEGM amplifiers 80 and 82 are further processed by an adder circuit 92. In particular, the signal output by IEGM amplifier 80 is applied to one input node of adder 92, while the signal output by IEGM amplifier 82 is applied to a pair of input node switches 94. Switches 94 may be opened and closed under the direction of microprocessor 64 (see FIG. 2) to selectively add or subtract the signals from circuits 80 and 82. [0039] The signals produced and processed by the foregoing circuitry are available for conversion to digitized values via output conductors 96, 98, 100, 102, 104 and 106. In the illustrated embodiment, first and second output conductors 96 and 98 are coupled to programmable gain amplifiers 88 and 90, respectively. A third output conductor 100 is coupled to directly to the output of IEGM amplifier 80. A fourth output conductor 102 is coupled to the output node of adder 92. A fifth output conductor 104 is coupled directly to the output of IEGM amplifier 82. Finally, a sixth output conductor 106 carries the signal produced by impedance sensor 84. [0040] Referring now to the specific circuit configurations illustrated in FIG. 3, atrial and ventricular sense amplifiers 76 and 78 include subcircuits for comparing, filtering and amplifying the signals they monitor. Each circuit thus includes an operational amplifier 108 which compares signals transmitted via respective tip and ring conductors within leads 20 and 22. The output signals produced by operational amplifiers 108 are applied to respective low pass filters 110. The signals output by low pass filters 110 are conveyed to first sets of switches within switching bank 86. The signal are further processed by respective second low pass filters 112, and third low pass filters 114. The signals output by low pass filters 114 are conveyed to additional sets of switches within switch bank 86. The signals from low pass filters 114 are also further filtered by high pass filters 116. The output signals from high pass filters 116 are applied to third sets of switches within switch bank 86. As will be appreciated by those skilled in the art, low pass filters 110, 112 and 114, and high pass filters 116 serve to limit the bandwidth of the analog signal output by operational amplifiers 108. [0041] In addition to the filtering circuitry described above, each sense amplifier 76 and 78 includes an evoked potential detector 118. The evoked potential detectors receive the raw output from operational amplifiers 108 and produce signals available via additional switches within switch bank 86. As will be appreciated by those skilled in the art, evoked potential detectors 118 are configured to detect signals within a very short time delay after a pacing pulse from stimulus generating circuits 48 and 50. Outputs of the evoked potential detectors serve to indicate whether such pacing pulses were able to capture the chambers of the heart stimulated by the pulses. Thus, the evoked potential detectors amplify the signals produced by operational amplifiers 108 very rapidly after pacing pulses, filtering the signal to verify chamber capture. Such verification may be used to regulate further stimulation pulses and thereby to avoid unnecessarily draining the implanted power source. [0042] Circuits 76 and 78 also include programmable threshold-crossing comparators 120 which produce pulses if the outputs from high pass filters 116 exceed predetermined thresholds. As will be appreciated by those skilled in the art, signals produced by comparators 120 serve to indicate whether a chamber signal has been detected. Signals from comparators 120 are applied directly to microprocessor 64. [0043] IEGM amplifiers 80 and 82 also include filtering and amplification circuitry as shown in FIG. 3. Each amplifier circuit thus includes an operational amplifier 122 which is coupled to the ring anode conductor within leads 20 and 22, and to enclosure 18. Signals output by operational amplifiers 122 are filtered through low pass filters 124 and high pass filters 126. Output signals from high pass filters 126 are amplified in programmable gain amplifiers 128. The signals are then output to third and fifth output conductors 100 and 104, and are applied to adder 92 as summarized above. [0044] In the illustrated embodiment, certain of the settings used by the circuitry of FIG. 3 are controlled directly by microprocessor 64. For example, gains employed by programmable gain amplifiers 88, 90, 120 and 128 are set by microprocessor 64. As will be appreciated by those skilled in the art, amplifiers 88, 90 and 128 serve to scale the signals applied to them so as to obtain amplitudes corresponding to the dynamic range of A/D converter circuit 58. Moreover, the conductive states of switches within switch bank 86 and of switches 94 of adder 92 are configured by microprocessor 64. As described more fully below, the states of the switches are preferably set in accordance with an acquisition configuration defined via external device 12 and conveyed to device 10 by telemetry. [0045] Signals produced and processed by the circuitry of FIG. 3 are made available for conversion to digitized values, and for telemetry to external device 12. FIG. 4 represents an exemplary configuration of circuitry for executing such functions. As shown in FIG. 4, output conductors 96, 98, 100, 102, 104 and 106 are coupled to a series of selection switches, indicated generally by the reference numeral 130. Selection switches 130 are solid state switches which may be closed to apply signals from the output conductors to an A/D input line 132. The conductive states of switches 130 are commanded by logic circuit 56 via control signal conductors 134. A/D input line 132 delivers signals applied to it by closure of switches 130 to A/D conversion circuit 58. Circuit 58 thereafter converts the analog signal applied via the input line 132 to a digital value under the command of logic circuit 56. Control signals for commanding operation of circuit 58 are applied by logic circuit 56 via a control conductor 136. In addition to commanding conversion of the analog signals to digital values, logic circuit 56 also preferably places A/D conversion circuit 58 in a sleep mode when no analog signals are to be converted, and wakes circuit 58 from the sleep mode as required for conversion of the analog signals to digital values. [0046] Digital signals produced by A/D conversion circuit 58 are stored in a series of registers within memory circuit 60. In particular, the digital values are output from A/D conversion circuit 58 via an A/D output bus 138. Bus 138 is coupled to a series of registers 140 (denoted REG 1-REG 6 in FIG. 4) which are dedicated to the signals applied to circuit 58 via analog output lines 96-106. Registers 140 store the digitized values and hold the values available for output to telemetry circuit 62 via a digital output bus 142. In the illustrated embodiment, registers 140 are 8-bit registers which are appropriately addressed by cooperation of logic circuit 56 and conversion circuit 58. [0047] As mentioned above, external device or programmer 12 is configured to permit a programmer, typically an attending physician, to access information stored in registers 140. As illustrated diagrammatically in FIG. 4, external device 12 generally includes antenna 34, a telemetry interface circuit 144, a control circuit 146, and a human interface 148. Telemetry interface circuit 144 is configured to encode or encrypt signals, particularly data request signals, from external device 12 which are transmitted to telemetry circuit 62 via antenna 34. Interface circuit 144 is also configured to receive data signals from telemetry circuit 62 via antenna 34 and to decrypt the data signals. Control circuit 146 may execute a variety of signal processing and control functions as desired by the particular application. For the present purposes, control circuit 146 serves to receive programmer inputs from human interface 148 and to prompt interface circuit 144 to send request signals for data from device 10. Control circuit 146 is further configured to translate received data from device 10 to a useable form, and to output or display the data via human interface 148. [0048] Telemetry circuit 62 and telemetry interface circuit 144 are preferably configured to exchange data via magnetic fields which extend through tissue 16 partially surrounding device 10. While various signal transmission protocols may be envisioned and employed for implementing the present data acquisition and telemetry technique, a presently preferred method is disclosed in U.S. Pat. No. 5,383,912 issued on Jan. 24, 1995 to Cox et al., and U.S. Pat. No. 5,480,415 issued on Jan. 2, 1996, also to Cox et al. Both of the foregoing patents are assigned to the assignee of the present invention and are hereby incorporated into the present disclosure by reference. [0049] Digitized parameter values stored within memory circuit 60 are telemetered to external device 12 in response to request or prompt signals received from the external device. FIG. 5 represents steps in exemplary control logic for accessing information stored in memory circuit 60, for telemetering the information in response to request signals, and for refreshing the telemetered information in real time. As mentioned above, prior to executing the telemetry and data conversion and storage steps summarized in FIG. 5, an attending physician or other operator will generally store an acquisition configuration for a particular experiment or set of data readings of interest. In particular, in the illustrated embodiment, the attending physician will transmit signals via the telemetry circuit to set switches of the switch bank 86 and switches 94 upstream of adder 92 (see FIG. 3), as well as desired gains of the programmable gain amplifiers described above. For example, switches of switch bank 86 may be opened and closed to provide broad or narrow band IEGM data or EPD data along first and second output lines 96 and 98. Based upon the instruction set provided to microprocessor 64 to establish this acquisition configuration, the conductive states of the switches in switch bank 86 and of switches 94, and the gains of the circuit amplifiers are set by microprocessor 64. [0050] With the acquisition configuration thus set, external device 12 telemeters data request signals as desired by the attending physician. The request signals are received by telemetry circuit 62, prompting telemetry circuit 62 to access the requested values stored in memory registers (see registers 1 through 6 in FIG. 4) and to telemeter signals representative of the values to the external device. As data is accessed from each register of memory circuit 60, a logical flag is set to inform telemetry and A/D logic circuit 56 (see FIG. 2) that the register has been read and its contents have been telemetered. Circuit 56 resets switches 30 so as to feed the analog signal corresponding to the accessed register to the A/D conversion circuit 58. Thus, telemetry and A/D logic circuit 56, in cooperation with switching circuit 54 and A/D conversion circuit 58, updates or refreshes the digitized values read from memory circuit 60 each time the values are accessed and telemetered. [0051] This control logic, designated generally by reference numeral 150, is summarized in FIG. 5. As indicated in FIG. 5, at step 152 a read request signal is transmitted by external device 12 and is received by telemetry circuit 62. The request signal identifies a particular digitized value which is desired to be telemetered, or a corresponding register in which the digitized value is stored (represented by the “i” in the nomenclature of FIG. 5). At step 154 the requested digitized parameter value is accessed and telemetered via telemetry circuit 62. As mentioned above, a logical flag is then set, indicating that register i has been accessed. At step 56, telemetry and A/D logic circuit 56 checks for such logical flags to determine whether a register has been accessed and read. When the circuit identifies that a particular register has been read, the logic advances to step 158. When the outcome of step 156 is negative, the logic returns to the upstream side of step 156 to continue to monitor for flags indicating that the registers have been read. [0052] At step 158 circuit 56 verifies whether A/D conversion circuit 58 is available for converting an additional analog signal to a digital value. The circuit logic continues to loop back through this inquiry until A/D conversion circuit 58 becomes available. Once the circuit is available, logic circuit 56 changes the conductive states of selection switches 130 (see FIG. 4) to apply the analog signal corresponding to the digital value read from register i to conversion circuit 58. With the switches thus set, the then-current amplitude of the corresponding analog signal is applied to conversion circuit 58. At step 162, the conversion is performed, generating a digitized value corresponding to the analog signal. At step 164 the new digitized value is addressed and stored in the corresponding register i from which the digitized value was accessed and telemetered, thereby refreshing the register with updated information. As indicated at step 166, once the register i has been refreshed, the system will enter an idle mode. In this idle mode, logic circuit 56 will again monitor logical flags for each register, awaiting an indication that a register has been accessed and its digital value telemetered. Upon detecting such a flag, circuit 56 will again execute steps 52 through 64 for the newly accessed register value. [0053] As will appreciated by those skilled in the art, the foregoing technique offers a number of significant advantages over existing data acquisition and telemetry schemes. For example, logic circuit 56 will apply analog signals to A/D conversion circuit 58 in a manner and sequence conforming to the specific needs and requests of the external device. Moreover, only the parameters of interest to the attending physician will be converted and telemetered, thereby reducing the power consumed by the device and more efficiently utilizing the signal processing capabilities and telemetry bandwidth. [0054] By way of example, an attending physician may set an acquisition configuration to obtain filtered IEGM data and impedance sense data only. In the acquisition configuration, then, switches in switch bank 86 (see FIG. 3) would be set to transmit signals from points downstream of high pass filters 116. External device 12 then sends request signals in a string for accessing the contents of registers corresponding to analog output lines 96, 98 and 106. The digital values are accessed and telemetered in response to the request signals. As the data is accessed and telemetered, the corresponding analog signals are, in turn, sequentially converted to digital values; the digital values are stored in memory circuit 60; and the telemetry and memory updating routine summarized in FIG. 5 is carried out for each requested data value. So long as request signals are received from the external device and the requested data is accessed and sent, corresponding analog signals are accessed and converted to digital values used to refresh the accessed memory registers. Once logic circuit 56 detects that no request or prompt signal has been received for a predetermined time period, it puts A/D conversion circuit 58 in a sleep mode, thereby further reducing energy consumption. [0055] Another advantage afforded by the present technique is the ability to set and change the sequence and sampling rate for particular parameters in real time by the request signals received from the external device. In particular, because meaningful information regarding particular parameters may require different sampling rates, external device 12 may be configured to request digitized values of changing analog waveforms in different sampling frequencies depending upon the particular parameter. Moreover, certain of the sensed parameters may change at speeds permitting relatively slow sampling rates, while other parameters require extremely high sampling rates to obtain meaningful information. For example, data request signals prompting telemetry of digital values corresponding to the output of impedance sensor 84 may be sent at a frequency resulting in a sampling rate on the order of 100 to 150 samples per second. Filtered IEGM data may be requested and telemetered at a higher rate, such as of on the order of 200 to 300 samples per second. Other IEGM data may be sampled on the order of 400 to 500 samples per second. Very wide band IEGM data may require much higher sampling rates, such as on the order of 1000 to 3000 samples per second. [0056] Such different sampling rates can be readily accommodated by the present technique. Request signals are assimilated into an appropriate string defining both the parameters to be converted and telemetered, as well as the resulting sampling rate. By changing the request signal string, the attending physician may, in real time, access different information or alter the effective sampling rate of the accessed information. To accommodate very high sampling rates, A/D conversion circuit 58 is preferably selected so as to permit the necessary conversion of any particular analog signal to a digitized value at least as fast as the highest anticipated sampling rate. That is, A/D conversion circuit 58 is conveniently selected to provide an A/D conversion time approximately equal to or faster than the telemetry time anticipated. [0057] As noted above, while the foregoing technique has been described in the context of a cardiac stimulator, in appropriate devices, it may be employed for providing information relating to other tissues and organs. Moreover, parameters in addition to those described above may be accessed, processed and telemetered in accordance with the foregoing technique. In particular, in a cardiac stimulator, other possible signal sources include implanted pressure sensors, such as transducers configured to generate signals indicative of intracardiac pressure. Moreover, signals may be processed from such sources as peak endocardial accelerometers, for providing an indication of global contractility of the heart as a function of a signal amplitude. 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