Source: http://www.google.com/patents/US7956344?ie=ISO-8859-1&dq=5251294
Timestamp: 2014-10-22 03:22:44
Document Index: 294530026

Matched Legal Cases: ['art.\n9', 'art.\n12', 'art 76', 'art 80', 'art 76', 'art 80', 'art 76', 'art 80', 'art 80', 'art 80', 'art 76', 'art 76']

Patent US7956344 - Memory cell with memory element contacting ring-shaped upper end of bottom ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA memory cell includes a bottom electrode, a top electrode and a memory element switchable between electrical property states by the application of energy. The bottom element includes lower and upper parts. The upper part has a generally ring-shaped upper end surrounding a non-conductive central region....http://www.google.com/patents/US7956344?utm_source=gb-gplus-sharePatent US7956344 - Memory cell with memory element contacting ring-shaped upper end of bottom electrodeAdvanced Patent SearchPublication numberUS7956344 B2Publication typeGrantApplication numberUS 11/679,343Publication dateJun 7, 2011Filing dateFeb 27, 2007Priority dateFeb 27, 2007Also published asCN101257086A, CN101257086B, US20080203375Publication number11679343, 679343, US 7956344 B2, US 7956344B2, US-B2-7956344, US7956344 B2, US7956344B2InventorsHsiang-Lan LungOriginal AssigneeMacronix International Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (103), Non-Patent Citations (54), Referenced by (3), Classifications (12), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetMemory cell with memory element contacting ring-shaped upper end of bottom electrodeUS 7956344 B2Abstract A memory cell includes a bottom electrode, a top electrode and a memory element switchable between electrical property states by the application of energy. The bottom element includes lower and upper parts. The upper part has a generally ring-shaped upper end surrounding a non-conductive central region. The lateral dimension of the lower part is longer, for example twice as long, than the lateral dimension of the ring-shaped upper end. The lower part is a non-perforated structure. The memory element is positioned between and in electrical contact with the top electrode and the ring-shaped upper end of the second part of the bottom electrode. In some examples the ring-shaped upper end has a wall thickness at the memory element of 2-10 nm. A manufacturing method is also discussed.
1. A memory cell of the type including a memory material switchable between electrical property states by the application of energy, the memory cell comprising:
a substrate with a contact for an access circuit;
an electrically conductive plug extending through an interlayer dielectric within the substrate to the contact;
a ring-shaped bottom electrode comprising a first, ring-shaped lower part having a first contact area with a first lateral dimension in contact with the plug, and a second, upper part, the second, upper part having a generally ring-shaped upper end surrounding a non-conductive central region, the ring-shaped upper end with a second contact area between an inside perimeter and an outside perimeter of the ring-shaped upper end, the outside perimeter having a second lateral dimension;
the first lateral dimension being longer than the second lateral dimension;
the lower part being a non-perforated structure;
a top electrode; and
a memory element comprising a memory material switchable between electrical property states by the application of energy, the memory element positioned between and in electrical contact with the top electrode and the second contact area on the ring-shaped upper end of the second part of the bottom electrode.
2. The memory cell according to claim 1 wherein the generally ring-shaped upper end is a continuous ring-shaped element.
3. The memory cell according to claim 1 wherein the ring-shaped upper end has a wall thickness at the memory element of 2-10 nm.
4. The memory cell according to claim 1 wherein the first lateral dimension is about twice as long as the second lateral dimension.
5. The memory cell according to claim 1 wherein the non-conductive central region comprises a first dielectric material and the second, upper part of the bottom electrode is surrounded by and is in direct contact with a second dielectric material.
6. The memory cell according to claim 5 wherein the first and second dielectric materials have different etching properties.
7. The memory cell according to claim 5 further comprising a third dielectric material surrounding the second dielectric material.
8. The memory cell according claim 7 wherein:
the second dielectric material has an outer surface;
the third dielectric material contacts the outer surface of the second dielectric material; and
the second dielectric material overlies and is aligned with the first, ring-shaped lower part.
9. The memory cell according to claim 8 wherein the second dielectric material has a dielectric material lateral dimension about equal to the first lateral dimension.
10. The memory cell according to claim 1 wherein the memory element comprises a programmable resistive memory material.
11. A memory cell of the type including a memory material switchable between electrical property states by the application of energy, the memory cell comprising:
a ring-shaped bottom electrode comprising a first, ring-shaped lower part having a first lateral dimension and a second, upper part, the second, upper part having a generally ring-shaped upper end, the upper end being completely hollow to define an opening that surrounds a non-conductive central region, the ring-shaped upper end having a second lateral dimension;
the second, upper part having an outer sidewall;
a memory element comprising a memory material switchable between electrical property states by the application of energy, the memory element positioned between and in electrical contact with the top electrode and the ring-shaped upper end of the second part of the bottom electrode;
a dielectric film layer;
a spacer positioned between and contacting the outer sidewall and the dielectric film layer;
the spacer having an outer surface;
the dielectric film layer contacting the outer surface of the spacer; and
the spacer overlying and aligned with the first, ring-shaped lower part.
12. The memory cell according to claim 11 wherein the spacer has a spacer lateral dimension about equal to the first lateral dimension.
13. A memory cell of the type including a memory material switchable between electrical property states by the application of energy, the memory cell comprising:
a ring-shaped bottom electrode comprising a first, ring-shaped lower part having a first lateral dimension, a second, upper part, and a third, middle part between the first, upper part and the second, lower part;
the second, upper part having a generally ring-shaped upper end, the upper end being completely hollow to define an opening that surrounds a non-conductive central region, the ring-shaped upper end having a second lateral dimension;
the non-conductive central region comprising a first dielectric material;
the second, upper part of the bottom electrode being surrounded by and in direct contact with a second dielectric material, the second dielectric material having an outer surface;
a third dielectric material surrounding the second dielectric material and contacting the outer surface of the second dielectric material;
the second dielectric material overlying and aligned with the first, ring-shaped lower part;
the second dielectric material having a dielectric material lateral dimension about equal to the first lateral dimension;
the third, middle part having a lateral dimension substantially equal to the second lateral dimension;
the lower and middle parts being non-perforated structures;
a memory element comprising a memory material switchable between electrical property states by the application of energy, the memory element positioned between and in electrical contact with the top electrode and the ring-shaped upper end of the second part of the bottom electrode. Description
CROSS-REFERENCE TO OTHER APPLICATIONS This is related to U.S. patent application Ser. No. 11/375,816 filed 15 Mar. 2006 entitled Manufacturing Method for Pipe-Shaped Electrode Phase Change Memory.
BRIEF SUMMARY OF THE INVENTION A first example of a memory cell, of the type including a memory material switchable between electrical property states by the application of energy, includes a bottom electrode, a top electrode and a memory element. The bottom element includes a first, lower part having a first lateral dimension and a second, upper part. The second, upper part has a generally ring-shaped upper end surrounding a non-conductive central region, the ring-shaped upper end having a second lateral dimension. The first lateral dimension is longer than the second lateral dimension. The lower part is a non-perforated structure. The memory element comprises a memory material switchable between electrical property states by the application of energy. The memory element is positioned between and in electrical contact with the top electrode and the ring-shaped upper end of the second part of the bottom electrode. In some examples the ring-shaped upper end has a wall thickness at the memory element of 2-10 nm. In some examples of the first lateral dimension is about twice as long as the second lateral dimension. In some examples the non-conductive central region comprises a first dielectric material and the second, upper part of the top electrode is surrounded by and is in direct contact with a second dielectric material, the first and second dielectric materials having different etching properties.
One example of a method for manufacturing a memory cell device, of the type including a memory material switchable between electrical property states by the application of energy, proceeds as follows. A memory cell access layer, having a top surface and an electrically conductive element at the top surface, is provided. A first electrode material layer is formed on the top surface. A first dielectric material layer is formed on the first electrode material layer. A mask is formed over the first dielectric material layer and the electrically conductive element. Portions of the first dielectric material layer and the first electrode material layer not covered by the mask are removed. The mask is removed to leave a dielectric/electrode stack on the electrically conductive element, the dielectric/electrode stack comprising a dielectric spacer element on a bottom electrode element. The dielectric/electrode stack is covered with a second electrode material layer to create a bottom electrode structure. The bottom electrode structure comprises the dielectric spacer element surrounded by the bottom electrode element and the second electrode material layer. The second electrode material layer is covered with a second dielectric material layer. Portions of the second dielectric material layer and the second electrode material layer covering the dielectric spacer element are removed thereby creating a dielectric spacer from the dielectric spacer element while leaving portions of the second dielectric material layer to surround the remaining portions of the second electrode material layer, and also creating a bottom electrode. The bottom electrode comprises a first, lower part having a first lateral dimension and a second, upper part. The second, upper part has a generally ring-shaped upper end surrounding the exposed dielectric spacer element, the ring-shaped upper end having a second lateral dimension. A memory element is formed on the ring-shaped upper end. A top electrode is formed over the memory element. In some examples the portions removing step is carried out so that the ring-shaped upper end has a wall thickness of 2-10 nm. In some examples the portions removing step comprises an etching step followed by a planarization step, and further comprises selecting different first and second dielectric materials for the first and second dielectric material layers having different etching properties so that during the etching step, the dielectric spacer element is not etched to any substantial degree.
FIG. 3 is a simplified side view of one example of a memory cell made according to the invention; and
FIGS. 5-15 illustrate stages in the manufacture of the memory device of FIG. 15.
FIG. 3 is an example of a mushroom-type memory cell 68 made according to the invention. Memory cell 68 includes a bottom electrode 70, a top electrode 72 and a memory element 74 therebetween. Bottom electrode 70 can be made of a suitable electrode material, such as TiN, TaN or WN. Top electrode 72 is typically made of TiN while memory element 74 is typically made of resistive memory materials such as GST, discussed in more detail below. Bottom electrode 70 includes a first part 76 having a first lateral dimensions 78 and a second part 80 having a ring-shaped upper end 82. Upper end 82 surrounds a central region 84 has a second lateral dimension 86 and a wall thickness 87 at memory element 74. Wall thickness 87 preferably 2-10 nm. First lateral dimensions 78 is longer than second lateral dimension 86. In one example first lateral dimensions 78 is 50 to 90 nm, typically about 65 nm, and second lateral dimension 86 is 20 to 45 nm, typically about 32 nm. First lateral dimension 78 is typically about twice as long as second lateral dimensions 86. Providing first part 76 with extra width compared to second part 80 results in better mechanical stability for bottom electrode 70 than would be achieved if first part 76 were the same width as second part 80.
A dielectric spacer 88 is contained within central region 84 and a dielectric spacer 89 surrounds second part 80. Dielectric spacer 89 has a wall thickness 91 at memory element 74. Wall thickness 91 is typically 10-30 nm. Dielectric spacers 88, 89 are typically made of different dielectric materials having different etching properties so that during the etching that creates dielectric spacer 89, discussed below with reference to FIGS. 10-12, dielectric spacer 88 is not etched to any substantial degree. The presence of dielectric spacer 89 protects second part 80 of bottom electrode 70 during etching procedures, discussed below. This is important because of the relatively thin wall thickness 87 of upper end 82. Typical materials for dielectric spacers 88, 89 include SiNx, silicon oxynitride and tantalum oxide. A dielectric material 90, such as SiOx, surrounds dielectric spacer 88 and first part 76. First part 76 rests against a plug 92.
The construction of memory cell 68 provides several advantages. Having a ring-shaped upper end 82 contacting memory element 74 reduces the contact area between bottom electrode 70 and memory element 74 thus concentrating the electrical current thereby reducing the required reset power and reset current. In addition, the ring-shaped upper end 82 provides better process uniformity after trimming when compared with a cylindrical bottom electrode. This is because the lithographic critical dimension (CD) variation and the trimming process used in creating a cylindrical bottom electrode and a ringed-shaped bottom electrode results in a relatively large variation in the radius for each bottom electrode. However, the variation in the radius of the cylindrical bottom electrode influences the area of the cylindrical bottom electrode more than it influences the ring-shaped bottom electrode. This is because the area of the cylindrical bottom electrode uses the radius squared in determining the area (pi R2) while the contact area of a bottom electrode with a ring-shaped upper end is calculated using only the radius (2 pi RT, where T is the wall thickness), not the radius squared.
Methods for making mushroom-type phase change memory cells 68 will be described with reference to FIGS. 4-15. Referring now to FIG. 4, a memory cell access layer 94 is shown formed on a substrate 96. Substrate 96 is typically SiO2. Access layer 94 typically comprises access transistors (not shown); other types of access devices, such as diodes, may also be used. Access layer 94 comprises first and second plugs 92, 98 and a source line 100 all within a dielectric film layer 102. First and second plugs 92, 98 and source line 100 are typically made of tungsten. Memory cell access layer 94 also contains polysilicon word lines 106, 108. Memory cell access layer 94 has an upper surface 104.
FIG. 5 illustrates the results of the deposition of a layer 110 of an electrode material, such as TiN, on upper surface 104, followed by the deposition of a layer 112 the same material as dielectric spacer 88. Photoresist masks 114, see FIG. 6, are then formed on the structure of FIG. 5 to be generally aligned with plugs 92, 98. Photo resist masks 114 preferably have a minimum lithographic lateral feature size, such as 30 to 65 nm, typically about 45 nm. FIG. 7 illustrates the results of a photoresist trimming step resulting in trimmed photoresist masks 116. Each trimmed photoresist mask 116 preferably has a sublithographic lateral feature size, such as 15 to 32 nm, typically about 22 nm. The portions of layers 110 and 112 not covered by trimmed photoresist masks 116 are etched away and photoresist masks 116 are removed as illustrated in FIG. 8, leaving a dielectric/electrode stack 115 including a bottom electrode element 117 and a dielectric spacer element 119. Dielectric spacer element 119 has an outer end 121. An electrode material 118, typically the same material as layer 110, is deposited on stack 115 as shown in FIG. 9 to create a bottom electrode structure 123. FIG. 10 illustrates the result of depositing a dielectric material 120 onto the structure of FIG. 9 with dielectric material 120 being the same as the dielectric material of dielectric spacer 89. The depositions of FIGS. 9 and 10 are typically accomplished using chemical vapor deposition (CVD) techniques. Dielectric material 120 is then etched followed by etching of exposed electrode material 118 covering outer end 121 of dielectric spacer element 119 creating the structure of FIG. 11. This etching is carried out to leave a dielectric material layer 125 laterally surrounding the remainder 127 of second electrode material layer 118 surrounding dielectric spacer element 119.
FIG. 12 illustrates the results of depositing a dielectric material 122, typically the same material as substrate 96, onto the structure of FIG. 11 followed by a chemical mechanical polishing (CMP) step. Doing so creates the bottom electrode 70 and dielectric spacers 88, 89 of FIG. 3 with dielectric material 122 acting as the dielectric material 90 of FIG. 3. FIG. 13 illustrates the results of depositing a memory material 124, typically GST, onto the structure of FIG. 12 and then depositing a top electrode material 126 onto memory material 124. FIG. 14 shows results of patterning memory material 124 and top electrode material 126 creating the memory element 74 and top electrode 72 of FIG. 3. The completed memory device 128 is shown in FIG. 15 after a metallization step in which a bit line 130 is electrically connected to top electrode 72 through conductive vias 132.
Dielectric materials 88, 89 may comprise an electrical insulator including one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C. In preferred devices, dielectric materials 88, 89 have a low thermal conductivity, less than about 0.014 J/cm*K*sec. In other preferred embodiments, when memory element 74 is made from a phase change material, one or both of the thermally insulating dielectric materials 88, 89 have a thermal conductivity less than that of the amorphous state of the phase change material, or less than about 0.003 J/cm*K*sec for a phase change material comprising GST. Representative thermally insulating materials include materials that are a combination of the elements silicon Si, carbon C, oxygen O, fluorine F, and hydrogen H. Examples of thermally insulating materials which are candidates for use for the thermally insulating dielectric materials 88, 89 include SiO2, SiCOH, polyimide, polyamide, and fluorocarbon polymers. Other examples of materials which are candidates for use for the thermally insulating dielectric materials 88, 89 include fluorinated SiO2, silsesquioxane, polyarylene ethers, parylene, fluoro-polymers, fluorinated amorphous carbon, diamond like carbon, porous silica, mesoporous silica, porous silsesquioxane, porous polyimide, and porous polyarylene ethers. In other embodiments, the thermally insulating structure comprises a gas-filled void for thermal insulation. A single layer or combination of layers within dielectric materials 88, 89 can provide thermal and electrical insulation.
A memory device 128 as described herein is readily manufacturable using standard lithography and thin film deposition technologies, without requiring extraordinary steps to form sub-lithographic patterns, while achieving very small dimensions for the region of the cell that actually changes resistivity during programming. In embodiments of the invention, the memory material may be a programmable resistive material, typically a phase change material, such as Ge2Sb2Te5 or other materials described below. The region in the memory element 74 that changes phase is small; and accordingly, the magnitude of the reset current required for changing the phase is very small.
Embodiments of memory device 128 include phase change based memory materials, including chalcogenide based materials and other materials, for memory element 74. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100−(a+b), where a and b represent atomic percentages that total 100% of the atoms of the constituent elements. One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. (Ovshinsky '112 patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7. (Noboru Yamada, �Potential of Ge�Sb�Te Phase-Change Optical Disks for High-Data-Rate Recording�, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.
NixOy; TixOy; AlxOy; WxOy; ZnxOy; ZrxOy; CuxOy; etc x:y 0.5:0.5 Other compositions with x: 0�1; y: 0�1 Formation method: 1. Deposition: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N2, O2, and/or He, etc. at the pressure of 1 mtorr�100 mtorr, using a target of metal oxide, such as NixOy; TixOy; AlxOy; WxOy; ZnxOy; ZrxOy; CuxOy; etc. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1�5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. If desired, they combination of DC bias and the collimator can be used simultaneously. The post deposition annealing treatment with vacuum or N2 ambient or O2/N2 mixed ambient as sometimes needed to improve the oxygen distribution of metal oxide. The annealing temperature ranges 400 C to 600 C with an anneal time of less than 2 hours. 2. Reactive deposition: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar/O2, Ar/N2/O2, pure O2, He/O2, He/N2/O2 etc. at the pressure of 1 mtorr�100 mtorr, using a target of metal oxide, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1�5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several ten to several hundred volts is also used. If desired, the combination of DC bias and the collimator can be used simultaneously. The post deposition annealing treatment with vacuum or N2 ambient or O2/N2 mixed ambient is sometimes needed to improve the oxygen distribution of metal oxide. The annealing temperature ranges 400 C to 600 C with an anneal time of less than 2 hours. 3. Oxidation: By a high temperature oxidation system, such as furnace or RTP system. The temperature ranges from 200 C to 700 C with pure O2 or N2/O2 mixed gas at a pressure of several mtorr to 1 atm. The time can range several minute to hours. Another oxidation method is plasma oxidation. An RF or a DC source plasma with pure O2 or Ar/O2 mixed gas or Ar/N2/O2 mixed gas at a pressure of 1 mtorr to 100 mtorr is used to oxidize the surface of metal, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The oxidation time ranges several seconds to several minutes. The oxidation temperature ranges room temperature to 300 C, depending on the degree of plasma oxidation. 4. Polymer Material
It is preferred that all or part of the portions of bottom and top electrodes 70, 72 contacting memory element 74 comprise an electrode material, such as TiN, or another conductor selected for compatibility with the phase change material of memory element 74. Other types of conductors can be used for the plug structures and the top and bottom electrodes structures, including for example aluminum and aluminum alloys, TiN, TaN, TiAlN or TaAlN. Other conductors that might be used comprise one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, Ru and O. TiN may be preferred because it makes good contact with GST (discussed above) as memory element 74, it is a common material used in semiconductor manufacturing, and it provides a good diffusion barrier at the higher temperatures at which GST transitions, typically in the 600-700� C. range.
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Proc., vol. 106, 1998, pp. 21-26.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8673692Jan 19, 2012Mar 18, 2014Globalfoundries Singapore Pte Ltd.Charging controlled RRAM device, and methods of making sameUS8674332Apr 12, 2012Mar 18, 2014Globalfoundries Singapore Pte LtdRRAM device with an embedded selector structure and methods of making sameUS8698118Feb 29, 2012Apr 15, 2014Globalfoundries Singapore Pte LtdCompact RRAM device and methods of making sameClassifications U.S. Classification257/4, 257/E29.003, 257/3, 257/E29.002, 257/E47.001, 257/2International ClassificationH01L29/02, H01L47/00, H01L29/04Cooperative ClassificationH01L45/04, H01L27/24European ClassificationH01L45/04Legal EventsDateCodeEventDescriptionFeb 27, 2007ASAssignmentOwner name: MACRONIX INTERNATIONAL CO., LTD., TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUNG, HSIANG LAN;REEL/FRAME:018936/0269Effective date: 20070227Owner name: MACRONIX INTERNATIONAL CO., LTD.,TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUNG, HSIANG LAN;US-ASSIGNMENT DATABASE UPDATED:20100329;REEL/FRAME:18936/269RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google