Source: http://www.google.ca/patents/US7536540
Timestamp: 2013-05-20 11:47:35
Document Index: 267929919

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 06', 'art 1', 'art 2']

Patent US7536540 - Method of hardware driver integrity check of memory card controller firmware - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Web History | Sign inAdvanced Patent SearchPatentsA memory system comprises an encryption engine implemented in the hardware of a controller. In starting up the memory system, a boot strapping mechanism is implemented wherein a first portion of firmware when executed pulls in another portion of firmware to be executed. The hardware of the encryption...http://www.google.ca/patents/US7536540?utm_source=gb-gplus-sharePatent US7536540 - Method of hardware driver integrity check of memory card controller firmwarePublication numberUS7536540 B2Publication typeGrantApplication number11/284,623Publication date19 May 2009Filing date21 Nov 2005Priority date14 Sep 2005Also published asCN101263501ACN101263501BUS20070061570US20070061897InventorsRon BarzilaiNiv CohenReuven ElhamiasMichael HoltzmanOriginal AssigneeSandisk CorporationSandisk Technologies Inc.U.S. Classification713/2713/189380/281International ClassificationG06F9/00G06F12/14H04L9/00Cooperative ClassificationG06F21/575G06F21/57European ClassificationG06F 21/57G06F 21/57BReferencesPatent Citations (104)Non-Patent Citations (69)Referenced by (1)External LinksUSPTOUSPTO AssignmentEspacenetMethod of hardware driver integrity check of memory card controller firmwareUS 7536540 B2Abstract A memory system comprises an encryption engine implemented in the hardware of a controller. In starting up the memory system, a boot strapping mechanism is implemented wherein a first portion of firmware when executed pulls in another portion of firmware to be executed. The hardware of the encryption engine is used to verify the integrity of at least the first portion of the firmware. Therefore, only the firmware that is intended to run the system will be executed.
1. A method for starting operation and operating a memory storage device comprising:
providing firmware of the memory storage device in a mass storage unit of the memory storage device;
passing said firmware through a hardware implemented encryption engine of the memory storage device;
calculating hash values for said firmware with said hardware implemented encryption engine;
providing firmware in a mass storage unit of the memory storage device, the firmware controlling operation of the memory storage device;
executing a first set of instructions in a read only memory that copy the firmware from the mass storage unit of the memory storage device to a random access memory of the memory storage device;
verifying the integrity of the firmware as it passes from the mass storage unit through a hardware implemented encryption engine in a memory controller of the memory storage device; and
5. The method of claim 1, wherein providing the firmware comprises providing a plurality of firmware overlays.
6. The method of claim 5, further comprising, storing, within each overlay of the plurality, a hash value expected to equal a calculated hash value of a quantity of the firmware that includes the overlay containing the hash.
7. The method of claim 6, wherein the calculated hash value of the quantity being read will only correspond to expected hash value when a sector containing the expected hash value is read.
8. The method of claim 6 further comprising disregarding false positive matches on a sector block or page other than the sector block or page containing the expected hash value.
9. The method of claim 1, wherein calculating hash values comprises calculating a MAC value for a block (i), but wherein the resulting MAC value covers blocks 0 to (i), such that MAC [0. . .(i)]=MAC[MAC[0. . .(i-1)], block (i)].
10. The method of claim 9, further comprising storing the calculated MAC value for block (i) in a register of a memory controller of the memory storage device, said register not in the mass storage unit.
11. The method of claim 9, wherein calculating the hash value for a block (i), wherein the resulting MAC value covers blocks 0 to (i), such that MAC [0. . . (i)]=MAC[MAC[0. . .(i-1)], block (i)]is done for a boot loader of the firmware.
12. The method of claim 9, wherein calculating the hash value for a block (i), wherein the resulting MAC value covers blocks 0 to (i), such that MAC [0. . . (i)]=MAC[MAC[0. . .(i-1)], block (i)]is done for a boot loader of the firmware, but not the entire firmware.
13. The method of claim 9, wherein calculating the hash value for a block (i), wherein the resulting MAC value covers blocks 0 to (i), such that MAC [0. . . (i)]=MAC[MAC[0. . .(i-1)], block (i)]is done for the entire firmware.
CROSS REFERENCE TO RELATED APPLICATIONS This application is related and claims priority to Provisional Application No. 60/717,347, entitled �Hardware Driver Integrity Check of Memory Card Controller Firmware� to Holtzman et al.
This application is also related to application Ser. No. 11/285,600 entitled �Hardware Driver Integrity Check of Memory Card Controller Firmware� to Holtzman et al.; application Ser. No. 11/053,273 entitled �Secure Memory Card with Life Cycle Phases� to Micky Holtzman et al.; Provisional Application No. 60/717,163 entitled �Secure Yet Flexible System Architecture For Secure Devices With Flash Mass Storage Memory� to Micky Holtzman et al.; and Provisional Application No. 60/717,164 entitled �Secure Yet Flexible System Architecture For Secure Devices With Flash Mass Storage Memory� to Micky Holtzman et al. All of the aforementioned applications are hereby incorporated by this reference in their entireties.
FIELD OF THE INVENTION The invention generally relates to memory cards with secure content and encryption of that content, and in particular relates to verifying the integrity of the firmware that runs secure memory cards.
BACKGROUND OF THE INVENTION It is crucial to be able to verify the functionality of commercially available memory cards before they leave the factory, and to ensure that the cards are secure from hackers once they leave the factory. With the advent of digital rights management and the spread of protected content such as music and movies etc . . . there is a need to ensure that the contents of the card cannot be freely copied. One way a hacker may attempt to do this is to alter or even replace the firmware that runs the memory card in order to be able to pirate the contents of the card. Thus it is essential to provide a system that ensures both the integrity and the reliability of the firmware running on the card at all times.
SUMMARY OF INVENTION Verifying the integrity of the firmware is an important aspect of running a secure and reliable memory card. The present invention verifies the integrity of firmware that runs a memory card, universal serial bus (USB) flash drive, or other memory system. The integrity of the firmware is verified before it is executed. This prevents the execution of firmware that is not the factory firmware from being executed. This is particularly important because the factory firmware comprises security mechanisms including encryption algorithms that are meant to protect content from being freely copied. The present invention when implemented in a memory card prevents the card from running non-factory firmware or altered factory firmware that may allow copying of secure content. Thus a hacker cannot �trick� the card into running the wrong firmware. The verification process can also be used to verify the integrity of any stored data.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram of system 10 according to an embodiment of the present invention.
FIG. 3 is a schematic illustration of the boot loader 200 a. FIG. 4 is a flowchart of a portion of the booting process including a hardware based integrity check of the firmware.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A Message Authentication Code (�MAC�) is a number computed from some content (or message) that is used to prove the integrity of the content. Its purpose is to detect if the content has been altered. A Message Authentication Code is a hash computed from a message and some secret data. It is difficult to forge without knowing the secret data. The MAC is computed using an algorithm based on the DES or AES ciphers, which use a secret key. The MAC is then stored or sent with the message. The recipient recomputes the MAC using the same algorithm and secret key and compares it to the one that was stored or sent. If they are the same, it is assumed that the content or message has not been tampered with.
The Advanced Encryption Standard (�AES�) is a NIST-standard cryptographic cipher that uses a block length of 128 bits and key lengths of 128, 192 or 256 bits. Officially replacing the Triple DES method in 2001, AES uses the Rijndael algorithm developed by Joan Daemen and Vincent Rijmen of Belgium. AES can be encrypted in one pass instead of three, and its key size is greater than Triple DES's 168 bits.
Although the aforementioned standards and various other algorithms and/or standards are well known to those skilled in cryptography, the following publications are informative and are hereby incorporated by reference in their entireties: RFC 3566�The AES-XCBC-MAC-96 Algorithm and Its Use With IPsec by Sheila Frankel, NIST�National Institute of Standards and Technology, 820 West Diamond Ave, Room 677, Gaithersburg, Md. 20899, available at http://www.faqs.org/rfcs/rfc3566.html; Performance Comparison of Message Authentication Code (MAC) Algorithms for the Internet Protocol Security (IPSEC) by Janaka Deepakumara, Howard M. Heys and R. Venkatesan, Electrical and Computer Engineering, Memorial University of Newfoundland, St. John's, NL, Canada, A1B3S7 available at http://www.engr.mun.ca/�howard/PAPERS/necec�2003b.pdf; and Comments to NIST concerning AES Modes of Operations: A Suggestion for Handling Arbitrary-Length Messages with the CBC MAC by John Black, University of Nevada, Reno, Phillip Rogaway, University of California at Davis, available at http://csrc.nist.gov/CryptoToolkit/modes/proposedmodes/xcbc-mac/xcbc-mac-spec.pdf.
An example memory system in which the various aspects of the present invention may be implemented is illustrated by the block diagram of FIG. 1A. As shown in FIG. 1A, the memory system 10 includes a central processing unit (CPU) or �controller� 12, a buffer management unit (BMU) 14, a host interface module (HIM) 16, flash interface module (FIM) 18, a flash memory 20 and a peripheral access module 22. Memory system 10 communicates with a host device 24 through a host interface bus 26 and port 26 a. The flash memory 20, which may be of the NAND type, provides data storage for the host device 24. The software code for CPU 12 may also be stored in flash memory 20. FIM 18 connects to the flash memory 20 through a flash interface bus 28 and in some instances a port, which is not shown, if the flash memory 20 is a removable component. HIM 16 is suitable for connection to a host system like a digital camera, personal computer, personal digital assistant (PDA) and MP-3 players, cellular telephone or other digital devices. The peripheral access module 22 selects the appropriate controller module such as FIM, HIM, and BMU for communication with the CPU 12. In one embodiment, all of the components of system 10 within the dotted line box may be enclosed in a single unit such as in a memory card and preferably enclosed in the card.
In step 410, the system checks the integrity of the BLR, again according to the process seen in detail in the flowchart of FIG. 5. This is done, as the BLR passes through crypto engine 40, in the same way other data from flash memory 20 is verified (while the system is in integrity check mode). In step 420 the system checks the result of the integrity check performed in step 410. This is done by checking the results (flags or other indicators) stored in step 270 of the integrity check of process 200 seen in FIG. 5, which indicates whether there is a problem or not. If the BLR is not OK, the system will wait for a host command as seen in step 430 to send the system into a failure analysis state known as the return merchandise authorization (RMA) state. For more detail on this and other operating states or modes, please refer to a co-pending U.S. patent application Ser. No. 11/053,273 entitled �SECURE MEMORY CARD WITH LIFE CYCLE PHASES� to Holtzman et al., which is hereby incorporated by this reference in its entirety. If, however the BLR is OK, the system will execute the BLR in step 440. When booting is finished, the system will leave the integrity check mode based upon instructions contained in the BLR itself, as seen in step 440 of FIG. 4. The BLR comprises numerous instructions or �steps.� Among them are step 440 a, where the BLR reconfigures the crypto engine 40 to normal mode, or in other words takes the crypto engine 40 out of the integrity check mode. The BLR also contains instructions, as represented by step 440 b, that cause the system to check the integrity of system firmware 200 b. FIG. 5 is a flow chart of integrity verification process 410, as discussed with regard to FIG. 4. It illustrates the general process of reading and hashing data that is stored in flash memory 20 when the system is in integrity check mode. While the reading of NAND type flash memory will be described for exemplary purposes, the present invention can be used with any type of memory or media used for mass storage purposes. Again, while the use of MAC values is illustrated and. described, other hash values may also be used. The table of FIG. 2B will generally include the corresponding start byte and number of bytes for each entry (not shown). Generally speaking, the overall process, in the preferred embodiment, is used to verify the integrity of the NAND on a page by page basis. The process will verify the integrity of any data stored in the NAND. When the data happens to be the firmware, the firmware integrity is verified. While this page by page comparison is preferred, a smaller or larger unit of comparison may be made.
The integrity verification process in a preferred embodiment utilizes a unique calculation and control loop as shown in FIG. 5. The loop involves a continuous calculation and comparison operation. Typically in verification schemes, some type of �correct� or expected value is pre-stored and compared with a calculated value. In a preferred embodiment having the process shown in FIG. 5, the �correct� or expected value is stored within the �data under test� itself. Specifically, in the preferred embodiments described, it is in the last 128 bits of the data blocks. The last 128 bits of the sector being read will, for practical purposes, only correspond to the stored MAC (or other hash value) once, when the correct sector is read. The very small probability that a (false positive) match will occur on a page other than the last can be discounted for practical purposes.
MAC[0 . . . (i)]=MAC[MAC[0 . . . (i−1)], block (i)].
After calculating in step 220, a comparison is performed in step 260. In step 260, the hardware of the controller, FWIC 31 in particular, compares the last 128 bits of block (i) with the previously stored MAC, that is, the MAC [0 . . . (i-1)]. In step 270, the result of the comparison is stored in a memory of the system. The first time the comparison of step 260 is performed, the �stored� value in the MAC register will not actually be an appropriate stored MAC value, but will be whatever value happens to be in the register, and can therefore be thought of as random. The result of the comparison will then be stored in step 270. For the first block, the comparison will not be checked. In step 230, the MAC value calculated in step 220 will be stored in a register of the controller, preferably in a register of FWIC 31. Next in step 235, a counter will be incremented so that the value of (i) is incremented by one and the next block will again be read in step 210. The loop will continue until all blocks (i) are read. When the last block is read, and thus processed by the encryption engine, if the last 128 bits match the MAC stored in step 230, the comparison will yield a match and the result stored in step 270 will reflect that the integrity has been verified by the hardware. Only when the last page of the BLR has been read will a match be used to indicate that the integrity has been verified. All previous matches (false true values) will be ignored. If the values are different this would indicate that there is a problem with the integrity of the data. Conversely, if the values are the same then the integrity of the data is assured.
The process described in FIG. 5 involves both the hardware (HW) and the firmware (FW). As was mentioned, the hardware carries out the integrity check, while the firmware simply checks the flag set at the end of the HW integrity check. The HW and SW functions or �loops� are shown in more detail in FIGS. 6 and 7 respectively.
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