Source: http://www.google.com/patents/US20090008798?dq=inventor:%22Arthur+R.+Hair%22&ei=VAy0Tsa4NYTl0QGQiqWiBA
Timestamp: 2017-05-24 22:43:26
Document Index: 209545493

Matched Legal Cases: ['art 281', 'art 291', 'art 281', 'art 291', 'arts 281', 'arts 281', 'arts 282', 'art 281', 'arts 281', 'arts 291', 'art 291', 'art 281', 'art 292', 'art 282', 'art 293', 'art 283', 'art 294', 'art 284', 'arts 292', 'arts 281', 'art 291']

Patent US20090008798 - Semiconductor device suitable for a stacked structure - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal...http://www.google.com/patents/US20090008798?utm_source=gb-gplus-sharePatent US20090008798 - Semiconductor device suitable for a stacked structureAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS20090008798 A1Publication typeApplicationApplication numberUS 12/210,645Publication dateJan 8, 2009Filing dateSep 15, 2008Priority dateJan 15, 2003Also published asUS7884459, US8216934, US20050167812, US20110092065, WO2004064159A1Publication number12210645, 210645, US 2009/0008798 A1, US 2009/008798 A1, US 20090008798 A1, US 20090008798A1, US 2009008798 A1, US 2009008798A1, US-A1-20090008798, US-A1-2009008798, US2009/0008798A1, US2009/008798A1, US20090008798 A1, US20090008798A1, US2009008798 A1, US2009008798A1InventorsEiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa WatanabeOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (13), Classifications (75), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device suitable for a stacked structure
US 20090008798 A1Abstract
a substrate that has first and second surfaces; an integrated circuit unit, an electrode pad, and a select terminal that are formed on the first surface; a lead-out unit that has one end electrically connected to the bottom surface of the electrode pad and the other end exposed to the second surface of the substrate, the electrode pad being electrically led out to the second surface of the substrate, the lead-out unit being formed in a hole that is in the form of a concavity extending from the second surface of the substrate and penetrating the substrate, the bottom surface of the electrode pad being exposed through the bottom of the hole; and a side-surface electrode pad that is formed on a side surface of the substrate and is electrically connected to the select terminal. 2. A three-dimensional semiconductor device comprising:
a plurality of semiconductor devices that are stacked on one another, the plurality of semiconductor devices including first and second semiconductor devices, the plurality of semiconductor devices each comprising: a substrate that has first and second surfaces; an integrated circuit unit and an electrode pad on the first surface; a hole extending through the substrate from the second surface and reaching a rear surface of the electrode pad on the first surface; a lead-out unit embedded inside the hole in electrical connection to the rear surface of the electrode pad, such that a surface of the lead-out unit projects slightly from said second surface; a first wiring formed on the first surface of the substrate in electrical connection with the electrode pad; and a second wiring formed on the second surface of the substrate in electrical connection with the lead out unit, said second wiring extending continuously from said lead out unit to a flat area of said second surface of said substrate, the electrode pads of the semiconductor devices being electrically connected to one another such that the first wiring of the first semiconductor device is connected to the second wiring of the second semiconductor device stacked on the first semiconductor device. 3. The three-dimensional semiconductor device as claimed in claim 2, wherein the first semiconductor device and the second semiconductor device have different sizes.
4. The semiconductor device as claimed in claim 2, wherein the lead-out unit is formed with a conductive material that fills the hole.
5. The semiconductor device as claimed in claim 2, wherein the lead-out unit is formed with a conductor material that is formed along the inner wall surface of the hole.
6. The semiconductor device as claimed in claim 2, wherein the hole in the substrate has a tapered structure, having a smaller diameter at the bottom than the diameter of the opening on the second surface.
7. The semiconductor device as claimed in claim 2, wherein the substrate is thinner than original crystals
8. A three-dimensional semiconductor device comprising:
a plurality of semiconductor devices that are stacked on one another, the semiconductor devices each comprising: a substrate that has first and second surfaces; an integrated circuit unit, an electrode pad, and a select terminal that are formed on the first surface; and a lead-out unit that has one end electrically connected to the bottom surface of the electrode pad and the other end exposed to the second surface of the substrate, the electrode pad being electrically led out to the second surface of the substrate, the lead-out unit being formed in a hole that is in the form of a concavity extending from the second surface of the substrate and penetrating the substrate, the bottom surface of the electrode pad being exposed through the bottom of the hole; and a side-surface electrode pad that is formed on a side surface of the substrate and is electrically connected to the select terminal, the electrode pads of the semiconductor devices being electrically connected to one another, the three-dimensional semiconductor device further comprising: a plurality of external select terminals to which a signal for designating a semiconductor device among the semiconductor devices is input; and a semiconductor device designating unit that includes parts that electrically connect the side-surface electrode pads, the semiconductor device designating unit electrically connecting each of the external select terminals only to the select terminal of a designated semiconductor device among the semiconductor devices, the semiconductor device designating unit being located on a side surface of the three-dimensional semiconductor device. 9. The three-dimensional semiconductor device as claimed in claim 8, wherein:
each of the stacked semiconductor devices is part of the semiconductor device designating unit, the stacked semiconductor devices having semiconductor designating parts that are different from one another; and the semiconductor device designating unit is formed by electrically connecting the semiconductor designating parts of the stacked semiconductor devices. 10. The three-dimensional semiconductor device as claimed in claim 8, wherein:
each of the stacked semiconductor devices is part of the semiconductor device designating unit, the stacked semiconductor devices having semiconductor designating parts that are different from one another; and the semiconductor device designating unit is formed by electrically connecting the semiconductor designating parts of the stacked semiconductor devices, and short-circuiting or cutting off a predetermined portion, or short-circuiting and cutting off a predetermined portion. Description
[0001] This application is a divisional of U.S. patent application Ser. No. 11/062,735, filed on Feb. 23, 2005, which is a U.S. continuation application filed under 35 USC 111(a) claiming benefit under 35 USC 120 and 365(c) of PCT International Application No. PCT/JP03/00283 filed on Jan. 15, 2003, all of which are hereby incorporated herein by reference.
[0086] An embedded electrode 18 is provided in the hole 16 via an insulating layer 17 and a base (seed) metal layer 17 a. The insulating layer 17 is formed to cover the inner surface of the hole 16. One end of the embedded electrode 18 is electrically connected to the electrode pad 15, and the other end of the embedded electrode 18 slightly protrudes from the other principal surface 19 of the semiconductor substrate 11. The embedded electrode 18 is equivalent to the “lead-out part” in claims.
[0103] One end of the embedded electrode 18 is electrically connected to the electrode pad 15, and the other end of the embedded electrode 18 slightly protrudes from the other principal surface 19 of the semiconductor substrate 11 by a height “a” (=5 μm to 15 μm).
[0153] The dry film 109 is then removed as shown in FIG. 8A.
[0154] In FIG. 8A, the electrode pad 105 is exposed to the hole 107 through the opening 111 formed in the insulating layer 108.
[0155] A base (seed) metal layer 112 for electroplating is then formed in the hole 107 and on the bottom surface 106 of the semiconductor substrate 101. This base metal layer 112 is in contact with the exposed portion of the electrode pad 105 in the through hole 111.
[0156] The base metal layer 112 includes a 2 μm thick titanium (Ti) layer (a base layer) and a 0.5 μm thick copper (Cu) layer (an upper layer). These layers can be formed by a sputtering technique.
[0157] A dry film 113 is then formed to cover the hole 107 and adhere to the bottom surface 106 of the semiconductor substrate 101, and an opening 114 is formed at the portion of the dry film 113 corresponding to the region on which the embedded electrode is to be formed. This process is shown in FIG. 8B.
[0158] With the dry film 113 serving as a mask, electroplating is performed to fill the hole 107 with metal, thereby forming an embedded electrode 115.
[0159] The metal to fill the hole 107 in the electroplating may suitably be copper (Cu) or the like, because plating is easy to perform with copper and electric resistance can be lowered with copper.
[0160] Further, a plating layer that includes a gold (Au) surface layer and a nickel (Ni) base layer is formed on the surface of the embedded electrode 115, if necessary. The thickness of the nickel layer is approximately 2 μm, and the thickness of the gold layer is approximately 0.5 μm.
[0161] The dry film 113 is then removed as shown in FIG. 8C.
[0162] The base (seed) metal layer 112 remaining around the embedded electrode 115 is removed to expose the insulating layer 108. As a result, the embedded electrode 115 protrudes from the bottom surface 106 of the semiconductor substrate 101 by a height of 5 μm to 15 μm as shown in FIG. 8D.
[0163] The semiconductor substrate 101 is then diced into electrode circuit units (integrated circuit units) by a known dicing technique. Before or after the dicing, the double-faced adhesive tape 131 is removed. Thus, the semiconductor device 10 shown in FIG. 8E that is the same as the semiconductor device 10 of the first embodiment is obtained.
[0164] In the above described embodiments of the present invention, the embedded electrode is formed in accordance with the location of the electrode pad. Therefore, so as to obtain electric connection among stacked semiconductor devices 10, it is necessary to stack the electrode pads on one another at the same locations. This requirement can be easily satisfied in the case of a combination of semiconductor devices with similar functions and operations such as semiconductor memories. However, in the case of a combination of semiconductor devices including logic circuits or a combination of semiconductor devices including semiconductor memories and logic circuits, the above requirement cannot be easily satisfied due to the difference in chip size.
[0165] The present invention also facilitates the stacking of semiconductor devices that are considered to be difficult to combine.
[0166] FIG. 9 illustrates the structure of a semiconductor device in accordance with a fourth embodiment of the present invention. FIG. 10 is an enlarged cross-sectional view of the substantial part of the semiconductor device 10A shown in FIG. 9.
[0167] In the semiconductor device 10A shown in FIG. 9, an electronic circuit unit (an integrated circuit unit) 13 that includes an active element, a passive element, and an electrode/wiring layer is formed on a principal surface 12 of a silicon semiconductor substrate 11. A wiring layer that is lead out from the electronic circuit unit 13 extends in an insulating layer 14, and is electrically connected to an electrode pad 15.
[0168] The semiconductor substrate 11 has a hole 16 formed at the location corresponding to the electrode pad 15. This hole 16 does not penetrate the electrode pad 15.
[0169] An embedded electrode 18 is provided in the hole 16 via an insulating layer 17 formed to cover the inner surface of the hole 16. One end of the embedded electrode 18 is electrically connected to the electrode pad 15 via an opening formed in the insulating layer 17 in the hole 16, and the other end of the embedded electrode 18 slightly protrudes from the other principal surface 19 of the semiconductor substrate 11.
[0170] The structure in accordance with this embodiment characteristically has a conductive layer 20 that extends from the embedded electrode 18 and is located near the protruding portion of the embedded electrode 18 on the other principal surface 19 of the semiconductor device 11. This conductive layer 20 is a laminated structure formed on the plating base (seed) layer. The laminated structure includes an aluminum (Al) surface layer, a nickel (Ni) layer, and a copper (Cu) layer.
[0171] With the conductive layer 20, the electrode area and the electrode pattern length on the bottom surface of the semiconductor device 10A are substantially increased.
[0172] FIG. 11 illustrates the structure of a semiconductor device in accordance with a fifth embodiment of the present invention.
[0173] In the semiconductor device 10B shown in FIG. 11, an electronic circuit unit (an integrated circuit unit) 13 that includes an active element, a passive element, and an electrode/wiring layer is formed on a principal surface 12 of a silicon semiconductor substrate 11. A wiring layer that is lead out from the electronic circuit unit 13 extends in an insulating layer 14, and is electrically connected to an electrode pad 15.
[0174] The semiconductor substrate 11 has a hole 16 formed at the location corresponding to the electrode pad 15. This hole 16 does not penetrate the electrode pad 15.
[0175] An embedded electrode 18 is provided in the hole 16 via an insulating layer 17 formed to cover the inner surface of the hole 16. One end of the embedded electrode 18 is electrically connected to the electrode pad 15 via an opening formed in the insulating layer 17 in the hole 16, and the other end of the embedded electrode 18 slightly protrudes from the other principal surface 19 of the semiconductor substrate 11.
[0176] The structure in accordance with this embodiment characteristically has a conductive layer 21 that extends from the electrode pad 15 and is located on the upper surface of the electrode pad 15 or the upper surface on the side of the principal surface 12 of the semiconductor substrate 11. This conductive layer 20 is formed to extend toward the inside of the semiconductor device 10B. The conductive layer 21 has an aluminum layer on the insulating layer 17.
[0177] With the conductive layer 21, the electrode area and the electrode pattern length on the surface of the semiconductor device 10B are substantially increased.
[0178] FIG. 12 illustrates the structure of a semiconductor device in accordance with a sixth embodiment of the present invention.
[0179] In the semiconductor device 10C shown in FIG. 12, an electronic circuit unit (an integrated circuit unit) 13 that includes an active element, a passive element, and an electrode/wiring layer is formed on a principal surface 12 of a silicon semiconductor substrate 11. A wiring layer that is lead out from the electronic circuit unit 13 extends in an insulating layer 14, and is electrically connected to an electrode pad 15.
[0180] The semiconductor substrate 11 has a hole 16 formed at the location corresponding to the electrode pad 15. This hole 16 does not penetrate the electrode pad 15.
[0181] An embedded electrode 18 is provided in the hole 16 via an insulating layer 17 formed to cover the inner surface of the hole 16. One end of the embedded electrode 18 is electrically connected to the electrode pad 15 via an opening formed in the insulating layer 17 in the hole 16, and the other end of the embedded electrode 18 slightly protrudes from the other principal surface 19 of the semiconductor substrate 11.
[0182] The structure in accordance with this embodiment characteristically has a conductive layer 21 that extends from the electrode pad 15 and is located on the upper surface of the electrode pad 15 or the upper surface on the side of the principal surface 12 of the semiconductor substrate 11.
[0183] Also, the structure in accordance with this embodiment characteristically has a conductive layer 20 that extends from the embedded electrode 18 and is located near the protruding portion of the embedded electrode 18 on the other principal surface 19 of the semiconductor substrate 11.
[0184] These conductive layers 20 and 21 extend toward the inside of the semiconductor device 10C.
[0185] With the conductive layers 20 and 21, the electrode area and the electrode pattern length on the upper and bottom surfaces of the semiconductor device 10C are substantially increased.
[0186] As the electrode area and the electrode pattern length are substantially increased in each of the semiconductor devices of the fourth through sixth embodiments, semiconductor devices having different chip sizes can be stacked on one another as shown in FIGS. 13 and 14.
[0187] Accordingly, semiconductor chips having different functions can be easily combined, and high performance semiconductor devices can be realized.
[0188] For example, it is easy to combine semiconductor devices having different chip sizes, different operating conditions, and different functions. More specifically, it is easy to combine flash memory devices and static memory devices, or combine a microcomputer and memory devices.
[0189] In the foregoing embodiments, the electrode pad of a first semiconductor device is in contact with the embedded electrode of a second semiconductor device. However, so as to improve the connectivity, it is also possible to employ a plating layer 151 on the surface of each electrode pad 15, as shown in FIG. 15.
[0190] In the foregoing embodiments, a plating layer is formed on the surface of the protruding portion of the embedded electrode. However, as shown in FIG. 16, the connectivity can be improved by providing soldering cover layers 161 in the form of solder balls or the like.
[0191] Meanwhile, in the structure and the manufacturing method in accordance with the first embodiment, the hole that penetrates the insulating layer on one of the principal surfaces of the semiconductor substrate is filled with metal to form the embedded electrode. In accordance with the present invention, it is also possible to provide a metal layer 171 to cover the insulating layer selectively formed in the hole as shown in FIG. 8A, the exposed portion of the electrode pad, and the bottom surface of the semiconductor substrate. Thus, an embedded electrode can be formed. Reference numeral 171 a indicates a metal layer formed on the side wall of the hole 16, and reference numeral 171 b indicates a metal layer formed on the principal surface 19 of the silicon semiconductor substrate 11. The metal layers can be formed by a sputtering technique or the like. The metal layer 171 forms the “lead-out part” claimed in claims.
[0192] As described above, the through hole 16 has a tapered structure. Accordingly, the film formed by the sputtering technique can have a uniform thickness.
[0193] Using the sputtering technique, a conductive layer can be more readily formed. Accordingly, the period of time required for manufacturing the semiconductor device can be shortened.
[0194] FIG. 17 is an enlarged view of this structure.
[0195] FIG. 20 illustrates a structure in which semiconductor devices each having a metal layer to form an embedded electrode layer, instead of the embedded electrode structure formed by filling the hole with metal, are stacked on one another.
[0196] In FIG. 20, the lower most semiconductor device 10-1 that is connected to the supporting substrate has an embedded electrode formed with a metal filling, but semiconductor devices 10-2 and 10-3 placed on the semiconductor device 10-1 each have an embedded electrode 171 formed by laminating a metal layer.
[0197] In accordance with the present invention, in the situation where an insulating layer is selectively formed in the hole as shown in FIG. 8A, a gold (Au) wire may be connected to the exposed portion of the electrode pad.
[0198] The gold wire is lead out, and the lead-out portion is melted down to form a so-called stud bump 181. The stud bump 181 forms the “lead-out part” claimed in claims.
[0199] A wire bonding technique normally used for semiconductor devices is applied to the stud bump structure, so that the stud bump structure can be easily achieved at low costs using a wire bonding device.
[0200] FIG. 18 is an enlarged view of this structure.
[0201] FIG. 21 illustrates a structure in which semiconductor devices each having an embedded electrode structure formed with a stud bump structure, instead of an embedded electrode structure formed with a metal filling, are stacked on one another.
[0202] In FIG. 21, an embedded electrode 181 formed with a stud bump structure is employed in each of the semiconductor devices 10-1 and 10-2 that are connected to the supporting substrate.
[0203] Also in accordance with the present invention, where an insulating film is selectively formed in the hole as shown in FIG. 8A, the hole may be filled with conductive paste 191, instead of the metal filling. The conductive paste 191 forms the “lead-out part” claimed in claims.
[0204] This embedded electrode structure formed by filling the hole with the conductive paste 191 can be provided at lower costs than an embedded electrode structure formed with a metal filling.
[0205] FIG. 19 is an enlarged view of this structure.
[0206] FIG. 22 illustrates a structure in which semiconductor devices each having an embedded electrode structure formed with the conductive paste filling, instead of the embedded electrode structure formed with the metal filling, are stacked on one another.
[0207] In FIG. 22, an embedded electrode 191 formed with the conductive paste filling is employed in each of the semiconductor devices 10-1, 10-2, and 10-3 that are connected to the supporting substrate.
[0208] If there are variations in chip size in any of the structures shown in FIGS. 20 through 22, the electrode area or the electrode pattern length is increased in the manner shown in FIG. 12, if necessary.
[0209] Further, in this embodiment, the supporting substrate is fixed to a principal substrate of the semiconductor device with double-face tape. However, it is also possible to form a base metal layer using a plating technique or a sputtering technique, and provide a supporting substrate on the base metal layer via an adhesive material. Here, the supporting substrate is a metal plate made of copper (Cu) or the like.
[0210] More specifically, as shown in FIG. 23A, a supporting substrate 201 made of copper (Cu) is fixed to a principal surface of the semiconductor substrate 11. As shown in FIG. 23B, the embedded electrode 18 is then formed, with the supporting substrate 201 serving as an electrode in the formation of the embedded electrode 18. As shown in FIG. 23C, the supporting substrate 201 is melted and removed.
[0211] The supporting substrate 201 made of copper (Cu) is bonded to the semiconductor substrate 11 in the following manner.
[0212] As shown in FIG. 24A, a plating layer 202 that includes a gold (Au) surface layer and a nickel (Ni) base layer is formed through electroless plating on the electrode pad 15 exposed through a principal surface of the semiconductor substrate 11.
[0213] As shown in FIG. 24B, a base layer 203 that is made of nickel (Ni) or titanium (Ti) is formed to cover the plating layer 202 on the electrode pad 15 and the insulating layer around the electrode pad 15.
[0214] As shown in FIG. 24C, an organic adhesive such as Cerasin (manufactured by Mitsubishi Gas Chemical Co., Inc.) or a polyimide-based heat resistant adhesive is applied onto the base layer 203, so that the supporting substrate 201 made of copper (Cu) with the same size as the semiconductor substrate 11 is bonded and fixed onto the base layer 203.
[0215] After the through hole is formed, the copper of the supporting substrate is removed using an acid etching liquid, and the adhesive layer is removed with an alkali etching liquid.
[0216] To facilitate the stacking of semiconductor devices (semiconductor chips), a conductive passage that penetrates the semiconductor substrate from one principal surface to the other is provided in accordance with the present invention. The conductive passage characteristically penetrates the insulating layer formed on the semiconductor substrate, but does not penetrate the corresponding electrode pad. The hole (the conductive passage) is then filled with a conductive material or a conductive layer is formed, so as to realize an embedded conductive layer that penetrates the semiconductor substrate.
[0217] The lead-out structure having such an embedded conductive layer does not penetrates the electrode pad, unlike the equivalent structure of the prior art. Accordingly, a stacked structure can be realized with high reliability, without a decrease in electrical or mechanical connectivity to the electrode pad.
[0218] Next, a memory three-dimensional semiconductor device in accordance with a seventh embodiment of the present invention is described.
[0219] FIGS. 25 through 30B illustrate the memory three-dimensional semiconductor device 50M in accordance with the seventh embodiment.
[0220] The memory three-dimensional semiconductor device 50M has four memory semiconductor devices 10M-1 through 10M-4 electrically connected to one another and stacked on one another, as shown in FIGS. 25, 26, 27B, 28B, 29B, and 30B. A memory integrated circuit is formed in each of the memory semiconductor devices 10M-1 through 10M-4. A memory semiconductor device designating unit 290 that designates a memory semiconductor device to perform data read and write operations among the memory semiconductor devices 10M-1 through 10M-4 is provided on a side surface.
[0221] The memory semiconductor device designating unit 290 includes select electrode pads 209 (see FIGS. 27A and 27B) and select terminals 210-1 through 210-4 that are provided in each of the memory semiconductor devices 10M-1 through 10M-4; comb-like wires 211-1 through 211-4 and electrode pad structures 221 through 224, 231 through 234, 241 through 244, and 251 through 254 that are provided in association with the select terminals 210-1 through 210-4 of the respective memory semiconductor devices 10M-1 through 10M-4; and external select bump terminals 260-1 through 260-4 provided on the lower surface of an interposer 51M.
[0222] Where wires 271 through 274 are formed as described later, the memory semiconductor device designating unit 290 is formed with the wires 271 through 274 and the wires 211-1 through 211-4 having the “X”-denoted portions cut off.
[0223] The electrode pad structure 221 has a first electrode part 281 and a second electrode part 291 connected to each other on a side surface of the corresponding semiconductor chip, as shown in FIGS. 26, 27A, and 27B. The first electrode part 281 is formed on the surface of the memory semiconductor chip, and the second electrode part 291 extends from the side surface to the bottom surface of the memory semiconductor chip.
[0224] The electrode pad structures 231, 241, and 251 each have the same structure as the electrode pad structure 221.
[0225] As shown in FIGS. 28A and 28B, the electrode pad structures 222, 232, 242, and 252 each have the same structure as the electrode pad structure 221.
[0226] As shown in FIGS. 29A and 29B, the electrode pad structures 223, 233, 243, and 253 each have the same structure as the electrode pad structure 221. As shown in FIGS. 30A and 30B, the electrode pad structures 224, 234, 244, and 254 each have the same structure as the electrode pad structure 221.
[0227] As shown in FIG. 26, the electrode pad structures 221 through 224, 231 through 234, 241 through 244, and 251 through 254 are located at the respective ends of the wires 211-1 through 211-4, and are also located at the corresponding areas on the side surfaces of the semiconductor chips of the memory semiconductor devices 10M-1 through 10M-4. These electrode pad structures each extend from the side surface to the upper surface and the lower surface of the corresponding semiconductor chip.
[0228] The wires 211-1 through 211-4 each have the “X”-denoted portions cut off with a laser, as shown in FIGS. 26, 27A, 27B, 28A, 28B, 29A, 29B, 30A, and 30B.
[0229] The electrode pad structures 221 through 224 of the lowermost memory semiconductor device 10M-1 are electrically connected to the external select bump terminals 260-1 through 260-4 on the interposer 51M, respectively.
[0230] The electrode pad structures 221 through 224, 231 through 234, 241 through 244, and 251 through 254 are electrically connected to one another through the corresponding side-surface electrode units and bottom-surface electrode units. More specifically, the electrode pad structures 221, 231, 241, and 251 are electrically connected to one another. The electrode pad structures 222, 232, 242, and 252 are electrically connected to one another. The electrode pad structures 223, 233, 243, and 253 are electrically connected to one another. The electrode pad structures 224, 234, 244, and 254 are electrically connected to one another.
[0231] When the memory three-dimensional semiconductor device 50M is seen from a side, the electrode pad structures 221 through 224, 231 through 234, 241 through 244, and 251 through 254 form four wires 271 through 274 that extend horizontally on the side surface of the memory three-dimensional semiconductor device 50M, as shown in FIG. 25.
[0232] Since the wires 211-1 through 211-4 have the “X”-denoted portions cut off, a select signal supplied to the external select bump terminal 260-1 is sent only to the select terminal 210-1, a select signal supplied to the external select bump terminal 260-2 is sent only to the select terminal 210-2, a select signal supplied to the external select bump terminal 260-3 is sent only to the select terminal 210-3, and a select signal supplied to the external select bump terminal 260-4 is sent only to the select terminal 210-4. With the select signal, a memory semiconductor device to perform data read and write operations is designated among the four memory semiconductor devices 10M-1 through 10M-4.
[0233] As the above described memory semiconductor device designating unit 290 is formed to utilize a side surface of the memory three-dimensional semiconductor device 50M, a smaller memory semiconductor device can be obtained, compared with a case where a memory semiconductor device designating unit is formed by placing terminals and wires on an interposer or the like on which memory integrated circuits are mounted. Thus, the above described memory three-dimensional semiconductor device 50M is smaller in size on a plane and more compact than a conventional memory three-dimensional semiconductor device.
[0234] As shown in FIGS. 31 through 43, the above described memory semiconductor device designating unit 290, together with each memory integrated circuit, is formed on the semiconductor substrate. Therefore, the process for forming the memory semiconductor device designating unit 290 is not necessary after the chip-type memory semiconductor devices are stacked on one another, and the memory three-dimensional semiconductor device 50M can be completed by simply stacking the chip-type memory semiconductor devices on one another. Thus, the memory three-dimensional semiconductor device 50M can be manufactured with high productivity.
[0235] Next, the method of producing the memory semiconductor device 10M-1, especially the electrode pad structure 221 and the wire 211-1, is described.
[0236] First, as shown in FIGS. 31 and 32, rewiring is performed on a silicon wafer 310 that has memory integrated circuits and a select electrode pad 209 formed therein, so as to form the select terminal 210-1 on the select electrode pad 209, the wire 211-1 that extends from the select terminal 210-1 and has a pattern width of 50 μm or smaller, and the first electrode parts 281 through 284 at the ends of the wire 211-1. A half of each of the first electrode parts 281 through 284 is located on a scribe line 300 that divides the silicon semiconductor substrate into semiconductor chips.
[0237] As shown in FIG. 33, the wire 211-1 is cut off at the portions denoted by “X”, using a laser with a spot diameter of 100 μm. By doing so, the electric connection between the select terminal 210-1 and each of the first electrode parts 282 through 284 is cut off, and only the first electrode part 281 remains electrically connected to the select terminal 210-1.
[0238] As shown in FIG. 34, with the memory integrated circuit side of the semiconductor substrate 310 facing down, the semiconductor substrate 310 is bonded onto the plate-like supporting member (supporting substrate) 132 with the double-faced tape 131. The bottom surface of the semiconductor substrate 310 is then ground, so as to thin the semiconductor substrate 310.
[0239] Next, a predetermined resist pattern 301 is formed on the bottom surface of the thinned semiconductor substrate 310A. Etching is then performed to form the hole 107 and a scribe groove 302 in the scribe line 300, as shown in FIGS. 35 and 36. The end half of each of the first electrode parts 281 through 284 is exposed through the bottom surface of the scribe groove 302.
[0240] After the resist pattern 301 is removed, the insulating film 108 is formed on the bottom surface of the semiconductor substrate 310A, as shown in FIG. 37.
[0241] As shown in FIGS. 38 and 39, the dry film 109 is bonded onto the bottom surface of the semiconductor substrate 310A, and a slit 110A and a pin hole 110 are formed in the dry film 109. With the dry film 109 serving as a mask, dry etching is performed to selectively remove an insulating film 45. A slit 303 is formed in the bottom of the scribe groove 302, and the opening 111 is also formed in the bottom of the hole 107.
[0242] Next, the seed metal layer 112 is formed on the insulating film 108, as shown in FIG. 40.
[0243] As shown in FIGS. 41 and 42, after a plating resist layer 304 is selectively formed, the semiconductor substrate 310A is immersed in a Cu plating bath, and electroplating is performed. Although there are steps on the bottom surface of the semiconductor substrate 310A, a resist with high solubility is employed, and exposure is carried out by a stepper exposure device with a small numerical aperture (NA). Thus, the plating resist 304 can be suitably formed. Through electroplating, the second electrode parts 291 through 294 are formed in the scribe groove 302, and the embedded electrode 115 is formed in the hole 107.
[0244] As shown in FIG. 42, the second electrode part 291 is electrically connected to the first electrode part 281, and is formed on the side surface of the semiconductor substrate 310A and extends along the bottom surface of the semiconductor substrate 310A.
[0245] Meanwhile, the second electrode part 292 is electrically connected to the first electrode part 282, the second electrode part 293 is electrically connected to the first electrode part 283, and the second electrode part 294 is electrically connected to the first electrode part 284. These electrode parts 292, 293, and 294 are formed on the side surface of the semiconductor substrate 310A and extend along the bottom surface of the semiconductor substrate 310A.
[0246] Next, as shown in FIG. 43, the plating resist 304 is removed, and the exposed portions of the seed metal layer 112 are removed.
[0247] After that, the adhesiveness of the double-faced tape 131 is reduced, and the plate-like supporting member 132 is removed. As a result, the memory semiconductor device 10M-1 shown in FIGS. 25 and 26 is obtained.
[0248] The other memory semiconductor devices 10M-2, 10M-3, and 10M-4 are produced through the same procedures as the above, except that the wires 211-2 through 211-4 are cut off at different locations.
[0249] As described above, the stacking order of the memory semiconductor devices 10M-1 through 10M-4 is determined in advance during the wafer processing.
[0250] The memory three-dimensional semiconductor device 50M is manufactured by picking up the memory semiconductor device 10M-1 from a first semiconductor substrate, the memory semiconductor device 10M-2 from a second semiconductor substrate, the memory semiconductor device 10M-3 from a third semiconductor substrate, and the memory semiconductor device 10M-4 from a fourth semiconductor substrate, and stacking up the memory semiconductor devices 10M-1 through 10M-4 in the predetermined order.
[0251] Next, a memory three-dimensional semiconductor device 50M-A in accordance with an eighth embodiment of the present invention is described.
[0252] In the memory three-dimensional semiconductor device 50M-A shown in FIG. 44, memory semiconductor devices 10M-A-1 through 10M-A-4 are electrically connected to one another and are stacked on one another. The memory three-dimensional semiconductor device 50M-A has a memory semiconductor device designating unit 290A formed on a side surface. The memory semiconductor device designating unit 290A is to designate a memory semiconductor device to perform data read and write operations among the memory semiconductor devices 10M-A-1 through 10M-A-4.
[0253] Although not shown in the drawings, the other electrodes of each of the memory semiconductor devices 10M-A-1 through 10M-A-4 are embedded electrodes 115. The embedded electrodes 115 of the memory semiconductor devices 10M-A-1 through 10M-A-4 are connected to one another when the memory semiconductor devices 10M-A-1 through 10M-A-4 are stacked as described in the foregoing embodiment.
[0254] The memory semiconductor devices 10M-A-1 through 10M-A-4 are semiconductor chips that have the same structures and are picked up from a single semiconductor substrate. After the four memory semiconductor devices 10M-A-1 through 10M-A-4 are stacked up, the memory semiconductor device designating unit 290A is formed through an external select bump terminal/select terminal connecting process, so that the external select bump terminals 260-1 through 260-4 are electrically connected only to the select terminals 210-1 through 210-4, respectively, as shown in FIG. 48.
[0255] Part of a memory semiconductor device 10M-A that forms the memory three-dimensional semiconductor device 50M-A is shown in FIGS. 45 and 46. The memory semiconductor device 10M-A differs from the memory semiconductor device 10M-1 shown in FIG. 25 in the following points 1), 2), and 3).
[0256] 1) The wire 211-1 is not cut off;
[0257] 2) The first electrode parts 281 through 284 of the electrode pad structures 221 through 224 are covered with an insulating film 400;
[0258] 3) Auxiliary electrode pad structures 411 through 414 are provided next to the electrode pad structures 221 through 224. The auxiliary electrode pad structures 411 through 414 have the same structures as the electrode pad structures 221 through 224.
[0259] Four memory semiconductor devices 10M-A are stacked on the interposer 51M, so as to form a stacked structure 420 shown in FIG. 47.
[0260] Four pairs of wires 431 through 434 are formed on a side surface of the stacked structure 420. The pairs of wires 431 through 434 are formed with first side-surface wires 441 through 444 and second side-surface wires 451 through 454.
[0261] As shown in FIG. 47, the first side-surface wire 441 is formed with the four vertically-aligned electrode pad structures 221 of the memory semiconductor devices 10M-A-1 through 10M-A-4 that constitute the stacked structure 420. In the first side-surface wire 441, the insulating film 400 shown in FIG. 46 insulates each two vertically-neighboring electrode pad structures 221 from each other. The other first side-surface wires 442, 443, and 444 are also formed with the vertically-aligned electrode pad structures 222 through 224 of the memory semiconductor devices 10M-A-1 through 10M-A-4, respectively. In each of the first side-surface wires 442, 443, and 444, an insulating film 400 insulates each two vertically-neighboring electrode pad structures from each other among the electrode pad structures 222, 223, and 224.
[0262] The second side-surface wire 451 is formed with the vertically-aligned auxiliary electrode pad structures 411 of the respective memory semiconductor devices 10M-A. Among the auxiliary electrode pad structures 411, each two vertically-neighboring auxiliary electrode pad structures 411 are electrically connected. The other second side-surface wires 452, 453, and 454 are also formed with the vertically-aligned auxiliary electrode pad structures 412 through 414, and each two vertically-neighboring auxiliary electrode pad structures among the auxiliary electrode pad structures 412 through 414 are electrically connected.
[0263] The electrode pad structures 411 through 414 of the lowermost memory semiconductor device 10M-A-1 are electrically connected to the external select bump terminals 260-1 through 260-4.
[0264] In this structure, the external select bump terminal/select terminal connecting process is carried out by applying silver paste to predetermined parts of the wires 431 through 434 with a silver paste dispenser 450, and performing thermal hardening to electrically connect the wires 431 through 434, as shown in FIG. 48.
[0265] As shown in FIG. 44, in the memory three-dimensional semiconductor device 50M-A, the first side-surface wire 441 and the second side-surface wire 451 are short-circuited to each other with a silver paste 470-1 on the side surface of the memory semiconductor device 10M-A-1. Likewise, the first side-surface wire 442 and the second side-surface wire 452 are short-circuited to each other with a silver paste 470-2 on the side surface of the memory semiconductor device 10M-A-2. Also, the first side-surface wire 443 and the second side-surface wire 453 are short-circuited to each other with a silver paste 470-3 on the side surface of the memory semiconductor device 10M-A-3. The first side-surface wire 444 and the second side-surface wire 454 are short-circuited to each other with a silver paste 470-4 on the side surface of the memory semiconductor device 10M-A-4.
[0266] In this structure, the external select bump terminal 260-1 is electrically connected only to the select terminal 210-1 among the select terminals 210-1 through 210-4 via the second side-surface wire 451 (the electrode pad structure 411), the silver paste 470-1, the first side-surface wire 441 (the electrode pad structure 221), and the wire 211-1. Likewise, the external select bump terminal 260-2 is electrically connected only to the select terminal 210-2 via the second side-surface wire 452, the silver paste 470-2, the first side-surface wire 442, and the wire 211-2. The external select bump terminal 260-3 is electrically connected only to the select terminal 210-3 via the second side-surface wire 453, the silver paste 470-3, the first side-surface wire 443, and the wire 211-3. The external select bump terminal 260-4 is electrically connected only to the select terminal 210-4 via the second side-surface wire 454, the silver paste 470-4, the first side-surface wire 444, and the wire 211-4.
[0267] The memory three-dimensional semiconductor device 50M-A is formed to utilize the side surface of the stacked structure 420, as shown in FIG. 44. Accordingly, the memory three-dimensional semiconductor device 50M-A is small in size on a plan view, and is more compact than a conventional three-dimensional semiconductor device.
[0268] Also, the stacked structure 420 is formed by stacking up chips that are randomly picked up from different silicon wafers, regardless of any stacking order. Thus, the memory three-dimensional semiconductor device 50M-A can be easily produced.
[0269] The memory semiconductor device designating unit 290A is formed by carrying out the external select bump terminal/select terminal connecting process after the formation of the stacked structure 420. Accordingly, there is a certain degree of freedom in the correspondence between the external select bump terminals 260-1 through 260-4 and the select terminals 210-1 through 210-4. Thus, the memory three-dimensional semiconductor device 50M-A is suitable for manufacturing a small number of memory three-dimensional semiconductor devices with different structures.
[0270] Further, the laser cutting process is not necessary in the external select bump terminal/select terminal connecting process in this embodiment. Because of this, the memory three-dimensional semiconductor device 50M-A can be more easily produced.
[0271] A memory three-dimensional semiconductor device 50M-B in accordance with a ninth embodiment of the present invention is shown in FIG. 49.
[0272] The memory three-dimensional semiconductor device 50M-B has memory semiconductor devices 10M-B-1 through 10M-B-4 electrically connected to one another and stacked on one another. The memory three-dimensional semiconductor device 50M-B also has a memory semiconductor device designating unit 290B on its side surface. The memory semiconductor device designating unit 290B is to designate a memory semiconductor device to perform data read and write operations among the memory semiconductor devices 10M-B-1 through 10M-B-4.
[0273] The memory semiconductor devices 10M-B-1 through 10M-B-4 have the same structures as the memory semiconductor devices 10M-A-1 through 10M-A-4, except that the insulating film 400 shown in FIGS. 45 and 46 is not employed.
[0274] First side-surface wires 441B through 444B are electrically connected to one another over the entire length, like the second side-surface wires 451 through 454.
[0275] The external select bump terminal/select terminal connecting process includes the step of performing thermosetting with a silver paste dispenser that applies silver paste on predetermined locations, and the step of cutting the first side-surface wires 441B through 444B at predetermined locations with a laser.
[0276] In the memory semiconductor device designating unit 290B, the first side-surface wires 441B through 444B are short-circuited to the second side-surface wires 451 through 454 with the silver pastes 470-1 through 470-4. Furthermore, the first side-surface wires 441B through 444B of the respective memory semiconductor devices 10M-B-1 through 10M-B-4 are cut off with a laser at the locations denoted by “X” and reference numeral 480. With the memory semiconductor device designating unit 290B, the external select bump terminals 260-1 through 260-4 are electrically connected to the select terminals of the respective memory semiconductor devices 10M-B-1 through 10M-B-4.
[0277] The stacked memory semiconductor devices 10M-B-1 through 10M-B-4 may not include the second electrode part 291 of the electrode pad structure 221 that extends onto the bottom surface of the semiconductor substrate. In that case, the laser cutting denoted by reference numeral 480 in FIG. 49 is not necessary.
[0278] Like the memory three-dimensional semiconductor device 50M-A, the memory three-dimensional semiconductor device 50M-B is small in size on a plan view and is more compact than a conventional three-dimensional semiconductor device. Accordingly, it is easy to produce the memory three-dimensional semiconductor device 50M-B. Thus, the memory three-dimensional semiconductor device 50M-B is suitable for manufacturing a small number of memory three-dimensional semiconductor devices with different structures.
[0279] It should be noted that the present invention is not limited to the embodiments specifically disclosed above, but other variations and modifications may be made without departing from the scope of the present invention.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4751562 *Sep 30, 1987Jun 14, 1988Fujitsu LimitedField-effect semiconductor deviceUS5028986 *Dec 23, 1988Jul 2, 1991Hitachi, Ltd.Semiconductor device and semiconductor module with a plurality of stacked semiconductor devicesUS6372620 *Feb 19, 1999Apr 16, 2002Sony CorporationFabrication method of wiring substrate for mounting semiconductor element and semiconductor deviceUS7196418 *Jan 26, 2005Mar 27, 2007Fujitsu LimitedSemiconductor device and stacked semiconductor device that can increase flexibility in designing a stacked semiconductor deviceUS20010008794 *Jan 5, 2001Jul 19, 2001Masatoshi AkagawaSemiconductor device and manufacturing method therefor* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS7919353 *Aug 22, 2007Apr 5, 2011Sanyo Electric Co., Ltd.Semiconductor device and manufacturing method thereofUS7977781 *Oct 30, 2010Jul 12, 2011Hitachi, Ltd.Semiconductor deviceUS8174109 *Apr 2, 2010May 8, 2012Shinko Electric Industries Co., Ltd.Electronic device and method of manufacturing sameUS8361838 *Sep 23, 2011Jan 29, 2013Hynix Semiconductor Inc.Semiconductor package and method for manufacturing the same via holes in semiconductor chip for plurality stack chipsUS8405197 *Mar 25, 2009Mar 26, 2013Stats Chippac Ltd.Integrated circuit packaging system with stacked configuration and method of manufacture thereofUS20100038742 *Aug 22, 2007Feb 18, 2010Sanyo Electric Co., Ltd.Semiconductor device and manufacturing method thereofUS20100244217 *Mar 25, 2009Sep 30, 2010Jong-Woo HaIntegrated circuit packaging system with stacked configuration and method of manufacture thereofUS20100252937 *Apr 2, 2010Oct 7, 2010Shinko Electric Industries Co., Ltd.Electronic device and method of manufacturing sameUS20110024864 *Aug 10, 2010Feb 3, 2011Panasonic CorporationSemiconductor device and method for manufacturing the sameUS20110042825 *Oct 30, 2010Feb 24, 2011Hitachi, Ltd.Semiconductor deviceUS20120009736 *Sep 23, 2011Jan 12, 2012Hynix Semiconductor Inc.Semiconductor package and method for manufacturing the sameUS20140335655 *Jul 25, 2014Nov 13, 2014Rui HuangIntegrated circuit package system with mounting structureUS20160013147 *Jul 8, 2014Jan 14, 2016Taiwan Semiconductor Manufacturing Company, Ltd.Methods for forming fan-out package structure* Cited by examinerClassifications U.S. Classification257/777, 257/E23.02, 257/E21.597, 257/E23.141, 257/E23.011, 257/E25.013International ClassificationH01L23/522, H01L23/31, H01L23/48, H01L23/485, H01L21/768, H01L29/76, H01L25/065, H01L23/52Cooperative ClassificationH01L2924/181, H01L2224/45144, H01L2224/13009, H01L2924/12042, H01L2924/0002, H01L2924/014, H01L2224/16145, H01L25/0657, H01L2924/01006, H01L2924/05042, H01L23/3128, H01L2924/01004, H01L2924/01019, H01L2225/06513, H01L2924/14, H01L2924/01027, H01L2225/06524, H01L2924/01011, H01L2924/15311, H01L2224/0401, H01L2225/06551, H01L2924/01022, H01L2924/01005, H01L2924/01014, H01L2924/01033, H01L2924/01013, H01L2924/0106, H01L2225/06527, H01L2924/01039, H01L2924/01015, H01L21/76898, H01L2924/01028, H01L2924/01082, H01L2924/01029, H01L2924/01075, H01L2924/01079, H01L2924/01074, H01L25/50, H01L2225/06517, H01L2225/06555, H01L2924/01078, H01L2924/01047, H01L2225/06541, H01L23/481, H01L2224/13008, H01L2224/02371, H01L24/05, H01L2224/131, H01L24/13, H01L24/16, H01L2224/16227, H01L2224/13025, H01L2224/16225, H01L2224/05572, H01L2224/06181European ClassificationH01L24/02, H01L25/50, H01L23/31H2B, H01L25/065S, H01L23/48J, H01L21/768TLegal EventsDateCodeEventDescriptionDec 9, 2008ASAssignmentOwner name: FUJITSU MICROELECTRONICS LIMITED, JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089Effective date: 20081104Owner name: FUJITSU MICROELECTRONICS LIMITED,JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089Effective date: 20081104Jul 9, 2010ASAssignmentOwner name: FUJITSU SEMICONDUCTOR LIMITED, JAPANFree format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024651/0744Effective date: 20100401Jul 9, 2014FPAYFee paymentYear of fee payment: 4Apr 27, 2015ASAssignmentOwner name: SOCIONEXT INC., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU SEMICONDUCTOR LIMITED;REEL/FRAME:035508/0337Effective date: 20150302RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services