Source: http://www.google.com/patents/US6549527?ie=ISO-8859-1&dq=7,013,345/
Timestamp: 2015-08-03 20:40:09
Document Index: 348431261

Matched Legal Cases: ['arts 147', 'art 147', 'arts 145', 'art 155', 'art 155', 'arts 145', 'art 100', 'art 100', 'art 100', 'arts 147', 'arts 98', 'art 153', 'art 147']

Patent US6549527 - Radio receiver and despreader - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA radio receiver for improving transmission performance by applying prescribed processing to received signals having reached to plural antennas concurrently, and a despreader to be mounted in the radio receiver. In such a radio receiver, the received signals are decimation-sampled, and multiplexed into...http://www.google.com/patents/US6549527?utm_source=gb-gplus-sharePatent US6549527 - Radio receiver and despreaderAdvanced Patent SearchPublication numberUS6549527 B1Publication typeGrantApplication numberUS 09/352,262Publication dateApr 15, 2003Filing dateJul 13, 1999Priority dateJan 7, 1999Fee statusLapsedPublication number09352262, 352262, US 6549527 B1, US 6549527B1, US-B1-6549527, US6549527 B1, US6549527B1InventorsMasafumi Tsutsui, Yoshinori Tanaka, Shuji KobayakawaOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (11), Classifications (14), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetRadio receiver and despreader
US 6549527 B1Abstract
A radio receiver for improving transmission performance by applying prescribed processing to received signals having reached to plural antennas concurrently, and a despreader to be mounted in the radio receiver. In such a radio receiver, the received signals are decimation-sampled, and multiplexed into a multiple-signal, which is demultiplexed and prediction processed for interpolating the values decimated in the sampling. In the despreader, the transfer functions and despreading codes are multiplied in real time, and interpolation processing and despreading processing are performed based on the filtering characteristics set as the results of the multiplication. In a radio transmission system to which the present invention is applied, it becomes possible to perform all of desired synthetic processing, phase scanning, frequency scanning and feeding point scanning adaptive to an array antenna system, without lowering the performance of the system or increasing the scale and the price of the hardware.
In connection to this, since the receiving parts 147-2 to 147-4 are the same as the receiving part 147-1 in configuration, the corresponding components are hereinafter designated by like numerals with the first index numbers of “2” to “4”, and explanations and drawings thereof are omitted here.
The matched filter 152 is composed of: a shift register 156, where it is operated in synchronization with the above-mentioned despreading code and with a clock, which is is 8fc in frequency with respect to the chip rate fc of the despreading code, and has stages of (8L−1) in number with respect to the word length L of the despreading code; a multiplier 157, where it individually connected to each of the inputs and outputs of all the stages of the shift register 156, and weights (either “1” or “−1”) representing the logical values of the corresponding bits are previously individually set among the bits composing a despreading code; and an adder 158, where it is arranged at the subsequent stage of the multiplier 157 as the final stage.It is assumed that the number of stages of the shift register 156 is “31,” for simplicity in th following.
In the conventional example of such configuration, the front end parts 145-1 to 145-4 respectively convert the received signals having reached concurrently to the antenna 141-1 to 141-4 into equivalent signals in the baseband domain (hereinafter, referred to as “spreading signals”).
The respective A/D converters 146-1 to 146-4 simultaneously over-sample the spread signals at a period of (⅛fc) (hereinafter, referred to as “over-sampling period”) with respect to the chip rate fc to generate discrete signals, and send the discrete signals to the lines 143-1 to 143-4.
The path sensing part 155 reads out the delay profile stored in the RAM 154 as described above, in the order of time series at the periods of the despreading code. By this means, the path sensing part 155 outputs a “path detection signal,” which is composed of pulse sequences showing the time point in which the averaged value exceeding a predetermined threshold value is detected, re-cyclically at the period of the despreading code.
Now, in the above-mentioned conventional example, the number of the lines designated by the numeral “143” increases in proportion to the number of the antennas designated by the numeral “141”. The number of lines can be lowered, for example by multiplexing the discrete signals generated by the A/D converters 146-1 to 146-4.
In view of the foregoing, an object of the present invention is to provide a radio receiver and a despreader in which the flexible modularization is achieved without greatly increasing the complexity of the configuration of the hardware.
First, the principle of radio receivers according to the present invention will be described with reference to FIG. 1.
In connection to this, since the interpolation filters 86-2 to 86-4 are the same as the interpolation filter 86-1 in configuration, the corresponding components are hereinafter designated by like numerals with an index number of “2” to “4”, respectively, and the descriptions and diagrams thereof will be omitted here.
In the A/D conversion package 80, the A/D converters 83-1 to 83-4 accept spreading signals obtained by the front end parts 145-1 to 145-4, respectively,and individually generate discrete signals by over-sampling the spreading signals re-cyclically at a period (=�fc; hereinafter, referred to as “decimation sampling period”) four times the aforementioned over-sampling period (=⅛fc) without overlapping on the time axis, as shown in FIG. 5.
C−16, C−15, . . . , C−1, C1, C1, C2, . . . , C16,
wherein a time function Cn=f(n/8fc) is defined as the fourier transformation (FIG. 6(b)) of a frequency function (FIG. 6(a)) which shows an ideal rectangular pass band and is equivalent to the quadruple of the chip rate fc (hereinafter, referred to as “decimation sampling frequency”) in bandwidth in the baseband domain.
In connection to this, since the interpolation filters 91-2 to 91-4 are the same as the interpolation filter 91-1 in configuration, the corresponding components are hereinafter designated by like numerals with an index number of “2” to “4”, respectively, and the descriptions and diagrams thereof will be omitted here.
In connection to this, since the interpolation filters 97-2 to 97-4 are the same as the interpolation filter 97-1 in configuration, the corresponding components are designated by like numerals with an index number of “2” to “4”, respectively in the following, and the descriptions and diagrams thereof will be omitted here.
Besides, the mapping ROM 102 equipped in the searcher 92 has distinction information showing the unique coefficient sequences respectively corresponding to the values “0” to “3” given as the synchronizing signal, among the above-mentioned coefficient sequences (1) to (4), as shown in FIG. 8(b) stored in advance. (For ease of description, it is assume that the distinction information is one of “(1)” to “(4)”.)
The path sensing part 100 outputs re-cyclically a “path detection signal,” which is composed of pulse train showing time points in which the averaged value exceeding a predetermined threshold value is detected, at the period of the despreading codes, among the aforementioned sequences showing the power, by reading out the delay profile thus stored in the RAM 99 in the order of time series and in synchronization with the despreading code.
Besides, the latches 101-1 to 101-4 are, concurrently, supplied with the synchronizing signals showing which discrete signals among those generated by the A/D converters 83-1 to 83-4 the discrete signal being restored by the demultiplexer 85 is, and hold the value of the synchronizing signal (one of “0” to “3”) at the time point in which the above-mentioned path detection signal is outputted by the path sensing part 100.
When the value of the synchronizing signal is held in any one latch among the latches 101-1 to 101-4 (hereinafter, referred to as “active latch,” for ease of description) as described above, the mapping ROM 102 obtains the distinction information corresponding to the value from among the previously stored distinction information (1) to (4). Then, the mapping ROM 102 supplies the distinction information to the interpolation filter (hereinafter, referred to as “active interpolation filter”; also, assume that “the interpolation filter 91-1” is the active interpolation filter, for ease of description) corresponding to the above-mentioned active latch among the interpolation filters 91-1 to 91-4.
As a result, according to the present embodiment, in the interpolation filters 91-1 to 91-4, the four discrete signals generated in over-sampling by the A/D conversion package 80 are interpolated in phase space for instantaneous values at the time points in which the “path detection signal” is supplied by the path sensing part 100 among the instantaneous values which actually are not contained in the discrete signals, by switching the coefficients to the respective multipliers 94-1 to 94-4, and are supplied to the four inputs of the receiving parts 147-1 to 147-4 concurrently. In comparison of the present embodiment with the embodiment shown in FIG. 4, the searcher 92 is equipped with the latches 101-4 to 101-4 and mapping ROM 102, which are not equipped in the searcher 148, and the interpolation filters 91-1 to 91-4 are equipped with the ROMS 96-1 to 96-4, which are not equipped in the interpolation filters 86-1 to 86-4.
However, the total sum of the stage numbers of the shift registers 93-1 to 93-4 equipped in the interpolation filter 91-1 to 91-4 and the hardware dimension of the multipliers 94-1 to 94-4 and adders 95-1 to 95-4 are equivalent to nearly “�” (=((⅛fc)/(�fc))) the total sum of the stage numbers of the shift registers 87-1 to 87-4 equipped in the interpolation filters 86-1 to 86-4 and the hardware dimension of the multipliers 88-1 to 88-4 and adders 89-1 to 89-4, respectively.
The smoothing parts 98-1 to 98-4 are larger in hardware dimension compared to the smoothing part 153; however, the spread of the major operations in the interpolation filters 91-1 to 91-4 and searcher 92 become “�” (=((⅛fc)/(�fc))) the speed of the like operations in the interpolation filters 86-1 to 86-4 and searcher 148.
The selector 111 generates a select signal (which takes a value of one of “0” to “3” re-cyclically) synchronizing with the synchronizing signal by counting following the time point in which the after-mentioned control signal is supplied to the above-mentioned control input and the proximate time point in which the synchronizing signal is updated, and supplies the select signal to the RAM 113.
For clear distinction from the components of the other interpolation/despreading filters 122-12 to 122-14, the components of the interpolation/despreading filter 122-11 are, in principle, designated by numerals in which the index numbers of the numerals for the components of the interpolation filters 91-1 to 91-4 shown in FIG. 7 and receiving part 147-1 shown in FIG. 14 are used as the second index numbers, and the first index numbers of “1”, are added in the following.
In connection to this, since the interpolation filters 122-12 to 122-14 are the same as the interpolation filter 122-11 in configuration, the corresponding components are designated by like numerals with the first index number of “2” to “4”, respectively, and the descriptions and diagrams thereof will be omitted here in the following.
As described above, according to the present embodiment, both the interpolation processing and the despread processing are performed at the same time in different configurations from that of the embodiment shown in FIG. 7. Therefore, like the embodiment shown in FIG. 7, even in the cases where the number of the antennas designated by the numerals of “141” is large, the restriction on the mounting of the hardware is eased and the suppression of interference based on the sector zone configuration and the diversity receiving system becomes possible.
In connection to this, since the interpolation despreading filters 132-12 to 132-14 are the same as the interpolation despreading filter 132-11 in configuration, the corresponding components are hereinafter designated by like numerals with the first index numbers of “2” to “4”, respectively, and the descriptions and diagrams thereof will be omitted here.
Besides, since the interpolation filters 132-2 to 132-4 are the same as the interpolation filter 132-1 in configuration, the corresponding components are hereinafter designated by like numerals with the first index numbers of “2” to “4”, respectively, and the descriptions and diagrams thereof will be omitted here.
Meanwhile, in accordance with the four coefficient sequences shown in FIG. 8(a) and the logical values of the above-mentioned despreading codes, the products of the binary (it is assumed here that it is “−1” and “1”, for ease of description) respectively corresponding to the logical values and the coefficient sequences are stored in the ROMs 131-11 to 133-14 through 131-41 to 131-44 in advance.
Furthermore, in the respective embodiments described above, the channels are individually allocated based on the process of channel control, and the plurality of receiving parts designated by the numerals of one of “147”, “121”, and “131” are equipped. However, the number of receiving parts may be, for example, “1”, in the case where the call to have channels established via the radio transmission channels at a time is one in number.
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