Source: https://patents.google.com/patent/US9060126B2/en
Timestamp: 2020-01-22 07:54:32
Document Index: 288667043

Matched Legal Cases: ['art 20', 'art 20', 'art 26', 'art 26', 'art 26', 'art 26', 'art 21', 'art 26', 'art 284', 'art 284', 'art 284', 'art 284', 'art 282', 'art 21', 'art 284', 'art 284', 'art 284', 'art 284', 'arts 284', 'art 284', 'art 284', 'art 284', 'art 26', 'art 284', 'art 284', 'art 284', 'art.\n3', 'art.\n7', 'art.\n9', 'art.\n13', 'art.\n14', 'art.\n15']

US9060126B2 - Solid-state image sensing apparatus - Google Patents
US9060126B2
US9060126B2 US10/934,886 US93488604A US9060126B2 US 9060126 B2 US9060126 B2 US 9060126B2 US 93488604 A US93488604 A US 93488604A US 9060126 B2 US9060126 B2 US 9060126B2
US10/934,886
US20050062864A1 (en
2003-09-04 Priority to JPJP2003-312498 priority Critical
2003-09-04 Priority to JP2003-312498 priority
2003-09-04 Priority to JP2003312498A priority patent/JP4457613B2/en
2004-09-03 Application filed by Sony Corp filed Critical Sony Corp
2004-12-03 Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MABUCHI, KEIJI
2005-03-24 Publication of US20050062864A1 publication Critical patent/US20050062864A1/en
2015-06-16 Publication of US9060126B2 publication Critical patent/US9060126B2/en
102100018206 CLK3 Human genes 0 description 67
101700079103 CLK3 family Proteins 0 description 67
102100018253 CLK2 Human genes 0 description 38
101700053639 CLK2 family Proteins 0 description 38
102100018203 CLK4 Human genes 0 description 8
101700059342 CLK4 family Proteins 0 description 8
101700029992 H2B1A family Proteins 0 description 2
102100016336 HIST1H2BA Human genes 0 description 2
The present application claims priority to Japanese Patent Application JP2003-312498, filed in the Japanese Patent Office Sep. 4, 2003; the entire contents of which is incorporated herein by reference.
Although not shown in the figure, the communication/timing generation part 20 includes a function block of a timing generator TG (an example of a read-address controller) which supplies clock signals and predetermined timing pulse signals necessary for the operation of each part, and a function block of a communication interface which receives an input clock signal and command data for operation modes, etc., and outputs data including information of the solid-state image sensing apparatus 1. For example, a horizontal address signal is supplied to a horizontal decoder 12 a, a vertical address signal is supplied to a vertical decoder 14 a, and each of the decoders 12 a and 14 a receives the signal to select the corresponding row or column.
Also, in the communication/timing generation part 20 of the present embodiment, a clock CLK1 having the same frequency as an input clock signal (master clock) CLK0 input though a terminal 5 a, a clock signal having a frequency half the frequency of the input clock signal, a low-speed clock signal having a further divided frequency are supplied to each part in the device, for example, the horizontal scanning circuit 12, the vertical scanning circuit 14, the column processing part 26, or a front stage side, that is to say, the side other than the signal processing system near the output terminal 5 c of the output circuit 28. In the following, a clock signal having a frequency divided by two, and a clock signals having a frequency further divided are all put together to be called a low-speed clock CLK2.
The vertical scanning circuit 14 selects a row of the pixel area, and supplies a necessary pulse signal to the row. For example, the vertical scanning circuit 14 has the vertical decoder 14 a for specifying (selecting a row of the pixel area 10) a reading row in a vertical direction, and a vertical drive circuit 14 b for supplying a pulse signal to a control line for the unit pixel 3 on the reading address (row direction) specified by the vertical decoder 14 a for driving. In this regard, the vertical decoder 14 a selects a row for an electronic shutter in addition to a row for reading out a signal.
The horizontal scanning circuit 12 selects a column AD circuit of the column processing part 26 in synchronism with the low-speed clock in sequence, and leads the signal to the horizontal signal line 18. For example, the horizontal scanning circuit 12 has the horizontal decoder 12 a for specifying (selecting an individual column circuit in the column processing part 26) a reading column in a horizontal direction, and a horizontal drive circuit 12 b for leading each signal of the column processing part 26 to a horizontal signal line 18 in accordance with the reading address specified by the horizontal decoder 12 a. In this regard, the horizontal signal lines 18 are disposed, for example, for the number of bits n (n is a positive integer) to be handled by the column AD circuit, for example, given 10 (=n) bits, 10 lines are disposed corresponding to the number of bits.
Also, the output circuit 28 is preferable to have a high-speed clock signal output function which outputs the high-speed clock signal CLK3 generated by the clock-conversion part 21 from a terminal other than the data terminal in addition to a function of outputting the video data D1 from the output terminal 5 c. For example, the bit data of the image pickup data D0 or the video data D1 is output from the terminal 5 c in sequence as serial-format data in synchronism with a rising edge, and the high-speed clock signal CLK3 used at this time is output from the terminal 5 d. At this time, the high-speed clock signal CLK3 is output in consideration of a delay with the video data D1. The consideration for a delay means that the data switching position of each bit of the video data D1 in a serial format is maintained to have a constant relationship with each edge of the high-speed clock signal CLK3 (for example, to have the same position). This is the same in the following.
For example, in the solid-state image sensing device of the VGA (about 300 thousand pixels), assuming that the frequency of the input clock is 24 MHz, and the circuits other than the output circuit 28 are operated at 12 MHz or 24 MHz (low-speed clock), using the high-speed clock signal CLK3 of 120 MHz from the single output terminal 5 c of the output circuit 28, the 10-bit video data D1 is serially output at a frame rate of 30 fps (frame/s).
Accordingly, it is necessary for the pixel area 10 and the column processing part 26 to decrease the frequency as much as possible to reduce white noises, and to operate at a low frequency as much as possible to eliminate irregularity of the pulse delay, etc. depending on the places. Furthermore, as desired output image information, images of hundreds of thousands to millions of pixels×10 bits must be output at tens to thousands of pieces per second. In addition, in order to mount the parts on a small apparatus such as a mobile phone, a PDA (personal digital assistant), there is a demand that the parts are produced as small as, as inexpensive as, and as reliable as possible. Thus the number of output terminals needs to be reduced, and the connection load to the next stage LSI needs to be small.
Also, in addition to outputting the high-speed clock signal CLK3, as shown in FIG. 3B, boundary data P2 indicating a delimiter of one pixel data may be output from the terminal 5 e other than each of the terminals 5 c and 5 d of the video data D1 and the high-speed clock signal CLK3 as data having a lower frequency than the high-speed clock signal CLK3. For example, in this embodiment, a clock having the same frequency as the low-speed clock CLK2, which indicates the start or the end of the 10-bit video data D1 may be output as the boundary data P2.
Accordingly, as shown in FIG. 5, the output buffer 286 of the output circuit 28 has a function of differential conversion part which converts the received data into differential-format data including normal video data D1P having the same polarity as the video data D1 and inverted video data D1N having the opposite polarity based on the n-bit (in this example, 10) video data D1, represented in a serial format, generated by the switching part 284 having a function of a parallel-serial conversion part. The output buffer 286 having a function of the differential conversion part has an output terminal 5 cP for externally outputting a normal video data D1P and an output terminal 5 cN for externally outputting the inverted video data D1N. The output buffer externally outputs differential outputs of the normal video data D1P and the inverted video data D1N from the corresponding two output terminals 5 cP and 5 cN, respectively.
In the same manner, an output buffer 288 other than the output buffer 286 has a function of differential conversion part which converts the received data into differential-format data including a normal high-speed clock signal CLK3P having the same polarity as the high-speed clock signal CLK3 received through the switching part 284 and an inverted high-speed clock signal CLK3N having the opposite polarity. The output buffer 288 has an output terminal 5 dP for externally outputting a normal high-speed clock signal CLK3P and an output terminal 5 dN for externally outputting the inverted high-speed clock signal CLK3N. Then the output buffer 288 externally outputs the high-speed clock signal CLK3 input through the switching part 284 in consideration of a delay with the video data D1, and the inverted high-speed clock signal CLK3N in consideration of a delay with the inverted video data D1N from the corresponding two output terminals 5 dP and 5 dN, respectively as differential outputs of the high-speed clock signal CLK3 and the inverted high-speed clock signal CLK3N.
In this manner, each of the differential outputs is output from the terminals (in this example, 5 dP and 5 dN) different from the data output terminals (in this example, 5 cP and 5 cN) in consideration of a delay with the video data D1P and D1N. It is, therefore, possible to fetch the video data D1P and D1N for any of the differential outputs in synchronism with the corresponding high-speed clock signal CLK3P and CLK3N at the data receiving side of the outside of the device, and thus an error can be prevented.
The switching part 284 includes a multiplexer (multiple-inputs and one-output switch; details are omitted), and parallel-format data from the signal processing part 282 is individually input into each of a plurality of input terminals 284 a of the multiplexer. Any one of each data input into the plurality of input terminals 284 a is selected to be output from the output terminal 248 b. The high-speed clock signal CLK3 from the clock-conversion part 21 is input into a control terminal 284 c of the multiplexer as a switching command. By using a multiplexer having such a structure, it is possible to achieve parallel-serial conversion with a simple circuit structure.
The switching part 284 having such a structure selects each one bit from 10-bit data input from an individual terminal using the high-speed clock signal CLK3 as a switching command in accordance with a predetermined sequence to output from the output terminal 248 b. Thus switching part 284 converts the parallel data into serial-format data (in the following, referred to parallel-serial conversion). Then switching part 284 leads the video data D1 after the parallel-serial conversion to the data output buffer 286. Also, the switching part 284 leads the high-speed clock signal CLK3 used at the parallel-serial conversion to the clock output buffer 288.
The output buffers 286 and 288 have a function of the differential conversion part in the same manner as the variation of the first example. For example, the output buffer 286 externally outputs the differential output of the normal video data D1P and the inverted video data D1N from the corresponding two output terminals 5 cP and 5 cN, respectively. In the same manner, the output buffer 288 outputs the high-speed clock signal CLK3 in consideration of a delay with the video data D1, and the inverted high-speed clock signal CLK3N in consideration of a delay with the inverted video data D1N as the differential output of the high-speed clock signal CLK3 and the inverted high-speed clock signal CLK3N from the corresponding two output terminals 5 dP and 5 dN, respectively.
For example, in the same manner as the first example, in the solid-state image sensing device of the VGA (about 300 thousand pixels), assuming that the frequency of the input clock is 24 MHz, and the circuits other than the output circuit 28 are operated at 12 MHz or 24 MHz (low-speed clock), using the high-speed clock signal CLK3 of 120 MHz from the two differential output terminals 5 cP and 5 cN of the output circuit 28, the 10-bit video data D1 is serially output at a frame rate of 30 fps (frame/s).
Also, for the structure of the second example, it is possible to use a structure (LVDS: low voltage differential signaling) in which differential interface in current mode is employed. In this way, it becomes advantageous against the problems of noise-withstandingness and unnecessary radiation. For example, when an interface of single output in current mode is employed as the variation of the second example shown in FIG. 7 and in the first example structure, as shown in FIG. 8A, a current goes and comes back (the timing is not simultaneous) between the output circuit 28 at the transmission side and the next-stage circuit and the next-stage IC at the receiving side. Thus, at each time, an electromagnetic field causing unnecessary radiation occurs, affecting peripheral circuits and the outside of the solid-state image sensing apparatus 1.
The output buffers 286-0 to 286-9 outputs the differential output of the video data D1 and the inverted video data D1N from the corresponding two output terminals 5 cP and 5 cN based on each bit of input pixel data D1. In the same manner, the output buffer 288, other than the output buffer 286, outputs the high-speed clock signal CLK4 and the inverted high-speed clock signal CLK4N in consideration of a delay, based on the input high-speed clock signal CLK4, from the corresponding two output terminals 5 dP and 5 dN.
FIG. 12 and FIG. 13 are circuit block diagrams illustrating a combination example structure of the example structures of the second and third output circuits. In both structures, two stages of the switching parts 284 a and 284 b are provided for the portion of converting into serial-format data. However, each role is different in FIG. 12 and in FIG. 13. In this regard, the structure of differential output is employed both in FIG. 12 and FIG. 13 in the same manner as the second and third examples. However, single output may be employed in the same manner as the variations of the second and third examples. In the following, a specific description will be given.
The example of FIG. 12 has a characteristic in that, in the same manner as the third example, first, m-column data is converted into serial-format data for each bit using the high-speed clock signal CLK4 in the switching part 284 a, thereafter the second example structure is applied using the high-speed clock signal CLK5 in the switching part 284 b, and this n-bit parallel data is further converted to serial-format data. The high-speed clock signal CLK5 used for converting the n-bit parallel data into the serial-format data in the switching part 284 b has a frequency n times the frequency of the high-speed clock signal CLK4, that is to say, m×n times the frequency of the low-speed clock CLK2, and is 4×10=40 in this example.
In contrast, the example of FIG. 13 has a characteristic in that, in the same manner as the third example, first, the second example is applied, the parallel data of n bits for each m columns in the column processing part 26 is converted into serial-format data using the high-speed clock signal CLK3 in the switching part 284 a, then the third example is applied using the high-speed clock signal CLK6 in the switching part 284 b, and m-column data is further converted into serial-format data. The high-speed clock signal CLK6 used for converting the m-column data into the serial-format data in the switching part 284 b has a frequency m times the frequency of the high-speed clock signal CLK3, that is to say, n×m times the frequency of the low-speed clock CLK2, and is 4×10=40 times in this example.
When a digital-signal processing circuit operated by the high-speed clock signal CLK3 is provided in the image sensing device, the power consumption of the device increases. On the other hand, if such a digital-signal processing circuit is not provided in the image-sensing device, a similar circuit is disposed at the outside of the circuit. In this case, the power consumption of the entire camera makes little difference whether the digital-signal processing circuit is provided in the device or not. It is sometimes rather more efficient to perform the processing in the device in which the connection with the pixel signals is strong. The second example satisfies such a request.
This strobe data strobe data STB is assumed to be used in place of the high-speed clock signal CLK3. That is to say, the strobe data STB is output from the terminal 5 d. Here, the strobe data STB is assumed to be a signal inverted at the timing when the video data D1 is not inverted.
Each of normal data DIP and STBP output from the normal terminal Q of the D flip-flops 308 and 318, respectively is externally output from the normal terminals 5 cP and 5 dP through the output buffers 286 and 290, respectively. Also, each of normal data DIN and STBN output from the inverted terminal QN of the D flip-flops 308 and 318, respectively is externally-output from the inverted terminals 5 cN and 5 dN through the output buffers 286 and 290, respectively.
The boundary data P2 output by the output buffer 292 is assigned for each one unit (in this example, 16 bits) of the video data D1. As shown in FIG. 19, the duty thereof may be set to 50%, and may be virtually the data having the opposite polarity to the low-speed clock CLK2. Alternatively, the duty thereof may be changed to a value other than 50% as shown in FIG. 3C.
As an example of using the high-speed clock signal only at the output circuit, an example of serializing data is described. However, the use of the high-speed clock signal is not limited to data serialization. For example, the high-speed clock signal can be used for movement extraction which requires multiple high-speed calculations and compression processing.
a pixel area which has a plurality of pixels;
an AD-conversion part which converts pixel signals output from the pixel area into pixel data, which is digital data;
a high-speed clock generation part which generates a high-speed clock signal having a higher frequency than a basic clock signal that is a basic pulse signal corresponding to a driving pulse signal for driving the pixel area;
a communication part for communicating with an external controller, wherein the high-speed clock generation part switches the high-speed clock frequency based on a frequency switching instruction, corresponding to an operating mode of the imaging sensing device, received by the communication part;
a data-output part which externally outputs a predetermined output data based on the digital data in accordance with the high-speed dock signal generated by the high-speed clock generation part,
wherein the data-output part comprises:
a data receiving part which receives, in synchronism with the basic clock signal, the digital data; and
a data processing part performs a predetermined processing on parallel-format digital data received by the data receiving part using the high-speed clock signal, and
a high-speed clock output part which converts high-speed clock signal into differential format clock signal including a normal high-speed clock signal having the same polarity as the high-speed clock signal generated by the high-speed clock generation part and an inverted high-speed clock signal having the opposite polarity, the high-speed clock output part has two clock-output terminals for externally outputting the normal high-speed clock signal and the inverted high-speed clock signal individually;
wherein the data-output part outputs image data and the high-speed clock signal to an external stage; and
wherein the pixel area, AD-conversion part, high-speed clock generation part, the data-output part, and communication part are disposed on a common semiconductor substrate.
wherein the data-output part outputs the output data in accordance with both a rising edge and a falling edge of the high-speed clock signal generated by the high-speed clock generation part.
3. The solid-state image sensing device according to claim 1,
wherein the high-speed clock generation part generates the high-speed clock signal having a frequency of k times (k is a positive integer of 2 or more) or more the frequency of the basic clock signal.
4. The solid-state image sensing device according to claim 1,
wherein the high-speed clock generation part generates the high-speed clock signal having a frequency of k times (k is a positive integer of 2 or more) or more the frequency of the basic clock signal and in synchronism with the basic clock signal.
5. The solid-state image sensing device according to claim 1,
wherein the high-speed clock generation part and the data-output part are disposed on the semiconductor substrate of the solid-state image sensing device being adjacent to each other at an edge of both of the parts.
6. The solid-state image sensing device according to claim 1, wherein the data processing part comprises a parallel serial conversion part which converts the parallel-format pixel data received by the data receiving part into serial format data using the high-speed clock signal generated by the high-speed clock generation part.
7. The solid-state image sensing device according to claim 6, wherein the parallel-serial conversion part has a switching part which includes an output terminal for outputting by selecting any one of a plurality of input terminals receiving individual input of the parallel-format data and each data input into the terminal, and a control terminal for receiving input of the high-speed clock signal generated by the high-speed clock generation part as a switching command,
wherein any one of each data input into the input terminal is selected and output from the output terminal to be converted into the serial format data in accordance with a predetermined procedure using the high-speed clock signal generated by the high-speed clock generation part as the switching command.
8. The solid-state image sensing device according to claim 6, wherein the data-output part has one data-output terminal for externally outputting n-bit output data, expressed in the serial format, generated by the parallel-serial conversion part.
9. The solid-state image sensing device according to claim 6, wherein the data-output part has a differential conversion part which converts the pixel data into differential-format data including normal data having the same polarity as n-bit output data, expressed in the serial format, generated by the parallel-serial conversion part and inverted data having the opposite polarity, and the differential conversion part has two data-output terminals for externally outputting the normal data and the inverted data individually.
10. The solid-state image sensing device according to claim 1, wherein the data processing part comprises a parallel-serial conversion part which converts the parallel-format pixel data of the plurality of pixels received by the data receiving part using the high-speed clock signal generated by the high-speed clock generation part for each bit of the parallel-format data in order to convert the plurality of pixel data into serial format data.
11. The solid-state image sensing device according to claim 10, wherein the data-output part has n data-output terminals for externally outputting the serial-format data generated by the parallel-serial conversion part for the plurality of pixels as n-bit data, expressed in the parallel format for each pixel.
12. The solid-state image sensing device according to claim 1, wherein the high-speed clock generation part generates a plurality of the high-speed clock signals having individually different frequencies, and the data processing part comprises a first parallel-serial conversion part which performs conversion of the parallel-format pixel data on a plurality of pixels received by the data receiving part into serial-format data for the plurality of pixels for each bit of the parallel-format data using the high-speed clock signal having a lower frequency among the plurality of high-speed clock signals generated by the high-speed clock generation part, and a second parallel-serial conversion part which performs conversion of the serial-format data for each bit output from the first parallel-serial conversion part into serial-format data for the bits using the high-speed clock signal having a higher frequency among the plurality of high-speed clock signals generated by the high-speed clock generation part.
13. The solid-state image sensing device according to claim 1,
wherein the high-speed clock generation part generates a plurality of the high-speed clock signals having individually different frequencies, and
the data processing part comprises: a first parallel-serial conversion part which performs conversion of the parallel-format pixel data on a plurality of pixels received by the data receiving part into serial-format data for the bits for each pixel using the high-speed clock signal having a lower frequency among the plurality of high-speed clock signals generated by the high-speed clock generation part; and a second parallel-serial conversion part which performs conversion of the serial-format data for each of the pixels output from the first parallel-serial conversion part into serial-format data for the plurality of pixels using the high-speed clock signal having a higher frequency among the plurality of high-speed clock signals generated by the high speed clock generation part.
14. The solid-state image sensing device according to claim 1, wherein the data-output part generates a high-speed clock signal having a sufficiently high frequency so as to output the pixel data together with additional data, which is other information on the pixel data, and the data-output part processes and outputs the parallel-format pixel data received by the data receiving part and the additional data based on a predetermined rule using the high-speed clock signal generated by the high speed clock generation part.
15. The solid-state image sensing device according to claim 1, wherein the data-output part has a differential conversion part for n bits, which converts the pixel data into differential-format data including normal data having the same polarity as n-bit data received, expressed in the parallel format, and inverted data having the opposite polarity, and each of the differential conversion parts for the n bits has two data-output terminals for externally outputting the normal data and the inverted data individually.
16. The solid-state image sensing device according to claim 1, further comprising:
an optical system for leading incident light into the pixel area; and
a digital signal processor for performing the output data processing.
a pixel area which has a plurality of pixels; and
an AD-conversion part which converts an analog signal sent from each of the pixels in the pixel area into a digital signal,
wherein a high-speed clock generation part generates a high-speed clock signal having a higher frequency than a basic clock signal that is a basic pulse signal corresponding to a driving pulse signal for driving the pixel area;
a data-output part externally outputs a predetermined output data based on the digital signal in accordance with the high-speed clock signal generated by the high-speed clock generation part;
a data receiving part which receives the digital signal in synchronism with the basic clock signal; and
a data processing part performs a predetermined digital signal processing on parallel-format pixel data using the high-speed clock signal; and
18. The solid-state image sensing device of claim 17, further comprising:
a communication timing generation controller that generates addressing control signals for selectively reading pixel signals from the pixels and also generates high-speed clock generation part control signals for controlling the clock speed of the high-speed clock generation part for outputting image information corresponding to the pixel signals.
a pixel area comprised of a plurality of pixels;
an AD-conversion part which converts an analog signal sent from each of the pixels in the pixel area into a digital signal; and
an optical system for leading incident light onto the pixel area,
wherein a high-speed clock generation part generates a high-speed clock signal having a higher frequency than a basic dock signal that is a basic pulse signal corresponding to a driving pulse signal for driving the pixel area;
US10/934,886 2003-09-04 2004-09-03 Solid-state image sensing apparatus Active 2027-09-14 US9060126B2 (en)
JPJP2003-312498 2003-09-04
JP2003-312498 2003-09-04
JP2003312498A JP4457613B2 (en) 2003-09-04 2003-09-04 Solid-state imaging device
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US9060126B2 true US9060126B2 (en) 2015-06-16
US10/934,886 Active 2027-09-14 US9060126B2 (en) 2003-09-04 2004-09-03 Solid-state image sensing apparatus
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