Source: https://patents.google.com/patent/US6404153B2/en
Timestamp: 2019-07-18 16:12:23
Document Index: 432701789

Matched Legal Cases: ['art 43', 'art 31', 'art 44', 'art 31', 'art 32', 'art 3', 'art 3', 'art 31', 'art 42', 'art 22', 'art 22', 'art 42', 'art 30', 'art 22', 'art 21', 'art 22', 'art 32', 'art 20', 'art 32', 'art 20', 'art 20', 'art 20', 'art 32', 'art 22', 'art 32', 'art 43', 'art 31', 'art 30', 'art 22', 'art 22', 'art 30', 'art 30', 'art 30', 'art 30', 'art 41', 'art 701', 'art 700', 'art 701', 'art 701', 'art 701', 'art 701', 'art 21', 'art 701', 'art 701', 'art 701', 'art 701']

US6404153B2 - Motor and disk drive apparatus - Google Patents
US6404153B2
US6404153B2 US09/731,196 US73119600A US6404153B2 US 6404153 B2 US6404153 B2 US 6404153B2 US 73119600 A US73119600 A US 73119600A US 6404153 B2 US6404153 B2 US 6404153B2
US09/731,196
US20010002785A1 (en
1999-12-06 Priority to JP34580799 priority Critical
1999-12-06 Priority to JPHEI11-345807 priority
1999-12-06 Priority to JP11-345807 priority
2000-12-06 Application filed by Panasonic Corp filed Critical Panasonic Corp
2000-12-06 Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GOTOU, MAKOTO
2001-06-07 Publication of US20010002785A1 publication Critical patent/US20010002785A1/en
2002-06-11 Publication of US6404153B2 publication Critical patent/US6404153B2/en
In a motor and a disk drive apparatus using the motor, a switching control part produces a PWM pulse signal in response to the comparison result between a current detected signal and a command signal. An activate control part determines the active periods of power transistors in response to the holding state of the state holding part, and performs high-frequency switching operation to turn ON/OFF the power transistors in response to the PWM pulse signal of the switching control part. Furthermore, a voltage detecting part stops the detection of terminal voltages for a predetermined time in response to the PWM operation by the switching control part. After the stop, the voltage detecting part resumes the detection of the terminal voltages. This prevents improper detection caused by PWM noise.
In the conventional configuration, power loses of the power transistors are large, and heat generation at the motor and the disk drive apparatus causes problems. The NPN power transistors 2021, 2022 and 2023 and the PNP power transistors 2025, 2026 and 2027 supply drive voltages having desired amplitudes to the windings 2012, 2013 and 2014 by controlling the voltage across the emitter and the collector in an analogue manner. Each of the NPN power transistors 2021, 2022 and 2023 and the PNP power transistors 2025, 2026 and 2027 changes the voltage across the emitter and the collector depending on the change in the resistance value across the emitter and the collector. Therefore, a remaining voltage in each power transistor is large, and a large power loss produced by the product of the large remaining voltage and the conducted current is generated, resulting in heat generation at each power transistor. Since a recordable disk (a RAM disk, a rewritable disk, etc.) is susceptible to heat, the heat generation at the power transistors, i.e., the main heat sources of the disk drive apparatus, is desired to be reduced as low as possible in order to improve the reliability of recording and/or-reproducing on/from the recordable disk.
A motor in accordance with the present invention comprises:
power supplying means having Q first power transistors and Q second power transistors for supplying a power to the Q-phase windings, each of the Q first power transistors forming a current path between one output terminal side of the voltage supplying means and one of the Q-phase windings, and each of the Q second power transistors forming a current path between the other output terminal side of the voltage supplying means and one of the Q-phase windings;
voltage detecting means for producing a detected pulse signal;
state shifting means for shifting a holding state from one state to at least one other state in sequence responding with the detected pulse signal of the voltage detecting means;
activation control means for controlling active periods of the Q first power transistors and the Q second power transistors responding with the holding state; and
switching operation means for causing at least one of the Q first power transistors and the Q second power transistors to perform high-frequency switching corresponding to a command signal;
the activation control means produces Q-phase first activation control signals and Q-phase second activation control signals responding with said holding state of said state shifting means for controlling the active periods of the Q first power transistors and the Q second power transistors, each of the active periods being an electrical angle larger than 360/Q degrees,
the switching operation means produces a switching pulse signal responding with the command signal, and makes high-frequency switching operation of at least one power transistor among the Q first power transistors and the Q second power transistors responding with the switching pulse signal, and
the voltage detecting means stops detecting of the detected pulse signal during at least one of a first stop period including a changing timing from OFF to ON of the at least one power transistor and a second stop period including another changing timing from ON to OFF of the at least one power transistor, and executes detecting of the detected pulse signal during at least ON period of the at least one power transistor excluding the at least one of the first stop period and the second stop period, thereby producing the detected pulse signal responding with terminal voltages of the Q-phase windings. With this configuration, the switching operation means subjects the power transistors of the power supplying means to high-frequency switching. Therefore, power loses at the power transistors of the power supplying means can be reduced significantly, and heat generation at the motor can also be reduced greatly. In addition, the voltage detecting means produces the detected pulse signal responding with the terminal voltages of the windings, and the state shifting means shifts the phases of the activation to the windings in response to the detected pulse signal. Furthermore, the activation control means activates the power transistors responding with the holding state so as to rotate the rotor in a predetermined direction. Therefore, no position detecting element is required, and the configuration of the motor is simplified. Moreover, each of the active periods of the first power transistors and the second power transistors is made larger than an electrical angle of 360/Q degrees. Therefore, two power transistors among the first power transistors or the second power transistors are activated simultaneously in an alteration of current paths. The alteration of current paths is thus smoothened, and the generated drive force has less pulsation. As a result, the vibration and the acoustic noise of the motor can be reduced. In addition, the power transistor/transistors is/are subjected to high-frequency switching operation by using the switching pulse signal. The detection of the detected pulse signal is stopped at least one of the first stop period including the changing timing from OFF to ON of the power transistor and the second stop period including the other changing timing from ON to OFF of the power transistor. Therefore, it is possible to prevent improper detection owing to high-frequency noises in the terminal voltages caused by the high-frequency switching operation of the power transistor/transistors. In addition, the detection of the detected pulse signal in response to the result of the comparison of the winding terminal voltages is performed during at least the ON period of the power transistor excluding at least one of the above-mentioned stop periods. It is therefore possible to produce the detected pulse signal promptly responding with the comparison result of the terminal voltages. In other words, it is possible to obtain the detected pulse signal accurately responding with the terminal voltages. Therefore, the alteration of current paths to the windings can be performed at accurate timing in response to the detected pulse signal of the voltage detecting means, and the rotor can be rotated smoothly and accurately. Furthermore, in the case when speed control is performed in response to an output pulse signal such as the detected pulse signal of the voltage detecting means for example, the rotational speed of the rotor can be controlled accurately. In other words, it is possible to attain an accurate rotation of the motor without an influence of high-frequency switching noises in the terminal voltages. As a result, an excellent motor without a position detecting element can be realized, which reduces the power consumption, the motor vibration and the acoustic noise, according to the present invention.
A motor in accordance with another aspect of the present invention comprises:
the voltage detecting means includes:
voltage comparing means for producing an output signal responding with comparison result of terminal voltages of the Q-phase windings, and
noise eliminating means for gating the output signal of the voltage comparing means with a noise eliminating signal responding or corresponding with the switching pulse signal, so as not to pass the output signal of the voltage comparing means during at least one of a first period including a changing timing from OFF to ON of the switching pulse signal and a second period including another changing timing from ON to OFF of the switching pulse signal.
With this configuration, the switching operation means subjects the power transistors of the power supplying means to high-frequency switching. Therefore, power loses at the power transistors of the power supplying means can be reduced significantly, and heat generation at the motor can also be reduced greatly. In addition, the voltage detecting means produces the detected pulse signal responding with the terminal voltages of the windings, and the state shifting means shifts the phases of the activation to the windings in response to the detected pulse signal. Furthermore, the activation control means activates the power transistors responding with the holding state so as to rotate the rotor in a predetermined direction. Therefore, no position detecting element is required, and the configuration of the motor is simplified. Moreover, each of the active periods of the first power transistors and the second power transistors is made larger than an electrical angle of 360/Q degrees. Therefore, two power transistors among the first power transistors or the second power transistors are activated simultaneously in an alteration of current paths. The alteration of current paths is thus smoothened, and the generated drive force has less pulsation. As a result, the vibration and the acoustic noise of the motor can be reduced. Furthermore, the voltage detecting means comprises the voltage comparing means and the noise eliminating means. In the noise eliminating means, the output signal of the voltage comparing means is logically gated with the noise eliminating signal which is responding with the switching pulse signal. In particular, the output signal of the voltage comparing means is nullified during at least one of the first period including the changing timing from OFF to ON of the switching pulse signal and the second period including the changing timing from ON to OFF of the switching pulse signal. Therefore, it is possible to produce the detected pulse signal free from an influence of noise due to the high-frequency switching operation of the power transistors. Furthermore, since the detected pulse signal responding with the output signal of the voltage comparing means is produced, it is possible to obtain the detected pulse signal promptly responding with the comparison result of the winding terminal voltages. Therefore, the alteration of current paths to the windings can be performed at accurate timing in response to the detected pulse signal of the voltage detecting means, and the rotor can be rotated smoothly and accurately. Furthermore, in the case when speed control is performed in response to an output pulse signal such as the detected pulse signal of the voltage detecting means for example, the rotational speed of the rotor can be controlled accurately. In other words, it is possible to attain an accurate rotation of the motor without an influence of high-frequency switching noises in the terminal voltages. As a result, an excellent motor without a position detecting element can be realized, which reduces the power consumption, the motor vibration and the acoustic noise, according to the present invention.
switching operation means for causing at least one of said Q first power transistors and said Q second power transistors to perform high-frequency switching corresponding to a command signal;
said state shifting means shifts said holding state from a first state to a second state after a first adjust time from detection of said detected pulse signal, and further shifts said holding state from said second state to a third state after a second adjust time from detection of said detected pulse signal, said second adjust time being larger than said first adjust time,
said activation control means produces Q-phase first activation control signals and Q-phase second activation control signals responding with said holding state of said state shifting means for controlling said active periods of said Q first power transistors and said Q second power transistors, each of said active periods being an electrical angle larger than 360/Q degrees, and
current detecting means for producing a current detected signal responding with or corresponding to a current from said voltage supplying means to said Q-phase windings, and
switching control means for comparing an output signal of said current detecting means with said command signal and producing a switching pulse signal responding with the comparison result, thereby making high-frequency switching operation of at least one power transistor among said Q first power transistors and said Q second power transistors responding with said switching pulse signal.
With this configuration, the switching operation means subjects the power transistors of the power supplying means to high-frequency switching. Therefore, power losses at the power transistors of the power supplying means can be reduced significantly, and heat generation at the motor can also be reduced greatly.
In addition, the voltage detecting means produces the detected pulse signal responding with the terminal voltages of the windings, and the state shifting means shifts the phases of the activation to the windings in response to the detected pulse signal.
Furthermore, the activation control means activates the power transistors responding with the holding state so as to rotate the rotor in a predetermined direction. Therefore, no position detecting element is required, and the configuration of the motor is simplified.
In addition, the state shifting means shifts the holding state from a first state to a second state after a first adjust time from detection of said detected pulse signal, and further shifts the holding state from the second state to a third state after a second adjust time (the second adjust time>the first adjust time) from detection of the detected pulse signal. The activation control means produces Q-phase first activation control signals and Q-phase second activation control signals responding with the holding state of the state shifting means for controlling the active periods of the Q first power transistors and the Q second power transistors. With this configuration, each of the active periods of the Q first power transistors and the Q second power transistors is made larger than an electrical angle of 360/Q degrees. Furthermore, the switching operation means controls the supply current to the Q-phase windings from the voltage supplying means in correspondence with the command signal by making high-frequency switching operation of at least one power transistor among the Q first power transistors and the Q second power transistors. With this configuration, two power transistors among the Q first power transistors or the Q second power transistors are activated simultaneously in each alteration of current paths while the at least one power transistor performs the high-frequency switching operation so as to control the supply current responding with the command signal.
Therefore, the supply current to the Q-phase windings is controlled responding with the command signal even when the two power transistors are activated simultaneously, and the pulsation of the generated drive force can be reduced. Furthermore, the alteration of current paths is thus smoothened by the simultaneous activation of the two power transistors, the pulsation of the generated drive force can further be reduced. As a result, an excellent motor without a position detecting element can be realized, which reduces the power consumption, the motor vibration and the acoustic noise, according to the present invention.
The switching operation means can be configured so as to include current detecting means for obtaining a current detected signal responding with the supply current to the Q-phase windings from the voltage supplying means, and switching control means for comparing the output signal of the current detecting means with the command signal and producing a switching pulse signal responding with the comparison result, thereby making high-frequency switching operation of at least one power transistor among the Q first power transistors and the Q second power transistors responding with the switching pulse signal. With this configuration, it is easy to control the supply current to the Q-phase windings responding with the command signal even when the two power transistors among the Q first power transistors or the Q second power transistors are activated simultaneously during an alteration of current paths.
The state shifting means can be configured so as to change the first adjust time and the second adjust time in response to an interval of the detected pulse signal. With this configuration, each of the active periods of the Q first power transistors and the Q second power transistors is easily made larger than 360/Q degrees (the period can be held at 130 degrees or more for example) even if the rotational speed of the rotor changes widely.
A disk drive apparatus in accordance with the present invention comprises:
processing means for at least processing an output signal from the head and outputting a reproducing information signal, or processing a recording information signal and outputting a signal into the head;
a rotor which has a field part generating field fluxes, and directly drives the disk;
the voltage detecting means stops detecting of the detected pulse signal during at least one of a first stop period including a changing timing from OFF to ON of the at least one power transistor and a second stop period including another changing timing from ON to OFF of the at least one power transistor, and executes detecting of the detected pulse signal during at least ON period of the at least one power transistor excluding the at least one of the first stop period and the second stop period, thereby producing the detected pulse signal responding with terminal voltages of the Q-phase windings.
With this configuration, the switching operation means subjects the power transistors of the power supplying means to high-frequency switching. Therefore, power loses at the power transistors of the power supplying means can be reduced significantly, and heat generation at the disk drive apparatus can also be reduced greatly. In addition, the voltage detecting means produces the detected pulse signal responding with the terminal voltages of the windings, and the state shifting means shifts the phases of the activation to the windings in response to the detected pulse signal. Furthermore, the activation control means activates the power transistors responding with the holding state so as to rotate the disk in a predetermined direction. Therefore, no position detecting element is required, and the configuration of the disk drive apparatus is simplified. Furthermore, each of the active periods of the first power transistors and the second power transistors is made larger than an electrical angle of 360/Q degrees. Therefore, two power transistors among the first power transistors or the second power transistors are activated simultaneously in an the alteration of current paths. The alteration of current paths is thus smoothened, and the generated drive force has less pulsation. As a result, the disk drive apparatus has a low vibration and a low acoustic noise. In addition, the power transistor/transistors is/are subjected to high-frequency switching operation by using the switching pulse signal. The detection of the detected pulse signal is stopped at least one of the first stop period including the changing timing from OFF to ON of the power transistor and the second stop period including the other changing timing from ON to OFF of the power transistor. Therefore, it is possible to prevent improper detection owing to high-frequency noises in the terminal voltages caused by the high-frequency switching operation of the power transistor/transistors. In addition, the detection of the detected pulse signal in response to the result of the comparison of the winding terminal voltages is performed during at least the ON period of the power transistor excluding at least one of the above-mentioned stop periods. It is therefore possible to produce the detected pulse signal promptly responding with the comparison result of the terminal voltages. In other words, it is possible to obtain a detected pulse signal accurately responding with the terminal voltages. Therefore, the alteration of current paths to the windings can be performed at accurate timing in response to the detected pulse signal of the voltage detecting means, and the disk can be rotated smoothly and accurately. Furthermore, in the case when speed control is performed in response to an output pulse signal such as the detected pulse signal of the voltage detecting means for example, the rotational speed of the disk can be controlled accurately. In other words, it is possible to attain an accurate rotation of the disk without an influence of high-frequency switching noises in the terminal voltages. As a result, an excellent disk drive apparatus can be realized, which reduces the power consumption, the disk vibration and the acoustic noise, according to the present invention.
A disk drive apparatus in accordance with another aspect of the present invention comprises:
With this configuration, the switching operation means subjects the power transistors of the power supplying means to high-frequency switching. Therefore, power loses at the power transistors of the power supplying means can be reduced significantly, and heat generation at the disk drive apparatus can also be reduced greatly. In addition, the voltage detecting means produces the detected pulse signal responding with the terminal voltages of the windings, and the state shifting means shifts the phases of the activation to the windings in response to the detected pulse signal. Furthermore, the activation control means activates the power transistors responding with the holding state so as to rotate the rotor in a predetermined direction. Therefore, no position detecting element is required, and the configuration of the disk drive apparatus is simplified.
Furthermore, each of the active periods of the first power transistors and the second power transistors is made larger than an electrical angle of 360/Q degrees. Therefore, two power transistors among the first power transistors or the second power transistors are activated simultaneously in an alteration of current paths. The alteration of current paths is thus smoothened, and the generated drive force has less pulsation. As a result, the vibration and the acoustic noise of the disk drive apparatus can be reduced.
Furthermore, the voltage detecting means comprises the voltage comparing means and the noise eliminating means. In the noise eliminating means, the output signal of the voltage comparing means is logically gated by the noise eliminating signal which is responding with the switching pulse signal. In particular, the output signal of the voltage comparing means is nullified during at least one of the first period including the changing timing from OFF to ON of the switching pulse signal and the second period including the changing timing from ON to OFF of the switching pulse signal. Therefore, it is possible to produce the detected pulse signal free from an influence of noise due to the high-frequency switching operation of the power transistors.
Furthermore, since the detected pulse signal responding with the output signal of the voltage comparing means is produced, it is possible to obtain the detected pulse signal promptly responding with the comparison result of the winding terminal voltages. Therefore, the alteration of current paths to the windings can be performed at accurate timing in response to the detected pulse signal of the voltage detecting means, and the disk can be rotated smoothly and accurately. Furthermore, in the case when speed control is performed in response to an output pulse signal such as the detected pulse signal of the voltage detecting means for example, the rotational speed of the disk can be controlled accurately. In other words, it is possible to attain an accurate rotation of the disk without an influence of high-frequency switching noises in the terminal voltages. As a result, an excellent disk drive apparatus can be realized, which reduces the power consumption, the disk vibration and the acoustic noise, according to the present invention.
a rotor, which has a field part generating field fluxes, and directly drives said disk;
voltage supplying means, which includes two output terminals for supplying a DC voltage;
Furthermore, the activation control means activates the power transistors responding with the holding state so as to rotate the rotor in a predetermined direction. Therefore, no position detecting element is required, and the configuration of the disk drive apparatus is simplified.
In addition, the state shifting means shifts the holding state from a first state to a second state after a first state adjust time from detection of said detected pulse signal, and further shifts the holding state from the second state to a third state after a second adjust time (the second adjust time >the first adjust time) from detection of the detected pulse signal. The activation control means produces Q-phase first activation control signals and Q-phase second activation control signals responding with the holding state of the state shifting means for controlling the active periods of the Q first power transistors and the Q second power transistors. With this configuration, each of the active periods of the Q first power transistors and the Q second power transistors is made larger than an electrical angle of 360/Q degrees. Furthermore, the switching operation means controls the supply current to the Q-phase windings from the voltage supplying means in correspondence with the command signal by making high-frequency switching operation of at least one power transistor among the Q first power transistors and the Q second power transistors. With this configuration, two power transistors among the Q first power transistors or the Q second power transistors are activated simultaneously in each alteration of current paths while the at least one power transistor performs the high-frequency switching operation so as to control the supply current responding with the command signal.
Therefore, the supply current to the Q-phase windings is controlled responding with the command signal even when the two power transistors are activated simultaneously, and the pulsation of the generated drive force can be reduced. Furthermore, the alteration of current paths is thus smoothened by the simultaneous activation of the two power transistors, the pulsation of the generated drive force can further be reduced. As a result, an excellent disk drive apparatus without a position detecting element can be realized, which reduces the power consumption, the disk vibration and the acoustic noise, according to the present invention.
The switching operation means can be configured so as to include current detecting means for obtaining a current detected signal responding with the supply current to the Q-phase windings from the voltage supplying means, and switching control means for comparing the output signal of the current detecting means with the command signal and producing a switching pulse signal responding with the comparison result, thereby making high-frequency switching operation of at least one power transistor among the Q first power transistors and the Q second power transistors responding with the switching pulse signal. With this configuration, it is easy to control the supply current to the Q-phase windings responding with the command signal even when the two power transistors among the Q first power transistors or the Q second power transistors are activated simultaneously during an altration of current paths.
These and other configurations and operations will be described in detail in the explanations of embodiments according to the present invention.
FIG. 13 is a waveform diagram illustrating the operation of the timing adjust part 43 of the state shifting part 31 in accordance with the embodiment 1;
FIG. 14 is a waveform diagram illustrating the operation of the state holding part 44 of the state shifting part 31 and the operation of the first selecting means 401 and the second selecting means 402 of the activation control part 32 in accordance with the embodiment 1;
FIG. 15 is a waveform diagram illustrating the operation of the compare pulse part shown in FIG. 10 in accordance with the embodiment 1;
FIG. 16 is a waveform diagram illustrating the operation of the compare pulse part shown in FIG. 11 in accordance with the embodiment 1;
FIG. 17 is a waveform diagram illustrating the operation of the PWM pulse part shown in FIG. 12 in accordance with the embodiment 1;
FIG. 19 is a waveform diagram illustrating the operation of the PWM pulse part shown in FIG. 18 in accordance with the embodiment 1;
FIG. 21 is a waveform diagram illustrating the operation of the PWM pulse part shown in FIG. 20 in accordance with the embodiment 1;
FIG. 24 is a block diagram relating to the signal of the disk drive apparatus in accordance with the embodiment 1 and the embodiment 2;
FIG. 24(a) shows an example of a disk drive apparatus for reproducing a signal in accordance with the embodiment 1. The disk 1 recorded a digital signal is directly rotated by the rotor 11 therewith. The head 2 reproduces the signal from the disk 1 and outputs a reproducing signal Pf. The signal processing part 3 digitally processes the reproducing signal Pf from the head 2 and outputs a reproduction signal Pg. The stator and windings of the apparatus are not shown herein.
FIG. 24(b) shows an example of a disk drive apparatus for recording a signal in accordance with the embodiment 1. The disk 1 is directly rotated by the rotor 11 therewith. The disk 1 is a recordable disk and capable of recording a digital signal at a high density. The signal processing part 3 digitally processes an input recording signal Rg and outputs a recording signal Rf to the head 2. The head 2 records the recording signal Rf on the disk 1.
FIG. 4 shows another configuration of the voltage comparing part. The voltage composing circuit 170 of the voltage comparing part of FIG. 4 produces a composed common voltage Vcr by composing the three-phase terminal voltages V1, V2 and V3 with resistors 171, 172 and 173. The switches 181, 182 and 183 of a first signal selecting circuit 180 selectively input one of the terminal voltages V1, V2 and V3 to a comparator circuit 185 in response to the first select command signal Bs2 of a select command circuit 195. The comparator circuit 185 compares the selected terminal voltage with the composed common voltage Vcr and outputs a compared pulse signal b8. An inverter circuit 186 outputs a pulse signal b9 by inverting the compared pulse signal b8. The switch 191 of a second signal selecting circuit 190 selects one of the pulse signals b8 and b9 depending on the second select command signal Bs3 of the select command circuit 195, and outputs the signal as the selective voltage compared signal Bj. The select command circuit 195 outputs the first select command signal Bs2 and the second select command signal Bs3 responding with the holding state of the state shifting part 31 described later. A pulse signal in the pulse signals b8 and b9, which corresponds to the states of the activation to the three-phase windings 12, 13 and 14, is selected and output as the selective voltage compared signal Bj.
The relationship among these signal waveforms is exemplified in FIG. 13 (the abscissa of FIG. 13 represents time). The first counter circuit 303 produces the count value corresponding to the time interval T0 (pulse interval T0) between the successive rising edges of the detected pulse signal Dt shown in the part (a) of FIG. 13. The second counter circuit 304 outputs the first zero pulse signal Df delayed by a first adjust time T1 (T1<T0), the first adjust time T1 being substantially proportional to the time interval T0 (see the part (b) in FIG. 13). As a result, the first timing adjust signal F1 becomes a pulse signal delayed by the first adjust time T1 substantially proportional to the time interval T0 from the rising edge of the detected pulse signal Dt (see the part (c) in FIG. 13). After the rising edge of the first zero pulse signal Df is generated, the third counter circuit 305 outputs the second zero pulse signal Dg delayed by a predetermined time substantially proportional to the time interval T0 (see the part (d) in FIG. 13). As a result, the second timing adjust signal F2 becomes a pulse signal delayed by the second adjust time T2 (T1<T2<T0) substantially proportional to the time interval T0 (see the part (e) in FIG. 13) from the generation moment of the rising edge of the detected pulse signal Dt. In a similar way, the delay pulse generating circuit 310 outputs the third timing adjust signal F3 delayed by a predetermined time from the generation moment of the rising edge of the second zero pulse signal Dg (see the part (f) in FIG. 13). As a result, the third timing adjust signal F3 becomes a pulse signal delayed by the third adjust time T3 (T2<T3<T0) substantially proportional to the time interval T0 from the generation of the rising edge of the detected pulse signal Dt. The third timing adjust signal F3 is input to the pulse generating circuit 202 of the detected pulse producing part 42, and the detected pulse signal Dt is reset by the generation of the third timing adjust signal F3 (see the part (a) in FIG. 13).
A first pulse composing circuit 403 produces the three-phase low-side activation control signals M1, M2 and M3 by composing logically the first selecting signals Mm1, Mm2 and Mm3 and the main PWM pulse signal Wm of the switching control part 22. Each of the low-side activation control signals M1, M2 and M3 becomes coincident with the main PWM pulse signal Wm in each active period. By the connection of the switch circuit 461 of the auxiliary selecting circuit 406, a high-side auxiliary signal Wj becomes a signal coincident with the auxiliary PWM pulse signal Wh of the switching control part 22 or becomes the “L” state. A second pulse composing circuit 404 produces three-phase auxiliary activation control signals Mm5, Mm6 and Mm7 by composing logically the first selecting signals Mm1, Mm2 and Mm3 and the high-side auxiliary signal Wj. In the case when the switch circuit 461 of the auxiliary selecting circuit 406 is connected to its Sa side, the high-side auxiliary signal Wj becomes coincident with the auxiliary PWM pulse signal Wh. So each of the auxiliary activation control signals Mm5, Mm6 and Mm7 becomes coincident with the auxiliary PWM pulse signal Wh in each “H” state period of the first selecting signals Mm1, Mm2 and Mm3. In the case when the switch circuit 461 of the auxiliary selecting circuit 406 is connected to its Sb side, the high-side auxiliary signal Wj becomes the “L” state, and the auxiliary activation control signals Mm5, Mm6 and Mm7 of the second pulse composing circuit 404 become the “L” state. A third pulse composing circuit 405 composes the second selecting signals Nn1, Nn2 and Nn3 and the auxiliary activation control signals Mn5, Mm6 and Mm7 respectively, and produces the high-side activation control signals N1, N2 and N3.
FIG. 14 shows the relationship among the first state signals P1 to P6, the second state signals Q1 to Q6, the first selecting signals Mm1, Mm2 and Mn3, and the second selecting signals Nn1, Nn2 and Nn3. The abscissa of FIG. 14 represents time. The first state signals P1 to P6 are six-phase signals which are shifted at every generation of the first timing adjust signal F1 (see the parts (a) to (f) in FIG. 14). The second state signals Q1 to Q6 are six-phase signals which are shifted at every generation of the second timing adjust signal F2 (see the parts (g) to (l) in FIG. 14). The first selecting signals Mm1, Mm2 and Mm3 are produced by composing logically the first state signals P1 to P6 and the second state signals Q1 to Q6, and each of the “H” periods of the three-phase first selecting signals Mm1, Mn2 and Mm3 becomes larger than an electrical angle of 120 degrees (see the parts (p) to (r) in FIG. 14). More specifically, the first selecting signals Mm1, Mm2 and Mm3 become three-phase signals, each having a “H” period equal to about 140 degrees. An electrical angle of 360 degrees corresponds to the rotation angle of the one set of the N and S poles of the rotor. In a similar way, the second selecting signals Nn1, Nn2 and Nn3 are produced by composing logically the first state signals P1 to P6 and the second state signals Q1 to Q6, each of the “H” periods of the three-phase second selecting signals becomes larger than an electrical angle of 120 degrees (see the parts (m) to (o) in FIG. 14). More specifically, the second selecting signals Nn1, Nn2 and Nn3 become three-phase signals, each having a “H” period equal to about 140 degrees. In addition, the first selecting signal and the second selecting signal being in phase with each other are opposite-phase signals having a phase difference of an electrical angle of 180 degrees (for example, Mm1 and Nn1).
FIG. 11 shows another configuration of the compare pulse part. The compare pulse part of FIG. 11 comprises a compare circuit 521, a reference pulse circuit 522 and a basic PWM pulse circuit 523. The compare circuit 521 compares the current detected signal Ad with the command signal Ac. When the current detected signal Ad becomes larger than the command signal Ac, the compare signal Ap is changed to “H.” The reference pulse circuit 522 outputs a reference pulse signal Ar at predetermined time intervals. The basic PWM pulse circuit 523 comprises a flip-flop for example, and sets its internal state to “H” at the rising edge of the reference pulse signal Ar, thereby setting the basic PWM pulse signal Wp to “H.” The basic PWM pulse circuit 523 sets its internal state to “L” at the rising edge of the compare signal Ap, thereby setting the basic PWM pulse signal Wp to “L.” Parts (a) to (c) in FIG. 16 show the relationship among the reference pulse signal Ar, the compare signal Ap and the basic PWM pulse signal Wp. The abscissa of FIG. 16 represents time. The basic PWM pulse signal Wp becomes “H” responding with the arrival of the pulses of the reference pulse signal Ar, and the basic PWM pulse signal Wp becomes “L” at the rising edge of the compare signal Ap. In this way, the basis PWM pulse signal Wp becomes a PWM signal responding with the result of the comparison between the current detected signal Ad and the command signal Ac. Furthermore, in the period wherein the reference pulse signal Ar is “H,” the basic PWM pulse signal Wp can be forcibly set to “L.” As a result, the basic PWM pulse signal Wp becomes a switching signal changing securely with a PWM frequency responding with the frequency of the reference pulse signal Ar.
Parts (a) to (f) in FIG. 17 show the relationship among the basic PWM pulse signal Wp, the first whole pulse delay signal Wa, the second whole pulse delay signal Wb, the main PWM pulse signal Wm, the auxiliary PWM pulse signal Wh and the noise eliminating signal Wx. The abscissa of FIG. 17 represents time. The first whole pulse delay signal Wa is a signal obtained by delaying wholly the basic PWM pulse signal Wp by the first predetermined time Ta. The second whole pulse delay signal Wb is a signal obtained by delaying wholly the first whole pulse delay signal Wa by the second predetermined time Tb (see the part (a) to (c) in FIG. 17). Since the main PWM pulse signal Wm is a signal obtained by outputting the first whole pulse delay signal Wa via a buffer circuit 561, the waveform of the main PWM pulse signal Wm is the same as that of the first whole pulse delay signal Wa (see the parts (b) and (d) in FIG. 17). The auxiliary PWM pulse signal Wh is obtained by composing logically the basic PWM pulse signal Wp and the second whole pulse delay signal Wb with a NOR circuit 562, and has the waveform shown in the part (e) of FIG. 17. In addition, the “H” period of the auxiliary PWM pulse signal Wh is within the “L” period of the main PWM pulse signal Wm. Therefore, the main PWM pulse signal Wm and the auxiliary PWM pulse signal Wh do not become “H” simultaneously. In other words, a time difference equal to the first predetermined time Ta or the second predetermined time Tb is provided between the “H” period of the auxiliary PWM pulse signal Wh and the “H” period of the main PWM pulse signal Wm. The noise eliminating signal Wx is obtained by composing logically the basic PWM pulse signal Wp and the second whole pulse delay signal Wb with an exclusive NOR circuit 563, and has the waveform shown in the part (f) of FIG. 17. The “L” period of the noise eliminating signal Wx includes the changing timing or the changing moment of the main PWM pulse signal Wm, and has at least the predetermined time Tb from the changing timing. This noise eliminating signal Wx is input to the noise eliminating circuit 201 of the detected pulse producing part 42 of the voltage detecting part 30. Noises, occurring on the comparison detected signals of the winding terminal voltages in accordance with the high-frequency switching operations of the power transistors, are eliminated with the noise eliminating signal Wx. Besides, the noise eliminating signal Wx can be produced by composing logically the main PWM pulse signal Wm and the second whole pulse delay signal Wb with an exclusive NOR circuit. In this case, the “L” period of the noise eliminating signal Wx includes substantially the changing timing from OFF to ON and the changing timing from ON to OFF of the high-frequency switching operation of the power transistor. In other words, the noise eliminating signal Wx is produced in response to the basic PWM pulse signal Wp, and becomes “L” in a predetermined period including the changing timing of the high-frequency switching operation of the power transistor. The time ratio wherein the noise eliminating signal Wx becomes “L” is about 20% (less than 50%). Therefore, the time for detecting the terminal voltages of the windings is much longer than the time for eliminating noise (the time for not detecting the terminal voltages).
The switching control part 22 and the current detecting part 21 form a switching operation block, and the switching operation block operates to supply PWM pulse-like drive voltages V1, V2 and V3 to the three-phase windings 12, 13 and 14, respectively. In response to the main PWM pulse signal Wm of the switching control part 22, the low-side activation control signals M1, M2 and M3 of the activation control part 32 become PWM pulse signals. One or two of the low-side power transistors 101, 102 and 103 of the power supplying part 20, which are selected by the low-side activation control signals M1, M2 and M3 of the activation control part 32, perform ON-OFF high-frequency switching operation simultaneously. The power supplying part 20 thus supplies the negative parts of the drive current signals I1, I2 and I3 to the windings 12, 13 and 14, respectively. When the low-side power transistors 101, 102 and 103 of the power supplying part 20 turn OFF, one or two of the high-side power diodes 105 d, 106 d and 107 d turn ON by the inductive reaction of the windings, thereby continuously supplying the negative parts of the drive currents I1, I2 and I3 to the windings 12, 13 and 14. As a result, the drive voltages V1, V2 and V3 to the three-phase windings 12, 13 and 14 become PWM voltages. This significantly reduces the power loses of the low-side power transistors 101, 102 and 103 of the power supplying part 20.
The case wherein the high-side auxiliary signal Wj of the activation control part 32 coincides with the auxiliary PWM pulse signal Wh of the switching control part 22 will be described below. This corresponds to the case wherein the switch circuit 461 of the auxiliary selecting circuit 406 is connected to the Sa side. The auxiliary PWM pulse signal Wh is a PWM signal turning OFF/ON complementarily to the ON-OFF PWM of the main PWM pulse signal Wm. Each of the high-side activation control signals N1, N2 and N3 of the activation control part 32 includes a PWM pulse signal responding with the auxiliary PWM pulse signal Wh. In the period during which one of the above-mentioned high-side power diodes turns ON, each of the high-side activation control signals N1, N2 and N3 activates the high-side power transistor having the same phase. In other words, the high-side power transistor having the same phase with the low-side power transistor performing ON-OFF high-frequency switching operation is controlled so as to perform OFF-ON high-frequency switching operation complementarily to the ON-OFF high-frequency switching operation of the low-side power transistor. As a result, power loses caused by the high-side power diodes can be reduced, whereby power loses and heat generation can thus be reduced further. Since the auxiliary PWM pulse signal Wh is auxiliary, its function can be eliminated (by connecting the switch 461 to the Sb side) as described above.
The timing adjust part 43 of the state shifting part 31 detects the arrival of the rising edge of the detected pulse signal Dt, and the first counter circuit 303 measures the time interval T0 between successive two detection edges of the detected pulse signal Dt. The second counter circuit 304 outputs the first timing adjust signal F1 delayed from the detection edge of the detected pulse signal Dt by the first adjust time T1 responding with the time interval T0. In addition, the second counter circuit 304 and the third counter circuit 305 output the second timing adjust signal F2 delayed from the detection edge of the detected pulse signal Dt by the second adjust time T2 responding with the time interval T0. Furthermore, the delayed pulse generating circuit 310 outputs the third timing adjust signal F3 delayed from the detection edge of the detected pulse signal Dt by the third adjust time T3 responding with the time interval T0 (see FIG. 13). It is herein assumed that the relationship of T1<T2<T3<T0 is established.
Furthermore, the voltage detecting part includes the pulse generating circuit. The state of the flip-flop of the pulse generating circuit is changed in response to the generation of the rising edge of the output signal of noise eliminating means, thereby producing the detected pulse signal responding with the state of the flip-flop. This prevents the detected pulse signal from generating excessively, and the activation control operation is stabilized. In other words, the disk or the rotor is rotated stably. The flip-flop is reset by the third timing adjust signal after the third adjust time T3 from the detecting edge of the detected pulse signal responding with the change of the state of the flip-flop. The third adjust time T3 changes in response to the interval T0 of the detected pulse signal. Therefore, even if the rotational speed of the disk or the rotor changes widely, it is possible to prevent the detected signal from generating excessively.
In the case when the high-side auxiliary signal Wj in accordance with the present embodiment is fixed at the “L” state, the high-side diode turns ON when the low-side power transistor turns OFF. In detecting the winding terminal voltages by the voltage detecting part 30, an improper detection may occur because of the effect of the ON voltage of the high-side diode. In order to prevent the improper detection of the winding terminal voltages during the ON period of the high-side diode, the noise eliminating signal Wx may be modified so that the detection of the winding terminal voltages is carried out only during the ON period of the low-side power transistor in ON-OFF high-frequency switching operation. By substituting the configuration of the PWM pulse part shown in FIG. 18 for the PWM pulse part of the switching control part 22 shown in FIG. 12, it is possible to realize the above-mentioned operation. This configuration will be described below.
By configuring the PWM pulse part of the switching control part 22 as shown in FIG. 20, the low-side power transistors perform ON-OFF high-frequency switching operation in response to the main PWM pulse signal Wm. The high-side power transistors perform ON-OFF high-frequency switching operation in response to the auxiliary PWM pulse signal Wh. While the noise eliminating signal Wx is “L,” the voltage detecting part 30 stops the detection of the winding terminal voltages. Therefore, the voltage detecting part 30 stops the detection of the winding terminal voltages during the first stop period including the changing timing from OFF to ON and during the second stop period including the changing timing from ON to OFF of the low-side power transistor. The detection of the detected pulse signal in response to the comparison result of the winding terminal voltages is performed during the remaining period excluding the first stop period and the second stop period. Furthermore, the voltage detecting part 30 stops the detection of the winding terminal voltages during the first stop period including the changing timing from ON to OFF and during the second stop period including the changing timing from OFF to ON of the high-side power transistor. The detection of the detected pulse signal responding directly with the comparison result of the winding terminal voltages is performed during the remaining period excluding the first stop period and the second stop period. This prevents an improper detection and an improper operation caused by a PWM noise owing to the PWM switching operation of the low-side and/or high-side power transistors.
These operations are performed by using the noise eliminating signal Wx. In other words, the noise eliminating signal Wx responding with the main PWM pulse signal used as a switching pulse signal becomes “L” in the first predetermined time including the changing timing from OFF to ON and in the second predetermined time including the changing timing from ON to OFF of the switching pulse signal. The noise eliminating circuit 201 of the voltage detecting part 30 nullifies the output signal of the voltage comparing part 41 during these predetermined time periods. It is needless to say that these configurations and similar changes are included in the present invention.
The micro-computer part 701 shown in FIG. 22 receives the compared pulse signals Z1, Z2 and Z3 of the voltage comparing part 700, and detects the changing timings of the compared pulse signals corresponding to the zero-cross timings of the terminal voltages in response to the states of the activation to the windings while eliminating the influence of PWM noise. On the basis of this detection of the changing timing, the micro-computer part 701 performs timing adjustment operation for predetermined time periods and shifts its internal state. In other words, the micro-computer part 701 shifts the holding state from a first state to a second state after the first adjust time T1 from the detection of the changing timing, and further shifts the holding state from the second state to a third state after the second adjust time T2 from the detection of the changing time. The holding state in the micro-computer 701 is shifted sequentially in the twelve holding states. On the basis of this internal holding state, the micro-computer part 701 determines the active periods of the three-phase low-side activation control signals M1, M2 and M3 and the three-phase high-side activation control signals N1, N2 and N3. In addition, the micro-computer part 701 receives the current detected signal Ad of the current detecting part 21 as a digital current signal converted by an AD converter, and compares the digital current signal with a digital command signal. The micro-computer part 701 produces the main PWM pulse signal responding with the comparison result between the digital current signal and the digital command signal in the softwear, and produces the above-mentioned low-side activation control signals M1, M2 and M3 responding with the main PWM pulse signal. In other words, each of the low-side activation control signals M1, M2 and M3 is coincident with the main PWM pulse signal in each active period. Furthermore, the micro-computer part 701 produces the auxiliary PWM pulse signal responding with or corresponding to the main PWM pulse signal, and produces the above-mentioned high-side activation control signals N1, N2 and N3 responding with the auxiliary PWM pulse signal. In other words, each of the high-side activation control signals N1, N2 and N3 has an ON period without responding the auxiliary PWM pulse signal and another ON period with responding the auxiliary PWM pulse signal. As a result, the OFF-ON PWM operation of the high-side power transistors complementary to the ON-OFF PWM operation of the low-side power transistors is performed. Moreover, the micro-computer part 701 produces the noise eliminating signal responding with or corresponding to the main PWM pulse signal so as to eliminate PWM noises included in the above-mentioned compared pulse signals, thereby avoiding a miss-detection of the changing timings of the terminal voltages. The waveforms of the low-side activation control signals M1, M2 and M3 and the high-side activation control signals N1, N2 and N3 are same as those explained in the embodiment 1. Apart of these operations is not required to be executed only by using the software of the micro-computer part 701, but may be executed by using its hardware.
The configurations of the above-mentioned embodiments can be modified variously. For example, each of the three-phase windings may be formed by connecting plural winding portions in series or parallel. The connection of the three-phase windings is not limited to star connection, but delta connection may be used. Furthermore, the number of the phases of the windings is not limited to three. Generally, it is possible to realize a configuration having plural-phase windings. In addition, the number of the magnetic poles in the field part of the rotor is not limited to two, but multi-poles may be used.
In addition, in the above-mentioned embodiments, FET power transistors are used as the power transistors of the power supplying part to make high-frequency switching operation easy. With this configuration, power loses and heat generation of the power transistors are reduced, whereby the transistors can easily be formed into a one-chip integrated circuit. However, the present invention is not limited to such a case. For example, bipolar transistors or IGBT transistors can also be used as the power transistors. Furthermore, the power transistors of the power supplying part are subjected to ON-OFF high-frequency switching operation. However, the operation is not limited to full ON-OFF PWM operation, but ON-OFF PWM operation including half ON operation may be performed. For example, according to the U.S. Pat. No. 5,982,118, the drive voltages supplied to the windings are subjected to PWM operation in accordance with the output signals of three position detecting elements. This patent discloses a motor wherein FET power transistors are subjected to high-frequency switching operation between the ON state (full-ON or half-ON state) and the OFF state, in order to smoothly alternate the drive currents to the windings while reducing the power loses of the power transistors.
said activation control means produces Q-phase first activation control signals and Q-phase second activation control signals responding with said holding state of said state shifting means for controlling said active periods of said Q first power transistors and said Q second power transistors, each of said active periods being an electrical angle larger than 360/Q degrees,
said switching operation means produces a switching pulse signal responding with said command signal, and makes high-frequency switching operation of at least one power transistor among said Q first power transistors and said Q second power transistors responding with said switching pulse signal, and
said voltage detecting means stops detecting of said detected pulse signal during at least one of a first stop period including a changing timing from OFF to ON of said at least one power transistor and a second stop period including another changing timing from ON to OFF of said at least one power transistor, and executes detecting of said detected pulse signal during at least ON period of said at least one power transistor excluding said at least one of said first stop period and said second stop period, thereby producing said detected pulse signal responding with terminal voltages of said Q-phase windings.
2. The motor in accordance with claim 1, wherein
said voltage detecting means stops detecting of said detected pulse signal during both of said first stop period and said second stop period, and executes detecting of said detected pulse signal during a rest period excluding said both of said first stop period and said second stop period, thereby producing said detected pulse signal responding with terminal voltages of said Q-phase windings.
3. The motor in accordance with claim 1, wherein
voltage comparing means for producing an output signal responding with comparison result of terminal voltages of said Q-phase windings, and
noise eliminating means for gating the output signal of said voltage comparing means with a noise eliminating signal responding or corresponding with said switching pulse signal, so as not to pass the output signal of said voltage comparing means during at least one of a first period including a changing timing from OFF to ON of said switching pulse signal and a second period including another changing timing from ON to OFF of said switching pulse signal.
4. The motor in accordance with claim 3, wherein
pulse producing means having a flip-flop circuit for changing a state of said flip-flop circuit with an rising or falling edge of an output signal of said noise eliminating means and producing said detected pulse signal responding with the state of said flip-flop circuit.
5. The motor in accordance with claim 1, wherein
said state shifting means shifts said holding state from a first state to a second state after a first adjust time from detection of said detected pulse signal, and further shifts said holding state from said second state to a third state after a second adjust time from detection of said detected pulse signal, said second adjust time being larger than said first adjust time.
6. The motor in accordance with the claim 5, wherein
7. The motor in accordance with claim 5, wherein
8. The motor in accordance with claim 1, wherein
switching control means for comparing an output signal of said current detecting means with said command signal and producing said switching pulse signal responding with the comparison result.
9. The motor in accordance with claim 1, wherein
said switching operation means causes at least one first power transistor of said Q first power transistors to perform an ON-OFF high-frequency switching operation, and causes at least one second power transistor of said Q second power transistors in the same phase to perform an OFF-ON high-frequency switching operation opposite to the ON-OFF high-frequency switching operation of said at least one first power transistor.
10. The motor in accordance with claim 1, further comprising
commanding means for producing said command signal responding with an output pulse signal of said voltage detecting means.
noise eliminating means for gating said output signal of said voltage comparing means with a noise eliminating signal responding or corresponding with said switching pulse signal, so as not to pass the output signal of said voltage comparing means during at least one of a first period including a changing timing from OFF to ON of said switching pulse signal and a second period including another changing timing from ON to OFF of said switching pulse signal.
12. The motor in accordance with claim 11, wherein
13. The motor in accordance with claim 11, wherein
said state shifting means shifts said holding state from a first state to a second state after a first adjust time from detection of said detected pulse signal, and further shifts said holding state from said second state to a third state after a second adjust time from detection of said detected pulse signal, said second adjust time being larger than said first adjust time, and
said first adjust time and said second adjust time are substantially proportional to an interval of said detected pulse signal.
14. The motor in accordance with claim 11, wherein
said voltage detecting means stops detecting of said detected pulse signal from a pulse timing of said detected pulse signal to a delayed timing.
15. The motor in accordance with claim 11, wherein
16. The motor in accordance with claim 11, further comprising
18. The motor in accordance with claim 17, wherein
19. The motor in accordance with claim 17, wherein
21. The disk drive apparatus in accordance with claim 20, wherein
22. The disk drive apparatus in accordance with claim 20, wherein
23. The disk drive apparatus in accordance with claim 22, wherein
24. The disk drive apparatus in accordance with claim 20, wherein
25. The disk drive apparatus in accordance with the claim 24, wherein
26. The disk drive apparatus in accordance with claim 24, wherein
27. The disk drive apparatus in accordance with claim 20, wherein
28. The disk drive apparatus in accordance with claim 20, wherein
29. The disk drive apparatus in accordance with claim 20, further comprising
30. A disk drive apparatus comprising:
31. The disk drive apparatus in accordance with claim 30, wherein
32. The disk drive apparatus in accordance with claim 30, wherein
said first adjust time and said second adjust time are proportional to an interval of said detected pulse signal.
33. The disk drive apparatus in accordance with claim 30, wherein
34. The disk drive apparatus in accordance with claim 30, wherein
35. The disk drive apparatus in accordance with claim 30, further comprising
36. A disk drive apparatus comprising:
37. The disk drive apparatus in accordance with claim 36, wherein
38. The disk drive apparatus in accordance with claim 36, wherein
US09/731,196 1999-12-06 2000-12-06 Motor and disk drive apparatus Expired - Fee Related US6404153B2 (en)
US10/132,814 US6639372B2 (en) 1999-12-06 2002-04-24 Motor and disk drive apparatus
US10/132,814 Division US6639372B2 (en) 1999-12-06 2002-04-24 Motor and disk drive apparatus
US20010002785A1 US20010002785A1 (en) 2001-06-07
US6404153B2 true US6404153B2 (en) 2002-06-11
US09/731,196 Expired - Fee Related US6404153B2 (en) 1999-12-06 2000-12-06 Motor and disk drive apparatus
US10/132,814 Expired - Fee Related US6639372B2 (en) 1999-12-06 2002-04-24 Motor and disk drive apparatus
DE (1) DE60036595T2 (en)
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2000-12-05 DE DE2000636595 patent/DE60036595T2/en not_active Expired - Fee Related
2000-12-05 EP EP20000126716 patent/EP1107444B1/en not_active Expired - Fee Related
2000-12-06 US US09/731,196 patent/US6404153B2/en not_active Expired - Fee Related
2002-04-24 US US10/132,814 patent/US6639372B2/en not_active Expired - Fee Related
DE60036595T2 (en) 2008-07-03
EP1107444B1 (en) 2007-10-03
US20020117981A1 (en) 2002-08-29
EP1107444A2 (en) 2001-06-13
US20010002785A1 (en) 2001-06-07
DE60036595D1 (en) 2007-11-15
US6639372B2 (en) 2003-10-28
EP1107444A3 (en) 2004-03-03
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