Source: https://patents.google.com/patent/US10338927B2/en
Timestamp: 2020-04-04 12:46:14
Document Index: 320870594

Matched Legal Cases: ['Application No. 2015', 'Application No. 201510091809', 'Application No. 10', 'Application No. 10', 'Application No. 2015', 'Application No. 201510091809', 'Application No. 2016', 'Application No. 10', 'Application No. 104105377']

US10338927B2 - Method and apparatus for implementing a dynamic out-of-order processor pipeline - Google Patents
US10338927B2
US10338927B2 US15/477,374 US201715477374A US10338927B2 US 10338927 B2 US10338927 B2 US 10338927B2 US 201715477374 A US201715477374 A US 201715477374A US 10338927 B2 US10338927 B2 US 10338927B2
US20170300334A1 (en
FIGS. 10A-B illustrate a conventional out of order (OOO) pipeline and an OOO pipeline in accordance with one embodiment of the invention;
FIGS. 13A-B illustrate register renaming, scheduler logic, and cancellation logic in a conventional OOO processor in an accordance with one embodiment of the invention;
FIG. 11A illustrates an example of a superscalar allocation “line” of micro-operations (“uops”) in a conventional out-of-order processor side by side with a corresponding entity in the optimized out-of-order pipeline, the VLIW, in FIG. 11B.
an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables, and wherein the plurality of RISC instruction syllables in the VLIWs include one or more false anti-dependencies;
an out-of-order execution engine to execute at least some of the syllables in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit.
2. The apparatus of claim 1, wherein the out-of-order execution engine includes register renaming logic to map the VLIWs onto physical registers.
3. The apparatus of claim 2, wherein the register renaming logic is to implement a write phase later to a read phase for reading logical register operands to remove the one or more false anti-dependencies.
4. The apparatus of claim 2, wherein the out-of-order execution engine further comprises scheduler setup logic to evaluate dependencies between syllables prior to scheduling of the syllables for execution by functional units, the schedule setup logic to perform in parallel with a read phase of the register renaming logic.
5. The apparatus of claim 4, wherein the scheduler setup logic implements a logic write phase later to a logic read phase to remove the one or more false anti-dependencies.
6. The apparatus as in claim 5, wherein the scheduler setup logic is to further operate on each syllable in parallel with cancellation setup logic usable by the out-of-order execution engine to cancel effects of certain dispatched syllables.
8. The apparatus as in claim 7, wherein the translator comprises an optimizing compiler or binary translator including a dynamic binary translator.
9. The apparatus as in claim 7, wherein the translator resolves data-flow dependencies and false output dependencies when translating to the private ISA format such that the syllables contained within each of VLIWs fetched in-order from memory do not have data-flow dependencies and false output dependencies.
10. The apparatus as in claim 9, wherein the data-flow dependencies comprise read-after-write (“R-A-W”) dependencies and the false output dependencies comprise write-after-write (“W-A-W”) dependencies.
11. The apparatus as in claim 7, wherein the public ISA comprise the Intel Architecture (IA).
12. The apparatus as in claim 1, wherein the false anti-dependencies comprise write-after-read (“W-A-R”) dependencies.
13. The apparatus as in claim 1, wherein the syllables are of multiple types including any combination of one or more control syllables, one or more floating-point vector syllables, one or more memory syllables, and/or one or more integer ALU syllables, where each syllable may be represented by a RISC instruction of a correspondent type.
14. The apparatus as in claim 13, wherein the syllable type is defined the allowed relative position of a syllable in a VLIW.
15. The apparatus as in claim 1, wherein the out-of-order execution engine includes dispatch logic to perform non-speculative early dispatch of syllables.
16. The apparatus as in claim 1, wherein the out-of-order execution engine is fully partitioned, including a register rename/allocation unit having N partitions and a scheduler unit having N partitions.
17. The apparatus as in claim 16, wherein the partitions are physically arranged to handle certain types of instructions.
18. The apparatus as in claim 17, wherein a first partition in the scheduler unit is associated with a first type of execution unit and a second partition in the scheduler unit is associated with a second type of execution unit.
19. The apparatus as in claim 16, wherein the partitioning of the rename/allocation unit and the scheduler unit reduces the number of write ports in the out-of-order execution engine and/or memory ordering buffer, including its load and store buffers.
fetching Very Long Instruction Words (VLIWs) in program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables, and wherein the plurality of RISC instruction syllables in the VLIWs include one or more false anti-dependencies;
decoding the VLIWs in program order and output the syllables of each decoded VLIW in parallel; and
executing at least some of the syllables in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decoding.
21. The method as in claim 20, further comprises:
translating program code from a high-level programming language or a public instruction set architecture (ISA) format to a private ISA format comprising the VLIWs and syllables.
22. The method as in claim 21, wherein the public ISA comprise the Intel Architecture (IA).
23. The method as in claim 21, wherein the translating comprises resolving data-flow dependencies and false output dependencies when translating to the private ISA format such that the syllables contained within each of VLIWs fetched in-order from memory do not have data-flow dependencies and false output dependencies.
24. The method as in claim 23, wherein the data-flow dependencies comprise read-after-write (“R-A-W”) dependencies and the false output dependencies comprise write-after-write (“W-A-W”) dependencies.
25. The method as in claim 20, wherein the false anti-dependencies comprise write-after-read (“W-A-R”) dependencies.
26. The method as in claim 20, wherein the syllables are of multiple types including any combination of one or more control syllables, one or more floating-point vector syllables, one or more memory syllables, and/or one or more integer ALU syllables, where each syllable may be represented by a RISC instruction of a correspondent type.
27. The method as in claim 26, wherein the syllable type is defined the allowed relative position of a syllable in a VLIW.
US20170300334A1 US20170300334A1 (en) 2017-10-19
US10338927B2 true US10338927B2 (en) 2019-07-02
US5983336A (en) 1996-08-07 1999-11-09 Elbrush International Limited Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to designated execution units groups
JP2001306324A (en) 2000-03-30 2001-11-02 Agere Systems Guardian Corp Method and device for identifying separable packet in multi-thread vliw processor
US20020035677A1 (en) 1998-12-23 2002-03-21 Gad S. Sheaffer Method and apparatus for pre-processing instructions for a processor
TW518516B (en) 2000-06-26 2003-01-21 Texas Instruments Inc Sub-pipelined and pipelined execution in a VLIW
CN102144225A (en) 2008-05-29 2011-08-03 阿克西斯半导体有限公司 Method & apparatus for real-time data processing
JP6043374B2 (en) 2014-03-28 2016-12-14 インテル・コーポレーション Method and apparatus for implementing a dynamic out-of-order processor pipeline
EP1152329A1 (en) 2000-03-30 2001-11-07 Agere Systems Guardian Corporation Method and apparatus for identifying splittable packets in a multithreated vliw processor
Akira Nakamura, Tech I, "Introduction to Microprocessor Architecture", vol. 20, Japan, CQ Publishing Co., Ltd., Hisaki Masuda, Apr. 1, 2004, 4 pages.
Combined Search and Examination Report for Application No. GB1500942.6, dated Jul. 22, 2015, 10 pages.
Decision for Grant for foreign counterpart Japan Application No. 2015-010321, dated Sep. 13, 2016, 3 pages.
Examination Report for foreign counterpart United Kingdom Application No. GB1500942.6, dated Sep. 1, 2016, 5 pages.
First Office Action and Search Report for foreign counterpart China Application No. 201510091809.4, dated Mar. 21, 2017, 31 pages.
Intention to Grant a patent for United Kingdom Application No. GB1500942.6, dated Feb. 6, 2017, 2 pages.
Nakada et al., "An Instruction Scheduling Method with VLIW Instruction Queue for Superscalar Processors," Journal of the Information Processing Society of Japan, Information Processing Society of Japan, Jul. 2, 2009, vol. 2 No. 2., 19 pages (Best Available Copy).
Non-Final Office Action for U.S. Appl. No. 14/228,690, dated Jun. 30, 2016, 17 pages.
Notice of Allowance for foreign counterpart Korea Application No. 10-2015-0026821, dated Apr. 25, 2017, 3 pages.
Notice of Allowance for U.S. Appl. No. 14/228,690, dated Nov. 22, 2016, 27 pages.
Notice of Preliminary Rejection for foreign counterpart Korea Application No. 10-2015-0026821, dated Jun. 29, 2016, 14 pages.
Notice of Reasons for Rejection for foreign counterpart Japan Application No. 2015-010321, dated May 10, 2016, 6 pages.
Notice on Grant of Patent Right for Invention from foreign counterpart China Patent Application No. 201510091809.4, dated May 14, 2018, 4 pages.
Notification of Grant for foreign counterpart Great Britain Application No. GB1500942.6, dated Mar. 21, 2017, 2 pages.
Notification of Reasons for Refusal from foreign counterpart Japan Patent Application No. 2016-221057, dated Feb. 14, 2019, 3 pages.
Notificaton of Reason for Refusal for foreign counterpart Korea Application No. 10-2015-0026821, dated Dec. 28, 2016, 15 pages.
Office Action and Taiwan Search Report for foreign counterpart Taiwan Application No. 104105377, dated Aug. 24, 2016, 9 pages.
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