Source: http://www.google.com/patents/US7933016?dq=oakley+D523,461&ei=qiI4T-CjGqXf0QHz_PSUCA
Timestamp: 2017-04-25 17:58:37
Document Index: 299018404

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 2005', 'Application No. 2006', 'Application No. 2006']

Patent US7933016 - Apparatus and methods for detecting overlay errors using scatterometry - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsDisclosed are techniques, apparatus, and targets for determining overlay error between two layers of a sample. A plurality of targets is provided. Each target includes a portion of the first and second structures and each is designed to have an offset between its first and second structure portions....http://www.google.com/patents/US7933016?utm_source=gb-gplus-sharePatent US7933016 - Apparatus and methods for detecting overlay errors using scatterometryAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7933016 B2Publication typeGrantApplication numberUS 12/641,663Publication dateApr 26, 2011Filing dateDec 18, 2009Priority dateDec 5, 2002Fee statusPaidAlso published asDE602004032117D1, EP1601931A2, EP1601931A4, EP1601931B1, US7242477, US7280212, US7289213, US7298481, US7301634, US7317531, US7379183, US7385699, US7433040, US7564557, US7663753, US7876440, US20040169861, US20040233439, US20040233440, US20040233441, US20040233442, US20040233443, US20040233444, US20040257571, US20080024766, US20080049226, US20080094630, US20090284744, US20100091284, WO2004076963A2, WO2004076963A3Publication number12641663, 641663, US 7933016 B2, US 7933016B2, US-B2-7933016, US7933016 B2, US7933016B2InventorsWalter D. Mieher, Ady Levy, Boris Golovanevsky, Michael Friedmann, Ian Smith, Michael Adel, Anatoly Fabrikant, Christopher F. Bevis, John Fielden, Noah Bareket, Kenneth P. Gross, Piotr Zalicki, Dan Wack, Paola Dececco, Thaddeus G. Dziura, Mark GhinovkerOriginal AssigneeKla-Tencor Technologies CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (152), Non-Patent Citations (70), Referenced by (4), Classifications (19), Legal Events (1) External Links: USPTO, USPTO Assignment, EspacenetApparatus and methods for detecting overlay errors using scatterometry
US 7933016 B2Abstract
Disclosed are techniques, apparatus, and targets for determining overlay error between two layers of a sample. A plurality of targets is provided. Each target includes a portion of the first and second structures and each is designed to have an offset between its first and second structure portions. The targets are illuminated with electromagnetic radiation to thereby obtain spectra from each target at a −1st diffraction order and a +1st diffraction order. It is determined whether there are any overlay error between the first structures and the second structures using a scatterometry technique based on the detected spectra by (i) for each target, determining a first differential intensity between the −1st diffraction order and a +1st diffraction order, (ii) for a plurality of pairs of targets each having a first target and a second target, determining a second differential intensity between the first differential intensity of the first target and the first differential intensity of the second target, and (iii) determining any overlay error between the first structures and the second structures using a scatterometry technique based on the second differential intensities determined from each target pair.
This application is a continuation of Ser. No. 11/963,730, entitled APPARATUS AND METHODS FOR DETECTING OVERLAY ERRORS USING SCATTEROMETRY, by Walter D. Mieher et al., filed Dec. 21, 2007, which is a divisional application of and claims priority of U.S. patent application Ser. No. 10/729,838, entitled APPARATUS AND METHODS FOR DETECTING OVERLAY ERRORS USING SCATTEROMETRY, by Walter D. Mieher et al., filed Dec. 5, 2003, now U.S. Pat. No. 7,317,531, issued Jan. 8, 2008, which claims priority from the following U.S. Provisional Patent Applications: (1) Application No. 60/431,314, entitled METHOD FOR DETERMINING OVERLAY ERROR BY COMPARISON BETWEEN SCATTEROMETRY SIGNALS FROM MULTIPLE OVERLAY MEASUREMENT TARGETS, by Walter D. Mieher et al., filed 5 Dec. 2002, (2) Application No. 60/440,970, entitled METHOD FOR DETERMINING OVERLAY ERROR BY COMPARISON BETWEEN SCATTEROMETRY SIGNALS FROM MULTIPLE OVERLAY MEASUREMENT TARGETS WITH SPECTROSCOPIC IMAGING OR SPECTROSCOPIC SCANNING, by Walter D. Mieher, filed 17 Jan. 2003, (3) Application No. 60/504,093, entitled APPARATUS AND METHODS FOR DETECTING OVERLAY ERRORS USING SCATTEROMETRY, by Walter D. Mieher, filed 19 Sep. 2003, (4) Application No. 60/449,496, entitled METHOD AND SYSTEM FOR DETERMINING OVERLAY ERRORS BASED ON SCATTEROMETRY SIGNALS ACQUIRED FROM MULTIPLE OVERLAY MEASUREMENT PATTERNS, by Walter D. Mieher, filed 22 Feb. 2003, and (5) Application No. 60/498,524, filed 27 Aug. 2003, entitled “METHOD AND APPARATUS COMBINING IMAGING AND SCATTEROMETRY FOR OVERLAY METROLOGY”, by Mike Adel. These applications are herein incorporated by reference in their entirety.
Xa=+F+f0 (for target A),
Xb=−F+f0 (for target B),
Xc=+F−f0 (for target C), and
Xd=−F−f0 (for target D).
FIG. 2( a) is a side view illustration of a patterned top layer L2 being offset by an amount F from a patterned bottom layer L1 in accordance with one embodiment of the present invention. Each layer L1 and L2 is patterned into a set of structures. A structure may include any suitable feature, such as a line, trench or a contact. A structure may be designed to be similar to a semiconductor device feature. A structure may also be formed from a combination of different features. Further, a structure may be located on any layer of the sample, e.g., either above the top layer of the sample, within any layer of the sample, or partially or completely within a layer of the sample. In the illustrated embodiment of FIG. 2( a), layer L1 includes the complete structures 204 a-c, while layer L2 includes the complete structures 202 a-c. Construction of scatterometry overlay targets structures and methods for producing them are described in U.S. patent application, having application Ser. No. 09/833,084, filed 10 Apr. 2001, entitled “PERIODIC PATTERNS AND TECHNIQUE TO CONTROL MISALIGNMENT”, by Abdulhalim, et al., US 2003/0002043 A1, which application is herein incorporated by reference in its entirety. In particular, properties which exhibited high sensitivity are intensity, phase and polarization properties of zero-order diffraction; differential intensity between the positive and negative first-order diffraction; differential phase between the positive and negative first-order diffraction; and differential polarization between the positive and negative first-order diffraction. These properties also yielded linear graphs when plotted against the overlay misalignment. This method can be used to determine misalignment on the order of nanometers.
Further embodiments of suitable measurement systems and their use for determining overlay error are further described below. In various embodiments of the present invention, the spectra SA, SB, SC, and SD (and any additional spectra that may be present) could include any type of spectroscopic ellipsometry or reflectometry signals, including: tan (Ψ), cos (Δ), Rs, Rp, R, α (spectroscopic ellipsometry “alpha” signal), β (spectroscopic ellipsometry “beta” signal), ((Rs−Rp)/(Rs+Rp)), etc.
E′=((S C −S D)*(Xa+Xb)/2+(S A −S B)*(Xc+Xd)/2)/(S A −S B)−(S C −S D))
In one embodiment, the primary offset F is optimized to provide larger or maximum sensitivity to overlay errors. For instance, an offset F equal to ¼ of the pitch of the target provides high overlay sensitivity since it is half-way in-between the two symmetry points where overlay error sensitivity is minimum. The secondary offset f0 may be chosen such that the f0 is outside the region of interest for overlay measurements, such as equal to or beyond the specification limits, but it should not cause the uncertainty of the overlay measurement to allow the error that an out-of-spec measurement can be interpreted as within specifications. Nevertheless, this is not a limitation on the range of f0. A large f0 may decrease the accuracy of the overlay measurements for overlay errors E between −f0 and +f0. For overlay errors E larger than |f0|, the accuracy of the overlay measurement may be reduced due to extrapolation beyond the region −f0 to +f0 and the accuracy of the linear approximation may also be reduced.
In accordance with one embodiment of the present invention, therefore, multiple scatterometry overlay measurements are performed with limited optical refocusing in order to increase the processing speed and throughput of the system. By limited optical refocusing, it is generally meant that at least some new measurements are performed without refocusing the optical system, i.e., multiple measurements are made with the same focus setting. For instance, the optical system may be initialized with a focus setting that is optimized for a plurality of scatterometric measurements that will be performed, and no further refocusing takes place during these individual scatterometric measurements. The optimized focus setting may be found once for the entire wafer, or it may be found periodically. When periodic, the focus setting may be established at preset increments of time during inspection (e.g., every 30 seconds), for a particular location on the wafer (e.g., every 2×2 cm2 of wafer), for a particular characteristic of the target (e.g., similar line widths and spacing) and the like.
In other combinational target arrangements, the imaging structures are laid out in the center of a symmetrically arranged set of scatterometry targets. FIG. 11 b is a top view representation of a second combination imaging and scatterometry target embodiment. As shown, scatterometry targets are symmetrically arranged around a central image type target 1152. In this example, the image type target 1152 is formed from quadrants of line segments, where each quadrant is either in the x or y direction. Suitable image type targets and techniques for determining overlay with same are described in the following U.S. patents and applications: (1) U.S. Pat. No. 6,462,818, issued 8 Oct. 2002, entitled “OVERLAY ALIGNMENT MARK DESIGN”, by Bareket, (2) U.S. Pat. No. 6,023,338, issued 8 Feb. 2000, entitled “OVERLAY ALIGNMENT MEASUREMENT OF WAFER”, by Bareket, (3) application Ser. No. 09/894,987, filed 27 Jun. 2001, entitled “OVERLAY MARKS, METHODS OF OVERLAY MARK DESIGN AND METHODS OF OVERLAY MEASUREMENTS”, by Ghinovker et al., and (4) U.S. Pat. No. 6,486,954, issued 26 Nov. 2002, entitled “OVERLAY ALIGNMENT MEASUREMENT MARK” by Levy et al. These patents and applications are all incorporated herein by reference in their entirety.
In one embodiment, the measurement instrument would project radiation (preferably light) through the mask and onto an area of the mask and wafer which contains one or more scatterometry overlay targets. The change in properties of the reflected light due to scattering or diffraction may then be used to determine the offset between the pattern on the mask and the pattern on the wafer. The wafer is then moved relative to the mask (or vice versa) to achieve the desired offset. A more accurate alignment may be achieved, rather than with conventional alignment techniques such as direct imaging or moiré techniques. The instrument could be a reflectometer, polarized reflectometer, spectrometer, imaging reflectometer, imaging interferometer, or other such instrument as described herein or in the above referenced provisional applications.
Scatterometry measurement targets consume a significant area of the wafer for both metrology of CD and overlay. This wafer area becomes very valuable as design rule shrinks. Currently, scatterometry overlay marks may consume >35×70 um space for each xy scatterometry overlay target group or mark on the wafer. These are used only for overlay measurements and therefore the manufacturers consider the loss of wafer space as undesirable. Therefore, it is desirable to reduce the total wafer area required for measurement targets or measurement features. Changes to optical system design to enable measurements on smaller targets may result in greater complexity of the optical system and potentially compromise measurement performance. In scatterometry overlay measurement as describe herein, the target area typically consists of four gratings for each axis (X and Y). Each of these gratings is typically larger than 15×15 um with a limited opportunity to shrink it further using conventional techniques. Each grating is composed of a first layer grating (e.g. STI) and a top layer grating (e.g. gate). Each of the two layers has a programmed offset, which is typically smaller than the pitch of the top grating. In many cases the top layer is photoresist. An overlay measurement is achieved by analyzing the spectra of a reflected light from each of these gratings.
In scatterometry critical dimension (CD) measurement, the target area typically consists of a single grating, which may be positioned along either axis (X or Y). In some cases, the target area may include multiple gratings for each axis (X and Y). Each of these gratings is typically about 50×50 um. The measurement is typically performed on a single process layer target with no pattern underneath. This measurement is typically done on a photoresist pattern following a resist development step in a lithographic patterning process or following an etch or CMP process in other modules of the fabrication. A CD measurement is achieved by analyzing the spectra of a reflected light from the grating(s) as described in the above referenced U.S. Pat. No. 6,590,656 by Xu, et al.
Scatterometry overlay may be combined with scatterometry profile or scatterometry critical dimension systems, or other semiconductor metrology or inspections systems. Scatterometry overlay may be integrated with a semiconductor process tool, for example a lithography resist process tool (also known as a resist track). Integration of metrology systems with process systems and combinations of metrology systems are described in (1) U.S. patent application, having patent Ser. No. 09/849,622, filed 4 May 2001, entitled “METHOD AND SYSTEMS FOR LITHOGRAPHY PROCESS CONTROL”, by Lakkapragada, Suresh, et al. and (2) U.S. patent, having U.S. Pat. No. 6,633,831, issued 14 Oct. 2003, entitled “METHODS AND SYSTEMS FOR DETERMINING CRITICAL DIMENSION AND A THIN FILM CHARACTERISTIC OF A SPECIMAN”, by Nikoonahad et al, which applications are incorporated herein by reference in their entirety.
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Fattakhov, (2000) "Formation of Periodic Diffraction Structures at Semiconductor Surfaces for Studying the Dynamics of Photoinduced Phase Transitions", 0030-400X/00/8901-0136.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8250497 *Dec 29, 2009Aug 21, 2012Industrial Technology Research InstituteMethod for designing two-dimensional array overlay target sets and method and system for measuring overlay errors using the sameUS9395633Jun 14, 2013Jul 19, 2016Asml Netherlands B.V.Lithographic cluster system, method for calibrating a positioning device of a lithographic apparatusUS20110154272 *Dec 29, 2009Jun 23, 2011Industrial Technology Research InstituteMethod for designing two-dimensional array overlay target sets and method and system for measuring overlay errors using the sameUS20150177166 *Jun 18, 2013Jun 25, 2015Asml Netherlands B.V.Inspection Method and Apparatus, Lithographic System and Device Manufacturing Method* Cited by examinerClassifications U.S. Classification356/401International ClassificationG03F7/20, G01B11/00, G03F9/00Cooperative ClassificationG03F9/7088, G03F9/7084, G03F9/7049, G03F7/70683, G03F7/70633, G03F7/70625, G01N21/956, G01N2021/213European ClassificationG03F7/70L10D, G03F9/70D, G03F9/70M, G03F9/70K6, G01N21/956, G03F7/70L10B, G03F7/70L10PLegal EventsDateCodeEventDescriptionOct 27, 2014FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services