Source: http://patents.com/us-9761724.html
Timestamp: 2018-02-18 20:28:27
Document Index: 175455149

Matched Legal Cases: ['Application No. 95122087', 'Application No. 95122087', 'Application No. 200680021817', 'Application No. 200680021817', 'Application No. 112006001589', 'Application No. 112006001589', 'Application No. 112006001589']

US Patent # 9,761,724. Semiconductor device structures and methods of forming semiconductor structures - Patents.com
United States Patent 9,761,724
Brask , et al. September 12, 2017
Brask; Justin K. (Portland, OR), Kavalieros; Jack (Portland, OR), Doyle; Brian S. (Portland, OR), Shah; Uday (Portland, OR), Datta; Suman (Beaverton, OR), Majumdar; Amlan (Portland, OR), Chau; Robert S. (Beaverton, OR)
Family ID: 1000002828254
15/182,343
US 20160293765 A1 Oct 6, 2016
14576111 Dec 18, 2014 9385180
14048923 Jan 13, 2015 8933458
13277897 Nov 12, 2013 8581258
12463309 Dec 6, 2011 8071983
11158661 Jun 16, 2009 7547637
Current CPC Class: H01L 29/7853 (20130101); H01L 21/3085 (20130101); H01L 21/30608 (20130101); H01L 21/30617 (20130101); H01L 21/84 (20130101); H01L 29/04 (20130101); H01L 29/045 (20130101); H01L 29/0657 (20130101); H01L 29/51 (20130101); H01L 29/66795 (20130101); H01L 29/78681 (20130101); H01L 29/78684 (20130101)
Current International Class: H01L 21/02 (20060101); H01L 21/308 (20060101); H01L 29/06 (20060101); H01L 29/51 (20060101); H01L 29/78 (20060101); H01L 21/306 (20060101); H01L 21/84 (20060101); H01L 29/04 (20060101); H01L 29/66 (20060101); H01L 29/786 (20060101)
Field of Search: ;257/410
5266518 November 1993 Binsma et al.
5693542 December 1997 Suh et al.
5814544 September 1998 Huang
6010921 January 2000 Soutome
6093947 July 2000 Hanafi et al.
6124177 September 2000 Lin
6346450 February 2002 Deleonibus et al.
6495403 December 2002 Skotnicki
6705571 March 2004 Yu et al.
6949433 September 2005 Ke et al.
7041601 May 2006 Yu et al.
7105891 September 2006 Visokay et al.
7615429 November 2009 Kim et al.
9385180 July 2016 Brask
2004/0075141 April 2004 Shigenobu et al.
2004/0132236 July 2004 Doris
2005/0003612 January 2005 Hackler et al.
2005/0023535 February 2005 Sriram
2006/0001095 January 2006 Doris et al.
2006/0057792 March 2006 Mathew et al.
2006/0091432 May 2006 Guha et al.
2006/0113605 June 2006 Currie
2007/0148937 June 2007 Yagishita et al.
2008/0102586 May 2008 Park
10203998 Aug 2003 DE
2156149 Oct 1985 GB
2303048 Dec 1990 JP
200414538 Aug 1992 TW
200518310 Nov 1992 TW
International Search Report & Written Opinion from PCT/US2006/024516 dated Jan. 10, 2007, 18 pgs. cited by applicant .
International Preliminary Report on Patentability from Application No. PCT/US2006/024516 dated Jan. 10, 2008, 11 pgs. cited by applicant .
Final Office Action from U.S. Appl. No. 11/158,661 dated Jan. 15, 2008, 25 pgs. cited by applicant .
Office Action from Taiwan Patent Application No. 95122087 dated Dec. 16, 2008, 14 pgs. cited by applicant .
Office Action from Taiwan Patent Application No. 95122087 dated Jun. 20, 2008, 8 pgs. cited by applicant .
Second Office Action for Chinese Application No. 200680021817.0 dated Dec. 11, 2009, 11 pgs. cited by applicant .
Office Action for Chinese Patent Application No. 200680021817.0 dated Jun. 12, 2009, 11 pages. cited by applicant .
Office Action for Application No. 112006001589.3 dated Dec. 20, 2011, 9 pages. cited by applicant .
Non-Final Office Action for U.S. Appl. No. 11/158,661 dated Jun. 4, 2007, 26 pgs. cited by applicant .
Non-Final Office Action for U.S. Appl. No. 11/158,661 dated Sep. 17, 2007, 42 pgs. cited by applicant .
Non-Final Office Action for U.S. Appl. No. 11/158,661 dated Jun. 30, 2008, 24 pgs. cited by applicant .
Final Office Action for U.S. Appl. No. 11/158,661 dated Nov. 25, 2008, 7 pgs. cited by applicant .
Non-Final Office Action for U.S. Appl. No. 12/463,309 dated Feb. 2, 2011, 31 pgs. cited by applicant .
Non-Final Office Action for U.S. Appl. No. 13/277,897 dated Mar. 6, 2013, 19 pgs. cited by applicant .
Final Office Action for U.S. Appl. No. 14/048,923 dated May 29, 2014, 6 pgs. cited by applicant .
Non-Final Office Action for U.S. Appl. No. 14/048,923 dated Nov. 8, 2013, 23 pgs. cited by applicant .
Non-Final Office Action for U.S. Appl. No. 14/048,923 dated Feb. 20, 2014, 6 pgs. cited by applicant .
Non-Final Office Action for U.S. Appl. No. 14/576,111 dated Nov. 10, 2015, 23 pgs. cited by applicant .
Chang, L. , et al., CMOS Circuit Performance Enhancement by Surface Orientation Optimization, IEEE Transactions on Electron Devices, vol. 51, No. 10, Oct. 2004, 7 pgs. cited by applicant .
Park, Jae-Hyoun , et al., Quantum-Wired MOSFET Photodetector Fabricated by Conventional Photolighography on SOI Substrate, Nanotechnology, 4th IEEE Conference on Munich, Germany, Aug. 16-19, 2004, Piscataway, NJ, 3 pgs. cited by applicant .
Tokoro, Kenji, et al., Anisotropic Etching Properties of Silicon in KOH and TMAH Solutions, International Symposium on Micromechatronics and Human Science, IEEE, 1998, 6 pgs. cited by applicant .
Wolf, Stanley, et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, Sep. 1986, 3 pgs. cited by applicant .
Non-Final Office Action for German Patent Application No. 112006001589.3 dated Mar. 31, 2009, 3 pgs. cited by applicant .
Non-Final Office Action for German Patent Application No. 112006001589.3 dated Aug. 8, 2011, 5 pgs. cited by applicant.
1. A nonplanar transistor, comprising: a semiconductor body disposed on and continuous with a bulk monocrystalline silicon substrate, without an intervening insulating layer disposed between the semiconductor body and the bulk monocrystalline silicon substrate, wherein the semiconductor body comprises inwardly tapered sidewalls between two ends of the semiconductor body; and a gate electrode disposed over the semiconductor body and between the two ends of the semiconductor body.
9. A nonplanar transistor, comprising: a semiconductor body disposed on and continuous with a semiconductor substrate, without an intervening insulating layer disposed between the semiconductor body and the semiconductor substrate, wherein the semiconductor body comprises inwardly tapered sidewalls between two ends of the semiconductor body; and a gate electrode disposed over the semiconductor body and between the two ends of the semiconductor body.
A method of forming a three-dimensional semiconductor structure utilizing a self limiting etch and natural faceting is illustrated in FIGS. 2A-2F in accordance with embodiments of the present invention. The fabrication of a semiconductor structure begins with a substrate 200. In an embodiment of the present invention, substrate 200 is a silicon on insulator (SOI) substrate. A SOI substrate 200 includes a lower monocrystalline silicon substrate 202. An insulating layer 204, such as silicon dioxide or silicon nitride, is formed on monocrystalline substrate 202. A single crystalline silicon film 206 is formed on the top of the insulating layer 204 insulating layer 204 is sometimes referred to as a "buried oxide" or a "buried insulating" layer and is formed to a thickness sufficient to isolate single crystalline silicon film 206 from lower monocrystalline silicon substrate 202. In an embodiment of the present invention, the insulating layer is a buried oxide layer formed to a thickness between 200-2000 .ANG.. In an embodiment of the present invention, the silicon, film 206 is an intrinsic (i.e. undoped) silicon epitaxial film. In other embodiments, the single crystalline silicon film 206 is doped to a p type or n type conductivity with a concentration level between 1.times.10.sup.16-1.times.10.sup.19 atom/cm.sup.3. Silicon film 206 can be in situ doped (i.e., doped while it is deposited) or doped after it is formed on insulating layer 204 by, for example, ion implantation. Doping silicon film 206 after it is deposited enables both n type devices and p type devices to be fabricated on the same substrate in an embodiment of the present invention, silicon film 206 is formed to a thickness which is approximately equal to the height desired of the subsequently formed n structure. In an embodiment of the present invention, the single crystalline silicon film 206 has a thickness of less than 30 nanometers and ideally around 20 nanometers or less.
A silicon on insulator (SOI) substrate 200 can be formed in a well known method. In one method of forming the silicon insulator substrate, known as the SIMOX technique, oxygen atoms are implanted at a high dose into a single crystalline silicon substrate and then annealed to form buried oxide 204 within the substrate. The portion of the single crystalline silicon substrate above the buried oxide becomes the silicon film 206. Another technique currently used to form SOI substrates is an epitaxial silicon film transfer technique which is generally referred to as "bonded SOI". In this technique, a first silicon wafer has a thin oxide grown on its surface that will later serve as the buried oxide 204 in the SOL structure. Next, a high dose hydrogen implant is made into the first silicon wafer to form a stress region below the silicon surface of the first wafer. The first wafer is then flipped over and bonded to the surface of a second silicon wafer. The first wafer is then cleaved along the high stress plane created by the hydrogen implant. The cleaving results in a SOI structure with a thin silicon layer on top, the buried oxide underneath, all on top of the second single crystalline silicon wafer. Well known smoothing techniques, such as HCl smoothing or chemical mechanical polishing (CMP) can be used to smooth the top surface of the silicon film 206 to its desired thickness.
Although the present invention will be described with respect to silicon structures formed on silicon on insulator (SOI) substrates, the present invention can be carried out on standard monocrystalline silicon wafers or substrates to form a "bulk" device. The silicon structures can be formed directly from the monocrystalline silicon wafer or formed from epitaxial silicon films formed on a monocrystalline silicon substrate. Additionally, although embodiments of the present invention are illustrated with respect to the formation of single crystalline silicon structures and devices formed therefrom, the methods and structures of the present invention are equally applicable to other types of semiconductors, such as but not limited to germanium (Ge), a silicon germanium alloy (Si.sub.xGe.sub.y), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), and gallium antimonide (GaSb). Accordingly, embodiments of the present invention include semiconductor structures and methods of forming semiconductor structures utilizing semiconductors, such as but not limited to germanium (Ge), a silicon germanium alloy (Si.sub.xGe.sub.y), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), and gallium antimonide (GaSb).
Next, as shown in FIG. 2C, hard mask material 208 is etched in alignment with photoresist mask 210 to form a hard mask 212 as shown in FIG. 2C. Photoresist mask 210 prevents the underlying portion of hard mask material 208 from being etched. In an embodiment of the present invention, the hard mask material 208 is etched with an etchant which can etch the hard mask material but does not etch the underlying silicon film 206. In an embodiment of the present invention, the hard mask material is etched with an etchant that has almost perfect selectivity to the underlying silicon film 206. That is, in an embodiment of the present invention, the hard mask etchant etches the hard mask material 208 at least 20 times faster than the underlying silicon film 206 (i.e., etchant has a hard mask to silicon film selectivity of at least 20:1). When hard mask material 208 is a silicon nitride or silicon oxynitride film, hard mask material 208 can be etched into a hard mask 212 utilizing a dry etch process, such as a reactive ion etching. In an embodiment of the present invention, a silicon nitride or silicon oxynitride hard mask is reactively ion etched utilizing a chemistry comprising CHF.sub.3 and O.sub.2 and Ar.
Next, as also shown in FIG. 2C, after hard mask film 208 has been patterned into a hard mask 212, photoresist mask 210 may be removed by well known techniques. For example, photoresist mask 210 may be removed utilizing "piranha" clean solution which includes sulfuric acid and hydrogen peroxide. Additionally, residue from the photoresist mask 210 may be removed with an O.sub.2 ashing.
Next, as shown in FIG. 2D, silicon film 206 is etched in alignment with hard mask 212 to form a patterned silicon film 214 which has a first pair of laterally opposite sidewalls 218 aligned with the <110> crystal plane and a second pair of laterally opposite sidewalls 220 aligned with the <110> crystal plane. Hard mask 212 prevents the underlying portion of silicon film 206 from being etched during the etch process, in an embodiment of the present invention, the etch is continued until the underlying buried oxide layer 204 is reached. Silicon film 206 is etched with an etchant which etches silicon film 206 without significantly etching hard mask 212. In an embodiment of the present invention, silicon film 206 is etched with an etchant which enables silicon film 206 to be etched at least 5 times and ideally 10 times faster than hard mask 212 etchant has a silicon film 206 to hard mask 212 etch selectivity of at least 5:1 and ideally at least 10:1). Silicon film 206 can be etched utilizing any suitable process. In an embodiment of the present invention, silicon film 206 is anisotropically etched so that the silicon body 214 has nearly vertical sidewalls 218 formed in alignment with the sidewalls of hard mask 212. When hard mask. 212 is a silicon nitride or silicon oxynitride film, silicon film 206 can be etched utilizing a dry etch process, such as a reactive ion etch (RIE) or plasma etch with a chemistry comprising Cl.sub.2 and HBr.
Accordingly, in an embodiment of the present invention, the silicon structure 214 is exposed to a wet etch or a "faceting" etch while hard mask 212 is present on structure 214 in order to remove the edge roughness and/or to tailor the shape of the structure to enhance device performance. In an embodiment of the present invention, the hard mask 212 capped silicon structure 214, is exposed to an anisotropic wet etch. The wet etchant has sufficient chemical strength to overcome the activation energy barrier of the chemical etching reaction in order to etch less dense planes of the semiconductor structure, but insufficient chemical strength to overcome the activation energy barrier of the chemical etching reaction, thereby not etching high density planes.
In an embodiment of the present invention, a wet etch chemistry and process are used which can etch the less dense <100> and <110> planes, but which cannot etch the higher density <111> planes. Because hard mask 212 covers, the less dense <100> plane on the top surface of the silicon structure 214, said less dense plane is protected from etching. Because the less dense plane <100> on the top surface is shielded and because the etch does not have a sufficient chemical strength to etch the <111> plane, the wet, etch stops on, the first total intact or contiguous <111> plane as shown in FIG. 2E. In this way, the "faceting" or wet etch is self limiting. Thus, upon self-limitation of the yet etch, only <111> planes and etch-resistant films used, to shield the less dense <110> and <100> planes remain exposed. The faceting etch of the present invention can be said to be an anisotropic etch because it etches in one direction at one rate while etching in other directions at a second slower rate or not at all. Because the etch process etches the <100> and <110> planes but not the <111> planes, the faceting or wet etch forms a silicon structure 230 having sidewalls 232 defined by the <111> plane as shown in FIG. 2E. The anisotropic wet etch removes the surface roughness 222 from sidewalls 218 (FIG. 2D) and generates optically smooth sidewalls 232 as shown in FIG. 2E. Additionally, after exposing the structure 214 to the faceting etch for a sufficient period of time, sidewalls 218 are defined by the <111> plane and generate a structure 230 with a v-shape or inwardly tapered sidewalls 232. The sidewalls 232 angle inward from the top surface 219 of structure 230 at an angle alfa of 62.5 degrees. In an embodiment of the present invention, the top surface 219 of structure 230 has a width (W1) between laterally opposite sidewalk 232 of between 20-30 nm and the bottom surface has a width (W2) between laterally opposite sidewalk of between 10-15 nm.
In an embodiment of the present invention, the wet etch or "faceting" etch is a hydroxide based etch with a sufficiently low hydroxide concentration and nucleophillicity (i.e. chemical strength) so that there is no etching of the fully intact <111> planes. In an embodiment of the present invention, structure 214 is exposed to a faceting or wet etch which comprises less than 1% ammonia hydroxide (NH.sub.4OH) by volume. In an embodiment of the present invention, structure 214 is exposed to a wet etchant comprising between 0.2-1% NH.sub.4OH by volume at a temperature range between 5-25.degree. C. In an embodiment of the present invention, sonic energy at the frequency range between 600-800 kilohertz dissipating between 0.5-3 watts/cm.sup.2 is applied to the etch solution during the faceting etch. In an embodiment of the present invention, the hard mask capped silicon structure is exposed to the beefing etch for between 15 seconds-5 minutes.
In another embodiment of the present invention, the faceting or wet etch can comprise ultra-dilute (<0.1% by volume) aqueous solutions of tetraalkylammonium hydroxides (e.g. tetraethylammonium hydroxide and tetramethylammonium hydroxide at a temperature between 5 and 20.degree. C.).
In an embodiment of the present invention, silicon structure 230 provides a silicon body or fin for a tri-gate transistor 240 illustrated in FIG. 2F. In order to fabricate a tri-gate transistor 240 as illustrated in FIG. 2F, hard mask 212 is removed from silicon structure 230. In an embodiment of the present invention, when hard mask 212 is a silicon nitride of silicon oxynitride film, a wet etch comprising phosphoric acid in de-ionized water may be used to remove the hard mask. In an embodiment of the present invention, the hard mask etchant comprises an aqueous solution of between 50-90% phosphoric acid (by volume) heated to a temperature between 150-170.degree. C. and ideally to 160.degree. C. In an embodiment of the present invention, after removing hard mask 212, the substrate can be cleaned utilizing standard SC1 and SC2 cleans. It is desirable to clean the substrate after removal of the hard mask with phosphoric acid because phosphoric acid typically includes many metallic impurities which can affect device performance or reliability. It is to be appreciated that if one desires to form a FINFET or a dual gate device, the hard mask 212 may be left on silicon structure 230 in order to isolate the top surface of the semiconductor structure 230 from control by a subsequently formed gate electrode.
Next, a gate electrode 260 is formed on gate dielectric layer 250 on the to surface and sidewalk of semiconductor structure 230 as illustrated in FIG. 2F. Gate electrode 260 is formed perpendicular to sidewalls 232. The gate electrode can be formed from any well known gate electrode material, such as but not limited to doped polycrystalline silicon, as well as metal films, such as but not limited to tungsten, tantalum, titanium, and their nitrides. Additionally, it is to be appreciated that a gate electrode need not necessarily be a single material and can be a composite stack of thin films, such as but not limited to a lower metal film formed on the gate dielectric layer with a to polycrystalline silicon film. The gate dielectric layer and gate electrode may be formed by blanket depositing or growing the gate dielectric layer over the semiconductor body and then blanket depositing a gate electrode material over the gate dielectric layer. The gate dielectric layer and gate electrode material may then be patterned with well know photolithography and etching techniques to form gate electrode 260 and gate dielectric layer 250 as illustrated in FIG. 2F. Alternatively, the gate dielectric layer and gate electrode may be formed utilizing a well known replacement gate process. A source region 272 and a drain region 274 are formed in silicon body 230 on opposite sides of gate electrode 260 as illustrated in FIG. 2F. Any well known and suitable technique, such as solid source diffusion or ion implantation may be used to form source and drain regions. In an embodiment of the present invention, the source region 272 and drain region 274 are formed to a concentration between 1.times.10.sup.19-1.times.10.sup.21 atoms/cm.sup.3.
The fabricated nonplanar transistor 240 includes a semiconductor body 230 surrounded by gate dielectric layer 250 and gate electrode 260 as shown in FIG. 2F. The portion of the semiconductor body 230 located beneath the gate dielectric and gate electrode is the channel region of the device. In an embodiment of the present invention the source and drain region are doped to a first conductivity type (p type or p type) while the channel region is doped to a second opposite conductivity type (p type or n type) or is left undoped. When a conductive channel is formed by gate electrode 260 in the channel region of silicon body 230, charges (i.e., holes or electrons) flow between the source and drain region along the <110> plane in silicon body 230. That is, in transistor 240, charge migration is along the <110> crystal plane in structure 240, is has been found that charge migration in the <110> direction provides good hole mobility. Accordingly, in an embodiment of the present invention, device 240 is a p type device where the source and drain regions are formed to a p type conductivity and where the carriers are holes. Additionally, by inwardly tapering the sidewalls of silicon body 230, gate electrode 260 has good control over the channel region of body 230 enabling fast turn "on" and turn "off" of transistor 240.
FIGS. 3A-310 illustrate a method of forming a monocrystalline silicon body or structure in accordance with another embodiment of the present invention. As shown in FIG. 3A, a hard mask 312 is formed on a single crystalline silicon film 306 having a (100) global crystal orientation. Hard mask 312 can be formed as described above. In FIG. 3A, however, the hard mask 312 is orientated on silicon film 306 to produce a pair of sidewalls which are aligned with the <100> plane and a second pair of sidewalls which are also aligned to the <100> plane. (It is to be appreciated that the orientation of hard mask 312 is rotated approximately 45.degree. in the xy plane from the orientation of hard mask 212 in FIG. 2A.)
Next, the silicon structure 314 is exposed to a faceting wet etch while hard mask 312 is present on the top surface 319 of silicon structure 314. The faceting wet etch has a sufficient chemical strength to etch the less dense <110> and <100> planes but insufficient strength to etch the high density <111> plane. Because the less dense <100> plane on the top surface 319 of the silicon structure 314 is covered by the hard mask 312 and because the etch does not have sufficient chemical strength to etch the <111> plane, the silicon structure 314 is transformed into a silicon structure 330 having a pair of sidewalls 332 having a "V" notched shape formed by intersecting <111> planes as illustrated in FIG. 3C. As before, the faceting etch is self limiting, and stops at the first contiguous <111> planes. The <111> planes of sidewalls 332 meet at an angle .beta. of approximate 55.degree.. A combination of crystal orientation, atom shielding, and a well-controlled anisotropic wet etch enables the formation of silicon structure 330 with "V" notch sidewalls 332.
As discussed above, structure 430 can be used to create a variety of well known semiconductor devices, such as silicon nonplanar or three-dimensional devices, as well as opto-electronic devices and MEMS devices. In an embodiment of the present invention, the silicon structure 430 is used to form a silicon body of nonplanar transistor, such as a tri-gate transistor 440, as illustrated in FIG. 4D. The tri-gate transistor 440 has a gate dielectric layer 450 and a gate electrode 460 formed over and around a portion of silicon body 430 as illustrated in FIG. 4D. The gate electrode 460 runs in a direction perpendicular to sidewalls 432 as shown in FIG. 4D. The gate dielectric layer 450 and gate electrode 460 may be formed of any suitable material and suitable known method, such as described above. A source region 472 and a drain 474 are formed in silicon body 430 on opposite sides of gate electrode 460 as illustrated in FIG. 4D. The charge migration from the source region 472 to the drain region 474 in silicon body 430 is parallel to or in alignment with the <110> plane. The inwardly tapered sidewalls 432 of silicon body 430 provide good gate control 460 of the channel region of the device which enables the fast turn "on" and turn "off" of device 440.
Although the present invention thus far has been described with respect to the shaping or "faceting" of single crystalline silicon structures utilizing a combination of crystal orientation, hard mask shielding, and well controlled wet etchants, concepts of the present invention are equally applicable to other types of single crystalline semiconductor films, such as but not limited to germanium (Ge), a silicon germanium alloy (Si.sub.xGe.sub.y), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), and gallium antimonide (GaSb). For example, a single crystalline indium antimonide (InSb) structure can be faceted utilizing, a wet etchant comprising an aqueous solution of 0.05-0.1 mol/L citric acid at a temperature range between 5-15.degree. C. Similarly, a single crystalline gallium arsenide (GaAs) structure can be faceted by exposing a hard mask covered gallium arsenide structure to a wet etchant comprising an aqueous solution of less than 0.05 mol/L citric acid at a temperature range between 5-15.degree. C.
Additionally, in an embodiment of the present invention, an integrated circuit is formed from a p type transistor and an n type transistor 520 which are orientated and/or shaped to optimize the performance of each type of transistor. For example, as illustrated in FIG. 5, in an embodiment of the present invention a single crystalline silicon film having a (100) global crystal orientation is patterned as described with respect to FIGS. 2A-2F to form a silicon body 512 for a p type nonplanar transistor 510 wherein the charge (hole) migration is parallel with a <110> plane and is also patterned as described with respect to FIGS. 3A-3D to form a silicon body 522 for a n type nonplanar transistor 520 wherein charge (electron) migration is parallel with a <100> plane. Accordingly, in an embodiment of the present invention, a p type nonplanar transistor and an a type nonplanar transistor are orientated in a non-parallel (e.g., 45.degree. C. offset) manner with respect to one another on a substrate in order to optimize the hole mobility for the p type transistor and the electron mobility for the n type transistor. In other embodiments of the present invention, the semiconductor bodies of the p type device and the a type device are oriented with respect to one another to enable the faceting etch to shape the bodies into structures which optimize performance tier each device type. In this way, the performance of an integrated circuit which includes both an a type nonplanar transistor and a p type nonplanar transistor can be greatly improved.
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