Source: https://patents.google.com/patent/US8400836B2/en
Timestamp: 2019-10-20 02:11:37
Document Index: 459533743

Matched Legal Cases: ['Application No. 200780044147', 'Application No. 2009', 'Application No. 2009', 'Application No. 10', 'Application No. 10', 'Application No. 096144333', 'Application No. 096144333']

US8400836B2 - Segmented bitscan for verification of programming - Google Patents
US8400836B2
US8400836B2 US13/035,539 US201113035539A US8400836B2 US 8400836 B2 US8400836 B2 US 8400836B2 US 201113035539 A US201113035539 A US 201113035539A US 8400836 B2 US8400836 B2 US 8400836B2
US13/035,539
US20110141819A1 (en
2009-04-28 Priority to US12/431,573 priority patent/US7724580B2/en
2010-04-07 Priority to US12/755,610 priority patent/US7924625B2/en
2011-02-25 Application filed by SanDisk Technologies LLC filed Critical SanDisk Technologies LLC
2011-02-25 Priority to US13/035,539 priority patent/US8400836B2/en
2011-02-28 Assigned to SANDISK CORPORATION reassignment SANDISK CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LI, YAN, LUTZE, JEFFREY W., KAMEI, TERUHIKO
2011-06-16 Publication of US20110141819A1 publication Critical patent/US20110141819A1/en
2013-03-19 Publication of US8400836B2 publication Critical patent/US8400836B2/en
This application is a divisional application of U.S. patent application Ser. No. 12/755,610, “SEGMENTED BITSCAN FOR VERIFICATION OF PROGRAMMING,” filed on Apr. 7, 2010, by Yan Li, et al., which is a divisional application of U.S. patent application Ser. No. 12/431,573, “SEGMENTED BITSCAN FOR VERIFICATION OF PROGRAMMING,” filed on Apr. 28, 2009, by Yan Li, et al., issued as U.S. Pat. No. 7,724,580, which is a divisional application of U.S. patent application Ser. No. 11/563,585, “SEGMENTED BITSCAN FOR VERIFICATION OF PROGRAMMING,” filed on Nov. 27, 2006, by Yan Li, et al., issued as U.S. Pat. No. 7,545,681, all of which are incorporated herein by reference.
One example of a memory system suitable for implementing the present invention uses the NAND flash memory structure. However, other types of non-volatile storage devices can also be used. For example, a so called TANOS structure (consisting of a stacked layer of TaN—Al2O3—SiN—SiO2 on a silicon substrate), which is basically a memory cell using trapping of charge in a nitride layer (instead of a floating gate), can also be used with the present invention. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. Such a cell is described in an article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. See also Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, Apr. 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor. The foregoing two articles are incorporated herein by reference in their entirety. The programming techniques mentioned in section 1.2 of “Nonvolatile Semiconductor Memory Technology,” edited by William D. Brown and Joe E. Brewer, IEEE Press, 1998, incorporated herein by reference, are also described in that section to be applicable to dielectric charge-trapping devices. Other types of memory devices can also be used.
It is anticipated that some implementations will include multiple processors 492. In one embodiment, each processor 492 will include an output line (not depicted in FIG. 4) such that each of the output lines is wired-OR′ d together. In some embodiments, the output lines are inverted prior to being connected to the wired-OR line. This configuration enables a quick determination during the program verification process of when the programming process has completed because the state machine receiving the wired-OR line can determine when all bits being programmed have reached the desired level. For example, when each bit has reached its desired level, a logic zero for that bit will be sent to the wired-OR line (or a data one is inverted). When all bits output a data 0 (or a data one inverted), then the state machine knows to terminate the programming process. In embodiments where each processor communicates with eight sense modules, the state machine may (in come embodiments) need to read the wired-OR line eight times, or logic is added to processor 492 to accumulate the results of the associated bit lines such that the state machine need only read the wired-OR line one time.
As one example, a NAND flash EEPROM is depicted in FIG. 5A that is partitioned into 1,024 blocks. In each block, in this example, there are 69,623 columns corresponding to bit lines BL0, BL1, . . . BL69, 623. In one embodiment, all the bit lines of a block can be simultaneously selected during read and program operations. Memory cells along a common word line and connected to any bit line can be programmed at the same time.
FIG. 7 illustrates an example of a two-pass technique of programming a multi-state memory cell that stores data for two different pages: a lower page and an upper page. Four states are depicted: state E (11), state A (10), state B (0) and state C (01). For state E, both pages store a “1.” For state A, the lower page stores a “0” and the upper page stores a “1.” For state B, both pages store “0.” For state C, the lower page stores “1” and the upper page stores “0.” Note that although specific bit patterns have been assigned to each of the states, different bit patterns may also be assigned.
In some embodiments, the verification process includes testing whether the threshold voltages of the memory cells have reached the various target levels for each of the states. For example with respect to FIG. 6, there will be three verification operations: (1) for Vva, (2) for Vvb and (3)Vvc. For three bits of data, there can be up to seven verification operations.
Address selection logic 848 is connected to transistors 850, 854, 858, 862, 866, 870, 874 and 878. If the state machine is testing the data associated with the group of eight processors (492 a, 492 b, 492 c, 492 d, 492 e, 492 f, 492 g, 492 h) depicted in FIG. 17, then address selection logic 848 will turn on transistors 850, 854, 858, 862, 866, 870, 874 and 878. Address selection logic includes a circuit (e.g., combinational logic or other circuits) that receive the address bus ADDR and outputs a signal if the correct address is on the address bus ADDR. In one embodiment, the address bus ADDR includes a set of address lines (e.g., ADDR[0:12]) and a set of compliment address lines (ADDR′[0:12]). The compliment address lines (ADDR′[0:12]) can be separately asserted so that they need not always be the inverse of ADDR[0:12]. Address selection logic 848 can connect to the appropriate lines of ADDR[0:12] and the appropriate lines of ADDR′ [0:12], and send that data to a set of AND gates (or other logic or other circuit elements) that will recognize when the group of eight processors (492 a, 492 b, 492 c, 492 d, 492 e, 492 f, 492 g, 492 h) are selected. With this scheme, one group of eight processors can be selected or multiple groups of eight processors can be selected.
receiving input data to be programmed into a unit of storage, the unit of storage is associated with at least a plurality of overlapping groups of flash memory cells;
applying a programming pulse, at a first magnitude, to control gates of the flash memory cells;
applying a verify control gate voltage to the control gates;
sensing threshold voltages for the flash memory cells;
determining whether each of the flash memory cells have reached respective target threshold voltage levels; and
for each of the overlapping groups, determining a number of flash memory cells in that group which have not reached respective target threshold voltage levels and comparing the determined number to a limit.
the determining the number of flash memory cells in that group which have not reached respective target threshold voltage levels includes adding a number of redundant flash memory cells that have not reached target threshold voltage levels to a number of original data flash memory cells in that group which have not reached respective target threshold voltage levels to create a sum that is compared to the limit.
3. A method according to claim 1, wherein the determining the number of flash memory cells in that group which have not reached respective target threshold voltage levels comprises:
(a) performing a binary search on that group to find a first non-volatile storage element that has not reached its respective target threshold voltage level;
(b) updating a count of non-volatile storage elements that have not reached respective target threshold voltage levels;
(c) tagging the first non-volatile storage element so that it will not be counted again; and
(d) repeating steps (a), (b) and (c) to determine how many non-volatile storage elements for that group have not reached respective threshold voltage target levels.
the flash memory cells store data in sectors; and
each group is bigger than a sector, spans at least portions of two sectors and includes at least one whole sector.
the flash memory cells store multiple bits of data per flash memory cell;
each bit of data on a respective flash memory cell is in a different page;
the overlapping groups of flash memory cells include a first group of flash memory cells, a second group of flash memory cells and a third group of flash memory cells;
the second group of flash memory cells includes a first set of flash memory cells in the first group and a second set of flash memory cells in the second group; and
determining the number of flash memory cells in the second group includes counting a number of flash memory cells in the second set that have not reached respective target threshold voltage levels and adding that number of flash memory cells in the second set that have not reached respective target threshold voltage levels to a number of flash memory cells in the first set that have not reached respective target threshold voltage levels that was previously counted when operating on the first group of flash memory cells.
all of the flash memory cells in the second group are either in the first set or the second set.
half of the flash memory cells in the second group are in the first set; and
half of the flash memory cells in the second group are in the second set.
the comparing the determined number to a limit includes using a first limit for the first group, a second limit for the second group and a third limit for the third group.
the comparing the determined number to a limit includes using a first limit for the first group, the second group and the third group.
applying one or more additional program pulses to control gates of the flash memory cells if at least one of the overlapping groups has an amount of flash memory cells that have not reached respective target threshold voltage levels being greater than the limit.
applying one or more additional program pulses to control gates of the flash memory cells if at least one of the overlapping groups has an amount of flash memory cells that have not reached respective target threshold voltage levels being greater than the limit and stopping programming in response to less than a predetermined number of groups having an amount of flash memory cells that have not reached respective target threshold voltage levels being greater than the limit.
if at least one of the overlapping groups has an amount of flash memory cells that have not reached respective target threshold voltage levels being greater than the limit, then
applying another programming pulse, at a magnitude higher than the first magnitude, to control gates of the flash memory cells,
applying a verify control gate voltage to the control gates,
sensing threshold voltages for the flash memory cells, and
determining whether each of the flash memory cells have reached respective target threshold voltage levels.
subsequent to the receiving the input data and prior to the applying of the program pulse at the first magnitude, performing multiple iterations of applying a program pulse and applying a verify control gate voltage until a predetermined iteration, the determining the number of flash memory cells in a group which have not reached respective target threshold voltage levels and comparing the determined number to the limit is performed after the predetermined iteration.
(a) receiving input data to be programmed into a unit of storage, the unit of storage is associated with at least a plurality of overlapping groups of non-volatile memory cells;
(b) applying a programming pulse to control gates of the non-volatile memory cells;
(c) applying one or more verify control gate voltages to the control gates and determining whether each of the non-volatile memory cells have reached respective target threshold voltage levels; and
(d) for each of the overlapping groups, determining a number of non-volatile memory cells in that group which have not reached respective target threshold voltage levels and comparing the determined number to a respective limit.
repeating (b)-(d) if a predetermined number of groups have an amount of non-volatile memory cells which have not reached respective target threshold voltage levels that is greater than one or more respective limits.
the non-volatile memory cells store data in sectors; and
the overlapping groups of non-volatile memory cells include a first group of non-volatile memory cells, a second group of non-volatile memory cells and a third group of non-volatile memory cells;
the second group of non-volatile memory cells includes a first set of non-volatile memory cells in the first group and a second set of non-volatile memory cells in the second group;
all of the non-volatile memory cells in the second group are either in the first set or the second set; and
determining the number of non-volatile memory cells in the second group includes counting a number of non-volatile memory cells in the second set that have not reached respective target threshold voltage levels and adding that number of non-volatile memory cells in the second set that have not reached respective target threshold voltage levels to a number of non-volatile memory cells in the first set that have not reached respective target threshold voltage levels that was previously counted when operating on the first group of non-volatile memory cells.
US13/035,539 2006-11-27 2011-02-25 Segmented bitscan for verification of programming Active 2027-08-07 US8400836B2 (en)
US12/755,610 Division US7924625B2 (en) 2006-11-27 2010-04-07 Segmented bitscan for verification of programming
US20110141819A1 US20110141819A1 (en) 2011-06-16
US8400836B2 true US8400836B2 (en) 2013-03-19
US20170117036A1 (en) 2015-10-22 2017-04-27 Sandisk Technologies Llc Source line driver for three dimensional non-volatile memory
WO2008067185A1 (en) 2006-11-27 2008-06-05 Sandisk Corporation Segmented bitscan for verification of programming
US20090207661A1 (en) 2006-11-27 2009-08-20 Yan Li Segmented bitscan for verification of programming
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US7545681B2 (en) 2009-06-09
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LI, YAN;KAMEI, TERUHIKO;LUTZE, JEFFREY W.;SIGNING DATES FROM 20061121 TO 20061122;REEL/FRAME:025870/0381
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