Source: http://www.google.com/patents/US20070200583?ie=ISO-8859-1
Timestamp: 2015-03-02 02:12:56
Document Index: 299982206

Matched Legal Cases: ['art. 3', 'art. 4', 'art. 6', 'art. 7', 'art. 9', 'art. 10', 'art. 13', 'art. 14', 'art 112', 'art 112', 'art 112', 'art 112', 'art 112', 'art 212', 'art 212', 'art 212', 'art 212', 'art 212', 'art 212', 'art 212', 'art 212', 'art 212', 'art 212', 'art 312', 'art 512', 'art 512', 'art 512']

Patent US20070200583 - Plunger and chip-testing module applying the same - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA plunger is suitable for a chip-testing module having a probe card, which has a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, conductive through-vias penetrating the membrane, and bumps disposed on a second membrane surface opposite...http://www.google.com/patents/US20070200583?utm_source=gb-gplus-sharePatent US20070200583 - Plunger and chip-testing module applying the sameAdvanced Patent SearchPublication numberUS20070200583 A1Publication typeApplicationApplication numberUS 11/484,268Publication dateAug 30, 2007Filing dateJul 10, 2006Priority dateFeb 15, 2006Also published asUS7586320Publication number11484268, 484268, US 2007/0200583 A1, US 2007/200583 A1, US 20070200583 A1, US 20070200583A1, US 2007200583 A1, US 2007200583A1, US-A1-20070200583, US-A1-2007200583, US2007/0200583A1, US2007/200583A1, US20070200583 A1, US20070200583A1, US2007200583 A1, US2007200583A1InventorsHsin-Kuan Wu, Hsing-Chou HsuOriginal AssigneeHsin-Kuan Wu, Hsing-Chou HsuExport CitationBiBTeX, EndNote, RefManClassifications (6), Legal Events (2) External Links: USPTO, USPTO Assignment, EspacenetPlunger and chip-testing module applying the same
US 20070200583 A1Abstract
A plunger is suitable for a chip-testing module having a probe card, which has a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, conductive through-vias penetrating the membrane, and bumps disposed on a second membrane surface opposite to the first membrane surface, located in a pushed area of the membrane, and electrically connected to the circuit layer through the conductive through-vias. The plunger includes a body having a pushing part and a base part and a conductive layer disposed on a surface of the pushing part and the base part. Part of the circuit layer located in the pushed area is suitable for contacting and being electrically connected to part of the conductive layer located on the pushing part. The bumps are electrically connected to the conductive layer through the conductive through-vias. Images(5) Claims(20)
1. A plunger for a chip-testing module having a probe card with a circuit board and a membrane, wherein the membrane having a circuit layer disposed on a first surface of the membrane, at least one conductive through-via penetrating the membrane, and a plurality of bumps disposed on a second surface located in a pushed area of the membrane, wherein the second surface is opposite to the first surface, wherein at least one of the bumps is connected to the circuit layer through the conductive through-via, the plunger comprising: a body having a pushing part and a base part; and a conductive layer disposed on a surface of the pushing part and the base part, wherein the circuit layer located in the pushed area is suitable for contacting and being connected to the conductive layer located on the pushing part, and at least one of the bumps is connected to the conductive layer through the conductive through-via. 2. The plunger as claimed in claim 1, wherein the probe card comprises at least one capacitor disposed on the first surface of the membrane and located outside the pushed area, and the body further has a pocket located on one side of the pushing part. 3. The plunger as claimed in claim 1, wherein the probe card comprises at least one capacitor disposed on the first surface of the membrane and located in the pushed area, and the body further has a pocket located on a top end of the pushing part. 4. The plunger as claimed in claim 1, wherein the circuit layer is suitable for contacting and being connected to the circuit board. 5. The plunger as claimed in claim 1, wherein the circuit board is suitable for contacting and being connected to the conductive layer located on the base part. 6. The plunger as claimed in claim 1, wherein the circuit layer is suitable for contacting and being connected to part of the conductive layer located on the base part. 7. A chip-testing module, comprising: a plunger, comprising: a body having a pushing part and a base part; and a conductive layer disposed on a surface of the pushing part and the base part; and a probe card, comprising: a circuit board with an opening, wherein the pushing the body penetrates the circuit board through the opening; and a membrane, having a first circuit layer disposed on a first surface of the membrane, at least one conductive through-via penetrating the membrane, and a plurality of bumps disposed on a second surface located in a pushed area of the membrane, wherein the second surface is opposite to the first surface, wherein at least one of the bumps is connected to the first circuit layer through the conductive through-via, the first circuit layer located in the pushed area contacts and is connected to the conductive layer located on the pushing part, and at least one of the bumps is connected to the conductive layer through the conductive through-via. 8. The chip-testing module as claimed in claim 7, wherein the probe card further comprises at least one capacitor disposed on the first surface of the membrane and located outside the pushed area, and the body further has a pocket located on one side of the pushing part. 9. The chip-testing module as claimed in claim 7, wherein the probe card further comprises at least one capacitor disposed on the first surface of the membrane and located in the pushed area, and the body further has a pocket located on a top end of the pushing part. 10. The chip-testing module as claimed in claim 7, wherein the probe card further comprises at least one capacitor disposed on the second surface of the membrane. 11. The chip-testing module as claimed in claim 7, wherein the first circuit layer contacts and is connected to the circuit board. 12. The chip-testing module as claimed in claim 7, wherein the circuit board contacts and is connected to the conductive layer located on the base part. 13. The chip-testing module as claimed in claim 7, wherein the first circuit layer contacts and is connected to the conductive layer located on the base part. 14. The chip-testing module as claimed in claim 7, wherein the membrane comprises a first dielectric layer disposed on the first surface of the membrane and covering part of the first circuit layer. 15. The chip-testing module as claimed in claim 7, wherein the membrane comprises a second circuit layer disposed on the second surface of the membrane. 16. The chip-testing module as claimed in claim 15, wherein the second circuit layer contacts and is connected to the circuit board. 17. The chip-testing module as claimed in claim 15, wherein the membrane comprises a second dielectric layer disposed on the second surface of the membrane and covering part of the second circuit layer. 18. The chip-testing module as claimed in claim 15, wherein the membrane comprises a plurality of circuit layers including the first circuit layer and the second circuit layer. 19. The chip-testing module as claimed in claim 7, wherein the first circuit layer comprises a power supply circuit. 20. The chip-testing module as claimed in claim 7, wherein the first circuit layer comprises a ground circuit.
CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit of Taiwan application serial no. 95105013, filed on Feb. 15, 2006. All disclosure of the Taiwan application is incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of Invention The present invention relates to a testing device and a testing module, and more particularly to a plunger and a chip-testing module applying the same. 2. Description of Related Art Testing for integrated circuit chips (IC chips) is necessary at different stages of the semiconductor process. Each IC chip in the wafer configuration and package configuration must be tested to ensure its electrical function. Along with the enhancement and complication of chip functions, the requirements for high-speed and precise testing become more and more important. The process of testing individual chips in the wafer configuration, called wafer sorting, includes establishing a temporary electrical contact between a chip and an automatic testing apparatus. Wafer sorting is an important test of the design and function of ICs, in order to select good IC chips before chip dicing and subsequent packaging. Referring to FIG. 1, it shows the schematic sectional view of a conventional chip-testing module. The conventional chip-testing module 100 is suitable for being electrically connected to a tested surface TS of a chip C. The conventional chip-testing module 100 includes a plunger 110 and a probe card 120. The plunger 110 includes a body 112 with a pushing part 112 a and a base part 112 b. The probe card 120 includes a circuit board 122 and a membrane 124. The circuit board 122 has an opening 122 a. The pushing part 112 a of the body 112 penetrates the circuit board 122 through the opening 122 a. The membrane 124 has a plurality of circuit layers 124 a overlapping one another and a plurality of bumps 124 b. The circuit layers 124 a further include a first circuit layer L1 disposed on a first membrane surface 124 c of the membrane 124, and the layers 124 a also include a second circuit layer L2 disposed on a second membrane surface 124 d of the membrane 124 where the second membrane surface 124 d is opposite to the first membrane surface 124 c. The bumps 124 b are disposed on part of a pushed area PA of the second circuit layer L2, where the pushed area PA is located on the membrane 124, to contact the tested surface TS of the chip C. The membrane 124 further has a plurality of conductive through-vias 124 e (only one of which is shown) to electrically connect the circuit layers 124 a. The membrane 124 further has a first dielectric layer 124 f disposed on the first membrane surface 124 c and covering part of the first circuit layer L1 to protect it. The membrane 124 further has a second dielectric layer 124 g disposed on the second membrane surface 124 d and covering part of the first circuit layer L2 to protect it. Furthermore, the probe card 120 further includes at least one capacitor 126 disposed on the second membrane surface 124 d of the membrane 124. In addition, the above-mentioned first circuit layer L1 includes a power supply circuit or a ground circuit. The following part illustrates the process of electrically testing the chip C by using the conventional chip-testing module 100. Referring to FIGS. 1 and 2, FIG. 2 shows the schematic sectional view of the chip-testing module in FIG. 1 during performing an electrical test. After the pushed area PA of the membrane 124 is pushed by the pushing part 112 a (which penetrates through the opening 122 a of the circuit board 122) of the body 112 of the plunger 110 and after a pressed area SA connected to the pushed area PA of the membrane 124 is clamped between the base part 112 b and the circuit board 122, the membrane 124, the circuit board 122, and the plunger 110 are fixed together to form the chip-testing module 100. In the testing process, relative displacement occurs between the chip C and the chip-testing module 100. Usually, the chip C moves perpendicularly, so that the bumps 124 b of the membrane 124 contact the tested surface TS of the chip C to electrically test the chip C. However, for the conventional chip-testing module with a membrane of high-density wiring, the connecting path of the first circuit layer is very long, resulting in an increase of its parasitic inductance value. Furthermore, the number of the signal pads on the tested surface of a chip tested by the conventional chip-testing module is limited due to the limited wiring ability of the membrane. Further, when high frequency signals are transmitted, the long connecting path of the first circuit layer increases its insertion loss, thereby reducing its transmission efficiency. SUMMARY OF THE INVENTION The present invention provides a plunger suitable for a chip-testing module. The chip-testing module has a probe card with a circuit board and a membrane. The membrane has a circuit layer disposed on a first membrane surface of the membrane, at least one conductive through-via penetrating the membrane, and a plurality of bumps disposed on a second membrane surface opposite to the first membrane surface and located in a pushed area of the membrane. At least one of the bumps is electrically connected to the circuit layer through the conductive through-via. The plunger includes a body having a pushing part and a base part and a conductive layer disposed on a surface of the pushing part and the base part. Part of the circuit layer located in the pushed area is suitable for contacting and being electrically connected to part of the conductive layer located on the pushing part. At least one of the bumps is electrically connected to the conductive layer through the conductive through-via. The present invention provides a chip-testing module, including a plunger and a probe card. The plunger includes a body having a pushing part and a base part and a conductive layer disposed on a surface of the pushing part and the base part. The probe card includes a circuit board having an opening and a membrane. The pushing part of the body penetrates the circuit board through the opening. The membrane has a first circuit layer disposed on a first membrane surface of the membrane, at least one conductive through-via penetrating the membrane, and a plurality of bumps disposed on a second membrane surface opposite to the first membrane surface and located in a pushed area of the membrane. At least one of the bumps is electrically connected to the first circuit layer through the conductive through-via. Part of the first circuit layer located in the pushed area is contacting and being electrically connected to part of the conductive layer located on the pushing part. At least one of the bumps is electrically connected to the conductive layer through the conductive through-via. In order to the make the aforementioned features and advantages of the present invention comprehensible, multiple embodiments accompanied with figures are described in detail below.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the schematic sectional view of a conventional chip-testing module. FIG. 2 shows the schematic sectional view of the chip-testing module in FIG. 1 when performing an electrical test. FIG. 3 shows the schematic sectional view of a chip-testing module according to a first embodiment of the present invention. FIG. 4 shows the schematic sectional view of the chip-testing module in FIG. 3 when performing an electrical test. FIG. 5 shows the schematic sectional view of a chip-testing module according to a second embodiment of the present invention. FIG. 6 shows the schematic sectional view of a chip-testing module according to a third embodiment of the present invention. FIG. 7 shows the schematic sectional view of a chip-testing module according to a fourth embodiment of the present invention. DESCRIPTION OF EMBODIMENTS Referring to FIG. 3, it shows the schematic sectional view of a chip-testing module according to the first embodiment of the present invention. The chip-testing module 200 of the first embodiment is suitable for being electrically connected to a tested surface TS of a chip C. The chip-testing module 200 includes a plunger 210 and a probe card 220. The plunger 210 includes a body 212 having a pushing part 212 a and a base part 212 b, and the plunger 210 also includes a conductive layer 214 disposed on the surfaces of the pushing part 212 a and the base part 212 b. The probe card 220 includes a circuit board 222 having an opening 222 a and a membrane 224. The pushing part 212 a of the body 212 penetrates the circuit board 222 through the opening 222 a. The membrane 224 has a plurality of circuit layers 224 a overlapping one another, a plurality of conductive through-vias 224 e (only one is shown) penetrating the membrane 224, and a plurality of bumps 224 b. The circuit layers 224 a further include a first circuit layer L1 disposed on a first membrane surface 224 c of the membrane 224, and the layers 224 a also include a second circuit layer L2 disposed on a second membrane surface 224 d opposite to the first membrane surface 224 c of the membrane 224. The bumps 224 b are disposed on the second membrane surface 224 d and located in a pushed area PA of the membrane 224 to contact the tested surface TS of the chip C. Furthermore, at least one of the bumps 224 b is electrically connected to the first circuit layer L1 via the conductive through-via 224 e. In the first embodiment, the membrane 224 further has a first dielectric layer 224 f disposed on the first membrane surface 224 c and covering part of the first circuit layer L1 to protect it. The membrane 224 further has a second dielectric layer 224 g disposed on the second membrane surface 224 d and covering part of the second circuit layer L2 to protect it. The probe card 220 further includes at least one capacitor 226 (FIG. 3 shows four capacitors) disposed on the first membrane surface 224 c and the second membrane surface 224 d of the membrane 224 and located outside of the pushed area PA. The body 212 may further have a pocket 212 c located on one side S of the pushing part 212 a to accommodate the capacitors 226 disposed on the first membrane surface 224 c. Furthermore, in the first embodiment, the first circuit layer L1 includes a power supply circuit or a ground circuit. The following part illustrates the process of electrically testing the chip C by using the chip-testing module 200 of the first embodiment. Referring to FIGS. 3 and 4, FIG. 4 shows the schematic sectional view of the chip-testing module in FIG. 3 when an electrical test is performed. After the pushed area PA of the membrane 224 is pushed by the pushing part 212 a (which penetrates through the opening 222 a of the circuit board 222) of the body 212 of the plunger 210 and after a pressed area SA connected to the pushed area PA of the membrane 224 is clamped between the base part 212 b and the circuit board 222, the membrane 224, circuit board 222, and plunger 210 are fixed together to form the chip-testing module 200. Therefore, part of the first circuit layer L1 located in the pushed area PA contacts and is electrically connected to part of the conductive layer 214 located on the pushing part 212 a. At least one of the bumps 224 b is electrically connected to the conductive layer 214 through the conductive through-via 224 e. Part of the first circuit layer L1 located in the pressed area SA contacts and is electrically connected to part of the conductive layer 214 located on the base part 212 b, and part of the second circuit layer L2 contacts and is electrically connected to the circuit board 222. In the testing process, relative displacement occurs between the chip C and the chip-testing module 200. Usually, the chip C moves perpendicularly, so that the bumps 224 b of the membrane 224 contact the tested surface TS of the chip C to electrically test the chip C. When the first circuit layer L1 includes a power supply circuit or a ground circuit, the return path is increased by simultaneously contacting the circuit board 222 and the conductive layer 214 of the first circuit layer L1. As a result, the parasitic inductance is reduced. Referring to FIGS. 5 and 6, the schematic sectional views of a chip-testing module according to the second embodiment and the third embodiment of the present invention are respectively shown. The difference between the second embodiment and the first embodiment is that part of the capacitors 326 included in the probe card 320 of the chip-testing module 300 in the second embodiment may be disposed on the first membrane surface 324 c in the pushed area PA of the membrane 324 and that the body 312 may further have a pocket 312 c located on a top end T of the pushing part 312 a to accommodate the above-mentioned capacitors 326 located in the pushed area PA of the membrane 324. However, the positions where the capacitors 226 are disposed in the first embodiment may be combined with the positions where the capacitors 326 are disposed in the second embodiment. The manner of combination may be seen in the positions where the capacitors 426 are disposed in the chip-testing module 400 of the third embodiment. Referring to FIG. 7, it shows the schematic sectional view of a chip-testing module according to the fourth embodiment of the present invention. The difference between the fourth embodiment and the first embodiment is that the membrane 224 of the chip-testing module 200 in the first embodiment is fixed on the first plate surface 222 b of the circuit board 222, while the membrane 524 of the chip-testing module 500 in the fourth embodiment is fixed on the second plate surface 522 c of the circuit board 522, i.e. part of the first circuit layer (not shown) contacts and is electrically connected to the circuit board 522. Additionally, the base part 512 a adjacent to the pushing part 512 b of the plunger 510 is directly fixed on the first plate surface 522 b of the circuit board 522 without via the membrane 524, and part of the conductive layer 514 located on the base part 512 a directly contacts and is electrically connected to a pad (not shown) of the first plate surface 522 b of the circuit board 522. In view of the above, the plunger and the chip-testing module applying the same of the present invention have at least the following advantages: a. Since a conductive layer is disposed on the surface of the plunger of the present invention, when a chip is electrically tested, the conductive layer contacts the circuit layer of the membrane, thereby increasing the return path and reducing the connecting path of the circuit layer of the membrane, so as to reduce the parasitic inductance value, insertion loss, and crosstalk interference of the circuit layer of the membrane. b. Since the body of the plunger of the present invention has a pocket for accommodating capacitors, the options of the positions of the capacitors and the number thereof on the membrane are increased. c. Since the ground circuit of the membrane can provide additional return paths via the conductive layer of the plunger, the flexibility in designing the wiring layout of the membrane is increased to raise the number of the signal pads of the chip to be tested. Though the present invention has been disclosed above by the embodiments, they are not intended to limit the invention. Anybody skilled in the art may make some modifications and variations without departing from the spirit and scope of the invention. Therefore, the protecting range of the invention falls in the appended claims. Classifications U.S. Classification324/754.07, 324/756.03, 324/762.03International ClassificationG01R31/02Cooperative ClassificationG01R31/2889European ClassificationG01R31/28G5CLegal EventsDateCodeEventDescriptionFeb 6, 2013FPAYFee paymentYear of fee payment: 4Jul 10, 2006ASAssignmentOwner name: VIA TECHNOLOGIES, INC., TAIWANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:WU, HSIN-KUAN;HSU, HSING-CHOU;REEL/FRAME:018052/0162;SIGNING DATES FROM 20060427 TO 20060503RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services