Source: http://www.google.com/patents/US7013413?dq=3657699
Timestamp: 2016-07-26 08:39:47
Document Index: 452156324

Matched Legal Cases: ['art 40', 'art 30', 'art 40', 'art 30', 'art 40', 'art 40', 'art 30', 'art 20', 'art 30', 'art 20', 'art 30', 'art 40', 'art 500', 'art 300', 'art 400', 'art 500', 'art 300', 'art 500', 'art 400', 'art 300']

Patent US7013413 - Method for compressing output data and a packet command driving type memory ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsThe present invention relates to a packet command driving type memory device, a method for compressing output data according to the present invention is characterized to write first data of a certain bit in a corresponding address of core cell regions, read the first data of a certain bit written in...http://www.google.com/patents/US7013413?utm_source=gb-gplus-sharePatent US7013413 - Method for compressing output data and a packet command driving type memory deviceAdvanced Patent SearchPublication numberUS7013413 B1Publication typeGrantApplication numberUS 09/604,086Publication dateMar 14, 2006Filing dateJun 27, 2000Priority dateJun 28, 1999Fee statusPaidPublication number09604086, 604086, US 7013413 B1, US 7013413B1, US-B1-7013413, US7013413 B1, US7013413B1InventorsSung Wook Kim, In Hong KimOriginal AssigneeHyundai Electronics Industries Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (15), Referenced by (21), Classifications (15), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetMethod for compressing output data and a packet command driving type memory device
US 7013413 B1Abstract
The present invention relates to a packet command driving type memory device, a method for compressing output data according to the present invention is characterized to write first data of a certain bit in a corresponding address of core cell regions, read the first data of a certain bit written in the address, compare the written data and the read data by dividing it to an upper certain bit and a lower certain bit, generate compressed data of 1 bit with an information about whether a fail is.
During a write operation, individual data bits are transferred to an interface part 40 and are packed into 8-bit packets, each of which is packed during 4 clock cycles timed at a negative edge and a positive edge of each clock cycle per data pad (DQA0–DQA7, DQB0–DQB7). Even bits (i.e., 0, 2, 4, 6) of the 8-bit data packeted during 4 clock cycles, for example, are transferred to a data input/output part 30 via an interface part 40 at an ascending edge of a clock signal tclk. Odd bits (i.e., 1, 3, 5, 7), for example, are transferred to the data input/output part 30 via the interface part 40 at a descending edge of a clock signal tclk.
The 8-bit data transferred via the interface part 40 are transformed to parallel data of 8 bits WD<0:7> through a data input shift part (not shown in the drawing) of the data input/output part 30, transferred to the core cell region 10 via a column control part 20, and written in a packet form. During a read operation, an 8-bit packet RD<0:7> is read from the core cell region 10, transferred to the data input/output part 30 via the column control part 20. The data input/output part 30 transforms data in packet form to an even-bit part and an odd-bit part via shift registers 31–34. Multiplexer and the drivers 41–44 of the interface part 40 transfer even data bits eread<0, 2, 4, 6> to data pads at an ascending edge of each clock signal tclk and Odd data bits oread<1, 3, 5, 7> to data pads at a descending edge of each clock signal tclk. Accordingly, 8 bits are transferred from a packet form to a serial form via respective data pads (DQA0–DQA7, DQB0–DQB7) during 4 clock cycles.
The present invention solves the problem of the prior art. It is an object of the present invention to provide a method for compressing output data to reduce testing time and a packet command driving type memory device with a pre-fetched data output structure.
FIG. 1 shows a data pass structure in a packet command driving type memory device of the prior art.
Referring to FIG. 4, in a memory device according to an embodiment of the present invention, the read data comparing part 500 comprises a number of comparators 501–508 for receiving 8 bits data RD<0:7> read from the core cell region 100 according to a control signal (S_DATEST) when it is a DA mode test, compressing upper 4-bit data RD<0:3> and a lower 4-bit data RD<4:7> and generating a 1-bit data error<i>, 0<i<7, having information indicating whether a failure exists, multiplexers 509–512 for selecting the 8-bit data RD<0:7> read from the core cell region 100 when it is a normal mode or error <0:7> generated by the comparators 501–508 when it is a DA mode test according to the control signal (S_DATEST).
First of all, a control signal (S_DATEST) in a low state is inputted from the outside when it is in a normal mode and thereby the comparators 501–508 are disabled, the multiplexers 509–512 select the 8-bit data RD<0:7> read from the core cell region 100 inputted to a first input terminal 10 of the multiplexer 509–512 according to the control signal (S-DATEST). Data New RD<0:7> outputted from the multiplexers 509–512 are transformed to an even-bit part and an odd-bit part via shift registers 301–304 of the data input/output part 300. FIG. 5 shows respective shift registers 301–304 in detail. Even data bits New RD<0, 2, 4, 6> of the New RD<0:7> transferred via the multiplexers 509–512 are shifted via shift registers 301-1, 302-1, 303-1, 304-1 according to a clock signal. Odd data bits New RD<1, 3, 5, 7> are shifted via shift registers 301-2, 302-2, 303-2, 304-2.
Data transformed via shift registers 301–304 are synchronized to a clock signal TestClkR via a plurality of multiplexers and drivers 401–404 of the interface part 400 and outputted serially via respective output pads (DQA0–DQA7 or DQB0–DQB7).
That is, since even data bits transferred via each shift register at an ascending edge of the clock signal TestClkR and odd data bits are transferred at a descending edge of the clock signal TestClkR, 8-bit data are transferred serially in a packet form via respective output pads (DQA0–DQA7 or DQB0–DQB7) during 4 clock cycles.
On one hand, as the control signal (S_DATEST) changes to a high state when it is a DA mode test and inputted to an enable terminal (EN) of data comparators 501–508, the data comparators 501–508 are enabled. The data comparators 501–508 receive 8-bit data read and prefetched from the core cell region 100. Each data comparator receives 4 bits and compresses them and generates a compressed 1-bit data error <i>, i≦i≦7, each indicating whether a failure has occurred.
Specifically, the comparators 501, 503, 505, 507 receive upper 4 bits RD<0:3> of 8-bit data read from the core cell region 100 respectively and each generates a 1-bit compressed data, namely, error<0>, error<2>, error<4>, and error <6>. The comparators 502, 504, 506, 508 receive lower 4 bits RD<4:7> of 8-bit data respectively and each generates a 1-bit compressed data, namely error <1>, error <3>, error <5>, and error <7>. A comparing block is defined to include 2 adjacent comparators (e.g., comparators 501 and 502, comparators 503 and 504, comparators 505 and 506, comparators 507 and 508), one for upper 4 bits and one for lower 4 bits. The 4 comparing blocks of the read data comparing part 500 are arranged corresponding to the respective shift registers 301–304 of the data input/output part 300. With this configuration, four 8-bit data packets are read respectively, compared with corresponding 8-bit written data by adjacent 4 comparing blocks of the read data comparing part 500 as shown in FIG. 4, thereby each comparator generates a 1-bit compressed data. Accordingly, 8 comparators in 4 comparing blocks generate a compressed 8-bit error data error<0:7> which is transformed to an even-bit part and an odd-bit part via the shift register 301.
The multiplexer 509 selects the error <0:7> compressed by the comparators 501–508 during a DA mode test according to the control signal (S-DATEST). That is, the data New RD<0:7> selected via the multiplexer 509 can be either error<0:7> or the read data RD<0:7>. The selected parallel data is forwarded to the shift register 301 where the data is transformed into an even-bit part and an odd-bit part and further converted into serial data via the multiplexer and driver 401 of the interface part 400 and outputted via a corresponding output pad DQB0. In a preferred embodiment, the second input terminal I1 of multiplexers 510–512 is grounded so that these multiplexers only select RD<0:7> when S-DATEST is low in a normal mode. The selected data by the multiplexers 510–512 are forwarded to shift registers 302–304, and multiplexers and drivers 402–404, respectively, which transform the selected data into serial data and output the serial data to the output pads DQB1, DQB2 and DQB3. That is, when S-DATEST is high, there is no data selected by multiplexers 510–512. When S-DATEST is low, these multiplexers select RD<0:7> (an 8-bit data packet read from the core cell region 100). Therefore, during a DA mode test, DQB1, DQB2, and DQB3 have no test output.
FIG. 5 shows one example of a shift register, e.g., 301, of a data input/output part 300. Other shift registers 302–304 may be similarly constructed. The exemplary shift register 301 according to the present invention comprises a first shift register (e.g., 301-1) for even data bits for shifting even data bits of 8-bit data New RD<0:7> inputted via multiplexer 509 at an ascending edge of a clock signal TestClkR, a second shift register (e.g., 301-2) for odd data bits for shifting odd data bits of 8-bit data New RD<0:7> inputted via the multiplexers 509 in a descending edge of a clock signal TestClkR.
FIG. 6 shows an exemplary construct of a comparator (e.g., 501) in a memory device according to the present invention. In this exemplary embodiment, comparator 501 stores 4-bit data WD<0:3> in the core cell region 100 (not shown), reads back 4 written bits RD<0:3> immediately after a write operation and compares the read 4 bits RD<0:3> with the stored 4 bits WD<0:3>. Each of the comparators 502–508 compares a 4-bit stored data with a 4-bit read data. The 4-bit stored data can be either WD<0:3> or WD<4:7>. The 4-bit read data can be either RD<0:3> or RD<4:7>.
The comparator 501 includes a number of comparing means 521–524 for comparing 4 bits WD<0:3> or WD<4:7> of the written data WD<0:7> with 4 bits RD<0:3> or RD<4:7> of the read data RD<0:7>, each of the comparing means performs 1-bit comparison, respectively. The comparator 501 further includes a generating means 525 for receiving an output signal from each of the comparing means 521–524 and generating a 1-bit compressed data Error <0>, indicating whether a failure has occurred. Each of the comparing means 521–524 (e.g., 521) comprises a first NAND GATE 526 for receiving a corresponding 1-bit signal of the 4-bit written data WD<0:3> and a control signal (S_DATEST) as an enabling signal EN, a second NAND GATE 527 for receiving a corresponding 1-bit signal of the 4-bit read data RD<0:3> and the same control signal (S_DATEST) as an enabling signal EN, a second NAND GATE 527 for receiving a corresponding 1-bit signal of the 4-bit read data RD<0:3> and the same control signal (S_DATEST) as an enabling signal EN, a first NMOS transistor 528 with a gate receiving the output of the second NAND GATE 527 and a drain receiving the output of the first NAND GATE 526, a second NMOS transistor 529 with a gate receiving the output of the first NAND GATE 526 and a drain receiving the output of the second NAND GATE 527, a first and a second PMOS transistor 530, 531 connected serially between a power voltage Vcc and the sources of the first and the second NMOS transistors 528 and 529, and with their gates receiving the output signals of the first and the second NAND GATE 526, 527, respectively, a third NAND GATE 532 for receiving the output signals of the first and the second NAND GATE 526, 527, a third PMOS transistor 533 with a gate receiving an output of the third NAND GATE 532, a source receiving a power voltage, a drain connected to the sources of the first and second NMOS transistor 528, 529 and drains of the first and the second PMOS transistor 530, 531.
Each of the comparing means 521–524 generates a comparing signal output at the sources of the first and the second NMOS transistor 528, 529 and the drains of the first to the third PMOS transistor 530, 531, 533. Specifically, the comparing means 521 generates a first comparing signal OUT1; the comparing means 522 generates a second comparing signal OUT2; the comparing means 523 generates a third comparing signal OUT3; and the comparing means 524 generates a fourth comparing signal OUT4. The generating means 525 receives these four comparing signals OUT1–OUT4 and generates a 1-bit compressed data ERROR<0> signaling whether a failure has occurred. Hereinafter, an operation of each comparator of the present invention having a construction as described above will be explained.
When the 1-bit read data RD<0> and 1-bit written data WD<0> inputted to the comparator 521 are the same, for example, both being ‘0’, the outputs of the first and the second NAND GATE 526, 527 are high, turning on the first and the second NMOS transistor 528, 529. The output of the NAND GATE 532 receiving the outputs of the first and the second NMOS transistor 528, 529 as input becomes low, thereby turning on the PMOS transistor 533. When all the comparing means 521–524 output comparing signals OUT1–OUT4 are high, the compressed data error <0> produced by the NAND GATE 525 is low.
Similarly, when the 1-bit read data RD<0> and the 1-bit written data WD<0>, inputted to the comparator 521, are both ‘1’, the outputs of the first and the second NAND GATE 526, 527 are high. In this case, the first and the second NAND NMOS transistor 528, 529 are turned off and the PMOS transistors 530, 531 are turned on. When all 4 bits in RD<0:3> have the same value as the 4 bits in WD<0:3>, i.e., the first to the fourth comparing signal OUT1–OUT4 from the comparing means 521–524 are all high, making the compressed error <0> low. When the 1-bit read data (e.g., RD<0>, and 1-bit written data, e.g., WD<0>, are different from each other, for example, RD<0>=0, WD<0>=1, the first NMOS transistor 528 is turned off and the second NMOS transistor 529 is turned on. When the 1-bit written data WD<0> is low and the 1-bit read data RD<0> is high, the first NMOS transistor 528 is turned on and the second NMOS transistor 529 is turned off. When 528 and 529 have different states (one is on and one is off), the third PMOS transistor 533 is turned off and the first PMOS transistor 530 and the second PMOS transistor 531 are not turned on. In this case, OUT1 is low.
Accordingly, when any of the comparing means 521–524 of the comparator 501 generates a low comparing signal, the 1-bit compressed output error <0> generated by the NAND GATE of the corresponding generating means 525 becomes high.
Similar operational scheme applies to other comparators 502–508. That is, each comparator has four comparing means (similar to 521–524) and each of the comparing means of each comparator compares 1 written bit with 1 read bit by performing a logic operation, such as an Exclusive NOR GATE, generating a high state signal when two inputs (i.e., the 1 written bit and the 1 read bit) are the same, a low state signal when two inputs are different from each other. Then the corresponding NAND GATE (similar to 525) in each comparator will generate a low output when all 4 bits read match the 4 written bits and a high output when any of the 4 read bits fails to match the corresponding written bit.
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