Source: https://patents.google.com/patent/US20140177358A1/en
Timestamp: 2019-10-21 00:24:30
Document Index: 228041645

Matched Legal Cases: ['§119', 'art 231', 'art 231', 'art 231', 'art 231', 'art 231', 'art 231', 'art 231', 'art 231', 'art 231', 'art1']

US20140177358A1 - Address counting circuit and semiconductor apparatus using the same - Google Patents
US20140177358A1
US20140177358A1 US13/845,293 US201313845293A US2014177358A1 US 20140177358 A1 US20140177358 A1 US 20140177358A1 US 201313845293 A US201313845293 A US 201313845293A US 2014177358 A1 US2014177358 A1 US 2014177358A1
US13/845,293
US9336842B2 (en
Yong Kee KWON
Hyung Gyun YANG
2012-12-24 Priority to KR10-2012-0151737 priority Critical
2012-12-24 Priority to KR1020120151737A priority patent/KR20140082173A/en
2013-06-26 Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YANG, HYUNG GYUN, KWON, YONG KEE, LEE, HYUNG DONG, MOON, YOUNG SUK
2014-06-26 Publication of US20140177358A1 publication Critical patent/US20140177358A1/en
2016-05-10 Publication of US9336842B2 publication Critical patent/US9336842B2/en
A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die.
The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2012-0151737 filed on Dec. 24, 2012, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.
Various embodiments relate to a semiconductor integrated circuit, and more particularly to an address counting circuit and a semiconductor apparatus using the same.
A semiconductor apparatus is configured to store data and output stored data. In order to increase the data storage capacity of a semiconductor apparatus, a stacked semiconductor apparatus in which two or more semiconductor memory dies for storing data are stacked upon one another may be used.
For example, where a data copying operation is performed in a semiconductor apparatus which has a plurality of semiconductor memory dies integrated vertically therein, that is, where the data stored in one memory die among the plurality of semiconductor memory dies is to be transferred to and stored in another memory die, when a large data copying operation is performed, a processor for controlling the plurality of semiconductor memory dies, according to a known art, consecutively input read commands and addresses to one memory die and consecutively input write commands and addresses to another memory die.
Therefore, power consumption may increase due to the commands and addresses consecutively inputted to the semiconductor apparatus in which the plurality of semiconductor memory dies are stacked when a large data copying operation is to performed.
In an embodiment of the present invention, a semiconductor apparatus includes: a first memory die; a second memory die; and a is processor configured to output an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and output an external command, an external start address and an external end address which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be stored in the second memory die.
In an embodiment of the present invention, a semiconductor apparatus includes: a command processing unit configured to decode an external command inputted from a processor and generate an internal command; an address buffer configured to buffer external address information inputted from the processor and output internal address information; an internal address generation block configured to count internal addresses in response to the internal command and the internal address information; and a memory die including a data storage unit which is configured to store data in a region designated by the internal address information or output data from a region designated by the internal address information, according to the internal command.
In an embodiment of the present invention, an address counting circuit includes: a counting control section configured to generate an enable signal, a column start address and a row start address in response to an internal command, internal address information, a first counting signal and a second counting signal; a column address counting section configured to generate the first is counting signal and a row address increase signal in response to the enable signal and the column start address; a row address counting section configured to generate the second counting signal in response to the row start address and the row address increase signal; a column address buffer configured to buffer the first counting signal and output a column-side counting address; and a row address buffer configured to buffer the second counting signal and output a row-side counting address.
FIGS. 1 and 2 are diagrams explaining a semiconductor apparatus in accordance with an embodiment of the present invention;
FIG. 3 is a configuration diagram of the first memory die of FIG. 1;
FIG. 4 is a configuration diagram of the address counting unit of FIG. 3;
FIG. 5 is a configuration diagram of the counting control section of FIG. 4; and
FIG. 6 is a diagram explaining the semiconductor apparatus in accordance with an embodiment of the present invention.
Hereinafter, an address counting circuit and a semiconductor apparatus using the same according to the present invention will be described below with reference to the accompanying drawings through exemplary embodiments.
Referring to FIG. 1, a semiconductor apparatus 1000 in accordance with an embodiment of the present invention includes a processor 100, a first memory die 200, and a second memory die 300.
The processor 100 is configured to control the first and second semiconductor memory dies 200 and 300 and electrically coupled to the first and second semiconductor memory dies 200 and 300.
The first memory die 200 is configured to receive an external command, an external address and data transmitted from the processor 100 and store received data. Also, the first memory die 200 may output stored data.
The second memory die 300 is configured to receive an external command, an external address and data inputted from the processor 100, store received data. Also, the second memory die 300 may output stored data.
FIG. 1 shows the case where, in the semiconductor apparatus in accordance with an embodiment of the present invention, the data stored in the first memory die 200 is to be stored in the second memory die 300.
Referring to FIG. 1, for example, the processor 100 inputs a read command Read_com as an external command, and an external is start address start_add and an external end address end_add as external addresses, to the first memory die 200. Also, the processor 100 inputs a write command Write_com as an external command, and an external start address start_add and an external end address end_add as external addresses, to the second memory die 300.
When the read command Read_com is inputted, the first memory die 200 outputs data Data—1 stored in addresses from the external start address start_add to the external end address end_add, to the processor 100.
When the write command Write_com is inputted, the second memory die 300 stores data Data—2 inputted from the processor 100, in a region from the external start address start_add to the external end address end_add.
The processor 100 includes a data buffer 110 which is configured to store the data Data—1 outputted from the first memory die 200 and output the data Data—2 to the second memory die 300. For example, the data Data—1 is the same data as the data Data—2.
FIG. 2 shows the case where, in the semiconductor apparatus in accordance with an embodiment of the present invention, the data stored in the second memory die 300 is to be stored in the first memory die 200.
Referring to FIG. 2, for example, the processor 100 inputs a read command Read_com as an external command, and an external start address start_add and an external end address end_add as external addresses, to the second memory die 300. Also, the is processor 100 inputs a write command Write_com as an external command, and an external start address start_add and an external end address end_add as external addresses, to the first memory die 200.
When the read command Read_com is inputted, the second memory die 300 outputs data Data—2 stored in the address from the external start address start_add to the external end address end_add, to the processor 100.
When the write command Write_com is inputted, the first memory die 200 stores data Data—1 inputted from the data buffer 110 provided in the processor 100, in a region from the external start address start_add to the external end address end_add.
The first and second semiconductor memory dies 200 and 300 operating in these ways are configured in the same manner, and thus, the description of the configuration of the first memory die 200 will replace the description of the configuration of the second memory die 300.
Referring to FIG. 3, the first memory die 200 includes a command processing unit 210, an address buffer 220, an address counting unit 230, a row-side address processing unit 240, a column-side address processing unit 250, a data storage unit 260, a data processing unit 270, and a data input/output pad 280. The address counting unit 230, the row-side address processing unit 240 and the column-side address processing unit 250 may constitute an internal address generation block 290.
The command processing unit 210 is configured to decode an external command CMD_ext inputted from the processor 100 and generate an internal command CMD_int.
The address buffer 220 is configured to buffer external address information Add_ext inputted from the processor 100 and output internal address information Add_int. The external address information Add_ext includes a start address start_add and an end address end_add of a region to and from which data is to be inputted and outputted. The internal address information Add_int generated by, for example, buffering such external address information Add_ext also includes a start address start_add and an end address end_add.
The internal address generation block 290 is configured to generate an internal address in response to the internal command CMD_int and the internal address information Add_int. The internal address may include a row-side internal address R_addint and a column-side internal address C_addint. For example, the internal address generation block 290 generates the internal addresses R_addint and C_addint by performing a counting operation in response to the internal command CMD_int. The internal address generation block 290 generates the internal addresses R_addint and C_addint, for example, by increasing the address by one from the value of the start address start_add to the value of the end address end_add.
In an embodiment of the present invention, the internal address generation block 290 includes the address counting unit 230, is the row-side address processing unit 240, and the column-side address processing unit 250.
The address counting unit 230 is configured to generate a row-side counting address R_addcnt and a column-side counting address C_addcnt by performing a counting operation in response to the internal address information Add_int when the internal command CMD_int is a write command or a read command. For example, if the internal command CMD_int is a write command or a read command, the address counting unit 230 sets the row-side counting address R_addcnt to a value corresponding to the value of the start address start_add and performing a count operation. In the counting operation, the address increases from the set row-side counting address R_addcnt and ends the counting operation when the row-side counting address R_addcnt has reached the value of the end address end_add. Also, if the internal command CMD_int is a write command or a read command, the address counting unit 230 sets the column-side counting address C_addcnt to a value corresponding to the value of the start address start_add and performing a count operation. In the counting operation, the address increases from the set column-side counting address C_addcnt and ends the counting operation when the column-side counting address C_addcnt has reached the value of the end address end_add.
The row-side address processing unit 240 is configured to generate the row-side internal address R_addint in response to the row-side counting address R_addcnt.
The column-side address processing unit 250 is configured to generate the column-side internal address C_addint in response to the column-side counting address C_addcnt.
The data storage unit 260 is configured to store data Data in a region which is designated by the internal address information Add_int or output data Data stored in the region which is designated by the internal address information Add_int, according to the internal command CMD_int.
The data processing unit 270 is configured to output the data inputted from the data input/output pad 280, to the data storage unit 260 in response to the internal command CMD_int, or output the data Data outputted from the data storage unit 260, to the data input/output pad 280 in response to the internal command CMD_int.
The data input/output pad 280 is coupled to the data buffer 110 which is provided in the processor 100 shown in FIG. 1.
Referring to FIG. 4, the address counting unit 230 includes a counting control section 231, a column address counting section 232, a row address counting section 233, a column address buffer 234, and a row address buffer 235.
The counting control section 231 is configured to generate an enable signal en_signal, a column start address col_adds and a row start address row_adds in response to the internal command CMD_int, the internal address information Add_int, a first counting signal CNT—1 and a second counting signal CNT—2. As described above, the internal command CMD_int includes the start address start_add and the end address end_add. For example, when the internal command CMD_int is a read command or a write command, the counting control section 231 enables the enable signal en_signal, outputs the row start address row_adds and the column start address col_adds in response to the start address start_add, and disables the enable signal en_signal by comparing the end address end_add with the first and second counting signals CNT—1 and CNT—2. For example, the counting control section 231 disables the enable signal en_signal when the end address end_add is identical to the first and second counting signals CNT—1 and CNT—2.
The column address counting section 232 is configured to generate the first counting signal CNT—1 and a row address increase signal row_inc in response to the enable signal en_signal and the column start address col_adds. For example, the column address counting section 232 sets the first counting signal CNT—1 to the same value as the column start address col_adds when the enable signal en_signal is enabled, increases the set first counting signal CNT—1 by performing a counting operation, and enables the row address increase signal row_inc for a preset time in the case where the first counting signal CNT—1 reaches a maximum value and then becomes a minimum value. Describing this in detail through an example, the first counting signal CNT—1 is set to (0, 0, 1, 1) by the column start address col_adds, and is increased from the set value by performing a counting operation. If the first counting signal CNT—1 reaches the is maximum value of (1, 1, 1, 1) and then becomes the minimum value of (0, 0, 0, 0), the row address increase signal row_inc is enabled for the preset time and is then disabled.
The row address counting section 233 is configured to generate the second counting signal CNT—2 in response to the row start address row_adds and the row address increase signal row_inc. For example, the row address counting section 233 sets the second counting signal CNT—2 to the same value as the row start address row_adds, and increases the counting value of the set second counting signal CNT—2 each time the row address increase signal row_inc is enabled. Describing this in detail through an example, the second counting signal CNT—2 is set to (0, 0, 1, 0) by the row start address row_adds, and is increased consecutively to counting values of (0, 0, 1, 1), (0, 1, 0, 0), (0, 1, 0, 1), (0, 1, 1, 0), (0, 1, 1, 1), . . . each time the row address increase signal row_inc is enabled.
The column address buffer 234 is configured to buffer the first counting signal CNT—1 when the enable signal en_signal is enabled and output the column-side counting address C_addcnt.
The row address buffer 235 is configured to buffer the second counting signal CNT—2 when the enable signal en_signal is enabled and output the row-side counting address R_addcnt.
Referring to FIG. 5, the counting control section 231 includes a decoding part 231-1, a first address storage part 231-2, a second address storage part 231-3, and a comparison part 231-4.
The decoding part 231-1 is configured to decode the internal is command CMD_int, enable the enable signal en_signal when the internal command CMD_int is a read command or a write command, and generates first and second storage enable signals SA1 and SA2. Also, the decoding part 231-1 disables the enable signal en_signal when a counting end signal CNT_end is enabled.
The first address storage part 231-2 is configured to store the start address start_add and the end address end_add when the first storage enable signal SA1 is enabled, and output the stored start address start_add and end address end_add as the column start address col_adds and a column end address col_adde.
The second address storage part 231-3 is configured to output the start address start_add and the end address end_add as the row start address row_adds and a row end address row_adde when the second storage enable signal SA2 is enabled.
The comparison part 231-4 is configured to enable the counting end signal CNT_end when the first counting signal CNT—1 and the column end address col_adde are the same with each other and the second counting signal CNT—2 and the row end address row_adde are the same with each other.
Operations of one memory die provided in the semiconductor apparatus 1000 in accordance with an embodiment of the present invention, configured as mentioned above, will be described below.
Referring to FIG. 3, the first memory die 200 includes the command processing unit 210, the address buffer 220, the address is counting unit 230, the row-side address processing unit 240, the column-side address processing unit 250, the data storage unit 260, the data processing unit 270, and the data input/output pad 280.
The command processing unit 210 decodes the external command CMD_ext inputted from the processor 100 and generates the internal command CMD_int.
The address buffer 220 buffers the external address information Add_ext and outputs the internal address information Add_int. Each of the external address information Add_ext and the internal address information Add_int includes the start address start_add and the end address end_add.
The address counting unit 230 generates the row-side counting address R_addcnt and the column-side counting address C_addcnt by performing a counting operation to increase the internal command CMD_int from the start address start_add to the end address end_add when the internal command CMD_int is a read or write command. In detail, referring to FIGS. 4 to 6, in the case where the internal command CMD_int is a read or write command, the column-side counting address C_addcnt and the row-side counting address R_addcnt corresponding to the start address start_add are set. The column-side counting address C_addcnt and the row-side counting address R_addcnt with set values are increased up to the end address end_add by performing a counting operation. For example, referring to FIG. 6, the start address start_add of the column-side counting address C_addcnt is the decimal number of 3, and the end address end_add of the column-side counting address C_addcnt is the decimal number of 4. Also, the start address start_add of the row-side counting address R_addcnt is the decimal number of 0, and the end address end_add of the row-side counting address R_addcnt is the decimal number of 3. The column-side counting address C_addcnt is increased from 3 to 7 by performing a counting operation, and, then, when becoming 0 (a minimum value) from 7 (a maximum value), the row-side counting address R_addcnt is increased to 1 from 0 by performing a counting operation. In this way, the column-side counting address C_addcnt and the row-side counting address R_addcnt are generated. When the row-side counting address R_addcnt becomes 3 and the column-side counting address C_addcnt becomes 4, counting operation of the column-side counting address C_addcnt and the row-side counting address R_addcnt is ended.
Referring back to FIG. 3, the row-side address processing unit 240 outputs the row-side counting address R_addcnt as the row-side internal address R_addint.
The column-side address processing unit 250 outputs the column-side counting address C_addcnt as the column-side internal address C_addint.
The data storage unit 260 stores the data Data inputted from the data processing unit 270, in a region corresponding to the row-side internal address R_addint and the column-side internal address C_addint when the internal command CMD_int is a write command. Further, the data storage unit 260 outputs the data Data stored in a region corresponding to the row-side internal address R_addint and the column-side internal address C_addint, to the data processing unit 270 when the internal command CMD_int is a read command.
The data processing unit 270 outputs the data Data outputted from the data storage unit 260, through the data input/output pad 280 to the data buffer 110 provided in the processor 100 when the internal command CMD_int is a read command. Further, the data processing unit 270 outputs the data Data outputted from the data buffer 110 and inputted through the data input/output pad 280, to the data storage unit 260 when the internal command CMD_int is a write command.
In this way, a memory die (for example, the first memory die 200) which is provided in the semiconductor apparatus 1000 in accordance with an embodiment of the present invention may input data to a position corresponding to addresses from a start address to an end address when a read or write command is inputted and the start address and the end address are inputted, and may output the data stored in the corresponding position.
Therefore, it is not necessary for a processor to consecutively input a read or write command to a memory die to output or input large data, and also, it is not necessary for the processor to consecutively input addresses. Accordingly, power consumption may be reduced when inputting and outputting large is capacity data.
As is apparent from the above descriptions, a semiconductor apparatus which has a plurality of semiconductor memory dies stacked upon one another may include a processor for controlling the semiconductor memory dies. For example, where large data is copied from one memory die to another memory die, by inputting a read command, a start address and an end address to one memory die and by inputting a write command, a start address and an end address to another memory die, it is not necessary for the processor to consecutively input the read command, the write command and the addresses to the semiconductor memory dies which perform data copy. As a consequence, in the semiconductor apparatus in accordance with an embodiment of the present invention in which the plurality of semiconductor memory dies share one processor, power consumption may be reduced in the case of performing a large data copying operation when compared to a known semiconductor apparatus.
While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the address counting circuit and the semiconductor apparatus using the same described herein should not be limited based on the described embodiments. Rather, the address counting circuit and the semiconductor apparatus using the same described herein should only be limited in light of the claims that follow when taken in is conjunction with the above description and accompanying drawings.
a processor configured to provide an external command, an external start address and an external end address, which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die.
2. The semiconductor apparatus according to claim 1, wherein the processor is configured to output an external command, an external start address and an external end address which are associated with a read operation, to the second memory die, and output an external command, an external start address and an external end address which are associated with a write operation, to the first memory die, in the case where data stored in the second memory die is to be transferred to and stored in the first memory die.
3. The semiconductor apparatus according to claim 2, wherein the processor comprises:
a data buffer configured to transfer data outputted from the first memory die, to the second memory die when data stored in the first memory die is to be transferred to and stored in the second memory die, and transfer data outputted from the second memory die, to the first memory die when data stored in the second memory die is to be transferred to and stored in the first memory die.
4. The semiconductor apparatus according to claim 3, wherein the first memory die outputs data stored in addresses from the external start address to the external end address, to an outside when the external command outputted from the processor is a read command, and stores data, inputted from an outside, in a region from the external start address to the external end address when the external command outputted from the processor is a write command.
5. The semiconductor apparatus according to claim 3, wherein the second memory die outputs data stored in addresses from the external start address to the external end address, to an outside when the external command outputted from the processor is a read command, and stores data, inputted from an outside, in a region from the external start address to the external end address when the external command outputted from the processor is a write command.
a command processing unit configured to decode an external command inputted from a processor and generate an internal command;
an address buffer configured to buffer external address information inputted from the processor and output internal address information;
an internal address generation block configured to generate internal addresses by performing a counting operation in response to the internal command and the internal address information; and
a data storage unit configured to store data in a region designated by the internal address information or output data from a region designated by the internal address information in response to the internal command.
7. The semiconductor apparatus according to claim 6, wherein each of the external address information and the internal address information comprises a start address and an end address of a region to and from which data is to be inputted and outputted.
8. The semiconductor apparatus according to claim 7, wherein the internal address generation block generates the internal addresses by performing a counting operation in response to the internal command, and the internal addresses are generated performing a counting operation from a value of the start address to a value of the end address.
wherein the internal addresses comprise a row-side internal address and a column-side internal address, and
wherein the internal address generation block comprises:
an address counting unit configured to generate a row-side counting address and a column-side counting address by performing a counting operation in response to the internal address information when the internal command is a read command or a write command;
a row-side address processing unit configured to generate the row-side internal address in response to the row-side counting address; and
a column-side address processing unit configured to generate the column-side internal address in response to the column-side counting address.
10. The semiconductor apparatus according to claim 9, wherein the address counting unit generates the column-side counting address by performing a counting operation in response to the internal address information, and generates the row-side counting address by performing a counting operation each time the column-side counting address reaches a maximum value and then becomes a minimum value.
11. An address counting circuit comprising:
a counting control section configured to generate an enable signal, a column start address and a row start address in response to an internal command, internal address information, a first counting signal and a second counting signal;
a column address counting section configured to generate the first counting signal and a row address increase signal in response to the enable signal and the column start address;
a row address counting section configured to generate the second counting signal in response to the row start address and the row address increase signal;
a column address buffer configured to buffer the first counting signal and output a column-side counting address; and
a row address buffer configured to buffer the second counting signal and output a row-side counting address.
12. The address counting circuit according to claim 11,
wherein the internal address information comprises a start address and an end address, and
wherein the counting control section enables the enable signal when the internal command is a read command or a write command, outputs the row start address and the column start address in response to the start address, and disables the enable signal by comparing the end address and the first and second counting signals.
13. The address counting circuit according to claim 12, wherein the counting control section is configured to disable the enable signal when the end address is identical to the first and second counting signals.
14. The address counting circuit according to claim 12, wherein the counting control section comprises:
a decoding part configured to decode the internal command, enable the enable signal when the internal command is a read command or a write command, generate first and second storage enable signals, and disable the enable signal when a counting end signal is enabled;
a first address storage part configured to store the start address and the end address when the first storage enable signal is enabled, and output the stored start address and end address as the is column start address and the column end address;
a second address storage part configured to store the start address and the end address when the second storage enable signal is enabled, and output the stored start address and end address as the row start address and the row end address; and
a comparison part configured to enable the counting end signal when the first counting signal and the column end address are the same with each other and the second counting signal and the row end address are the same with each other.
15. The address counting circuit according to claim 11, wherein the column address counting section sets the first counting signal to the same value as the column start address when the enable signal is enabled, generates the set first counting signal by performing a counting operation, and enables the row address increase signal in the case where the first counting signal reaches a maximum value and then becomes a minimum value.
16. The address counting circuit according to claim 15, wherein the row address counting section sets the second counting signal to the same value as the row start address, and increases a counting value of the set second counting signal each time the row address increase signal is enabled.
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