Source: http://www.google.com/patents/US7287235?dq=3984803
Timestamp: 2017-12-15 05:43:24
Document Index: 170894798

Matched Legal Cases: ['art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2', 'art 1', 'art 2']

Patent US7287235 - Method of simplifying a circuit for equivalence checking - Google Patents
A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, it is converted to a fixed delay circuit...http://www.google.com/patents/US7287235?utm_source=gb-gplus-sharePatent US7287235 - Method of simplifying a circuit for equivalence checking
Publication number US7287235 B1
Application number US 10/912,985
Publication number 10912985, 912985, US 7287235 B1, US 7287235B1, US-B1-7287235, US7287235 B1, US7287235B1
Inventors Gagan Hasteer, Deepak Goyal
Original Assignee Calypto Design Systems, Inc.
Patent Citations (25), Referenced by (9), Classifications (11), Legal Events (6)
US 7287235 B1
A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, it is converted to a fixed delay circuit by using additional circuitry to obtain a fixed delay circuit. If the fixed delay circuit is a logic circuit that performs multiple cycle computations, it is converted to a logic circuit that performs the same computation in a single cycle. Circuit acceleration includes concatenating multiple copies of the fixed delay circuit. After performing circuit acceleration on all sub-circuits in the fixed delay circuit, a combined accelerated circuit is obtained. Thereafter, redundant flip-flops are identified and removed from the combined accelerated circuit and the combined accelerated circuit is optimized.
The present invention relates to the field of computer-aided design of integrated circuits and, in particular, to testing the equivalence of digital logic circuits.
There are many equivalence checking techniques and tools for equivalence checking in combinational circuits. The research paper titled ‘Equivalence Checking Using Cuts and Heaps’, by Andreas Kuehlmann and Florian Krohm, Proceedings of the 34th annual ACM IEEE conference on Design automation, pages: 263-268, describes one such approach. Another technique is described in research paper titled ‘Combinational Equivalence Checking through Function Transformation’, by Hee Hwan Kwak, InHo Moon, James H. Kukula and Thomas R. Shiple, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pages: 526-533. Examples of software tools used for combinational equivalence checking are Conformal LEC from Cadence Design Systems; Formality® from Synopsys, Inc; and FormalPro from Mentor Graphics.
There are many techniques in the art for performing the mapping of storage elements. One such technique has been described in U.S. Pat. No. 6,496,955, titled ‘Latch Mapper’ assigned to Sun Microsystems, Inc., Santa Clara, Calif. Another technique is mentioned in U.S. Pat. No. 6,247,163, titled ‘Method and System of Latch Mapping for Combinational Equivalence Checking’, assigned to Cadence Design Systems, Inc., San Jose, Calif. However, these techniques are not failsafe and may fail in complex sequential circuits, which involve a large number of storage (or memory) elements. Further, in some commercially available tools, there is the requirement of one-to-one latch mapping between the two circuits being compared. In these tools, the correspondence between the storage elements must be provided by the user of the tool.
An object of the invention is to simplify and optimize a logic circuit for enabling circuit equivalence checking.
FIG. 1 is a flowchart illustrating the steps of the invention, according to an exemplary embodiment of the invention;
FIG. 7 is a block diagram showing a fixed delay circuit achieved after using additional blocks—a Handshake module and an Output Module, in a variable delay circuit;
FIG. 9 illustrates a fixed delay circuit for multiplying three numbers achieved after using additional blocks—the handshake module and the output module.
For the sake of convenience, terms that have been used to describe the various embodiments are defined below. It is to be noted that these definitions are provided merely to aid the understanding of the description, and are in no way to be construed as limiting the scope of the invention.
The term “Logic Circuit” signifies a digital circuit with one or more inputs and outputs, which can include one or more logic gates and sequential circuit elements. The logic circuit can be modeled in a computer system using a hardware description language such as Verilog HDL or VHSIC Hardware Description Language (VHDL). VHSIC is an acronym for Very High-Speed Integrated Circuits. These hardware description languages can be used to model a logic circuit at many levels of abstraction ranging from the algorithmic level to the gate level.
The term ‘Register Transfer Level’ or RTL signifies a high level description of a logic circuit. RTL is used to describe the registers of a computer or digital electronic system using variables and data operators, and the way in which data is transferred between them. For example, in the RTL, a simple digital circuit performing an AND operation may be described as “OUT=a&b,” where “&” represents the AND operation between the variables a and b, and OUT represents the output of the digital circuit.
The term “Throughput” is defined as the rate at which a logic circuit produces a particular valid output. For example, if a particular output in a logic circuit produces a valid output every 2 clock cycles, it is said to have a throughput of 0.5.
The term “System Level Representation” signifies a high level representation of a logic circuit showing the essential functional components required for the working of the logic circuit.
The term ‘Register Transfer Level Representation’ or ‘RTL Representation’ signifies a representation of a logic circuit using registers (storage elements) and logic gates/elements.
The term “Output Cone” signifies a sub-circuit responsible for generating a particular output, where the output is input to a register or is a primary output.
The term “Fixed Delay Circuit” signifies a logic circuit in which valid outputs have a constant throughput.
The term “Variable Delay Circuit” signifies a logic circuit in which the throughput is not constant and depends on the inputs.
The term “Circuit Acceleration” signifies a circuit transform for converting a logic circuit that performs a desired functionality in multiple clock cycles to a logic circuit that performs the functionality in a single clock cycle.
The term “Constant Valued Flip-flops” signifies the flip-flops in a logic circuit that do not change their values in any of the clock cycles.
The term “multiple cycle logic circuit” or “multi cycle logic circuit” refers to a logic circuit that provides an output in multiple clock cycles.
The term “single cycle logic circuit” refers to a logic circuit that provides an output in a single clock cycle.
The present invention provides a method of simplifying a circuit for equivalence checking. In general, two or more logic circuits can be used to implement the same functionality. The logic circuit implementations may differ as far as the number and type of circuit elements and the number of cycles for the generation of a valid output are concerned. Further, the use of a different number of flip-flops and different throughputs make cycle-by-cycle equivalence checking difficult to perform. Therefore, it is essential to simplify any two logic circuits, which are to be compared, so that they have the same throughput, thereby making equivalence checking easier. The simplification of a logic circuit should, therefore, achieve two aims—removing redundant flip-flops from the logic circuit and increasing the throughput of the resulting circuit to one.
The present invention achieves circuit simplification by first performing circuit acceleration (or acceleration) on the logic circuits to be compared, and then removing those flip-flops that have a constant value during the operation of the accelerated logic circuit. The circuit acceleration can be performed by combining multiple ‘copies’ of the combinational portion of the same circuit in series. Once the logic circuit has been accelerated, the constant valued flip-flops are identified and removed in the accelerated circuit. Thereafter, the logic circuit can be simplified by using known techniques such as dead code elimination. Afterwards, the logic circuit can be compared for cycle-by-cycle equivalence checking, using techniques known in the art.
STEP 1: Initialize a RESET list that includes the flip-flops with known reset values in the accelerated logic circuit;
STEP 2: Start all flip-flops in the accelerated logic circuit. The flip-flops in the reset list start with their reset values, and the other flip-flops are treated as free variables;
STEP 3: Compute the next state equations of these flip-flops. Check if these equations simplify to their reset values;
STEP 4: Identify a subset of flip-flops in the RESET list, which do not reach reset values;
STEP 5: If this subset is empty then GO TO STEP 7;
STEP 6: Remove the flip-flops (belonging to the subset) from the RESET list, and GO TO STEP 2; and
STEP 7: The remaining flip-flops in the RESET list are constant valued flip-flops.
At step 112, all the constant valued flip-flops in the combined accelerated circuit are removed. The process of removing the constant valued flip-flops leaves some hanging wires in the circuit (that is, some unconnected wires). These hanging wires are removed and the circuit is optimized at step 114 using known techniques such as constant propagation and dead code elimination. Constant propagation is a technique that checks whether the supply of constant inputs results in constant outputs. Dead code elimination is a technique of identifying and removing open ended wires from a circuit.
FIG. 2 a is a system-level representation of a logic circuit for adding three numbers. The inputs to a three-number adder 202 are three N-bit numbers ‘a’, ‘b’ and ‘c’. Adder 204 is an N-bit adder that can result in a maximum of (N+1) bit output. The numbers ‘a’ and ‘b’ are inputs to adder 204. The result of this computation is then input to adder 206, which is an (N+1) bit adder plus a carry. Adder 206 adds the number ‘c’ and output of adder 204. As is apparent, this is a generalized scheme for any logic circuit adding three numbers. However, the RTL implementation can be done in several ways. Each of these implementations can involve a different number of sequential and combinational circuit elements. The invention aims to enable circuit equivalence checking between any two such implementations.
FIG. 2 b is a Register Transfer Level (RTL) representation of a possible logic circuit for adding three numbers. This RTL implementation performs the addition of three N-bit numbers, ‘a’, ‘b’ and ‘c’, in two clock cycles. First multiplexer 208 and second multiplexer 210 are N bit, two-to-one multiplexers that choose one of the two inputs, and pass it to the output, depending on the value of the select signal ‘Count’. ‘Count’ is generated by means of a one-bit counter 212. One-bit counter 212 is implemented by using a delay flip-flop 214 followed by a NOT gate 216, as shown in FIG. 2 b. When ‘Count’ is 0, the input corresponding to 0 is chosen as the output by first multiplexer 208 and second multiplexer 210; and when ‘Count’ is 1, the input corresponding to 1 is chosen as the output by first multiplexer 208 and second multiplexer 210. Adder 218 adds the outputs of first multiplexer 208 and second multiplexer 210. The output of adder 218 is stored in a register 220 that is of the same number of bits as adder 218. The working of the logic circuit in FIG. 2 b is described hereinafter.
First, all memory storage elements, that is, delay flip-flop 214 and register 220 are initialized to zero. Thereafter, one-bit counter 212 starts counting. The values of the numbers ‘a’, ‘b’ and ‘c’ are supplied at the inputs. When the value of ‘Count’ is 0, adder 218 performs the addition of ‘a’ and ‘c’ and the sum is stored in register 220. In the next clock cycle, the value of ‘Count’ is 1. Now, the input number ‘b’ and the value stored in register 220 are passed as inputs to adder 218. The result of this computation, which is the sum of all three numbers ‘a’, ‘b’ and ‘c’, is available as a valid output. This computation takes two clock cycles. Therefore, the throughput of this logic circuit is one valid output per two clock cycles. This logic circuit can be accelerated by concatenating two copies of the logic circuit together.
FIG. 3 illustrates an accelerated logic circuit derived from the RTL implementation of logic circuit for adding the three numbers shown in FIG. 2 b. Accelerated logic circuit 301 has a throughput of one valid output per clock cycle. Accelerated logic circuit 301 is divided into two parts—Part 1 and Part 2. The outputs of Part 1 are inputs to Part 2. The working of accelerated logic circuit 301 is described hereinafter.
First, all memory storage elements, that is, delay flip-flop 214 and register 220 are initialized to zero. Thereafter, one-bit counter 212 starts counting. The values of the numbers ‘a1’, ‘b1’ and ‘c1’ are supplied at the inputs of Part 1. Similarly, the values of the numbers ‘a2’, ‘b2’ and ‘c2’ are supplied at the inputs of Part 2. The values of ‘a1’, ‘b1’, and ‘c1’ are equal to ‘a2’, ‘b2’, and ‘c2’ respectively. When the value of ‘Count1’ is 0, adder 218 performs the addition of ‘a1’ and ‘c1’ and the sum is transferred to next multiplexer 208. Further, ‘Count2’ is 1. Therefore, multiplexer 208 in Part 2 selects the output of adder 218 in Part 1 and ‘b2’. The result of this computation is stored in register 220 and is also available at the output of Part 2. Therefore, compared to the logic circuit described in FIG. 2 b, accelerated logic circuit 301 computes the addition of three numbers in a single cycle.
There are two flip-flops, flip-flops 214 and 220, in accelerated circuit 301. Initializing these flip-flops to their reset states, the next states of these flip-flops are calculated. One may note that the value of delay flip-flop 214 always remains zero due to the action of invertors 216. On the other hand, the value of flip-flop 220 changes from reset value to the state equation a1+b2+c1. Hence, the delay flip-flop is a constant valued flip-flop, and can be removed from the circuit. This is shown in FIG. 4 a.
Optimization of Circuit:
Since delay flip-flop 214 has a constant value, first multiplexer 208 and second multiplexer 210 in Part 1 always select the input corresponding to 0. Similarly, first multiplexer 208 and second multiplexer 210 in Part 2 always select the input corresponding to 1. Therefore, first multiplexer 208 and second multiplexer 210 in Part 1 and Part 2 can be removed, while retaining only relevant components in the accelerated logic circuit. This is shown in FIG. 4 b. At the same time, register 220 is redundant since the value it stores is never used. Therefore, register 220 can also be removed. This is shown in FIG. 4 b.
After removing all the redundant components, there are hanging wires in the logic circuit, as shown in FIG. 4 b. The hanging wires are wires that are not connected to circuit elements on both ends. These can be removed by using standard circuit optimization techniques such as dead code elimination. After performing circuit optimization, using known techniques such as dead code elimination, a simplified logic circuit, as depicted in FIG. 4 c is obtained. This logic circuit does not involve any redundant flip-flops and can be used by standard equivalence checkers to check circuit equivalence.
FIG. 5 illustrates a system-level representation of a logic circuit that multiplies three numbers. A three-input multiplier 502 multiplies three numbers, ‘a’, ‘b’ and ‘c’, the inputs being N-bit numbers. Three-input multiplier 502 comprises an N-bit by N-bit multiplier, multiplier 504 and a 2N-bit by N-bit multiplier (multiplier 506) that results in an output of maximum size 3N. In three-input multiplier 502, the numbers ‘a’ and ‘b’ are multiplied first by multiplier 504, and the product is multiplied by ‘c’ to get the product of the numbers ‘a’, ‘b’ and ‘c’. As is apparent, this is a generalized scheme for any logic circuit multiplying three numbers. However, the RTL implementation for the same logic circuit can be carried out in several ways. Each of these implementations can involve a different number of sequential and combinational circuit elements.
FIG. 6 illustrates a possible Register Transfer Level (RTL) representation of a variable delay logic circuit that multiplies three numbers. A three-input multiplier 602 multiplies three numbers, ‘a’, ‘b’ and ‘c’, the inputs being N-bit numbers. Logic block 604 is a logic circuit whose output is 1 if the input number equals 0, and the output is 0 otherwise. The output of all logic blocks 604 is input to a three-input OR gate 606. The output of three-input OR gate 606 is labeled ‘Zero’. ‘Zero’ is 1 if any of the inputs is 0, and 0 otherwise. A multiplexer 608 is a 3N bit, two-to-one multiplexer that chooses one of the two inputs and passes it to the output depending on the value of the select signal ‘Zero’. The output of multiplexer 608 corresponding to 1 is a zero. The output of multiplexer 608 corresponding to 0 is the output of a multiplier 610. Therefore, when ‘Zero’ is 1, multiplexer 608 selects the input corresponding to 1, that is, the output ‘Op’ is a zero, as it should be. Further, ‘Zero’ is an input to a two-input OR gate 612, the output of which is a handshake signal, represented by ‘HS’. The other input is ‘Count’, which is generated by one-bit counter 212. The value of ‘HS’ equal to 1 implies that the computation is complete and the value of ‘Op’ is a valid output. The value of ‘HS’ equal to 0 implies that the computation is not complete and the output ‘Op’ may not be valid. Therefore, when at least one of the inputs is zero, the actual multiplication does not need to be performed and a valid output is available at ‘Op’ in one cycle only.
In the case where none of the inputs is zero, the value of ‘Zero’ is 0. The numbers ‘a’ and ‘b’ are input to a 2N bit multiplier, multiplier 614. The result of the computation performed by multiplier 614 is stored in register 612. In the next clock cycle, multiplier 610 performs multiplication of the value stored in register 612 and ‘c’. In the second clock cycle, the value of ‘Count’ is 1 and the ‘HS’ signal becomes 1. Further, the value of ‘Zero’ is 0, therefore, multiplexer 608 selects the input corresponding to value 0, that is, the output of multiplier 610. Therefore, the value of ‘Op’ is now the valid product of the three input numbers. In this case, the computation is performed in two clock cycles. As is seen from the two cases given above, three-input multiplier 602 is a variable delay circuit whose throughput depends on the values of the inputs.
FIG. 7 is a block diagram showing a fixed delay circuit achieved after using additional blocks—a handshake module and an output module, in a variable delay circuit 702. Variable delay circuit 702 is any variable delay circuit whose throughput depends on the values of one or more of its inputs. The outputs of variable delay circuit 702 are a handshake signal represented by ‘HS’ and the result of the computation represented by ‘Op’. It should be noted here that variable delay circuit 702 is shown to have only a single output ‘Op’. In general, there can be one or more outputs. And the method described below is then performed for each of the outputs taken separately. The handshake signal ‘HS’ is input to a handshake module 704. Outputs of handshake module 704 are an accelerated handshake signal represented by ‘HSacc’ and a control signal represented by ‘Ctrl’. The output signal ‘Op’ and control signal ‘Ctrl’ are inputs to an output module 706. The output of output module 706 is an accelerated output signal ‘Opacc’. ‘HSacc’ has value 1 if the value of the accelerated output signal ‘Opacc’ is a valid output and 0 otherwise. Exemplary implementations of handshake module 704 and output module 706 are described below.
FIG. 8 a illustrates an exemplary implementation of handshake module 704 according to an embodiment of the invention. ‘HS’ is input to a two-input AND gate 708 and a two-input OR gate 710. The output of two-input OR gate 710 is HSacc. Further, the output of two-input OR gate 710 is input to a 1-bit register, register 712. Output of register 712 is represented by ‘Pout’. ‘Pout’ is input to two-input OR gate 710 and a NOT gate 714. The output of NOT gate 714 is the second input to two-input AND gate 708. The output of two-input AND gate 708 is the ‘Ctrl’ signal. In addition to this, a ‘Clear’ signal is generated to make register 712 reset to 0. ‘Clear’ is generated by a two-input OR gate 716, the inputs to which are an ‘Rst’ signal and a ‘Cout’ signal. Logic block 604 generates ‘Cout’ with ‘Cin’ as input. When ‘Cin’ is zero, ‘Cout’ is 1 and 0 otherwise. A counter 718 generates ‘Cin’. Counter 718 counts from 0 to (Lmax−1) where Lmax is the maximum number of cycles taken by variable delay circuit 702 to produce a valid output.
FIG. 8 b illustrates an exemplary implementation of output module 706 according to an embodiment of the invention. ‘Op’ is input to a two-to-one multiplexer, multiplexer 720, corresponding to the case when ‘Ctrl’ is 1. The output of multiplexer 720 is the accelerated output ‘Opacc’, which is also stored in a register of suitable size, register 722. Register 722 also forms an input to multiplexer 720 corresponding to the case when ‘Ctrl’ is 0.
FIG. 9 illustrates a fixed delay circuit for multiplying three numbers achieved after using additional blocks—handshake module 704 and output module 706 in three-input multiplier 602. Due to space constraints, three-input multiplier 602 is shown in FIG. 9 as a block diagram. The details and labels used in this description are the same as those provided in conjunction with FIG. 6. The functioning of fixed delay multiplier 902 determined, as in FIG. 9, is discussed now.
As discussed previously in conjunction with FIG. 6, three-input multiplier 602 produces a valid output ‘Op’ in a single clock cycle when one or more of the three inputs is zero. Otherwise, a valid output is produced in two cycles. With the use of additional circuitry as described in FIG. 7 and FIG. 8, fixed delay multiplier 902 has a valid output at ‘Opacc’ after every two clock cycles. In addition to this, the inputs are held for two clock cycles before the next set of inputs can be applied. In this case, counter 718 counts till 2 (that is, 0 and 1 alternately). Further, it should be noted that the reset signal to all flip-flops takes precedence over other signals. That is, whenever reset signals ‘Rst’, ‘Zero’ and ‘Clear’ are 1, the corresponding flip-flop or register is reset to 0. The working of three-input multiplier 602 with the values of different signals in different clock cycles is described in the following table.
Clock Reset Zero Op Count HS HSacc Ctrl Opacc Cout Clear Pout
T = −1 1 X X X x X x x x 1 x
T = 0 0 1 0 0 1 1 1 0 0 0 0
T = 1 0 1 0 0 1 1 0 0 1 1 1
T = 2 0 0 0 0 0 0 0 0 0 0 0
T = 3 0 0 M 1 1 1 1 M 1 0
Table 1 illustrates the working of three-input multiplier 602 for five clock cycles, with the first clock showing the initial state of three-input multiplier 602. The symbol ‘x’ denotes a ‘don't care’ state—that is, the value of the signal can be a 0, 1 or unknown.
For clock cycle T=−1, ‘Reset’ and ‘Clear’ are 1, thereby resetting delay flip-flop 214 and register 712. For clock cycle T=0, ‘Reset’ and ‘Clear’ are 0, that is, disabled. Further, this is the case when one or more of the inputs ‘a’, ‘b’ and ‘c’ are zero. Therefore, ‘Zero’ is 1 for T=0 and T=1. In this case, for clock cycle T=0 itself, ‘HSacc’ is 1. This implies that the output available at ‘Opacc’ is a valid output. As is evident, ‘Opacc’ is 0, which is the correct output. Also, after two clock cycles, that is, at T=1, ‘Opacc’ is 0. Therefore, a valid output is available at the end of two clock cycles.
At clock cycle T=2, the inputs to three-input multiplier 602 are changed so that none of the inputs is zero. At clock cycle T=3, it should be noted that ‘HSacc’ is 1, which implies that ‘Opacc’ is a valid output. Further, the value Of ‘Opacc’ is M, which is the product of the three input numbers. Again, in this case, a valid output is available at the end of two clock cycles. Therefore, three-input multiplier 602 behaves like a fixed delay circuit, giving a valid output every two clock cycles.
The method and system described above to convert variable delay circuit 702 to a fixed delay circuit can be performed, in general, for logic circuits with any throughput. The mathematical description for the same is given below. The same can also be derived from FIG. 8 a and FIG. 8 b.
For variable delay circuit 702 producing a valid output in a maximum of Lmax cycles, the following analysis holds:
HS acc(n)=HS acc(n−1)|HS(n)=HS(0)|HS(1)| . . . HS(n) (1)
HS(n), HSacc(n) and Ctrl(n) are the values of ‘HS’ and ‘HSacc’ and ‘Ctrl’ signals respectively, at the (n+1)th clock cycle; and ‘n’ is an integer such that 0≦n≦Lmax; and
the operator ‘|’ denotes logical OR operation.
Ctrl(n)=˜HS acc(n−1)&HS(n)=˜HS(0)&˜HS(1)& . . . ˜HS(n−1)&HS(n) (2)
HS(n), HSacc(n) and Ctrl(n) are the values of ‘HS’ and ‘HSacc’ and ‘Ctrl’ signals respectively, at the (n+1)th clock cycle; and ‘n’ is an integer such that 0≦n≦Lmax;
the operator ‘˜’ denotes logical NOT operation; and
the operator ‘&’ denotes logical AND operation.
Op acc(n)=Ctrl(n)?Op(n):Op acc(n−1)=Ctrl(n)?Op(n):(Ctrl(n−1)?Op(n−1): ( . . . (Ctrl(0)?Op(0):F int) . . . )) (3)
the logic Opacc(n)=Ctrl(n)?Op(n):Opacc(n−1) implies that Opacc(n) gets the value Op(n) if Ctrl(n) is 1 and the value Opacc(n−1) if Ctrl(n) is 0; and
Finit is the initial value stored in register 718.
If (Tautology(Ctrl(n)|Ctrl(n−1)| . . . Ctrl(0)==1)) then Opacc(n) as obtained in equation 3 does not depend on Finit. (5)
Equations 1, 2 and 5 imply that if (Tautology(HSacc(n)==1)) then an error is flagged stating Finit is unreachable. (6)
Opacc(n) such that Tautology(HSacc(n)==1) represents the accelerated data value Op for all possible completions of the transaction. (7)
Once a variable delay circuit is converted to a fixed delay circuit, the steps of circuit acceleration, removal of redundant flip-flops, circuit optimization, and so on, can be performed. These steps are as discussed in conjunction with FIG. 1.
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U.S. Classification 716/107, 327/280, 327/161, 703/15, 327/158
International Classification H03L7/06, G06F17/50, H03H11/26, H03L7/00
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