Source: http://www.google.com/patents/US8017305?dq=6948823
Timestamp: 2017-09-24 09:01:36
Document Index: 294367255

Matched Legal Cases: ['Application No. 2004', 'art 53', 'art 54', 'arts 53', 'arts 53', 'arts 23', 'art 23', 'art 24', 'arts 23', 'art 23', 'art 24', 'art 15', 'art 15', 'art 15', 'art 16', 'art 16', 'art 16', 'arts 53', 'art 18', 'art 18', 'art 18', 'arts 53', 'art 18', 'art 17', 'art 17', 'art 17', 'art 17']

Patent US8017305 - Pattern forming method, semiconductor device manufacturing method and ... - Google Patents
First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process...http://www.google.com/patents/US8017305?utm_source=gb-gplus-sharePatent US8017305 - Pattern forming method, semiconductor device manufacturing method and exposure mask set
Publication number US8017305 B2
Application number US 12/652,470
Also published as CN1790167A, CN100565347C, US7459265, US7670756, US20060088792, US20090075187, US20100104983
Publication number 12652470, 652470, US 8017305 B2, US 8017305B2, US-B2-8017305, US8017305 B2, US8017305B2
Inventors Takeo Ishibashi, Takayuki Saito, Maya Itoh, Shuji Nakao
US 8017305 B2
First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.
performing a first exposure process with a first exposure mask on said first region of said resist, said first exposure mask having a repetition pattern in which a line and space are repeated alternately;
performing a second exposure process with a second exposure mask on said second region of said resist, said second exposure mask having a standard pattern that is a pattern excluding said repetition pattern, said standard pattern partially including a connection pattern continuous with said repetition pattern; and
This application is a Continuation of U.S. Ser. No. 12/271,567, filed Nov. 14, 2008, which is a Continuation of and claims benefit of priority from U.S. Ser. No. 11/255,877, filed Oct. 24, 2005, which claims benefit of priority from Japanese Patent Application No. 2004-312076, filed Oct. 27, 2004. The entire contents of each of the above-listed applications are incorporated herein by reference.
R=k1·(λ/NA) (1)
It is now assumed that a resist pattern for a fine circuit pattern that includes a grating pattern having a process factor k1 of less than “0.3”, and a standard pattern having an arbitrary pattern such as fine isolated space and a process factor k1 of “0.5” level, is subjected to patterning. It may be required in some instances that a grating pattern and standard pattern be connected in such resist pattern.
In the conventional techniques described above, it is difficult to resolve this fine circuit pattern with stability no matter how optimized the shape of illumination is. For example, setting the NA to “0.85” with the ArF wavelength (193 nm), the grating pattern of 65 nm L/S will have a process factor k1 of “0.28”. In this case, it was extremely difficult even with a phase shift mask technique having a process factor k1 of less than “0.3” to form the fine circuit pattern with high accuracy that includes the fine grating pattern and the arbitrary standard pattern having a process factor k1 of “0.5” level.
It is an object of this invention to provide a pattern forming method capable of forming a fine circuit pattern including a grating pattern having a process factor k1 of “0.3” or less and a standard pattern having a process factor k1 of “0.5” level with high accuracy.
FIG. 1 illustrates a flow chart for a pattern forming method according to a first preferred embodiment of this invention;
In FIG. 2, line patterns 11 to 14 are arranged in a lattice as the grating pattern 100, and patterns 21 to 24 (21: arbitrary pattern, 22 and 24: pad pattern, 23: wiring pattern) are arranged in arbitrary fashion as the standard pattern 101. The line pattern 12 and wiring pattern 23 are connected, and the line pattern 14 and pad pattern 24 are connected. The “standard pattern” as used in this specification means patterns other than the grating pattern.
Subsequently, at step S2, heat treatment before exposure (soft bake) is performed for about 60 seconds at a temperature of about 110° C., for example.
Then, at step S5, heat treatment after exposure (PEB: Post Exposure Bake) is performed for about 60 seconds at a temperature of about 125° C., for example.
Thereafter, at step S6, a development process is performed to subject the resist to patterning. A 2.38 wt % aqueous solution of tetramethyl ammonium hydroxide may be used as a developer in this process. The result is that the resist is patterned into the desired pattern mentioned above. The development process is followed by heat treatment for dehydration for about 60 seconds at a temperature of about 115° C., for example.
Δ=d1+d2=P·(sin θi+sin θd)=λ (2)
σin ={(λ/P)−NA}/NA (3)
σout=iNA/NA (4)
The result is that the inner sigma σin and outer sigma σout of the openings 32 shown in FIG. 3 are obtained as “0.75” and “0.95”, respectively.
FIG. 6 depicts the structure of an illumination system stop for ⅔ annular illumination used in the second exposure process. As shown, an illumination system stop 38 includes an annular opening 39, with the ratio between an inner diameter R1 from the center to the opening 39 and an outer diameter R2 from the center to the opening 39 being set to 2:3. The use of the illumination system stop 38 thus allows for ⅔ annular illumination. The numerical aperture NA is set to “0.85”. Exposure conditions in the second exposure process including the amount of irradiation and a focus position are respectively optimized.
Accordingly, a resist pattern for a circuit pattern that includes both a grating pattern having a process factor k1 of less than “0.3”, and a standard pattern having a process factor k1 of 0.5 level can be obtained with high accuracy.
The extension region E2 is thus a transmissive region. Imaginary line patterns 11 v to 14 v are indicated by dashed lines in order to clarify the size of the reduced light blocking pattern 56. The edge line LB5 corresponds to edge positions of the imaginary line patterns 11 v to 14 v.
Meanwhile, a light blocking pattern 53 of the HT mask 4 includes the light blocking pattern 53 of the HT mask 2 shown in FIG. 7, and additionally a light blocking pattern extension part 53 c extending toward the (inside of) grating-pattern mask part M1 side in the extension region E1, while a light blocking pattern 54 includes the light blocking pattern 54 of the HT mask 2 shown in FIG. 7, and additionally a light blocking pattern extension part 54 c extending toward the grating-pattern mask part M1 side in the extension region E1. That is, the extension parts 53 c and 54 c of the light blocking patterns 53 and 54 serving as connection patterns of the standard pattern 101 are provided in the extension region E1.
A wiring width LW of the light blocking pattern extension parts 53 c and 54 c is determined as follows: when a line dimension of the grating pattern is set to 65 nm, for example, a simple sum of a overlay tolerance of 15 nm (vertical and horizontal directions in the plane structure shown in FIG. 12) and a dimensional accuracy tolerance of 10 nm (tolerance of finished dimensional deviation) leads to the wiring width LW of 115 nm. The tolerances may be obtained by a simple sum or by a root sum square. The dimensions of wiring with a thickness tolerance as defined herein should not be regarded as design dimensions of a mask, but may be regarded as the dimensions of a resist pattern obtained after exposure and development.
The result is that wiring pattern extension parts 23 c and 24 c are formed extending from a boundary line LB1 between the grating-pattern forming region A1 and the standard-pattern forming region A2 toward the gating-pattern forming region A1 side only by the amount of recession dc1, as shown in FIG. 13. The wiring pattern extension part 23 c connects the wiring pattern 23 and line pattern 12, and the wiring pattern extension part 24 c connects the pad pattern 24 and line pattern 14. Therefore, a pattern equivalent to the FIG. 2 pattern in terms of electrical connection relationship is obtained even in the event of the edge recession phenomenon.
The result is that wiring pattern extension parts 23 c and 24 c are formed extending from the boundary line LB1 toward the gating-pattern forming region A1 side only by the amount of deviation dc2, as shown in FIG. 14. The wiring pattern extension part 23 c connects the wiring pattern 23 and line pattern 12, and the wiring pattern extension part 24 c connects the pad pattern 24 and line pattern 14. Therefore, a pattern equivalent to the FIG. 2 pattern in terms of electrical connection relationship is obtained even in the event of the mask overlay deviation phenomenon in a rightward-slanting direction.
Like the first preferred embodiment, the finally obtained grating pattern by the pattern forming method according to the second preferred embodiment is thinner than a resist pattern immediately after the first exposure process, and vertically deteriorated in resist shape. This is possibly the consequence of being subjected to half-tone transmitted light through the second HT mask 6 used in the second exposure process. As a result, the contrast of a composite optical image of the first mask (during the first exposure process) and the second mask (during the second exposure process) deteriorates, further causing deterioration in line edge roughness (straightness of wiring). Improvements are made to these deteriorations in a third preferred embodiment of this invention.
The triton mask 15, however, differs from the HT mask 1 in including an HT mask part 15 a, which is an incomplete light blocking part, and a complete light blocking part 15 b.
The HT mask part 15 a is formed as a region where the whole light blocking pattern 41 is formed, and extends from a boundary line LB3 between the light blocking patterns 43 and 41 by a shift amount ΔD1 to be formed as part of the light blocking pattern 43 as well.
The triton mask 16, however, differs from the HT mask 4 in including an HT mask part 16 a, which is an incomplete light blocking part, and a complete light blocking part 16 b.
The HT mask part 16 a is formed as a region where the whole light blocking patterns 51 to 54 are formed, and extends from a boundary line LB4 between the reduced light blocking pattern 56 and the light blocking pattern extension parts 53 c, 54 c by a shift amount ΔD2 to be formed as part of the reduced light blocking pattern 56 as well.
The triton mask 18, however, differs from the HT mask 4 in including an HT mask part 18 a, which is an incomplete light blocking part, and a complete light blocking part 18 b.
The complete light blocking part 18 b is formed as a region where the whole reduced light blocking pattern 56 is formed, and extends from the boundary line LB4 between the reduced light blocking pattern 56 and the light blocking pattern extension parts 53 c, 54 c by a shift amount ΔD4 to be formed as parts of the light blocking patterns 53 and 54 as well. That is, the complete light blocking part 18 b is formed as a light blocking pattern of the whole grating-pattern mask part M1 and an adjacent region to the boundary line LB2.
The triton mask 17, however, differs from the HT mask 1 in including an HT mask part 17 a, which is an incomplete light blocking part, and a complete light blocking part 17 b.
The complete light blocking part 17 b is formed as a region where the whole light blocking pattern 43 is formed, and extends from the boundary line LB3 between the light blocking patterns 41 and 43 by a shift amount ΔD3 to be formed as part of the light blocking pattern 41 as well. That is, the complete light blocking part 17 b is formed as a light blocking pattern of the entire standard-pattern mask part M2 and an adjacent region to the boundary line LB2.
Application to First Embodiment
The first to fourth modes described above may be applied to the first preferred embodiment. In such cases, no part of the region EX1 equivalent to the most part of the line patterns 11 to 14 is subjected to light transmission during the second exposure process. This prevents the line patterns 11 to 14 in the region EX1 from being subjected to half-tone transmitted light, and allows the line patterns 11 to 14 to be obtained with high accuracy.
FIG. 30 illustrates a flow chart for an exposure method to be performed on a plurality of wafers according to a fourth preferred embodiment of this invention. A general process is performed in the same fashion as the first preferred embodiment illustrated in FIG. 1, except that this method is performed on a plurality of wafers (predetermined substrate of each wafer) and that the steps S3 and S4 are performed as shown in FIG. 30.
US6351304 Jun 1, 2000 Feb 26, 2002 Canon Kabushiki Kaisha Multiple exposure method
US6930754 Jun 28, 1999 Aug 16, 2005 Canon Kabushiki Kaisha Multiple exposure method
US7279257 Jan 30, 2004 Oct 9, 2007 Sharp Kabushiki Kaisha Pattern forming method, method of manufacturing thin film transistor substrate, method of manufacturing liquid crystal display and exposure mask
US7670756 * Nov 14, 2008 Mar 2, 2010 Renesas Technology Corp. Pattern forming method, semiconductor device manufacturing method and exposure mask set
US20040197680 May 12, 2004 Oct 7, 2004 Numerical Technologies, Inc. Phase shifting circuit manufacture method and apparatus
JP2000021718A Title not available
JP2001110719A Title not available
JP2003158183A Title not available
JP2004226898A Title not available
JP2004304094A Title not available
JPH04273245A Title not available
WO1999065066A1 Jun 2, 1999 Dec 16, 1999 Nikon Corporation Transfer method and aligner
International Classification G03F7/26, G03F1/68, H01L21/027, G03F1/32, G03F1/70