Source: https://patents.google.com/patent/US8806298
Timestamp: 2018-02-25 21:06:56
Document Index: 10051537

Matched Legal Cases: ['Application No. 2008', 'Application No. 07799113', 'Application No. 200710129013', 'Application No. 07799113', 'Application No. 96123239', 'Application No. 200710129013', 'Application No. 200710129013']

US8806298B2 - Reliability, availability, and serviceability in a memory device - Google Patents
US8806298B2
US8806298B2 US12824298 US82429810A US8806298B2 US 8806298 B2 US8806298 B2 US 8806298B2 US 12824298 US12824298 US 12824298 US 82429810 A US82429810 A US 82429810A US 8806298 B2 US8806298 B2 US 8806298B2
US20100262889A1 (en )
This application is a continuation of and claims the priority of U.S. patent application Ser. No. 11/479,067 filed Jun. 30, 2006 now U.S. Pat. No. 7,774,684.
a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits (stored ECC bits) corresponding to the data bits, the memory core comprising at least one split bank pair that has the first portion in a first memory bank and the second portion a second memory bank, wherein, in error check mode, data bits are stored in the first memory bank and corresponding error check bits are stored in the second memory bank, the memory core to support either error check mode or non-error check mode in response to a register bit; and
2. The memory device of claim 1, wherein the error correction logic further comprises:
3. The memory device of claim 2, wherein the error correction logic further comprises:
6. The memory device of claim 1, wherein the memory device comprises a dynamic random access memory (DRAM) device.
7. The memory device of claim 1, wherein the memory device further comprises:
reading data bits from a first portion of a memory core, the memory core comprising at least one split bank pair that has the first portion in a first memory bank and the second portion a second memory bank;
reading stored error correction code (ECC) bits from a second portion of the memory core, wherein, in error check mode, data bits are stored in the first memory bank and corresponding error check bits are stored in the second memory bank, the memory core to support either error check mode or non-error check mode in response to a register bit;
12. The method of claim 11, wherein sending the CRC bits and the data bits to the requester comprises:
a split bank pair of memory banks including a first memory bank and a second memory bank, wherein data bits are to be stored in the first memory bank and corresponding error correction code (ECC) bits (stored ECC bits) are to be stored in the second memory bank, if the DRAM device is in an error check mode, the DRAM device to support either error check mode or non-error check mode in response to a register bit, and
15. The system of claim 14, wherein the error correction logic further comprises:
16. The system of claim 15, wherein the error correction logic further comprises:
17. The system of claim 14, wherein the error correction logic further comprises:
18. The system of claim 14, wherein error correction logic further comprises:
19. The system of claim 14, wherein the DRAM device further includes:
US20100262889A1 true US20100262889A1 (en) 2010-10-14
US8806298B2 true US8806298B2 (en) 2014-08-12
US20050172177A1 (en) 2004-01-19 2005-08-04 Kohei Oikawa Semiconductor memory device for correcting errors using ECC (error correcting code) circuit
US20060053361A1 (en) 2004-09-06 2006-03-09 Hyung-Gon Kim Memory devices with error detection using read/write comparisons
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