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Patent US5774684 - Integrated circuit with multiple functions sharing multiple internal signal ... - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsAn integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions:...http://www.google.com/patents/US5774684?utm_source=gb-gplus-sharePatent US5774684 - Integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitrationAdvanced Patent SearchPublication numberUS5774684 APublication typeGrantApplication numberUS 08/730,996Publication dateJun 30, 1998Filing dateOct 8, 1996Priority dateMay 26, 1995Fee statusPaidAlso published asDE69633166D1, DE69633166T2, EP0776504A2, EP0776504B1, EP1343076A2, EP1343076A3, US5857094, WO1996037854A2, WO1996037854A3Publication number08730996, 730996, US 5774684 A, US 5774684A, US-A-5774684, US5774684 A, US5774684AInventorsJames Andrew Colgan, Robert James Divivier, John R. Gunther, Ralph Warren Haines, Daniel R. Herrington, Brian J. Marley, William V. Miller, Dan Craig O'Neill, Jianhua Helen Pang, Alexander Perez, Stephen C. Pries, Michael J. Shay, Kent B. Waterson, David S. WeinmanOriginal AssigneeNational Semiconductor CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (21), Non-Patent Citations (30), Referenced by (40), Classifications (10), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetIntegrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitrationUS 5774684 AAbstract An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions. Maximum performance is thereby achieved from the circuit functions accessed most frequently, while still achieving high performance from those circuit functions accessed less frequently. The IC may provided with a processor core with features that support In-Circuit Emulation (ICE).
What is claimed is: 1. An apparatus including an integrated circuit (IC) with a plurality of circuit functions and a plurality of signal buses, said IC comprising:a first signal bus for communicating a first plurality of bus signals within said IC; a second signal bus for communicating a second plurality of bus signals within said IC; a third signal bus for coupling to an external circuit and communicating a third plurality of bus signals between said IC and said external circuit; a plurality of master controllers, coupled to said first signal bus, for selectively accessing said first signal bus and controlling said communicating of said first plurality of bus signals; a first plurality of peripheral circuits, coupled to said first, second and third signal buses, for selectively communicating with said plurality of master controllers via said first signal bus and said first plurality of bus signals, selectively accessing said second signal bus and controlling said communicating of said second plurality of bus signals, and selectively accessing said third signal bus and controlling said communicating of said third plurality of bus signals; and a second plurality of peripheral circuits, coupled to said second signal bus, for selectively communicating with said first plurality of peripheral circuits via said second signal bus and said second plurality of bus signals. 2. The apparatus of claim 1, wherein said first signal bus comprises a synchronous signal bus.
3. The apparatus of claim 1, wherein said second signal bus comprises an asynchronous signal bus.
4. The apparatus of claim 1, wherein said third signal bus comprises an asynchronous signal bus.
5. The apparatus of claim 1, wherein said plurality of master controllers is further for communicating with one another and in accordance therewith determining which one thereof gains access to said first signal bus and control of said communicating of said first plurality of bus signals.
6. The apparatus of claim 1, wherein said plurality of master controllers includes a central processing unit (CPU) and a direct memory access (DMA) controller.
7. The apparatus of claim 1, wherein said first plurality of peripheral circuits is for communicating with one another and in accordance therewith determining which one thereof gains access to said second signal bus and control of said communicating of said second plurality of bus signals.
8. The apparatus of claim 1, wherein said first plurality of peripheral circuits is for communicating with one another and in accordance therewith determining which one thereof gains access to said third signal bus and control of said communicating of said third plurality of bus signals.
9. The apparatus of claim 1, wherein said first plurality of peripheral circuits includes a dynamic random access memory (DRAM) controller and a bus interface unit (BIU).
10. The apparatus of claim 1, wherein said second plurality of peripheral circuits includes a PCMCIA controller.
11. The apparatus of claim 1, wherein said second plurality of peripheral circuits is further for coupling to and communicating with a plurality of other circuits external to said IC.
12. An apparatus including an integrated circuit (IC) with a plurality of circuit functions interconnected by and sharing a plurality of signal buses according to distributed bus access and control arbitration, said IC comprising:a plurality of signal buses for communicating a plurality of bus signals; a plurality of master controllers, coupled to a first portion of said plurality of signal buses, for communicating with one another and in accordance therewith determining which one thereof becomes a bus master having access to and control of a first one of said plurality of signal buses and in accordance therewith controlling communication of a first portion of said plurality of bus signals; a first plurality of peripheral circuits, coupled to said first portion and a second portion of said plurality of signal buses, for communicating with one another and in accordance therewith determining which one thereof communicates with said bus master and gains access to and control of a second one of said plurality of signal buses and in accordance therewith communicating with said bus master and controlling communication of a second portion of said plurality of bus signals; and a second plurality of peripheral circuits, coupled to a third portion of said plurality of signal buses, for communicating with one another and in accordance therewith determining which one thereof gains access to a third one of said plurality of signal buses and in accordance therewith communicating a third portion of said plurality of bus signals. 13. The apparatus of claim 12, wherein one of said plurality of signal buses comprises a synchronous signal bus.
14. The apparatus of claim 12, wherein one of said plurality of signal buses comprises an asynchronous signal bus.
15. The apparatus of claim 12, wherein said plurality of master controllers includes a central processing unit (CPU) and a direct memory access (DMA) controller.
16. The apparatus of claim 12, wherein said first plurality of peripheral circuits includes a dynamic random access memory (DRAM) controller and a bus interface unit (BIU).
17. The apparatus of claim 12, wherein said second plurality of peripheral circuits includes a PCMCIA controller.
18. The apparatus of claim 12, wherein said second plurality of peripheral circuits is further for coupling to and communicating with a plurality of other circuits external to said IC.
19. An apparatus including an integrated circuit (IC) with a plurality of circuit functions interconnected by and sharing a plurality of signal buses according to distributed bus access and control arbitration, said IC comprising:a plurality of signal buses for communicating a plurality of bus signals; a plurality of master controllers, coupled to a first portion of said plurality of signal buses, for communicating with one another and in accordance therewith determining which one thereof becomes a bus master having access to and control of a first one of said plurality of signal buses and in accordance therewith controlling communication of a first portion of said plurality of bus signals; a first plurality of peripheral circuits, coupled to said first portion and a second portion of said plurality of signal buses, for communicating with one another and in accordance therewith determining which one thereof communicates with said bus master and gains access to and control of a second one of said plurality of signal buses and in accordance therewith communicating with said bus master and controlling communication of a second portion of said plurality of bus signals; a second plurality of peripheral circuits, coupled to a third portion of said plurality of signal buses, for communicating with one another and in accordance therewith determining which one thereof gains access to a third one of said plurality of signal buses and in accordance therewith communicating a third portion of said plurality of bus signals; and wherein one of said second portion of said plurality of signal buses is for coupling to an external circuit and communicating therewith via a plurality of external bus signals, and wherein one of said first plurality of peripheral circuits is further for communicating with one of said second plurality of peripheral circuits and in accordance therewith controlling communication of a fourth portion of said plurality of bus signals and said plurality of external bus signals. Description
This is a divisional of application No. 08/451,503, filed May 26, 1995 now abandoned.
REFERENCE TO MICROFICHE APPENDIX The appendix A submitted with this specification is incorporated by reference. Appendix A is microfiche (five sheets containing a total of 302 frames) containing copyrighted material, Copyright 1995, National Semiconductor Corporation, consisting of a C-language code listing for a CPU design for an integrated circuit in accordance with the following discussion.
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B together show a functional block diagram of an integrated circuit implementing a circuit architecture in accordance with the present invention.
FIG. 2B is a more detailed functional block diagram of the architecture of FIG. 2A as implemented in the integrated circuit of FIGS. 1A and 1B.
FIGS. 3A and 3B together illustrate a flowchart of distributed arbitration among the central processing unit, DMA controller, DRAM controller, bus interface unit and PCMCIA controller of FIGS. 1A and 1B for controlling transactions on the buses in accordance with another embodiment of the present invention.
FIGS. 4A and 4B together show a functional block diagram of the architecture implementation for the central processing unit of the integrated circuit of FIGS. 1A and 1B.
FIG. 5 is a functional block diagram of the logic implementation for the central processing unit of the integrated circuit of FIGS. 1A and 1B.
DETAILED DESCRIPTION OF THE INVENTION Referring to FIGS. 1A and 1B, an IC 10 in which the present invention has been implemented contains a number of functions integrated therein, including a central processing unit (CPU) 12, a direct memory access (DMA) controller 14, a dynamic random access memory (DRAM) controller 16, a bus interface unit (BIU) 18, a PCMCIA controller 20, an ECP parallel port 22 and a liquid crystal display (LCD) controller 24, plus a number of other peripheral circuits as shown. As discussed in more detail below, such functional elements 12, 14, 16, 18, 20, 22, 24 communicate via one or more signal buses 50, 52, 54 amongst themselves and with external functional elements (not shown) which are connected to the external terminals of the IC 10. (Further discussion beyond that which follows immediately below can be found in the various documents which are referenced and incorporated herein by reference at the end of this section.)
Referring to FIG. 2B, for the above-discussed circuit architecture as implemented in the IC 10 of FIGS. 1A and 1B, the first physical (and logical) bus is the multi-master, synchronous, extremely high performance CPU local bus 50. From an architectural point of view the CPU local bus 50 may be driven by any number of bus masters (making this bus a multi-master bus). Before driving the CPU local bus 50 a bus master must first arbitrate for, and gain control of, the CPU local bus 50. In the IC 10 of FIGS. 1A and 1B, there are two bus masters, namely the CPU 12 and the DMA controller 14. The CPU 12 is the default bus master and retains control of the CPU local bus 50 at all times except when the DMA controller 14 requests control, whereupon the CPU 12 grants control of the CPU local bus 50 to the DMA controller 14 at its first reasonable chance, e.g. upon completion of the execution of the present CPU bus transaction sequence. After gaining control of the CPU local bus 50, the DMA controller 14 retains control until such time as it removes its request for continued mastership, whereupon the CPU 12 resumes its control of the CPU local bus 50.
The CPU local bus 50 is synchronous, which means that all signals on the bus are considered to be valid only in reference to the bus's clock signal. In the IC 10 of FIGS. 1A and 1B, all signals are valid only in reference to the rising edge of the clock for the CPU local bus 50. Further, the CPU local bus 50 is considered to operate at an extremely high performance because the bus is capable of performing one access per clock period, which corresponds to the theoretical maximum performance of a synchronous bus.
Both the DRAM controller 16 and the BIU 18 receive a CPU local bus 50 access at the same time and both blocks 16, 18 begin determining the type of cycle and its target. Architecturally, either the DRAM controller 16 or the BIU 18, or both, must make the ultimate determination of which one of the two blocks 16, 18 will perform the access. In the IC 10 of FIGS. 1A and 1B, the DRAM controller 16 either accepts or rejects the cycle. The BIU 18 accepts all cycles rejected by the DRAM controller 16 and rejects all cycles accepted by the DRAM controller 16.
Following each of these access operations 218, 222, 226, 228 the next operation 230 is a decision as to whether the CPU 12 is in control of the CPU local bus 50. If so, the foregoing process is repeated beginning with the operation 202 determining whether a CPU access sequence is progress. If not, the next operation 232 is to determine whether there are more DMA cycles to be run. If so, the system continues, or re-enters, the state 214 in which the CPU local bus 50 is controlled by the DMA controller 14. If not, the next operation 208 is to run an idle cycle on the CPU local bus 50 with the CPU 12 in control.
Referring to FIGS. 4A and 4B, the architecture of the CPU 12 employs a three-stage pipeline using microprogrammed control. The three primary stages of the pipe are the decode 70, execute 72 and writeback 74 stages. The writeback stage 74 is further divided into two substages 74a, 74b. The second substage 74b is only used for some of the memory accesses. For register-to-register operations, only three stages are required. Hence the pipeline functions primarily with these three stages 70, 72, 74.
The prefetch unit 102 consists of two 8-byte registers 102a, 102b (FIGS. 4A and 4B) that are filled in either from the instruction cache 104 or directly from memory. The decode unit 100 gets the instruction from the prefetch unit 102 and consumes them to generate the entry microcode address for the instruction, register addresses, immediate values, displacement values and segment information. The decoder 100 also generates information for some of the exceptions, and is also used to handle the case of the non-implemented instructions, i.e. x86 instructions that are not implemented on the CPU 12.
The execution unit 108 has two major functions. One is to perform all the arithmetic and logic operations. For this function, the execution unit 108 has an arithmetic and logic unit 114 (FIGS. 4A and 4B) and a barrel shifter. The second function is address computation (linear address generation) and limit checking. This unit 108 computes the address offset and linear address and does the limit checking in a single cycle.
TABLE 1__________________________________________________________________________EMULATOR DEDICATED SIGNAL PINSSignal (type)  Description            Type__________________________________________________________________________ICEMODE  If high at the end of Reset, this pin selects ICE                         Input, sampled at rising(input)  operation of the device. While running in ICE Mode,                         edge of PWGOOD signal  this input dynamically selects the performance level:                         for enabling ICE Mode,                         then relative to rising  1 = Aggressive Tracing: an address is guaranteed                         edges of the Clock.  be presented for all branch targets, at a small cost in  performance because the processor must wait on  in-cache branches when the bus is occupied.  0 = Non-Aggressive (Real-Time) Tracing: The  processor runs in real time, without interference, and  NSF does not wait for the bus (if the target is in the  cache). A valid address is therefore not always present  with NSF.  In the standard (non-ICE) package, this pad will be  tied permanently low.  Because the processor core does not have direct access  to the PWGOOD pin, the latched and dynamic values  of ICEMODE will be presented separately to the core.IXSTAT Instruction Execution Status. This signal is presented                         Output, status indication.(output)  at the rising edge of each clock, encoding the actions                         Re-evaluated every rising  being taken by the CPU:                         edge of clock (i.e.: may                         glitch at that time, even if  1 = Execution Complete. An instruction, or an                         value does not change).  Exception microcode sequence, has completed  execution. The NSF status may occur before or  simultaneously with IXSTAT=1, and means that the  exiting instruction is branching. (Exception microcode  sequences always branch.) Otherwise, the instruction  is continuing to the next sequential instruction in  memory, and the number of bytes in the exiting  instruction is signalled by the IXQUAL pins.  0 = Other. Internal status is signalled on the IXQUAL  pins.IXQUAL 3:0!  Instruction Execution Qualifier. These four bits                         Output, status indication.(output)  presented at the rising edge of each clock, and their                         Re-evaluated every rising  meaning differs according to the state of the IXSTAT                         edge of clock (i.e., may  signal:                glitch at that time, even if                         value does not change).  If IXSTAT = 1 in the same clock cycle, these signals  present the length in bytes of the instruction. A value  of 0000 does not currently appear: instructions with a  REPx prefix report IXSTAT = 1 only at the end of  the last iteration. Note that instruction length beyond  15 bytes is considered illegal and will cause an Invalid  Opcode exception.  If IXSTAT = 0, these signals present ICE exception  handling status, as listed below:  Code   Interpretation  0000 No Status To Report (Default)  0001 ICE Exception Is Being TakenNSF (output)  Non-Sequential Fetch. When presented high for one                         Output, status indication.  clock cycle, it indicates that the processor is                         Re-evaluated every rising  performing a branch, interrupt, or anything else                         edge of clock (i.e.: may  changes the instruction flow in a non-sequential                         glitch at that time, even if  manner. In Aggressive Trace mode, the address of                         value does not change).  target is guaranteed to be presented at the next or  concurrent ALS pulse (but if the fetch is from the  cache no data transfer strobe occurs). DMA requests  will never be granted between an NSF = 1 cycle and  its associated ALS pulse.ODD (output)  A "1" on this pin indicates that the address being                         Output, status indication.  accessed is odd. This pin replaces pin SA0 for tracing                         Re-evaluated every rising  purposes, since SA0 is always held at zero during                         edge of clock (i.e.: may  instruction fetches if the cache is enabled.                         glitch at that time, even if                         value does not change).                         Use ALS to latch it.OCP (output)  High means that an on-chip peripheral is being                         Output, decoded from  accessed. The ICD bit in BIU Control Register 1                         address.  (outside the CPU Core) will enable driving of on-chip  peripheral data onto the off-chip bus during on-chip  I/O Read cycles. This signal is provided in order to  allow buffers to be disabled and avoid bus conflicts  when the ICD feature is usedICEMAP This signal goes active whenever an address within                         Output, decoded from(output)  ICE range (80000000-83FFFFFF) is presented. Its                         address.  functional timing will be identical to that of the Chip  Select signals. Do not delete this: without the top 6  address bits, there is no other way to tell.ALS (output)  Address Latch Strobe. Indicates the presence of a                         Output pulse.  valid address on the off-chip address pins.BPREQ  A high level requests an ICE Exception. The pin                         Input level, sampled on(input)  should be kept high until the request is acknowledged.                         rising edges of the clock.  The acknowledgement comes from the ICE monitor  software. If BPREQ is asserted high on exit from  Reset, ICE code is entered instead of Reset code. This  pin always triggers the ICE Exception, regardless of  whether the Debug Registers are in ICE Mode.  However, the device must have been placed in Ice  Mode with the ICEMODE pin, otherwise this input is  entirely disabled.DMA 1:0!  Indicates by a two-bit encoded value which, if any,                         Outputs, combinationally(output)  the three on-chip (otherwise invisible) DMA channels                         following the on-chip  is active.             DACK signals.  Code   Interpretation  00    None  01    LCD Controller  10    ECP Port  11    PCMCIA ControllerVCC (input)  One extra VCC pin.     PowerGND (input)  One extra Ground pin.  PowerThe following three signals encode the traditional '486 three-bit statuscode;these are enumerated in Table 2 below.M/O    One of three bus status indicators:                         Output, status indication.  1 = Memory access, 0 = I/O access  (Will be 1 during fly-by DMA xfers.)D/C    One of three bus status indicators:                         Output, status indication.  1 = Data access, 0 = Control/CodeW/R    One of three bus status indicators:                         Output, status indication.  1 = Write access, 0 = Read access__________________________________________________________________________
TABLE 2______________________________________ENUMERATED BUS STATUS STATESM/IO      D/C    W/R        Type of Bus Event______________________________________0         0      0          Interrupt Acknowledge0         0      1          Halt/Special0         1      0          I/O Read0         1      1          I/O Write1         0      0          Code Read1         0      1          (Not Used)1         1      0          Memory Read1         1      I          Memory Write______________________________________
______________________________________     IM  Bit 12 of Register DR7     BI  Bit 12 of Register DR6______________________________________
The BHE pin follows all addresses, regardless of the locations addressed. This represents no change between ICE Mode and Normal Mode.
The IOR and IOW strobe signals are activated for all 1/0 accesses, internal as well as external.
The ICE Mapped space is also assumed to be 16 bits wide when ICE Mode is enabled. The CS16 signal will be ignored for accesses within this space. During accesses to locations in the ICE Map, the ISA-like memory timing is used. When the device is in ICE Mode, software is able to access a register at IO Address EF5Fh, which is called the ICE Mode Timing Control Register. When the device is not in ICE Mode, this register has no effect and may not be read or written.
______________________________________I.sub.-- CD  Bit 3. ICE Command Delay, this bit determines if a  Command delay is associated with accesses to the ICE  Memory address range (80000000h-83FFFFFFh). Reset  state is "1".I.sub.-- WS2-0  Bits 2-0. ICE Wait State bits 2-0, these bits determine the  number of wait states associated with accesses to the  ICE Memory address range (80000000h-83FFFFFFh). Reset  state is "111" (7 wait states).Reserved  Bits 4-7. Reserved: make no changes to these bits.______________________________________
From the point that the emulator begins to service the ICE Exception to the time that the ICE Monitor program returns program control to User code (RSM, below), neither another ICE Exception nor any Non-Maskable Interrupt (NMI) is recognized. Any NMI request is held pending internally, and is serviced upon exit to Run Mode. Any additional BPREQ requests are to be held pending by off-chip circuitry until a BPREQ Acknowledge (from the ICE monitor) is seen; this also does not occur until the exit to User code.
To get back to Run Mode, the monitor causes the processor to execute an instruction RSM (Opcode OF, AA hex), which causes the CPU's architectural registers and shadow registers to be loaded from the ICE Dump Table. Execution then continues from the point indicated by the restored EIP and CS images. Temporary registers are not restored at all.
The appendices attached hereto contain information about an integrated circuit in which the present invention has been implemented and are incorporated herein by reference. Appendix A is microfiche (five sheets containing a total of 302 frames) containing copyrighted material, Copyright 1995, National Semiconductor Corporation, consisting of a C-language code listing for a CPU design for an integrated circuit in accordance with the foregoing discussion. Appendix B is a preliminary specification and data sheet for such integrated circuit. Appendix C is a preliminary specification for the internal signal bus for the core of such integrated circuit. Appendix D is a preliminary specification for the internal signal bus for the internal peripherals of such integrated circuit. The invention embodiments described herein have been implemented in an integrated circuit which includes a number of additional functions and features which are described in the following co-pending, commonly assigned patent applications, the disclosure of each of which is incorporated herein by reference: U.S. patent application No. 08/451,319 entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING AN EXTERNAL MEMORY FOR GRAY SCALE MODULATION DATA" (atty. docket no. NSC1-2700); U.S. patent application No. 08/451,965, entitled "SERIAL INTERFACE CAPABLE OF OPERATING IN TWO DIFFERENT SERIAL DATA TRANSFER MODES" (atty. docket no. NSC1-62800); U.S. patent application No. 08/453,076, entitled "HIGH PERFORMANCE MULTIFUNCTION DIRECT MEMORY ACCESS (DMA) CONTROLLER" (atty. docket no. NSC1-62900); U.S. patent application No. 08/452,001, entitled "OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING MINIMUM PULSE WIDTH" (atty. docket no. NSC1-63000); U.S. patent application No. 08/451,503 (abandoned), entitled "INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING MULTIPLE INTERNAL SIGNAL BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRATION" (atty. docket no. NSC1-63100); U.S. patent application No. 08/451,924, now U.S. Pat. No. 5,655,139, entitled "EXECUTION UNIT ARCHITECTURE TO SUPPORT x86 INSTRUCTION SET AND x86 SEGMENTED ADDRESSING" (atty. docket no. NSC1-63300); U.S. patent application No. 08/451,444, now U.S. Pat. No. 5,652,718, entitled "BARREL SHIFTER" (atty. docket no. NSC1-63400); U.S. patent application Serial No. 08/451,204, entitled "BIT SEARCHING THROUGH 8, 16, OR 32-BIT OPERANDS USING A 32-BIT DATA PATH" (atty. docket no. NSC1-63500); U.S. patent application No. 08/451,195, entitled "DOUBLE PRECISION (64-BIT) SHIFT OPERATIONS USING A 32-BIT DATA PATH" (atty. docket no. NSC1-63600); U.S. patent application No. 08/451,571, entitled "METHOD FOR PERFORMING SIGNED DIVISION" (atty. docket no. NSC1-63700); U.S. patent application No. 08/452,162, entitled "METHOD FOR PERFORMING ROTATE THROUGH CARRY USING A 32-BIT BARREL SHIFTER AND COUNTER" (atty. docket no. NSC1-63800); U.S. patent application No. 08/451,434, entitled "AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT" (atty. docket no. NSC1-63900); U.S. patent application No. 08/451,535, now U.S. Pat. No. 5,617,543, entitled "NON-ARITHMETICAL CIRCULAR BUFFER CELL AVAILABILITY STATUS INDICATOR CIRCUIT" (atty. docket no. NSC1-64000); U.S. patent application No. 08/445,563, entitled "TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION" (atty. docket no. NSC1-64100); U.S. patent application No. 08/450,153, now U.S. Pat. No. 5,546,353, entitled "PARTITIONED DECODER CIRCUIT FOR LOW POWER OPERATION" (atty. docket no. NSC1-64200); U.S. patent application No. 08/451,495, now U.S. Pat. No. 5,649,147, entitled "CIRCUIT FOR DESIGNATING INSTRUCTION POINTERS FOR USE BY A PROCESSOR DECODER" (atty. docket no. NSC1-64300); U.S. patent application No. 08/451,219, entitled "CIRCUIT FOR GENERATING A DEMAND-BASED GATED CLOCK" (atty. docket no. NSC1-64500); U.S. patent application No. 08/451,214, now U.S. Pat. No. 5,598,112, entitled "INCREMENTOR/DECREMENTOR" (atty. docket no. NSC1-64700); U.S. patent application No. 08/451,150, now U.S. Pat. No. 5,583,453, entitled "A PIPELINED MICROPROCESSOR THAT PIPELINES MEMORY REQUESTS TO AN EXTERNAL MEMORY" (atty. docket no. NSC1-64800); U.S. patent application No. 08/451,198, entitled "CODE BREAKPOINT DECODER" (atty. docket no. NSC1-64900); U.S. patent application No. 08/445,569, entitled "TWO TIER PREFETCH BUFFER STRUCTURE AND METHOD WITH BYPASS" (atty. docket no. NSC1-65000); U.S. patent application No. 08/445,564, entitled "INSTRUCTION LIMIT CHECK FOR MICROPROCESSOR" (atty. docket no. NSC1-65100); U.S. patent application No. 08/452,306 (abandon,154,ed), entitled "A PIPELINED MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE" (atty. docket no. NSC1-65200); U.S. patent application No. 08/452,080, entitled "APPARATUS AND METHOD FOR EFFICIENT COMPUTATION OF A 486� MICROPROCESSOR COMPATIBLE POP INSTRUCTION" (atty. docket no. NSC1-65700); U.S. patent application No. 08/450,154 (abandoned), entitled "APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY" (atty. docket no. NSC1-65800); U.S. patent application No. 08/451,742, entitled "METHOD OF IMPLEMENTING FAST 486�πMICROPROCESSOR COMPATIBLE STRING OPERATION" (atty. docket no. NSC1-65900); U.S. patent application No. 08/452,659, now U.S. Pat. No. 5,659,712, entitled "A PIPELINED MICROPROCESSOR THAT PREVENTS THE CACHE FROM BEING READ WHEN THE CONTENTS OF THE CACHE ARE INVALID" (atty. docket no. NSC1-66000); U.S. patent application No. 08/451,507 (abandoned), entitled "DRAM CONTROLLER THAT REDUCES THE TIME REQUIRED TO PROCESS MEMORY REQUESTS" (atty. docket no. NSC1-66300); U.S. patent application No. 08/451,420, entitled "INTEGRATED PRIMARY BUS AND SECONDARY BUS CONTROLLER WITH REDUCED PIN COUNT" (atty. docket no. NSC1-66400); U.S. patent application No. 08/452,365, now U.S. Pat. No. 5,612,637, entitled "SUPPLY AND INTERFACE CONFIGURABLE INPUT/OUTPUT BUFFER" (atty. docket no. NSC1-66500); U.S. patent application No. 08/451,744, entitled "CLOCK GENERATION CIRCUIT FOR A DISPLAY CONTROLLER HAVING A FINE TUNEABLE FRAME RATE" (atty. docket no. NSC1-66600); U.S. patent application No. 08/451,206, entitled "CONFIGURABLE POWER MANAGEMENT SCHEME" (atty. docket no. NSC1-66700); U.S. patent application No. 08/452,350, entitled "BIDIRECTIONAL PARALLEL SIGNAL INTERFACE" (atty. docket no. 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