Source: http://www.google.com/patents/US5610953?dq=7143430
Timestamp: 2014-03-17 18:10:38
Document Index: 276075514

Matched Legal Cases: ['Application No. 59', 'Application No. 59', 'Application No. 62', 'Application No. 62', 'Application No. 59', 'Application No. 59', 'Application No. 62', 'Application No. 62']

Patent US5610953 - Asynchronous low latency data recovery apparatus and method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA receiver device is provided with a low latency recovery apparatus for recovering serially transmitted digital data. The receiver device operates asynchronously in respect to a transmitting device. The low latency recovery apparatus synchronizes the receiver device in one clock time to support throughput...http://www.google.com/patents/US5610953?utm_source=gb-gplus-sharePatent US5610953 - Asynchronous low latency data recovery apparatus and methodAdvanced Patent SearchPublication numberUS5610953 APublication typeGrantApplication numberUS 08/407,928Publication dateMar 11, 1997Filing dateMar 21, 1995Priority dateFeb 22, 1991Fee statusLapsedPublication number08407928, 407928, US 5610953 A, US 5610953A, US-A-5610953, US5610953 A, US5610953AInventorsRobert Betts, Howard T. OlnowichOriginal AssigneeInternational Business Machines CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (16), Non-Patent Citations (8), Referenced by (21), Classifications (25), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetAsynchronous low latency data recovery apparatus and methodUS 5610953 AAbstract A receiver device is provided with a low latency recovery apparatus for recovering serially transmitted digital data. The receiver device operates asynchronously in respect to a transmitting device. The low latency recovery apparatus synchronizes the receiver device in one clock time to support throughput of high speed transmission messages received from interconnection networks or interface cables. A metastability proof latch is provided. A synchronization method provides individual alignment for each incoming message. There is instantaneous response to back-to-back messages from different sources. Synchronization is accomplished in the receiving device by implementing a clocking system capable of generating N phase-shifted clocks all operating at the same frequency as the incoming data. The N clocks are shifted an approximately equal amount in relation to each other. The data recovery apparatus selects the one of N clocks which is best in synchronization with the incoming serial data and then to receive the message correctly. The apparatus has a two wire interface for serial data and a bracketing control signal. Serial data is synchronized first to the selected clock and then to a local clock. The bracketing control signals when each message recovery is complete and triggers the start of another message recovery in as little as one clock time.
What is claimed is: 1. An apparatus for receiving a data message input to the apparatus parallel data inputs having a synchronization bit and a message portion, the apparatus comprising:receiving means for receiving the data message; a clock generator for generating a plurality of phase shifted clocks; a clock selector coupled to said receiving means and to said clock generator for receiving the synchronization bit and the plurality of clocks, and for selecting and outputting one of the plurality of clocks as a selected clock; a data alignment circuit coupled to both the clock selector and to the receiving means for receiving the message portion and the selected clock, for aligning the message portion with the selected clock directly and unbuffered as it arrives to the apparatus, and for sending the message portion; a synchronization means for generating the selected clock from the parallel data inputs and synchronization bit, stripping the synchronization bit from the data message, and activating the selected clock to data alignment circuit within one clock time of the input of the synchronization bit to the receiving means; and an input circuit coupled to the data alignment circuit for receiving and storing the message portion, and for sending the message portion to an attached receiving device. 2. The apparatus of claim 1 further comprising an error detector coupled to the input circuit for performing error detection upon the message portion stored in the input circuit.
FIELD OF THE INVENTIONS The present invention relates to communication and digital computer input/output systems and their ability to receive asynchronously serial data and provides an apparatus and method for recovering a clock for clocking the serial data in serial data transmission.
BACKGROUND OF THE INVENTIONS In modern digital systems, serial data are transferred between various elements of the system. It is recognized that others have done work in various systems. They have devised multi-mode digital enciphering systems which may be utilized on full duplex and half duplex communication channels as illustrated by U.S. Pat. No. 4,169,212 to Federick A. Kinch, Jr. et al, issued Sep. 25, 1985. Unlike the present application others have developed processor to peripheral interfaces for asynchronous or synchronous applications dealing with parallel data transmission, as illustrated by U.S. Pat. No. 4,785,469, to Sunil Joshi et al, issued Nov. 15, 1988. Variable rate data has been recovered by very complex methods based on patent recognition, as illustrated by U.S. Pat. No. 4,087,681 to John P. Spencer et al, issued May 2, 1978. Similarly complex is U.S. Pat. No. 4,756,010 to Leonard E. Nelson, issued Jul. 5, 1988 wherein a method of recovery was proposed that was intended to work for slower transmission rates where the receiving data contains a clock that is many time faster than the data transmission clock.
SUMMARY OF THE INVENTIONS The inventions herein relate to an apparatus for enabling a receiving device to get in synchronization with an incoming serial data message. It requires only one synchronization bit be added to the beginning of the message, instead of a long preamble--the synchronization bit is transmitted first and is always a logical 1. The hardware required with the system disclosed is a simple set and recovers a clock for the clocking of the serial data with the one synchronization bit which is first transmitted. The apparatus will prove useful in future bus applications for distributed systems, and in other applications.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1A, the locality of the disclosed asynchronous data recovery apparatus 10 (as shown in FIG. 1) is shown in relationship to the overall communication process. Apparatus 10 comprises part of a receiving device 2, said part being used to receive serial data over line 4 under the control of bracketing control signal 3. The signals 3 and 4 connecting the transmitting device 1 to the receiving device 2 are used to send serial data from transmitting device 1 to receiving device 2. The transmitting device 1 and the receiving device 2 can be any electronic equipment or computer input/output devices having a requirement for the transmittal of data from the transmitting device to the receiving device. The present invention resides at the receiving device only and serves as a means of synchronizing and recovering the asynchronous data sent over line 4 from transmitting device 1 to receiving device 2. The bracketing control signal 3 is transmitted simultaneously with data on line 4 and aids in the process of recovering the asynchronous data.
OTHER EMBODIMENTS Other embodiments are possible with the preferred embodiment being shown by FIGS. 1-6. These alternative embodiments may be implemented with use of the principles described with respect to the preferred embodiment. For example, the recovery apparatus can be applied to longer messages and still be much more efficient than existing 8B/10B methods. Referring to FIG. 8 it is possible to resync the serial data at any time by dropping the +VALID line for 5 ns of dead time and then raising it again and prefixing the next data with a sync bit again. The recovery logic will think that this is a new transmission and re-synchronize. The example of FIG. 8 shows a break in a long transmission after 1000 bits of serial data have been transferred and before the subsequent bits (1001 and greater) are transferred. The break and resynchronization is caused by the +VALID signal going inactive. This causes latches 30 to 37 of FIG. 4 to reset when +VALID goes to 0, and then to resynchronize when +VALID returns to a logical 1; thus, removing the reset from latches 30 to 37 and allowing them to become active again. The resynchronization example of FIG. 8 shows the pin-point control provided by the bracketing control signal (+VALID) that permits resynchronization in one clock time (5 ns in the example. Likewise, the pin-point control of the +VALID signal can be used to transfer two different messages, where the first 1000 bits in the example are from a first message, resynchronization occurs, and the bits starting at 1001 are from a second message.
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circuitryUS7936759Dec 6, 2006May 3, 2011Juniper Networks, Inc.Systems and methods for routing data in a network deviceUS8000351Feb 27, 2009Aug 16, 2011Juniper Networks, Inc.Source synchronous link with clock recovery and bit skew alignmentUS8185739 *Jan 9, 2009May 22, 2012Silicon Image, Inc.Method and system for detecting successful authentication of multiple ports in a time-based roving architectureUS8284888Jan 14, 2010Oct 9, 2012Ian KylesFrequency and phase acquisition of a clock and data recovery circuit without an external reference clockWO2003052679A2 *Nov 25, 2002Jun 26, 2003Cuylen MichaelMethod for correcting initial sampling of the serial bit rate of a filter's output signal* Cited by examinerClassifications U.S. Classification375/373, 375/371, 375/369, 327/144International ClassificationG06F1/12, G06F13/00, H04L7/033, H04L7/04, H04L12/18, H03M9/00, H04L12/56, H04Q11/00Cooperative ClassificationH04L7/0338, H04L49/256, H03M9/00, H04L7/044, H04L12/1881, H04L2012/5627, H04Q11/0066, H04L49/3081European ClassificationH04L49/30J, H04L49/25F, H04L7/04B3, H04L7/033E2, H03M9/00Legal EventsDateCodeEventDescriptionApr 28, 2009FPExpired due to failure to pay maintenance feeEffective date: 20090311Mar 11, 2009LAPSLapse for failure to pay maintenance feesSep 15, 2008REMIMaintenance fee reminder mailedJul 12, 2004FPAYFee paymentYear of fee payment: 8Jun 28, 2000FPAYFee paymentYear of fee payment: 4RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google