Source: http://www.google.com/patents/US7756158?dq=5,072,412
Timestamp: 2014-12-29 07:02:24
Document Index: 766950115

Matched Legal Cases: ['art 13', 'art 14', 'art 15', 'art 16', 'art 11', 'art 12', 'art 13', 'art 13', 'art 12', 'art 14', 'art 13', 'art 15', 'art 15', 'art 15', 'art 13', 'art 12', 'art 11', 'art 11', 'art 12', 'art 15', 'art 13', 'art 14', 'art 17', 'art 16', 'art 15', 'art 17', 'art 17', 'art 11', 'art 11', 'art 12', 'art 12', 'art 13', 'art 24', 'art 13', 'art 24', 'art 14', 'art 13', 'art 24', 'art 13', 'art 14', 'art 15', 'art 47', 'art 48', 'art 50', 'art 47', 'art 43', 'art 43', 'art 47', 'art 47', 'art 47', 'art 47', 'art 49', 'art 50', 'art 47', 'art 50', 'art 47', 'art 61', 'art 50', 'art 61', 'art 50', 'art 61', 'art 50', 'art 50', 'art 50', 'art 48', 'art 47', 'art 47', 'art 47', 'art 47', 'art 43', 'art 43', 'art 42', 'art 61', 'art 50', 'art 61', 'art 50', 'art 50', 'art 47', 'art 47', 'art 47', 'art 47', 'art 61', 'art 47', 'art 47', 'art 61', 'art 50', 'art 50', 'art 47', 'art 61', 'art 50', 'art 47']

Patent US7756158 - Radio integrated circuit and radio communication method - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA PHY-equipped radio LSI and a radio communication method capable of transmitting data without fail while maintaining a beacon interval. Using a selector which is switched by a beacon transmission signal output from a beacon register, a data transmission request signal is switched for transmitting data...http://www.google.com/patents/US7756158?utm_source=gb-gplus-sharePatent US7756158 - Radio integrated circuit and radio communication methodAdvanced Patent SearchPublication numberUS7756158 B2Publication typeGrantApplication numberUS 11/299,778Publication dateJul 13, 2010Filing dateDec 13, 2005Priority dateFeb 24, 2005Fee statusLapsedAlso published asCN1825855A, CN1825855B, US20060187961Publication number11299778, 299778, US 7756158 B2, US 7756158B2, US-B2-7756158, US7756158 B2, US7756158B2InventorsAtsuhiro KaiOriginal AssigneeOki Semiconductor Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (14), Non-Patent Citations (4), Referenced by (3), Classifications (5), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetRadio integrated circuit and radio communication methodUS 7756158 B2Abstract A PHY-equipped radio LSI and a radio communication method capable of transmitting data without fail while maintaining a beacon interval. Using a selector which is switched by a beacon transmission signal output from a beacon register, a data transmission request signal is switched for transmitting data from a RAM to a PHY part, and a transfer is started when this signal goes to �1.� In this way, for transmitting beacon data, the beacon data has been previously transferred to the RAM, and the beacon data is transmitted at the time of beacon transmission interval with the PHY part remaining in a transmission state, so that the beacon interval can be maintained. In addition, it is possible to prevent a failure in the transmission of transfer data due to the state of the PHY part.
The present invention relates to a large-scale radio integrated circuit (hereinafter called the �radio LSI�) which includes an interface (hereinafter called the �I/F�), conforming to IEEE (the Institute of Electric and Electronic Engineers) 802.15.4, with a physical layer (hereinafter called the �PHY�) and a data link layer including a media access control layer (hereinafter called the �MAC�) higher than the physical layer, and employs ZigBee (a trademark of ZigBee Alliance), which is one of near field radio communication standards included in radio communication standards, which divides a 2.4-GHz frequency band, the same as a radio LAN (Local Area Network) standard IEEE 802.11b, into 16 channels for utilization, and to a radio communication method, particularly, a transmission data control therefor.
The protocol configuration of ZigBee employs a PHY 1 of IEEE 802.15.4 which is an international standard of WL-PAN (Wireless Personal Area Network), and a data link layer which includes a MAC 2 and a logical link control layer (hereinafter called the �LLC�), and a network layer 3 and an application I/F layer 4, higher than the layers 1, 2, are standardized in accordance with ZigBee. The application I/F layer 4 is overlaid by an application layer 5 which can be arbitrarily defined by a customer.
The MAC 2 defines a beacon (BEACON) mode for performing intermittent operations and bandwidth guaranteed communications, and a non-beacon mode for making direct communications mutually among all nodes. The beacon mode is used in a star network which is centered at a network management node called the �PAN (Personal Area Network) coordinator.� The PAN coordinator periodically transmits a beacon signal, while other nodes make communications within durations assigned thereto in synchronism with the beacon signal. One node assigned by the coordinator can solely occupy a channel to make communications without collisions, and is utilized for communications for which a low latency is required. On the other hand, the non-beacon mode is a mode for accessing channels at all times in accordance with CSMA-CA. When the non-beacon mode is used in a mesh link which directly communicates with peripheral nodes, each node can directly make a communication at all times, but must be waiting for reception such that it can receive data destined thereto at all times, so that the power cannot be saved by intermittent operations as in the beacon mode.
For example, when ZigBee data is transmitted/received between two communication devices 10-1, 10-2 at a radio frequency (RF) of 2.4 GHz, each communication device 10-1, 10-2 comprises a radio transmission/reception part (hereinafter called the �RF part�) 11; a modem part (MODEM) 12 for making modulation and demodulation; a PHY part 13; a PHY I/F part 14; a MAC part 15; a MAC I/F part 16; a network layer part (NETWORK) 17; an application I/F part (APPLICATION I/F) 18; an application layer part (APPLICATION) 19; and the like.
The RF part 11 is a transceiver which makes transmission/reception through an antenna at RF 2.4 GHz defined by the PHY 1 of IEEE 802.15.4. The modem part 12 modulates or demodulates data communicated with the PHY part 13 in accordance with modulation/demodulation circuit regulations defined in the PHY 1 of IEEE 802.15.4. The PHY part 13 outputs IQ data to the modem part 12 during transmission, and acquires demodulated data during reception in accordance with a data format defined in the PHY 1 of IEEE 802.15.4. The PHY I/F part 14 transmits/receives data between the PHY part 13 and MAC part 15 using a serial I/F such as a synchronous communication I/F (hereinafter called the �SCI�).
The MAC part 15 handles all MAC commands in the MAC 2 of IEEE 802.15.4. Transmission data is transferred from the MAC part 15 to the PHY part 13, modulated by the modem part 12, and transmitted from the RF part 11 and antenna. Reception data received by the antenna and RF part 11 is demodulated by the modem part 12, analyzed by the MAC part 15 through the PHY part 13 and PHY I/F part 14, and transferred to a higher rank device (network layer part 17). The MAC I/F part 16 transmits/receives data between the MAC part 15 and the network layer part 17 using a serial I/F such as SCI. The network layer part 17 transmits/receives data to/from a central processing part (hereinafter called the �CPU�) in a host using a serial I/F.
The PHY-equipped radio LSI 10B is a chip for serially communicating signals with a host 30 through SCI or the like, and has an RF part 11 connected to an antenna 21. The RF part 11 is connected to a modem part 12 through a serial transfer signal line, and the modem part 12 is connected to a PHY part 13 through a serial transfer signal line. The radio LSI 10B is also provided with a random access memory (hereinafter called the �RAM�) 22 for storing transmission data and the like; a bus 23 for parallelly transferring signals; a security part 24; a register, not shown; and the like. The RAM 22 is connected to the PHY part 13, security part 24, and PHY I/F part 14 through the parallel transfer bus 23, the PHY part 13 and security part 24 are interconnected through a parallel transfer signal line, and the PHY part 13 and PHY I/F part 14 are interconnected through a parallel transfer signal line.
The host 30, installed outside, comprises a MAC part 15, a CPU 31 for executing a network layer 3, an application layer 5 and the like in software, and the like, and D/A converts internal digital signals (D) to analog signals (A) which are output from the host 30, D/A converts analog signals (A) from the outside to digital signals (D) which are captured into the host 30, and performs a variety of input/output (hereinafter called �I/O�) operations and the like.
SUMMARY OF THE INVENTION However, the conventional PHY-equipped radio LSI 10B and radio communication method has the following problems.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a communication layer model diagram showing the protocol configuration of ZigBee used in near field radio communications;
DETAILED DESCRIPTION OF THE EMBODIMENTS Configuration of First Embodiment FIGS. 5A, 5B are diagrams generally showing the configuration of a PHY-equipped radio LSI according to a first embodiment of the present invention, where FIG. 5A is a general functional block diagram, and FIG. 5B is a diagram showing the configuration of a switching circuit provided in a wrapper in FIG. 5A.
The PHY part 47 connected to the wrapper 46 is also connected to the security part 48 and PHY I/F part 50 through parallel transfer signal lines. The PHY part 47 has functions of temporarily saving transmission data in an internal buffer, and then converts the temporarily saved transmission data to IQ data (converted data) in accordance with a data format defined by the PHY 1 of IEEE 802.15.4, outputting the IQ data to the modem part 43, capturing reception data (demodulated data) from the modem part 43 for temporary storage in its internal buffer, outputting a PHY transmission state transition signal S47 which takes logical �1� or �0� representing a current state such as a transmission state, a reception state (RX_ON), a stop state (TRX_OFF), and an internal buffer full state, and the like. The internal buffer of the PHY part 47 temporarily holds transfer data, and when untransferred data is present therein (i.e., in the full state), newly incoming transfer data cannot be captured into the PHY part 47. The Buffer_full state arises when new data is transferred before data within the internal buffer has been completely transferred when a plurality of data are transmitted in succession in a data transmission (for example, when 127 bytes or more of data is divided and transmitted in succession). By indicating the Buffer_full state to the outside, the transfer of new data into the internal buffer is limited to prevent corruption of data in the internal buffer. The PHY part 47 contains a time measuring part (for example, a timer) 47 a. The timer 47 a outputs a pulsed beacon interval BI signal S47 a through an internal interrupt or the like at the time the beacon interval BI expires. The timer 47 a may be disposed external to the PHY part 47.
The register part 49 controls a transfer method and the like (for example, stores a set value for switching data transfer paths, an adjusting value for data transmission/reception timings different from one circuit component to another, parameters necessary for the AES processing, and the like), and has an internal beacon register 49 a which is a beacon flag. The beacon register 49 a is a register which outputs a beacon transmission signal S49 a which is set, for example, to logical �0� by the host 60 when normal transmission data, sent from the host 60, is transmitted, and to �1� when beacon data (for example, a variable-length data having a maximum length of 127 bytes), sent from the host 60, is transmitted, and is cleared by a data transmission completion signal S46 d. The PHY I/F part 50 transmits/receives data between the PHY 1 and MAC 2 shown in FIG. 2 using a serial I/F such as SCI, which is driven by a serial transfer clock CK, and outputs a pulsed RAM data transmission request signal S50 at the time transmission data from the host 60 has been stored in the RAM 44 through the bus 45.
The switching circuit comprises a first latch circuit (for example, a detector circuit including a flip-flop (hereinafter called the �FF�) or the like) 46 a for detecting and holding the PHY transmission state transition signal S47 at �1� or �0� output from the PHY part 47; a second latch circuit (for example, a detector circuit including an FF or the like) 46 b for detecting and holding the pulsed beacon interval BI signal S47 a output from the timer 47 a; a third latch circuit (for example, a detector circuit including an FF or the like) 46 c for detecting and holding a pulsed RAM data transmission request signal S50 output from the PHY I/F part 50; and a clear circuit (for example, a data transmission completion signal generator circuit) 46 d for generating a pulsed data transmission completion signal S46 d which indicates that the wrapper 46 has completed a transfer of transmission data to the PHY part 47.
Each detector circuit 46 b, 46 c is provided with a reset terminal R, and is cleared by the data transmission completion signal S46 d which is input to the reset terminal R. A logical circuit (for example, a three-input, one-output AND gate) 46 e is connected to output terminals of the detector circuits 46 a, 46 b, 46 c, and has an output terminal connected, for example, to a �1� side input terminal of a selecting part (for example, a two-input, one-output selector) 46 f. The selector 46 f has a �0� side input terminal connected to the output terminal of the detector circuit 46 c. The selector 46 f selects the �1� side input terminal when the beacon transmission signal S49 a output from the beacon register 49 a is, for example, �1,� and selects an output signal of the AND gate 46 e which is output as the data transmission request signal S46 f. The selector 46 f selects the �0� side input terminal when the beacon transmission signal S49 a is �0,� and selects an output signal of the detector circuit 46 c which is output as the data transmission request signal S46 f. Radio Communication Method in First Embodiment A radio communication method in the radio LSI 40 shown in FIG. 1 will be described separately for (1) transmission of normal data, (2) transmission of beacon data, and (3) data reception.
During a normal data transmission, the beacon register 49 a is set to �1� from the external MAC part 61 through the PHY I/F part 50, and this beacon transmission signal S49 a set at �1� causes the input terminal of the selector 46 f to switch to the �0� side. A data transmission command (PD_DATA.request) is sent from the external MAC part 61 to the PHY I/F part 50 of the radio LSI 40 in synchronism with a serial transfer clock CK, and transmission data from the external MAC part 61 is parallelly transferred to the RAM 44 through the PHY I/F part 50 and bus 45 and stored therein. As the transmission data is stored in the RAM 44 from the PHY I/F part 50, the PHY I/F part 50 outputs the pulsed RAM data transmission request signal S50 which is applied to the wrapper 46.
In the wrapper 46, the RAM data transmission request signal S50 is detected by and held in the detector circuit 46 c which outputs a signal at �H� level which is selected by the selector 46. Then, the selector 46 outputs the data transmission request signal S46 at �H� level. The wrapper 46 reads data stored in the RAM 44 in response to the data transmission request signal S46 in accordance with a data transfer path set by the register 49. The read data is encrypted in the security part 48, and then parallelly transferred to the PHY part 47. Otherwise, the data in the RAM 44 is parallelly transferred to the PHY part 47. As the data in the RAM 44 is transferred to the PHY part 47, the pulsed data transmission completion signal S46 d is output from the data transmission completion signal generator circuit 46 d to clear the detector circuit 46 c. The PHY part 47, when in a transmission state, temporarily holds the read data received thereby in an internal buffer, converts the data to data in the ZigBee format, and serially transfers the converted data to the modem part 43. The modem part 43 modulates the data to generate transmission data which is serially transferred to the RF part 42, and is transmitted from the antenna 41.
During a beacon data transmission, the beacon register 49 a is set to �1� from the external MAC part 61 through the PHY I/F part 50, and this beacon transmission signal S49 a set at �1� causes the selector 46 f to switch the input terminal to the �1� side. Beacon data sent from the external MAC part 61 is parallelly transferred from the PHY I/F part 50 to the RAM 44 through the bus 45, and stored in the RAM 44. As the beacon data is stored in the RAM 44, the PHY I/F part 50 outputs the pulsed RAM data transmission request signal S50 which is applied to the wrapper 46.
In the wrapper 46, the pulsed RAM data transmission request signal S50 is detected by and held in the detector circuit 46 c which outputs a signal at �H� level and applies this signal to the AND gate 46 e. As the beacon interval BI expires, causing the pulsed beacon interval BI signal S47 to be output from the timer 47 a through an internal interrupt, and the PHY transmission state transition signal S47 to transition to �H� level, indicating that the PHY part 47 is in a transmission state, the beacon interval BI signal S47 a is detected by and held in the detector circuit 46 b. The detector circuit 46 b outputs a signal at �H� level which is applied to the AND gate 46 e. The PHY transmission state transition signal S47 at �H� level is detected by and held in the detector circuit 46 a. The detector circuit 46 a outputs a signal at �H� level which is applied to the AND gate 46 e. This causes the AND gate 46 e to output a signal at �H� level, which is selected by the selector 46 f, to output the data transmission request signal S46 f at �H� level.
To solve the foregoing problem, the first embodiment provides a circuit configuration which completes the transmission of beacon data without fail at the time the beacon interval BI arrives. Specifically, by setting the beacon register 49 a to �1,� the RAM data transmission request signal S50 goes to �H� level at the time the beacon data is stored in the RAM 44, but the selector 46 f is prevented from outputting the data transmission request signal S46 f at �H� level until the beacon interval BI signal S47 a and PHY transmission state transition signal S47 go to �H� level.
Effects of First Embodiment The first embodiment has the following effects (A)-(C).
(A) The first embodiment employs the selector 46 f which is switched by the beacon transmission signal S49 a output from the beacon register 49 a, to switch the data transmission request signal S46 f for transmitting data from the RAM 44 to the PHY part 47, such that a transfer is started at the time the data transmission request signal S46 f goes to �1.� In this way, for transmitting the beacon data, the beacon data has been previously transferred to the RAM 44, such that the beacon data is transmitted during the beacon transmission interval BI and when the PHY part 47 is in the transmission state, thus making it possible to maintain the beacon interval BI, and moreover prevent a failure in the transmission of transfer data due to the state of the PHY part 47. Afterward, the beacon register 49 a is cleared to �0� by the data transmission completion signal S46 d upon completion of the transmission of the beacon data, and the selector 46 f is switched to the �0� side, so that data can be subsequently transmitted in a normal state.
FIG. 7 shows an example in which a first data period (for example, a super-frame duration) SD is set to 15.36 millisec, and the beacon interval BI is set to 30.72 millisec in the super-frame structure. H4 in the figure represents a section in which data is transferred with the beacon register 49 b set to �1.�
The storage of the beacon data in the RAM 44 can be supported by doing so at the start of a second data period (for example, Inactive) of the super-frame structure. However, the beacon interval BI may be set to the same value as the super-frame duration SD. In this event, another interrupt is generated by the timer 47 a before the interrupt triggered by the beacon interval BI time, and a notification is made in response to this interrupt that it is the time the beacon setting is required. The external MAC part 61 sets the beacon transmission signal to �H� level in response to the interrupt, and stores the beacon data in the RAM 44, thereby supporting the storage of the beacon data.
In the absence of the beacon register 49 a and selector 46 f as those in the first embodiment, during the transmission of the beacon data, the AND gate 46 e outputs the data transmission request signal (S46 f) at �H� level at the time all the output signals of the detector circuits 46 a, 46 b, 46 c go to �H� level, and the beacon data stored in the RAM 44 is transferred to the PHY part 47. Since the transfer section H12 is delayed from the transfer section H2 in FIG. 6, the time H13 required from the beacon interval signal to the completion of the data transfer to the PHY part 47 is longer than the time H3 in FIG. 6.
After the start of Inactive in the super-frame structure, the beacon interval BI signal is output, followed by the transmission of the beacon data from the MAC part 61, storage of the beacon data in the RAM 44 through the PHY I/F part 50, and the data transmission request signal (Sf46 f) at �H� level output from the AND gate 46 e. In this section from the output of the beacon interval BI signal to the output of the data transmission request signal (S46 f), a time lag occurs due to the PHY I/F part 50 which operates with the serial transfer clock CK (for example, approximately 2 millisec with a 500-KHz clock). As the data transmission request signal (S46 f) at �H� level is output, the beacon data stored in the RAM 44 is parallelly transferred to the PHY part 47. Therefore, the actual beacon interval BI is approximately 3 millisec, resulting in a shift of the interval by 2 millisec or longer.
On the other hand, in the first embodiment, the RAM data transmission request signal S50 is output at the start of Inactive, and the beacon data is transmitted from the MAC part 61, and stored in the RAM 44 through the PHY I/F part 50, as shown in FIG. 7. Subsequently, the beacon interval BI signal is output, the data transmission request signal S46 f at �H� level is output from the selector 46 f, and the beacon data stored in the RAM 44 is parallelly transferred to the PHY part 47. This transfer time is approximately several μsec because it is a parallel transfer internal to the LSI. Thus, the actual beacon interval BI is approximately 30.72 millisec, and a shift in the beacon interval BI is small enough, as compared with FIG. 9, to fall within an allowable range. In this way, data can be communicated while the beacon interval BI is maintained.
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Oct. 2004, vol. 71, No. 4, pp. 24-29 and 70-73.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8224272 *Dec 5, 2007Jul 17, 2012Marvell International Ltd.System for signal metric based receive selectionUS8483634 *Jul 16, 2012Jul 9, 2013Marvell International Ltd.System for signal metric based receive selectionUS20110142028 *Dec 10, 2009Jun 16, 2011Nokia CorporationSynchronization via additional beacon transmission* Cited by examinerClassifications U.S. Classification370/469, 370/352International ClassificationH04J3/22Cooperative ClassificationH04L63/0428European ClassificationH04L63/04BLegal EventsDateCodeEventDescriptionSep 2, 2014FPExpired due to failure to pay maintenance feeEffective date: 20140713Jul 13, 2014LAPSLapse for failure to pay maintenance feesMar 21, 2014ASAssignmentFree format text: CHANGE OF NAME;ASSIGNOR:OKI SEMICONDUCTOR CO., LTD;REEL/FRAME:032495/0483Effective date: 20111003Owner name: LAPIS SEMICONDUCTOR CO., LTD., JAPANFeb 21, 2014REMIMaintenance fee reminder mailedJan 16, 2009ASAssignmentOwner name: OKI SEMICONDUCTOR CO., LTD., JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022162/0586Effective date: 20081001Owner name: OKI SEMICONDUCTOR CO., LTD.,JAPANFree format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100216;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100225;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100302;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100316;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100323;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100330;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100406;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100504;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100511;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;US-ASSIGNMENT DATABASE UPDATED:20100525;REEL/FRAME:22162/586Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:22162/586RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google