Source: https://patents.google.com/patent/US8842786B2/en
Timestamp: 2019-04-23 03:40:09
Document Index: 618303461

Matched Legal Cases: ['Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60', 'Application No. 60']

US8842786B2 - Methods for managing alignment and latency in interference suppression - Google Patents
Methods for managing alignment and latency in interference suppression Download PDF
US8842786B2
US8842786B2 US13/314,787 US201113314787A US8842786B2 US 8842786 B2 US8842786 B2 US 8842786B2 US 201113314787 A US201113314787 A US 201113314787A US 8842786 B2 US8842786 B2 US 8842786B2
US13/314,787
US20120195360A1 (en
2002-09-20 Priority to US10/247,836 priority Critical patent/US7158559B2/en
2005-04-11 Priority to US11/103,138 priority patent/US7359465B2/en
2006-09-19 Priority to US84559406P priority
2006-09-19 Priority to US84559506P priority
2006-09-21 Priority to US84621306P priority
2007-09-19 Priority to US11/858,074 priority patent/US8085889B1/en
2011-12-08 Priority to US13/314,787 priority patent/US8842786B2/en
2011-12-08 Application filed by III Holdings 1 LLC filed Critical III Holdings 1 LLC
2012-08-02 Publication of US20120195360A1 publication Critical patent/US20120195360A1/en
2014-04-09 Assigned to III HOLDINGS 1, LLC reassignment III HOLDINGS 1, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RAMBUS INC.
2014-09-23 Publication of US8842786B2 publication Critical patent/US8842786B2/en
This application is a continuation of U.S. patent application Ser. No. 11/858,074, entitled “Methods for managing alignment and latency in interference cancellation,” and filed Sep. 19, 2007, now U.S. Pat. No. 8,085,889; which (1) claims priority to U.S. Patent Application No. 60/845,594, entitled “Calculation of constant processing latency in a system with two locked clocks,” and filed on Sep. 19, 2006; (2) claims priority to U.S. Patent Application No. 60/845,595, entitled “Latency and Clock Frequency Reduction Using Data Reuse in Interference Cancellation for Coded Systems,” and filed Sep. 19, 2006; (3) claims priority to U.S. Patent Application No. 60/846,213, entitled “Real Time Implementation Techniques for Interference Cancellation,” and filed Sep. 21, 2006; and (4) is a continuation-in-part of U.S. patent application Ser. No. 11/103,138, entitled “Serial cancellation receiver design for a coded signal processing engine,” and filed on Apr. 11, 2005, now U.S. Pat. No. 7,359,465, which is a divisional of U.S. patent application Ser. No. 10/247,836, entitled “Serial cancellation receiver design for a coded signal processing engine,” and filed on Sep. 20, 2002, now U.S. Pat. No. 7,158,559, which claims priority to U.S. Patent Application No. 60/348,106, entitled “Serial Receiver Design for a Coded Signal Processing Engine,” and filed Jan. 14, 2002. The entirety of each of the foregoing patents, patent applications, and patent application publications is incorporated by reference herein.
This application also incorporates by reference in their entirety U.S. Patent Application No. 60/354,093, entitled “A Parallel CSPE Based Receiver for Communication Signal Processing,” and filed Feb. 5, 2002; U.S. Patent Application No. 60/333,143, entitled “Method and Apparatus to Compute the Geolocation of a Communication Device Using Orthogonal Projection Methods,” and filed Nov. 27, 2001; U.S. Patent Application No. 60/331,480, entitled “Construction of an Interference Matrix for a Coded Signal Processing Engine,” and filed Nov. 16, 2001; U.S. Patent Application No. 60/326,199, entitled “Interference Cancellation in a Signal,” and filed Oct. 2, 2001; U.S. Provisional Patent Application No. 60/325,215, entitled “An Apparatus for Implementing Projections in Signal Processing Applications,” and filed Sep. 28, 2001; U.S. patent application Ser. No. 09/988,218, entitled “Interference Cancellation In a Signal,” and filed Nov. 19, 2001, now U.S. Pat. No. 6,711,219; U.S. Patent Application No. 60/251,432, entitled “Architecture for Acquiring, Tracking and Demodulating Pseudorandom Coded Signals in the Presence of Interference,” and filed Dec. 4, 2000; U.S. patent application Ser. No. 09/988,219, entitled “A Method and Apparatus for Implementing Projections in Signal Processing Applications,” and filed Nov. 19, 2001, now U.S. Pat. No. 6,856,945; U.S. patent application Ser. No. 09/612,602, entitled “Rake receiver for spread spectrum signal demodulation,” and filed Jul. 7, 2000, now U.S. Pat. No. 6,430,216; and U.S. patent application Ser. No. 09/137,183, entitled “Printed circuit board socket,” and filed Aug. 20, 1998, now U.S. Pat. No. 5,928,035.
In a multipath environment, received signals are superpositions of time-delayed and complex-scaled versions of the transmitted signals. Multipath can cause several types of interference. Intra-channel interference occurs when the multipath time-delays cause sub channels to leak into other subchannels. For example, in a forward link, subchannels that are orthogonal at the transmitter may not be orthogonal at the receiver. When multiple base stations (or sectors or cells) are active, there may also be inter-channel interference caused by unwanted signals received from other base stations. Each of these types of interference can degrade communications by causing a receiver to incorrectly decode received transmissions, thus increasing a receiver's error floor. Interference may also have other deleterious effects on communications. For example, interference may lower capacity in a communication system, decrease the region of coverage, and/or decrease maximum data rates. For these reasons, a reduction in interference can improve reception of selected signals while addressing the aforementioned limitations due to interference.
In view of the foregoing background, embodiments of the present invention may provide a generalized interference-canceling receiver for canceling intra-channel and interchannel interference in transmissions that propagate through frequency-selective communication channels.
Interference Cancellation systems comprise two major functions: estimating the interference and then removing the estimated interference. The interference experienced by a given signal path or ray is attributed to multi-paths from the same sector and paths from other sectors. The propagation time for the various multipaths from the transmitter to the receiver varies based on signal reflections from objects such as buildings, trees, etc. Different sectors might not be synchronized to each other, either because of different propagation times from the respective sectors, or because the sectors are deployed asynchronously, as is possible in some systems such as WCDMA and HSPDA. In effect, the signal paths arriving at the receiver can often be misaligned to each other's timing.
If interference estimation and removal is performed on a per path basis, alignment may be performed simply by adjusting the removal boundary to be the symbol boundary of the path being removed. Interference estimation and removal where multiple paths from a sector are involved, and where multiple asynchronous sectors are involved presents a more complicated situation of alignment. In such techniques, multiple paths from a single sector are combined either using some form of Rake combining such as Maximal Ratio Combining (MRC) or equalization. The equalization may be performed using an LMMSE equalizer or a Decision feedback Equalizer (DFE). The input per sector to an interference estimator is aligned to the sector's transmitter timing indicated by its symbol boundaries.
A symbol boundary marks the chip location in a received signal or a despread chip sequence from which point chips may be collected for a decovering (or de-Walshing) operation to be performed and yield valid symbol estimates. Symbol boundaries are well known in the art, and are the boundary locations in a transmitted or received chip sequence, which marks the beginning and end of the transmission of a symbol. In some systems, such as CDMA2000 and HSPDA, multiple symbol lengths are supported, in which case the symbol boundary refers to the boundary of any of the supported symbols.
Multiple paths from a sector may be combined to form a single data stream input to the symbol estimator. The combination of multiple paths may be performed either using some form of Maximal Ratio Combining (MRC) or using equalization. In Rake based combining or MRC, all the paths of a sector are aligned to their transmitter timing (symbol boundaries) before being combined with each other, in proportion to their signal strength or SNR. This step also may include an optional phase rotation step, which typically uses the pilot channel in conjunction with the received signal stream. A despreading operation may also be performed. As an alternative to MRC combining, equalization may be performed on the received signal, which has the effect of creating a single stream of data, but with the effective mitigation of channel effects. A decision feedback equalizer structure may be employed for symbol estimation, where inter-symbol interference is mitigated as well.
In a preferred embodiment, a received analog signal is down converted to digital data at a rate faster than the chipping rate specified in the standard. For each multipath identified and tracked, a downsampler downconverts the data corresponding to that ray to its chipping rate, by only extracting the on-time sample. The on-time samples from multiple fingers of a particular source are then combined in order to extract symbol estimates using a Fast Hadamard transform module. Symbol estimates are generated at what is known as a symbol rate, and is related to the processing length chosen for the particular implementation. In an exemplary embodiment, the processing length is 128 chips. Symbol level data at the symbol rate is then modified using a post-processor which performs either thresholding or weighing. This modified symbol level data is then used to construct interference estimates by performing the operations performed at the transmitter such as covering and spreading, using an inverse fast Hadamard transform module (which is equivalent to a fast Hadamard transform module with some intermediate scaling steps), and a spreader. Performing covering or spreading on the symbol level data leads to chip level data, which may then be interpolated back to a sample rate.
The efficiency of implementing the interference cancellation algorithm(s) at any given time depends on the specific “environment” presented by all the input rays, the timing of which is recovered in the fingers. The environment of input fingers can be characterized by the number of different base stations (sectors) identified, fingers detected per sector (multipaths), the strength distribution of all fingers, and the relative temporal positions of the symbol boundaries for all of the fingers. When a radio (terminal) is in motion, these characteristic details change rapidly. If the input fingers happen to be time multiplexed in the radio, the time multiplexing may be removed as a first step to restore the original relative time positions of the fingers.
1) One technique which offers operational efficiencies is to employ a common processing symbol boundary reference to be used for all fingers during the interference removal phase (not the estimation phase) based on a sorting of the offsets of the arrival times of the input fingers. One embodiment uses the boundary of the input finger identified by the sorting logic for the common processing boundary. Another embodiment creates a “virtual reference finger” that would initially be synchronized to the symbol boundaries of the input finger identified by the sorting logic, but when that input finger is deeply fading (even to the point of losing the time tracking of its symbol boundaries), the virtual reference finger boundaries would remain “locked” to the timing of where the original input finger was until the virtual reference finger no longer satisfied the sorting rules to be the reference. Virtual reference fingers are described in Patent Application, “Virtual Reference Timing for Multi-Time Based Systems,” filed on Sep. 15, 2006, which is hereby incorporated by reference. When the virtual reference finger no longer satisfies the sorting rules it is resynchronized to the new input finger selected by the sorting logic.
An exemplary embodiment for the sorting logic is as follows:
A) Sort all fingers into groups where each group is the set of received multi-paths from a single base station (cell). This is done by comparing the PN sequences of all fingers at various time offsets relative to each other until all possible matches within the allowed “multi-path time window” are found. This window is the maximum allowed difference in arrival time between the first finger and last finger of a multi-path group. A typical multi-path time window may be ¼ of a symbol time since any multipaths which have arrival times more than ¼ of a symbol later than the first arriving finger of a sector may be too weak to be utilized efficiently in interference estimation. An enhancement may be used to improve performance in noisy environments where a finger may be included in a group even though its PN sequence doesn't exactly match that of the group for short periods of time. The mismatch rate allowed is a design parameter that trades off noise sensitivity with detection time and false detection rate.
B) Within each group (sector), find the first arriving finger (as defined by their symbol boundaries).
C) Measure the arrival time offsets between all the first arriving fingers of each group.
D) Find the pair of first arriving fingers that has the largest time offset, and select the finger of this pair that arrived last as the “reference finger.” Hysteresis may be used to minimize sorting changes due to time variations of the fingers. This reference finger is the first arriving finger of the first arriving base station.
To put these techniques in context, an example of a system level embodiment utilizing these techniques follows:
1. Find a reference finger using the steps of the sorting logic outlined previously.
2. Within each group (sector), find the first or earliest arriving finger (as defined by their symbol boundaries). Create a sorted list starting with the reference finger and ending with the latest arriving fingers amongst the earliest arriving finger from each sector. This is the “first arriving finger” list.
3. Within each group (sector), find the last arriving finger (as defined by the symbol boundaries), and sort these fingers in order of arrival time after the reference finger's SBS (signal boundary strobe). This is the “last arriving finger” list.
4. Store the samples of all input fingers of sufficient strength in rolling 3 symbol memories (Input Finger Memory).
5. Wait for the SBS of the first element of the sorted “last arriving finger” list.
6. Read a whole symbol of 1× (on chip) samples of each finger (each multipath) of the first sector (as identified by the sorted “last arriving finger” list) from the Input Finger Memory. Note that these multipaths now have their symbol boundaries aligned to transmitter time (may not be aligned to receiver timing). Perform symbol and interference estimation on it.
7. Store the interference estimates for the current sector into a rolling three-symbol memory (Estimation Memory).
8. The Estimation Memory stores data such that address zero corresponds to the first interference estimate chip of the sector with the reference finger. Storage address (or write address) for other sectors is set by the offset between the reference finger and the first arriving finger of the sector being stored.
In another embodiment the use of the timing boundary of the reference finger can be replaced by an arbitrary reference timing signal (herein referred to as the arbitrary time reference, TR), which represents an arbitrary, but fixed reference time. FIG. 1 shows a storage structure that helps align the interference estimates to an arbitrary reference in time during data arrival at the receiver. RAMs (Random Access memories) can be used as the storage structures. Alternative embodiments for storage structures could be built using delay lines. The arbitrary time reference (TR) can be made to correspond to address zero in the RAM block. For every finger included in the estimation process, the offset between the TR and the finger's nearest symbol boundary after the reference is calculated. The offset can be calculated in chips or in samples (if oversampled data exists). For fingers whose offset in chips is not an exact integer multiple away from the reference time, the closest integer multiple is used. The interference estimates for sector 1 is stored in the RAM 100 such that the chip corresponding to the symbol boundary of the first arriving finger of the sector is stored in a location exactly M address locations away, where M chips is the offset in chips between the reference time and the symbol boundary of the first arriving finger. Similarly, sectors 2 and 3 are stored at the Nth and pth location, corresponding to their first arriving finger's offsets' (N and P chips) from the reference time. The above method of storing data aligns the sectors' interference estimates with respect to the TR. Every location of the RAM now stores reference time aligned interference estimates for the sectors used in the interference summation. The embodiment assumes a scenario where all three sectors have one finger each. If a sector has more than 1 finger used in the interference estimation process, all its fingers interference estimates can be generated using the sector interference estimates. The RAM may store multiple symbols of data per sector and multiple such RAMs may be used.
The input to the estimator is at chip rate and may have been decimated from a data set with a higher sample rate than the chip rate, e.g. four times the chip rate (4×), referred to as the sampling rate. The interference estimates at the point at which they are summed together have to be aligned to their arrival timing at the receiver. But, the chips corresponding to the interference estimate of a path may not be aligned to the interference estimate chips from other paths. FIG. 4 shows an example of a 4× system with two fingers with different chip alignments as well as the 4× sample points. Interference estimates are present only at samples points W1, A1, etc. for finger 1 and X2, B2, etc. for finger 2. For correct summation of the interference estimates, the estimates at the intermediate sample points are required. For e.g. to obtain a summed interference data sample for time point A, samples A1 and A2 are required. While A1 may be available from the estimator since it corresponds to finger 1's chip markers, the closest data samples to A2 that are available are X2 and B2 corresponding to finger 2's chip markers. An interpolator solves the problem where A2 can be obtained by performing an interpolation using multiple interference estimate samples that are available at finger 2's chip markers.
FIG. 2 shows the alignment of the interference estimates of the fingers when being summed together. This does not necessarily align the symbol boundaries of all the fingers that were estimated. Instead the alignment is based on the arrival timing of each path at the receiver. The summed interference is then removed from the corresponding uncanceled data stream that is a composite of all the signals as received at the receiver. The un-canceled data was stored before the interference estimation process to be used in the interference removal stage. The summation contains interference estimates for all fingers that were estimated except the finger that is being improved.
One embodiment of the interference removal module is where estimated interference is summed for all fingers. The sum is then subtracted from the un-canceled data stream, while adding back the individual interference estimates obtaining interference removed versions for individual fingers as shown in FIG. 5. For e.g. the interference removed version for finger 1 and finger 3 are shown in equations 1 and 2, where Y is the uncanceled data stream, S1 and S3 are interference estimates for fingers 1 and 3, Y1′ and Y3′ are interference removed versions of fingers 1 and 3 and μ is a weighting factor that may offer stabilization for the interference removal process. The summation of S over all fingers estimated is indicated by ΣSi performed by summer 514. The subtraction of the summation of interference estimates of all fingers from Y is performed by 516 a to 516 n. The result can be multiplied (using multipliers 518 a-518 n) by μ which can be held constant over all fingers. The estimated interference term added back (using summers 520 a-520 n) decides the finger that has interference removed from it.
Y′ 1=μ(Y−ΣS i)+S 1 (1)
Y′ 3=μ(Y−ΣS i)+S 3 (2)
An alternative embodiment for removing interference does not use the weighting factor μ as shown in equation 3 for finger 1. In this embodiment, the cancellation is implemented as
Y′ 1 =Y−ΣS i +S 1 (3)
FIG. 6 shows a storage structure consisting of a RAM 600 used to align the canceled data back to symbol boundaries. All the fingers' canceled data is made available with their symbol boundary indicators. The chip enable indicators may be available if the cancellation output is at the sample rate. Only samples corresponding to chip enable indicators are stored since the estimation process only uses chip-rate (1× chip) data as input. The data is stored such that anytime a symbol boundary indicator is encountered for a finger, the write address for the finger in the RAM 600 is reset to 0, and the chip corresponding to the symbol boundary is stored in address 0. Every finger will have its data aligned to its symbol boundary corresponding to the location with address 0. Reading data from address 0 for all fingers within a sector will provide symbol boundary aligned data which can be combined and sent to the interference estimator. The RAM 600 may store multiple symbol worth of data per finger and multiple RAMs may be used.
The un-canceled data is stored prior to the interference estimation. The timing control block (TCB) that generates the TR also starts a timer, based on the TR, which counts up to the latency of the system and then rolls over. When the timer reaches a preset value, defined by the interference removal block latency plus the output FIFO worst case delay, a request is sent to the block with the RAM 100 storing interference estimates. The RAM 100 may read the interference estimates corresponding to the TR (address zero as shown in FIG. 1) based on the request pulse from the TCB.
An advanced system includes a processing block with an input and output FIFO. The data-processing clock mayor may not be frequency/phased locked to the data-sampling clock, although, in general, it will be a higher clock rate that is not phase locked. Both the input and output FIFOs are port asynchronous. This indicates that the respective read and write port clocks are neither frequency nor phase locked. Data enters the processing block via the input FIFO. The depth of the input FIFO is small since the processing clock is greater than or equal to the sampling clock. The data is then stored in a port synchronous buffer for use by the processing block.
512=T sp+Δi+Δp+Δo +T ps
Δi =T R i +T w i
In one embodiment of the invention, the time Tw i is time-stamped to the sampling system and this time (or address) is given to the time TR o (0) on the read channel of the port synchronous output FIFO. With Δi determined from timing addresses within the processing system, one of which is explicitly time-stamped and the other of which is synchronously locked to this address, the first equation may be re-written as
512−T sp−Δi −T ps=Δp+Δo
Δo′=512−T sp −T ps−Δi
w o =R o+Δo
Δo′=Δo+Δp
Note that an additional assumption is made that the maximum processing time ΔP does not exceed the minimum output buffer time Δo. Since the processing clock frequency is assumed to be greater than the sampling clock frequency, the rest of the data burst from the processor P will be stored in the output FIFO ahead of the corresponding read access of the data.
The A/D converter at the front end of the receiver samples data at a rate higher than the chipping rate. The higher sampling rate is denoted as Nx, while the chip rate is denoted as 1×. The sample rate (Nx) is converted to the chip rate (1×) before the interference estimation process which uses 1× data. The Nx data is accompanied with chip enable indicators at the chips of a finger. The chip enable indicators can be used to pick 1× data from an Nx stream of data. The 1× data stream is then aligned to its symbol boundaries before the symbol and interference estimation process. The interference estimates stay at the 1× rate till the input of the interpolator. The interpolator creates Nx data samples from the 1× data samples, creating an Nx data stream for all fingers. Using RAM 100, the 1× input data to the interpolator was aligned to the closest chip point. Any left over sample level alignment is performed using delay lines on the Nx data stream at the output of the interpolator. The interference removal can be performed at the sample level (Nx) data rate. The interference removed data can then be stripped back to 1× data rate using stored chip enable indicators corresponding to the un-canceled data. Alternatively, the chip enable indicators can be regenerated using the symbol boundary information per finger. The interference removed 1× rate data can be sent out to the rake receiver or used in another iteration of interference cancellation.
Those skilled in the art will recognize that this invention may be realized in a chipset or a handset that is implemented for downlink processing, as well as a chipset or a basestation implemented for uplink processing.
The functions of the various elements shown in the drawings, including functional blocks labeled as “modules” may be provided through the use of dedicated hardware, as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be performed by a single dedicated processor, by a shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “modulecircuit” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor DSP hardware, read-only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and/or custom, may also be included. Similarly, the function of any component or device described herein may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.
1. An interference cancelling receiver, comprising:
at least one symbol estimator configured to operate on a signal stream to produce one or more symbol estimates from the signal stream;
one or more interference estimators coupled to the at least one symbol estimator to produce one or more of interference estimates;
one or more storage structures configured to store the one or more interference estimates at one or more locations in the one or more storage structures that are offset from a reference address by a number of addresses representative of a temporal offset between a time reference associated with the reference address and the corresponding interference estimate; and
an interference estimate combiner configured to combine one or more interference estimates aligned to the time reference to produce a composite interference estimate.
2. The interference cancelling receiver in claim 1, wherein the at least one symbol estimator is configured to operate on Rake combined data.
3. The interference cancelling receiver in claim 1, wherein the at least one symbol estimator is configured to operate on Equalizer combined data.
4. The interference cancelling receiver in claim 1, wherein the signal stream comprises data selected from one of an original received signal, an interference cancelled signal, and a combination of an original received signal and an interference cancelled signal.
5. The interference cancelling receiver in claim 1, further comprising a front-end configured to sample a received signal at a rate higher than a chipping rate and accompany sampled data at chips with chip enable indicators.
6. The interference cancelling receiver in claim 1, further comprising:
a sampling clock domain comprising a data sampling clock;
a processing clock domain comprising a processing clock having a greater frequency than the data sampling clock and not frequency or phase locked with the data sampling clock; and
an input first-in-first-out (FIFO) buffer and an output FIFO that interconnect the sampling clock domain with the processing clock domain, wherein both the input FIFO and the output FIFO are port asynchronous.
7. The interference cancelling receiver in claim 1, further comprising:
an input first-in-first-out (FIFO) buffer and an output FIFO that interconnect the sampling clock domain with the processing clock domain, wherein both the input FIFO and the output FIFO are port synchronous and include a retiming circuit configured to address frequency and phase differences between the data sampling clock and the processing clock.
8. A method for performing interference cancellation comprising:
computing symbol estimates from a combined data stream;
processing the symbol estimates to produce modified symbol estimates;
using said modified symbol estimates to create a plurality of interference estimates;
aligning at least one of the plurality of interference estimates with respect to a time reference by storing the plurality of interface estimates at a plurality of locations in one or more storage structures that are offset from a reference address by a number of addresses representative of a temporal offset between the time reference and the corresponding interference estimate;
combining the plurality of interference estimates aligned to the time reference to create a combined interference estimate; and
using the combined interference estimate to create at least one interference cancelled signal stream.
9. The method recited in claim 8, wherein said aligning comprises aligning chip-level data from a plurality of paths from a single source to a symbol boundary of each of said plurality of paths to produce a plurality of aligned paths.
10. The method recited in claim 8, wherein said combining comprises summing the plurality of interference estimates.
11. The method recited in claim 8, wherein the combined data stream comprises interference cancelled data.
12. The method recited in claim 8, wherein the combined data stream comprises a combination of interference cancelled data and raw signal.
13. The method recited in claim 8, further comprising:
sampling a received signal at a rate higher than a chipping rate; and
accompanying the sampled data at chips with chip enable indicators.
operating a sampling clock domain based on a data sampling clock;
operating a processing clock domain based on a processing clock having a greater frequency than the data sampling clock and not frequency or phase locked with the data sampling clock; and
interconnecting the sampling clock domain and the processing clock domain with an input first-in-first-out (FIFO) buffer and an output FIFO that both are port asynchronous.
15. The method recited in claim 8, further comprising:
operating a processing clock domain based on a processing clock having a greater frequency than the data sampling clock domain and not frequency or phase locked with the data sampling clock; and
interconnecting the sampling clock domain and the processing clock domain with an input first-in-first-out (FIFO) buffer and an output FIFO that are both port synchronous and that both include a retiming circuit configured to address frequency and phase differences between the data sampling clock and the processing clock.
US13/314,787 2001-09-28 2011-12-08 Methods for managing alignment and latency in interference suppression Active US8842786B2 (en)
US10/247,836 US7158559B2 (en) 2002-01-15 2002-09-20 Serial cancellation receiver design for a coded signal processing engine
US11/103,138 US7359465B2 (en) 2001-09-28 2005-04-11 Serial cancellation receiver design for a coded signal processing engine
US84559406P true 2006-09-19 2006-09-19
US84559506P true 2006-09-19 2006-09-19
US84621306P true 2006-09-21 2006-09-21
US11/858,074 US8085889B1 (en) 2005-04-11 2007-09-19 Methods for managing alignment and latency in interference cancellation
US13/314,787 US8842786B2 (en) 2002-09-20 2011-12-08 Methods for managing alignment and latency in interference suppression
US14/490,961 US9118400B2 (en) 2002-01-15 2014-09-19 Methods for managing alignment and latency in interference suppression
US11/858,074 Continuation US8085889B1 (en) 2001-09-28 2007-09-19 Methods for managing alignment and latency in interference cancellation
US14/490,961 Division US9118400B2 (en) 2001-09-28 2014-09-19 Methods for managing alignment and latency in interference suppression
US20120195360A1 US20120195360A1 (en) 2012-08-02
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US14/490,961 Active US9118400B2 (en) 2001-09-28 2014-09-19 Methods for managing alignment and latency in interference suppression
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