Source: http://www.google.com/patents/US5861669?ie=ISO-8859-1&dq=4316055
Timestamp: 2015-01-25 23:08:01
Document Index: 611451044

Matched Legal Cases: ['art 14', 'art 13', 'art 13', 'art 13', 'art 13', 'art 14', 'art 14', 'art 14', 'art 14', 'arts 14', 'art 14', 'art 14', 'art 14', 'art 14', 'art 13', 'art 13', 'art 81', 'art 81']

Patent US5861669 - Semiconductor package for surface mounting - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly...http://www.google.com/patents/US5861669?utm_source=gb-gplus-sharePatent US5861669 - Semiconductor package for surface mountingAdvanced Patent SearchPublication numberUS5861669 APublication typeGrantApplication numberUS 08/488,673Publication dateJan 19, 1999Filing dateJun 7, 1995Priority dateMay 17, 1991Fee statusLapsedAlso published asDE69222084D1, DE69222084T2, EP0513743A2, EP0513743A3, EP0513743B1, US5574310Publication number08488673, 488673, US 5861669 A, US 5861669A, US-A-5861669, US5861669 A, US5861669AInventorsMichio Sono, Junichi Kasai, Masanori Yoshimoto, Kazuto Tsuji, Kouji SaitoOriginal AssigneeFujitsu LimitedExport CitationBiBTeX, EndNote, RefManPatent Citations (22), Non-Patent Citations (6), Referenced by (4), Classifications (30), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor package for surface mountingUS 5861669 AAbstract A semiconductor device having a package of a single in-line type includes a semiconductor chip, a package body that accommodates the semiconductor chip therein and defined by a pair of opposing major surfaces and a plurality of interconnection leads held by the package body to extend substantially perpendicularly to a bottom surface. Each of the interconnection leads consists of an inner lead part located inside the package body and an outer lead part located outside the package body, the outer lead part being bent laterally at a boundary between the inner part and the outer part, in one of first and second directions that are opposite from each other and substantially perpendicular to the opposing major surfaces of the package body. A plurality of support legs extend laterally at the bottom surface of the package body for supporting the package body upright when the semiconductor device is placed on a substrate.
What is claimed is: 1. A semiconductor device having a package of a single in-line type, comprising:a semiconductor chip; a package body that accommodates the semiconductor chip therewithin, the package body being defined by a pair of opposing major surfaces connected by a bottom wall, the bottom wall including a substantially planar edge part that extends substantially perpendicular to the major surfaces, the package body further comprising a stage member embedded therein and supporting the semiconductor chip thereon; a plurality of interconnection leads held by the package body so as to extend substantially perpendicularly to the edge surface, each of the interconnection leads being connected to the semiconductor chip electrically, each of the interconnection leads consisting of an inner lead part located inside the package body and an integral, outer lead part located outside the package body and having a distal end, the outer lead part being bent laterally, relatively to the inner lead part, at a boundary between the inner lead part and the outer lead part, in one of first and second directions that are opposite to each other and substantially perpendicular to the opposing major surfaces; and a plurality of support legs formed as a unitary body with the stage member and held by the package body so as to extend substantially perpendicularly to the edge surface and in the first and second directions, each of the support legs consisting of an inner part located inside the package body and a corresponding outer part located outside the package body and bent laterally in one of the first and second directions at a boundary between the corresponding inner and outer parts, the outer leg parts extending beyond the distal ends of the outer lead parts and supporting the package body, when placed on a substrate, in an upright position relatively to the substrate. 2. A semiconductor device as claimed in claim 1 in which said semiconductor device includes an additional semiconductor chip, said stage member having first and second, mutually opposing major surfaces, said semiconductor chip and said additional semiconductor chip being provided on said first and second major surfaces of said stage member respectively.
3. A semiconductor device as claimed in claim 1 in which each of said stage member, said support legs and said interconnection leads comprises a composite conductor body comprising a first layer of a copper alloy and a second layer of an iron alloy stacked with each other, said first layer having a first thickness t while said second layer having a second thickness T, wherein there holds a relationship 0.3&#8806;t/T&#8806;2 between the first and second thicknesses. 4. A semiconductor device as claimed in claim 3 in which said composite conductor body has first and second opposing major surfaces separated with each other by an overall thickness W, wherein there holds a relationship 0.4&#8806;t/W&#8806;0.7 between the first thickness and the overall thickness. 5. A semiconductor device as claimed in claim 3 in which said copper alloy contains Cu, Sn and Zn, while said iron alloy contains Fe and Ni.
6. A semiconductor device as claimed in claim 1 in which said stage member is provided with an opening for dispersing a stress applied thereto.
7. A semiconductor device package of a single in-line type, comprising:a semiconductor chip; a package body housing the semiconductor chip therewithin and defined by a pair of spaced, opposing major sidewalls and a bottom wall extending between and interconnecting the opposing major sidewalls, a portion of the bottom wall comprising a planar edge surface which lies in a plane substantially transverse to the major sidewalls, the package body further comprising a stage member embedded therein and supporting the semiconductor chip thereon; a plurality of interconnection leads, each lead comprising an inner lead part disposed and secured within the package body and electrically connected to the semiconductor chip and an outer lead part extending integrally from the inner lead part, exteriorly of the package body, the respective inner lead parts of the plurality of interconnection leads being aligned in parallel relationship, intermediate the major sidewalls of the package body and the corresponding outer lead parts of the plurality of interconnection leads being bent, relatively to the corresponding inner lead parts and toward the bottom wall, so as to extend laterally in one of first and second, opposite directions from the planar edge surface; and a plurality of support legs formed as a unitary body with the stage member, each support lea comprising an inner leg part secured within the package body and an outer lea part extending from the inner leg part and emerging substantially perpendicularly from the planar edge surface, an outer leg part of each support leg being bent and extending laterally and exteriorly of the package body, in a selected one of the first and second directions, relatively to the planar edge surface, the outer leg parts of the support legs being of a longer dimension than the outer lead parts of the interconnection leads and supporting the package body, when the outer leg parts are received on a supporting substrate; such that the pair of major sidewalls of the package is disposed in an erect position relatively to the substrate. 8. The semiconductor device package of claim 7, wherein the successive outer lead parts are bent, in alternating succession and respectively, in the first and second opposite directions.
9. The semiconductor device package of claim 7, wherein all of the outer lead parts are bent in a selected, common one of the first and second directions.
10. The semiconductor device package of claim 7, wherein the outer lead parts are arranged in plural groups, each group comprising plural outer lead parts and wherein successive groups of the outer lead parts are bent, in alternating succession and respectively, in the first and second opposite directions.
11. The semiconductor device package of claim 7, wherein the outer lead parts have corresponding distal ends and the outer leg parts have corresponding distal ends, the distal ends of the outer leg parts being disposed laterally outwardly of the distal ends of the outer lead parts.
12. The semiconductor device package of claim 7, wherein the outer lead parts of the plurality of interconnection leads are bent, in alternating succession and respectively, in the first and second directions.
13. The semiconductor device package of claim 7, wherein the stage member has first and second mutually opposing major surfaces and wherein the semiconductor chip is mounted on the first major surface, further comprising;a second semiconductor chip, the second semiconductor chip being mounted on the second major surface of the lead frame. 14. A semiconductor device package of a single in-line type, comprising:a semiconductor chip; a package body housing the semiconductor chip therewithin and defined by a pair of spaced, opposing major sidewalls and a bottom wall extending between and interconnecting the opposing major sidewalls, the bottom wall including an edge surface which lies in a plane substantially transverse to the major sidewalls; a plurality of interconnection leads, each lead comprising an inner lead part and an outer lead part, the inner lead part disposed and secured within the package body and electrically connected to the semiconductor chip and the outer lead part extending integrally from the inner lead part, exteriorly of the package body, the plurality of interconnection leads being intermediate the major sidewalls of the package body and the corresponding outer lead parts of the plurality of interconnection leads being bent, relatively to the corresponding inner lead parts and toward the bottom wall, so as to extend laterally in one of first and second, opposite directions from the planar edge surface; and a lead frame comprising a stage member portion having a chip mounting surface on which the semiconductor chip is mounted and a plurality of support legs disposed in correspondence to, and emerging from, the planar edge surface, an outer leg part of each support leg being bent and extending, exteriorly of the package body, laterally in a selected one of the first and second directions from the planar edge surface, the outer leg parts of the support legs being of a longer dimension than the outer lead parts of the interconnection leads and supporting the package body. 15. The semiconductor device package of claim 14, wherein successive the outer lead parts are bent, in alternating succession and respectively, in the first and second opposite directions.
16. The semiconductor device package of claim 14, wherein all of the outer lead parts are bent in a selected, common one of the first and second directions.
17. The semiconductor device package of claim 14, wherein the outer lead parts are arranged in plural groups, each group comprising plural outer lead parts and wherein successive groups of the outer lead parts are bent in alternating succession and respectively, in the first and second opposite directions.
18. The semiconductor device package of claim 14, wherein the outer lead parts have corresponding distal ends and the outer leg parts have corresponding distal ends, the distal ends of the outer leg parts being disposed laterally outwardly of the distal ends of the outer lead parts.
19. The semiconductor device package of claim 14, wherein the outer lead parts of the plurality of support legs are bent, in alternating succession and respectively, in the first and second directions.
20. A semiconductor device package of a single in-line type, comprising:a semiconductor chip; a package body housing the semiconductor chip therewithin and defined by a pair of spaced, opposing major sidewalls and a bottom wall extending between and interconnecting the opposing major sidewalls, a portion of the bottom wall comprising a planar edge surface which lies in a plane substantially transverse to the major sidewalls; a plurality of interconnection leads, each interconnection lead comprising an inner lead part disposed and secured within the package body and electrically connected to the semiconductor chip and an outer lead part extending integrally from the inner lead part and exteriorly of the package body, the respective inner lead parts of the plurality of interconnection leads being aligned in parallel relationship, intermediate the major sidewalls of the package body, and the corresponding outer lead parts of the plurality of interconnection leads being bent, relatively to the corresponding inner lead parts and toward the bottom wall, so as to extend laterally in one of first and second, opposite directions from the planar edge surface; a plurality of support legs, each support leg comprising an inner leg part secured within the package body and an outer leg part extending from the inner leg part and emerging from the planar edge surface, the inner leg parts of the plurality of support legs being disposed in a common plane intermediate the pair of spaced, opposing major side walls, the outer leg part of each support leg being bent and extending, exteriorly of the package body and laterally in a selected one of the first and second, opposite directions relatively to the planar edge surface, the outer leg parts of the support legs being of a longer dimension than the outer lead parts of the interconnection leads and supporting the package body when the outer leg parts are received on a supporting substrate and such that the pair of major sidewalls of the package is disposed in an erect position relatively to the substrate; and each of the plurality of interconnection leads and each of the plurality of support legs having a common thickness and being formed of a common material composition. 21. The semiconductor device package of claim 20, wherein the outer lead parts are bent, in alternating succession and respectively, in the first and second opposite directions.
22. The semiconductor device package of claim 20, wherein all of the outer lead parts are bent in a selected, common one of the first and second directions.
23. The semiconductor device package of claim 20, wherein the outer lead parts are arranged in plural groups, each group comprising plural outer lead parts, and wherein successive groups of the outer lead parts are bent, in alternating succession and respectively, in the first and second opposite directions.
24. The semiconductor device package of claim 20, wherein the outer lead parts have corresponding distal ends and the outer leg parts have corresponding distal ends, the distal ends of the outer leg parts being disposed laterally outwardly of the distal ends of the outer lead parts.
25. The semiconductor device package of claim 20, wherein the outer lead parts of the plurality of interconnection leads are bent, in alternating succession and respectively, in the first and second directions.
26. The semiconductor device package of claim 20, further comprising a lead frame embedded within the package body and supporting the semiconductor chip thereupon.
27. The semiconductor device package of claim 20, wherein the corresponding inner leg parts of at least selected support legs, of the plurality of support legs, are integral with the lead frame.
28. The semiconductor device package of claim 20 wherein the lead frame has first and second mutually opposing major surfaces and wherein the semiconductor chip is mounted on the first major surface, further comprising;a second semiconductor chip, the second semiconductor chip being mounted on the second major surface of the lead frame. 29. A semiconductor device package of a single in-line type, comprising:a semiconductor chip; a package body housing the semiconductor chip therewithin and defined by a pair of spaced, opposing major sidewalls and a bottom wall extending between and interconnecting the opposing major sidewalls, the bottom wall including an edge surface which lies in a plane substantially transverse to the major sidewalls; a plurality of interconnection leads, each lead comprising an inner lead part and an outer lead part, the inner lead parts being disposed in a common plane parallel to and intermediate the major sidewalls and secured within the package body and electrically connected to the semiconductor chip and the outer lead parts extending integrally from the corresponding inner lead parts, exteriorly of the package body, the corresponding outer lead parts of the plurality of interconnection leads being bent, relatively to the corresponding inner lead parts and toward the bottom wall, so as to extend laterally in one of first and second, opposite directions from the planar edge surface; a lead frame comprising a chip mounting surface on which the semiconductor chip is mounted and a plurality of support legs, each support leg comprising an inner support leg part integral with the lead frame and disposed with the lead frame in the common plane and an outer support leg part extending integrally from the inner leg part and emerging from the planar edge surface, the outer leg part of each support leg being bent and extending, exteriorly of the package body, laterally in a selected one of the first and second directions from the planar edge surface, the outer leg parts of the support legs being of a longer dimension than the outer lead parts of the interconnection leads and supporting the package body; and each of the plurality of interconnection leads and each of the plurality of support legs having a common thickness and being formed of a common material composition. 30. The semiconductor device package of claim 29, wherein the outer lead parts are bent, in alternating succession and respectively, in the first and second opposite directions.
31. The semiconductor device package of claim 29, wherein all of the outer lead parts are bent in a selected, common one of the first and second directions.
32. The semiconductor device package of claim 29, wherein the outer lead parts are arranged in plural groups, each group comprising plural outer lead parts, and wherein successive groups of the outer lead parts are bent, in alternating succession and respectively, in the first and second opposite directions.
33. The semiconductor device package of claim 29, wherein the outer lead parts have corresponding distal ends and the outer leg parts have corresponding distal ends, the distal ends of the outer leg parts being disposed laterally outwardly of the distal ends of the outer lead parts.
34. The semiconductor device package of claim 29, wherein the outer lead parts of the plurality of interconnected leads are bent, in alternating succession and respectively, in the first and second directions.
35. The semiconductor device package of claim 29 wherein the lead frame includes first and second mutually opposing major surfaces and wherein the semiconductor chip is mounted on the first major surface, further comprising:a second semiconductor chip the second semiconductor chip being mounted on the second major surface of the lead frame. 36. A semiconductor device package of a single in-line type, comprising:a semiconductor chip; a package body housing the semiconductor chip therewithin and defined by a pair of spaced, opposing major sidewalls and a bottom wall extending between and interconnecting the opposing major sidewalls, a portion of the bottom wall comprising an edge surface which lies in a plane substantially transverse to the major sidewalls; a plurality of interconnection leads, each lead comprising an inner lead part disposed and secured within the package body and electrically connected to the semiconductor chip and an outer lead part extending integrally from the inner lead part, exteriorly of the package body, the respective inner lead parts being disposed in a common plane parallel to and spaced intermediate the major sidewalls of the package body and secured therewithin and the corresponding outer lead parts of the plurality of interconnection leads being bent, relatively to the corresponding inner lead parts and toward the bottom wall, so as to extend laterally in a selected one of first and second, opposite directions relatively to the planar edge surface; and a first lead frame, embedded in the package body, comprising a chip carrier portion for supporting the semiconductor chip and a plurality of first support legs integral with and extending from the chip carrier portion for supporting the package, each first support leg comprising at least an inner leg part integral with the first lead frame and disposed therewith in the common plane and a corresponding outer leg part, the outer leg parts being of a longer dimension than the outer lead parts and extending exteriorly of the package body and laterally, transversely to the major sidewalls of the package body; a second lead frame, embedded in the package body, comprising a plurality of second support legs for supporting the package, each support leg comprising at least an inner leg part integral with the second lead frame and disposed therewith in the common plane and a corresponding an outer leg part, the outer leg parts being of a longer dimension than the outer lead parts and extending exteriorly of the package body and laterally, transversely to the major sidewalls of the package body. 37. The semiconductor device package of claim 36, wherein the outer lead parts are bent, in alternating succession and respectively, in the first and second opposite directions.
38. The semiconductor device package of claim 36, wherein all of the outer lead parts are bent in a selected, common one of the first and second directions.
This application is a division of application Ser. No. 08/330,737, filed Oct. 28, 1994 and now abandoned, in turn a continuation of application Ser. No. 07/881,899, filed May 12, 1992 and now abandoned.
In order to mount as many as possible of the semiconductor devices on a single support substrate, a so-called single in-line package (SIP) is proposed. In the single in-line package, the leads are provided along a single edge of a flat package body to extend perpendicularly with respect to the edge, and the package body is held upright on the substrate by inserting the leads into the corresponding holes of the substrate. As the package body is held vertically on the substrate, one can increase the number of the packages that are mounted on the single substrate. Further, such a structure is advantageous for cooling the device.
In order to combine the advantageous features of the single in-line package with the advantageous features of the surface mounting technology, a package structure shown in FIG. 1 is proposed in U.S. Pat. No. 4,975,763.
The package of FIG. 1 has another drawback in that each lead 4 has to extend straight from the package body 2 at least for a distance corresponding to the length of the stop portion 6 of each stud 5. This straight part of the lead 4 does not contribute to anything and causes an unwanted delay of the electrical signals that is carried therethrough. With the increasing operational speed of semiconductor devices, such a delay may cause a serious problem in the exchange of electric signals between the chip and the conductor pattern on the substrate. Further, such a structure having a long, exposed lead is vulnerable to external noises. As long as the studs are used for supporting the package body on the substrate, one cannot reduce the length of the lead cannot be satisfactorily reduced.
FIGS. 24(A) and 24(B) are diagrams showing the package according to a fifteenth embodiment of the present invention in an end view and a top view;
FIG. 25 is a diagram showing the mounting of the package of the fifteenth embodiment on a substrate;
FIG. 3 shows also a number of leads 14 provided at the bottom edge 11f of the package body 11. As will be explained later with reference to FIG. 7, each lead 14 is formed of a conductor strip that projects in the downward direction from the bottom edge 11f of the package body 11 and is bent laterally to form an outer lead part 14a. In other words, the leads 14 are bent at the root part thereof similarly to the support leads and extend in one of first and second, mutually opposite directions that are perpendicular to the major surface 11a and 11b of the package body 11. In the embodiment of FIG. 3, the outer leads 14a extend alternately in the first and second directions. Thereby, the chance of a short-circuit occurring between the adjacent leads is substantially reduced. Further, by providing the leads 14 alternately as shown in FIG. 3, one can increase the pitch of the conductor patterns that are provided on the substrate in correspondence to the leads 14. Thereby, the fabrication of the substrate becomes substantially easier.
Referring to FIG. 5, the semiconductor device 10 includes a first lead frame 12 and a second lead frame 13 both embedded in the resin package body 11, wherein the first lead frame 12 has extension parts that project outside the package body as the aforementioned support leads 12a and 12b. Similarly, the second lead frame 13 has extension parts that project outside the package body as the support leads 13a and 13b. The second lead frame 13 further includes a stage part 13c for supporting the semiconductor chip 15 thereon. In the illustrated example, the stage part 13c has an elongated rectangular form in correspondence to an elongated rectangular form of the chip 15. In correspondence to the stage part 13c, the package body 11 also has an elongated rectangular form.
Referring to FIG. 6, it can be seen that the support legs 13a and 13b extend as a part of the lead frame 13 and are bent laterally at the root part thereof upon emerging from the package body 11. On the other hand, FIG. 7 shows the semiconductor chip 15 that is held on the stage part 13c, and the bonding wire 17 connects the bonding pad 16 on the semiconductor chip 15 to the inner lead part 14b of the interconnection lead 14. As already described, the inner lead part 14b of the lead 14 extends substantially perpendicular to the bottom edge surface 14f of the package body 11, while the outer lead part 14a is bent laterally upon emerging from the package body 11. Thereby, it will be noted that the outer lead part 14a is formed at a level substantially flush with the support legs 12a, 12b, 13a and 13b. When placed on the substrate 19, the outer lead parts 14a establish contact with a corresponding conductor pattern 19a that is provided on the substrate 19. Thus, any unnecessary vertical extension of the leads is effectively eliminated, and the delay of electrical signals in the lead 14 is minimized.
Referring to FIG. 9(A) showing the improved outer lead part 14a, there is provide a semi-circular cutout 20a in a conductor strip 20 that forms the lead 14, for increasing the area for contacting with the soldering alloy. Thereby, a firm contact is achieved, in terms of mechanical as well as electrical reliability, between the lead 14 and the conductor pattern 19a. FIG. 9(B) shows a modification of the structure of FIG. 9(A) wherein a plurality of cutouts 21a are provided in a conductor strip 21 that forms the outer lead part 14a of the lead 14.
FIGS. 10(A) and 10(B) are diagrams showing a fourth embodiment of the present invention, wherein the outer lead part 14a that includes a conductor strip 22 is shown. Referring to the drawings, a pair of semispherical projections 22a are provided on the lower major surface of the conductor strip 22 to protrude in a downward direction, and corresponding depressions are formed on the upper major surface of the outer lead part 14a. There, the projections 22a establishes a contact with the conductor pattern 19a on the substrate 19 with a space formed between the conductor pattern 19a and the conductor strip 19 as shown in FIG. 10(B). In the semiconductor device of the present embodiment, the air between the conductor strip 22 and the conductor strip 19a can escape freely upon reflowing of the soldering alloy, and a firm, reliable contact can be obtained. Further, the lead 14 of the present embodiment has an improved mechanical rigidity due to the semi-spherical projections 22a. In this embodiment, too, the rest of the device structure is identical with the device of the first embodiment and further description thereof with reference to drawings will be omitted.
In the embodiment of FIG. 15, the leads at the bottom edge 11f of the package body 11 are not provided alternately in the first and second directions. Instead, the leads are grouped into a number of lead pairs, each including a lead pair 41-1, and 41-2, 41-3 and 41-4, 41-5 and 41-6, etc., wherein the direction of extension of the leads is changed alternately in each lead pair. The device 40 of FIG. 15 is suitable for use in combination with the substrate 19 wherein the density or pitch of the conductor pattern is relatively sparse. FIG. 16 shows a semiconductor device 50 corresponding to a modification of the device of FIG. 15 that includes interconnection leads 51 at the bottom edge of the package body 11 in correspondence to the interconnection lead 14. In the device 50, the interconnection leads 51 extend in the same direction. Similarly to the previous device 40, this construction is useful when the interconnection leads 51 are provided with a relatively sparse pitch. Particularly, the construction of FIG. 16 is advantageous for inspecting the contact at the interconnection leads 14 visually, as such a visual inspection can be achieved from one side of the device. Thereby, the efficiency of assembling is substantially improved.
0.4&#8806;(t/W)&#8806;0.7                                (2)
Within the range where the foregoing two conditions (1) and (2) are met, one can set the thickness of the layers 27a, 27b and 27c as desired. FIG. 18 shows a few examples can be set that satisfy the foregoing requirements wherein the thickness t1 is set equal to the thickness t2 and where the total thickness W is set at about 150 μm.
The aperture 28a of FIG. 20(A) extends laterally through the stage part 13c, while FIG. 20(B) shows four apertures 28b that are disposed laterally and vertically to form a cross-shaped pattern. FIG. 20(C), on the other hand, shows apertures 28c that include a cross-shaped opening at the center of the stage part 13c and four elongated openings that extend obliquely to surround the central cross-shaped pattern. FIG. 20(D) shows an aperture pattern 28d that includes a pair of T-shaped openings disposed oppositely to each other vertically and a pair of E-shaped openings that are disposed to oppose with each other laterally. FIG. 20(E) shows an aperture pattern 28e that includes four elongated openings disposed radially. Further, FIG. 20(F) shows four elongated apertures 28f that are disposed parallel with each other to extend laterally. Any of these apertures are effective in avoiding the concentration of the thermal stress particularly at the time of the reflowing of the solder alloy.
The embodiment of FIGS. 24(A) and 24(B) is intended to provide a lateral support of the upright package body on the substrate when the semiconductor devices are mounted in a large mounting density, and includes semispherical projections 73 protruding laterally from the two major surfaces 11a and 11b of the package body 11 as shown in FIG. 24(A). Such lateral projections 73 are provided to oppose each other as shown in the plan view of FIG. 24(B).
FIG. 25 shows a number of semiconductor devices 70-1, 70-2, 70-3, . . . that are provided on a substrate (not shown). As shown in FIG. 25, the devices are arranged on the substrate such that the semi-spherical projections 73 of adjacent devices oppose with each other. Thus, when one of the devices such as the semiconductor device 70-2 is tilted toward the device 70-3 by an external force F, for example, the semi-spherical projection 73 on the major surface 11a of the device 70-2 makes a contact with the corresponding projection 73 provided on the major surface 11b of the device 70-3. Thereby, the device 70-2 is supported laterally against tilting by the device 70-3.
Referring to FIG. 28(A) showing the device 80 in a bottom view, the semiconductor device 80 includes the interconnection lead 14, wherein an outer lead part 81 of the interconnection lead 14 extends beyond the package body 11 by a length of 0.1-0.2 mm. Similar to the first embodiment, the outer lead part 81 extend alternately in opposite directions. By providing the lead 14 as such visual inspection of the connection of th interconnection becomes easier.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS4441119 *Jan 15, 1981Apr 3, 1984Mostek CorporationIntegrated circuit packageUS4967262 *Nov 6, 1989Oct 30, 1990Micron Technology, Inc.Gull-wing zig-zag inline lead package having end-of-package anchoring pinsUS4975763 *Mar 14, 1988Dec 4, 1990Texas Instruments IncorporatedEdge-mounted, surface-mount package for semiconductor integrated circuit devicesUS5147815 *Mar 1, 1991Sep 15, 1992Motorola, Inc.Method for fabricating a multichip semiconductor device having two interdigitated leadframesUS5245215 *Feb 3, 1992Sep 14, 1993Kabushiki Kaisha ToshibaMultichip packaged semiconductor device and method for manufacturing the sameEP0333374A2 *Mar 8, 1989Sep 20, 1989Texas Instruments IncorporatedEdge-mounted, surface-mount package for semiconductor integrated circuit devicesJPH01140844A * Title not availableJPH01166545A * Title not availableJPH01230254A * Title not availableJPH01230265A * Title not availableJPH02109357A * Title not availableJPH02110960A * Title not availableJPH02125651A * Title not availableJPH03104265A * Title not availableJPH03129866A * Title not availableJPS6489353A * Title not availableJPS60241241A * Title not availableJPS60242653A * Title not availableJPS61174656A * Title not availableJPS62136060A * Title not availableJPS62243348A * Title not availableJPS63169055A * Title not available* Cited by examinerNon-Patent CitationsReference1 *Patent Abstracts of Japan , vol. 011, No. 359 (E 559), Nov. 12, 1987 & JP-A-62 136 060 (Mitsubishi Electric Corp.), Jun. 19, 1987.2 *Patent Abstracts of Japan , vol. 012, No. 435 (E 683), Nov. 16, 1988 & JP-A-63 169 055 (NEC Corp.), Jul. 13, 1988.3 *Patent Abstracts of Japan , vol. 014, No. 324 (E 951), Jul. 11, 1990 & JP-A-02 109 357 (Sumitomo Special Metals Co.), Apr. 23, 1990.4Patent Abstracts of Japan, vol. 11, No. 359 (E-559), Nov. 12, 1987 & JP-A-62 136 060 (Mitsubishi Electric Corp.), Jun. 19, 1987.5Patent Abstracts of Japan, vol. 12, No. 435 (E-683), Nov. 16, 1988 & JP-A-63 169 055 (NEC Corp.), Jul. 13, 1988.6Patent Abstracts of Japan, vol. 14, No. 324 (E-951), Jul. 11, 1990 & JP-A-02 109 357 (Sumitomo Special Metals Co.), Apr. 23, 1990.* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS6836003Mar 28, 2001Dec 28, 2004Micron Technology, Inc.Integrated circuit package alignment featureUS6858453 *Oct 12, 1999Feb 22, 2005Micron Technology, Inc.Integrated circuit package alignment featureUS6979900 *Oct 21, 2003Dec 27, 2005Delphi Technologies, Inc.Integrated circuit package with integral leadframe convector and method thereforUS6991960Aug 30, 2001Jan 31, 2006Micron Technology, Inc.Method of semiconductor device package alignment and method of testing* Cited by examinerClassifications U.S. Classification257/696, 257/723, 257/666, 257/672, 257/E23.048International ClassificationH01L23/482, H01L23/58, H05K3/34, H05K3/30, H01L23/495Cooperative ClassificationH01L24/48, H01L24/49, H05K2201/10454, H05K2201/10696, H05K2201/10568, H05K3/303, H05K2201/10659, H01L2224/49175, H01L23/49555, H01L2224/48247, H01L2924/01079, H05K2201/09709, H05K2201/09781, H05K2201/10522, H01L2224/48091, H05K3/3426, H01L2224/48472, H01L2224/45144European ClassificationH01L23/495G4B6, H05K3/30CLegal EventsDateCodeEventDescriptionMar 8, 2011FPExpired due to failure to pay maintenance feeEffective date: 20110119Jan 19, 2011LAPSLapse for failure to pay maintenance feesAug 23, 2010REMIMaintenance fee reminder mailedJun 23, 2006FPAYFee paymentYear of fee payment: 8Jun 27, 2002FPAYFee paymentYear of fee payment: 4Jul 6, 1999CCCertificate of correctionRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services