Source: http://www.google.com/patents/US6479391?dq=7,579,397
Timestamp: 2016-05-28 20:52:23
Document Index: 785895973

Matched Legal Cases: ['art 210', 'art 310', 'art 310', 'art 310', 'art 410', 'art 410']

Patent US6479391 - Method for making a dual damascene interconnect using a multilayer hard mask - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsAn improved method for making a semiconductor device is described. Initially, a structure is formed that includes first and second hard masking layers that cover a dielectric layer. A layer of photoresist is deposited and patterned to expose part of the second hard masking layer to define a via. That...http://www.google.com/patents/US6479391?utm_source=gb-gplus-sharePatent US6479391 - Method for making a dual damascene interconnect using a multilayer hard maskAdvanced Patent SearchPublication numberUS6479391 B2Publication typeGrantApplication numberUS 09/746,035Publication dateNov 12, 2002Filing dateDec 22, 2000Priority dateDec 22, 2000Fee statusLapsedAlso published asUS20020081854Publication number09746035, 746035, US 6479391 B2, US 6479391B2, US-B2-6479391, US6479391 B2, US6479391B2InventorsPatrick Morrow, Jihperng Leu, Chia-Hong JanOriginal AssigneeIntel CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (6), Referenced by (79), Classifications (17), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetMethod for making a dual damascene interconnect using a multilayer hard mask
US 6479391 B2Abstract
forming a conductive layer on a substrate; forming a dielectric layer on the conductive layer; forming a first hard masking layer on the dielectric layer; forming a second hard masking layer on the first hard masking layer; forming a third hard masking layer on the second hard masking layer; forming a fourth hard masking layer on the third hard masking layer; depositing a first layer of photoresist and then patterning that first layer to expose a first part of the fourth hard masking layer to define a via to be etched through the dielectric layer; etching through the exposed first part of the fourth hard masking layer and through the underlying portions of the third and second hard masking layers; depositing a second layer of photoresist and then patterning that second layer to expose a second part of the fourth hard masking layer to define a trench to be etched through the dielectric layer; etching through the exposed second part of the fourth hard masking layer; etching through the portion of the third hard masking layer that had lain beneath the exposed second part of the fourth hard masking layer while etching through the portion of the first hard masking layer that had lain beneath the exposed first part of the fourth hard masking layer to expose a first portion of the dielectric layer; etching a via and trench into the dielectric layer; and filling the via and trench with a conductive material. 2. The method of claim 1 further comprising:
forming a barrier layer on the surface of the conductive layer prior to forming the dielectric layer; and removing part of the barrier layer before filling the via and trench with the conductive material. 3. The method of claim 2 further comprising:
etching into the exposed first portion of the dielectric layer to a first depth, after etching through the portion of the first hard masking layer that had lain beneath the exposed first part of the fourth hard masking layer; removing the portions of the second hard masking layer and the first hard masking layer that had lain beneath the exposed second part of the fourth hard masking layer to expose a second portion of the dielectric layer; and etching into both the first and second exposed portions of the dielectric layer to form the via and trench. 4. The method of claim 3 wherein the first and third hard masking layers include a material that is selected from the group consisting of silicon dioxide, silicon oxyfluoride, silicon oxycarbide, silicon oxynitride, silicon carbide, and carbon doped oxide, and the second and fourth hard masking layers include a material that is selected from the group consisting of silicon nitride, silicon carbide, silicon oxycarbide, and silicon oxynitride.
forming a conductive layer on a substrate; forming a barrier layer on the surface of the conductive layer; forming a first dielectric layer that contains an oxide on the barrier layer; forming a second dielectric layer that contains a polymer based film on the first dielectric layer; forming a first hard masking layer on the second dielectric layer; forming a second hard masking layer on the first hard masking layer; depositing a first layer of photoresist and then patterning that first layer to expose a first part of the second hard masking layer to define a via to be etched through the first and second dielectric layers; etching through the exposed first part of the second hard masking layer; depositing a second layer of photoresist and then patterning that second layer to expose a second part of the second hard masking layer to define a trench to be etched through the second dielectric layer; etching through the exposed second part of the second hard masking layer; etching through a first portion of the first hard masking layer to expose a first portion of the second dielectric layer; etching a via through the second dielectric layer; etching through a second portion of the first hard masking layer to expose a second portion of the second dielectric layer while etching the via through the first dielectric layer; etching through the second exposed portion of the second dielectric layer to form a trench; and removing the part of the barrier layer that underlies the via before filling the via and trench with a conductive material. 7. A method of forming a semiconductor device comprising:
forming a conductive layer on a substrate; forming a barrier layer on the surface of the conductive layer; forming a first dielectric layer that contains an oxide on the conductive layer; forming a second dielectric layer that contains a polymer based film on the first dielctric layer; forming a first hard masking layer on the second dielectric layer; forming a second hard masking on the first hard masking layer; depositing a first layer of photoresist and then patterning that first layer to expose a first part of the second hard masking layer to define a trench to be etched through the second dielectric layer; etching through the exposed first part of the second hard masking layer; depositing a second layer of photoresist and then patterning that second layer to expose a first part of the first hard masking layer to define a via to be etched through the first and second dielectric layers; etching through a second part of the second hard masking layer; then etching through the exposed first part of the first hard masking layer to expose a first portion of the second dielectric layer; etching a via through the second dielectric layer removing a second portion of the first hard masking layer to expose a second portion of the second dielectric layer while etching the via through the first dielectric layer; etching through the second exposed portion of the second dielectric layer to form a trench; and removing the part of the barrier layer that underlies the via before filling the via and trench with a conductive material.
After that etch step, the photoresist is removed such as by applying a conventional photoresist ashing step, e.g. one that applies an oxygen and nitrogen containing plasma to remove the photoresist. The remaining portion of silicon dioxide layer 208 protects dielectric layer 203 during that photoresist removal step. The resulting structure is shown in FIG. 2b. A second layer of photoresist 230 is then deposited and patterned to define the trench to be etched into dielectric layer 203. When patterned, a second part 210 of second hard masking layer 209 is exposed, as shown in FIG. 2c. That figure shows how the patterned photoresist layer 230 may be misaligned with respect to the etched portion 220 of layers 208 and 209, without any adverse impact. As long as part of the region that layer 230 exposes lines up with part of etched portion 220, an acceptable trench and via structure may ultimately result. The process of the present invention thus enables an increased alignment budget, when compared to a process that performs trench lithography before via lithography.
At this point, remaining portion 223 of first hard masking layer 208, which overlies the region where the via will be formed within dielectric layer 203, must be removed. When portion 223 comprises silicon dioxide, a plasma etch process that is conventionally used to remove such a material may be employed, e.g., one that uses fluorocarbon chemistry. A preferred plasma that may be used to perform such an etching step may result from feeding a mixture of C4F8, carbon monoxide, oxygen and argon into a conventional plasma etcher. That etcher is operated long enough to cause the plasma to etch through portion 223 of oxide hard mask 208, but only long enough to partially etch through section 225 of oxide hard mask 208. Part of section 225 must remain to protect the underlying portion of dielectric layer 203. The resulting structure is shown in FIG. 2e. After portion 223 is removed, a first part of via 240 is etched into dielectric layer 203 to generate the structure shown in FIG. 2f. When dielectric layer 203 comprises a polymer based film, a plasma formed from a mixture of oxygen, nitrogen, and carbon monoxide may be used to perform that etch step. That process terminates when via 240 reaches a first depth within dielectric layer 203. This ensures that a subsequent process step for etching the trench will not extend the via through barrier layer 202. Following that via etch step, the remaining portion of section 225 of first hard masking layer 208 is removed—using, for example, the same process that was used previously to remove portion 223, as described above. This generates the FIG. 2g structure.
Barrier layer 202 removal may be followed by a short wet etch (which employs an etch chemistry that is compatible with the material used to form conductive layer 201) to clear etch residue from the surface of conductive layer 201. When copper is used to make that conductive layer, that portion of barrier layer 202 should be removed, using a copper compatible chemistry, before any copper electroplating step is applied to fill via 240 and trench 250. Removal of barrier layer 202 produces the structure shown in FIG. 2i. Following that barrier layer removal step, trench 250 and via 240 are filled with a conductive material to form second conductive layer 205. That conductive material may comprise any of the materials identified above in connection with conductive layer 201. It may comprise the same substance as conductive layer 201, or may comprise a substance different from that used to make conductive layer 201.
After forming that four layer hard mask, a photoresist layer is deposited and patterned on top of it to define a via formation region. The patterned photoresist leaves exposed a first part of fourth hard masking layer 365. That exposed portion is then etched using a nonselective plasma etch step, e.g., one created by feeding C4F8, oxygen and argon into a conventional plasma etcher. That etcher is operated long enough to cause the plasma to etch through layers 365, 360, and 309. After that etch step, the photoresist is removed using a conventional ashing step, e.g., one which employs an oxygen and nitrogen based plasma, to produce the structure shown in FIG. 3b. A second layer of photoresist 330 is then deposited and patterned to define the trench. When patterned, a second part 310 of fourth hard masking layer 365 is exposed, as shown in FIG. 3c. Like the structure shown in FIG. 2c, patterned photoresist layer 330 is misaligned with respect to the etched portion 320 of layers 365, 360 and 309. After photoresist layer 330 is patterned, the exposed second part 310 of fourth hard masking layer 365 is etched, e.g., by using a plasma formed from feeding a mixture of CH2F2, oxygen and argon into a plasma etcher. When removing second part 310, a substantial portion of photoresist layer 330 may be removed at the same time. Any remaining photoresist may be removed using a conventional ashing step to generate the structure illustrated in FIG. 3d. Remaining portion 323 of first hard masking layer 308, which overlies the region where the via will be formed within dielectric layer 303, is then removed at the same time unprotected portion 361 of layer 360 is removed. When portions 323 and 361 comprise silicon dioxide, a plasma etch process that uses a plasma resulting from feeding a mixture of C4F8, carbon monoxide, oxygen and argon into a plasma etcher may be used. Section 327 of nitride hard mask 309 and section 325 of oxide hard mask 308 remain to protect the underlying portion of dielectric layer 303. The resulting structure is shown in FIG. 3e. After portion 323 is removed, a first part of via 340 is etched into dielectric layer 303 to generate the structure shown in FIG. 3f. When dielectric layer 303 comprises a polymer based film, a plasma generated from a mixture of hydrogen and nitrogen, or from a mixture of oxygen, nitrogen and carbon monoxide, may be used to perform that etch step. Following that via etch step, unprotected portion 327 of second hard masking layer 309, and the remainder of fourth hard masking layer 365, are removed—using, for example, a plasma formed from feeding a mixture of CH2F2, oxygen and argon into a plasma etcher. The FIG. 3g structure results.
Following that step, unprotected portion 325 of layer 308 and the remainder of third hard masking layer 360 are removed (e.g., by feeding a mixture of C4F8, carbon monoxide, oxygen and argon into a plasma etcher), creating the structure of FIG. 3h. Trench 350 and the remaining part of via 340 are then etched into dielectric layer 303 to produce the structure illustrated in FIG. 3i using, for example, the same process that was used to partially etch via 340 to generate the structure shown in FIG. 3f. Following that trench etching step, conventional post etch cleaning steps may be performed, as will be apparent to those skilled in the art. The portion of barrier layer 302 that lies underneath via 340 may then be removed and via 340 and trench 350 filled with a conductive material, as described above in connection with FIGS. 2a-2 j. Because barrier layer 302 is not exposed when etching the trench, until the via reaches that layer, the chemistry used to etch the trench need not ensure a high etch rate for dielectric layer 303, when compared to the etch rate for barrier layer 302. No longer constrained by that requirement, the trench etch process may be optimized to yield trenches and vias that have substantially vertical profiles, substantially flat bottom surfaces, and a more controllable depth, without regard for the selectivity that the chosen etch chemistry produces.
FIGS. 4a-4 j illustrate another variation of the process described above in connection with FIGS. 2a-2 j. In this variation, FIG. 4a shows a structure similar to the one shown in FIG. 2a, except that dielectric layer 403 comprises oxide based layer 455 (e.g., a layer that includes silicon dioxide, SiOF, or carbon doped oxide), which is covered by polymer based film 456. Oxide based layer 455 may be formed on barrier layer 402 in the conventional manner (e.g., by a conventional spin on or CVD process), prior to applying film 456 to layer 455 using a conventional spin on process. Film 456 and layer 455 preferably have similar dielectric constants to ensure that line-to-line capacitance will not be compromised, while this hybrid dielectric stack enhances mechanical stability. The FIG. 4b structure may be produced by deposited and patterning a photoresist layer to expose part of layer 409, etching through layer 409 and partially through layer 408, then removing the photoresist, as described above in connection with FIG. 2b. A second layer of photoresist 430 is then deposited and patterned to define the trench to be etched into dielectric layer 403. When patterned, a second part 410 of second hard masking layer 409 is exposed, as shown in FIG. 4c. After photoresist layer 430 is patterned, the exposed second part 410 of second hard masking layer 409 is etched, followed by removing any remaining photoresist, to generate the structure illustrated in FIG. 4d, e.g., by using process steps described above in connection with FIG. 2d. The remaining portion 423 of first hard masking layer 408 is then etched, while retaining part of section 425 of oxide hard mask 408, to produce the structure shown in FIG. 4e. The same process steps described above to produce the structure shown in FIG. 2e may be used here.
After portion 423 is removed, a first part of via 440 is etched through film 456 until it reaches oxide based layer 455, generating the structure shown in FIG. 4f. A plasma generated from a mixture of oxygen, nitrogen, and carbon monoxide may be used to perform that etch step. That process may stop when via 440 reaches layer 455 because of the high selectivity of that etch chemistry to that layer. Following that via etch step, the remaining portion of section 425 of layer 408 is removed—using, for example, a plasma generated by feeding a mixture of C4F8, carbon monoxide, oxygen, nitrogen, and argon into a plasma etcher. That process, in addition to removing the remainder of section 425, etches into the exposed part of oxide based layer 455—extending via 440 to barrier layer 402 and generating the structure shown in FIG. 4g. Trench 450 is then etched into dielectric layer 403 to produce the structure illustrated in FIG. 4h. The same process that was used previously to etch via 440 through polymer based film 456 may be used to etch trench 450 through that film. As with that via etch step, the trench etch process will stop when the trench reaches layer 455 because of the high selectivity of that etch chemistry to that layer. The mechanical strength of the resulting structure is increased by locating the harder oxide based material under the trench, enabling that material to support the trench.
The etch chemistry chosen to etch trench 450 should also be highly selective to barrier layer 402 to ensure that the trench etch step will not etch through that layer. The portion of barrier layer 402 that lies underneath via 440 may then be removed to produce the structure shown in FIG. 4i, and via 440 and trench 450 filled with a conductive material to produce the FIG. 4j structure—as described above in connection with FIGS. 2a-2 j. Using a composite dielectric layer, which enables the trench to be formed within the relatively soft polymer based film and the via to be formed within the harder oxide based layer, should enhance the resulting structure's mechanical integrity, rendering it more durable. That property should enable this structure to withstand stresses that will be applied during device fabrication, testing and packaging. Another benefit from using this composite dielectric layer is that the via profile may be preserved during the trench etch process because of the high selectivity of the etch chemistry to the oxide based layer.
A first part of via 540 may then be etched through film 556 until it reaches oxide based layer 555, generating the structure shown in FIG. 5e. If a plasma formed from a mixture of oxygen, nitrogen, and carbon monoxide is used to perform that etch step, then photoresist layer 530 may be removed at the same time via 540 is etched through layer 556. Following that via etch step, section 525 of layer 508 is removed while etching via 540 through oxide based layer 555 using, for example, the process steps described above in connection with FIG. 4g, to generate the structure shown in FIG. 5f. Trench 550 is then etched into dielectric layer 503 to produce the structure illustrated in FIG. 5g. The same process that was used previously to etch via 540 through polymer based film 556 may be used to etch trench 550 through that film. The portion of barrier layer 502 that lies underneath via 540 may then be removed to produce the structure shown in FIG. 5h, and via 540 and trench 550 filled with a conductive material, as described above in connection with FIGS. 2a-2 j. The improved method for making a semiconductor device of the present invention, which performs via lithography prior to trench lithography to make a dual damascene structure using a multilayer hard mask, increases the alignment budget for via and trench formation. In doing so, such a method enables photoresist to be removed while protecting the dielectric layer. When the dielectric layer includes an oxide based layer that is covered by a polymer based film, the method of the present invention also promotes superior via and trench profiles and increased mechanical strength.
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H01L21/76813European ClassificationH01L21/768B2D8, H01L21/311D, H01L21/768B12, H01L21/768B2D6Legal EventsDateCodeEventDescriptionMar 22, 2001ASAssignmentOwner name: INTEL CORPORATION, CALIFORNIAFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MORROW, PATRICK;LEU, JIHPERNG;JAN, CHIA-HONG;REEL/FRAME:011663/0388Effective date: 20010322May 5, 2006FPAYFee paymentYear of fee payment: 4Jun 21, 2010REMIMaintenance fee reminder mailedNov 12, 2010LAPSLapse for failure to pay maintenance feesJan 4, 2011FPExpired due to failure to pay maintenance feeEffective date: 20101112RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services