Source: http://www.google.com/patents/US6130721?dq=5787449
Timestamp: 2017-01-16 18:44:00
Document Index: 387546347

Matched Legal Cases: ['§19', 'art 250', 'art 290', 'art 250', 'art 250', 'art 250', 'art 250', 'art 250']

Patent US6130721 - Video format mode detector - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA video format mode detector for detecting the format mode of a video signal transmitted from a video data output device such as personal computer, which includes a counter for counting a horizontal synchronous signal input during one cycle of a vertical synchronous signal separated from the video signal,...http://www.google.com/patents/US6130721?utm_source=gb-gplus-sharePatent US6130721 - Video format mode detectorAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS6130721 APublication typeGrantApplication numberUS 09/377,910Publication dateOct 10, 2000Filing dateAug 20, 1999Priority dateAug 20, 1998Fee statusPaidAlso published asCN1164129C, CN1246022APublication number09377910, 377910, US 6130721 A, US 6130721A, US-A-6130721, US6130721 A, US6130721AInventorsJoong-Sun Yoo, Yeon-Mo Jeong, Ju-Soon HongOriginal AssigneeSamsung Electronics Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (7), Referenced by (39), Classifications (10), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetVideo format mode detector
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C §19 from an application entitled Video Format Mode Detector earlier filed in the Korean Industrial Property Office on Aug. 20, 1998, and there duly assigned Serial No. 98-33747 by that Office.
FIG. 2 illustrates a configuration of a VGA format frame having 640×480 resolution;
To help understand the present invention, it is assumed that a video signal with 640×480 resolution is output from a personal computer. FIG. 1 illustrates a configuration of an image processing system including a video format mode detector according to an embodiment of the present invention, FIG. 2 illustrates a configuration of a VGA format frame having 640×480 resolution, and FIG. 3 illustrates one cycles of synchronous signals, having polarities opposite to each other. A video signal output from a personal computer 100, that is an output signal of a video card included in the computer, consists of R(Red), G(Green), B(Blue) color signals, ground signals for these color signals, a horizontal synchronous signal H-- Sync constructing the lines of a picture, and a vertical synchronous signal V-- Sync constructing a frame or field of a picture. This video signal is sent to a video format mode detector 200 (referred to as "mode detector" hereinafter) through video card output pins included in personal computer 100 as shown in FIG. 1. Mode detector 200 detects the format mode of the video signal received from computer 100 using the horizontal synchronous signal H-- Sync and the vertical synchronous signal V-- Sync and a reference clock signal having a specific frequency, and generates corresponding mode detection signal. A scan format converter 300 converts the format of the R, G, B data of the video signal with 640×480 resolution to meet the resolution of a display device according to the mode detection signal sent from mode detector 200. The format-converted video signals (1) and (2) are displayed on the display device, TV 400 or monitor 500. For reference, horizontal synchronous signal H Sync and vertical synchronous signal V-- Sync of a video signal output from the video card using 18 M, VESA standard are applied to mode detector 200 through the thirteenth and fourteenth pins, respectively. Here, horizontal synchronous signal H-- Sync and vertical synchronous signal V-- Sync are output as digital signals. There will be explained below the configuration of a VGA format frame with 640×480 resolution with reference to FIG. 2. One picture (frame) is constructed of 525 lines, each line being synchronized with horizontal synchronous signal H-- Sync. Picture elements (pixels) construct each of the 525 lines. With VGA mode, there are 704 pixels in one line and 96 pixels in the synchronous part of the line. Accordingly, 800 pixel clocks (referred to as PCLK) are included in one cycle of horizontal sync signal H-- Sync. For one cycle of pixel clock PCLK, data processing is performed for R, G, B of one pixel constructing a picture. One cycle of horizontal synchronous signal H-- Sync includes a right border, left border, front porch and back porch which have no picture data. The number of pixels corresponding to these parts and number of pixels corresponding to the synchronous part are subtracted from the total number of pixels included in one cycle of horizontal synchronous signal H-- Sync, resulting in 640 pixels which make a visible line, a part having picture data. Vertical synchronous signal V-- Sync includes the top border, bottom border, front porch and back porch which are constructed of lines having no picture data. The number of lines corresponding to these parts and number of lines corresponding to the synchronous part are subtracted from the total number of lines included in one cycle of vertical synchronous signal V-- Sync, resulting in 480 lines which construct a visible frame.
As described above, the visible frame constructed of 640 pixels and 480 lines corresponds to a 640×480 mode which depends on various standards specified by IBM, VESA, SIGMA and MAC. Furthermore, characteristics of components forming a picture differ from frequencies used. The horizontal and vertical synchronous signals have different polarities depending on manufacturers, as shown in FIG. 3, while they are fixed in accordance with standards. In FIG. 3, reference numeral (3) represents a positive synchronous signal, (4) represents a negative synchronous signal, and T represents one cycle of a synchronous signal. Since the polarity of the synchronous signal depends on the manufacturer, an algorithm for detecting the video signal format using the synchronous signal becomes complicated. Therefore, the present invention constructs a mode detector which is able to detect the format mode of a video signal only using a simple circuit configuration employing the synchronous signals and reference clock as its input without regard to the polarity of the synchronous signals.
Data comparator 240 compares positive holding data Po-- HD and negative holding data Ne-- HD sent from data holder 220 with each other, to output data having the smaller value. Accordingly, data comparator 240 outputs the number of horizontal lines H-- sync cnt which is counted during "HIGH" period (that is, synchronous period) of the vertical synchronous signal. Mode discrimination part 250 searches the ROM table included therein, to generate a mode detection signal corresponding to data sent from data adder 230 and data comparator 240, that is, the total number of horizontal lines included in one cycle of vertical synchronous signal V-- sync and number of lines counted during the synchronous period. Therefore, scan format converter 300 shown in FIG. 1 converts VGA mode with resolution of 640×480, sent from personal computer 100, into a video format corresponding to the resolution of TV 400 or monitor 500 depending on the mode detection signal.
Data holder 270 holds the time data of counter 260 whenever the reference clock is applied through its clock port CLK. Data comparator 280 compares the time data held, outputting data having the smaller value. Mode discrimination part 290 searches an ROM table included therein to detect a video format mode corresponding to the time data sent from data comparator 280, generating corresponding mode detection signal. Accordingly, scan format converter 300 shown in FIG. 1 converts VGA mode with 640×480 resolution transmitted from personal computer 100 into a video format corresponding to the resolution of TV 400 or monitor 500 depending on the mode detection signal.
FIG. 6 illustrates the configuration of video format mode detector 200 according to another embodiment of the present invention, which is constructed by combining the video format mode detectors of FIGS. 4 and 5 with each other. Referring to FIG. 6, a first counter 210 counts horizontal synchronous signal H-- sync during which vertical synchronous signal V-- sync is in "HIGH" and "LOW" states, generating positive counting data Po-- cnt and negative counting data Ne-- cnt. A first data holder 220 holds the positive counting data Po-- cnt and negative counting data Ne-- cnt for each event of horizontal synchronous signal H-- sync input through its clock port CLK. Data adder 230 adds up positive holding data Po-- HD and negative holding data Ne-- HD generated by first data holder 220 whenever horizontal synchronous signal H-- sync is applied thereto. By doing so, data adder 230 outputs data Ls indicating the total number of horizontal lines corresponding to one cycle of vertical synchronous signal V-- sync. A first comparator 295A constructing a data comparator 295 compares positive holding data Po-- HD and negative holding data Ne-- HD sent from first data holder 220 with each other, outputting data having the smaller value. Accordingly, data comparator 295 outputs the number of horizontal lines H-- sync cnt counted for "HIGH" period (that is, synchronous period) of the vertical synchronous signal. Mode discrimination part 250 searches a ROM table included therein, generating a mode detection signal corresponding to data sent from data adder 230 and data comparator 295, that is, the total number of horizontal lines H-- sync cnt included in one cycle of the vertical synchronous signal and the number of lines Ls counted for the synchronous period. A second counter 260 counts the synchronous period of horizontal synchronous signal H-- sync separated from the input video signal with 25 MHz reference clock, generating positive counting data Po-- cnt and negative counting data Ne-- cnt which correspond to time data of the synchronous period of the horizontal synchronous signal. A second data holder 270 holds the time data of second counter 260 whenever the reference clock applied to its clock port CLK. A second comparator 295B included in data comparator 295 compares the holding time data with each other, outputting data having the smaller value. In this embodiment, though the data from the first comparator is sent to mode discrimination part 250, it is possible to design the mode detector in such a manner that the output data of the first and second comparators are selectively applied to mode discrimination part 250. If the output data from the second comparator is sent to mode discrimination part 250, mode discrimination part 250 searches the ROM table included therein to detect a video format mode corresponding to the time data sent from data comparator 295, generating corresponding mode detection signal. Therefore, scan format converter 300 shown in FIG. 1 can convert VGA mode with 640×480 resolution transmitted from personal computer 100 into a video format corresponding to the resolution of TV 400 or monitor 500.
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Classification348/558, 348/E05.114, 348/524International ClassificationH04N5/46, G09G5/00, H04N5/08Cooperative ClassificationG09G5/006, H04N5/46European ClassificationG09G5/00T4, H04N5/46Legal EventsDateCodeEventDescriptionAug 3, 2000ASAssignmentOwner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OFFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOO, JOONG-SUN;JEONG, YEON-MO;HONG, JU-SOON;REEL/FRAME:011057/0583Effective date: 20000626Mar 10, 2004FPAYFee paymentYear of fee payment: 4Mar 13, 2008FPAYFee paymentYear of fee payment: 8Mar 19, 2012FPAYFee paymentYear of fee payment: 12RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services