Source: https://encrypted.google.com/patents/US9141829
Timestamp: 2018-04-25 08:36:53
Document Index: 681284091

Matched Legal Cases: ['Application No. 12165501', 'Application No. 12165519', 'Application No. 12165501', 'Application No. 12165519', 'Application No. 12165494', 'Application No. 12165501', 'Application No. 12165515', 'Application No. 2011', 'application No. 200710140450', 'Application No. 2004']

Patent US9141829 - Secure processor and a program for a secure processor - Google Patents
The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform...https://www.google.com/patents/US9141829?utm_source=gb-gplus-sharePatent US9141829 - Secure processor and a program for a secure processor
Publication number US9141829 B2
Application number US 14/091,479
Also published as CN1722046A, CN100361039C, CN101174290A, CN101174290B, CN101178758A, CN101178758B, EP1632835A2, EP1632835A3, EP1632835B1, EP2482222A2, EP2482222A3, EP2482222B1, EP2490146A2, EP2490146A3, EP2490146B1, EP2490147A2, EP2490147A3, EP2490147B1, EP2490148A2, EP2490148A3, EP2490148B1, US7865733, US8886959, US9536110, US9652635, US9672384, US20060015748, US20110167278, US20140082371, US20140089676, US20140089680, US20140089681, US20170046538, US20170046539
Publication number 091479, 14091479, US 9141829 B2, US 9141829B2, US-B2-9141829, US9141829 B2, US9141829B2
Inventors Seijo Goto, Jun Kamada, Taijji TAMIYA
Patent Citations (58), Non-Patent Citations (29), Referenced by (1), Classifications (23), Legal Events (2)
US 9141829 B2
an execution unit configured to output a first virtual address;
a mode register configured to indicate whether the processor is in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited; and
a memory access control unit configured to output a first physical address corresponding to the first virtual address by referring to either a first translation look aside buffer for the first mode or a second translation look aside buffer for the second mode in accordance with a value of the mode register,
wherein, by executing a first instruction code stored in the secure address space in the first mode, a second instruction code is checked in the first mode before the second instruction code is executed in the second mode, and
wherein, in the second mode, the memory access control unit prohibits an access to a physical address within the secure address space in accordance with the second translation look aside buffer.
wherein the first instruction code is stored in a non-rewritable memory.
wherein a mode switching between the first mode and the second mode is triggered by an interruption.
4. The processor according to claim 3,
wherein the mode register is set in response to the interruption.
wherein each of the first translation look aside buffer and the second translation look aside buffer includes a plurality of page table entries and each of the page table entries includes a physical address, a virtual address corresponding to the physical address, and an identifier that each indicate the first mode or the second mode.
wherein the second instruction code is executed in the second mode after the second instruction code is checked.
7. The processor according to claim 1,
wherein the first mode is a secure mode and the second mode is a normal mode.
8. A processor connprising:
wherein, by executing a first instruction code stored in the secure address space in the first mode, an second instruction code is checked in the first mode, and the second instruction code is executed in the second mode after the second instruction code is checked, and
9. The processor according to claim 8,
11. The processor according to claim 8,
When a processing starts in FIG. 63, the following procedures are taken. Using the program operated on the core 154, generally by the transfer management unit 157 which received instructions such as the transfer source address from the OS. The data reader 158 is instructed to read the next 64 byte data from the I/O device 102, and the 64 byte data are read by the data reader 158 at Step S111. The hash operator 159 is instructed to perform hash operation by the transfer management unit 157 at Step S112 and the hash operation is performed by the hash operator 159 at Step S113. The interim results are retained and, a data write 160 is instructed to write 64 byte data to the physical memory 101 is instructed by the transfer management unit 157 at Step S114 and the 64 byte data are written in the physical memory 101 by the data writer 160 at Step S115. Whether or not the data transfer of one page is completed is determined at Step S116. If it is not completed, the processes from Step S110 are repeated, whereas if it is completed, a pair of hash values and the physical page top address as a transfer destination address is given by the transfer management unit 157 to a retention unit 161 to end the processing.
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International Classification G06F21/57, G06F21/72, G06F12/14, G06F21/64, G06F11/30, G06F21/55, G06F21/70, G06F21/71, G06F21/52
Cooperative Classification G06F21/70, G06F21/74, G06F2212/682, G06F2212/1052, G06F13/24, G06F12/1027, G06F21/53, G06F21/575, G06F21/52, G06F21/72, G06F21/554, G06F21/71, G06F12/1408, G06F21/64