Source: https://patents.google.com/patent/US9886277B2/en
Timestamp: 2020-08-15 18:20:43
Document Index: 444410666

Matched Legal Cases: ['Application No. 1402853', 'Application No. 2014026125', 'Application No. 2014', 'Application No. 201410097060', 'Application No. 10201429227', 'Application No. 10201429227']

US9886277B2 - Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources - Google Patents
Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources Download PDF
US9886277B2
US9886277B2 US13/842,754 US201313842754A US9886277B2 US 9886277 B2 US9886277 B2 US 9886277B2 US 201313842754 A US201313842754 A US 201313842754A US 9886277 B2 US9886277 B2 US 9886277B2
US13/842,754
US20140281389A1 (en
2013-03-15 Priority to US13/842,754 priority Critical patent/US9886277B2/en
2013-08-05 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LOKTYUKHIN, MAXIM, CHARNEY, MARK J., HORN, JULIAN C., VALENTINE, ROBERT
2014-09-18 Publication of US20140281389A1 publication Critical patent/US20140281389A1/en
2018-02-06 Publication of US9886277B2 publication Critical patent/US9886277B2/en
230000001419 dependent Effects 0.000 claims abstract description 21
238000005265 energy consumption Methods 0.000 description 7
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239000003607 modifiers Substances 0.000 description 1
Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition. A portion of the plurality of instructions are fused into a single micro-operation, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction. Some embodiments generate a novel test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the novel test instruction through a just-in-time compiler. Some embodiments also fuse the novel test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.
The present disclosure pertains to the field of processing logic, microprocessors, and associated instruction set architecture that, when executed by the processor or other processing logic, perform logical, mathematical, or other functional operations. In particular, the disclosure relates to methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources.
Modern processors may include micro-architectural structures and techniques to improve processing performance and/or make use of specialized instructions. These micro-architectural structures and techniques may include, for example, out-of-order execution, decoders for fusing macro-instructions into a fused instruction, micro-instruction or micro-operation (or micro-op, “uop”) cache, or trace cache, or queue for processing compressed and/or fused instructions or micro-ops.
Instruction fusion is a dynamic process that combines two instructions into a single instruction which results in a one operation, micro-operation, sequence within a processor at runtime. Instructions stored in a processor instruction queue (IQ) may be “fused” after being read out of the IQ and before being sent to instruction decoders or after being decoded by the instruction decoders. Typically, instruction fusion occurring before the instruction is decoded is referred to as “macro-fusion”, whereas instruction fusion occurring after the instruction is decoded (into uops, for example) is referred to as “micro-fusion”. An example of macro-fusion is the combining of a compare (“CMP”) instruction or test instruction (“TEST”) (“CMP/TEST”) with a conditional jump (“JCC”) instruction. CMP/TEST and JCC instruction pairs may occur regularly in programs at the end of loops, for example, where a comparison is made and, based on the outcome of a comparison, a branch is taken or not taken. Since macro-fusion may effectively increase instruction throughput, it may be desirable to find as many opportunities to fuse instructions as possible.
Web browsers may include support for one or more interpreted computer programming language so that client-side scripts may interact with a user, control the browser, communicate asynchronously and alter document content as it is displayed, etc. An interpreted computer programming or scripting language, for example such as JavaScript, JScript or ECMAScript, may be dynamic and weakly typed and may support object-oriented, imperative and functional programming styles. Such interpreted computer programming languages may find browser support in the form of a just-in-time (JIT) compiler, which dynamically compiles the interpreted language into machine instruction sequences. JIT compilers may optimize stored values for faster processing, but then need to dynamically test the types of objects for such optimizations during runtime. These dynamic tests can introduce additional processing overhead requiring higher energy consumption and also limiting any performance advantages of such optimizations.
To date, potential solutions to such performance limiting issues, energy consumption worries, and other runtime bottlenecks have not been adequately explored.
FIG. 1A is a block diagram of one embodiment of a system that executes instructions to provide OR-test and AND-test functionality on multiple test sources.
FIG. 1B is a block diagram of another embodiment of a system that executes instructions to provide OR-test and AND-test functionality on multiple test sources.
FIG. 1C is a block diagram of another embodiment of a system that executes instructions to provide OR-test and AND-test functionality on multiple test sources.
FIG. 2 is a block diagram of one embodiment of a processor that executes instructions to provide OR-test and AND-test functionality on multiple test sources.
FIG. 3D illustrates an instruction encoding to provide OR-test and AND-test functionality on multiple test sources according to one embodiment.
FIG. 3E illustrates an instruction encoding to provide OR-test and AND-test functionality on multiple test sources according to another embodiment.
FIG. 3F illustrates an instruction encoding to provide OR-test and AND-test functionality on multiple test sources according to another embodiment.
FIG. 3G illustrates an instruction encoding to provide OR-test and AND-test functionality on multiple test sources according to another embodiment.
FIG. 3H illustrates an instruction encoding to provide OR-test and AND-test functionality on multiple test sources according to another embodiment.
FIG. 4A illustrates elements of one embodiment of a processor micro-architecture to execute instructions that provide OR-test and AND-test functionality on multiple test sources.
FIG. 4B illustrates elements of another embodiment of a processor micro-architecture to execute instructions that provide OR-test and AND-test functionality on multiple test sources.
FIG. 5 is a block diagram of one embodiment of a processor to execute instructions that provide OR-test and AND-test functionality on multiple test sources.
FIG. 6 is a block diagram of one embodiment of a computer system to execute instructions that provide OR-test and AND-test functionality on multiple test sources.
FIG. 7 is a block diagram of another embodiment of a computer system to execute instructions that provide OR-test and AND-test functionality on multiple test sources.
FIG. 8 is a block diagram of another embodiment of a computer system to execute instructions that provide OR-test and AND-test functionality on multiple test sources.
FIG. 9 is a block diagram of one embodiment of a system-on-a-chip to execute instructions that provide OR-test and AND-test functionality on multiple test sources.
FIG. 10 is a block diagram of an embodiment of a processor to execute instructions that provide OR-test and AND-test functionality on multiple test sources.
FIG. 11 is a block diagram of one embodiment of an IP core development system that provides OR-test and AND-test functionality on multiple test sources.
FIG. 12 illustrates one embodiment of an architecture emulation system that provides OR-test and AND-test functionality on multiple test sources.
FIG. 13 illustrates one embodiment of a system to translate instructions that provide OR-test and AND-test functionality on multiple test sources.
FIG. 14 illustrates elements of one alternative embodiment of a processor micro-architecture to fuse instructions to provide OR-test and AND-test functionality on multiple test sources.
FIG. 15A illustrates a flow diagram for one embodiment of a fused instruction structure to provide OR-test and AND-test functionality on multiple test sources.
FIG. 15B illustrates a flow diagram for an alternative embodiment of a fused instruction structure to provide OR-test and AND-test functionality on multiple test sources.
FIG. 15C illustrates a flow diagram for another alternative embodiment of a fused instruction structure to provide OR-test and AND-test functionality on multiple test sources.
FIG. 16A illustrates a flow diagram for one embodiment of a process to fuse instructions to provide OR-test and AND-test functionality on multiple test sources.
FIG. 16B illustrates a flow diagram for an alternative embodiment of a process to fuse instructions to provide OR-test and AND-test functionality on multiple test sources.
FIG. 16C illustrates a flow diagram for another alternative embodiment of a process to fuse instructions to provide OR-test and AND-test functionality on multiple test sources.
FIG. 16D illustrates a flow diagram for another alternative embodiment of a process to fuse instructions to provide OR-test and AND-test functionality on multiple test sources.
FIG. 17 illustrates a flow diagram for an embodiment of a process to execute instructions to provide OR-test and AND-test functionality on multiple test sources.
The following description discloses fusible instructions and logic to provide OR-test and AND-test functionality on multiple test sources within or in association with a processor, computer system, or other processing apparatus.
Web browsers may include support for one or more interpreted computer programming language, for example such as JavaScript, JScript or ECMAScript, which may be dynamic and weakly typed and may support object-oriented, imperative and functional programming styles. Such interpreted computer programming languages may find browser support in the form of a just-in-time (JIT) compiler, which dynamically compiles the interpreted language into machine instruction sequences. JIT compilers may optimize stored values for faster processing, but may then need to dynamically test the types of objects for such optimizations during runtime. For example, JIT compilers may use one or more bits of the machine word to distinguish and/or designate that a value is an optimized integer, rather than a more generic floating point value or string. The presence of these one or more bits can be dynamically checked at runtime before accessing the value. Such dynamic type tests can introduce additional processing overhead in the form of frequently executed type testing instruction sequence idioms, requiring higher energy consumption and limiting any performance advantages of such compiler optimizations.
These frequently executed instruction sequence idioms may include a logical operation to combine two source data operands (e.g. OR when testing if bits in either source are one, AND when testing if bits in either source are zero); a compare or test instruction (e.g. to TEST the result of the logical operation against a mask); and a conditional branch (e.g. JZ/JNZ to jump to a slower generic code sequence if the zero flag was set/not-set by TEST). Processor decode logic may make use of macro-fusion in the combining of a compare instruction or test instruction (e.g. TEST) with a conditional branch instruction (e.g. JZ).
Embodiments of methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition. A portion of the plurality of instructions are fused into a single micro-operation, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction. Some embodiments generate a novel test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction dynamically, but through the JIT compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction (e.g. JZ), and perform a branch according to how the condition flag is set. Thus, a frequently executed instruction sequence idiom may be fusible into a single instruction which results in a one micro-operation sequence within the processor at runtime.
It will be appreciated that fusible instructions and logic to provide OR-test and/or AND-test functionality on multiple test sources may all but eliminate performance limitation issues, energy consumption worries and other runtime bottlenecks associated with frequently executed type testing instruction idioms generated by the JIT compilers.
FIG. 1C illustrates another alternative embodiments of a data processing system capable of executing instructions to provide OR-test and AND-test functionality on multiple test sources. In accordance with one alternative embodiment, data processing system 160 may include a main processor 166, a SIMD coprocessor 161, a cache memory 167, and an input/output system 168. The input/output system 168 may optionally be coupled to a wireless interface 169. SIMD coprocessor 161 is capable of performing operations including instructions in accordance with one embodiment. Processing core 170 may be suitable for manufacture in one or more process technologies and by being represented on a machine readable media in sufficient detail, may be suitable to facilitate the manufacture of all or part of data processing system 160 including processing core 170.
FIG. 2 is a block diagram of the micro-architecture for a processor 200 that includes logic circuits to perform instructions in accordance with one embodiment of the present invention. In some embodiments, an instruction in accordance with one embodiment can be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc., as well as datatypes, such as single and double precision integer and floating point datatypes. In one embodiment the in-order front end 201 is the part of the processor 200 that fetches instructions to be executed and prepares them to be used later in the processor pipeline. The front end 201 may include several units. In one embodiment, the instruction prefetcher 226 fetches instructions from memory and feeds them to an instruction decoder 228 which in turn decodes or interprets them. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called “microinstructions” or “micro-operations” (also called micro op or uops) that the machine can execute. In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that are used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, the trace cache 230 takes decoded uops and assembles them into program ordered sequences or traces in the uop queue 234 for execution. When the trace cache 230 encounters a complex instruction, the microcode ROM 232 provides the uops needed to complete the operation.
The execution block 211 contains the execution units 212, 214, 216, 218, 220, 222, 224, where the instructions are actually executed. This section includes the register files 208, 210, that store the integer and floating point data operand values that the microinstructions need to execute. The processor 200 of one embodiment is comprised of a number of execution units: address generation unit (AGU) 212, AGU 214, fast ALU 216, fast ALU 218, slow ALU 220, floating point ALU 222, floating point move unit 224. For one embodiment, the floating point execution blocks 222, 224, execute floating point, MMX, SIMD, and SSE, or other operations. The floating point ALU 222 of one embodiment includes a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. For embodiments of the present invention, instructions involving a floating point value may be handled with the floating point hardware. In one embodiment, the ALU operations go to the high-speed ALU execution units 216, 218. The fast ALUs 216, 218, of one embodiment can execute fast operations with an effective latency of half a clock cycle. For one embodiment, most complex integer operations go to the slow ALU 220 as the slow ALU 220 includes integer execution hardware for long latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. Memory load/store operations are executed by the AGUs 212, 214. For one embodiment, the integer ALUs 216, 218, 220, are described in the context of performing integer operations on 64 bit data operands. In alternative embodiments, the ALUs 216, 218, 220, can be implemented to support a variety of data bits including 16, 32, 128, 256, etc. Similarly, the floating point units 222, 224, can be implemented to support a range of operands having bits of various widths. For one embodiment, the floating point units 222, 224, can operate on 128 bits wide packed data operands in conjunction with SIMD and multimedia instructions.
In one embodiment, the uops schedulers 202, 204, 206, dispatch dependent operations before the parent load has finished executing. As uops are speculatively scheduled and executed in processor 200, the processor 200 also includes logic to handle memory misses. If a data load misses in the data cache, there can be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations need to be replayed and the independent ones are allowed to complete. The schedulers and replay mechanism of one embodiment of a processor are also designed to catch instructions that provide OR-test and AND-test functionality on multiple test sources.
Turning next to FIG. 3G is a depiction of another alternative operation encoding (opcode) format 397, to provide OR-test and AND-test functionality on multiple test sources according to another embodiment, corresponding with a type of opcode format described in the “Intel® Advanced Vector Extensions Programming Reference,” which is available from Intel Corp., Santa Clara, Calif. on the world-wide-web (www) at intel.com/products/processor/manuals/.
Opcode format 397 corresponds with opcode format 370 and comprises optional VEX prefix bytes 391 (beginning with C4 hex in one embodiment) to replace most other commonly used legacy instruction prefix bytes and escape codes. For example, the following illustrates an embodiment using two fields to encode an instruction, which may be used when a second escape code is present in the original instruction, or when extra bits (e.g., the XB and W fields) in the REX field need to be used. In the embodiment illustrated below, legacy escape is represented by a new escape value, legacy prefixes are fully compressed as part of the “payload” bytes, legacy prefixes are reclaimed and available for future expansion, the second escape code is compressed in a “map” field, with future map or feature space available, and new features are added (e.g., increased vector length and an additional source register specifier).
Turning next to FIG. 3H is a depiction of another alternative operation encoding (opcode) format 398, to provide OR-test and AND-test functionality on multiple test sources according to another embodiment. Opcode format 398 corresponds with opcode formats 370 and 397 and comprises optional EVEX prefix bytes 396 (beginning with 62 hex in one embodiment) to replace most other commonly used legacy instruction prefix bytes and escape codes and provide additional functionality. An instruction according to one embodiment may be encoded by one or more of fields 396 and 392. Up to four operand locations per instruction and a mask may be identified by field 396 in combination with source operand identifiers 374 and 375 and in combination with an optional scale-index-base (SIB) identifier 393, an optional displacement identifier 394, and an optional immediate byte 395. For one embodiment, EVEX prefix bytes 396 may be used to identify 32-bit or 64-bit source and destination operands and/or 128-bit, 256-bit or 512-bit SIMD register or memory operands. For one embodiment, the functionality provided by opcode format 398 may be redundant with opcode formats 370 or 397, whereas in other embodiments they are different. Opcode format 398 allows register to register, memory to register, register by memory, register by register, register by immediate, register to memory addressing, with masks, specified in part by MOD field 373 and by optional (SIB) identifier 393, an optional displacement identifier 394, and an optional immediate byte 395. The general format of at least one instruction set (which corresponds generally with format 360 and/or format 370) is illustrated generically by the following:
For one embodiment an instruction encoded according to the EVEX format 398 may have additional “payload” bits that may be used to provide OR-test and AND-test functionality on multiple test sources with additional new features such as, for example, a user configurable mask register, or an additional operand, or selections from among 128-bit, 256-bit or 512-bit vector registers, or more registers from which to select, etc.
For example, where VEX format 397 may be used to provide OR-test and AND-test functionality on multiple test sources with an implicit mask, the EVEX format 398 may be used to provide OR-test and AND-test functionality on multiple test sources with an explicit user configurable mask. Additionally, where VEX format 397 may be used to provide OR-test and AND-test functionality on multiple test sources on 128-bit or 256-bit vector registers, EVEX format 398 may be used to provide OR-test and AND-test functionality on multiple test sources on 128-bit, 256-bit, 512-bit or larger (or smaller) vector registers.
Example fusible instructions to provide OR-test and AND-test functionality on multiple test sources are illustrated by the following examples:
source source source Instruction destination 1 2 3 description OR-test Zero-flag Reg1 Reg2/Mem Imm8/Imm32 Perform a bit-wise logical OR between the data from the Reg1 and the Reg2/Mem operands, and perform a bit-wise logical AND between the result of the logical OR and the Imm8/Imm32 operand; set the Zero-flag according to the result of the logical AND. AND-test Zero-flag Reg1 Reg2/Mem Imm8/Imm32 Perform a bit-wise logical AND between the data from the Reg1 and the Reg2/Mem operands, and perform another bit-wise logical AND between the Imm8/Imm32 operand and the result of the first logical AND; set the Zero-flag according to the result of the second logical AND.
It will be appreciated that fusible instructions and logic to provide OR-test and/or AND-test functionality on multiple test sources, as in the examples above, may be used to all but eliminate performance limitation issues, energy consumption worries and other runtime bottlenecks associated with frequently executed type testing instruction idioms generated by the JIT compilers that support one or more interpreted computer programming language, for example such as JavaScript, JScript or ECMAScript, which may be dynamic and weakly typed and may support object-oriented, imperative and functional programming styles.
The front end unit 430 includes a branch prediction unit 432 coupled to an instruction cache unit 434, which is coupled to an instruction translation lookaside buffer (TLB) 436, which is coupled to an instruction fetch unit 438, which is coupled to a decode unit 440. The decode unit or decoder may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decoder may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The instruction cache unit 434 is further coupled to a level 2 (L2) cache unit 476 in the memory unit 470. The decode unit 440 is coupled to a rename/allocator unit 452 in the execution engine unit 450.
FIG. 14 illustrates elements of one alternative embodiment of a processor micro-architecture to fuse instructions to provide OR-test and AND-test functionality on multiple test sources. Embodiments of processor micro-architecture 1400 may be part of a pipeline 400 or part of a core 490 (e.g. front end unit 430 and execution engine unit 450) for execution of an instruction to provide OR-test and AND-test functionality on multiple test sources. Embodiments of apparatus 1400 may be coupled with a decode stage (e.g. decode 406) or a decoder (e.g. decode unit 440) to decode an instruction to provide OR-test and AND-test functionality on multiple test sources, the instruction specifying a first source data operand, a second source data operand, a third source data operand, and an operation type. One or more execution units (e.g. an execution unit 462 and/or an execution unit 464) responsive to the decoded instruction, perform a first logical operation, according to the specified operation type (e.g. a bitwise logical OR, or a bitwise logical AND), between data from the first and second source data operands, and perform a second logical operation (e.g. a test operation, or non-destructive bitwise logical AND) between the data from the third source data operand and the result of the first logical operation to set a condition flag.
For example, embodiments of processor pipeline 1400 include a fetch stage 1402, an instruction queue stage 1403, a length decoding stage 1404, a macro-instruction fusion stage 1405, a decode stage 1406, a micro-op storage stage 1407, a micro-op fusion stage 1411, a scheduling (also known as a dispatch or issue) stage 1412, an execute stage 1416, and a write back/memory write stage 1418. Embodiments of processor pipeline 1400 may also include other pipeline stages (not shown in this illustration) that are not necessary to understand the functional aspects of processor pipeline 1400, with regard to fusing instructions to provide OR-test and AND-test functionality on multiple test sources.
For some embodiments of processor pipeline 1400, when decode stage 1406 decodes the first instruction to provide OR-test or AND-test functionality on multiple test sources, it fuses the first instruction with a branch instruction identified as fusible with the first instruction from the instruction queue stage 1403 by macro-instruction fusion stage 1405 and produces a single fused micro-operation to store in micro-op storage stage 1407 for execution in processor pipeline 1400.
For some alternative embodiments of processor pipeline 1400, fetch stage 1402 may fetch a number of instructions including: a first logical instruction (e.g. a bitwise logical OR, or a bitwise logical AND instruction) specifying a first operand destination; a second instruction (e.g. a bitwise logical AND, or a non-destructive test instruction) specifying a second operand source; and a third instruction (e.g. a jump-zero, JZ, jump-not-zero, JNZ, or some other jump-condition-code, JCC, instruction) specifying a branch condition. Fetch stage 1402 stores the instructions to instruction queue stage 1403, where pre-decoding logic of length decoding stage 1404 and macro-instruction fusion stage 1405 determine the instruction boundaries and identify fusible instructions for decoding in decode stage 1406. Decode stage 1406 may fuse a portion of the instructions into a single micro-operation, that portion including both the first and second instructions if the first operand destination and said second operand source are the same (e.g. a single register) and said branch condition is dependent upon the second instruction (e.g. if the second instruction is the last instruction to modify the condition code used by the third instruction as a branch condition). For some embodiments the portion being fused may include the first, second and third instructions (e.g. if the first operand destination and said second operand source are the same, the second and third instructions are sequential, and the second instruction is a test instruction). For some alternative embodiments the portion being fused may include only the first and second instructions, wherein the decode stage 1406 decodes the first and second instructions into a single micro-operation to provide OR-test or AND-test functionality on multiple test sources to be stored in micro-op storage stage 1407 for execution in processor pipeline 1400.
In some alternative embodiments of processor pipeline 1400, micro-op storage stage 1407 may also be coupled with a micro-op fusion stage 1411 to fuse a second micro-operation for said third instruction with said single first micro-operation if the branch condition is dependent upon the single first micro-operation to provide OR-test or AND-test functionality on multiple test sources. In such an embodiment scheduling stage 1412 may receive just one fused micro-operation to issue to execute stage 1416 and then to write back/memory write stage 1418, that one fused micro-operation to provide OR-test or AND-test functionality on multiple test sources and branching according to the result.
Some frequently executed instruction sequence idioms may include a logical operation to combine two source data operands (e.g. OR when testing if bits in either source are one, AND when testing if bits in either source are zero); a compare or test instruction (e.g. to TEST the result of the logical operation against a mask); and a conditional branch (e.g. JZ/JNZ to jump to a slower generic code sequence if the zero flag was set/not-set by TEST). Processor decode logic may make use of macro-fusion in the combining of a compare instruction or test instruction (e.g. TEST) with a conditional branch instruction (e.g. JZ).
Some embodiments may also generate the test instruction dynamically by fusing one logical instruction (e.g. OR) with a prior-art test instruction. Other embodiments generate the test instruction dynamically, but through a JIT compiler. Some embodiments may also fuse the test instruction with a subsequent conditional branch instruction (e.g. JZ), and perform a branch according to how the condition flag is set. Thus, a frequently executed instruction sequence idiom may be fusible into a single instruction which results in a one micro-operation sequence within the processor at runtime.
FIG. 15A illustrates a flow diagram for one embodiment of a fused instruction structure 1501 to provide OR-test and AND-test functionality on multiple test sources. A first logical instruction (e.g. a bitwise logical OR, or a bitwise logical AND instruction) specifying a first operand destination, TEMP, and a second instruction (e.g. a non-destructive TEST instruction) specifying a second operand source, TEST, are stored (e.g. by fetch stage 1402) in an instruction queue, IQ 1510. A third instruction 1514 (e.g. a jump-condition-code, JCC, instruction) specifying a branch condition, is also stored in IQ 1510 (e.g. in instruction queue stage 1403). Pre-decoding logic (e.g. of length decoding stage 1404 and macro-instruction fusion stage 1405) determines the instruction boundaries and identifies fusible instructions 1512 for decoding (e.g. in decode stage 1406). During decode (e.g. in decode stage 1406) a portion of the instructions (e.g. instructions 1512) may be fused into a single micro-operation 1522, the portion including both the first and second instructions 1512 if the first operand destination and said second operand source are the same (e.g. a single register, TEMP) and the branch condition code (CC) is dependent upon the second instruction (e.g. if the second instruction is the last instruction to modify the CC used by the third instruction as a branch condition). For some alternative embodiments the portion being fused may include only the first and second instructions 1512, wherein the processor decodes the first and second instructions 1512 into a single micro-operation 1522 to provide OR-test or AND-test functionality on multiple test sources to be stored in micro-op storage 1520 (e.g. in micro-op storage stage 1407 for execution in processor pipeline 1400). In some embodiments, micro-op storage 1520 may also be coupled with micro-op fusion logic to fuse a second micro-operation 1524 for said third instruction 1514 with said single first micro-operation 1522 (e.g. in a micro-op fusion stage 1411) if the branch condition is dependent upon the single first micro-operation 1522 to provide OR-test or AND-test functionality on multiple test sources. In such an embodiment one fused micro-operation 1526 may be stored back to micro-op storage 1520 (e.g. for execution in processor pipeline 1400), that one fused micro-operation 1526 to provide OR-test or AND-test functionality on multiple test sources and branching according to the resulting CC.
For some embodiments the portion being fused may include the first, second and third instructions (e.g. if the first operand destination and said second operand source are the same, the second and third instructions are sequential, and the second or middle instruction is a test instruction).
FIG. 15B illustrates a flow diagram for an alternative embodiment of a fused instruction structure 1502 to provide OR-test and AND-test functionality on multiple test sources and branching according to the resulting CC. A first logical instruction (e.g. a bitwise logical OR, or a bitwise logical AND instruction) specifying a first operand destination, TEMP, a second instruction (e.g. a non-destructive TEST instruction) specifying a second operand source, TEST, and a third instruction (e.g. a jump-condition-code, JCC, instruction) specifying a branch condition, are stored in IQ 1510 (e.g. in instruction queue stage 1403 by fetch stage 1402). Pre-decoding logic (e.g. of length decoding stage 1404 and macro-instruction fusion stage 1405) determines the instruction boundaries and identifies fusible instructions 1516 for decoding (e.g. in decode stage 1406). During decode (e.g. in decode stage 1406) a portion of the instructions (e.g. instructions 1516) may be fused into a single micro-operation 1526, the portion including the first, second and third instructions 1516 if the first operand destination, and second operand source are the same (e.g. TEMP), the second (e.g. TEST) and third (e.g. JCC) instructions are sequential, and the second or middle instruction is an instruction such as TEST, which modifies the branch CC as a result of execution (e.g. in processor pipeline 1400).
For some embodiments the processor instruction set architecture (ISA) may provide an alternative type of macro-instruction, TEST2, to provide OR-test and AND-test functionality on multiple test sources. In such an embodiment, the task of identifying a portion of instructions that could be fused into a single micro-operation may be simplified.
FIG. 15C illustrates a flow diagram for another alternative embodiment of a fused instruction structure 1503 to provide OR-test and AND-test functionality on multiple test sources and branching according to the resulting CC. A first instruction, TEST2, specifying a first source data operand, a second source data operand, a third source data operand, and an operation type (e.g. an OR-test or an AND-test instruction), and a second branch instruction (e.g. a jump-condition-code, JCC, instruction) specifying a branch condition, are stored in IQ 1511 (e.g. in instruction queue stage 1403 by fetch stage 1402) wherein when the decode stage (e.g. decode stage 1406) decodes the first instruction it fuses the first instruction with the branch instruction for execution as a single fused micro-operation 1526 to provide OR-test or AND-test functionality on multiple test sources and branching according to the resulting CC, the single fused micro-operation 1526 to be stored in micro-op storage 1520 (e.g. in micro-op storage stage 1407 for execution in processor pipeline 1400).
Thus, embodiments of fusible instructions and logic may provide OR-test and AND-test functionality on multiple test sources. In some embodiments processor decode stage 1406 may decode a novel test instruction (e.g. such as an OR-test or AND-test) for execution, the instruction specifying first, second and third source data operands, and an operation type (e.g. OR-test or AND-test). Execution units (e.g. an execution unit 462 and/or an execution unit 464) responsive to the decoded test instruction, may perform one logical operation (e.g. OR) according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation (e.g. AND) between the data from the third source data operand and the result of the first logical operation to set a condition flag. In some alternative embodiments processing to provide OR-test and AND-test functionality on multiple test sources may be performed by dedicated hardware. In some other alternative embodiments such processing may be performed by software or firmware operation codes executable by general purpose machines or by special purpose machines or by some combination.
FIG. 16A illustrates a flow diagram for one embodiment of a process 1601 to fuse instructions to provide OR-test and AND-test functionality on multiple test sources. As stated, process 1601 and other processes herein disclosed are performed by processing blocks that may comprise dedicated hardware or software or firmware operation codes executable by general purpose machines or by special purpose machines or by a combination of both.
In processing block 1610 of process 1601 a first instruction specifying a first operand destination is fetched. In processing block 1620 a second instruction specifying a second operand source is fetched. In processing block 1630 it is determined whether or not the first and the second operands are the same. If not, processing proceeds in processing block 1610. Otherwise processing proceeds in processing block 1640 where the first and second instructions are fused into a single micro-op or micro-operation. In processing block 1650 a third instruction specifying a branch condition dependent upon the second instruction is fetched. Then in processing block 1660 the third instruction is also fused into the single micro-op or micro-operation.
FIG. 16B illustrates a flow diagram for an alternative embodiment of a process 1602 to fuse instructions to provide OR-test and AND-test functionality on multiple test sources. In processing block 1610 of process 1602 a first instruction specifying a first operand destination is fetched. In processing block 1620 a second instruction specifying a second operand source is fetched. In processing block 1650 a third instruction specifying a branch condition dependent upon the second instruction is fetched. Then in processing block 1670 a portion of the fetched instructions are fused, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and the branch condition is dependent upon the second instruction.
FIG. 16C illustrates a flow diagram for another alternative embodiment of a process 1603 to fuse instructions to provide OR-test and AND-test functionality on multiple test sources. In processing block 1645 of process 1603 a first instruction for testing two operands, the first instruction specifying a first operand source, a second operand source, a third operand source, and an operation type is fetched. In processing block 1655 a second instruction specifying a branch condition flag is fetched, the branch condition flag being dependent upon the first instruction. Then in processing block 1665 a portion of the fetched instructions are fused, the portion including both the first and second instructions if for example, the branch condition flag is dependent upon the first instruction.
FIG. 16D illustrates a flow diagram for another alternative embodiment of a process 1604 to fuse instructions to provide OR-test and AND-test functionality on multiple test sources. In processing block 1647 of process 1604 a first instruction is decoded for execution, the first instruction specifying a first operand source data, a second operand source data, a third operand source data, and an operation type. In processing block 1649 a first micro-op or micro-operation is stored for the first instruction. In processing block 1657 a second instruction is decoded for execution, the second instruction specifying a branch condition. In processing block 1659 a second micro-op or micro-operation is stored for the second instruction. In processing block 1667 the first and second micro-ops are fused into a single micro-op if the branch condition depends on the first instruction.
Some embodiments may generate a novel test instruction (e.g. an OR-test or an AND-test instruction) dynamically, but through a JIT compiler. These embodiments may also fuse the test instruction with a subsequent conditional branch instruction (e.g. JZ), and perform a branch according to how the condition flag is set. Thus, a frequently executed instruction sequence idiom may be fusible into a single instruction which results in a single micro-operation within the processor pipeline at runtime.
FIG. 17 illustrates a flow diagram for an embodiment of a process 1701 to execute instructions to provide OR-test and AND-test functionality on multiple test sources. In processing block 1710 of process 1701 a first instruction is decoded for execution, the first instruction specifying a first operand source data, a second operand source data, a third operand source data, and an operation type. In processing block 1720 one or more execution units, responsive to the decoded first instruction, perform a first logical operation, according to the specified operation type, between data from the first and second operand sources. In processing block 1730 a second operation is performed between the data from the third operand source and the result of the first logical operation to conditionally set a condition flag. In processing block 1740 program flow conditionally branches if the condition flag gets set. In some embodiments processing blocks 1720-1740 may be performed responsive to a single fused micro-op or micro-operation to provide OR-test and AND-test functionality on multiple test sources and branching according to the resulting CC.
Frequently executed instruction sequence idioms may often include a logical operation to combine two source data operands (e.g. OR when testing if bits in either source are one, AND when testing if bits in either source are zero); a compare or test instruction (e.g. to TEST the result of the logical operation against a mask); and a conditional branch (e.g. JZ/JNZ to jump to a slower generic code sequence if the zero flag was set/not-set by TEST). Processor decode logic may make use of macro-fusion in the combining of a compare instruction or test instruction (e.g. TEST) with a conditional branch instruction (e.g. JZ).
1. A method for fusing instructions in a processor comprising:
fetching a plurality of instructions, said plurality of instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition, wherein the first instruction is a logical instruction; and
fusing a portion of the plurality of instructions into a single micro-operation, said portion including both the first and second instructions when said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction.
2. The method according to claim 1, said portion including the first, second and third instructions when: said first operand destination and said second operand source are the same, the second and third instructions are sequential, and the second instruction is a test instruction.
3. The method of claim 2 wherein the first instruction is a logical OR instruction.
4. The method of claim 2 wherein the first instruction is a logical AND instruction.
5. The method according to claim 1, said portion including the first, second and third instructions when: said first operand destination and said second operand source are the same, the second and third instructions are sequential, and the first instruction is a logical OR instruction.
6. The method according to claim 1, said portion including the first, second and third instructions when: said first operand destination and said second operand source are the same, the second and third instructions are sequential, and the first instruction is a logical AND instruction.
a first pipeline stage to fetch a plurality of instructions, said plurality of instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition, wherein the first instruction is a logical instruction; and
a second pipeline stage to decode a portion of the plurality of instructions into a single first micro-operation, said portion including both the first and second instructions when said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction.
8. The processor of claim 7, said portion including the first, second and third instructions when: said first operand destination and said second operand source are the same, the second and third instructions are sequential, and the second instruction is a test instruction.
9. The processor of claim 8 wherein the first instruction is a logical OR instruction.
10. The processor of claim 8 wherein the first instruction is a logical AND instruction.
11. The processor of claim 7, said portion including both the first and second instructions when: said first operand destination and said second operand source are the same, the second instruction is a test instruction, and the first instruction is a logical OR instruction.
12. The processor of claim 11 comprising:
a third pipeline stage including micro-fusion logic to fuse a second micro-operation for said third instruction with said single first micro-operation when: said branch condition is dependent upon the second instruction.
13. The processor of claim 7, said portion including the first, second and third instructions when: said first operand destination and said second operand source are the same, the second and third instructions are sequential, and the first instruction is a logical OR instruction.
14. The processor of claim 7, said portion including the first, second and third instructions when: said first operand destination and said second operand source are the same, the second and third instructions are sequential, and the first instruction is a logical AND instruction.
15. A system for fusing instructions in a processor comprising:
a first pipeline stage to fetch the plurality of instructions, said plurality of instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition, wherein the first instruction is a logical instruction; and
a second pipeline stage to decode a portion of the plurality of instructions into a single micro-operation, said portion including both the first and second instructions when said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction.
16. The system of claim 15, said portion including the first, second and third instructions when: said first operand destination and said second operand source are the same, the second and third instructions are sequential, and the second instruction is a test instruction.
17. The system of claim 16 wherein the first instruction is a logical OR instruction.
18. The system of claim 16 wherein the first instruction is a logical AND instruction.
19. The system of claim 15 said processor comprising:
a third pipeline stage including micro-fusion logic to fuse a second micro-operation for said third instruction with said single first micro-operation when said branch condition is dependent upon the second instruction.
a decode stage to decode:
a first instruction specifying a first source/destination data operand, and a second source data operand, wherein the first instruction is a logical instruction,
a second instruction specifying the first source data operand, and a third source data operand, and
a third instruction specifying a branch target;
said decode stage to fuse the first instruction and the second instruction with the third instruction for execution as a single fused micro-operation; and
one or more execution units, responsive to the single fused micro-operation, to:
perform a first logical operation between data from the first source/destination data operand and the second source data operand,
perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag, and
perform a conditional branch to the branch target when the condition flag gets set.
21. The processor of claim 20, wherein performing the second logical operation comprises a logical TEST operation and conditionally sets a zero flag.
22. The processor of claim 21, wherein according to the first instruction, a logical AND is performed between data from the first source/destination data operand and the second source data operand.
23. The processor of claim 22, wherein according to the first instruction, a logical OR is performed between data from the first source/destination data operand and the second source data operand.
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