Source: http://www.google.com/patents/US6518594?dq=6948823
Timestamp: 2013-12-12 08:28:03
Document Index: 463569986

Matched Legal Cases: ['application No. 10', 'application No. 10', 'application No. 7', 'application No. 8', 'application No. 10', 'application No. 10', 'application No. 09', 'application No. 09']

Patent US6518594 - Semiconductor devices - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Advanced Patent Search | Sign inAdvanced Patent SearchPatentsSubjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film....http://www.google.com/patents/US6518594?utm_source=gb-gplus-sharePatent US6518594 - Semiconductor devicesPublication numberUS6518594 B1Publication typeGrantApplication numberUS 09/441,025Publication dateFeb 11, 2003Filing dateNov 16, 1999Priority dateNov 16, 1998Fee statusPaidAlso published asUS6815273, US7244962, US7485898, US20030096460, US20050067618, US20070210312Publication number09441025, 441025, US 6518594 B1, US 6518594B1, US-B1-6518594, US6518594 B1, US6518594B1InventorsSetsuo Nakajima, Hisashi Ohtani, Shunpei YamazakiOriginal AssigneeSemiconductor Energy Laboratory Co., Ltd.Export CitationBiBTeX, EndNote, RefManPatent Citations (25), Non-Patent Citations (16), Referenced by (52), Classifications (28), Legal Events (4) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor devicesUS 6518594 B1Abstract Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film. LDD region is formed by using the first gate electrode as a mask, and a source region and a drain region are formed by using the second gate electrode as a mask. By removing a portion of the second gate electrode, a structure in which a region where LDD region and the second gate electrode overlap with a gate insulating film interposed therebetween, and a region where LDD region and the second gate electrode do not overlap, is obtained.
FIG. 8(A) shows a top view of the pixel area 701 for almost one pixel. The pixel area is provided with an n-channel TFT. A gate electrode 820 formed contiguous to a gate line 802 crosses an underlying semiconductor layer 801 with a gate insulating film not shown interposed therebetween. Though not shown, the semiconductor layer is formed with a first impurity region and source and drain regions formed as a second impurity region. On the drain side of the pixel TFT is formed a storage capacitance 807 which comprises the semiconductor layer, the gate insulating film, and an electrode made of the same material as the first and second conductive layers. A capacitive line 821 connected to the storage capacitance 807 is laid parallel to the gate line 802. The cross-sectional constitution along the line A�A′ of FIG. 8(A) corresponds to the cross sections of the pixel area shown in FIGS. 3(C) and 4(C).
In the CMOS circuit shown in FIG. 8(B), gate electrodes 813 and 814 extending from a gate line 819 cross underlying semiconductor layers 810 and 812, respectively, with a gate insulating film not shown interposed therebetween. Though not shown, the semiconductor layer on the n-channel TFT is similarly formed with a first impurity region and source and drain regions formed as a second impurity region. The semiconductor layer of the p-channel TFT is formed with source and drain regions formed as a third impurity region. As to the positional relationship, the cross-sectional constitution along the line B�B′ corresponds to the cross sections of the pixel area shown in FIG. 3(C) or FIG. 4(C).
FIG. 22 is a cross section taken along the line B-B′ of FIG. 21(B), showing the cross section of the switching TFT 30, storage capacitance 32, current control TFT 31 and organic EL element portion. Over a substrate 40, base films 41, 42, gate insulating film 45, first interlayer insulating film 46, gate electrodes 47, 48, capacitance line 49, source and drain lines 18 a, 19 a, 51, 52, and second interlayer insulating film 50 are formed in the same way as in the example 1. Then, over these layers is formed a third interlayer insulating film 53 in a way similar to the second interlayer insulating film 50. A contact hole reaching the drain line 52 is formed, after which a pixel electrode 54 made of a transport conductive film is formed. The organic EL element portion comprises the pixel electrode 54; an organic EL layer 55 overlaying the pixel electrode and the third interlayer insulating film 53; and a first electrode 56 made of Mg�Ag compound and a second electrode 57 made of Al, formed over the organic EL layer 55. If a color filter, though not shown, is used, a color display is possible. By applying the active matrix substrate manufacturing method shown in the examples 1 to 10, the active matrix type organic EL display can be fabricated easily.
EXAMPLE 13 In this embodiment, another EL display device having a different structure from the embodiment 12 is explained, as shown in FIGS. 24A and 24B. The same reference numerals in FIG. 24A and 24B as in FIGS. 23A and 23B indicate same constitutive elements, so an explanation is omitted.
EXAMPLE 14 In this example, the structure of the pixel region in the panel is illustrated in more detail. FIG. 25 shows the cross section of the pixel region; FIG. 26A shows the top view thereof; and FIG. 26B shows the circuit pattern for the pixel region. In FIG. 25, FIG. 26A and FIG. 26B, the same reference numerals are referred to for the same ports, as being common thereto.
Various types of PVV-type organic EL materials are known, such as those disclosed in �H. Shenk, H. Becker, O. Gelsen, E. Klunge, W. Kreuder, and H. Spreitzer; Polymers for Light Emitting Diodes, Euro Display Proceedings, 1999, pp. 33-37� and in Japanese Patent Laid-Open No. 92576/1988. Any of such known materials are usable herein.
EXAMPLE 18 The liquid crystal display of this invention can use a variety of liquid crystals other than a nematic liquid crystal. Examples of such liquid crystals include those disclosed in papers entitled �Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability� by H. Furue, et al. 1998, SID, �A Full-Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time� by T. Yoshida, et al. 1997, SID DIGEST, 841, and �Thresholdless antiferroelectricity in liquid crystals and its application to displays� by S. Inui, et al. 1996, J. Mater. Chem. 6(4), 671-673, and those described in U.S. Pat. No. 5,594,569.
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Co., Ltd.EL display device and manufacturing method thereofUS8373171Jun 6, 2011Feb 12, 2013Semiconductor Energy Laboratory Co., Ltd.Light-emitting device having a triple-layer wiring structureUS8426876Nov 18, 2010Apr 23, 2013Semiconductor Energy Laboratory Co., Ltd.Organic electroluminescent display deviceUS8440484Jun 22, 2012May 14, 2013Semiconductor Energy Laboratory Co., Ltd.Semiconductor device and fabrication method thereofUS20110309510 *Aug 31, 2011Dec 22, 2011Samsung Electronics Co., Ltd.Array substrate, display device having the same and method of manufacturing the same* Cited by examinerClassifications U.S. Classification257/59, 257/412, 257/E21.413, 257/E29.278, 257/347International ClassificationG02B27/00, H01L29/423, G02B27/01, G02F1/1362, H01L21/336, H01L29/786, H01L21/84, H01L21/77Cooperative ClassificationH01L29/78621, H01L29/42384, G02B27/017, H01L29/78627, H01L27/1214, H01L29/78624, H01L29/66757, G02B2027/0138, G02F1/13454European ClassificationH01L29/66M6T6F15A2, H01L29/786B4B4, H01L27/12T, H01L29/423D2B8, G02B27/01C, H01L29/786B4BLegal EventsDateCodeEventDescriptionJul 14, 2010FPAYFee paymentYear of fee payment: 8Jul 14, 2006FPAYFee paymentYear of fee payment: 4Aug 12, 2003CCCertificate of correctionFeb 7, 2000ASAssignmentOwner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD., JAPANFree format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAKAJIMA, SETSUO;OHTANI, HISASHI;YAMAZAKI, SHUNPEI;REEL/FRAME:010537/0640;SIGNING DATES FROM 20000105 TO 20000120Owner name: SEMICONDUCTOR ENERGY LABORATORY CO., LTD. 398, HASRotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google