Source: https://patents.google.com/patent/US8883562B2/en
Timestamp: 2019-03-20 17:57:30
Document Index: 278062355

Matched Legal Cases: ['§371', 'Application No. 60', 'Application No. 200880110215', 'Application No. 201110370722', 'Application No. 2010', 'Application No. 2011', 'Application No. 2011', 'Application No. 10']

US8883562B2 - Reconstituted wafer stack packaging with after-applied pad extensions - Google Patents
Reconstituted wafer stack packaging with after-applied pad extensions Download PDF
US8883562B2
US8883562B2 US13/911,555 US201313911555A US8883562B2 US 8883562 B2 US8883562 B2 US 8883562B2 US 201313911555 A US201313911555 A US 201313911555A US 8883562 B2 US8883562 B2 US 8883562B2
US13/911,555
US20130344652A1 (en
2007-07-27 Priority to US96220007P priority Critical
2008-07-25 Priority to PCT/US2008/009207 priority patent/WO2009017758A2/en
2010-05-14 Priority to US67095210A priority
2013-06-06 Application filed by Tessera Inc filed Critical Tessera Inc
2013-06-06 Priority to US13/911,555 priority patent/US8883562B2/en
2013-09-05 Assigned to TESSERA, INC. reassignment TESSERA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OVRUTSKY, DAVID, HUMPSTON, GILES, HABA, BELGACEM, MIRKARIMI, LAURA WILLS
2013-12-26 Publication of US20130344652A1 publication Critical patent/US20130344652A1/en
2014-11-11 Publication of US8883562B2 publication Critical patent/US8883562B2/en
A stacked microelectronic unit is provided which can include a plurality of vertically stacked microelectronic elements each having a front surface, contacts exposed at the front surface, a rear surface and edges extending between the front and rear surfaces. Traces connected with the contacts may extend along the front surfaces towards edges of the microelectronic elements with the rear surface of at least one of the stacked microelectronic elements being adjacent to a top face of the microelectronic unit. A plurality of conductors may extend along edges of the microelectronic elements from the traces to the top face. The conductors may be conductively connected with unit contacts such that the unit contacts overlie the rear surface of the at least one microelectronic element adjacent to the top face.
The present application is a continuation of U.S. patent application Ser. No. 12/670,952 filed May 14, 2010, which application is a national phase entry under 35 U.S.C. §371 of International Application No. PCT/US2008/009207 filed Jul. 25, 2008, which claims priority from U.S. Provisional Application No. 60/962,200 filed Jul. 27, 2007, the disclosures of all of which are incorporated herein by reference.
Microelectronic packages or assemblies also include wafer level packages, which provide a package for a microelectronic component that is fabricated while the die is still in a wafer form. The wafer is subject to a number of additional process steps to form the package structure and the wafer is then diced to free the individual die. Wafer level processing may provide a cost savings advantage. Furthermore, the package footprint can be identical to the die size, resulting in very efficient utilization of area on a printed circuit board (PCB) to which the die will eventually be attached. As a result of these features, die packaged in this manner are commonly referred to as wafer-level chip scale packages (WLCSP).
In accordance with an aspect of the invention, a method is provided for fabricating a stacked microelectronic assembly. The method can include providing a plurality of subassemblies, each being a reconstituted wafer or portion of a reconstituted wafer. Each reconstituted wafer or wafer portion has a front side and a rear side remote from the front side and may include a plurality of spaced apart microelectronic elements each having a front face exposed at the front side, contacts exposed at the front side, a rear face adjacent to the rear side, and edges extending between the front and rear faces. Each reconstituted wafer may further include a fill layer overlying the rear faces of the microelectronic elements and extending between the edges of adjacent microelectronic elements.
A plurality of traces may then be formed at the front side of each subassembly. The traces may extend from the contacts to beyond the edges of the microelectronic elements. A thickness of a first one of the microelectronic elements may then be reduced, e.g., by processing applied from the rear side, to reduce a thickness of the microelectronic elements therein. Thereafter, a second one of the subassemblies can be joined with the first subassembly such that the front side of the second subassembly confronts the rear side of the first subassembly and such that the front faces of microelectronic elements of the second subassembly may face toward the rear faces of the microelectronic elements of the first subassembly. Leads may be formed in at least one opening extending downwardly from the rear side of the second subassembly, the leads connected to the traces of the microelectronic elements of the first and second subassemblies.
In accordance with such aspect of the invention, prior to forming the leads, one or more additional subassemblies can be joined with the first and second subassemblies, such that the front faces of microelectronic elements in each such additional subassembly face toward the rear faces of microelectronic elements in each subassembly underlying the additional subassembly.
In accordance with another aspect of the invention, a method is provided for fabricating a stacked microelectronic assembly. In accordance with such aspect, a plurality of subassemblies can be provided, each being a reconstituted wafer or portion of a reconstituted wafer. Each such reconstituted wafer or wafer portion may have a front side and a rear side remote from the front side, and a plurality of spaced apart microelectronic elements having front faces exposed at the front side, contacts exposed at the front side, rear faces adjacent to the rear side, and edges extending between the front and rear faces. Each such reconstituted wafer may further include a plurality of traces extending from the contacts to beyond the edges of the microelectronic elements and a fill layer overlying the rear faces of the microelectronic elements and extending between the edges of adjacent microelectronic elements.
A first one of the subassemblies may then be reduced in thickness by processing applied to the rear side so as to reduce a thickness of the microelectronic elements therein. A second one of the subassemblies may then be joined with the first subassembly such that the front side of the second subassembly confronts the rear side of the first subassembly and the front faces of the microelectronic elements of the second subassembly overlie and face toward the rear faces of the microelectronic elements of the first subassembly.
Leads may then be formed in at least one opening extending downwardly from the rear side of the second subassembly which conductively connect to the traces of the microelectronic elements of the first and second subassemblies.
In accordance with another aspect of the invention, a method is provided for fabricating a stacked microelectronic unit. In accordance with such method, a plurality of microelectronic elements may be stacked and joined together, each of the microelectronic elements having a front face, a rear face remote from the front face, contacts exposed at the front face, edges extending between the front and rear faces and traces connected to the contacts, the traces extending along the front faces towards the edges. The microelectronic elements can be stacked such that front faces of at least some of the microelectronic elements overlie and confront the rear faces of other microelectronic elements. A plurality of conductors may then be formed which extend along the edges of the microelectronic elements from the traces to unit contacts overlying and adjacent to rear faces of microelectronic elements of the at least some of the microelectronic elements in the stacked microelectronic unit.
In accordance with one aspect of the invention, the unit contacts may overlie the rear faces of the microelectronic elements of uppermost microelectronic elements in the stacked microelectronic unit.
A stacked microelectronic unit may be provided in accordance with one aspect of the invention, the stacked unit having a top face, unit contacts exposed at the top face and a bottom face remote from the top face. In accordance with such aspect of the invention, the stacked unit may include a plurality of vertically stacked microelectronic elements each having a front surface, contacts exposed at the front surface, a rear surface and edges extending between the front and rear surfaces. Traces connected with the contacts may extend along the front surfaces towards the edges of the microelectronic elements, with the rear surface of at least one of the stacked microelectronic elements being adjacent to the top face of the microelectronic unit. A plurality of conductors may extend along the edges of the microelectronic elements from the traces to the top face. The conductors may be conductively connected with the unit contacts such that the unit contacts overlie the rear surface of the at least one microelectronic element adjacent to the top face of the stacked microelectronic unit.
In accordance with one of more aspects of the invention, some of the unit contacts may be exposed at the bottom face of the stacked microelectronic unit. One or more of the unit contacts may be connected to contacts on a front surface of at least one microelectronic element, such front surface being adjacent to the bottom face.
In accordance with an aspect of the invention, a stacked microelectronic unit is provided which can include first and second vertically stacked microelectronic elements. Each of the stacked microelectronic elements can have a front surface defining a lateral direction, at least one edge extending away from the front surface, contacts exposed at the front surface, and traces extending in the lateral direction from the contacts toward the edges, wherein the front surface of the second microelectronic element at least partially overlies the front surface of the first microelectronic element and the second microelectronic element has at least one edge displaced in the lateral direction from an adjacent edge of the first microelectronic element. A dielectric layer may overlie the laterally displaced edges of the microelectronic elements, the dielectric layer defining an edge of the stacked unit. Leads may be connected to traces at front faces of the microelectronic elements, the leads extending along the edges of the microelectronic elements to unit contacts.
In accordance with a more particular aspect of the invention, a stacked microelectronic unit may be provided in which the laterally displaced edges are first edges, and the edges of the microelectronic elements include second edges which extend in a second direction transverse to a first direction in which the first edges extend. Each of the first and second microelectronic elements may have at least one second edge which is displaced from an adjacent second edge of the other of the first and second microelectronic elements. The dielectric layer may overlie the second edges of the microelectronic elements, and second leads may overlie the dielectric layer and extend along the second edges of the microelectronic elements to unit contacts.
In accordance with one aspect of the invention, a stacked microelectronic unit is provided. In such microelectronic unit, first and second vertically stacked microelectronic elements can be provided wherein at least one first edge of the first microelectronic element at a first level extends beyond a corresponding first edge of a second microelectronic element at a second level overlying the first level. A dielectric layer may overlie the first edges of the first and second microelectronic elements, the dielectric layer defining a first edge of the stacked unit.
In accordance with a particular aspect of the invention conductive vias can extend through the dielectric layer, the vias being connected to traces at front faces of the microelectronic elements.
In accordance with another aspect of the invention, a stacked microelectronic unit is provided in which first and second microelectronic elements are vertically stacked such that the front face of the first microelectronic element overlies at least one of a front face or a rear face of the second microelectronic element. At least one of a width or a length of the front faces of the first and second microelectronic elements may differ. A dielectric layer may overlie the first edges of the first and second microelectronic elements. Leads may be connected to traces at front faces of the microelectronic elements. The leads may overlie the dielectric layer and the leads may extend along a first edge of the stacked unit.
FIG. 1A is a plan view illustrating a wafer or portion of a wafer including a plurality of microelectronic elements attached at peripheral edges, in accordance with a stage in a method of fabricating a stacked microelectronic unit according to an embodiment of the invention.
FIG. 1B is a sectional view of the wafer or portion of wafer through line 1B-1B of FIG. 1A.
FIGS. 2A, 2B, 3, 4, 5, 6, 7 and 8A are sectional views illustrating stages in a method of fabricating a stacked microelectronic unit according to an embodiment of the invention.
FIG. 8B is a fragmentary partial plan view of a stacked assembly in accordance with the stage of fabrication corresponding to the sectional view of FIG. 8A.
FIGS. 9 and 10A are sectional views illustrating stages subsequent to the stage illustrated in FIGS. 8A-B, in a method of fabricating a stacked microelectronic unit according to an embodiment of the invention.
FIG. 10B is a sectional view illustrating a stacked microelectronic unit in accordance with a variation of the embodiment illustrated in FIG. 10A.
FIG. 10C is a sectional view of a stacked assembly in a stage of a method in accordance with an embodiment of the invention.
FIG. 10D is a fragmentary partial plan view corresponding to the sectional view of FIG. 10C, the sectional view in FIG. 10C being taken through line 10C-10C of FIG. 10D.
FIG. 11 is a sectional view of a stacked microelectronic unit and its external interconnection to other elements in accordance with an embodiment of the invention.
FIG. 12 is a fragmentary partial plan view of a stacked assembly in a stage of a method in accordance with a variation of the embodiment of invention shown in FIGS. 2A through 10A.
FIGS. 13A, 13B, 13C, and 13D are sectional views illustrating successive stages (A) through (D) in a method of fabricating a stacked microelectronic unit in accordance with an embodiment of the invention.
FIG. 14 is a sectional view illustrating a stacked assembly in a stage subsequent to stage (D) of FIG. 13 in a method of fabricating a stacked microelectronic unit in accordance with an embodiment of the invention.
FIG. 15 is a sectional view illustrating a stacked assembly in a stage subsequent to the stage shown in FIG. 14 in a method of fabricating a stacked microelectronic unit in accordance with an embodiment of the invention.
FIG. 16 is a sectional view illustrating a microelectronic element contained within a stacked assembly in accordance with a variation of the embodiment of the invention illustrated in FIGS. 13 through 15.
FIG. 17 is a fragmentary partial plan view illustrating a reconstituted wafer for fabrication into stacked microelectronic units in accordance with one or more of the embodiments of the invention.
FIGS. 1A-C illustrate an array, or a portion of an array of microelectronic elements, such as may be provided on a semiconductor wafer. FIG. 1A is a top plan view of a wafer 10 or portion of a wafer and includes a plurality of microelectronic elements 12, 12′ (twelve prime), 12″ (twelve double prime), each microelectronic element being shown as a rectangle. As seen in FIG. 1A, each microelectronic element is positioned side by side and adjacent to one another. The wafer can be in the shape of a circular wafer. Hereinafter, for ease of reference, the wafer 10 or wafer portion is referred to as “wafer”. The wafer 10 may include numerous rows of microelectronic elements 12 aligned along an X-axis and a Y-axis. The wafer may include any number of microelectronic elements, including as little as tow or as many as is desirable. The microelectronic elements are formed integral with one another using semiconductor fabrication techniques. Each of the microelectronic elements of the wafer is typically of the same type. The microelectronic elements can have memory function, logic or processor function or a combination of logic and processor functions, among other possible types. In a particular example, each of the microelectronic elements includes a flash memory. For example, each microelectronic element can be a dedicated flash memory chip.
Wafer 10 in FIG. 1A has a top edge 15, a right edge 13, a left edge 11 and a bottom edge 17. FIG. 1C is an elevated side view of wafer 10 taken along line 1B (FIG. 1A), showing left edge 11 and right edge 13 of wafer 10. FIG. 1C also shows that each microelectronic element of wafer 10 also has a front face 14 and an oppositely-facing rear face 16. Note that in FIG. 1C, the front face 14 of wafer 10 has been turned over such that it faces downward in the figure.
In FIG. 1A, three microelectronic elements 12, 12″, and 12′ are individually called out in the middle row of the wafer 10. With reference to microelectronic element 12 of FIG. 1A, each microelectronic element has a first edge 18, a second edge 20, a third edge 19 and a fourth edge 21. When microelectronic element 12 is still part of the array of wafer 10, a first edge 18 of one microelectronic element 12 abuts (or is attached to) second edge 20 of a second and adjacent microelectronic element 12. Similarly, a third edge 19 (FIG. 1A) of one microelectronic element 12 is attached to a fourth edge 21 of an adjacent microelectronic element. Thus, a microelectronic element 12″ positioned in a middle row of the wafer portion 10 is bordered by an adjacent microelectronic element at all four edges, as shown in FIG. 1A. When microelectronic element 12 is entirely separated from wafer 10 (e.g., singulated thereform), it can be seen that each of first edge 18, second edge 20, third edge 19 and fourth edge 21 extends from the front face 14 (FIG. 1C) to the rear face 16 (FIG. 1C) of the microelectronic element 12.
Portions of wafer 10 where adjacent microelectronic elements contact one another form saw lanes or strips 23 and 25 where the wafer can be cut without damaging the individual microelectronic elements. For instance, as shown in FIG. 1B, second edge 20′ of microelectronic element 12′ abuts first edge 18′ of microelectronic element 12″ and forms a saw lane 23. Similarly, throughout the wafer 10, saw lanes 23 (shown in FIGS. 1A and 1C) are located at positions where microelectronic elements 12 abut one another.
With reference to microelectronic element 12″ of FIG. 1B, each microelectronic element includes a plurality of contacts 22″ exposed at the respective front face 14 of the microelectronic element 12. The contacts 22 can be, for example, bond pads or lands of the microelectronic elements as originally formed in a wafer fabrication facility. Each microelectronic element of the uncut wafer 10 has a device region 26 (area within dashed lines 27) in which active semiconductor devices and typically also passive devices are disposed. Each microelectronic element also includes a non-device region disposed beyond edges of the device region 26 where no active semiconductor devices or passive devices are disposed. Note that the bounded area of device region 26 is shown by solid lines in FIG. 1C.
In one stacked assembly fabrication embodiment, an assembly including a plurality of stacked microelectronic elements is fabricated by simultaneously processing a plurality of microelectronic elements en masse. Moreover, processing can be carried out simultaneously as to microelectronic elements which are arranged in form of an array, similar to the processing of an original wafer containing such microelectronic elements. FIGS. 2A-10A illustrate stages in a method of forming a package or assembly of stacked microelectronic elements in accordance with a first fabrication embodiment. In this embodiment, original, wafer 10 is first separated into individual microelectronic elements and then selected ones of the individual microelectronic elements are attached in form of an array to a carrier layer for further processing. In this embodiment, the array of selected microelectronic elements can be considered a “reconstituted wafer” which is then available for processing according to wafer-level processing techniques.
FIG. 2 illustrates a stage of fabrication in which an original wafer 10 is separated into individual microelectronic elements 12 by severing, e.g., sawing or scribing wafer 10 along the dicing lanes 23 and 25 (FIG. 1A).
FIG. 2A illustrates a stage of fabrication in which the wafer 10 is separated into individual microelectronic elements 12 by severing, e.g., sawing or scribing the wafer 10 along the dicing lanes 23 and along dicing lanes 25 (FIG. 1A). From the individual microelectronic elements obtained during this stage (FIG. 2B), selected ones 12 of the microelectronic elements, i.e., known good die, are attached at their front faces to an adhesive carrier 160 (FIG. 3) or other carrier having an adhesive interface (not shown). FIG. 2B represents determination of a known good die 12 a and a rejected die 12 b, the rejected die being removed from further processing.
A pick-and-place tool can be used, for example, to place each microelectronic element 12 at the proper position on the carrier 160 to form a layer of microelectronic elements which make up a first reconstituted wafer 110 as shown in sectional view in FIG. 3. As seen therein, the reconstituted wafer 110 includes individual microelectronic elements 12 that were selected from the microelectronic elements 12 obtained during the dicing (sawing) stage of FIG. 2. Individual microelectronic elements 12 are referred to as the known good die, and are attached to a carrier 160 using an adhesive 162, with the front face of each die and contacts 22 thereon facing the carrier 160. A pick-and-place tool can be used to place each microelectronic element at the proper position on the carrier 160 to form reconstituted wafer structure 90.
An advantage of processing a reconstituted wafer rather than the original wafer 10 is that the microelectronic elements that make up each reconstituted wafer can be individually selected. When some of the microelectronic elements of the original wafer are of known or suspected marginal or failing quality, they need not be processed into reconstituted wafers. Rather, those microelectronic elements can be left out of the reconstituted wafer such that the reconstituted wafer contains better quality microelectronic elements. Selection of the microelectronic elements to go into the reconstituted wafer can be based on various criteria of quality or expected quality based on results of visual, mechanical or electrical inspection or location of the microelectronic element within the original wafer 10, for example. In a particular embodiment, microelectronic elements may in fact be tested electrically before placing each one into position on the reconstituted wafer. Whether the microelectronic elements are selected based on visual, mechanical or electrical criteria or other criteria, the microelectronic elements which are selected for inclusion in the reconstituted wafer can be referred to as “known good” microelectronic elements or “known good die”.
After attaching the microelectronic elements 12 to the carrier 160, a fill layer 116 (FIG. 4) is formed which fills spaces 114 of the reconstituted wafer 110 between adjacent microelectronic elements. The fill layer may also cover rear faces 118 of the microelectronic elements 112. The fill layer can include a variety of materials. The fill layer may include a dielectric material for providing isolation between the microelectronic elements and conductors which may be connected thereto, such as described in the following. For example, the fill layer may include one or more inorganic dielectric materials such as an oxide, nitride, which may include silicon dioxide, silicon nitride or other dielectric compound of silicon such as SiCOH, among others, or may include an organic dielectric, among which are various polymers such as epoxies, polyimide, thermoplastics, thermoset plastics, among others. The fill layer may be an encapsulant such as commonly used to form an overmold overlying the rear face and edges of an overmold packaged chip.
The carrier 160 then can be removed to expose front faces 117 of the microelectronic elements and the contacts 22 including contact 22′ and 22″ of microelectronic elements 12′ and 12″, respectively. Thereafter, traces 24 are formed which extend outwardly from each of the contacts 22 beyond at least some of the edges 18′, 20′, 18″ and 20″ (FIG. 5) of the microelectronic elements and optionally beyond edges 19 and 21 (FIG. 1A) of individual microelectronic elements 12. Traces 24′ and 24″ of adjacent microelectronic elements 12′ and 12″ may meet at a location between the edges 20′ and 18″ of the adjacent microelectronic elements. Traces 24′, 24″ (FIG. 5) may actually form a single trace extending between contact 22′ and contact 22″. However, it is not required that the traces actually contact one another.
The resulting reconstituted wafer 130 (FIG. 5) includes the reconstituted wafer 110 with the microelectronic elements 12′, 12″ having the overmold or other fill layer 116 covering the rear faces 118 and space 114. Traces 24, 24′, 24″ and 24′″ extend from the contacts 22 (including contacts 22′, 22″, etc.) along the front faces 117 of the microelectronic elements. Front faces 117 of the microelectronic elements 12 are adjacent to a front side 132 of the reconstituted wafer. The rear faces 118 of the microelectronic elements are disposed remote from the front side 312 and are adjacent to the rear side 134 of reconstituted wafer 130.
A plurality of reconstituted wafers 130 can be prepared according to the foregoing described processes, before conducting further processing as described below to form stacked microelectronic units. In such further processing, each reconstituted wafer 130 can be referred to as a “subassembly” because such subassemblies can be fabricated individually and then assembled and processed to form a stacked microelectronic unit, as will be described below. FIG. 6 illustrates a stage of fabrication in which the front side 132 of a first subassembly 130 is joined with a packaging layer 140, e.g., a bottom dielectric substrate which may include organic or inorganic materials or a combination thereof. An adhesive layer 162 can be used to join the subassembly 130 with the packaging layer 140.
Subsequently, the thickness of the first subassembly 130 (FIG. 7) and the microelectronic elements 12 therein can be reduced by grinding, lapping or polishing such subassembly from its rear side 134 so as to reduce the thickness of each microelectronic element 12 therein. A second subassembly 130A similar to the first subassembly can then be bonded to the first subassembly using an adhesive layer 162A, such that the front side 132 of the second subassembly confronts the rear side 134 of the first subassembly, as shown in FIG. 7. The microelectronic elements 12A of the second subassembly are stacked in registration with corresponding microelectronic elements 12 of the first subassembly, such that at least a portion of the microelectronic elements 12A of the second subassembly directly overlie the rear faces 118 of microelectronic elements 12 of the first subassembly. In one embodiment as illustrated in FIGS. 8A-B, edges 18 of the microelectronic elements 12A of the second subassembly 130A are aligned in a vertical direction 60 (a direction transverse to the front faces 117 of microelectronic elements 12) with corresponding edges 18 of the microelectronic elements 12 of the first subassembly 130. In addition, edges 20 of the microelectronic elements 12A of the second subassembly 130A can be aligned in the vertical direction 60 with corresponding edges 20 of the microelectronic elements 12 of the first subassembly. In like manner, the edges 19 and 21 (FIG. 1A) of microelectronic elements 12A of the second subassembly 130A can be aligned in the vertical direction with respective edges 19 and 21 of the corresponding microelectronic elements 12 of the first subassembly 130.
Thereafter, the thickness of the second subassembly is reduced, such as by grinding, lapping or polishing, that the microelectronic elements 12A thereof have reduced thickness, as illustrated in FIG. 8A. As a result, the dielectric material of the fill layer 116 which directly overlies each microelectronic element 12A can be removed such that the fill layer only remains between the confronting edges 18 and 20 and between confronting edges 19 and 21 of adjacent microelectronic elements 12A of the second subassembly, as best seen in the fragmentary partial plan view of FIG. 8B. As also depicted in FIG. 8B, the edges of the microelectronic elements 12A of the second subassembly and the edges of microelectronic elements 12 of the underlying first subassembly are aligned so as to define streets 123 and 125 of a stacked assembly 30 with the fill layer 116 disposed in the streets. As also seen in FIG. 8B, the traces 22 extend outward beyond the edges 18, 19, 20, 21 of each chip into the streets 123, 125 between the microelectronic elements.
Subsequently, a plurality of channels 46 are cut into the stacked assembly 30 in alignment with the streets, as illustrated in FIG. 9. The channels 46 can be formed using a mechanical cutting instrument not shown in the figures. Examples of such a mechanical cutting instrument can be found in U.S. Pat. Nos. 6,646,289 and 6,972,480, the disclosures of which are hereby incorporated by reference herein. Alternatively, a laser drilling technique can be used to form the channels. Channels 46 can be formed in the stacked assembly 30 at locations that are between first edges 18 of microelectronic elements 12, 12A in the stacked assembly 30 and adjacent second edges 20 of other microelectronic elements 12, 12A in the stacked assembly. Channels may also be formed at locations between third edges 19 (FIG. 8B) of microelectronic elements and fourth edges 21 (FIG. 8B) of microelectronic elements 12, 12A adjacent thereto. The channels 46 extend downwardly within the streets adjacent to edges of microelectronic elements 12, 12A of respective subassemblies 130, 130A.
As illustrated in FIG. 9, the channels 46 may be formed such that they do not extend entirely through the stacked assembly 30. For example, as shown in FIG. 9, the microelectronic elements 12 of the first subassembly 130 remain attached to each other because the channels 46 do not extend through the carrier layer 140 underlying the first subassembly 130. However, the channels 46 do extend far enough so as to contact the traces 24 of the first subassembly 130. Similarly, the channels 46 extend through adhesive layer 162A connecting the first and second subassemblies 130, 130A. Optionally, the channels may extend through the lower adhesive layer 162 which connects the first subassembly to the carrier layer 140. Although the channels 46 are illustrated having inclined walls 48, 50, optionally, the walls may be straight, that is, parallel to each other and oriented in a normal direction to the plane defined by the front faces 117 of the microelectronic elements 12.
Once the channels 46 have been created in the stacked assembly 30, leads 66 (FIG. 9) may be formed on the walls 48, 50 of channels 46. The leads 66 may be formed by any suitable metal deposition technique, for example, a process that includes sputtering or electroless plating, photolithography and electroplating or any combination thereof. A three-dimensional photolithography process may be employed to define locations of the leads, such as is disclosed in commonly owned U.S. Pat. No. 5,716,759, the disclosure of which is hereby incorporated by reference herein. The leads 66 extend along walls of the channels 46 and electrically contact the traces 24 of the microelectronic elements 12, 12A of each respective subassembly 130, 130A.
In the embodiment illustrated in FIG. 9, the leads 66 extend beyond the walls 48, 50 of channels 46 such that the leads overlie the rear surfaces 118 of microelectronic elements 12A. The leads 66 may include ends 75 or pads remote from channels 46 on which solder bumps 74 may be disposed. Each lead 66 can electrically connect with both a trace 24 of a microelectronic element 12 and a trace 24A of microelectronic element 12A, as a result of those traces 24, 24A being aligned and exposed at a given wall, e.g. wall 48 of the channel 46.
Alternatively, each lead 66 can electrically connect with only one of the traces 24, 24A exposed at a wall of the channel, e.g., wall 48. Such result may be obtained by positioning the traces 24, 24A in different planes which occur at different positions into and out of the sheet relative to the particular section which is illustrated in FIG. 9. For example, the plane in which trace 24 is found as illustrated in FIG. 9 may be offset from the plane in which trace 24A is found such that trace 24 is closer to the reader when viewed in three dimensions. Lead 66, which is aligned and connected with trace 24, would then also be offset from trace 24A and not in contact with trace 24A. In such embodiment, each of the traces 24, 24A then would be attached to different leads 66 which would extend along a wall 48 or 50 and to positions overlying the rear surface 118 of the microelectronic elements 12A.
As shown in FIG. 10A, after the channels 46 and various conductive elements including leads 66 are formed in the stacked assembly 30, individual packages 80 may be severed from the stacked assembly 30 by separating the carrier layer 140 from the stacked assembly and cutting or breaking any material remaining between adjacent microelectronic elements of the stacked assembly. In this way, a plurality of stacked individual microelectronic units 80 result, with each stacked individual unit 80 containing a plurality of microelectronic elements stacked one upon another. Alternatively, the carrier layer 140 may remain in place and the carrier layer then is severed in alignment with the channels 46. In such case, a portion of the carrier layer then will be included in each resulting individual stacked unit 80.
As further seen in FIG. 10A, the ends 75 of the leads, with bumps 74 optionally disposed thereon, function as unit contacts 76 at a top face 90 of each microelectronic unit 80. In each stacked microelectronic unit 80, at least one or more of the microelectronic elements 12, 12A has a front face 117 and contacts 22 which face away from the top face 90 of the stacked unit.
FIG. 10B is a fragmentary sectional view illustrating a portion of an individual stacked microelectronic unit 490 having four microelectronic elements 412, 412A, 412B and 412C stacked therein, the microelectronic elements being joined together through adhesive layers 162, 162A, and 162B. Greater or fewer numbers of vertically stacked microelectronic elements can be included in the package. The front face 417 of some of the microelectronic elements can face toward the rear faces of other microelectronic elements in the microelectronic unit 490. For example, in FIG. 10B, the front face 417 of microelectronic element 412A faces toward the rear face 418 of microelectronic element 412. The package is capable of being externally interconnected to other elements by ends 475 of leads functioning as top unit contacts overlying the top face 490 of the unit. The top unit contacts 475 are adjacent to the rear face 418 of microelectronic element 412C. Thus, the front faces of microelectronic elements 412, 412A, face away from the top face 490 of the stacked unit.
In addition, the package is capable of being externally interconnected by bottom unit contacts 476 exposed at a bottom face 492 of the microelectronic unit. Each bottom unit contact 476 may be conductively connected to only one trace 424 of one microelectronic element and have no connections to the traces on the other microelectronic elements in the microelectronic unit. Alternatively, each bottom unit contact 476 may be conductively connected to two, three or more of the traces 424, 424A, 424B, 424C which are aligned together within the plane in the section illustrated in FIG. 10B.
In a variation of the above-described process of forming stacked packages through the formation and joining of reconstituted wafers (FIG. 10C) microelectronic elements of differing sizes are joined together within a stacked assembly 830. FIG. 10C illustrates a stage of fabrication prior to that in which channels 46 (FIG. 9) are formed. FIG. 10D is a fragmentary partial plan view corresponding thereto, looking towards front faces of microelectronic elements 812A and microelectronic elements 812 which underlie and are aligned with the microelectronic elements 812A in a vertical direction 840 of the assembly. As illustrated in FIGS. 10C-10D, some of the microelectronic elements 812A which make up an upper subassembly 832A of the stacked assembly may have greater or smaller dimensions than microelectronic elements 812 of a lower subassembly 832 therein. Thus, in the example shown in FIG. 10D, both the length 834′ and width 836′ of the front face 817A of the upper microelectronic element 812A can be smaller than the length 834 and width 836 of the front face 817 of the lower microelectronic element 812 that it overlies. In another example, the length and width of front faces 817′, 817A′ of vertically aligned microelectronic elements 812′ and 812A′ of the stacked assembly are the same, but these dimensions are different from, i.e., smaller than the dimensions of other microelectronic elements in the stacked assembly 830.
The versatility of the techniques described herein is exemplified by the structure shown in FIGS. 10C-10D. Specifically, traces 824 extending outward from contacts 822 on microelectronic elements 812 can have different lengths from the traces 824 which extend outward from the contacts 822A on microelectronic elements 812A, since the process of forming an overmold layer 116 (FIG. 4) leaves a surface on which traces of different lengths can be formed by subsequent processing (FIG. 5). Many variations can be made whereby, for example, microelectronic elements of an upper layer have larger size than those of the lower layer. In yet another example, smaller dimensioned chips can be vertically sandwiched between larger dimensioned chips, or larger dimensioned chips can be vertically sandwiched between smaller dimensioned chips.
An individual stacked assembly 80, unit or package (FIG. 11) can be conductively connected using solder bumps at the front face 220 of the package 80 to an interconnection element 210, e.g., a dielectric element, substrate, circuit panel or other element having terminals 84, 86 and conductive wiring therein. One or more additional microelectronic elements 230 can be attached to a rear face 222 of the package 80 and electrically interconnected by bond wires 82 to the terminals 84 of the interconnection element. Such microelectronic element 230 can include one or more additional microelectronic elements which supplement the function of the stacked package 80, e.g., such as a microcontroller, or can include one or more redundancy elements for substitution with one or more microelectronic elements 112, 112A, 112B, or 112C, etc. of the assembly in case of a problem with such microelectronic element. In a particular embodiment, the individual stacked assembly or unit 80 may be incorporated into microprocessors, and RF units among other assemblies. One or more stacked units 80 may incorporate particular types of microelectronic elements such as flash memory or dynamic random access memory (DRAM) units and be incorporated in various units including memory modules, memory cards, and the like. Other exemplary arrangements for mounting and interconnecting the stacked unit 80 to an interconnection element are shown and described in commonly owned U.S. patent application Ser. No. 11/787,209 filed Apr. 13, 2007, the disclosure of which is hereby incorporated herein by reference. For example, the stacked unit 80 can be mounted with the front face facing either downwardly towards the interconnection element or upwardly away therefrom. In addition, the one or more additional microelectronic elements can be mounted either face-up as shown in FIG. 11 or face-down, such that the contact-bearing face is flip-chip mounted to the stacked unit 80. Various combinations and configurations and possible, such as illustrated in incorporated U.S. patent application Ser. No. 11/787,209.
FIG. 12 is a fragmentary partial plan view showing a variation of the above embodiment, wherein, after forming the stacked assembly 30 (FIG. 8), the step of forming channels which expose all of the traces 24, 24A of both the stacked microelectronic elements 12, 12A is omitted. Instead, a series of individual openings 228 are formed between the edges of respective microelectronic elements in alignment with the streets 218, 220. Unlike the channels 46 (FIG. 9) formed in the above-described embodiment, each of the openings 228 exposes no more than a single trace 224 of each respective microelectronic element. As shown in FIG. 12, traces 224 connected to contacts of two adjacent microelectronic elements 212 are exposed within one of the openings 228 between two adjacent microelectronic elements. In the stacked assembly 30 as shown in FIG. 12, a plurality of traces 224 connected to microelectronic elements of the same subassembly can be exposed within a single opening 228. Alternatively or in addition thereto, a plurality of traces 224 connected to respective subassemblies 130, 130A (FIG. 7) of the stacked assembly can be exposed within a single opening 228. However, openings 228 can be formed such that no more than one trace of each individual microelectronic element is exposed within each opening 228.
To form leads and external unit contacts connected to individual ones of the traces 224 all openings 228 in the stacked assembly can be simultaneously filled with a conductor to form conductive vias connected to single traces of each microelectronic element. For example, the openings can be filled with a metal to form conductive vias by depositing a primary metal, e.g., by sputtering or electroless deposition, and then electroplating the resulting structure. Some of the metal deposited by the electroplating step may form a layer overlying the rear faces of the microelectronic elements. Such metal layer can be removed from the rear faces of the microelectronic elements, leaving surfaces of individual conductive vias exposed within each opening 228. Alternatively, the metal layer overlying the rear faces of the microelectronic elements 212 can be patterned by photolithography into individual leads extending from the vias onto locations overlying the rear faces of microelectronic elements 212, similar to the leads 66 overlying the rear faces 118 of microelectronic elements 12A in FIG. 9. Conductive bumps, e.g., solder bumps are balls, may then be formed at ends of the leads, as shown and described above with reference to FIG. 9.
In a particular embodiment, a metal composite can be deposited through a stencil or by screen-printing to fill the openings 228 in the stacked assembly and form leads which overlie the rear faces. Subsequently, the stacked assembly can be heated to cure the metal composite. The openings can be filled at the same time by the same deposition process as that which forms the leads or the openings can be filled at a different time or different process than that which forms the leads. The metal composite can include, for example, a metal-filled paste such as an epoxy-solder composition, silver-filled paste, or other flowable composition having a dielectric, e.g., polymeric component loaded with metal particles. The process of forming the leads can be additive; the leads can be formed by printing the metal composite through a screen or stencil onto the stacked assembly.
FIGS. 13 through 16 illustrate a method of fabricating a stacked assembly containing a plurality of microelectronic elements in accordance with a variation of the above-described embodiment (FIGS. 2A through 10A). FIG. 13 contains a series of sectional views (A) through (D) illustrating successive stages in the fabrication method. In stage (A) of FIG. 13, a reconstituted wafer 130 such as shown and described above (FIG. 5) is bonded with an adhesive layer 162 to a carrier 160 to form a structure similar to that shown in FIG. 6. The reconstituted wafer is bonded with the front faces 317 of the microelectronic elements 312, the contacts 22 thereon and the traces 24 extending therefrom being adjacent to the carrier 160. The traces may be such as to extend beyond only one or only some of the edges, e.g., edge 20—of each microelectronic element.
Then, as illustrated in stage (B) the reconstituted wafer is thinned to produce reconstituted wafer 310 by reducing the thickness of each microelectronic element 312 and the dielectric layer 116 such as by lapping, grinding or polishing the reconstituted wafer 130 from the rear faces 318 of the microelectronic elements 312.
After thinning the reconstituted wafer 310 to the desired thickness, a second reconstituted wafer 130A then is bonded (by adhesive layer 162A) to the first reconstituted wafer 310 with the front faces 317 of the microelectronic elements 312A facing toward the rear faces 318 of microelectronic elements 312 of the first reconstituted wafer 310 (stage (C)). The second reconstituted wafer 310A is bonded to the first reconstituted wafer in such way that an edge 340A of a microelectronic element 312A of the second reconstituted wafer 130A occurs at position 350A which is offset in a lateral direction 360 from the edge 340 of the first reconstituted wafer 310. Thus, when referring to microelectronic elements 312A of the second reconstituted wafer as the overlying microelectronic elements and microelectronic elements 312 of the first reconstituted wafer 310 as the underlying microelectronic elements, each of the overlying microelectronic elements 312A has an area overlapping an area of the underlying microelectronic element 312 to which it is bonded. Each of the overlying microelectronic elements 312A has an edge 340A that is displaced in the lateral direction 360 from the edge 340 of the underlying microelectronic element 312. The lateral offset distance between edges of vertically adjacent overlapping microelectronic elements can range from a few microns to tens of microns or more, for example.
With continued reference to FIG. 13, stage (D) shows the structure after thinning the second reconstituted wafer 130A in a manner such as described above (FIG. 13, stage (B)) to form reconstituted wafer 310A. The sub-processes shown with respect to stages (C) and (D) of FIG. 13 then are repeated for forming a third reconstituted wafer 310B containing microelectronic elements 312B and a fourth reconstituted wafer 310C containing microelectronic elements 312C to form the stacked assembly 330 shown in FIG. 14. As illustrated in FIG. 15, notches 346 are then cut between adjacent elements to expose the edges of the traces disposed on the front faces of the microelectronic elements in each reconstituted wafer 310, 310A, 310B and 310C.
An advantage of forming the stacked assembly in this manner is that process tolerances can improve for forming the leads 366. The lateral displacement of each overlapping microelectronic element in the stacked assembly relative to the microelectronic elements it overlies allows for slope in the sidewalls of each notch 346 formed therein. Increased lateral displacement allows the sidewalls of each notch 346 to be more heavily sloped, i.e., at a greater angle from the vertical. “Vertical” is defined herein as a normal angle to the plane defined by the contact-bearing surface of a microelectronic element, e.g., element 312. Despite greater slope of the wall, the notching operation, performed, e.g., by cutting or laser drilling exposes the edges of the traces even when the length of such traces is limited.
FIG. 16 is a plan view illustrating a microelectronic element 312 of one reconstituted wafer 310 of a stacked assembly in a variation of the above-described embodiment (FIG. 15). When the microelectronic elements 312 are provided with contact pads adjacent to edges 340 and 342 as illustrated in FIG. 16, a redistribution layer including additional traces 326 can be provided which extends between the pads at edge 342 and outwardly beyond a third edge 344 of the microelectronic element 312. When forming the stacked assembly 330 (FIG. 14), the edges 344 of overlapping microelectronic elements of each successively stacked reconstituted wafer 310, 310A, 310B and 310C can also be offset from edges 344 of underlying microelectronic elements in a direction 362. In this way, leads can be formed in channels which expose traces 328 along the third edges 344 of the overlapping microelectronic elements, and process tolerance can also be improved for forming such leads.
In a particular variation of the above-described embodiments, alignment features 560, 562 (FIG. 17) can be formed on the front faces 517 each microelectronic element 512 of the reconstituted wafer at a stage of fabrication when the outwardly extending traces 524 are formed. The alignment features can be formed of metal simultaneously with the traces 524 by the same processing which forms the traces, such processing illustrated and described above with respect to FIG. 5. Alternatively, the alignment features can be formed by different processing from that which forms the traces. Stated another way, the alignment features can be formed using all the same processing steps as used to form the traces or by performing at least one processing step different from the processing steps used to form the redistribution traces.
When the alignment features are formed by different processing, they may include a material which is not included in the traces 524. Likewise, traces 524 may include a material, e.g., a metal which is not included in the alignment features. Optionally, the alignment features may be formed to include a material which is particularly reflective of a wavelength of a source, e.g., an infrared source used to illuminate the alignment features.
The alignment features may include two or more types of features, e.g., closed features 560 and open features 562 to permit edges of each microelectronic element 512 to be distinguished and to facilitate alignment of each microelectronic subassembly within two dimensions. The alignment features 560, 562 may be aligned with the area of each underlying microelectronic element 512 such that the alignment features do not extend beyond the edges of each microelectronic element 512. Alternatively, some or all alignment features, e.g., feature 560′ may be only partially aligned with the area of the microelectronic element 512, such that the alignment feature extends beyond an edge of the microelectronic element 512. In another variation, as shown with respect to microelectronic element 512′, alignment features 560″ and 562″ are disposed at locations which lie beyond the edges 518′, 519′ of the microelectronic element 512′. Such alignment features 560″, 562″ may be aligned entirely or partially with the area that the later formed channels 46 (FIG. 9) will occupy. In this way, alignment features can be provided while at the same time permitting a compact layout to be achieved in the microelectronic elements.
The alignment features 560, 562 at the front face 517 of the first microelectronic subassembly 130 may be illuminated and detected by instruments disposed above the rear faces of microelectronic elements 12 that subassembly 130 when assembling a next subassembly 130A thereto in a process such as shown and described above (FIG. 7). Alternatively or in addition thereto, the alignment features 560, 562 at the front face 517 of the first microelectronic subassembly 130 and similar alignment features of the second microelectronic assembly 130A may be illuminated and detected by instruments disposed below the carrier layer 140 (FIG. 7) and below the front faces of microelectronic elements 12 of the first subassembly 130. In such case, the carrier layer 140 (FIG. 7) should have optical transmission characteristics that permit sufficient illumination by light passing through the thickness of the carrier layer 140.
1. A method of fabricating first and second stacked microelectronic units, comprising:
a) stacking and joining a plurality of microelectronic elements to form a stacked assembly thereof, each of the microelectronic elements having a front face, a rear face remote from the front face, contacts exposed at the front face, edges extending between the front and rear faces and traces connected to the contacts extending along the front face towards the edges, the front faces of at least some of the microelectronic elements overlying and confronting the rear faces of other microelectronic elements, wherein at least first and second microelectronic elements of the stacked assembly are spaced apart from one another in a direction parallel to their front faces, a third microelectronic element overlies the rear face of the first microelectronic element, and a fourth microelectronic element overlies the rear face of the second microelectronic element;
b) then forming at least one conductor extending from a trace of each of the first, second, third, and fourth microelectronic elements; and
c) severing the stacked assembly into the first and second microelectronic units, the first and second microelectronic units including the first and second microelectronic elements, respectively, such that a first portion of the at least one conductor extends along the edges of each of the first and third microelectronic elements and a second portion of the at least one conductor extends along the edges of each of the second and fourth microelectronic elements.
2. The method of claim 1, wherein each of the plurality of microelectronic elements is included in a microelectronic subassembly containing a plurality of microelectronic elements arranged in an array, wherein (a) includes stacking and joining a plurality of the microelectronic subassemblies and forming a plurality of openings extending between edges of stacked microelectronic elements therein.
3. The method of claim 1, wherein the plurality of microelectronic elements are stacked and joined to form a stacked assembly thereof on a carrier layer, and wherein the stacked assembly is severed into the first and second microelectronic units such that the carrier layer remains unsevered.
4. The method of claim 1, wherein alignment features are provided on the front faces of and adjacent to the edges of at least one of the first and second microelectronic elements, the method further comprising aligning edges of each of the microelectronic elements within the first and second stacked subassemblies using the alignment features.
5. The method of claim 4, further comprising forming the alignment features during and by the same processing as the traces on the front faces of the first and second microelectronic elements.
6. The method of claim 5, wherein at least some of the alignment features extend from the traces formed on the front faces of the first and second microelectronic elements.
7. The method of claim 4, wherein at least some of the alignment features include a material which is not included in the traces.
8. The method of claim 1, wherein at least one of a width and a length of the front faces of the first and third microelectronic elements differ.
9. The method of claim 1, wherein at least some of the conductors extend to unit contacts overlying and adjacent to the rear faces of the third and fourth microelectronic elements.
10. The method of claim 7, wherein solder balls are formed at the end of the at least one conductor to form the unit contacts.
11. The method of claim 1, further comprising exposing only a portion of a trace of at least one of the first and second stacked microelectronic units to form a unit contact for external interconnection thereof.
12. The method of claim 1, further comprising forming an inclined wall through the microelectronic elements of the first and third microelectronic elements, the inclined wall being at an angle relative to a normal direction with respect to a plane defined by the front faces of one of the first and second microelectronic elements and defining the edges of the microelectronic elements of the first and third microelectronic elements.
13. The method of claim 12, wherein the stacked assembly is formed on a carrier layer, and wherein the inclined wall does not extend through the carrier layer.
14. The method of claim 1, further comprising forming an overmold layer over the edges of at least the first and second microelectronic elements, the at least one conductor extending along the overmold layer.
15. The method of claim 1, wherein the first and second microelectronic elements are portions of a reconstituted wafer.
16. A stacked microelectronic unit, comprising:
first and second vertically stacked microelectronic elements, each of the first and second microelectronic elements having a front face, a rear face remote from the front face, edges extending between the front and rear faces, contacts at their respective front faces, each of the first and second microelectronic elements being electrically connectable and testable through the respective contacts;
a dielectric layer overlying at least first edges of the edges of the first and second microelectronic elements; and
conductive vias, each of the vias extending through one of a plurality of openings spaced apart within the dielectric layer and along the first edges of the first and second microelectronic elements, the vias being connected to traces at front faces of the microelectronic elements.
17. The stacked microelectronic unit of claim 16, wherein at least the first edge of the second microelectronic element overlies the first edge of the first microelectronic element.
18. A stacked microelectronic unit, comprising:
first and second vertically stacked microelectronic elements, wherein a front face of the first microelectronic element overlies at least one of a front face and a rear face of the second microelectronic element and at least one of a width and a length of the front faces of the first and second microelectronic elements differ;
a dielectric layer overlying edges of the first and second microelectronic elements;
a plurality of openings spaced apart within the dielectric layer in a lateral direction and extending along the first edges of the first and second microelectronic elements; and
leads extending through at least some of the plurality of openings, the leads being connected to traces at front faces of the microelectronic elements and extending along a first edge of the stacked unit.
US13/911,555 2007-07-27 2013-06-06 Reconstituted wafer stack packaging with after-applied pad extensions Active US8883562B2 (en)
US96220007P true 2007-07-27 2007-07-27
PCT/US2008/009207 WO2009017758A2 (en) 2007-07-27 2008-07-25 Reconstituted wafer stack packaging with after-applied pad extensions
US67095210A true 2010-05-14 2010-05-14
US13/911,555 US8883562B2 (en) 2007-07-27 2013-06-06 Reconstituted wafer stack packaging with after-applied pad extensions
US12670952 Continuation
PCT/US2008/009207 Continuation WO2009017758A2 (en) 2007-07-27 2008-07-25 Reconstituted wafer stack packaging with after-applied pad extensions
US67095210A Continuation 2010-05-14 2010-05-14
US20130344652A1 US20130344652A1 (en) 2013-12-26
US8883562B2 true US8883562B2 (en) 2014-11-11
ID=39768837
US12/670,952 Active 2029-02-20 US8461672B2 (en) 2007-07-27 2008-07-25 Reconstituted wafer stack packaging with after-applied pad extensions
US13/911,555 Active US8883562B2 (en) 2007-07-27 2013-06-06 Reconstituted wafer stack packaging with after-applied pad extensions
US (2) US8461672B2 (en)
EP (1) EP2186134A2 (en)
JP (1) JP5572089B2 (en)
KR (1) KR101458538B1 (en)
CN (1) CN101809739B (en)
WO (1) WO2009017758A2 (en)
DE202010000751U1 (en) 2010-01-08 2011-05-12 Big Dutchman International Gmbh Driving device for a membrane filtration device
US9070423B2 (en) * 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
JP2002217331A (en) 2000-10-23 2002-08-02 Matsushita Electric Ind Co Ltd Semiconductor chip, wiring board and their manufacturing method and semiconductor device
JP2003086762A (en) 2001-07-04 2003-03-20 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2003243606A (en) 2002-02-06 2003-08-29 Samsung Electronics Co Ltd Semiconductor chip and laminated chip package as well as manufacturing method thereof
US20030218191A1 (en) 2000-03-15 2003-11-27 Per-Erik Nordal Vertical electrical interconnections in a stack
US20040023438A1 (en) 1999-04-01 2004-02-05 Yoshimi Egawa Semiconductor package with a chip connected to a wiring substrate using bump electrodes and underfilled with sealing resin
US20040048419A1 (en) 2001-11-30 2004-03-11 Masahiko Kitamura Production method for semiconductor chip
JP2004080006A (en) 2002-06-18 2004-03-11 Sanyo Electric Co Ltd Method for manufacturing semiconductor device
US20050009302A1 (en) 2003-02-06 2005-01-13 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device
WO2006027981A1 (en) 2004-09-08 2006-03-16 Matsushita Electric Industrial Co., Ltd. Stereoscopic electronic circuit device, electronic device using the same, and method for manufacturing the same
2008-07-25 WO PCT/US2008/009207 patent/WO2009017758A2/en active Application Filing
2008-07-25 CN CN200880109094.9A patent/CN101809739B/en active IP Right Grant
2008-07-25 US US12/670,952 patent/US8461672B2/en active Active
2008-07-25 JP JP2010519235A patent/JP5572089B2/en active Active
2008-07-25 KR KR1020107004470A patent/KR101458538B1/en active IP Right Grant
2008-07-25 EP EP08794877A patent/EP2186134A2/en not_active Withdrawn
2013-06-06 US US13/911,555 patent/US8883562B2/en active Active
JPH0945848A (en) 1995-07-26 1997-02-14 Internatl Business Mach Corp <Ibm> End cap chip provided with conductive monolithic l connection for multi-chip stack use and its manufacture
US20050009236A1 (en) 1996-05-20 2005-01-13 Ball Michael B. Method of fabrication of stacked semiconductor devices
JP2001015683A (en) 1999-04-02 2001-01-19 Alcatel Transfer method of ultra-thin substrate and manufacture of multilayer thin film device using the same
JP2007243207A (en) 1999-08-19 2007-09-20 Seiko Epson Corp Wiring board and its manufacturing method, electronic component and its manufacturing method, circuit board, and electronic equipment
US7196418B2 (en) 2002-12-17 2007-03-27 Fujitsu Limited Semiconductor device and stacked semiconductor device that can increase flexibility in designing a stacked semiconductor device
CN1723556A (en) 2003-06-03 2006-01-18 卡西欧计算机株式会社 Semiconductor package having semiconductor constructing body and method of manufacturing the same
WO2008045422A2 (en) 2006-10-10 2008-04-17 Tessera, Inc. Edge connect wafer level stacking
KR20090079924A (en) 2006-10-10 2009-07-22 테세라, 인코포레이티드 Edge connect wafer level stacking
US20140027931A1 (en) 2007-08-03 2014-01-30 Tessera, Inc. Stack packages using reconstituted wafers
11 International Search Report and Written Opnion, PCT/US2007/021552 dated May 29, 2008.
Chinese Office Action for Application No. 200880110215.1 dated Apr. 19, 2013.
Chinese Office Action for Application No. 201110370722.2 dated Dec. 3, 2013.
International Search Report and Written Opinion from PCT/US2010/000777, dated Nov. 19, 2010.
International Search Report and Written Opinion, PCT/US08/09207, dated Jan. 16, 2009.
International Search Report and Written Opinion, PCT/US2008/009353 dated Feb. 10, 2009.
International Search Report and Written Opinion, PCT/US2008/009356, dated Feb. 19, 2009.
International Search Report and Written Opinion, PCT/US2008/010746, dated May 27, 2009.
International Search Report, PCT/US07/26095, dated Jul. 7, 2008.
International Search Report, PCT/US2008/002659 dated Oct. 17, 2008.
Japanese Office Action for Application No. 2010-519235 dated Nov. 13, 2012.
Japanese Office Action for Application No. 2011-514614 dated Jan. 17, 2014.
Japanese Office Action for Application No. 2011-514614 dated Sep. 13, 2013.
Korean Office Action for Application No. 10-2009-7009468 dated Oct. 31, 2013.
Partial International Search Report, PCT/US2008/002659 dated Jul. 16, 2008.
WO2009017758A2 (en) 2009-02-05
JP5572089B2 (en) 2014-08-13
US20110006432A1 (en) 2011-01-13
CN101809739B (en) 2014-08-20
CN101809739A (en) 2010-08-18
JP2010534951A (en) 2010-11-11
US20130344652A1 (en) 2013-12-26
EP2186134A2 (en) 2010-05-19
KR101458538B1 (en) 2014-11-07
US8461672B2 (en) 2013-06-11
WO2009017758A3 (en) 2009-04-02
KR20100047880A (en) 2010-05-10
US7910385B2 (en) 2011-03-22 Method of fabricating microelectronic devices
CN101681886B (en) 2014-04-23 Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices
US20060216858A1 (en) 2006-09-28 Vertically Stacked Semiconductor Device
US7749808B2 (en) 2010-07-06 Stacked microelectronic devices and methods for manufacturing microelectronic devices
CN101861646B (en) 2015-03-18 Stack packages using reconstituted wafers
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