Source: http://www.google.com/patents/US4404048?dq=6101531
Timestamp: 2013-12-18 10:56:43
Document Index: 331713416

Matched Legal Cases: ['art 2', 'arts 2', 'art 7', 'art 19', 'arts 2', 'arts 8']

Patent US4404048 - Semiconductor device manufacture - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsP-type isolation regions, which surround an island of an n-type epitaxial layer, are formed by providing a p-type dopant at a part of the surface of a p-type silicon substrate. After growing the layer a p-type dopant is also provided at the surface of the layer opposite the part of the substrate surface...http://www.google.com/patents/US4404048?utm_source=gb-gplus-sharePatent US4404048 - Semiconductor device manufactureAdvanced Patent SearchPublication numberUS4404048 APublication typeGrantApplication numberUS 06/321,500Publication dateSep 13, 1983Filing dateNov 16, 1981Priority dateDec 17, 1980Fee statusLapsedAlso published asDE3149158A1Publication number06321500, 321500, US 4404048 A, US 4404048A, US-A-4404048, US4404048 A, US4404048AInventorsDirk A. VogelzangOriginal AssigneeU.S. Philips CorporationExport CitationBiBTeX, EndNote, RefManPatent Citations (5), Referenced by (7), Classifications (22), Legal Events (6) External Links: USPTO, USPTO Assignment, EspacenetSemiconductor device manufactureUS 4404048 AAbstract P-type isolation regions, which surround an island of an n-type epitaxial layer, are formed by providing a p-type dopant at a part of the surface of a p-type silicon substrate. After growing the layer a p-type dopant is also provided at the surface of the layer opposite the part of the substrate surface where the dopant is provided. The dopants are diffused into the layer until the p-type regions meet. To inhibit diffusion of the p-type dopant during epitaxial growth, an n-type dopant having a lower diffusion coefficient than that of the p-type dopant is provided at the part of the substrate surface before providing the epitaxial layer. Formation of the isolation regions can be carried out simultaneously with the formation of p-type regions of a circuit element, for example a transistor, in the islands.
What is claimed is: 1. A method of manufacturing a semiconductor device, which comprises:providing a p-type monocrystalline silicon substrate having a major surface; providing a p-type dopant at a part of said major substrate surface and diffusing said dopant into the substrate; providing an n-type dopant having a smaller diffusion coefficient than that of said p-type dopant at said part of the major substrate surface where the p-type dopant is provided in order to inhibit diffusion of said p-type dopant; diffusing said n-type dopant into the substrate; then forming an n-type epitaxial silicon layer having an upper surface on said major surface of the substrate; providing a further p-type dopant at a part of said upper surface of the epitaxial layer opposite said part of the major surface of the substrate; and then diffusing said p-type dopants into the epitaxial layer from both sides by a thermal treatment to form diffused p-type regions which meet in said epitaxial layer. 2. A method as claimed in claim 1, wherein boron is provided at the substrate surface as said p-type dopant.
BACKGROUND OF THE INVENTION The invention relates to a method of manufacuturing a semiconductor device, in which a p-type dopant is provided at a part of a surface of a p-type monocrystalline silicon substrate and is diffused into the substrate, an n-type epitaxial silicon layer is then provided on the surface, after which a p-type dopant is provided at a part of the surface of the epitaxial layer opposite said part of the substrate surface, wherein the p-dopants are diffused into the epitaxial layer from two sides by a thermal treatment to form diffused p-type regions which meet each other in said layer.
SUMMARY OF THE INVENTION According to the invention, a method having the features mentioned in the opening paragraph is characterized in that in order to inhibit diffusion of the p-type dopant, an n-type dopant having a smaller diffusion coefficient than that of the p-type dopant is provided at the part of the substrate surface where the p-type dopant is provided and the n-type dopant is then diffused into the substrate before the epitaxial layer is provided.
BRIEF DESCRIPTION OF THE DRAWING An illustrative embodiment of the invention will now be described with reference to the accompanying drawing. The drawing is a diagrammatic sectional view of a part of a semiconductor device at a stage during its manufacture using a method in accordance with the invention. The manufacture of a circuit element forming part of an integrated circuit will be described hereinafter by way of example.
DESCRIPTION OF THE PREFERRED EMBODIMENTS A p-type dopant is provided at a part 2 (see the FIGURE) of a surface 3 of a p-type monocrystalline silicon substrate 1, and is diffused into the substrate 1.
In a conventional manner, after masking by means of an oxide provided by vapor deposition, a dose of 10.sup.19 boron atoms/cm.sup.2 is provided at parts 2 and 7 of the surface 3 as a p-type dopant. Diffusion at 1160
The part 7 of the surface 3 is then made bigger to form part 19 and a dose of 2 introduced into the substrate by ion implantation via the parts 2 and 19. P-type regions 6,20 and n-type regions 11,13 are formed by diffusion for 5 hours at 1250
A 40 μm thick n-type epitaxial silicon layer 4 having a resistivity of 35 Ωcm is then provided on the surface 3 of substrate 1. After masking, a dose of 2 dopant is provided in the usual manner at parts 8 and 14 of the surface 9 of the epitaxial layer 4.
In a subsequent thermal treatment at 1200 p-type dopant diffuses to form p-type regions 5, 10 and 12, 15 respectively, which meet each other in the epitaxial layer 4.
Patent CitationsCited PatentFiling datePublication dateApplicantTitleUS3663872 *Jan 19, 1970May 16, 1972Nippon Electric CoIntegrated circuit lateral transistorUS3667006 *Feb 19, 1970May 30, 1972Philips CorpSemiconductor device having a lateral transistorUS3930909 *Nov 26, 1974Jan 6, 1976U.S. Philips CorporationMethod of manufacturing a semiconductor device utilizing simultaneous outdiffusion during epitaxial growthUS4087900 *Oct 18, 1976May 9, 1978Bell Telephone Laboratories, IncorporatedFabrication of semiconductor integrated circuit structure including injection logic configuration compatible with complementary bipolar transistors utilizing simultaneous formation of device regionsUS4132573 *Feb 2, 1978Jan 2, 1979Murata Manufacturing Co., Ltd.Method of manufacturing a monolithic integrated circuit utilizing epitaxial deposition and simultaneous outdiffusion* Cited by examinerReferenced byCiting PatentFiling datePublication dateApplicantTitleUS4525922 *Oct 21, 1983Jul 2, 1985Fujitsu LimitedMethod of producing a semiconductor deviceUS4629520 *Aug 14, 1984Dec 16, 1986Fujitsu LimitedMethod of forming shallow n-type region with arsenic or antimony and phosphorusUS4721686 *Jan 22, 1987Jan 26, 1988Sgs Microelettronica S.P.A.Manufacturing integrated circuits containing P-channel MOS transistors and bipolar transistors utilizing boron and arsenic as dopantsUS4965215 *Dec 21, 1988Oct 23, 1990Sgs-Thomson Microelectronics S.R.L.Manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chipUS5132235 *Mar 29, 1991Jul 21, 1992Siliconix IncorporatedMethod for fabricating a high voltage MOS transistorUS5248624 *Aug 23, 1991Sep 28, 1993Exar CorporationMethod of making isolated vertical pnp transistor in a complementary bicmos process with eeprom memoryUSRE38510 *Feb 6, 1995May 4, 2004Stmicroelectronics SrlManufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip* Cited by examinerClassifications U.S. Classification438/357, 257/E21.136, 438/492, 257/552, 257/E21.544, 438/419, 257/E21.538, 257/544, 257/504, 257/565, 257/499International ClassificationH01L21/74, H01L21/22, H01L21/761, H01L29/73, H01L21/331Cooperative ClassificationH01L21/761, H01L21/2205, H01L21/743European ClassificationH01L21/22C, H01L21/74B, H01L21/761Legal EventsDateCodeEventDescriptionNov 21, 1995FPExpired due to failure to pay maintenance feeEffective date: 19950913Sep 10, 1995LAPSLapse for failure to pay maintenance feesApr 18, 1995REMIMaintenance fee reminder mailedFeb 25, 1991FPAYFee paymentYear of fee payment: 8Dec 29, 1986FPAYFee paymentYear of fee payment: 4Mar 15, 1982ASAssignmentOwner name: U.S.PHILIPS CORPORATION 100 EAST 42ND ST NEW YORK,Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:VOGELZANG, DIRK A.;REEL/FRAME:003956/0461Effective date: 19811125RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services©2012 Google