Source: https://patents.google.com/patent/US9437279B2/en
Timestamp: 2018-10-15 17:21:14
Document Index: 301521848

Matched Legal Cases: ['Application No. 10176311', 'Application No. 10150033', 'Application No. 10175885', 'Application No. 10177771', 'Application No. 05797483', 'Application No. 05797483', 'Application No. 10175885', 'Application No. 10176311', 'Application No. 10177771', 'Application No. 05797483', 'Application No. 10175885', 'Application No. 10176311', 'Application No. 10177771', 'Application No. 05797483', 'Application No. 10175885', 'Application No. 05797483', 'Application No. 10176311', 'Application No. 10177771', 'Application No. 10176311', 'Application No. 05797483', 'Application No. 10175885', 'Application No. 10177771', 'Application No. 05022021', 'Application No. 2009', 'Application No. 02009032', 'Application No. 02009032', 'Application No. 2008']

US9437279B2 - Memory controller with clock-to-strobe skew compensation - Google Patents
Memory controller with clock-to-strobe skew compensation Download PDF
US9437279B2
US9437279B2 US14951190 US201514951190A US9437279B2 US 9437279 B2 US9437279 B2 US 9437279B2 US 14951190 US14951190 US 14951190 US 201514951190 A US201514951190 A US 201514951190A US 9437279 B2 US9437279 B2 US 9437279B2
US14951190
US20160148671A1 (en )
G11C2207/2254—Calibration
A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.
This application is a continuation of U.S. patent application Ser. No. 14/267,446 filed May 1, 2014 and entitled “Memory Controller with Clock-To-Strobe Skew Compensation:” (now U.S. Pat. No. 9,229,470), which is a continuation of U.S. patent application Ser. No. 13/890,801 filed May 9, 2013 and entitled “Memory Module Having a Write-Timing Calibration Mode” (now U.S. Pat. No. 8,743,636), which is a continuation of U.S. patent application Ser. No. 13/741,255 filed Jan. 14, 2013 and entitled “Memory Controller Having a Write-Timing Calibration Mode” (now U.S. Pat. No. 8,493,802), which is a continuation of U.S. patent application Ser. No. 13/554,967 filed Jul. 9, 2012 and entitled “Memory Controller Having a Write-Timing Calibration Mode” (now U.S. Pat. No. 8,363,493), which is a continuation of U.S. patent application Ser. No. 13/228,070 filed Sep. 8, 2011 and entitled “Memory Component Having a Write-Timing Calibration Mode” (now U.S. Pat. No. 8,218,832), which is a division of U.S. patent application Ser. No. 12/757,035 filed Apr. 8, 2010 and entitled “Memory-Write Timing Calibration Including Generation of Multiple Delayed Timing Signals” (now U.S. Pat. No. 8,045,407), which is a division of U.S. patent application Ser. No. 12/246,415 filed Oct. 6, 2008 and entitled “Memory Controller with Multiple Delayed Timing Signals” (now U.S. Pat. No. 7,724,590), which is a division of U.S. patent application Ser. No. 11/746,007 filed May 8, 2007 and entitled “Memory Component with Multiple Delayed Timing Signals” (now U.S. Pat. No. 7,480,193), which is a continuation of U.S. patent application Ser. No. 10/942,225 filed Sep. 15, 2004 and entitled “Memory Systems with Variable Delays for Write Data Signals” (now U.S. Pat. No. 7,301,831). Each of the above-referenced U.S. Patent Applications is hereby incorporated by reference.
The disclosure herein relates generally to memory systems and methods. In particular, this disclosure relates to systems and methods for transferring information among memory components and a memory controller.
High-speed processor-based electronic systems have become all-pervasive in computing, communications, and consumer electronic applications to name a few. The pervasiveness of these systems, many of which are based on multi-gigahertz processors, has led in turn to an increased demand for high performance memory systems. As one example, FIG. 8 is a block diagram of a high performance memory system 800 under the prior art. This memory system 800 includes a memory controller 802 coupled to one or more memory component(s) 804. The memory controller 802 includes address circuitry 812 to drive address/control information outputs and write data circuitry 822 to drive write data information outputs to the memory component(s) 804.
FIG. 9 is a timing diagram 900 showing signals for a write operation in the memory system 800 under the prior art. Address/control information, “addr,” is placed on the address/control signal A0 by the memory controller in response to the first rising edge of the T0 timing signal. The address/control signal A0 is then driven onto the signal path as the A1 signal along with a rising edge of the corresponding TA1 signal. The A1 and TA1 signals propagate to the core circuitry of the memory component and become the A2 and TA2 signals at time tPD-A later.
In the drawings, the same reference numbers identify identical or substantially similar elements or acts. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the Figure number in which that element is first introduced (e.g., element 150 is first introduced and discussed with respect to FIG. 1).
Systems and methods for generating write data signals having variable delays for use in writing data to memory components are provided below. These systems and methods, also referred to herein as variable delay write circuitry, receive a write data signal and a corresponding data valid or timing signal (also referred to as a write data valid signal or write data timing signal) and in turn generate multiple delayed versions of the write data signals and delayed valid signals. The memory system selects one of these delayed write data signals and delayed data valid signals for use in writing data to memory components.
The storage circuits 154 of an embodiment couple to receive the delayed data valid signals T0+Y from the delay circuits 152 as well as write data signal W0, data valid signal T0, and control signal Sel[2, 1, 0]. The storage circuits in turn generate a number of delayed write data signals WD. Each delayed write data signal WD is delayed a period of time in a range of approximately 1.00 to 2.75 clock periods or cycles, as described below, but is not so limited. The delayed write data signals WD couple to the output circuits 156.
The output circuits 156 couple to receive the delayed write data signals WD from the storage circuits 154 and the delayed data valid signals T0+Y from the delay circuits 152. Additionally the output circuits 156 couple to receive the control signal Sel[2, 1, 0]. The output circuits 156 in response to information of the control signal Sel[2, 1, 0] select one of the delayed write data signals WD for the transfer of write data information as write data signal W1 to the memory components 104-2/104-3, as described below. Further, the output circuits 156 select one of the delayed data valid signals T0+Y for output to the memory components 104-2/104-3 as write data valid signal TW1 (also referred to as delayed write data valid signal TW1).
The delay line 202 (delayed signal) couples to a first input of the comparator 204 while the write data valid signal T0 (undelayed signal) couples to a second input of the comparator 204. The comparator uses information of a comparison between the write data valid signal T0 and the delayed write data valid signal of the delay line 202 (one clock period delay) to generate the control signal 206. The comparator outputs the control signal 206 for use in controlling delays or timing offsets of one or more of the unit delay elements DE1-DE4. The control signal 206 can be any of a variety of signal types known in the art, such as voltage bias signals, current bias signals, or digital delay-control signals. The offsets of the delay elements DE1-DE4 are controlled within a pre-specified range in response to variations in operating parameters of the memory system 100.
FIG. 3 is a timing diagram 300 showing the delayed data valid signals T0+Y (where “Y” is one of 0.00 (+1.00), +0.25, +0.50, and +0.75) along with the corresponding write data valid signals TW1 selected for output by the variable delay write circuitry, under an embodiment. With further reference to FIG. 2, the delay circuits 152 output the write data valid signal T0 (T0+0.00) along with three delayed data valid signals, as described above. The first delayed data valid signal T0+0.25 has a +0.25 period delay, the second delayed data valid signal T0+0.050 has a +0.50 period delay, and the third delayed data valid signal T0+0.075 has a +0.75 period delay (T0+0.75), but the embodiment is not so limited. The T0+1.00 timing signal will be approximately the same as the T0+0.00 signal, since T0 is periodic in this example.
The variable delay write circuitry outputs a write data valid signal TW1 302 delayed by approximately 1.00 period when the control signal Sel[2,1,0] includes logic values “000”. With further reference to FIG. 2, the first logic value (“0”) forms control signal Sel[2] which selects write data signal W0+0.00 as the output of multiplexer 220. The second and third logic values (“00”) of control signal Sel[1,0] select the timing signal T0+1.00 as the valid signal TW1 output 302 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.00 is generated using the next timing event (a rising edge in this example); the circuitry to do this is a component of enabling logic that creates timing events on the TW1 signal when the TW1 signal is not periodic). The control signal Sel[1,0] also selects the write data signal 234 (W0+1.00) as the write data signal W1 output from multiplexer 262.
The variable delay write circuitry outputs a write data valid signal TW1 304 delayed by approximately 1.25 periods when the control signal Sel[2,1,0] includes logic values “001”. The first logic value (“0”) forms control signal Sel[2] which selects write data signal W0+0.00 as the output of multiplexer 220. The second and third logic values (“01”) of control signal Sel[1,0] select the timing signal T0+0.25 as the valid signal TW1 output 304 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.25 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 238 (W0+1.25) as the write data signal W1 output of multiplexer 262.
The variable delay write circuitry outputs a write data timing signal TW1 306 delayed by approximately 1.50 periods when the control signal Sel[2,1,0] includes logic values “010”. The first logic value (“0”) forms control signal Sel[2] which selects write data signal W0+0.00 as the output of multiplexer 220. The second and third logic values (“10”) of control signal Sel[1,0] select the timing signal T0+0.50 as the valid signal TW1 output 306 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.50 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 242 (W0+1.50) as the write data signal W1 output of multiplexer 262.
The variable delay write circuitry outputs a write data timing signal TW1 308 delayed by approximately 1.75 periods when the control signal Sel[2,1,0] includes logic values “011”. The first logic value (“0”) forms control signal Sel[2] which selects write data signal W0+0.00 as the output of multiplexer 220. The second and third logic values (“11”) of control signal Sel[1,0] select the timing signal T0+0.75 as the valid signal TW1 output 308 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.75 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 246 (W0+1.75) as the write data signal W1 output of multiplexer 262.
The variable delay write circuitry outputs a write data timing signal TW1 310 delayed by approximately 2.00 periods when the control signal Sel[2,1,0] includes logic values “100”. The first logic value (“1”) forms control signal Sel[2] which selects write data signal W0+1.00 as the output of multiplexer 220. The second and third logic values (“00”) of control signal Sel[1,0] select the timing signal T0+1.00 as the valid signal TW1 output 310 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.00 is generated using the next timing event (a rising edge in this example); the circuitry to do this is a component of enabling logic that creates timing events on the TW1 signal when the TW1 signal is not periodic). The control signal Sel[1,0] also selects the write data signal 234 (W0+2.00) as the write data signal W1 output of multiplexer 262.
The variable delay write circuitry outputs a write data timing signal TW1 312 delayed by approximately 2.25 periods when the control signal Sel[2,1,0] includes logic values “101”. The first logic value (“1”) forms control signal Sel[2] which selects write data signal W0+1.00 as the output of multiplexer 220. The second and third logic values (“01”) of control signal Sel[1,0] select the timing signal T0+0.25 as the valid signal TW1 output 312 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.25 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 238 (W0+2.25) as the write data signal W1 output of multiplexer 262.
The variable delay write circuitry outputs a write data timing signal TW1 314 delayed by approximately 2.50 periods when the control signal Sel[2,1,0] includes logic values “110”. The first logic value (“1”) forms control signal Sel[2] which selects write data signal W0+1.00 as the output of multiplexer 220. The second and third logic values (“10”) of control signal Sel[1,0] select the timing signal T0+0.50 as the valid signal TW1 output 314 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.50 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 242 (W0+2.50) as the write data signal W1 output of multiplexer 262.
The variable delay write circuitry outputs a write data timing signal TW1 316 delayed by approximately 2.75 periods when the control signal Sel[2,1,0] includes logic values “111”. The first logic value (“1”) forms control signal Sel[2] which selects write data signal W0+1.00 as the output of multiplexer 220. The second and third logic values (“11”) of control signal Sel[1,0] select the timing signal T0+0.75 as the valid signal TW1 output 316 of multiplexer 264 (it is assumed that the T0 signal is periodic, so that a delay of T0+1.75 is generated using the next timing event). The control signal Sel[1,0] also selects the write data signal 246 (W0+2.75) as the write data signal W1 output of multiplexer 262.
As described above, control signals Sel[2,1,0] control selection of a write data signal W1 and the corresponding write data valid signal TW1 having a delay value appropriate to the signal paths between the memory controller and the memory components. The control signals are provided by one or more control circuits (not shown) that are components of and/or coupled to the memory controller. As an example, the control circuits of one or more embodiments can include one or more programmable registers. The content of the programmable registers, which control selection of the write data signal W1 and corresponding write data valid signal TW1 provided by the variable delay write circuitry, is determined in accordance with several approaches, including both automatic and user-programmable processes.
The pre-determined differences between the signal propagation times are determined during a calibration process, as described above, but are not so limited. This example assumes a difference between propagation delay times that results in selection of a 2.25 clock period delay (corresponding to control signal Sel[2,1,0] that includes logic values “101”).
Furthermore, the variable delay write circuitry of an embodiment also provides increased control over propagation delay differences in write operations to memory components of multiple-slice memory systems. FIG. 6 is a block diagram of a multiple-slice memory system 600 that includes the variable delay write circuitry 150 for generating write data signals and data valid signals with variable delays, under an embodiment. This memory system 600 includes a memory controller 602 coupled to one or more memory components 604-a in memory slice Sa and one or more memory components 604-b in memory slice Sb; while two memory slices are shown the embodiment is not limited to any number of memory slices and/or components. The memory controller 602 drives address/control signals A and address/control valid signals TA to the memory components 604-a/604-b.
Difficulty can be found in controlling the difference between the propagation delays of the TA/A signals and the TW/W signals in this multi-slice memory system because the TA/A signals are coupled to two or more memory components (slices). Each slice Sa and Sb therefore sees a different propagation delay on the TA/A signals (tPD-Aa, tPD-Ab) as a result. The delay of the TW/W signal groups (tPD-Wa, tPD-Wb) will however tend to be approximately the same, since these signal groups have a similar routing topology.
The variable delay write circuitry of an embodiment also provides increased control over propagation delay differences in write operations to memory components of multiple-rank memory systems. FIG. 7 is a block diagram of a multiple-rank memory system 700 that includes the variable delay write circuitry 150 for generating write data signals and data valid signals with variable delays, under an embodiment. This memory system 700 includes a memory controller 702 coupled to one or more memory components 704-z in memory rank Rz and one or more memory components 704-y in memory rank Ry; while two memory ranks are shown the embodiment is not limited to any number of memory ranks and/or components. The memory controller 702 drives write data signals W and write data valid signals TW to the memory components 704-z/704-y.
Difficulty can be found in controlling the difference between the propagation delays of the TA/A signals and the TW/W signals in this multi-rank memory system because the TW/W signals are coupled to two or more memory components (ranks). Each rank Rz and Ry therefore sees a different propagation delay on the TW/W signals (tPD-WZ, tPD-Wy) as a result. The delay of the TA/A signal groups (tPD-Az, tPD-Ay) will however tend to be approximately the same, since these signal groups have a similar routing topology.
The components of the memory systems described above include any collection of computing components and devices operating together. The components of the memory systems can also be components or subsystems within a larger computer system or network. The memory system components can also be coupled among any number of components (not shown), for example other buses, controllers, memory devices, and data input/output (I/O) devices, in any number of combinations. Many of these system components may be soldered to a common printed circuit board (for example, a graphics card or game console device), or may be integrated in a system that includes several printed circuit boards that are coupled together in a system, for example, using connector and socket interfaces such as those employed by personal computer motherboards and dual inline memory modules (“DIMM”). In other examples, complete systems may be integrated in a single package housing using a system in package (“SIP”) type of approach. Integrated circuit devices may be stacked on top of one another and utilize wire bond connections to effectuate communication between chips or may be integrated on a single planar substrate within the package housing.
Further, functions of the memory system components can be distributed among any number/combination of other processor-based components. The memory systems described above include, for example, various dynamic random access memory (DRAM) systems. As examples, the DRAM memory systems can include double data rate (“DDR”) systems like DDR SDRAM as well as DDR2 SDRAM and other DDR SDRAM variants, such as Graphics DDR (“GDDR”) and further generations of these memory technologies, i.e., GDDR2, and GDDR3, but is not limited to these memory systems.
1. A method of operation within an memory controller integrated circuit (IC) that controls operation of a memory IC, the method comprising:
outputting a first timing signal to a memory IC via a first timing signal line;
performing a timing calibration operation, including:
outputting a sequence of differently delayed calibration data timing signals to the memory IC via a second timing signal line,
identifying one of the calibration data timing signals that compensates for a difference in signal propagation times over the first and second timing signal lines, and
selecting, as a write timing delay, a delay value applied to generate the identified one of the calibration data timing signals; and
outputting signals to perform a write operation, including:
outputting address/control signals to be sampled by the memory IC at a time or times corresponding to one or more transitions of the first timing signal,
outputting write data to the memory IC in association with the address/control signals, and
outputting a write data timing signal, delayed according to the write timing delay, to the memory IC via the second timing signal line to time reception of the write data therein.
2. The method of claim 1 wherein identifying the one of the calibration data timing signals that compensates for the difference in signal propagation times over the first and second timing signal lines comprises identifying one of the calibration data timing signals that compensates for the difference in signal propagation times over the first and second timing signal lines better than others of the calibration data timing signals.
3. The method of claim 1 wherein identifying the one of the calibration data timing signals that compensates for the difference in signal propagation times over the first and second timing signal lines comprises identifying one of the calibration data timing signals that yields, at the first memory IC, a smaller timing mismatch with respect to the first timing signal at the first memory IC, than others of the calibration data timing signals.
4. The method of claim 3 wherein the timing mismatch with respect to the first timing signal at the first memory IC comprises, for each of the calibration data timing signals, a time interval between respective transitions of the calibration data timing signal and the first timing signal.
5. The method of claim 1 further comprising outputting signals to perform a sequence of dummy write operations as part of the timing calibration operation and wherein transmitting the sequence of differently delayed calibration data timing signals to the memory IC via the second timing signal line comprises transmitting each of the calibration data timing signals to the memory IC via the second timing signal line as part of a respective one of the dummy write operations.
6. The method of claim 5 wherein outputting signals to perform a sequence of dummy write operations as part of the timing calibration operation comprises outputting a plurality of calibration data sequences, each calibration data sequence to be received by the memory IC in response to transitions of a respective one of the calibration data timing signals.
7. The method of claim 6 further comprising, as part of performing the timing calibration operation, reading back each of the calibration data sequences from the memory IC and comparing each of the calibration data sequences read back from the memory IC with the corresponding calibration data sequence output to the memory IC to ascertain whether a successful dummy write operation was executed with respect to the calibration data sequence.
8. The method of claim 1 wherein outputting the sequence of differently delayed calibration data timing signals comprises selecting, during each of a sequence of time intervals, an output of a respective delay element within a chain of delay elements and transmitting the output of the respective delay element onto the second timing signal line.
9. The method of claim 8 further comprising controlling propagation delay through each delay element within the chain of delay elements using a locked-loop control circuit to establish respective phase-offsets between the differently calibration data timing signals.
10. The method of claim 8 wherein outputting the sequence of differently delayed calibration data timing signals comprises propagating an internal timing signal through the chain of delay elements, and wherein outputting the first timing signal via the first timing signal line comprises transmitting the internal timing signal via the first timing signal line.
11. A memory controller integrated circuit (IC) comprising:
first timing circuitry to outputting a first timing signal to a memory IC via a first timing signal line;
calibration circuitry to perform a timing calibration operation, including circuitry to:
output a sequence of differently delayed calibration data timing signals to the memory IC via a second timing signal line,
identify one of the calibration data timing signals that compensates for a difference in signal propagation times over the first and second timing signal lines, and
select, as a write timing delay, a delay value applied to generate the identified one of the calibration data timing signals; and
write circuitry to perform a write operation, including circuitry to:
output address/control signals to be sampled by the memory IC at a time or times corresponding to one or more transitions of the first timing signal,
output first write data to the memory IC in association with the address/control signals, and
output a write data timing signal, delayed according to the write timing delay, to the memory IC via the second timing signal line to time reception of the write data therein.
12. The memory controller IC of claim 11 wherein the circuitry to identify the one of the calibration data timing signals that compensates for the difference in signal propagation times over the first and second timing signal lines comprises circuitry to identify one of the calibration data timing signals that compensates for the difference in signal propagation times over the first and second timing signal lines better than others of the calibration data timing signals.
13. The memory controller IC of claim 11 wherein the circuitry to identify the one of the calibration data timing signals that compensates for the difference in signal propagation times over the first and second timing signal lines comprises circuitry to identify one of the calibration data timing signals that yields, at the first memory IC, a smaller timing mismatch with respect to the first timing signal at the first memory IC, than others of the calibration data timing signals.
14. The memory controller IC of claim 13 wherein the timing mismatch with respect to the first timing signal at the first memory IC comprises, for each of the calibration data timing signals, a time interval between respective transitions of the calibration data timing signal and the first timing signal.
15. The memory controller IC of claim 11 wherein the calibration circuitry further comprises circuitry to perform a sequence of dummy write operations as part of the timing calibration operation and wherein the circuitry to transmit the sequence of differently delayed calibration data timing signals to the memory IC via the second timing signal line comprises circuitry to transmit each of the calibration data timing signals to the memory IC via the second timing signal line as part of a respective one of the dummy write operations.
16. The memory controller IC of claim 15 wherein the circuitry to perform a sequence of dummy write operations as part of the timing calibration operation comprises circuitry to output a plurality of calibration data sequences, each calibration data sequence to be received by the memory IC in response to transitions of a respective one of the calibration data timing signals.
17. The memory controller IC of claim 16 wherein the calibration circuitry further comprises circuitry to read back each of the calibration data sequences from the memory IC and compare each of the calibration data sequences read back from the memory IC with the corresponding calibration data sequence output to the memory IC to ascertain whether a successful dummy write operation was executed with respect to the calibration data sequence.
18. The memory controller IC of claim 11 further comprising a chain of delay elements and wherein the circuitry to output the sequence of differently delayed calibration data timing signals comprises circuitry to selecting, during each of a sequence of time intervals, an output of a respective delay element within the chain of delay elements and transmit the output of the respective delay element onto the second timing signal line.
19. The memory controller IC of claim 18 further comprising a locked-loop control circuit to control propagation delay through each delay element within the chain of delay elements to establish respective phase-offsets between the differently calibration data timing signals.
20. A memory controller integrated circuit (IC) comprising
means for outputting a first timing signal to a memory IC via a first timing signal line;
means for performing a timing calibration operation, including:
means for outputting a sequence of differently delayed calibration data timing signals to the memory IC via a second timing signal line,
means for identifying one of the calibration data timing signals that compensates for a difference in signal propagation times over the first and second timing signal lines, and
means for selecting, as a write timing delay, a delay value applied to generate the identified one of the calibration data timing signals; and
means for outputting signals to perform a write operation, including:
means for outputting address/control signals to be sampled by the memory IC at a time or times corresponding to one or more transitions of the first timing signal,
means for outputting write data to the memory IC in association with the address/control signals, and
means for outputting a write data timing signal, delayed according to the write timing delay, to the memory IC via the second timing signal line to time reception of the write data therein.
US14951190 2004-09-15 2015-11-24 Memory controller with clock-to-strobe skew compensation Active US9437279B2 (en)
US10942225 US7301831B2 (en) 2004-09-15 2004-09-15 Memory systems with variable delays for write data signals
US11746007 US7480193B2 (en) 2004-09-15 2007-05-08 Memory component with multiple delayed timing signals
US12246415 US7724590B2 (en) 2004-09-15 2008-10-06 Memory controller with multiple delayed timing signals
US12757035 US8045407B2 (en) 2004-09-15 2010-04-08 Memory-write timing calibration including generation of multiple delayed timing signals
US13228070 US8218382B2 (en) 2004-09-15 2011-09-08 Memory component having a write-timing calibration mode
US13544967 US8363493B2 (en) 2004-09-15 2012-07-09 Memory controller having a write-timing calibration mode
US13554967 US9208191B2 (en) 2012-07-20 2012-07-20 Lock-free, scalable read access to shared data structures
US13741255 US8493802B1 (en) 2004-09-15 2013-01-14 Memory controller having a write-timing calibration mode
US13890801 US8743636B2 (en) 2004-09-15 2013-05-09 Memory module having a write-timing calibration mode
US14267446 US9229470B2 (en) 2004-09-15 2014-05-01 Memory controller with clock-to-strobe skew compensation
US14951190 US9437279B2 (en) 2004-09-15 2015-11-24 Memory controller with clock-to-strobe skew compensation
US15242425 US9830971B2 (en) 2004-09-15 2016-08-19 Memory controller with clock-to-strobe skew compensation
US15805009 US20180166118A1 (en) 2004-09-15 2017-11-06 Memory controller with clock-to-strobe skew compensation
US14267446 Continuation US9229470B2 (en) 2004-09-15 2014-05-01 Memory controller with clock-to-strobe skew compensation
US15242425 Continuation US9830971B2 (en) 2004-09-15 2016-08-19 Memory controller with clock-to-strobe skew compensation
US20160148671A1 true US20160148671A1 (en) 2016-05-26
US9437279B2 true US9437279B2 (en) 2016-09-06
ID=35502606
US10942225 Active 2026-01-06 US7301831B2 (en) 2004-09-15 2004-09-15 Memory systems with variable delays for write data signals
US11746007 Active US7480193B2 (en) 2004-09-15 2007-05-08 Memory component with multiple delayed timing signals
US12246415 Active US7724590B2 (en) 2004-09-15 2008-10-06 Memory controller with multiple delayed timing signals
US12757035 Active US8045407B2 (en) 2004-09-15 2010-04-08 Memory-write timing calibration including generation of multiple delayed timing signals
US13228070 Active US8218382B2 (en) 2004-09-15 2011-09-08 Memory component having a write-timing calibration mode
US13544967 Active US8363493B2 (en) 2004-09-15 2012-07-09 Memory controller having a write-timing calibration mode
US13741255 Active US8493802B1 (en) 2004-09-15 2013-01-14 Memory controller having a write-timing calibration mode
US13890801 Active US8743636B2 (en) 2004-09-15 2013-05-09 Memory module having a write-timing calibration mode
US14267446 Active 2024-09-22 US9229470B2 (en) 2004-09-15 2014-05-01 Memory controller with clock-to-strobe skew compensation
US14951190 Active US9437279B2 (en) 2004-09-15 2015-11-24 Memory controller with clock-to-strobe skew compensation
US15242425 Active US9830971B2 (en) 2004-09-15 2016-08-19 Memory controller with clock-to-strobe skew compensation
US15805009 Pending US20180166118A1 (en) 2004-09-15 2017-11-06 Memory controller with clock-to-strobe skew compensation
US (12) US7301831B2 (en)
EP (4) EP1820106A2 (en)
WO (1) WO2006031697A3 (en)
US10082823B1 (en) * 2017-10-11 2018-09-25 Integrated Device Technology, Inc. Open loop solution in data buffer and RCD
DE102005032059B3 (en) * 2005-07-08 2007-01-18 Infineon Technologies Ag Semiconductor memory module with bus architecture
JP4777807B2 (en) * 2006-03-29 2011-09-21 エルピーダメモリ株式会社 Stacked memory
US8207976B2 (en) * 2007-03-15 2012-06-26 Qimonda Ag Circuit
US8006045B2 (en) * 2009-02-27 2011-08-23 Atmel Rousset S.A.S. Dummy write operations
WO2012158392A3 (en) * 2011-05-17 2013-03-21 Rambus Inc. Memory system using asymmetric source-synchronous clocking
WO2016171934A1 (en) * 2015-04-20 2016-10-27 Netlist, Inc. Memory module and system and method of operation
US9843315B2 (en) 2011-11-01 2017-12-12 Rambus Inc. Data transmission using delayed timing signals
US9158330B1 (en) * 2011-11-15 2015-10-13 Marvell Israel (M.I.S.L) Ltd. Apparatus and method to compensate for data skew for multiple memory devices and adjust delay for individual data lines based on an optimized critical window
CN103366793B (en) 2012-03-28 2017-08-11 飞思卡尔半导体公司 SDRAM timing control data transmission
US8825978B2 (en) * 2012-06-04 2014-09-02 Macronix International Co., Ltd. Memory apparatus
US20140181452A1 (en) * 2012-12-26 2014-06-26 Nvidia Corporation Hardware command training for memory using read commands
US9824772B2 (en) * 2012-12-26 2017-11-21 Nvidia Corporation Hardware chip select training for memory using read commands
US9607714B2 (en) 2012-12-26 2017-03-28 Nvidia Corporation Hardware command training for memory using write leveling mechanism
US9378169B2 (en) 2012-12-31 2016-06-28 Nvidia Corporation Method and system for changing bus direction in memory systems
US9948809B2 (en) * 2013-02-01 2018-04-17 Canon Kabushiki Kaisha Image forming apparatus, memory management method for image forming apparatus, and program, using discretely arranged blocks in prioritizing information
US9136842B2 (en) * 2013-06-07 2015-09-15 Altera Corporation Integrated circuit device with embedded programmable logic
US9442842B2 (en) * 2013-08-19 2016-09-13 Sandisk Technologies Llc Memory system performance configuration
US9804931B2 (en) 2014-04-25 2017-10-31 Rambus Inc. Memory mirroring utilizing single write operations
US9330749B1 (en) * 2014-10-21 2016-05-03 Xilinx, Inc. Dynamic selection of output delay in a memory control device
US9866883B2 (en) 2016-06-02 2018-01-09 Biamp Systems Corporation Dynamic delay equalization for media transport
US9871020B1 (en) * 2016-07-14 2018-01-16 Globalfoundries Inc. Through silicon via sharing in a 3D integrated circuit
US10025677B2 (en) * 2016-12-05 2018-07-17 Arteris, Inc. Redundancy for cache coherence systems
US3820081A (en) 1972-10-05 1974-06-25 Honeywell Inf Systems Override hardware for main store sequencer
US4266282A (en) 1979-03-12 1981-05-05 International Business Machines Corporation Vertical semiconductor integrated circuit chip packaging
US4280221A (en) 1979-05-31 1981-07-21 The Boeing Company Digital data communication system
US4567545A (en) 1983-05-18 1986-01-28 Mettler Rollin W Jun Integrated circuit module and method of making same
US4654790A (en) 1983-11-28 1987-03-31 Amdahl Corporation Translation of virtual and real addresses to system addresses
US4785206A (en) 1985-07-05 1988-11-15 Nec Corporation Signal input circuit utilizing flip-flop circuit
US4866680A (en) 1977-12-05 1989-09-12 Scherbatskoy Serge Alexander Method and apparatus for transmitting information in a borehole employing signal discrimination
US4866677A (en) 1984-08-03 1989-09-12 Kabushiki Kaisha Toshiba Semiconductor memory device with multiple alternating decoders coupled to each word line
US4866678A (en) 1987-05-21 1989-09-12 Texas Instruments Incorporated Dual-port memory having pipelined serial output
US4866679A (en) 1988-08-11 1989-09-12 Western Atlas International, Inc. Method for identifying anomalous noise amplitudes in seismic data
US4866676A (en) 1988-03-24 1989-09-12 Motorola, Inc. Testing arrangement for a DRAM with redundancy
EP0379772A2 (en) 1989-01-27 1990-08-01 Digital Equipment Corporation Programmable data transfer timing
US5097489A (en) 1989-05-19 1992-03-17 Tucci Patrick A Method for incorporating window strobe in a data synchronizer
US5117389A (en) 1990-09-05 1992-05-26 Macronix International Co., Ltd. Flat-cell read-only-memory integrated circuit
US5164916A (en) 1992-03-31 1992-11-17 Digital Equipment Corporation High-density double-sided multi-string memory module with resistor for insertion detection
US5239639A (en) 1990-11-09 1993-08-24 Intel Corporation Efficient memory controller with an independent clock
US5329484A (en) 1992-06-02 1994-07-12 Nec Corporation Semiconductor memory circuit, semiconductor memory module using the same, and acoustic signal reproducing system
US5343427A (en) 1991-11-14 1994-08-30 Kabushiki Kaisha Toshiba Data transfer device
US5379438A (en) 1990-12-14 1995-01-03 Xerox Corporation Transferring a processing unit's data between substrates in a parallel processor
US5386375A (en) 1993-11-01 1995-01-31 Motorola, Inc. Floating point data processor and a method for performing a floating point square root operation within the data processor
US5406518A (en) 1994-02-08 1995-04-11 Industrial Technology Research Institute Variable length delay circuit utilizing an integrated memory device with multiple-input and multiple-output configuration
US5422858A (en) 1993-06-28 1995-06-06 Hitachi, Ltd. Semiconductor integrated circuit
US5428389A (en) 1990-06-14 1995-06-27 Fuji Photo Film Co., Ltd. Image data storage/processing apparatus
US5430676A (en) 1993-06-02 1995-07-04 Rambus, Inc. Dynamic random access memory system
US5511025A (en) 1993-10-18 1996-04-23 Texas Instruments Incorporated Write per bit with write mask information carried on the data path past the input data latch
EP0709786A1 (en) 1994-10-25 1996-05-01 Oki Electric Industry Co., Ltd. Semiconductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed
US5530623A (en) 1993-11-19 1996-06-25 Ncr Corporation High speed memory packaging scheme
JPH08227394A (en) 1994-07-05 1996-09-03 Monolithic Syst Technol Inc Data processing system and method for operating the same
US5560000A (en) 1992-05-28 1996-09-24 Texas Instruments Incorporated Time skewing arrangement for operating memory in synchronism with a data processor
EP0735492A1 (en) 1995-03-31 1996-10-02 Motorola, Inc. Method and apparatus for distributing bus loading in a data processing system
US5568445A (en) 1994-03-03 1996-10-22 Samsung Electronics Co., Ltd. Synchronous semiconductor memory device with a write latency control function
US5577236A (en) 1994-12-30 1996-11-19 International Business Machines Corporation Memory controller for reading data from synchronous RAM
US5578940A (en) 1995-04-04 1996-11-26 Rambus, Inc. Modular bus with single or double parallel termination
US5579352A (en) 1994-04-06 1996-11-26 National Semiconductor Corporation Simplified window de-skewing in a serial data receiver
US5708297A (en) 1992-09-16 1998-01-13 Clayton; James E. Thin multichip module
JPH1022458A (en) 1996-07-04 1998-01-23 Fujitsu Ltd Semiconductor device and pin array
EP0831402A1 (en) 1996-09-23 1998-03-25 Hewlett-Packard Company Dynamically configuring timing to match memory bus loading conditions
WO1998015897A1 (en) 1996-10-10 1998-04-16 Hewlett-Packard Company Memory system and device
US5742798A (en) 1996-08-09 1998-04-21 International Business Machines Corporation Compensation of chip to chip clock skew
US5796624A (en) 1994-09-16 1998-08-18 Research Foundation Of State University Of New York Method and apparatus for designing circuits for wave pipelining
US5819076A (en) 1995-09-12 1998-10-06 Micron Electronics, Inc. Memory controller with low skew control signal
EP0884732A2 (en) 1997-06-12 1998-12-16 Fujitsu Limited Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system
JPH117335A (en) 1997-04-25 1999-01-12 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit, system for reducing skew between clock signal and data signal and its method
US5867541A (en) 1994-05-18 1999-02-02 Hitachi, Ltd. Method and system for synchronizing data having skew
US5880998A (en) 1996-01-17 1999-03-09 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device in which current consumed by input buffer circuit is reduced
JPH1185345A (en) 1997-09-02 1999-03-30 Toshiba Corp Input/output interface circuit and semiconductor system
JPH11167515A (en) 1997-10-03 1999-06-22 Matsushita Electric Ind Co Ltd Data transmitter and data transmission method
US5933387A (en) 1998-03-30 1999-08-03 Richard Mann Divided word line architecture for embedded memories using multiple metal layers
US5933379A (en) 1996-11-18 1999-08-03 Samsung Electronics, Co., Ltd. Method and circuit for testing a semiconductor memory device operating at high frequency
WO1999041667A1 (en) 1998-02-13 1999-08-19 Intel Corporation Memory module including a memory module controller
US5943573A (en) 1997-01-17 1999-08-24 United Microelectronics Corp. Method of fabricating semiconductor read-only memory device
US5952691A (en) 1997-05-14 1999-09-14 Ricoh Company, Ltd. Non-volatile electrically alterable semiconductor memory device
WO1999046687A1 (en) 1998-03-12 1999-09-16 Hitachi, Ltd. Data transmitter
WO1999050852A1 (en) 1998-04-01 1999-10-07 Mosaid Technologies Incorporated Semiconductor memory asynchronous pipeline
US5966343A (en) 1997-01-02 1999-10-12 Texas Instruments Incorporated Variable latency memory circuit
JPH11284126A (en) 1998-03-31 1999-10-15 Fujitsu Ltd Electronic device
US5987576A (en) 1997-02-27 1999-11-16 Hewlett-Packard Company Method and apparatus for generating and distributing clock signals with minimal skew
JPH11328004A (en) 1998-05-12 1999-11-30 Fujitsu Ltd Method and system for memory control
US6003118A (en) 1997-12-16 1999-12-14 Acer Laboratories Inc. Method and apparatus for synchronizing clock distribution of a data processing system
US6005776A (en) 1998-01-05 1999-12-21 Intel Corporation Vertical connector based packaging solution for integrated circuits
US6016282A (en) 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
JP2000035831A (en) 1998-07-21 2000-02-02 Nec Corp Low skew clock tree circuit using variable threshold voltage transistor
US6034878A (en) 1996-12-16 2000-03-07 Hitachi, Ltd. Source-clock-synchronized memory system and memory unit
US6041419A (en) 1998-05-27 2000-03-21 S3 Incorporated Programmable delay timing calibrator for high speed data interface
US6044429A (en) 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
US6049238A (en) 1998-05-12 2000-04-11 Mitsubishi Denki Kabushiki Kaisha Clock generator and clock generating method capable of varying clock frequency without increasing the number of delay elements
US6049467A (en) 1998-08-31 2000-04-11 Unisys Corporation Stackable high density RAM modules
US6057743A (en) 1998-06-22 2000-05-02 Hubbell Incorporation Distributed noise reduction circuits in telecommunication system connector
US6065092A (en) 1994-11-30 2000-05-16 Hitachi Micro Systems, Inc. Independent and cooperative multichannel memory architecture for use with master device
US6067594A (en) 1997-09-26 2000-05-23 Rambus, Inc. High frequency bus system
US6070217A (en) 1996-07-08 2000-05-30 International Business Machines Corporation High density memory module with in-line bus switches being enabled in response to read/write selection state of connected RAM banks to improve data bus performance
US6075730A (en) 1997-10-10 2000-06-13 Rambus Incorporated High performance cost optimized memory with delayed memory writes
US6075393A (en) 1997-07-22 2000-06-13 Fujitsu Limited Clock synchronous semiconductor device system and semiconductor devices used with the same
US6075728A (en) 1997-02-28 2000-06-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device accessible at high speed
US6088774A (en) 1996-09-20 2000-07-11 Advanced Memory International, Inc. Read/write timing for maximum utilization of bidirectional read/write bus
US6105144A (en) 1998-03-02 2000-08-15 International Business Machines Corporation System and method for alleviating skew in a bus
US6111757A (en) 1998-01-16 2000-08-29 International Business Machines Corp. SIMM/DIMM memory module
US6115318A (en) 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
EP0849685A3 (en) 1996-12-19 2000-09-06 Texas Instruments Incorporated Communication bus system between processors and memory modules
JP2000243893A (en) 1999-02-17 2000-09-08 Fujitsu Ltd Integrated circuit device and module mounting it
WO2000054164A1 (en) 1999-03-05 2000-09-14 International Business Machines Corporation Dynamic wave-pipelined interface apparatus and methods therefor
US6124727A (en) 1997-07-11 2000-09-26 Adaptec, Inc. Bias compensator for differential transmission line with voltage bias
US6125419A (en) 1996-06-13 2000-09-26 Hitachi, Ltd. Bus system, printed circuit board, signal transmission line, series circuit and memory module
US6131149A (en) 1997-06-04 2000-10-10 Oak Technology, Inc. Apparatus and method for reading data from synchronous memory with skewed clock pulses
JP2000284873A (en) 1999-03-31 2000-10-13 Adtec:Kk Memory circuit board
US6137734A (en) 1999-03-30 2000-10-24 Lsi Logic Corporation Computer memory interface having a memory controller that automatically adjusts the timing of memory interface signals
US6151271A (en) 1998-01-23 2000-11-21 Samsung Electronics Co., Ltd. Integrated circuit memory devices having data selection circuits therein which are compatible with single and dual rate mode operation and methods of operating same
US6154417A (en) 1998-11-26 2000-11-28 Samsung Electronics Co., Ltd. Integrated circuit memory devices having synchronous wave pipelining capability and methods of operating same
US6154821A (en) 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
US6160754A (en) 1998-05-27 2000-12-12 Hyundai Electronics Industries Co., Ltd. Synchronous memory device of a wave pipeline structure
JP2000348490A (en) 1994-01-21 2000-12-15 Hitachi Ltd Memory device
US6172895B1 (en) 1999-12-14 2001-01-09 High Connector Density, Inc. High capacity memory module with built-in-high-speed bus terminations
US6178517B1 (en) 1998-07-24 2001-01-23 International Business Machines Corporation High bandwidth DRAM with low operating power modes
JP2001027918A (en) 1999-05-12 2001-01-30 Hitachi Ltd Directional coupling type memory system
JP2001044325A (en) 1999-07-30 2001-02-16 Hitachi Ltd Semiconductor device and semiconductor module
US6191997B1 (en) 2000-03-10 2001-02-20 Mosel Vitelic Inc. Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel.
US6211703B1 (en) 1996-06-07 2001-04-03 Hitachi, Ltd. Signal transmission system
US6219384B1 (en) 1995-06-26 2001-04-17 Phillip S. Kliza Circuit for determining clock propagation delay in a transmission line
US6226757B1 (en) 1997-10-10 2001-05-01 Rambus Inc Apparatus and method for bus timing compensation
US6226723B1 (en) 1996-09-20 2001-05-01 Advanced Memory International, Inc. Bifurcated data and command/address communication bus architecture for random access memories employing synchronous communication protocols
US6232792B1 (en) 1997-06-25 2001-05-15 Sun Microsystems, Inc. Terminating transmission lines using on-chip terminator circuitry
US6233157B1 (en) 1998-11-07 2001-05-15 Hyundai Electronics Industries Co., Ltd. Printed circuit board and method for wiring signal lines on the same
US6240039B1 (en) 1999-06-26 2001-05-29 Samsung Electronics Co., Ltd. Semiconductor memory device and driving signal generator therefor
US6253266B1 (en) 1999-02-19 2001-06-26 Inet Technologies, Inc. Apparatus and method for controlling information flow in a card cage having multiple backplanes
US6266737B1 (en) 1995-10-19 2001-07-24 Rambus Inc. Method and apparatus for providing a memory with write enable information
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6292877B1 (en) 1997-07-01 2001-09-18 Micron Technology, Inc. Plural pipelined packet-oriented memory systems having a unidirectional command and address bus and a bidirectional data bus
US20010026487A1 (en) 2000-03-16 2001-10-04 Kabushiki Kaisha Apparatus and method for controlling access to a memory system for electronic equipment
US6310171B1 (en) 1997-10-29 2001-10-30 Kanebo Limited Resin composition with biodegradability and foamability
US6321282B1 (en) 1999-10-19 2001-11-20 Rambus Inc. Apparatus and method for topography dependent signaling
US20010047450A1 (en) 1998-07-27 2001-11-29 Peter Gillingham High bandwidth memory interface
US6336205B1 (en) 1998-11-12 2002-01-01 Matsushita Electric Industrial Co., Ltd. Method for designing semiconductor integrated circuit
US6343352B1 (en) 1997-10-10 2002-01-29 Rambus Inc. Method and apparatus for two step memory write operations
US6356260B1 (en) 1998-04-10 2002-03-12 National Semiconductor Corporation Method for reducing power and electromagnetic interference in conveying video data
US6388886B1 (en) 2000-05-08 2002-05-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory module and module system
US6388934B1 (en) 2000-10-04 2002-05-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device operating at high speed with low current consumption
US6400625B2 (en) 2000-05-10 2002-06-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester
US6404258B2 (en) 2000-05-26 2002-06-11 Mitsubishi Denki Kabushiki Kaisha Delay circuit having low operating environment dependency
US6449159B1 (en) 2000-05-03 2002-09-10 Rambus Inc. Semiconductor module with imbedded heat spreader
US6449727B1 (en) 1998-05-07 2002-09-10 Kabushiki Kaisha Toshiba High-speed data transfer synchronizing system and method
US6456544B1 (en) 2001-03-30 2002-09-24 Intel Corporation Selective forwarding of a strobe based on a predetermined delay following a memory read command
US20020174311A1 (en) 2001-04-24 2002-11-21 Ware Frederick A. Method and apparatus for coordinating memory operations among diversely-located memory components
US6504790B1 (en) 2001-08-09 2003-01-07 International Business Machines Corporation Configurable DDR write-channel phase advance and delay capability
US6526469B1 (en) 1999-11-12 2003-02-25 International Business Machines Corporation Bus architecture employing varying width uni-directional command bus
US20030047757A1 (en) 2001-09-13 2003-03-13 Kabushiki Kaisha Toshiba Semiconductor integrated circuit and memory system
US6539454B2 (en) 1998-04-01 2003-03-25 Mosaid Technologies Incorporated Semiconductor memory asynchronous pipeline
US6545875B1 (en) 2000-05-10 2003-04-08 Rambus, Inc. Multiple channel modules and bus systems using same
US6553472B2 (en) 2001-01-12 2003-04-22 Sun Microsystems, Inc. Method for programming clock delays, command delays, read command parameter delays, and write command parameter delays of a memory controller in a high performance microprocessor
US20030076702A1 (en) 2001-10-23 2003-04-24 Samsung Electronics Co., Ltd. Semiconductor memory device having first and second memory architecture and memory system using the same
US20030112677A1 (en) 2001-12-13 2003-06-19 Gunther Lehmann Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits
US20030117864A1 (en) 2001-10-22 2003-06-26 Hampel Craig E. Phase adjustment apparatus and method for a memory device signaling system
US6618736B1 (en) 2001-03-09 2003-09-09 Ensim Corporation Template-based creation and archival of file systems
US6629222B1 (en) 1999-07-13 2003-09-30 Micron Technology Inc. Apparatus for synchronizing strobe and data signals received from a RAM
US20030200407A1 (en) 2000-05-18 2003-10-23 Hideki Osaka Memory system
US6640292B1 (en) 1999-09-10 2003-10-28 Rambus Inc. System and method for controlling retire buffer operation in a memory system
US6643752B1 (en) 1999-12-09 2003-11-04 Rambus Inc. Transceiver with latency alignment circuitry
US20040003194A1 (en) 2002-06-26 2004-01-01 Amit Bodas Method and apparatus for adjusting DRAM signal timings
US6680866B2 (en) 2001-10-05 2004-01-20 Renesas Technology Corp. Clock synchronous semiconductor memory device
US6697918B2 (en) 2001-07-18 2004-02-24 Broadcom Corporation Cache configured to read evicted cache block responsive to transmitting block's address on interface
US6748465B2 (en) 2001-09-28 2004-06-08 Intel Corporation Local bus polling support buffer
US20040120197A1 (en) 2002-01-11 2004-06-24 Tetsujiro Kondo Memory cell circuit, memory device, motion vector detection device, and motion compensation prediction coding device
US6760857B1 (en) 2000-02-18 2004-07-06 Rambus Inc. System having both externally and internally generated clock signals being asserted on the same clock pin in normal and test modes of operation respectively
JP2000174505A5 (en) 2004-07-22
US6788594B2 (en) 2001-02-28 2004-09-07 Rambus Inc. Asynchronous, high-bandwidth memory component using calibrated timing elements
EP0855653B1 (en) 1997-01-23 2004-10-06 Hewlett-Packard Company, A Delaware Corporation Memory controller with a programmable strobe delay
US6804764B2 (en) 2002-01-22 2004-10-12 Mircron Technology, Inc. Write clock and data window tuning based on rank select
US6807613B1 (en) 2000-08-21 2004-10-19 Mircon Technology, Inc. Synchronized write data on a high speed memory bus
US6807614B2 (en) 2001-07-19 2004-10-19 Shine C. Chung Method and apparatus for using smart memories in computing
US6813196B2 (en) 2000-06-30 2004-11-02 Hynix Semiconductor, Inc. High speed interface type semiconductor memory device
US6833984B1 (en) 2000-05-03 2004-12-21 Rambus, Inc. Semiconductor module with serial bus connection to multiple dies
US6839266B1 (en) 1999-09-14 2005-01-04 Rambus Inc. Memory module with offset data lines and bit line swizzle configuration
US6839393B1 (en) 1999-07-14 2005-01-04 Rambus Inc. Apparatus and method for controlling a master/slave system via master device synchronization
US6873939B1 (en) 2001-02-02 2005-03-29 Rambus Inc. Method and apparatus for evaluating and calibrating a signaling system
US6912680B1 (en) 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US6928571B1 (en) 2000-09-15 2005-08-09 Intel Corporation Digital system of adjusting delays on circuit boards
US6940782B2 (en) 2002-06-13 2005-09-06 Elpida Memory, Inc. Memory system and control method for the same
US6970988B1 (en) 2001-07-19 2005-11-29 Chung Shine C Algorithm mapping, specialized instructions and architecture features for smart memory computing
US20060056244A1 (en) 2004-09-15 2006-03-16 Ware Frederick A Memory systems with variable delays for write data signals
US20060077731A1 (en) 2001-04-24 2006-04-13 Ware Frederick A Memory module with termination component
US7057948B2 (en) 2003-04-28 2006-06-06 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having a test function
US7076745B2 (en) 2003-11-12 2006-07-11 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit device
US7095661B2 (en) 2003-12-25 2006-08-22 Elpida Memory, Inc. Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM
US7100066B2 (en) 2001-12-28 2006-08-29 Lg Electronics Inc. Clock distribution device and method in compact PCI based multi-processing system
US7102905B2 (en) 2003-11-06 2006-09-05 Elpida Memory, Inc. Stacked memory, memory module and memory system
US7159092B2 (en) 2001-06-28 2007-01-02 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US7224595B2 (en) 2004-07-30 2007-05-29 International Business Machines Corporation 276-Pin buffered memory module with enhanced fault tolerance
US7251162B2 (en) 2004-04-27 2007-07-31 Renesas Technology Corp. Nonvolatile memory with multi-frequency charge pump control
US7386696B2 (en) * 2003-07-08 2008-06-10 Infineon Technologies Ag Semiconductor memory module
US7457189B2 (en) 2001-07-20 2008-11-25 Samsung Electronics Co., Ltd. Integrated circuit memory devices that support selective mode register set commands and related methods
US7457174B2 (en) 2005-04-23 2008-11-25 Infineon Technologies Ag Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted
US20090251987A1 (en) 2006-08-30 2009-10-08 Advanced Micro Devices, Inc. Memory Data Transfer
US7610524B2 (en) 2004-08-10 2009-10-27 Micron Technology, Inc. Memory with test mode output
US20130028039A1 (en) 2011-07-26 2013-01-31 Inphi Corporation Power management in semiconductor memory system
GB8707313D0 (en) * 1987-03-26 1987-04-29 Alfa Lavel Cheese Systems Ltd Cheese block former
DE29512758U1 (en) * 1995-08-08 1995-10-19 Heidelberger Druckmasch Ag Cleaning device for cleaning cylinders of a printing press
JP3803204B2 (en) 1998-12-08 2006-08-02 シャープ株式会社 The electronic device
US6434081B1 (en) * 2000-05-12 2002-08-13 Micron Technology, Inc. Calibration technique for memory devices
US6760856B1 (en) 2000-07-17 2004-07-06 International Business Machines Corporation Programmable compensated delay for DDR SDRAM interface using programmable delay loop for reference calibration
US7313715B2 (en) 2001-02-09 2007-12-25 Samsung Electronics Co., Ltd. Memory system having stub bus configuration
US6877079B2 (en) * 2001-03-06 2005-04-05 Samsung Electronics Co., Ltd. Memory system having point-to-point bus configuration
KR100382736B1 (en) * 2001-03-09 2003-05-09 삼성전자주식회사 Semiconductor memory device having different data rates in read operation and write operation
KR100393217B1 (en) * 2001-03-09 2003-07-31 삼성전자주식회사 Memory module having control circuit for operating memory devices and data buffer by same clock frequency
US6883984B2 (en) * 2001-04-30 2005-04-26 Microsoft Corporation Keyboard with improved numeric section
US6678699B2 (en) * 2001-10-09 2004-01-13 International Business Machines Corporation Visual indexing of displayable digital documents
JP2003123493A (en) * 2001-10-12 2003-04-25 Fujitsu Ltd Nonvolatile memory in which program operation is optimized by controlling source potential
US7031207B2 (en) 2003-04-30 2006-04-18 Yamaha Corporation Semiconductor memory device with configurable on-chip delay circuit
US7126399B1 (en) 2004-05-27 2006-10-24 Altera Corporation Memory interface phase-shift circuitry to support multiple frequency ranges
US20060076702A1 (en) * 2004-10-07 2006-04-13 Fu-Chi Tsai Method of manufacturing a casing of an electronic product with surface decoration thereon
JP5072072B2 (en) 2007-03-15 2012-11-14 東洋ゴム工業株式会社 Polishing pad
US6314051B1 (en) 1990-04-18 2001-11-06 Rambus Inc. Memory device having write latency
US5606717A (en) 1990-04-18 1997-02-25 Rambus, Inc. Memory circuitry having bus interface for receiving information in packets and access time registers
US6266285B1 (en) 1990-04-18 2001-07-24 Rambus Inc. Method of operating a memory device having write latency
US6584037B2 (en) 1990-04-18 2003-06-24 Rambus Inc Memory device which samples data after an amount of time transpires
US5615358A (en) 1992-05-28 1997-03-25 Texas Instruments Incorporated Time skewing arrangement for operating memory in synchronism with a data processor
US5844855A (en) 1993-06-14 1998-12-01 Rambus, Inc. Method and apparatus for writing to memory components
US5646904A (en) 1994-10-25 1997-07-08 Oki Electric Industry Co., Ltd. Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed
US5663661A (en) 1995-04-04 1997-09-02 Rambus, Inc. Modular bus with single or double parallel termination
US5857095A (en) 1995-09-12 1999-01-05 Micron Electronics, Inc. Method for aligning a control signal and a clock signal
US6493789B2 (en) 1995-10-19 2002-12-10 Rambus Inc. Memory device which receives write masking and automatic precharge information
US7287109B2 (en) 1995-10-19 2007-10-23 Rambus Inc. Method of controlling a memory device having a memory core
US6681288B2 (en) 1995-10-19 2004-01-20 Rambus Inc. Memory device with receives write masking information
US6496897B2 (en) 1995-10-19 2002-12-17 Rambus Inc. Semiconductor memory device which receives write masking information
US5892981A (en) 1996-10-10 1999-04-06 Hewlett-Packard Company Memory system and device
US6278300B1 (en) 1997-09-02 2001-08-21 Kabushiki Kaisha Toshiba I/O interface circuit, semiconductor chip and semiconductor system
US6266730B1 (en) 1997-09-26 2001-07-24 Rambus Inc. High-frequency bus system
US6868474B2 (en) 1997-10-10 2005-03-15 Rambus Inc. High performance cost optimized memory
US6359815B1 (en) 1998-03-12 2002-03-19 Hitachi, Ltd. Data transmitter
US6240495B1 (en) 1998-05-12 2001-05-29 Fujitsu Limited Memory control system and memory control method
US6510503B2 (en) 1998-07-27 2003-01-21 Mosaid Technologies Incorporated High bandwidth memory interface
US6654897B1 (en) 1999-03-05 2003-11-25 International Business Machines Corporation Dynamic wave-pipelined interface apparatus and methods therefor
US7548601B2 (en) 1999-07-14 2009-06-16 Rambus Inc. Slave device with synchronous interface for use in synchronous memory system
US6516365B2 (en) 1999-10-19 2003-02-04 Rambus Inc. Apparatus and method for topography dependent signaling
US6684263B2 (en) 1999-10-19 2004-01-27 Rambus Inc. Apparatus and method for topography dependent signaling
US6950956B2 (en) 1999-10-19 2005-09-27 Rambus Inc. Integrated circuit with timing adjustment mechanism and method
US6590781B2 (en) 2000-05-10 2003-07-08 Rambus, Inc. Clock routing in multiple channel modules and bus systems
US6657871B2 (en) 2000-05-10 2003-12-02 Rambus Inc. Multiple channel modules and bus systems using same
US6765800B2 (en) 2000-05-10 2004-07-20 Rambus Inc. Multiple channel modules and bus systems using same
US6898085B2 (en) 2000-05-10 2005-05-24 Rambus Inc. Multiple channel modules and bus systems using same
US6724666B2 (en) 2001-02-23 2004-04-20 Micron Technology, Inc. Method of synchronizing read timing in a high speed memory system
US20040170072A1 (en) 2001-04-24 2004-09-02 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US20040054845A1 (en) 2001-04-24 2004-03-18 Rambus, Inc. Method and apparatus for signaling between devices of a memory system
US20050169097A1 (en) 2001-04-24 2005-08-04 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US20090138646A1 (en) 2001-04-24 2009-05-28 Ware Frederick A Method and apparatus for signaling between devices of a memory system
US20090063887A1 (en) 2001-04-24 2009-03-05 Ware Frederick A Memory module with termination component
US20070247935A1 (en) 2001-04-24 2007-10-25 Ware Frederick A Clocked Memory System with Termination Component
US20060007761A1 (en) 2001-04-24 2006-01-12 Ware Frederick A Memory module with termination component
US20060039174A1 (en) 2001-04-24 2006-02-23 Ware Frederick A Memory module with termination component
US20060069895A1 (en) 2001-04-24 2006-03-30 Ware Frederick A Method, system and memory controller utilizing adjustable write data delay settings
US20060129776A1 (en) 2001-04-24 2006-06-15 Ware Frederick A Method, system and memory controller utilizing adjustable read data delay settings
US20070255919A1 (en) 2001-04-24 2007-11-01 Ware Frederick A Memory controller device having timing offset capability
"Draft Standard for a High-Speed Memory Interface (SyncLink)," Draft 0.99 IEEE P1596.7-199X, pp. 1-56 (1996), Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society. 66 pages.
Commission Investigative Staffs' Response to Complaint's Motion for Leave to File a Reply to Commission Investigative Staffs' Response in Support of Respondents Motion for Summary Determination that U.S. Pat. Nos. 7,210,016 and 7,177,998 are invalid, dated Aug. 6, 2009, In the Matter of "Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same," Investigation No. 337-TA-661. 16 pages.
Crisp, Richard, "Direct Rambus Technology: The New Main Memory Standard," IEEE Micro, Nov./Dec. 1997, pp. 18-28. 11 pages.
EP Communication dated Jan. 5, 2011 for EP Application No. 10176311.8 re extended European Search Report. 9 pages.
EP Extended Search Report dated Apr. 15, 2010 re EP Application No. 10150033.8. 8 pages.
EP Extended Search Report dated Feb. 7, 2011 re EP Application No. 10175885.2. 7 pages.
EP Extended Search Report with mail date of Jan. 5, 2011 re EP Application No. 10177771.2. 8 pages.
EP Office Action dated Feb. 14, 2011 re EP Application No. 05797483.4. 6 pages.
EP Office Action dated Feb. 21, 2012 re EP Application No. 05797483.4. 8 pages.
EP Office Action dated Feb. 21, 2012 re EP Application No. 10175885.2. 5 pages.
EP Office Action dated Feb. 21, 2012 re EP Application No. 10176311.8. 9 pages.
EP Office Action dated Feb. 21, 2012 re EP Application No. 10177771.2. 8 pages.
EP Office Action dated Sep. 20, 2012 re EP Application No. 05797483.4, includes New Claims dated Jun. 5, 2012. 8 pages.
EP Office Action dated Sep. 20, 2012 re EP Application No. 10175885.2, includes New Claims dated Jun. 8, 2012. 7 pages.
EP Office Action dated Sep. 20, 2012 re EP Application No. 10176311.8, includes New Claim dated Jun. 13, 2012. 10 pages.
EP Office Action dated Sep. 20, 2012 re EP Application No. 10177771.2, includes New Claims dated Jun. 8, 2012. 8 pages.
EP Response dated Apr. 18, 2011 regarding European Application No. 05797483.4, including remarks in response to Official Communication, new claims with highlighted amendment, and new description p. 41. 12 pages.
EP Response dated Aug. 26, 2011 to the Official Communication dated Mar. 14, 2011 and to the European Search Opinion dated Feb. 7, 2011 re EP Application No. 10175885.2-1229. 15 pages.
EP Response dated Feb. 15, 2013 to the Official Communication dated Sep. 20, 2012 in EP Application No. 05797483.4-1229. 15 pages.
EP Response dated Jul. 12, 2011 to the Official Communication dated Feb. 7, 2011 and to the European Search Opinion dated Jan. 5, 2011 for EP Application No. 10176311.8-1229. 32 pages.
EP Response dated Jul. 15, 2011 to the Official Communication dated Feb. 7, 2011 and to the European Search Opinion dated Jan. 5, 2011 re EP Application No. 10177771.2-1229. 23 pages.
EP Response dated Jun. 13, 2012 to the Official Communication dated Feb. 21, 2012 in EP Application No. 10176311.8-1229, Includes New Claims 1-16. 16 pages.
EP Response dated Jun. 5, 2012 to the Official Communication dated Feb. 21, 2012 in EP Application No. 05797483.4-1229. 3 pages.
EP Response dated Jun. 8, 2012 to the Official Communication dated Feb. 21, 2012 in EP Application No. 10175885.2-1229, Includes New Claims 1-9. 9 pages.
EP Response dated Jun. 8, 2012 to the Official Communication dated Feb. 21, 2012 in EP Application No. 10177771.2-1229, Includes New Claims 1-11. 11 pages.
European Search Report and Written Opinion in EP Application No. 05022021.9, dated Jun. 1, 2006. 6 pages.
European Search Report and Written Opinion in European Patent Application 02009032.0-2212, dated Jul. 4, 2005. 9 pages.
Exhibit 26: Yang et al., "A Scalable 32Gb/s Parallel Data Transceiver with On-Chip Timing Calibration Circuits," IEEE International Solid State Circuits Conference, pp. 258-259, 2000. 2 pages.
Gillingham et al., "SLDRAM: High Performance Open-Standard Memory," IEEE Micro, Nov./Dec. 1997, pp. 29-39, vol. 17, No. 6, Institute of Electrical and Electronics Engineers, Inc., Los Alamitos, California. 11 pages.
Gillingham, Peter, "SLDRAM Architectural and Functional Overview," SLDRAM Consortium, Aug. 29, 1997, pp. 1-14. 14 pages.
IBM Corp., "Application Note: Direct Rambus Memory System Overview," Mar. 30, 1998, pp. 1-5. 6 pages.
IBM, "184 Pin DIMM Design Updates/Ramifications for Unbuffered and Registered DDR DIMMs," JC-42.5, Dec. 1999, pp. 1-12. 13 pages.
IBM, Micron Technology and Reliance Computer Corporation, "DDR SDRAM Registered DIMM," Design Specification, Revision 0.6, Nov. 1999. 62 pages.
IEEE Standard for Scalable Coherent Interface (SCI), "Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society," IEEE Std. 1596-1992. Aug. 2, 1993. 270 pages.
International Preliminary Report on Patentability (Chapter 1) dated Apr. 12, 2007, re International Application No. PCT/US2005/032770. 6 pages.
International Preliminary Report on Patentability and Written Opinion in International Application No. PCT/US2005/032346, dated Mar. 29, 2007. 10 pages.
International Search Report and Written Opinion dated May 10, 2006 in International Application No. PCT/US2005/042722. 15 pages.
International Search Report and Written Opinion in International Application No. PCT/US2005/032346, Apr. 18, 2006. 11 pages.
JP Response dated Mar. 30, 2012 re JP Application No. 2009-162534. 7 pages.
Kim, Y.R., "Memory Product Planning and Application," Samsung Electronics, DDR, Today and Tomorrow, Platform Conference, Jul. 18-19, 2000. 26 pages.
Lluis Paris, et al., WP 24.3 A 800MB/s 72 Mb SLDRAM with Digitally-Calibrated DLL, 1999 IEEE International Solid-State Circuits Conference, 0-7803-5129-0/99, 10 pages.
Nakase et al., "Source-Synchronization and Timing Vernier Techniques for 1.2 GB/s SLDRAM Interface," IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999, pp. 494-501. 8 pages.
Notice of Opposition with mail date of Apr. 8, 2008 re European Patent No. 1291778; Application No. 02009032.0; 23 pages.
Notice of Opposition with mail date of Apr. 8, 2008, re European Patent No. 1291778 with EP Application No. 02009032.0. 24 pages.
Paris et al., "WP 24.3: A 800 MB/s 72 Mb SLDRAM with Digitally-Calibrated DLL," ISSCC, 0-7803-5129-0/99, Slide Supplement, IEEE, 1999. 10 pages.
Poulton, John, "Signaling in High Performance Memory Systems," IEEE Solid State Circuits Conference, slides 1-59, Feb. 1999. 30 pages.
Rambus Inc., "8/9-Mbit (1Mx8/9) & 16/18Mbit (2Mx8/9) RDRAM-Preliminary Information," Rambus Inc. Data Sheet, Mar. 1, 1996. 30 pages.
Rambus Inc., "Direct RAC Data Sheet," Advanced Information, Last Modified Aug. 7, 1998, pp. 1-46. 46 pages.
Rambus Inc., "Direct Rambus Short Channel Layout Guide," Version 0.8, Mar. 2000. 34 pages.
Rambus Inc., "Rambus RIMM Module (with 64/72Mb RDRAMs)" Data Sheet, Preliminary Information, Document DL0078, Version 0.90, Mar. 1999, pp. 1-11. 11 pages.
Rambus Inc., "Rambus SO-RIMM Module (with 128/144Mb RDRAMs)," Advance Information, Document DL0076, Version 0.7, Feb. 2000, p. 1-12. 12 pages.
Rambus, Inc., "Direct RDRAM 256/288-Mbit (1Mx16/18x16d)," Preliminary Information, Document DL0105, Version 1.1, Aug. 2000. 72 pages.
Rambus, Inc., "Rambus RIMM Connector," Document DL 0069, Version 1.01, Jul. 1999. 14 pages.
Samsung Electronics Inc., "KMM377S1620CT2 SDRAM Module Datasheet," Rev. 1 (Nov. 1998), Preliminary, pp. 1-12. 12 pages.
Sato et al., "A 5-GByte/s Data-Transfer Scheme with Bit-to-Bit Skew Control for Synchronous DRAM," IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 653-660. 8 pages.
Seibert, Mike, "Competitive DDR Memory Sub-Systems," Micron Technology, Inc., DRAM Memory Enabling, Platform Conference, Jul. 18-19, 2000. 67 pages.
SLDRAM Inc., "SLD4M18DR400 4 MEG X 18 SLDRAM: 400 Mb/s/pin SLDRAM 4 M x 18 SLDRAM Pipelined, Eight Bank, 2.5 V Operation," Jul. 9, 1998. 69 pages.
SLDRAM Inc., 4M x 18 SLDRAM, Draft Advance, Jul. 9, 1998, pp. 1-69.
The Institute of Electrical and Electronics Engineers, "Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface Signaling Technology (RamLink)," Mar. 19, 1996, IEEE STD 1596.4-1996, XP002315223, pp. 12, 43-45. 5 pages.
Translation of Notice of Reasons for Rejection for Japanese Patent Application No. 2008-027486 mailed Jan. 9, 2009. 9 pages.
U.S. Appl. No. 13/923,634, Jun. 21, 2013, Ware et al.
Wang et al., "A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique," Apr. 2001, IEEE Journal of Solid-State Circuits, pp. 648-657, vol. 36. No. 4. 10 pages.
Wong et al., "Inserting Active Delay Elements to Achieve Wave Pipelining," IEEE 1989, p. 270-273. 4 pages.
Yeung et al., "A 2.4 Gb/s/pin Simultaneous Bidirectional Parallel Link with Per-Pin Skew Compensation," IEEE Journal of Solid-State Circuits, vol. 35, No. 11, pp. 1619-1627, Nov. 2000. 10 pages.
Yoo, Changsik, "DRAM Design 3," Samsung Electronics, High Speed DRAM Interface, Dec. 2001. 35 pages.
US20110317504A1 (en) 2011-12-29 application
US7480193B2 (en) 2009-01-20 grant
US20100188911A1 (en) 2010-07-29 application
US20170040047A1 (en) 2017-02-09 application
US20160148671A1 (en) 2016-05-26 application
WO2006031697A2 (en) 2006-03-23 application
US20180166118A1 (en) 2018-06-14 application
US9830971B2 (en) 2017-11-28 grant
EP2275942A2 (en) 2011-01-19 application
US20130262757A1 (en) 2013-10-03 application
US7724590B2 (en) 2010-05-25 grant
US20130176800A1 (en) 2013-07-11 application
EP2267603A3 (en) 2011-03-09 application
US20090063890A1 (en) 2009-03-05 application
US20140244923A1 (en) 2014-08-28 application
EP1820106A2 (en) 2007-08-22 application
EP2267603A2 (en) 2010-12-29 application
US8743636B2 (en) 2014-06-03 grant
US20060056244A1 (en) 2006-03-16 application
US9229470B2 (en) 2016-01-05 grant
EP2275942A3 (en) 2011-02-02 application
US8363493B2 (en) 2013-01-29 grant
EP2267604A3 (en) 2011-02-02 application
US20070206429A1 (en) 2007-09-06 application
US20120275237A1 (en) 2012-11-01 application
US8218382B2 (en) 2012-07-10 grant
US8045407B2 (en) 2011-10-25 grant
EP2267604A2 (en) 2010-12-29 application
US8493802B1 (en) 2013-07-23 grant
US7301831B2 (en) 2007-11-27 grant
WO2006031697A3 (en) 2006-06-29 application
US6480946B1 (en) 2002-11-12 Memory system for synchronized and high speed data transfer
US6680866B2 (en) 2004-01-20 Clock synchronous semiconductor memory device
US6446158B1 (en) 2002-09-03 Memory system using FET switches to select memory banks
US6215727B1 (en) 2001-04-10 Method and apparatus for utilizing parallel memory in a serial memory system
US5577236A (en) 1996-11-19 Memory controller for reading data from synchronous RAM
US20110016250A1 (en) 2011-01-20 System and method utilizing distributed byte-wise buffers on a memory module
US20060129712A1 (en) 2006-06-15 Buffer chip for a multi-rank dual inline memory module (DIMM)
Kushiyama et al. 1993 A 500-megabyte/s data-rate 4.5 M DRAM
US6745275B2 (en) 2004-06-01 Feedback system for accomodating different memory module loading
US6172893B1 (en) 2001-01-09 DRAM with intermediate storage cache and separate read and write I/O
US20090157994A1 (en) 2009-06-18 Memory module with reduced access granularity
US20060142977A1 (en) 2006-06-29 Circuits, systems and methods for dynamic reference voltage calibration
US20070008791A1 (en) 2007-01-11 DQS strobe centering (data eye training) method
US7948812B2 (en) 2011-05-24 Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
US6530006B1 (en) 2003-03-04 System and method for providing reliable transmission in a buffered memory system
US20050105318A1 (en) 2005-05-19 Memory module, memory chip, and memory system
US20130208546A1 (en) 2013-08-15 Latency control circuit and semiconductor memory device comprising same
US6646929B1 (en) 2003-11-11 Methods and structure for read data synchronization with minimal latency
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WARE, FREDERICK A.;REEL/FRAME:037200/0831