Source: http://www.google.com/patents/US7159102?dq=5,825,352
Timestamp: 2017-05-22 18:33:22
Document Index: 235455716

Matched Legal Cases: ['ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115', 'ART 115']

Patent US7159102 - Branch control memory - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA branch control memory store branch instructions which are adapted for optimizing performance of programs run on electronic processors. Flexible instruction parameter fields permit a variety of new branch control and branch instruction implementations best suited for a particular computing environment....http://www.google.com/patents/US7159102?utm_source=gb-gplus-sharePatent US7159102 - Branch control memoryAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS7159102 B2Publication typeGrantApplication numberUS 10/869,760Publication dateJan 2, 2007Filing dateJun 15, 2004Priority dateOct 1, 1999Fee statusLapsedAlso published asEP1089170A2, EP1089170A3, US6772325, US20040225871Publication number10869760, 869760, US 7159102 B2, US 7159102B2, US-B2-7159102, US7159102 B2, US7159102B2InventorsNaohiko Irie, Tony Lee WernerOriginal AssigneeRenesas Technology Corp.Export CitationBiBTeX, EndNote, RefManPatent Citations (94), Non-Patent Citations (9), Referenced by (19), Classifications (23), Legal Events (5) External Links: USPTO, USPTO Assignment, EspacenetBranch control memory
(1) deciding the branch outcome (2) calculating the branch target address (i.e., the location of the instruction that needs to be loaded) (3) transferring control so that the correct instruction is executed next In most systems, steps (1) and (2) must be resolved in this order by a branch instruction. Branch instructions also fall generally into two classes: conditional, and unconditional. When the branch is always taken it is referred to as an unconditional branch, and the above three operational steps are not required. A conditional branch is taken depending on the result of step (1) above. If the branch is not taken, the next sequential instruction is fetched and executed. If the branch is taken, the branch target address is calculated at step (2), and then control is transferred to such path at step (3). A good description of the state of the art in branch prediction can be found generally in section 4.3 of a textbook entitled Computer Architecture: A Quantitative Approach, 2nd edition, by Patterson and Hennessy; pages 262–278 are incorporated by reference herein.
Looking more specifically at the breakdown of the category (1) time penalty within a particular pipelined computing system, it can be seen to consist of the following: reading the branch operand (0 to 1 cycles); calculating the branch target address (1–2 cycles); and accessing the instruction cache and putting the target instruction into the decode stage of the pipeline (1–2 cycles). Thus, in a worst case scenario, a branch instruction latency of 5 cycles can be incurred. In some types of programs where branch instructions are executed with some regularity (i.e., 20% of the time) it is apparent that the average branch instruction penalty can be quite high (an average of 1 cycle per instruction).
Yet another approach is discussed in the following: (1) an article tided “Implementation of the PIPE Processor by Farrens and Pleszkun on pages 65–70 of the January 1991 edition of the journal Computer; and (2) an article tided “A Simulation Study of Architectural Data Queues and Prepare-T0-Branch Instruction,” by Young and Goodman on pages 544–549 of the October 1984 IEEE International Conference on Computer Design: VLSI in Computers, both of which are hereby incorporated by reference. In the scheme described in these references, a form of delayed branch is proposed by using a prepare-to-branch (PTB) instruction. The PTB instruction is inserted before the branch instruction, decides the branch outcome, and then specifies a delay before transfer of control. By ensuring that the delay is sufficiently large to guarantee the branch condition will have been evaluated when the instruction is completed, the pipeline is kept full. A problem with this approach, however, lies in the fact that the latency caused by the target address calculation (step 2) cannot be entirely accommodated, because it can be quite large. U.S. Pat. No. 5,615,386 to Amerson et. al., also incorporated by reference herein, also specifies the use of a PTB instruction. This reference also mentions that branch execution can be improved by separating the target address calculation (step (2)) from the comparison operation (step (1)). By computing the branch address out of order, latencies associated with branches can be further reduced. This reference discusses a number of common approaches, but is limited by the fact that: (1) It does not use a folded compare approach; thus separate compare and branch instructions are required, and this increases code size, dynamic execution time, etc; (2) the compare result must be recognized by way of an internal flag, instead of a register, and this reduces flexibility; (3) without using a register, such as a link register, execution of function subroutines is more challenging because it is more difficult to save/switch contexts; (4) the disclosure also relies on a kind of complex nomination process, whereby the execution of a loop effects the prediction weighting for a subsequent related loop.
FIGS. 2D–2L provide detailed visual and temporal illustrations of the operation of the pipeline during various branch operations;
FIGS. 3A–3H are timing diagrams indicating the timing and relationship of control signals asserted by the computing system when performing a branch handling operation;
(1) During decoding stage D, BRCTL sends the branch target address, IAR number, and branch prediction information to FECTL 101. If the prediction is that the branch will be taken, and the target instruction is already preloaded into IART 115, then it is read from this buffer, and loaded into D 120 so that it will be ready for decoding in the next cycle. (2) Still in decoding stage D, if IART 115 has not been preloaded, FECTL 101 sends a fetch request to IC 105 using the branch target address provided by BRCTL 150. This results in the instruction being loaded from cache 105 to IB 110 in time for it to be decoded in the event the prediction is proven accurate. If IART 115 has been preloaded, FECTL 101 sends a fetch request to IC 105 using the incremented target address in IAR.IA instead of the target address provided by BRCTL 150 to fetch the next instructions required as target instructions for IART 115. (3) If the prediction is “not-taken” in the decode stage, and the fall-through instruciton (the next instruction after the branch, but not the target of the branch if it were taken) is in IB 110, then it is shifted to be ready for decoding in the next cycle. FECTL 101 sends a preload request for the predicted not-taken instruction, if it is not already loaded into IART 115. This helps in the case that the branch is mis-predicted, because the target instruction will still be available if it later turns out to be needed. (4) In the E1 stage, BRCTL 150 receives the actual resolution of the branch condition, and verifies it against the prediction before the end of this cycle. BRCTL then provides the IAR number to FECTL to prepare for an actual branch in the E2 stage. (5) During the E2 stage, if the prediction is correct, everything proceeds normally. Otherwise, BRCTL sends a squash signal to remove invalid instructions from the stages that need purging. If it is the case that the branch was predicted not taken, but it actually was, then the BRCTL sends the correct target address to FECTL 101 with information that the branch was actually taken (AKTN command). FECTL 101 then changes the instruction stream to the correct target instruction, and additional instructions are demanded from IC 105 if needed. (6) If during the E2 stage the mis-prediction is of the other variety—i.e., predicted taken, and is actually not taken—BRCTL sends the PC of the instruction following the branch instruction to FECTL with information indicating that the prediction of “taken” failed (CONT command). FECTL then changes the execution direction back to sequential, and gets the next fall through instruction ready for decoding in the next cycle. (7) In case an unconditional branch is in the D stage, BRCTL 150 sends the branch target address and target register number to FECTL 101. If IART 115 is already preloaded, the target instruction is read and moved into D 120 to be decoded in the next cycle. If IART 115 is not preloaded, FECTL issues a fetch command to IC 105 to get the necessary target instructions. The above is a detailed accounting of the operation of the computing system 100 from a temporal perspective (i.e., looking at the status of particular pipeline stages at different times). An additional complementary accounting, taken from an instruction perspective (i.e., looking at the behavior of the computing system 100, and specifically BRCTL 150 in response to a specific type of branch instruction) is also provided further below.
(1) br_fe—pt_vld_el: this indicates that a branch control (PT) instruction in E1 is being executed (2) br_fe_br_addr [31:0]: this provides the branch target address (3) br_fe_pt_iar[2:0]: this indicates the IAR number pointed to by the PT instruction in the E1 stage (4) br_fe_pt_hint: indicates the value of the BHB of the PT instruction (5) br_fe_squash: this is used to squash a target fetch in case of a misprediction (6) br_fe_br_iarnum[2:0]: indicates the IAR number attached to br_fe_br13 command (7) br_fe_br_command: indicates a branch instruction. These commands are structured also to include the following information:
[i] PTKN: predict taken [ii] ATKN: actual taken [iii] CNT: continue=predict taken failed [iv] PRLD: preload [v] IDLE: idle BRCTL 150 also generates a “squash”—br_ppc_squash_dec and br_ppc_squash_E1, which are used by a pipeline control unit (not shown) to remove instructions from DEC 125 and ALU 130 when they are no longer valid. This type of instruction squashing operation is well-known in the art, and therefore any conventional implementation compatible with the present invention can be used. BRCTL 150 also receives the branch false signal referred to above, which is identified more specifically in other places in the figures as imu_fcmp_pred_ex1.
The same operation as above takes place, except that, when a branch control (PT) instruction is decoded by DEC 125, any necessary data must be read out from GPR 135, or PC_D 128 b (because of the flexible nature of the PT instruction, i.e., that displacements from the PC or register set can be used in computing target addresses) and set in E1 latch 127 b as an operand. During this same D stage, DEC 125 generates a series of control signals on line 129 to BRCTL, including dec_pt (indicating a decode of a PT instruction), as well as information for the additional parameters associated with the PT instruction, including dec_iar_pd and dec_hint. Next, during an E1 stage, the operands stored in E1 latch 127 b are operated on by ALU 130. At this same time, BRCTL 150 asserts a number of control signals on line 152 to FECTL 101, including br_fe_pt_el (indicating execution of a branch control instruction) and also br_fe_pt_iar and br_fe_pt_hint as discussed above. Again, in the preferred embodiment, the information for br_fe_pt_iar and br_fe_pt_hint were gleaned at the decoding stage D by DEC 125. During this same E1 stage, BRCTL 150 invalidates any instruction entry in IART 115 that exists having a target address stored in IAR.A 140 and pointed to by br_fe—pt_iar. This is done by setting the first (valid) bit in the instruction validity register to zero for such target instruction in HB 104. In addition, the br_fe_pt_hint information is used to set the second (hint) bit in HB 104 for the target instruction. After the E2 stage, the new target address is available for use in preloading, discussed further below. During the W stage, the results of ALU 130, including the calculation of the new target address, are stored in the IAR.A 140 entry designated by br_fe_pt_iar.
(1) Waiting for a target address to be calculated. Because of the fact that branch instructions can be quickly pre-decoded in the present invention, it is also necessary that the target address be ready at this time as well before they can be completely decoded. Since branch control (PT) instructions do not forward the target address until the E2 stage, there will be at least one “bubble” (a single stage gap in the pipeline where an instruction is not executed) created when a branch control (PT) instruction and a branch instruction are placed back to back. In most cases, however, a reasonably efficient compiler can ensure that there are more than enough instructions between the two to avoid such a problem. (2) Waiting for the target instruction to be fetched. This delay is a function of the latency cycles of IC 105 and whether IART 115 is ready with instructions. In the preferred embodiment described herein, IC 105 has a 2 cycle latency, and IART can hold 2 instructions. This means that the worst case scenario would require 2 cycles, and the best scenario would use no cycles. (3) Correcting pipeline loading for mis-predictions. Mis-predicted instructions must be “squashed” (removed from the pipeline); since corrections can be determined at the E2 stage, at most 2 instructions need to be removed. It can be seen from this table that, if preloading is successful (2 instructions ready in IART 115 as shown in the fourth column) then the present invention is extremely effective in reducing/eliminating latency in computing system 100.
FIGS. 3A to 3G are timing diagrams illustrating the various signals used (and their relationship) during operation of the embodiments described herein, including during a branch instruction handling process. These diagrams particularly describe: (1) the state of the pipeline stages; (2) the progress of the instruction stream therein; (3) the identity and relative timing relationship of the control signals discussed above generated by DEC 125, BRCTL 150, FECTL 101, and other control logic, for a number of particular operational states that may arise within computing system 100. In particular, the potential states that are described include: (1) FIG. 3A—an unconditional branch instruction being handled when IART 115 is ready with target instructions; (2) FIG. 3B—a conditional branch, with a prediction (hint bit) indicating that the branch will be taken, and IART 115 is ready with target instructions when such branch is actually taken; (3) FIG. 3C—as for FIG. 3B, except IART 115 is not ready; (4) FIG. 3D—a conditional branch, with a prediction (hint bit) indicating that the branch will not be taken, such branch is actually not taken, but IART 115 is not ready with target instructions; (5) FIG. 3E—a conditional branch, with a prediction (hint bit) indicating that the branch will not be taken, IART 115 is ready with target instructions; but such branch is actually taken; (6) FIG. 3F—same as 3E, except IART 115 is not ready; (7) FIG. 3G—same as FIG. 3D, except IART 115 is ready with target instructions. As used in these diagrams, T0–T7 refer to the IARs described above, and likewise ib0 refers to IB 110. These are but representative examples of potential instruction states, of course, and other combinations of the control signals required to handle other operational states of computing system 100 will be apparent to those skilled in the art from the present disclosure.
In addition, FIG. 3H depicts how an improved branch control (P”) instruction is handled by computing system 100. When an unconditional branch instruction (denoted blink in the figure) follows such instruction in the pipeline, the necessary target address for it has already been computed (at stage E1 by the PT instruction) and is thus usable to load a target address instruction (T0) during the execution stage (E1) of the branch instruction.
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