Source: http://www.google.com/patents/US6587529?dq=7,003,515
Timestamp: 2015-03-31 00:03:28
Document Index: 22532693

Matched Legal Cases: ['art.\n19', 'art.\n20', 'art.\n27', 'art.\n28', 'art.\n35', 'art.\n36']

Patent US6587529 - Phase detector architecture for phase error estimating and zero phase restarting - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inAdvanced Patent SearchPatentsA system and method for enabling an efficient Zero Phase Restart (ZPR) of a device. The structure is based on deploying normalized timing gradient (NTG) blocks (501 and 502) in pairs, each circuit employing an orthogonal phase error transfer function characteristic (having one TG circuit sample orthogonally...http://www.google.com/patents/US6587529?utm_source=gb-gplus-sharePatent US6587529 - Phase detector architecture for phase error estimating and zero phase restartingAdvanced Patent SearchPublication numberUS6587529 B1Publication typeGrantApplication numberUS 09/258,827Publication dateJul 1, 2003Filing dateFeb 25, 1999Priority dateFeb 25, 1999Fee statusPaidPublication number09258827, 258827, US 6587529 B1, US 6587529B1, US-B1-6587529, US6587529 B1, US6587529B1InventorsRobert B. Staszewski, Fulvio SpagnaOriginal AssigneeTexas Instruments IncorporatedExport CitationBiBTeX, EndNote, RefManPatent Citations (4), Referenced by (18), Classifications (14), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetPhase detector architecture for phase error estimating and zero phase restarting
A system and method for enabling an efficient Zero Phase Restart (ZPR) of a device. The structure is based on deploying normalized timing gradient (NTG) blocks (501 and 502) in pairs, each circuit employing an orthogonal phase error transfer function characteristic (having one TG circuit sample orthogonally in relation to the other), for example, PR4 and EPR4 modes ideal sampling instances of a preamble. An NTG block (501 or 502) is selected based on having a native timing sampling instance with a phase error that is closest to zero. Since there is an equal chance that either of the circuits in a circuit pair will be selected, if the circuit implementing the current non-native architecture is selected, a separate signal is generated. This signal adds the equivalent of 180� to the error value that is provided to the timing recovery circuit. For example, by iterating the process after the special case of a zero phase restart (ZPR) operation, the native sampling instance is �forced� to be selected thereafter.
wherein, if said non-native timing gradient circuit has a timing instance closer to zero phase error than said native timing gradient circuit, then an equivalent of 180� is added to said adjustment value x.
15. The system of claim 14 wherein said equivalent of 180� is input as a state to the memory for further processing prior to input to the timing recovery circuit.
16. The system of claim 14 wherein said equivalent of 180� is input as a separate signal to the timing recovery circuit for further processing.
18. The system of claim 14 wherein said equivalent of 180� is input as a state to the memory for further processing prior to input to the timing recovery circuit for use in initiating a zero phase restart.
19. The system of claim 14 wherein said equivalent of 180� is input as a separate signal to the timing recovery circuit for further processing prior to use in initiating a zero phase restart.
20. The system of claim 14 further enabling modulo/circular arithmetics, if the phase detector output corresponds to an equivalent of 180�, wherein adding the equivalent of 180� involves inverting the MSB bit of said phase detector output.
23. The phase detector of claim 22 wherein said equivalent of 180� is input as a state to the memory for further processing prior to input to the timing recovery circuit.
24. The phase detector of claim 22 wherein said equivalent of 180� is input as a separate signal to the timing recovery circuit for further processing.
26. The phase detector of claim 22 wherein said equivalent of 180� is input as a state to the memory for further processing prior to input to the timing recovery circuit for use in initiating a zero phase restart.
27. The phase detector of claim 22 wherein said equivalent of 180� is input as a separate signal to the timing recovery circuit for further processing prior to use in initiating a zero phase restart.
28. The phase detector of claim 22 further enabling modulo/circular arithmetics if the phase detector output corresponds to an equivalent of 180�, wherein adding the equivalent of 180� involves inverting the MSB bit of said phase detector output.
31. The mass data storage system of claim 30 wherein said equivalent of 180� is input as a state to the memory for further processing prior to input to the timing recovery circuit.
32. The mass data storage system of claim 30 wherein said equivalent of 180� is input as a separate signal to the timing recovery circuit for further processing.
34. The mass data storage system of claim 30 wherein said equivalent of 180� is input as a state to the memory for further processing prior to input to the timing recovery circuit for use in initiating a zero phase restart.
35. The mass data storage system of claim 30 wherein said equivalent of 180� is input as a separate signal to the timing recovery circuit for further processing prior to use in initiating a zero phase restart.
36. The mass data storage system of claim 30 further enabling modulo/circular arithmetics if the phase detector output corresponds to an equivalent of 180�, wherein adding the equivalent of 180� involves inverting the MSB bit of said phase detector output.
Digital mass data storage devices use RLL codes, when applied to data only, to improve signal-to-noise ratio (SNR) or to implement frequent updates to the timing recovery and automatic gain control loops, or both. The RLL codes use two parameters, d and k, controlling the minimum and maximum number of symbol intervals between transitions in the input signal, respectively. For a given d, the RLL code dictates at least �d+1�, and at most �k+1�, symbol intervals between transitions. Conventionally used codes are those with (d, k) constraints of (1, 7) and (2,7), generally used with peak detection methods.
These asynchronous methods detect single pulses. The �k� constraint insures that a non-zero channel output is produced with some minimum frequency to maintain robust operation of timing recovery and AGC loops. The �d� constraint insures acceptable SNR with peak detection.
Conventional methods for estimating the initial phase error for ZPR have been applied to determine �zero-crossings� of analog, i.e., continuous, time signals. Of course, this is inappropriate for handling discrete, or digital, pulses.
Some conventional disk drives, for example, use continuous time peak detection designs to recover digital data written as a series of magnetic transitions on a recording surface of a rotating magnetic disk. A voltage controlled oscillator (VCO) uses an �Enable� command for controlled starting and stopping of the oscillator. When the �Enable� command is asserted, the VCO begins oscillating in a known state. The rising edges of the clock's transition occur at a fixed delay interval after �Enable� is asserted.
In turn, �zero phase restart� (ZPR), also sometimes referred to as zero phase start, senses a logic transition of a read gate control signal (�Rd Gate�) from inactive to active, and disables the VCO. Upon arrival of a subsequent �transition edge� at the ZPR logic, �Enable� is reasserted and the timing control circuit VCO is restarted. A timing delay block compensates for the delays associated with detection and restart, which results in the next transition edge and the first clock output coinciding at the input to the phase-frequency detector. Starting phase error, is brought near zero while PLL acquisition time is reduced.
To reduce the complexity required to decode, the readback signal in the read channel is first equalized to a prescribed partial response (PR) signal. PR signals permit a controlled overlap of responses in the output signal. A priori knowledge of the �controlled overlap� significantly reduces the complexity of the required detector, compared to that required for an unequalized signal.
One commonly-used PR target signal in digital magnetic recording systems is characterized by the transfer function P(D)=1−D2, where D is the transform of the unit symbol delay operation. This PR signal is commonly referred to as a �Class IV PR� or �PR4.� The noise-free output response at a suitably prescribed sampling instant for PR4 is given by
where: n =  2 , 3 , � a  ( nT ) =  the   input   symbol   at   time   instant   nT , normally   picked  from   a   binary   alphabet , { 0 , 1 }   or   { 1 , - 1 } . That is, the output sample at time instant, nT, involves the overlap of two input symbols, a(nT) and a[(n−2)T].
The equalized signal is then detected using a sequence detector such as a Viterbi Detector (based on the Viterbi Algorithm). This combination of PR4 and Viterbi detection is commonly referred to as �PRML� for �partial response maximum-likelihood.�
The choice of the PR target signal is dictated by the linear density of the recording (as well as additional functions that may be required of the system). A single system may require two different PR target signals, e.g., PR4 and EPR4. Many PR targets exist for magnetic recording and are now commonly referred to as the �Extended Class IV� family of PR signals. The Extended Class IV family of PR signals is defined by the polynomials P(D))=(1−D)(1+D)n, where n is a positive integer. Note that n=1 yields the standard PR4 signal; while n=2 yields EPR4; and n=3 yields E2 PR4, etc.
A PRML read channel uses ML detectors to �read� data based on sampled sequences of an analog waveform read from a disk, rather than by analyzing a single peak as in conventional peak detection. These samples are obtained by using an ADC that samples and quantizes the read waveform at predetermined sampling intervals. The intervals are controlled by a clock synchronizing the ADC and the incoming signal. The clock also must be phase aligned to the incoming signal.
The time it takes a timing recovery circuit to recover a synchronous data clock signal impacts both the speed of acquisition and the amount of required disk space. In conventional disk drives, when the �READ� mode is entered, the PLL acquires the initial data clock frequency, f, and phase, φ, from a known preamble waveform, most often a sinusoid, that precedes the input signal.
By minimizing PLL acquisition time, performance and capacity are improved. Early conventional PLLs had long acquisition times, and failed to lock within a desired maximum time. This problem is identified in a paper by Floyd M. Gardner entitled �Hangup in Phase-Lock Loops�, EEE Transactions on Communications, Vol. COM-25, No. 10, October 1977. Gardner observes that acquisition may start around a �reverse-slope null�, i.e., a metastable point where the initial phase difference is halfway between two stable phase-locked operating points. In this instance, acquisition may take additional cycles. Further, the presence of non-negligible noise can exacerbate this.
There are other methods for acquiring and tracking a sampling frequency. Timing recovery methods for synchronous data receivers have been investigated by K. H. Mueller and M. M�ller, �Timing recovery in digital synchronous data receivers,� EEEE Trans. Commun., Vol. COM-24, pp. 516-530, May 1976, incorporated herein by reference. Specifically, for PRML it has been proposed by F. Dolivo, W. Schott, and G. Ungerboeck, �Fast timing recovery for partial response signaling systems,� Int. Conf. Commun. '89, ICC'89, Boston, Mass., June 1989 (incorporated herein by reference) to update the timing phase at time instant nT using the timing gradient defined as:
(error)=−y n �x n−1 +y n−1 �x n (2)
These designs use a timing gradient (TG) calculated using actual signal samples and estimated signal samples obtained from symbol-by-symbol decisions. See �Timing Recovery in Digital Synchronous Receivers� by K. H. Mueller and M. M�ller, supra.
One inherent drawback of these designs is that during acquisition the sampling point may occur at the point halfway between the desired sampling times. Consequently, the method for correcting the phase may reverse its direction of adjustment several times in the vicinity of this metastable equilibrium point for an extended period of time. Although this �hang-up� effect does not frequently occur, the length of the acquisition preamble must be sufficiently long so that the system may still synchronize given this situation. A long preamble, however, reduces the total amount of storage space available for user data.
Another approach uses a single �TG circuit� to gather a rough estimate of the ideal sampling instances. This yields ZPR samples that may be metastable. Further, if these samples are averaged to reduce noise contributions, and, if �hangup� is to be avoided, a hysteresis effect must be introduced in order to reduce the probability of reversals in the once chosen direction of timing and phase adjustment. Having this additional function, i.e., the introduction of hysteresis, to address further complicates the solution and also reduces performance by increasing latency.
A method for avoiding the �hang-up� effect in order to reduce the preamble length has been perfected. With this method, a sliding threshold, based on past estimated values around X(n), introduces a hysteresis effect that makes reversals in timing phase adjustments very unlikely. However, the estimated sample values around X(n) are reconstructed from the signal sample values, Y(n), and are therefore subject to error. Errors in the estimated sample values further increase the necessary length of the acquisition preamble. In order to minimize the initial phase error between the sampling clock and the preamble, ZPR has been used with conventional timing control circuits.
Upon obtaining an initial input-signal-to-clock phase difference, the VCO is stopped in order to adjust for any phase difference. The ZPR method applies a controlled phase delay within the timing control circuit, permitting a �restart� of the read channel in phase alignment with the incoming signal. A ZPR circuit for timing acquisition in a PRML recording channel is described in Dolivo et al., �Fast Timing Recovery for Partial-Response Signaling Systems�, Proc. of ICC '89 (IEEE), Jun. 11-14, 1989.
Conventional ZPR designs are susceptible to noise on both the clocking and the input signal. Noise on the input signal contributes to inaccurate phase measurement, leading to inaccurate phase correction that may increase actual acquisition time. One type of noise is termed �pulse pairing� noise. Pulse pairing causes adjacent pulses to have alternating, i.e., early and late, phase errors. Conventional ZPR designs do not detect pulse pairing since they rely on a single initial measurement.
Implementations of EPRML channels have been documented by R. Wood, �Turbo-PRML: A Compromise EPRML Detector,� IEEE Trans. on Magnetics, vol. 29, no. 6, pp. 4018-4020, November 1993, herein incorporated by reference, and E. Eleftheriou and W. Hirt, �Improving Performance of PRML/EPRML through Noise Prediction,� INTERMAG 96, Seattle, Wash., April 1996, also herein incorporated by reference. These implementations universally require a signal processing block after the conventional PR4 Viterbi detector in order to optimize EPRML performance without modifying the timing recovery circuit.
gain(e n)=e n �x n (5)
During acquisition, a sinusoid with a period equal to 4T is used to provide the signal amplitude reference. Either continuous-time or discrete-time methods can be used to implement the acquisition mode. See R. Cideciyan, F. Dolivo, R. Hermann, W. Hirt and W. Schott, �A PRML System for Digital Magnetic Recording,� IEEE Journal on Selected Areas in Communications, Vol. 10, No.1, pp. 38-56, January 1992 and R. Yamasaki, T-W. Pan, M. Palmer and D. Browning, �A 72 Mb/s PRML Disk-Drive Channel Chip with an Analog Sampled-Data Signal Processor,� Proc. of IEEE ISSCC, San Francisco, 1994, pp. 278-279 incorporated herein by reference.
Before the initiation of a ZPR operation, each circuit of the installed pair(s) of timing gradient (TG) circuits is normalized if the two TG slopes of each pair are not the same and to allow for use of the power of two modulo arithmetics. This insures the same values for transfer characteristics. The circuits are then activated to calculate phase errors within each of their respective timing sampling instances. At the moment of ZPR activation, the one circuit of each pair of circuits that is closest to zero (i.e., gives the better quality of the phase error estimate) phase error is selected via a comparator circuit. (If more than one pair of TG circuits is used, then that circuit of all of the included circuits with the lowest error value is selected.). Since the initial phase error distribution is uniform, either of the pair (or any of the circuits of multiple pairs) has an equal chance of being chosen. In the case where a non-native TG is closer to the desired timing sampling instances, a separate signal is generated indicating that a phase shift (e.g., the equivalent of 180� for one pair of TG circuits) should be added to the resultant phase error values. This equivalent of 180� addition could be cyclically added either in the phase detector (internally) or in the timing circuit (externally). After initial ZPR operation, the resultant phase error should approach zero, thus �forcing� selection of the native TG thereafter. Note that FIG. 8a provides angular measurements of a sinusoid (preamble) and FIGS. 8b and 8 c provide angular measurements of a bit.
A preferred method used for the starting phase selection in a timing recovery process involves receiving a �known� (to an accurate degree) frequency sampled signal at two similar TG circuits. The received sampled signal is sent in parallel to each TG circuit and a comparator, e.g., minimum of absolute value, compares the error values produced from each TG circuit. An adjusted starting phase is selected, based on a signal representing the lesser absolute value of the two error values. The timing recovery circuit is coasting during this period until the user wants to use it. The timing gradient closest to zero is then either latched or averaged over a few cycles until ZPR is initiated.
FIG. 8a is a depiction of sampling points for a preferred embodiment that shows PR4, EPR4, and �worst case� sampling points associated with both positive and negative timing gradient slopes.
FIG. 8b depicts the TG circuit transfer function for EPR4 native mode with PR4 mode superimposed with an appropriate offset equivalent to 180�.
FIG. 8c depicts the TG circuit transfer function for PR4 native mode with EPR4 mode superimposed with an appropriate offset equivalent to 180�.
The output from multiplexer 514FIG. 5 is provided as signal SEL_NTG along paths 518 and 518 b FIG. 5 to XOR gate 517 FIG. 5 and along path 518 and 518 a to multiplexer 506 FIG. 5. The output from the XOR gate 517FIG. 5 is provided as signal OTHER_TG to selection circuit SEL 520FIG. 5 along path 521 FIG. 5. Signal OTHER_TG provides the equivalent of 180� addition as necessary to adjust to a native timing gradient. The output from multiplexer 506FIG. 5 is also sent as signal NTG (normalized TG), a 7-bit signal to adjustment circuit SEL 520FIG. 5 along path 522 FIG. 5. From SEL 520FIG. 5, two output signals are provided. Along path 523FIG. 5, a 6-bit output signal is clocked by register along path 524 FIG. 5 and provided as the phase error signal PHERR output to the timing recovery control circuit (not shown). The optional signal indicating overflow, OV_NTG, is provided as a 1-bit signal along path 525FIG. 5 where it is clocked at path 526 FIG. 5 and output to an external receiver (not shown in FIG. 5). The contributions of the aforementioned signals will be elaborated on below.
For the �ZPR-disabled� mode. If the ZPR operation is not performed, the initial phase position may be in a metastable region of the NTG block 501FIG. 5 or 502FIG. 5, potentially causing a �hang-up.� Therefore, as in the �ZPR-enabled� mode, the NTG block 501FIG. 5 or 502FIG. 5 that exhibits an error closer to zero has to be initially selected by keeping LATCH_MIN, provided along path 512FIG. 5 to latch 511FIG. 5, at logic LOW. After a few clock cycles, it must be ensured that the NTG block 501FIG. 5 or 502FIG. 5 is selected by transitioning FIXED_SEL, provided along path 519FIG. 5 to multiplexer 514FIG. 5, to logic HIGH. Note that, assuming a uniform distribution of initial phase error, the chance of the initial phase being in the metastable region is quite small. However, should this occur, the resulting phase error, i.e., the error value produced by the opposite (non-native) NTG block 501FIG. 5 or 502FIG. 5, would be very stable and near its maximum value, ensuring a quick adjustment away from it.
A preferred embodiment will enable a more precise determination of phase error, in both amplitude and direction, by employing NTG blocks 501FIG. 5 and 502 FIG. 5 that implement phase error transfer characteristics that are orthogonal to each other. For each additional pair of circuits employed, accuracy is doubled. For example, using PR4 mode for one NTG block FIG. 5 and EPR4 mode for the other 502FIG. 5 of a pair, enables a 50% reduction of phase error. This is readily seen in FIG. 6. in which phase error, 602FIG. 6, is plotted against phase, φ 603 FIG. 6. By applying the Pythagorean Theorem, and observing that the error now is at worst case at π/2 604FIG. 6, the introduction of an additional TG circuit indicated by 607FIG. 6 to the single TG circuit indicated by 608FIG. 6, operating in a native mode orthogonal to that of the first TG circuit, has moved the worst case error from the position of π 605FIG. 6 to π/2 FIG. 6, thus halving the error as seen at 606FIG. 6, with respect to ideal decision line 601FIG. 6, compared to a single TG circuit as seen at 607 FIG. 6. Further, by employing additional pairs of orthogonal TG circuits, additional accuracy can be attained. See FIG. 7, depicting worst case phase error occurring in graph 703FIG. 7 for the case represented by 705FIG. 7 in which two pairs of TG circuits (thus 2�2=4 detectors) are used, at π/4 704 FIG. 7.
Note that it may be advantageous to add the necessary equivalent of 180� to the selected non-native TG value externally to the phase detector circuitry 501 or 502 FIG. 5. For example, if this value is computed in the timing recovery circuit PLL 201 in FIG. 2, the averaging would be done first before the divide-and- add function for adjusting from the non-native TG circuit.
The slope at the ideal sampling points of a PRML mode can be obtained by one of two methods, the derivative method or the maximum range slope method. The derivative method is derived as follows for the PR4 mode and the EPR4 mode: PR4 _   Mode _   Δ 0 =   θ  A   sin  ( π 4 ) = A   cos  π 4 = 2 2  A (6a)  Φ 0 = 2 � 2 2  A = 2  A (6b) EPR4 _   Mode _   Δ 1 =   θ  A   sin  ( 0 ) = A   cos   0 = A (6c)  Φ 1 = A (6d) Ratio _   Φ 0 Φ 1 = 2  A A = 2 (6e) where: Δ 0 = slope   for   PR4   native   timing   mode Δ 1 = slope   for   EPR4   native   timing   mode Φ 0 = phase   error   for   PR4   native   timing   mode The maximum range slope method is derived as follows for the PR4 mode and the EPR4 mode: PR4 _   Mode _   Φ 0 = A π 2 (7a) EPR4 _   Mode _   Φ 1 = 2 2  A π 2 (7b) Ratio _   Φ 0 Φ 1 = A π 2 2 2  A π 2 = 2 (7c) A key point in determining phase error, that any estimate is a function of amplitude of the signal, A 802 in FIG. 8. Thus, if the estimate of the signal amplitude, �, is not accurate, the initiation of ZPR will not be accurate.
FIGS. 8b and 8 c depict detector output, A 802, versus phase error, 803, for EPR4 native timing instance mode 804� FIG. 8 and PR4 native timing instance mode 801′ FIG. 8, respectively. Observe the relative position of FIGS. 8a, 8 b, and 8 c, and note that the EPR4 and PR4 timing instances are orthogonal to one another and that the worst case of their respective deviations from the desired decision line (the 45� line through the origin) 601FIG. 6 occurs at π/2 805FIG. 8, and odd multiples thereof. Also note that the two modes for each pair must be normalized, if their slopes differ, in order to be able to correctly select the amplitude, A 802FIG. 8, of the NTG block 501FIG. 5 or 502FIG. 5 that is closest to zero phase error. The normalization is shown in FIG. 9 where it can be seen that normalized 901FIG. 9 is at the same slope as normalized NTG0 903FIG. 9 as compared to un-normalized TG1 902 FIG. 9 and TG0 904 FIG. 9.
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