Source: http://patents.com/us-8901740.html
Timestamp: 2019-01-16 21:22:02
Document Index: 511416740

Matched Legal Cases: ['Application No. 2011', 'Application No. 2011', 'Application No. 200980139236', 'Application No. 09837819', 'Application No. 098142486', 'Application No. 200980139236', 'Application No. 200980139236']

US Patent # 8,901,740. Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes - Patents.com
United States Patent 8,901,740
Mukherjee , et al. December 2, 2014
Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes
A contact may be fabricated by a method including depositing a dielectric layer on a substrate having a transistor, etching a first opening in the dielectric layer that extends to a source region, forming an insulator on the source region, forming a contact metal on the insulator, the insulator separating the contact metal from the source region, and filling substantially all of the first opening, wherein the contact metal remains separated from the source region after the first opening is filled.
Mukherjee; Niloy (Beaverton, OR), Dewey; Gilbert (Hillsboro, OR), Metz; Matthew V. (Portland, OR), Kavalieros; Jack (Portland, OR), Chau; Robert S. (Beaverton, OR)
Mukherjee; Niloy
Dewey; Gilbert
Metz; Matthew V.
Kavalieros; Jack
Chau; Robert S.
Family ID: 1000000807263
13/352,062
US 20120115330 A1 May 10, 2012
12317126 Dec 19, 2008 8110877
Current U.S. Class: 257/774; 438/233; 438/637; 438/648; 438/675; 438/682
Current CPC Class: H01L 29/785 (20130101); H01L 29/456 (20130101); H01L 21/823475 (20130101); H01L 29/452 (20130101); H01L 23/485 (20130101); H01L 21/76831 (20130101); H01L 29/66795 (20130101); H01L 21/28512 (20130101); H01L 29/41791 (20130101); H01L 29/0895 (20130101); H01L 21/823431 (20130101); H01L 21/823418 (20130101); H01L 29/518 (20130101); H01L 29/78 (20130101); H01L 29/66545 (20130101); H01L 29/517 (20130101)
Field of Search: ;438/233,637,648,675,682,683
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This application is a divisional of U.S. patent application Ser. No. 12/317,126 filed Dec. 19, 2008.
1. A method to make a contact, comprising: depositing a dielectric layer on a substrate having a transistor; etching a first opening in the dielectric layer that extends to a source region; forming an insulator on the source region; forming a contact metal on the insulator, the insulator and contact metal formed by a conformal deposition process the insulator separating the contact metal from the source region wherein the insulator at least partially release the metal Fermi level from the semiconductor source or drain region; and filling substantially all of the first opening, wherein the contact metal remains separated from the source region after the first opening is filled.
2. The method of claim 1, wherein the insulator has a thickness of about 4 nanometers or less.
3. The method of claim 2, wherein the insulator has a thickness of about 1 nanometer or less.
4. The method of claim 2, wherein forming the insulator comprises forming a conformal layer of the insulator.
5. The method of claim 1, wherein the transistor is a multigate transistor, wherein the insulator is formed on a top and on side walls of a fin of the multigate transistor to result in an insulator top and insulator side walls, and wherein the contact metal is formed on the insulator top and on the insulator side walls.
The contact includes an insulating layer 114 that is conformal to the trench and is adjacent the source and drain regions 106, 108 in the illustrated embodiment. Adjacent the insulating layer 114 is a conducting layer 116. The insulating layer 114 separates the conducting layer 116 from the source and drain regions 106, 108 (or from whatever component the contact is for). While the conducting layer 116 is not in direct contact with the source and drain regions 106, 108, it still functions as an electrical contact. This may occur by the insulating layer 114 wholly or partially depinning the metal Fermi level from the semiconductor source or drain region 106, 108. Thus, the inclusion of an insulating layer 114 between the conducting layer 116 and the source or drain region 106, 108 may actually reduce the resistance of the contact over a situation where a conductor is in direct contact with the source or drain region 106, 108. Such contacts may allow a Specific Contact Resistivity, .rho..sub.c, of approx 1.times.10.sup.-7 ohm-.mu.m.sup.2 (ohm-micrometer squared) or less on low-doped (doping level .about.1.times.10.sup.17 at/cm.sup.3) silicon in some embodiments, which is 5.times.-10.times. less than traditional silicide contacts (e.g., NiSi, TiSi2, CoSi2) on Si of the same doping level. This type of contact may also allow the tuning of the Schottky barrier height and contact resistance as desired for optimal device 100 performance.
As shown in FIG. 2, after the trenches 112 are formed 204, an insulating layer 114 may be deposited 206 in the trenches 112. FIG. 5 is a cross sectional side view that illustrates the insulating layer 114 deposited 206 in the trenches 112. In some embodiments, the insulating layer 114 may be deposited 206 by a conformal deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), may be formed 206 by a thermal growth process (such as thermal growth of an oxide, nitride or oxynitride of the substrate material), or formed 206 by another suitable deposition process. The insulating layer 114 may comprise a dielectric material such as HfO.sub.2, AlO, ZrO, Si.sub.3N.sub.4, SiO.sub.2, SiON, or another insulating dielectric material. In some embodiments, the thickness of the insulating layer 114 is chosen to allow unpinning of the Fermi level of the subsequently-deposited conductor. The insulating layer 114 may be very thin to accomplish this in some embodiments, such as less than about 4 nanometers, less than about three nanometers, or about one nanometer or less in various embodiments. In an embodiment, the insulating layer 114 is between about 5 and 10 Angstroms. Other thicknesses of the insulating layer 114 may also be used. Note that while the insulating layer 114 is illustrated as being conformally deposited, this is not a requirement. In some embodiments, such as embodiments with a thermally-grown insulating layer 114, the insulating layer 114 may be formed non-conformally.
The conductive layer 116 may be a metal or contain a metal in some embodiments. Various metals may be used. In some embodiments, the material of the conductive layer 116 may be chosen based on an appropriate workfunction for the type of transistor (high workfunction metal for a PMOS transistor, low workfunction metal for an NMOS transistor, with "high" workfunction being above about 5 eV and "low" workfunction being about 3.2 eV or lower), although this is not necessary. Materials used for the conductive layer 116 include aluminum, nickel, magnesium, copper or other metals. Conductive metal carbides, nitrides or other materials may also be used for the conductive layer 116. Any suitable thickness may be used for the conductive layer 116. In some embodiments, the conductive layer 116 is greater than 100 Angstroms, with the conductive layer 116 being considerably thicker than 100 Angstroms in some embodiments.
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