Source: http://www.google.com/patents/US8158471?dq=5,987,610
Timestamp: 2016-09-01 04:02:10
Document Index: 228640300

Matched Legal Cases: ['Application No. 2008', 'Application No. 2006800203457', 'Application No. 06', 'Application No. 095117389', 'Application No. 095117389', 'Application No. 2008', 'Application No. 200718354']

Patent US8158471 - Capacitorless DRAM on bulk silicon - Google PatentsSearch Images Maps Play YouTube News Gmail Drive More »Sign inPatentsA method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between...http://www.google.com/patents/US8158471?utm_source=gb-gplus-sharePatent US8158471 - Capacitorless DRAM on bulk siliconAdvanced Patent SearchTry the new Google Patents, with machine-classified Google Scholar results, and Japanese and South Korean patents.Publication numberUS8158471 B2Publication typeGrantApplication numberUS 12/897,999Publication dateApr 17, 2012Priority dateJun 8, 2005Fee statusPaidAlso published asCN101253622A, CN101253622B, EP1897135A2, US7517744, US7538389, US7829399, US8466517, US8971086, US20060278926, US20060284210, US20090190394, US20110020988, US20120199908, US20130279277, WO2006135505A2, WO2006135505A3Publication number12897999, 897999, US 8158471 B2, US 8158471B2, US-B2-8158471, US8158471 B2, US8158471B2InventorsSuraj Mathew, Jigish D TrivediOriginal AssigneeMicron Technology, Inc.Export CitationBiBTeX, EndNote, RefManPatent Citations (56), Non-Patent Citations (19), Referenced by (4), Classifications (20), Legal Events (3) External Links: USPTO, USPTO Assignment, EspacenetCapacitorless DRAM on bulk silicon
US 8158471 B2Abstract
forming at least one localized silicon-over-insulator region in the memory array region such that a silicon pillar extends from a silicon substrate to the silicon-over-insulator through an insulator layer surrounding the silicon pillar and beneath the silicon-over-insulator, without forming a silicon-over-insulator region in at least part of the periphery region; and
forming at least one capacitorless DRAM cell on and within the at least one localized silicon-over-insulator region.
4. The method of claim 1, wherein forming at least one localized silicon-over-insulator region comprises forming a silicon layer over the insulator layer by lateral epitaxial overgrowth.
5. The method of claim 4, wherein forming at least one localized silicon-over-insulator region further comprises forming the silicon pillar protruding through the insulator layer prior to lateral epitaxial overgrowth.
6. The method of claim 5, wherein forming at least one localized silicon-over-insulator region comprises etching a recess with the pillar therein and depositing the insulator layer into the recess.
7. The method of claim 5, further comprising recessing the insulator layer such that the pillar protrudes above the insulator layer prior to lateral epitaxial overgrowth.
8. The method of claim 1, wherein forming at least one localized silicon-over-insulator region comprises:
filling a trench surrounding the silicon pillar with the insulator layer;
recessing the insulator layer to expose an upper portion of the silicon pillar;
forming epitaxial silicon over the recessed insulator layer around the silicon pillar; and
wherein forming at least one capacitorless DRAM cell on and within the at least one silicon-over-insulator regions comprises forming at least one capacitorless DRAM cell on and within the epitaxial silicon.
9. The method of claim 8, wherein forming epitaxial silicon comprises growing about 50 Å and 500 Å of silicon over the recessed insulator layer.
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No. 03CH3747, pp. 913-916.Referenced byCiting PatentFiling datePublication dateApplicantTitleUS8648414 *Jul 1, 2011Feb 11, 2014Micron Technology, Inc.Semiconductor structures including bodies of semiconductor material, devices including such structures and related methodsUS8987108Feb 10, 2014Mar 24, 2015Micron Technology, Inc.Methods of forming semiconductor structures including bodies of semiconductor materialUS9362418Jan 27, 2015Jun 7, 2016Micron Technology, Inc.Semiconductor structures including bodies of semiconductor material and methods of forming sameUS20130001682 *Jul 1, 2011Jan 3, 2013Micron Technology, Inc.Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods* Cited by examinerClassifications U.S. Classification438/176, 438/311, 438/164, 257/E21.646, 257/E21.562, 257/E21.32, 438/269International ClassificationH01L21/338Cooperative ClassificationH01L29/7841, H01L21/84, H01L27/1203, H01L27/108, H01L27/10882, H01L27/10802, G11C7/00European ClassificationH01L21/84, H01L27/12B, H01L27/108, H01L29/78L, H01L27/108BLegal EventsDateCodeEventDescriptionSep 30, 2015FPAYFee paymentYear of fee payment: 4May 12, 2016ASAssignmentOwner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENFree format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001Effective date: 20160426Jun 2, 2016ASAssignmentOwner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERALFree format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001Effective date: 20160426RotateOriginal ImageGoogle Home - Sitemap - USPTO Bulk Downloads - Privacy Policy - Terms of Service - About Google Patents - Send FeedbackData provided by IFI CLAIMS Patent Services