PATENT ABSTRACT
The present invention provides a GOA (Gate-Driver-on-Array) circuit, which includes multiple GOA units connected in cascade. An nth stage GOA unit of the GOA circuit includes a first (n−1)th stage signal input terminal ( 21 ), a second (n−1)th stage signal input terminal ( 22 ), a (n+1)th stage signal input terminal ( 23 ), a first clock signal input terminal ( 24 ), a first low level input terminal ( 25 ), a second low level input terminal ( 26 ), a first output terminal ( 27 ), and a second output terminal ( 28 ). The nth stage GOA unit further includes: a pull-up control unit ( 42 ), a pull-up unit ( 44 ), a first pull-down holding unit ( 46 ), a second pull-down holding unit ( 47 ), and a pull-down unit ( 48 ). The GOA circuit of the present invention overcomes the problems of poor performance of the conventional the GOA circuit caused by introduction of two low level signals into the GOA circuit and short operation service life and can enhance the quality of displayed images.

PATENT DESCRIPTION
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to the field of liquid crystal displaying, and in particular to a gate-driver-on-array (GOA) circuit. 
         [0003]    2. The Related Arts 
         [0004]    Liquid crystal displays (LCDs) have a variety of advantages, such as thin device body, low power consumption, and being free of radiation, and are thus widely used. The development of the liquid crystal display industry brings in increasingly severer performance requirements, such as performance related to high resolution, high brightness, wide view angle, and low power consumption, and associated techniques have been developed. Most of the liquid crystal displays that are currently available in the market are backlighting liquid crystal displays, which comprise a liquid crystal display panel and a backlight module. The operation principle of the liquid crystal display panel is that, with liquid crystal molecules interposed between two parallel glass substrates, application of a drive voltage is selectively carried out by means of a driver circuit to the two glass substrates to control the liquid crystal molecules to change direction in order to refract out light emitting from the backlight module for generating images. 
         [0005]    The recent development of the LCDs is toward high integration and low cost of which an important technique is the realization of mass production of gate driver on array (GOA) technique. The GOA technique uses the front-stage array process of TFT-LCD (Thin-Film Transistor Liquid Crystal Display) to make a gate line scan drive signal circuit on an array substrate of a liquid crystal display panel in order to achieve progressive gate scanning. Using the GOA technique to integrate the gate line scan drive signal circuit on the array substrate of the liquid crystal display panel allows for omission of a gate driver integrated circuit so as to reduce the cost of product in both material cost and manufacturing operation. Such a gate line scan drive signal circuit that is integrated on an array substrate by means of the GOA technique is also referred to as a GOA circuit. The GOA circuit comprises a plurality of GOA units and as show in  FIG. 1 , a circuit diagram of a GOA unit of a conventional GOA circuit is shown, comprising: a pull-up circuit  100 , a pull-up control circuit  200 , a pull-down circuit  300 , a first pull-down holding circuit  400 , and a second pull-down holding circuit  500 , wherein the pull-up circuit  100  functions to output a clock signal CKn as a gate signal G n . The pull-up control circuit  200  controls the activation time of the pull-up circuit  100  and is generally connected to a transfer signal ST n−1  transmitted from a previous stage GOA unit and the gate signal G n−1  thereof. The first pull-down holding circuit  400  pulls the gate line down to a low voltage at first time, namely shutting off the gate signal. The second pull-down holding circuit  500  functions to maintain the gate signal G n  and a control signal Q n  of the pull-up circuit  100  at a shut-off condition (namely a negative potential). The GOA circuit is commonly provided with two low level signal lines and the two low level signal lines respectively supply a first low level signal V ss1  and a second low level signal V ss2 , whereby the second low level V ss2  is used to reduce the voltage difference V gs  between the gate terminal and the source terminal of the pull-up circuit  100  when the scan circuit is at a closed (holding) time so as to reduce the leakage currents of the pull-up circuit  100  and the second pull-down holding circuit  500 . A capacitor C boost  provides secondary boost of the control signal Q n  of the pull-up circuit  100  to facilitate the output of the gate signal G n . 
         [0006]    However, the conventional GOA circuit suffers the following two shortcomings: 
         [0007]    (1) A conductive path exists between two different negative potentials. Referring to  FIG. 2 , which is an equivalent circuit diagram of  FIG. 1 , L 100  indicates a loop of the leakage current induced by the connection of a thin-film transistor T 110  to the previous stage GOA unit and L 200  indicates a loop of the leakage current induced by the connection of a thin-film transistor T 410  to the instant stage GOA unit. The conventional GOA circuit would cause an effect of a great current between the leakage current loops L 100  and L 200 . The magnitude of the current is directly related to the potentials of pull-down points P n  and K n . Further, the current conducted therethrough is proportional to the number of the stages of the GOA circuit. This leads to an increase of the loading of the signal sources of V ss1  and V ss2  and in the worst case, abnormality of image displaying may result. 
         [0008]    (2) The diode design of thin-film transistors T 510  and T 610  makes it is not possible for the high voltage of the pull-down points P n  and K n  to be quickly released and the voltage variations at the points of P n  and K n  are illustrated in  FIG. 3 . This increases the influence of stress on four primary thin-film transistors T 320 , T 420 , T 330 , T 430  of the first and second pull-down holding circuits  400 ,  500 , eventually affecting the operation service life of the GOA circuit. 
       SUMMARY OF THE INVENTION 
       [0009]    An object of the present invention is to provide a GOA (Gate-Driver-on-Array) circuit, which uses a GOA technique to reduce the cost of a liquid crystal display and to overcome the problems of poor performance of the conventional the GOA circuit caused by introduction of two low level signals into the GOA circuit and short operation service life of the GOA circuit and enhance the quality of displayed images. 
         [0010]    To achieve the above object, the present invention provides a GOA circuit, which comprises multiple stages of GOA units connected in cascade, wherein: 
         [0011]    for each nth stage GOA unit between the second stage and the last second stage of the GOA circuit, the nth stage GOA unit comprises a first (n−1)th stage signal input terminal, a second (n−1)th stage signal input terminal, a (n+1)th stage signal input terminal, a first output terminal, and a second output terminal, wherein the first output terminal of the nth stage GOA unit is provided for driving an active zone of an array substrate; the first (n−1)th stage signal input terminal, the second (n−1)th stage signal input terminal, and the (n+1)th stage signal input terminal of the nth stage GOA unit are respectively and electrically connected to the first output terminal and the second output terminal of the (n−1)th GOA unit and the first output terminal of the (n+1)th GOA unit, the first output terminal of the nth stage GOA unit being electrically connected to the first (n−1)th stage signal input terminal of the (n+1)th GOA unit and the (n+1)th stage signal input terminal of the (n−1)th GOA unit, the second output terminal of the nth stage GOA unit being electrically connected to the second (n−1)th stage signal input terminal of the (n+1)th GOA unit; 
         [0012]    for the nth stage GOA unit at the first stage of the GOA circuit, the nth stage GOA unit comprises a first (n−1)th stage signal input terminal, a second (n−1)th stage signal input terminal, a (n+1)th stage signal input terminal, a first output terminal, and a second output terminal, wherein the first output terminal of the nth stage GOA unit is provided for driving an active zone of an array substrate; the first (n−1)th stage signal input terminal and the second (n−1)th stage signal input terminal of the nth stage GOA unit both provided for receiving an input of a pulse activation signal and the (n+1)th stage signal input terminal is electrically connected to the first output terminal of the (n+1)th GOA unit, the first output terminal and the second output terminal of the nth stage GOA unit being respectively and electrically connected to the first (n−1)th stage signal input terminal and the second (n−1)th stage signal input terminal of the (n+1)th GOA unit; 
         [0013]    for the nth stage GOA unit at the last stage of the GOA circuit, the nth stage GOA unit comprises a first (n−1)th stage signal input terminal, a second (n−1)th stage signal input terminal, a (n+1)th stage signal input terminal, a first output terminal, and a second output terminal; the first (n−1)th stage signal input terminal and the second input terminal of the nth stage GOA unit are respectively and electrically connected to the first output terminal and the second output terminal of the (n−1)th GOA unit, the (n+1)th stage signal input terminal of the nth stage GOA unit being provided to receive an input of a pulse activation signal, the first output terminal of the nth stage GOA unit being electrically connected to the (n+1)th stage signal input terminal of the (n−1)th GOA unit and the second output terminal being open; 
         [0014]    for each nth stage GOA unit between the first stage and the last stage of the GOA circuit, the nth stage GOA unit further comprises a first clock signal input terminal, a first low level input terminal, and a second low level input terminal, the first low level input terminal being provided for receiving an input of a first low level, the second low level input terminal being provided for receiving an input of a second low level, the second low level being smaller than the first low level; 
         [0015]    for each nth stage GOA unit between the first stage and the last stage of the GOA circuit, the nth stage GOA unit further comprises: 
         [0016]    a pull-up control unit, which is electrically connected to the first (n−1)th stage signal input terminal and the second (n−1)th stage signal input terminal; 
         [0017]    a pull-up unit, which is electrically connected to the pull-up control unit and the first clock signal input terminal, the first output terminal, and the second output terminal; 
         [0018]    a first pull-down holding unit, which is electrically connected to the first low level input terminal, the second low level input terminal, the pull-up control unit, and the pull-up unit; 
         [0019]    a second pull-down holding unit, which is electrically connected to the first low level input terminal, the second low level input terminal, the first pull-down holding unit, the pull-up control unit, and the pull-up unit; and 
         [0020]    a pull-down unit, which is electrically connected to the (n+1)th stage signal input terminal, the first low level input terminal, the pull-up control unit, the pull-up unit, the first pull-down holding unit, the second pull-down holding unit, and the first output terminal. 
         [0021]    The first clock signal input terminal has an input signal that is a first clock signal or a second clock signal, the first clock signal being opposite in phase to the second clock signal; when the input signal of the first clock signal input terminal of the nth stage GOA unit of the GOA circuit is the first clock signal, the input signal of the first clock signal input terminal of the (n+1)th stage GOA unit of the GOA circuit is the second clock signal. 
         [0022]    The pull-up control unit is a first thin-film transistor and the first thin-film transistor comprises a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is electrically connected to the second (n−1)th stage signal input terminal; the first source terminal is electrically connected to the first (n−1)th stage signal input terminal; and the first drain terminal is electrically connected to the first and second pull-down holding units, the pull-down unit, and the pull-up unit. 
         [0023]    The pull-up unit comprises a capacitor, a second thin-film transistor, and a third thin-film transistor and the second thin-film transistor comprises a second gate terminal, a second source terminal, and a second drain terminal and the third thin-film transistor comprises a third gate terminal, a third source terminal, and a third drain terminal, wherein the second gate terminal is electrically connected to one end of the capacitor, the first drain terminal, the third gate terminal, the first and second pull-down holding units, and the pull-down unit; the second source terminal is electrically connected to the third source terminal and the first clock signal input terminal; the second drain terminal is electrically connected to the second output terminal; and the third drain terminal is electrically connected to the first output terminal, the first and second pull-down holding units, the pull-down unit, and an opposite end of the capacitor. 
         [0024]    The pull-down unit comprises fourth and fifth thin-film transistors and the fourth thin-film transistor comprises a fourth gate terminal, a fourth source terminal, and a fourth drain terminal and the fifth thin-film transistor comprises a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fourth gate terminal is electrically connected to the fifth gate terminal and the (n+1)th stage signal input terminal; the fourth source terminal is electrically connected to a first low level input terminal and the fifth source terminal; the fourth drain terminal is electrically connected to the first drain terminal, said one end of the capacitor, the second gate terminal, the third gate terminal, and the first and second pull-down holding units; and the fifth drain terminal is electrically connected to the first output terminal, the third source terminal, said opposite end of the capacitor, and the first and second pull-down holding units. 
         [0025]    The first pull-down holding unit comprises sixth to ninth thin-film transistors and the sixth thin-film transistor comprises a sixth gate terminal, a sixth source terminal, and a sixth drain terminal; the seventh thin-film transistor comprises a seventh gate terminal, a seventh source terminal, and a seventh drain terminal; the eighth thin-film transistor comprises an eighth gate terminal, an eighth source terminal, and an eighth drain terminal; and the ninth thin-film transistor comprises a ninth gate terminal, a ninth source terminal, and a ninth drain terminal, wherein the sixth drain terminal is electrically connected to the seventh drain terminal, the eighth gate terminal, and the ninth gate terminal; the seventh gate terminal is electrically connected to the first drain terminal, the ninth drain terminal, said one end of the capacitor, the second gate terminal, the third gate terminal, the fourth drain terminal, and the second pull-down holding unit; the seventh source terminal is electrically connected to a second low level input terminal; the eighth drain terminal is electrically connected to said opposite end of the capacitor, the second pull-down holding unit, and the first output terminal; the eighth source terminal is electrically connected to the first low level input terminal; and the ninth source terminal is electrically connected to the first low level input terminal; and 
         [0026]    the second pull-down holding unit comprises tenth to thirteenth thin-film transistors and the tenth thin-film transistor comprises a tenth gate terminal, a tenth source terminal, and a tenth drain terminal; the eleventh thin-film transistor comprises an eleventh gate terminal, an eleventh source terminal, and an eleventh drain terminal; the twelfth thin-film transistor comprises a twelfth gate terminal, a twelfth source terminal, and a twelfth drain terminal; and the thirteenth thin-film transistor comprises a thirteenth gate terminal, a thirteenth source terminal, and a thirteenth drain terminal, wherein the tenth drain terminal is electrically connected to the eleventh drain terminal, the twelfth gate terminal, and the thirteenth gate terminal; the eleventh gate terminal is electrically connected to the first drain terminal, the thirteenth drain terminal, the seventh gate terminal, the ninth drain terminal, and said one end of the capacitor; the eleventh source terminal is electrically connected to the second low level input terminal; the twelfth drain terminal is electrically connected to said opposite end of the capacitor, the eighth drain terminal, and the first output terminal; the twelfth source terminal is electrically connected to the first low level input terminal; and the thirteenth source terminal is electrically connected to the first low level input terminal. 
         [0027]    The nth stage GOA unit of the GOA circuit further comprises a second clock signal input terminal and a third clock signal input terminal, the sixth gate terminal and the sixth source terminal being connected to the second clock signal input terminal, the tenth gate terminal and the tenth source terminal being connected to the third clock signal input terminal, the second clock signal input terminal receiving an input of the first clock signal, the third clock signal input terminal receiving an input of the second clock signal. 
         [0028]    The first pull-down holding unit further comprises a fourteenth thin-film transistor and the fourteenth thin-film transistor comprises a fourteenth gate terminal, a fourteenth source terminal, and a fourteenth drain terminal, wherein the fourteenth drain terminal is electrically connected to the sixth drain terminal, the seventh drain terminal, the eighth gate terminal, and the ninth gate terminal; and the fourteenth source terminal is electrically connected to the sixth gate terminal, the sixth source terminal, and the second clock signal input terminal; and the second pull-down holding unit further comprises a fifteenth thin-film transistor and the fifteenth thin-film transistor comprises a fifteenth gate terminal, a fifteenth source terminal, and a fifteenth drain terminal, wherein the fifteenth drain terminal is electrically connected to the tenth drain terminal, the eleventh drain terminal, the twelfth gate terminal, and the thirteenth gate terminal and the fifteenth source terminal is electrically connected to the tenth gate terminal and the tenth source terminal. 
         [0029]    The nth stage GOA unit of the GOA circuit further comprises a second clock signal input terminal and a third clock signal input terminal; the sixth gate terminal, the sixth source terminal, and the fourteenth source terminal are connected to the second clock signal input terminal; the fourteenth gate terminal is connected to the third clock signal input terminal; the tenth gate terminal, the tenth source terminal, and the fifteenth source terminal are connected to the third clock signal input terminal; the fifteenth gate terminal is connected to the second clock signal input terminal; and the second clock signal input terminal receives an input of the first clock signal and the third clock signal input terminal receives an input of the second clock signal. 
         [0030]    The nth stage GOA unit of the GOA circuit further comprises a first low frequency signal input terminal and a second low frequency input terminal, the sixth gate terminal; the sixth source terminal and the fourteenth source terminal are connected to the first low frequency signal input terminal; the fourteenth gate terminal is connected to the second low frequency signal input terminal; the tenth gate terminal, the tenth source terminal, and the fifteenth source terminal are connected to the second low frequency signal input terminal; the fifteenth gate terminal is connected to the first low frequency signal input terminal; and the first low frequency signal input terminal receives an input of a low frequency signal or an ultralow frequency signal and the second low frequency signal input terminal receives an input of a low frequency signal or an ultralow frequency signal. 
         [0031]    The present invention further provides a GOA circuit, comprising multiple stages of GOA units connected in cascade, wherein: 
         [0032]    for each nth stage GOA unit between the second stage and the last second stage of the GOA circuit, the nth stage GOA unit comprises a first (n−1)th stage signal input terminal, a second (n−1)th stage signal input terminal, a (n+1)th stage signal input terminal, a first output terminal, and a second output terminal, wherein the first output terminal of the nth stage GOA unit is provided for driving an active zone of an array substrate; the first (n−1)th stage signal input terminal, the second (n−1)th stage signal input terminal, and the (n+1)th stage signal input terminal of the nth stage GOA unit are respectively and electrically connected to the first output terminal and the second output terminal of the (n−1)th GOA unit and the first output terminal of the (n+1)th GOA unit, the first output terminal of the nth stage GOA unit being electrically connected to the first (n−1)th stage signal input terminal of the (n+1)th GOA unit and the (n+1)th stage signal input terminal of the (n−1)th GOA unit, the second output terminal of the nth stage GOA unit being electrically connected to the second (n−1)th stage signal input terminal of the (n+1)th GOA unit; 
         [0033]    for the nth stage GOA unit at the first stage of the GOA circuit, the nth stage GOA unit comprises a first (n−1)th stage signal input terminal, a second (n−1)th stage signal input terminal, a (n+1)th stage signal input terminal, a first output terminal, and a second output terminal, wherein the first output terminal of the nth stage GOA unit is provided for driving an active zone of an array substrate; the first (n−1)th stage signal input terminal and the second (n−1)th stage signal input terminal of the nth stage GOA unit both provided for receiving an input of a pulse activation signal and the (n+1)th stage signal input terminal is electrically connected to the first output terminal of the (n+1)th GOA unit, the first output terminal and the second output terminal of the nth stage GOA unit being respectively and electrically connected to the first (n−1)th stage signal input terminal and the second (n−1)th stage signal input terminal of the (n+1)th GOA unit; 
         [0034]    for the nth stage GOA unit at the last stage of the GOA circuit, the nth stage GOA unit comprises a first (n−1)th stage signal input terminal, a second (n−1)th stage signal input terminal, a (n+1)th stage signal input terminal, a first output terminal, and a second output terminal; the first (n−1)th stage signal input terminal and the second input terminal of the nth stage GOA unit are respectively and electrically connected to the first output terminal and the second output terminal of the (n−1)th GOA unit, the (n+1)th stage signal input terminal of the nth stage GOA unit being provided to receive an input of a pulse activation signal, the first output terminal of the nth stage GOA unit being electrically connected to the (n+1)th stage signal input terminal of the (n−1)th GOA unit and the second output terminal being open; 
         [0035]    for each nth stage GOA unit between the first stage and the last stage of the GOA circuit, the nth stage GOA unit further comprises a first clock signal input terminal, a first low level input terminal, and a second low level input terminal, the first low level input terminal being provided for receiving an input of a first low level, the second low level input terminal being provided for receiving an input of a second low level, the second low level being smaller than the first low level; 
         [0036]    for each nth stage GOA unit between the first stage and the last stage of the GOA circuit, the nth stage GOA unit further comprises: 
         [0037]    a pull-up control unit, which is electrically connected to the first (n−1)th stage signal input terminal and the second (n−1)th stage signal input terminal; 
         [0038]    a pull-up unit, which is electrically connected to the pull-up control unit and the first clock signal input terminal, the first output terminal, and the second output terminal; 
         [0039]    a first pull-down holding unit, which is electrically connected to the first low level input terminal, the second low level input terminal, the pull-up control unit, and the pull-up unit; 
         [0040]    a second pull-down holding unit, which is electrically connected to the first low level input terminal, the second low level input terminal, the first pull-down holding unit, the pull-up control unit, and the pull-up unit; and 
         [0041]    a pull-down unit, which is electrically connected to the (n+1)th stage signal input terminal, the first low level input terminal, the pull-up control unit, the pull-up unit, the first pull-down holding unit, the second pull-down holding unit, and the first output terminal; 
         [0042]    wherein the first clock signal input terminal has an input signal that is a first clock signal or a second clock signal, the first clock signal being opposite in phase to the second clock signal; when the input signal of the first clock signal input terminal of the nth stage GOA unit of the GOA circuit is the first clock signal, the input signal of the first clock signal input terminal of the (n+1)th stage GOA unit of the GOA circuit is the second clock signal; 
         [0043]    wherein the pull-up control unit is a first thin-film transistor and the first thin-film transistor comprises a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is electrically connected to the second (n−1)th stage signal input terminal; the first source terminal is electrically connected to the first (n−1)th stage signal input terminal; and the first drain terminal is electrically connected to the first and second pull-down holding units, the pull-down unit, and the pull-up unit; 
         [0044]    wherein the pull-up unit comprises a capacitor, a second thin-film transistor, and a third thin-film transistor and the second thin-film transistor comprises a second gate terminal, a second source terminal, and a second drain terminal and the third thin-film transistor comprises a third gate terminal, a third source terminal, and a third drain terminal, wherein the second gate terminal is electrically connected to one end of the capacitor, the first drain terminal, the third gate terminal, the first and second pull-down holding units, and the pull-down unit; the second source terminal is electrically connected to the third source terminal and the first clock signal input terminal; the second drain terminal is electrically connected to the second output terminal; and the third drain terminal is electrically connected to the first output terminal, the first and second pull-down holding units, the pull-down unit, and an opposite end of the capacitor; 
         [0045]    wherein the pull-down unit comprises fourth and fifth thin-film transistors and the fourth thin-film transistor comprises a fourth gate terminal, a fourth source terminal, and a fourth drain terminal and the fifth thin-film transistor comprises a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fourth gate terminal is electrically connected to the fifth gate terminal and the (n+1)th stage signal input terminal; the fourth source terminal is electrically connected to a first low level input terminal and the fifth source terminal; the fourth drain terminal is electrically connected to the first drain terminal, said one end of the capacitor, the second gate terminal, the third gate terminal, and the first and second pull-down holding units; and the fifth drain terminal is electrically connected to the first output terminal, the third source terminal, said opposite end of the capacitor, and the first and second pull-down holding units; and 
         [0046]    wherein the first pull-down holding unit comprises sixth to ninth thin-film transistors and the sixth thin-film transistor comprises a sixth gate terminal, a sixth source terminal, and a sixth drain terminal; the seventh thin-film transistor comprises a seventh gate terminal, a seventh source terminal, and a seventh drain terminal; the eighth thin-film transistor comprises an eighth gate terminal, an eighth source terminal, and an eighth drain terminal; and the ninth thin-film transistor comprises a ninth gate terminal, a ninth source terminal, and a ninth drain terminal, wherein the sixth drain terminal is electrically connected to the seventh drain terminal, the eighth gate terminal, and the ninth gate terminal; the seventh gate terminal is electrically connected to the first drain terminal, the ninth drain terminal, said one end of the capacitor, the second gate terminal, the third gate terminal, the fourth drain terminal, and the second pull-down holding unit; the seventh source terminal is electrically connected to a second low level input terminal; the eighth drain terminal is electrically connected to said opposite end of the capacitor, the second pull-down holding unit, and the first output terminal; the eighth source terminal is electrically connected to the first low level input terminal; and the ninth source terminal is electrically connected to the first low level input terminal; and 
         [0047]    the second pull-down holding unit comprises tenth to thirteenth thin-film transistors and the tenth thin-film transistor comprises a tenth gate terminal, a tenth source terminal, and a tenth drain terminal; the eleventh thin-film transistor comprises an eleventh gate terminal, an eleventh source terminal, and an eleventh drain terminal; the twelfth thin-film transistor comprises a twelfth gate terminal, a twelfth source terminal, and a twelfth drain terminal; and the thirteenth thin-film transistor comprises a thirteenth gate terminal, a thirteenth source terminal, and a thirteenth drain terminal, wherein the tenth drain terminal is electrically connected to the eleventh drain terminal, the twelfth gate terminal, and the thirteenth gate terminal; the eleventh gate terminal is electrically connected to the first drain terminal, the thirteenth drain terminal, the seventh gate terminal, the ninth drain terminal, and said one end of the capacitor; the eleventh source terminal is electrically connected to the second low level input terminal; the twelfth drain terminal is electrically connected to said opposite end of the capacitor, the eighth drain terminal, and the first output terminal; the twelfth source terminal is electrically connected to the first low level input terminal; and the thirteenth source terminal is electrically connected to the first low level input terminal. 
         [0048]    The nth stage GOA unit of the GOA circuit further comprises a second clock signal input terminal and a third clock signal input terminal, the sixth gate terminal and the sixth source terminal being connected to the second clock signal input terminal, the tenth gate terminal and the tenth source terminal being connected to the third clock signal input terminal, the second clock signal input terminal receiving an input of the first clock signal, the third clock signal input terminal receiving an input of the second clock signal. 
         [0049]    The first pull-down holding unit further comprises a fourteenth thin-film transistor and the fourteenth thin-film transistor comprises a fourteenth gate terminal, a fourteenth source terminal, and a fourteenth drain terminal, wherein the fourteenth drain terminal is electrically connected to the sixth drain terminal, the seventh drain terminal, the eighth gate terminal, and the ninth gate terminal; and the fourteenth source terminal is electrically connected to the sixth gate terminal, the sixth source terminal, and the second clock signal input terminal; and the second pull-down holding unit further comprises a fifteenth thin-film transistor and the fifteenth thin-film transistor comprises a fifteenth gate terminal, a fifteenth source terminal, and a fifteenth drain terminal, wherein the fifteenth drain terminal is electrically connected to the tenth drain terminal, the eleventh drain terminal, the twelfth gate terminal, and the thirteenth gate terminal and the fifteenth source terminal is electrically connected to the tenth gate terminal and the tenth source terminal. 
         [0050]    The nth stage GOA unit of the GOA circuit further comprises a second clock signal input terminal and a third clock signal input terminal; the sixth gate terminal, the sixth source terminal, and the fourteenth source terminal are connected to the second clock signal input terminal; the fourteenth gate terminal is connected to the third clock signal input terminal; the tenth gate terminal, the tenth source terminal, and the fifteenth source terminal are connected to the third clock signal input terminal; the fifteenth gate terminal is connected to the second clock signal input terminal; and the second clock signal input terminal receives an input of the first clock signal and the third clock signal input terminal receives an input of the second clock signal. 
         [0051]    The nth stage GOA unit of the GOA circuit further comprises a first low frequency signal input terminal and a second low frequency input terminal, the sixth gate terminal; the sixth source terminal and the fourteenth source terminal are connected to the first low frequency signal input terminal; the fourteenth gate terminal is connected to the second low frequency signal input terminal; the tenth gate terminal, the tenth source terminal, and the fifteenth source terminal are connected to the second low frequency signal input terminal; the fifteenth gate terminal is connected to the first low frequency signal input terminal; and the first low frequency signal input terminal receives an input of a low frequency signal or an ultralow frequency signal and the second low frequency signal input terminal receives an input of a low frequency signal or an ultralow frequency signal. 
         [0052]    The efficacy of the present invention is that the present invention provides a GOA circuit, which uses two low level signals to reduce the leakage currents of the thin-film transistors of a pull-down holding unit, wherein the second low level that has a lower level provides a low voltage to pull-down points P n  and K n  and the first low level that has a higher level provides a low voltage to the pull-down points Q n  and G n , so as to reduce the potentials of the pull-down point P n  and K n  when the pull-down point Q n  and G n  are activated to thereby facilitate charging of Q n  and G n  and also to break the leakage current loop of the circuit between two low level signals to greatly reduce the leakage current between the two low level signal, enhance the performance of the GOA circuit, and improve the quality of displayed images; further, the fourteenth thin-film transistor and the fifteenth thin-film transistor are additionally included in respect of the diode design of the sixth thin-film transistor and the tenth thin-film transistor to perform discharging to the pull-down points P n  and K n , thereby achieving the potentials of P n  and K n  changing up and down with the variation of the first clock signal CK 1  and the second clock signal CK 2 , providing alternating operations so as to reduce the influence of the eighth and ninth thin-film transistor and the twelfth and thirteenth thin-film transistor by stresses, extending the lifespan of the GOA circuit. Further, using low frequency or ultralow frequency signals to control the pull-down holding unit effectively reduces power consumption of the circuit. 
         [0053]    For better understanding of the features and technical contents of the present invention, reference will be made to the following detailed description of the present invention and the attached drawings. However, the drawings are provided for the purposes of reference and illustration and are not intended to impose limitations to the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0054]    The technical solution, as well as other beneficial advantages, of the present invention will be apparent from the following detailed description of embodiments of the present invention, with reference to the attached drawing. In the drawing: 
           [0055]      FIG. 1  is a circuit diagram of a conventional GOA (Gate Driver on Array) circuit; 
           [0056]      FIG. 2  is an equivalent circuit of  FIG. 1 ; 
           [0057]      FIG. 3  is a drive timing diagram of the GOA circuit shown in  FIG. 1 ; 
           [0058]      FIG. 4  is a circuit diagram of a GOA circuit according to a preferred embodiment of the present invention; 
           [0059]      FIG. 5  is a drive timing diagram of the GOA circuit shown in  FIG. 4 ; 
           [0060]      FIG. 6  is plot of a characteristic I-V curve of a thin-film transistor; 
           [0061]      FIG. 7  is a circuit diagram of a GOA circuit according to another preferred embodiment of the present invention; 
           [0062]      FIG. 8  is a drive timing diagram of the GOA circuit shown in  FIG. 7   
           [0063]      FIG. 9  is a circuit diagram of a GOA circuit according to a further preferred embodiment of the present invention; and 
           [0064]      FIG. 10  is a drive timing diagram of the GOA circuit shown in  FIG. 9 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0065]    To further expound the technical solution adopted in the present invention and the advantages thereof, a detailed description is given to a preferred embodiment of the present invention and the attached drawings. 
         [0066]    Referring to  FIGS. 4-6 , the present invention provides a GOA (Gate-Driver-on-Array) circuit, which comprises multiple stages of GOA units connected in cascade, wherein: 
         [0067]    for each nth stage GOA unit between the second stage and the last second stage of the GOA circuit, the nth stage GOA unit comprises a first (n−1)th stage signal input terminal  21  (G n−1 ), a second (n−1)th stage signal input terminal  22  (ST n−1 ), a (n+1)th stage signal input terminal  23  (G n+1 ), a first output terminal  27  (G n ), and a second output terminal  28  (ST n ), wherein the first output terminal  27  (G n ) of the nth stage GOA unit is provided for driving an active zone of an array substrate; the first (n−1)th stage signal input terminal  21  (G n−1 ), the second (n−1)th stage signal input terminal  22  (ST n−1 ), and the (n+1)th stage signal input terminal  23  (G n+1 ) of the nth stage GOA unit are respectively and electrically connected to the first output terminal  27  (G n ) and the second output terminal  28  (ST n ) of the (n−1)th GOA unit and the first output terminal  27  (G n ) of the (n+1)th GOA unit, the first output terminal  27  (G n ) of the nth stage GOA unit being electrically connected to the first (n−1)th stage signal input terminal  21  (G n−1 ) of the (n+1)th GOA unit and the (n+1)th stage signal input terminal  23  (G n+1 ) of the (n−1)th GOA unit, the second output terminal  28  (ST n ) of the nth stage GOA unit being electrically connected to the second (n−1)th stage signal input terminal  22  (ST n−1 ) of the (n+1)th GOA unit; 
         [0068]    for the nth stage GOA unit at the first stage of the GOA circuit, the nth stage GOA unit comprises a first (n−1)th stage signal input terminal  21  (G n−1 ), a second (n−1)th stage signal input terminal  22  (ST n−1 ), a (n+1)th stage signal input terminal  23  (G n+1 ), a first output terminal  27  (G n ), and a second output terminal  28  (ST n ), wherein the first output terminal  27  (G n ) of the nth stage GOA unit is provided for driving an active zone of an array substrate; the first (n−1)th stage signal input terminal  21  (G n−1 ) and the second (n−1)th stage signal input terminal  22  (ST n−1 ) of the nth stage GOA unit both provided for receiving an input of a pulse activation signal and the (n+1)th stage signal input terminal  23  (G n+1 ) is electrically connected to the first output terminal  27  (G n ) of the (n+1)th GOA unit, the first output terminal  27  (G n ) and the second output terminal  28  (ST n ) of the nth stage GOA unit being respectively and electrically connected to the first (n−1)th stage signal input terminal  21  (G n−1 ) and the second (n−1)th stage signal input terminal  22  (ST n−1 ) of the (n+1)th GOA unit; 
         [0069]    for the nth stage GOA unit at the last stage of the GOA circuit, the nth stage GOA unit comprises a first (n−1)th stage signal input terminal  21  (G n−1 ), a second (n−1)th stage signal input terminal  22  (ST n−1 ), a (n+1)th stage signal input terminal  23  (G n+1 ), a first output terminal  27  (G n ), and a second output terminal  28  (ST n ); the first (n−1)th stage signal input terminal  21  (G n−1 ) and the second input terminal  22  (ST n−1 ) of the nth stage GOA unit are respectively and electrically connected to the first output terminal  27  (G n ) and the second output terminal  28  (ST n ) of the (n−1)th GOA unit, the (n+1)th stage signal input terminal  23  (G n+1 ) of the nth stage GOA unit being provided to receive an input of a pulse activation signal, the first output terminal  27  (G n ) of the nth stage GOA unit being electrically connected to the (n+1)th stage signal input terminal  23  (G n+1 ) of the (n−1)th GOA unit and the second output terminal  28  (ST n ) being open; 
         [0070]    for each nth stage GOA unit between the first stage and the last stage of the GOA circuit, the nth stage GOA unit further comprises a first clock signal input terminal  24 , a first low level input terminal  25 , and a second low level input terminal  26 , the first low level input terminal  25  being provided for receiving an input of a first low level V ss1 , the second low level input terminal  26  being provided for receiving an input of a second low level V ss2 , the second low level V ss2  being smaller than the first low level V ss1 ; 
         [0071]    for each nth stage GOA unit between the first stage and the last stage of the GOA circuit, the nth stage GOA unit further comprises: 
         [0072]    a pull-up control unit  42 , which is electrically connected to the first (n−1)th stage signal input terminal  21  and the second (n−1)th stage signal input terminal  22 ; 
         [0073]    a pull-up unit  44 , which is electrically connected to the pull-up control unit  42  and the first clock signal input terminal  24 , the first output terminal  27 , and the second output terminal  28 ; 
         [0074]    a first pull-down holding unit  46 , which is electrically connected to the first low level input terminal  25 , the second low level input terminal  26 , the pull-up control unit  42 , and the pull-up unit  44 ; 
         [0075]    a second pull-down holding unit  47 , which is electrically connected to the first low level input terminal  25 , the second low level input terminal  26 , the first pull-down holding unit  46 , the pull-up control unit  42 , and the pull-up unit  44 ; and 
         [0076]    a pull-down unit  48 , which is electrically connected to the (n+1)th stage signal input terminal  23 , the first low level input terminal  25 , the pull-up control unit  42 , the pull-up unit  44 , the first pull-down holding unit  46 , the second pull-down holding unit  47 , and the first output terminal  27 . 
         [0077]    In the instant embodiment, the nth stage GOA unit of the GOA circuit further comprises a second clock signal input terminal  31  and a third clock signal input terminal  32 . The first clock signal input terminal  24  has an input signal that is a first clock signal CK 1  or a second clock signal CK 2 , the second clock signal input terminal  31  having an input signal that is the first clock signal CK 1 , the third clock signal input terminal  32  having an input signal that is the second clock signal CK 2 , the first clock signal CK 1  being opposite in phase to the second clock signal CK 2 , meaning high and low voltages of the signals CK 1  and CK 2  being opposite to each other at a given time point; when the input signal of the first clock signal input terminal  24  of the nth stage GOA unit of the GOA circuit is the first clock signal CK 1 , the input signal of the first clock signal input terminal  24  of the (n+1)th stage GOA unit of the GOA circuit is the second clock signal CK 2 . 
         [0078]    The pull-up control unit  42  is a first thin-film transistor T 1  and the first thin-film transistor T 1  comprises a first gate terminal g 1 , a first source terminal s 1 , and a first drain terminal d 1 , wherein the first gate terminal g 1  is electrically connected to the second (n−1)th stage signal input terminal  22 ; the first source terminal s 1  is electrically connected to the first (n−1)th stage signal input terminal  21 ; and the first drain terminal d 1  is electrically connected to the first and second pull-down holding units  46 ,  47 , the pull-down unit  48 , and the pull-up unit  44 . 
         [0079]    The pull-up unit  44  comprises a capacitor C b , a second thin-film transistor T 2 , and a third thin-film transistor T 3  and the second thin-film transistor T 2  comprises a second gate terminal g 2 , a second source terminal s 2 , and a second drain terminal d 2  and the third thin-film transistor T 3  comprises a third gate terminal g 3 , a third source terminal s 3 , and a third drain terminal d 3 , wherein the second gate terminal g 2  is electrically connected to one end of the capacitor C b , the first drain terminal d 1 , the third gate terminal g 3 , the first and second pull-down holding units  46 ,  47 , and the pull-down unit  48 ; the second source terminal s 2  is electrically connected to the third source terminal s 3  and the first clock signal input terminal  24 ; the second drain terminal d 2  is electrically connected to the second output terminal  28 ; and the third drain terminal d 3  is electrically connected to the first output terminal  27 , the first and second pull-down holding units  46 ,  47 , the pull-down unit  48 , and an opposite end of the capacitor C b . 
         [0080]    The pull-down unit  48  comprises fourth and fifth thin-film transistors T 4 , T 5  and the fourth thin-film transistor T 4  comprises a fourth gate terminal g 4 , a fourth source terminal s 4 , and a fourth drain terminal d 4  and the fifth thin-film transistor T 5  comprises a fifth gate terminal g 5 , a fifth source terminal s 5 , and a fifth drain terminal d 5 , wherein the fourth gate terminal g 4  is electrically connected to the fifth gate terminal g 5  and the (n+1)th stage signal input terminal  23 ; the fourth source terminal s 4  is electrically connected to a first low level input terminal and the fifth source terminal s 5 ; the fourth drain terminal d 4  is electrically connected to the first drain terminal d 1 , said one end of the capacitor C b , the second gate terminal g 2 , the third gate terminal g 3 , and the first and second pull-down holding units  46 ,  47 ; and the fifth drain terminal d 5  is electrically connected to the first output terminal  27 , the third source terminal s 3 , said opposite end of the capacitor C b , and the first and second pull-down holding units  46 ,  47 . 
         [0081]    The first pull-down holding unit  46  comprises sixth to ninth thin-film transistors T 6 , T 7 , T 8 , T 9  and the sixth thin-film transistor T 6  comprises a sixth gate terminal g 6 , a sixth source terminal s 6 , and a sixth drain terminal d 6 ; the seventh thin-film transistor T 7  comprises a seventh gate terminal g 7 , a seventh source terminal s 7 , and a seventh drain terminal d 7 ; the eighth thin-film transistor comprises an eighth gate terminal g 8 , an eighth source terminal s 8 , and an eighth drain terminal d 8 ; and the ninth thin-film transistor comprises a ninth gate terminal g 9 , a ninth source terminal s 9 , and a ninth drain terminal d 9 , wherein the sixth gate terminal g 6  and the sixth source terminal s 6  are connected to the second clock signal input terminal  31 ; the sixth drain terminal d 6  is electrically connected to a pull-down point P n , the seventh drain terminal d 7 , the eighth gate terminal g 8 , and the ninth gate terminal g 9 ; the seventh gate terminal g 7  is electrically connected to the first drain terminal d 1 , the ninth drain terminal d 9 , said one end of the capacitor C b , the second gate terminal g 2 , the third gate terminal g 3 , the fourth drain terminal d 4 , and the second pull-down holding unit  47 ; the seventh source terminal s 7  is electrically connected to a second low level input terminal  26 ; the eighth drain terminal d 8  is electrically connected to said opposite end of the capacitor C b , the second pull-down holding unit  47 , and the first output terminal  27  (G n ); the eighth source terminal s 8  is electrically connected to the first low level input terminal  25 ; and the ninth source terminal s 9  is electrically connected to the first low level input terminal  25 . 
         [0082]    The eighth thin-film transistor T 8  is provided generally for maintaining a low voltage of the first output terminal  27  (G n ); the ninth thin-film transistor T 9  is provided for maintaining a low voltage of the pull-down point Q n ; the seventh thin-film transistor T 7  is provided for setting pull-down points P n  and K n  at low voltages when Q n  is at a high voltage and also for deactivating the first pull-down holding unit  46  to prevent the pull-down point Q n  from affecting the first output terminal  27  (G n ). The second low level V ss2  being smaller than the first low level V ss1  helps reduce leakage currents of the eighth and ninth thin-film transistors T 8 , T 9 . 
         [0083]    The second pull-down holding unit  47  comprises tenth to thirteenth thin-film transistors T 10 , T 11 , T 12 , T 13  and the tenth thin-film transistor T 10  comprises a tenth gate terminal g 10 , a tenth source terminal s 10 , and a tenth drain terminal d 10 ; the eleventh thin-film transistor T 11  comprises an eleventh gate terminal g 11 , an eleventh source terminal s 11 , and an eleventh drain terminal d 11 ; the twelfth thin-film transistor T 12  comprises a twelfth gate terminal g 12 , a twelfth source terminal s 12 , and a twelfth drain terminal d 12 ; and the thirteenth thin-film transistor T 13  comprises a thirteenth gate terminal g 13 , a thirteenth source terminal s 13 , and a thirteenth drain terminal d 13 , wherein the tenth gate terminal g 10  and the tenth source terminal s 10  are connected to the third clock signal input terminal  32 ; the tenth drain terminal d 10  is electrically connected to a pull-down point K n , the eleventh drain terminal d 11 , the twelfth gate terminal g 12 , and the thirteenth gate terminal g 13 ; the eleventh gate terminal g 11  is electrically connected to the first drain terminal d 1 , the thirteenth drain terminal d 13 , the seventh gate terminal g 7 , the ninth drain terminal d 9 , and said one end of the capacitor C b ; the eleventh source terminal s 11  is electrically connected to the second low level input terminal  26 ; the twelfth drain terminal d 12  is electrically connected to said opposite end of the capacitor C b , the eighth drain terminal d 8 , and the first output terminal  27  (G n ); the twelfth source terminal s 12  is electrically connected to the first low level input terminal  25 ; and the thirteenth source terminal s 13  is electrically connected to the first low level input terminal. 
         [0084]    The twelfth thin-film transistor T 12  is provided generally for maintain a low voltage of the first output terminal  27  (G n ); the thirteenth thin-film transistor T 13  is provided for maintain a low voltage of the pull-down point Q n ; the eleventh thin-film transistor T 11  is provided for setting the pull-down points P n  and K n  at a low voltage when Q n  is at a high voltage and for deactivating the second pull-down holding unit  47  to prevent the pull-down point Q n  from affecting the first output terminal  27  (G n ). The second low level V ss2  being smaller than the first low level V ss1  helps reduce leakage currents of the twelfth and thirteenth thin-film transistors T 12 , T 13 . 
         [0085]    Referring to  FIG. 5 , in the drawing, signals CK 1  and CK 2  are two clock signals of which the low voltages are opposite at a give time point; the second low level V ss2  is smaller than the first low level V ss1 ; and G n  and G n+1  are the output signals of the second output terminals  27  of two adjacent GOA units. It can be seen that Q n  and G n  can be pulled down to the low voltage of V ss1  and P n  and K n  can be pulled to the low voltage of V ss2  when Q n  and G n  are at the high voltage. In this way, the relative potential V gs  between the gate terminal and the source terminal of the eighth and ninth thin-film transistors T 8 , T 9  and between those of the twelfth and thirteenth thin-film transistors T 12 , T 13  is less than 0 (V gs =V ss2 −V ss1 ). Since the minimum leakage current of a thin-film transistor in an OFF state is at a location where the relative potential V gs  between the gate terminal and the source terminal is less than 0 (as shown in  FIG. 6 ), the GOA circuit of the instant embodiment can effectively reduce the leakage currents of the eighth and ninth thin-film transistors T 8 , T 9  and the twelfth and thirteenth thin-film transistors T 12 , T 13 . 
         [0086]    Referring to  FIGS. 7-8 , which shows a GOA circuit according to another embodiment of the present invention provides, in the instant embodiment, the first pull-down holding unit  46  further comprises a fourteenth thin-film transistor T 14  and the fourteenth thin-film transistor T 14  comprises a fourteenth gate terminal g 14 , a fourteenth source terminal s 14 , and a fourteenth drain terminal d 14 , wherein the fourteenth gate terminal g 14  is connected to the third clock signal input terminal  32 ; the fourteenth drain terminal d 14  is electrically connected to the sixth drain terminal d 6 , the seventh drain terminal d 7 , the eighth gate terminal g 8 , and the ninth gate terminal g 9 ; and the fourteenth source terminal s 14  is electrically connected to the sixth gate terminal g 6 , the sixth source terminal g 6 , and the second clock signal input terminal  31 . The second pull-down holding unit  47  further comprises a fifteenth thin-film transistor T 15  and the fifteenth thin-film transistor T 15  comprises a fifteenth gate terminal g 15 , a fifteenth source terminal s 15 , and a fifteenth drain terminal d 15 , wherein the fifteenth gate terminal g 15  is connected to the second clock signal input terminal  31 ; the fifteenth source terminal s 15  is electrically connected to the tenth source terminal s 10 , the tenth gate terminal g 10 , and the third clock signal input terminal  32 ; and the fifteenth drain terminal d 15  is electrically connected to the tenth drain terminal d 10 , the eleventh drain terminal d 11 , the twelfth gate terminal g 12 , and the thirteenth gate terminal g 13 . 
         [0087]    In the instant embodiment, the first and second pull-down holding units  46 ,  47  are improved in respect of the drawback of the diode design of the sixth thin-film transistor T 6  and the tenth thin-film transistor T 10  by additionally including the fourteenth thin-film transistor T 14  and the fifteenth thin-film transistor T 15  to discharge to the pull-down points P n  and K n  in order to fast pull the potentials of the pull-down points P n  and K n  down to the low voltage of the first clock signal CK 1  or the second clock signal CK 2            the low voltage. Through the alternative operations of the first and second pull-down holding units  46 ,  47 , the potentials of P n  and K n  following variations of the first clock signal CK 1  and the second clock signal CK 2  to change up and down can be achieved, providing alternating operations thereby reducing the influence of the eighth and ninth thin-film transistors T 8 , T 9  and the twelfth and thirteenth thin-film transistor sT 12 , T 13  by stress. 
         [0088]    Referring to  FIGS. 9-10 , which show a GOA circuit according to a further embodiment of the present invention, the instant embodiment is generally similar to the embodiment with reference to  FIG. 7  and a difference therebetween is that in the instant embodiment, the second and third clock signal input terminals  31 ,  32  of the first and second pull-down holding units  46 ,  47  are replaced by first and second low frequency signal input terminals  34 ,  35  and the first and second low frequency signal input terminals  34 ,  35  receive inputs of low frequency or ultralow frequency signals LC 1  and LC 2 . This helps reduce power consumptions of the first and second pull-down holding units  46 ,  47 , because the first and second pull-down holding units  46 ,  47  are constantly kept in operating conditions and for a large number of stages included in the GOA circuit, high frequency signals would increase the power consumption of the GOA circuit. 
         [0089]    In summary, the present invention provides a GOA circuit, which uses two low level signals to reduce the leakage currents of the thin-film transistors of a pull-down holding unit, wherein the second low level that has a lower level provides a low voltage to pull-down points P n  and K n  and the first low level that has a higher level provides a low voltage to the pull-down points Q n  and G n , so as to reduce the potentials of the pull-down point P n  and K n  when the pull-down point Q n  and G n  are activated to thereby facilitate charging of Q n  and G n  and also to break the leakage current loop of the circuit between two low level signals to greatly reduce the leakage current between the two low level signal, enhance the performance of the GOA circuit, and improve the quality of displayed images; further, the fourteenth thin-film transistor and the fifteenth thin-film transistor are additionally included in respect of the diode design of the sixth thin-film transistor and the tenth thin-film transistor to perform discharging to the pull-down points P n  and K n , thereby achieving the potentials of P n  and K n  changing up and down with the variation of the first clock signal CK 1  and the second clock signal CK 2 , providing alternating operations so as to reduce the influence of the eighth and ninth thin-film transistor and the twelfth and thirteenth thin-film transistor by stresses, extending the lifespan of the GOA circuit. Further, using low frequency or ultralow frequency signals to control the pull-down holding unit effectively reduces power consumption of the circuit. 
         [0090]    Based on the description given above, those having ordinary skills of the art may easily contemplate various changes and modifications of the technical solution and technical ideas of the present invention and all these changes and modifications are considered within the protection scope of right for the present invention.