PATENT ABSTRACT
An audio signal processor which modifies audio signal components outside the conventional audio frequency band. The processor includes a Delta Sigma Modulator (DSM) that receives a non-interpolated digital audio signal sampled at a frequency of at least 198 kHz.

PATENT DESCRIPTION
This is a continuation application of U.S. Ser. No. 09/973,254, filed Oct. 9, 2001 now U.S. Pat. No. 6,754,341, which is a continuation application of U.S. Ser. No. 09/737,425, filed Dec. 15, 2000, now U.S. Pat. No. 6,330,330, which is a continuation application of U.S. Ser. No. 09/034,683, filed Mar. 4, 1998, now U.S. Pat. No. 6,167,134, which is a continuation-in-part of U.S. Ser. No. 08/841,409, now U.S. Pat. No. 6,137,827, Ser. No. 08/837,702, now U.S. Pat. No. 5,870,046 and er. No. 08/837,714, now U.S. Pat. No. 6,430,229 all filed on Apr. 22, 1997. Further, the following U.S. patent applications Ser. No. 09/034,687, filed Mar. 4, 1998, now U.S. Pat. No. 6,359,983, and entitled “Digital Isolation System With Data Scrambling” by Andrew W. Krone et al.; Ser. No. 09/034,456, filed Mar. 4, 1998, now U.S. Pat. No. 6,144,326, and entitled “Digital Isolation With ADC Offset Calibration” by Andrew W. Krone et al.; Ser. No. 09/034,455, filed Mar. 4, 1998, now U.S. Pat. No. 6,480,602, and entitled “Ring-Detect Interface Circuitry and Method for a Communication System” by Timothy J. Dupuis et al.; Ser. No. 09/035,779, filed Mar. 4, 1998, now U.S. Pat. No. 6,389,134, and entitled “Call Progress Monitor Circuitry and Method for a Communication System” by Timothy J. Dupuis et al.; Ser. No. 09/034,620, filed Mar. 4, 1998, now U.S. Pat. No. 6,160,885, and entitled “Caller ID Circuit Powered Through Hookswitch Devices” by Jeffrey W. Scott et al.; Ser. No. 09/034,682, filed Mar. 4, 1998, now U.S. Pat. No. 6,408,034, and entitled “Framed Delta Sigma Data With Unlikely Delta Sigma Data Patterns”: by Andrew W. Krone et al.; and Ser. No. 09/035,175, filed Mar. 4, 1998, now U.S. Pat. No. 6,385,235, and entitled “Direct Digital Access Arrangement Circuitry and Method for Connecting to Phone Lines” by Jeffrey W. Scott et al. are expressly incorporated herein by reference. 

   TECHNICAL FIELD OF THE INVENTION 
   This invention relates to the field of isolation systems for use in selectively isolating electrical circuits from one another. More particularly, this invention relates to techniques for minimizing power dissipation in DC holding circuitry for a communication system that may include isolation systems having capacitor-coupled isolation barriers. This invention is useful in, for example, telephony, medical electronics and industrial process control applications. 
   BACKGROUND 
   Electrical isolation barriers can be identified in many industrial, medical and communication applications where it is necessary to electrically isolate one section of electronic circuitry from another electronic section. In this context isolation exists between two sections of electronic circuitry if a large magnitude voltage source, typically on the order of one thousand volts or more, connected between any two circuit nodes separated by the barrier causes less than a minimal amount of current flow, typically on the order of ten milliamperes or less, through the voltage source. An electrical isolation barrier must exist, for example, in communication circuitry which connects directly to the standard two-wire public switched telephone network and that is powered through a standard residential wall outlet. Specifically, in order to achieve regulatory compliance with Federal Communications Commission Part 68, which governs electrical connections to the telephone network in order to prevent network harm, an isolation barrier capable of withstanding 1000 volts rms at 60 Hz with no more than 10 milliamps current flow, must exist between circuitry directly connected to the two wire telephone network and circuitry directly connected to the residential wall outlet. 
   In many applications there exists an analog or continuous time varying signal on one side of the isolation barrier, and the information contained in that signal must be communicated across the isolation barrier. For example, common telephone network modulator/demodulator, or modem, circuitry powered by a residential wall outlet must typically transfer an analog signal with bandwidth of approximately 4 kilohertz across an isolation barrier for transmission over the two-wire, public switched telephone network. The isolation method and associated circuitry must provide this communication reliably and inexpensively. In this context, the transfer of information across the isolation barrier is considered reliable only if all of the following conditions apply: the isolating elements themselves do not significantly distort the signal information, the communication is substantially insensitive to or undisturbed by voltage signals and impedances that exist between the isolated circuitry sections and, finally, the communication is substantially insensitive to or undisturbed by noise sources in physical proximity to the isolating elements. 
   High voltage isolation barriers are commonly implemented by using magnetic fields, electric fields, or light. The corresponding signal communication elements are transformers, capacitors and opto-isolators. Transformers can provide high voltage isolation between primary and secondary windings, and also provide a high degree of rejection of lower voltage signals that exist across the barrier, since these signals appear as common mode in transformer isolated circuit applications. For these reasons, transformers have been commonly used to interface modem circuitry to the standard, two-wire telephone network. In modem circuitry, the signal transferred across the barrier is typically analog in nature, and signal communication across the barrier is supported in both directions by a single transformer. However, analog signal communication through a transformer is subject to low frequency bandwidth limitations, as well as distortion caused by core nonlinearities. Further disadvantages of transformers are their size, weight and cost. 
   The distortion performance of transformer coupling can be improved while reducing the size and weight concerns by using smaller pulse transformers to transfer a digitally encoded version of the analog information signal across the isolation barrier, as disclosed in U.S. Pat. No. 5,369,666, “MODEM WITH DIGITAL ISOLATION” (incorporated herein by reference). However, two separate pulse transformers are disclosed for bidirectional communication with this technique, resulting in a cost disadvantage. Another disadvantage of transformer coupling is that additional isolation elements, such as relays and opto-isolators, are typically required to transfer control signal information, such as phone line hookswitch control and ring detect, across the isolation barrier, further increasing the cost and size of transformer-based isolation solutions. 
   Because of their lower cost, high voltage capacitors have also been commonly used for signal transfer in isolation system circuitry. Typically, the baseband or low frequency analog signal to be communicated across the isolation barrier is modulated to a higher frequency, where the capacitive isolation elements are more conductive. The receiving circuitry on the other side of the barrier demodulates the signal to recover the lower bandwidth signal of interest. For example, U.S. Pat. No. 5,500,895, “TELEPHONE ISOLATION DEVICE” (incorporated herein by reference) discloses a switching modulation scheme applied directly to the analog information signal for transmission across a capacitive isolation barrier. Similar switching circuitry on the receiving end of the barrier demodulates the signal to recover the analog information. The disadvantage of this technique is that the analog communication, although differential, is not robust. Mismatches in the differential components allow noise signals, which can capacitively couple into the isolation barrier, to easily corrupt both the amplitude and timing (or phase) of the analog modulated signal, resulting in unreliable communication across the barrier. Even with perfectly matched components, noise signals can couple preferentially into one side of the differential communication channel. This scheme also requires separate isolation components for control signals, such as hookswitch control and ring detect, which increase the cost and complexity of the solution. 
   The amplitude corruption concern can be eliminated by other modulation schemes, such as U.S. Pat. No. 4,292,595, “CAPACITANCE COUPLED ISOLATION AMPLIFIER AND METHOD,” which discloses a pulse width modulation scheme; U.S. Pat. No. 4,835,486 “ISOLATION AMPLIFIER WITH PRECISE TIMING OF SIGNALS COUPLED ACROSS ISOLATION BARRIER,” which discloses a voltage-to-frequency modulation scheme; and U.S. Pat. No. 4,843,339 “ISOLATION AMPLIFIER INCLUDING PRECISION VOLTAGE-TO-DUTY CYCLE CONVERTER AND LOW RIPPLE, HIGH BANDWIDTH CHARGE BALANCE DEMODULATOR,” which discloses a voltage-to-duty cycle modulation scheme. (All of the above-referenced patents are incorporated herein by reference.) In these modulation schemes, the amplitude of the modulated signal carries no information and corruption of its value by noise does not interfere with accurate reception. Instead, the signal information to be communicated across the isolation barrier is encoded into voltage transitions that occur at precise moments in time. Because of this required timing precision, these modulation schemes remain analog in nature. Furthermore, since capacitively coupled noise can cause timing (or phase) errors of voltage transitions in addition to amplitude errors, these modulation schemes remain sensitive to noise interference at the isolation barrier. 
   Another method for communicating an analog information signal across an isolation barrier is described in the Silicon Systems, Inc. data sheet for product number SSI73D2950. (See related U.S. Pat. No. 5,500,894 for “TELEPHONE LINE INTERFACE WITH AC AND DC TRANSCONDUCTANCE LOOPS” and U.S. Pat. No. 5,602,912 for “TELEPHONE HYBRID CIRCUIT”, both of which are incorporated herein by reference.) In this modem chipset, an analog signal with information to be communicated across an isolation barrier is converted to a digital format, with the amplitude of the digital signal restricted to standard digital logic levels. The digital signal is transmitted across the barrier by means of two, separate high voltage isolation capacitors. One capacitor is used to transfer the digital signal logic levels, while a separate capacitor is used to transmit a clock or timing synchronization signal across the barrier. The clock signal is used on the receiving side of the barrier as a timebase for analog signal recovery, and therefore requires a timing precision similar to that required by the analog modulation schemes. Consequently one disadvantage of this approach is that noise capacitively coupled at the isolation barrier can cause clock signal timing errors known as jitter, which corrupts the recovered analog signal and results in unreliable communication across the isolation barrier. Reliable signal communication is further compromised by the sensitivity of the single ended signal transfer to voltages that exist between the isolated circuit sections. Further disadvantages of the method described in this data sheet are the extra costs and board space associated with other required isolating elements, including a separate high voltage isolation capacitor for the clock signal, another separate isolation capacitor for bidirectional communication, and opto-isolators and relays for communicating control information across the isolation barrier. 
   Opto-isolators are also commonly used for transferring information across a high voltage isolation barrier. Signal information is typically quantized to two levels, corresponding to an “on” or “off” state for the light emitting diode (LED) inside the opto-isolator. U.S. Pat. No. 5,287,107 “OPTICAL ISOLATION AMPLIFIER WITH SIGMA-DELTA MODULATION” (incorporated herein by reference) discloses a delta-sigma modulation scheme for two-level quantization of a baseband or low frequency signal, and subsequent communication across an isolation barrier through opto-isolators. Decoder and analog filtering circuits recover the baseband signal on the receiving side of the isolation barrier. As described, the modulation scheme encodes the signal information into on/off transitions of the LED at precise moments in time, thereby becoming susceptible to the same jitter (transition timing) sensitivity as the capacitive isolation amplifier modulation schemes. 
   Another example of signal transmission across an optical isolation barrier is disclosed in U.S. Pat. No. 4,901,275 “ANALOG DATA ACQUISITION APPARATUS AND METHOD PROVIDED WITH ELECTRO-OPTICAL ISOLATION” (incorporated herein by reference). In this disclosure, an analog-to-digital converter, or ADC, is used to convert several, multiplexed analog channels into digital format for transmission to a digital system. Opto-isolators are used to isolate the ADC from electrical noise generated in the digital system. Serial data transmission across the isolation barrier is synchronized by a clock signal that is passed through a separate opto-isolator. The ADC timebase or clock, however, is either generated on the analog side of the barrier or triggered by a software event on the digital side of the barrier. In either case, no mechanism is provided for jitter insensitive communication of the ADC clock, which is required for reliable signal reconstruction, across the isolation barrier. Some further disadvantages of optical isolation are that opto-isolators are typically more expensive than high voltage isolation capacitors, and they are unidirectional in nature, thereby requiring a plurality of opto-isolators to implement bidirectional communication. 
   In addition, direct access arrangement (DAA) circuitry including isolation barriers may be used to terminate the telephone connections at the user&#39;s end and may include, for example, an isolation barrier, DC termination circuitry, AC termination circuitry, ring detection circuitry, and processing circuitry that provides a communication path for signals to and from the phone lines. The DC impedance that the DAA circuitry presents to the telephone line (typically≦300Ω) is required by regulations to be less than the AC impedance that the DAA circuitry presents to the telephone line (typically≈600Ω). Consequently, inductive behavior is required from the section of the DAA circuitry that sinks DC loop current, which is typically called the DC holding circuitry. This inductive behavior of the DC holding circuitry should provide both high impedance and low distortion for voiceband signals. 
   Prior techniques for implementing DC holding circuitry have included bipolar transistor (e.g., PNP transistor) implementations. These prior techniques, however, have suffered from various disadvantages. For example, although bipolar transistor implementations typically present a desired high impedance (e.g., &gt;&gt;600Ω) to the telephone network for voiceband signals, such implementations are limited. In contrast, a CMOS design would be preferable because CMOS technology allows a high level of integration, for example with other phone line interface functions. CMOS implementations on CMOS integrated circuits, however, may face considerable problems in dissipating the power consumed by the DC holding circuitry. 
   SUMMARY OF THE INVENTION 
   The present invention provides a CMOS implementation for DC holding circuitry in DAA circuitry that achieves the desired inductive behavior while minimizing the power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry may include MOS transistors located on a CMOS integrated circuit and an off-chip resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation of the present invention also allows a path for drawing DC current to power other CMOS circuits (e.g., ADCs and DACs) in the CMOS integrated circuit. 
   In one general respect, the present invention is a communication system including phone line side circuitry that may be coupled to phone lines, powered side circuitry that may be coupled to the phone line side circuitry through an isolation barrier, and a DC holding circuit within the phone line side circuitry including a power dissipating resistor coupled external to an integrated circuit chip interface of the phone line side circuitry. 
   In a further embodiment, the isolation barrier is coupled between the phone line side circuitry and the powered side circuitry. Still further, the isolation barrier may comprise one or more capacitors and the information communicated across the isolation barrier may be digital. In a more detailed embodiment, the DC holding circuitry of the communication system may include a MOS transistor and an operational amplifier connected to two voltage supplies. 
   In another general respect, the present invention is a method for reducing power dissipation requirements for a communication system including coupling an isolation barrier between powered side circuitry and phone line side circuitry that may be coupled to phone lines, providing a DC holding circuit within the phone line side circuitry that may be coupled to receive current from the phone lines, and dissipating power within the DC holding circuit with a resistor that is coupled external to an integrated circuit chip interface of the phone line side circuitry. 
   In a further embodiment, the isolation barrier may be capacitive and information transmitted across the isolation barrier may be digital. In a more detailed embodiment, the dissipating step may include positioning a MOS transistor within a current path of the DC holding circuit, generating an internal power supply for the integrated circuit, and coupling an external power dissipating resistor to the MOS transistor. 
   In a further general respect, the present invention is a DC holding circuit for reducing power dissipation requirements of an integrated circuit within a communication system that may be connected to phone lines including power supply circuitry providing an internal DC supply voltage for the integrated circuit and a power dissipating resistor coupled to the power supply circuitry and coupled external to the chip interface of the integrated circuit. 
   In a more detailed embodiment, the power supply circuitry may include a MOS transistor and the power dissipating resistor may be connected within a current path of the MOS transistor but outside of a current path of the internal DC supply voltage. Further, the power supply circuitry may also include a first and a second voltage supplies and an operational amplifier. 
   In still another general respect, the present invention is a method for reducing power dissipation requirements for an integrated circuit within a communication system that may be connected to phone lines including providing a DC holding circuit that may receive current from phone lines, generating an internal DC supply voltage for the integrated circuit with the DC holding circuit, and coupling an external power dissipating resistor to the power supply circuitry and connected external to the chip interface of the integrated circuit. 
   In a further embodiment, the coupling step further includes positioning the power dissipating resistor outside of a current path for the internal DC supply voltage. Still further, the generating step may include providing a first and a second voltage supplies. 

   
     DESCRIPTION OF THE DRAWINGS 
     So that the manner in which the herein described advantages and features of the present invention, as well as others which will become apparent, are attained and can be understood in detail, more particular description of the invention summarized above may be had by reference to the embodiments thereof which are illustrated in the appended drawings, which drawings form a part of this specification. 
     It is noted, however, that the appended drawings illustrate only exemplary embodiments of the invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
       FIG. 1  is a block diagram of a telephone set illustrating a typical application of the present invention. 
       FIG. 2  is a block diagram showing a unidirectional isolation system according to the present invention. 
       FIG. 3A  is a block diagram detailing the circuitry used to provide a two-phase, non-overlapping clock signal to the delta-sigma modulators that are used in preferred embodiments of this invention. 
       FIG. 3B  is a timing diagram that illustrates timing relationships between various clock and data signals that occur in the circuitry of the present invention. 
       FIGS. 4A and 4B  are diagrams that illustrate signal formats that may be produced by the encoders used in this invention. 
       FIG. 5  is a block diagram showing the components of exemplary clock recovery circuit that is used in the present invention. 
       FIGS. 6A and 6B  are schematic diagrams of active diode bridge circuits that may be used as power supplies in preferred embodiments of the present invention. 
       FIG. 7  is a block diagram illustrating a bidirectional isolation system according to the present invention. 
       FIG. 8  is a block diagram of a clock recovery and data synchronization circuit according to a preferred embodiment of the present invention. 
       FIG. 9  is a schematic diagram of a phase detector circuit that may be used in a clock recovery circuit according to a preferred embodiment of the present invention. 
       FIG. 10  is a schematic diagram of a frequency detector circuit that may be used in a clock recovery circuit according to a preferred embodiment of the present invention. 
       FIG. 11  is a block diagram of a decoder circuit that may be utilized in a preferred embodiment of the present invention. 
       FIG. 12  is an illustration representing a framing format that may be beneficially used in preferred embodiments of the present invention. 
       FIGS. 13A and 13B  are schematic diagrams of driver circuits that may be utilized to implement the present invention. 
       FIG. 14  is a timing diagram illustrating an alternative framing format that may be used in bidirectional embodiments of the present invention. 
       FIG. 15  is a block diagram of a clock recovery circuit that may be employed for use with the framing format of FIG.  14 . 
       FIG. 16  is a block diagram of DC holding circuitry according to the present invention located within phone line side circuitry that may be part of direct access arrangement (DAA) circuitry. 
       FIG. 17  is a circuit diagram of DC holding circuitry according to the present invention. 
       FIG. 18  is a circuit diagram of loop current monitor circuitry according to the present invention included within the DC holding circuitry of FIG.  17 . 
       FIG. 19  is a block diagram of an analog-to-digital converter for converting analog information from the loop current monitor circuitry of  FIG. 18  to digital information for transmission across the isolation barrier. 
       FIG. 20  is a detailed circuit diagram for a voltage input version of an analog successive approximation (SAR) analog-to-digital converter (ADC) according to the present invention that may be used as an embodiment for the analog-to-digital converter of FIG.  19 . 
       FIG. 21  is a detailed circuit diagram for a current input version of an analog successive approximation (SAR) analog-to-digital converter (ADC) according to the present invention that may be used as an embodiment for the analog-to-digital converter of FIG.  19 . 
   

   DESCRIPTION OF PREFERRED EMBODIMENTS 
   In order to provide a context for understanding this description,  FIG. 1  illustrates a typical application for the present invention: a telephone that includes circuitry powered by a source external to the phone system. A basic telephone circuit  118  is powered by the “battery” voltage that is provided by the public telephone system and does not have a separate power connection. Many modem phones  110 , however, include radio (cordless), speakerphone, or answering machine features that require an external source of power  112 , typically obtained by plugging the phone (or a power supply transformer/rectifier) into a typical 110-volt residential wall outlet. In order to protect public phone system  114  (and to comply with governmental regulations), it is necessary to isolate “powered circuitry”  116  that is externally powered from “isolated circuitry”  118  that is connected to the phone lines, to prevent dangerous or destructive voltage or current levels from entering the phone system. (Similar considerations exist in many other applications as well, including communication, medical and instrumentation applications in which this invention may be beneficially applied.) The required isolation is provided by isolation barrier  120 . The signal that passes through the isolation barrier  120  is an analog voice signal in a typical telephone application, but it may also be a digital signal or a multiplexed signal with both analog and digital components in various applications. In some applications, communication across isolation barrier  120  may be unidirectional (in either direction), but in many applications, including telephony, bidirectional communication is required. Bidirectional communication may be provided using a pair of unidirectional isolator channels, or by forming a single isolation channel and multiplexing bidirectional signals through the channel. 
   The primary requirements placed on isolation barrier  120  are that it effectively prevents harmful levels of electrical power from passing across it, while accurately passing the desired signal from the powered side  122  to the isolated side  124 , or in the reverse direction if desired. 
     FIG. 2  illustrates a basic block diagram of a preferred embodiment of the present invention. First the overall operation of the invention will be described, and then each component will be described in detail to the extent required to enable a person skilled in the art to make and use the invention. As a matter of terminology, the circuitry shown on the left or powered side of the isolation barrier (capacitors  209  and  210  in  FIG. 2 ) will be referred to as the “powered” circuitry or the “transmit” circuitry or system, and the circuitry on the right side of the isolation barrier will be referred to as the “isolated” or “receive” circuitry or system. The “transmit” side can ordinarily be identified by the location of the dominant master oscillator  202  on that side of the barrier, and the slave oscillator (e.g. clock recovery circuit  216 ) is located on the receive side. Note, however, that in some embodiments of the present invention signals may be transmitted from the receive system to the transmit system, so these terms do not necessarily indicate the direction of data flow across the barrier. Furthermore, in some embodiments the master oscillator may be on the low-power (e.g. telephone system) side of the barrier, and a clock recovery PLL may be located on the high-power side of the barrier. 
   Referring to  FIG. 2 , a preferred unidirectional capacitive isolation system according to the present invention includes a delta-sigma analog to digital converter  201  operable on the analog input  212  and driven by a clock signal from oscillator  202 . The digital output of the delta-sigma ADC  224  is synchronous with the operating frequency of oscillator  202  and time division multiplexed with digital control signals  219  by encoder circuit  213 . The encoder circuit  213  also formats the resulting digital data stream  230  into a coding scheme or framing format that allows for robust clock recovery on the receiving side of the isolation barrier. The isolation barrier comprises two high voltage capacitors  209  and  210 . In one embodiment of the present invention, driver circuit  214  drives the transmit side of capacitor  209  with a digital voltage signal. Clock recovery circuit  216  presents a very high impedance to the receive side of capacitor  209 , allowing the digital voltage output of driver  214  to couple across the isolation barrier. In this embodiment, capacitor  210  provides a return current path across the barrier. In another embodiment, capacitors  209 ,  210  are differentially driven by complementary digital outputs of driver circuit  214 . In that embodiment, clock recovery circuit  216  presents a very high impedance to the receive sides of capacitors  209  and  210 , allowing the differential digital voltage outputs of driver  214  to couple across the isolation barrier. The input to driver circuit  214  is the output  230  of encoder  213 . 
   The receive side of the isolation barrier includes clock recovery circuit  216 , with inputs connected to isolation capacitors  209  and  210 . The clock recovery circuit recovers a clock signal from the digital data driven across the isolation barrier. The recovered clock provides clocking signals for decoder  217  and delta-sigma digital-to-analog converter  208 . Decoder circuit  217  separates the time division multiplexed data signal from control signals, providing a digital control output  228  and data output  232  that is routed to delta-sigma DAC  208 . The delta-sigma DAC  208 , with digital input supplied from decoder  217  and clock supplied from clock recovery circuit  216 , provides the analog output of the receive side of the isolation system, which closely corresponds to the original analog input  212 . 
   Active diode bridge circuit  640  may also be connected to isolation capacitors  209  and  210  to provide a DC voltage source  220  to clock recovery circuit  216  and decoder circuit  217  derived from energy contained in the signal transmitted across the isolation barrier. 
   In the descriptions of preferred embodiments that follow, all circuit references are made with respect to MOS (metal oxide-semiconductor) integrated circuit technology, although the invention may be implemented in other technologies as well, as will be understood by one skilled in the art. A preferred embodiment incorporates transmit system  225  consisting of delta-sigma ADC  201 , oscillator  202 , encoder  213  and driver  214  fabricated on one silicon substrate, and receive system  226  consisting of clock recovery circuit  216 , decoder  217 , delta-sigma DAC  208  and active diode bridge  640  fabricated on a second silicon substrate. The two separate silicon substrates are required to maintain the high voltage isolation provided by capacitors  209  and  210 , since typical MOS technologies cannot provide high voltage isolation of 1000 volts or greater. 
   The delta-sigma analog-to-digital converter, shown as block  201  of  FIG. 2 , is well known in the art. See, for example, J. C. Candy,  A Use of Double Integration in Sigma Delta Modulation , IEEE Trans. On Communication, March 1985, pp. 249-258, and B. E. Boser and B. A. Wooley,  The Design of Sigma - Delta Modulation Analog - to - Digital Converters , IEEE Journal Solid State Circuits, December 1988, pp. 1298-1308, both of which are incorporated herein by reference. The specific design of ADC  201  will be a matter of design choice depending upon the needs of the particular application in which the isolation barrier will be used. 
   The use of a delta-sigma converter within the isolation system provides several desirable features. It will be appreciated that the delta-sigma converter uses a high oversampling rate to provide accurate A/D conversion over the input signal bandwidth without the use of precisely matched components or high-order, analog anti-aliasing filters. Moreover, such converters occupy a relatively small amount of space on an integrated circuit and are relatively easy to fabricate on a CMOS chip. 
   The digital pulse stream  224  output from delta-sigma converter  201  encodes the analog input signal  212  in a pulse density modulation format. In pulse density modulation, the amplitude information of the analog input signal is contained in the density of output pulses generated during a given interval of time. 
   Suitable designs for oscillator circuit  202  are well known in the art and may typically comprise a ring oscillator, relaxation oscillator, or an oscillator based on a piezo-electric crystal disposed external to the integrated MOS circuit. See, for example, A. B. Grebene,  Bipolar and MOS Analog Integrated Circuit Design , John Wiley and Sons, 1984, which is incorporated herein by reference.  FIG. 3A  further illustrates the clock signals that may be provided to delta-sigma converter  201  in a preferred embodiment of this invention. Clock signal  302  from oscillator  202  is input to clock divider circuit  304  that divides the frequency of the input clock and provides an output in the form of two phase, non-overlapping clock signals Ø 1  and Ø 2  to the delta-sigma modulator circuit. The design and construction of clock divider circuit  304  is within the ordinary skill in the art and is not detailed here. Since encoder circuit  213  may perform time-division multiplexing of the digitized data signal  224  with digital control input data  219  using a time base derived from oscillator  202 , clock divider  304  of  FIG. 3A  must typically divide the frequency of oscillator  202  by at least a factor of two. 
     FIG. 3B  illustrates exemplary signals associated with clock divider circuit  304  and delta-sigma modulator  201  in FIG.  3 A. Trace  310  is the clock signal received from oscillator  202  on line  302 . Trace  312  is the “clock divided by 2” signal that is generated by clock divider circuit  304 . Traces  314  and  316  illustrate exemplary two phase, non-overlapping clock signals Ø 1  and Ø 2 , respectively, that may be output from clock divider circuit  304  to delta-sigma modulator  201 . Trace  318  represents the analog input to ADC  201 , which generally changes very slowly in comparison to the frequency of clock signal  310 . This bandwidth relationship is required because the delta-sigma modulator must operate at a sampling rate much higher than a typical Nyquist rate (for example, a 1 MHz sampling rate for a 4 kHz voiceband signal is typical) in order for the information in the analog signal to be accurately represented by the single-bit binary output. Finally, trace  320  represents the digital output of delta-sigma modulator  201 , which may, for example, be synchronized to the rising edge of clock signal Ø 1 . (The illustrated output bit pattern  320  is provided to show exemplary timing relationships and does not attempt to accurately reflect the illustrated analog input  318 ). 
   Referring to  FIG. 2 , the encoder circuit  213  performs two primary functions in preferred embodiments of this invention. The first function of encoder  213  is time-division multiplexing of control signals  219  from other circuitry and data signals  224  from the delta-sigma modulator  201 , an operation that is well known in the art and subject to many suitable implementations. The multiplexing function is synchronized by clock signals from oscillator  202 . The second function of encoder  213  is formatting the data for transmission across isolation capacitors  209 ,  210 .  FIG. 4  details one coding scheme that may be used to transmit digital pulses across the capacitive isolation barrier. (Another suitable coding scheme is described below with reference to  FIG. 14. )  FIG. 4A  shows the format for data sent from the transmit circuit to the receive circuit. When data=1 for a given bit cell, the output of the encoder is high for the first quarter of the bit cell period. When data=0 for a given bit cell, the output of the encoder is high for the third quarter of the bit cell period. This coding scheme guarantees one low-to-high transition followed by one high-to-low transition for every bit cell period, independent of the data pattern. The resulting data independent transition density allows for robust clock recovery in the receiving circuitry on the other side of isolation capacitors  209 ,  210 . Alternatively, robust clock recovery can also be achieved by use of a preamble used for frequency locking followed by a data pattern which is not of constant average frequency. 
   In a bidirectional system, as is described below in connection with  FIG. 7 , the transmit system encoder  702  and driver  703  may cooperate to provide a high-impedance tri-state output to the isolation capacitor  705  during either the last half of the bit cell period  410  (if transmit data=1) or the first half of the bit cell period  411  (if transmit data=0) as shown in  FIG. 4   a . This permits transmission of information from the receive system to the transmit system during that portion of each bit cell when the transmit driver  703  is tri-stated. 
   In a preferred embodiment, at the beginning of each bit cell period the receive system decoder section  708  detects whether the transmit circuit has sent a data −1 pulse across the isolation barrier. If a transmit data=1 pulse was sent, the receive driver remains tri-stated until the second half of the bit cell period, during which time a receive data=0 or 1 pulse can be sent back across the isolation barrier to the transmit system. If a transmit data=1 pulse is not detected by the receive circuit the receive driver sends receive data=0 or 1 during the first half of the bit cell period and tri-states for the second half of the bit cell period. This operation is shown in FIG.  4 B. 
   In those embodiments in which the digital, bidirectional communication is differential, capacitors  705  and  706  are driven by complementary digital voltages in both directions, and the driver circuits associated with both capacitors are tri-stated during selected portions of the bit cell period in accordance with the coding scheme shown in FIG.  4 . 
   A preferred embodiment of the unidirectional driver circuit  214  of  FIG. 2  is detailed in  FIG. 13A  for single ended (not differential) communication and  FIG. 13B  for differential communication across the capacitive isolation barrier. Referring to  FIG. 13A , the transmit circuit driver  214  may comprise an inverter  250  driven by the encoder output signal  230 . The output of inverter  250  drives the transmit circuit side of isolation capacitor  209  to transmit logic levels defined by the transmit V DD  and ground voltage levels. The clock recovery input buffer presents a high impedance to the receive side of capacitor  209 , thereby allowing the receive side of capacitor  209  to attain substantially the same logic levels as the transmit side of capacitor  209 . In this manner the digital logic signal is effectively coupled across the capacitive isolation barrier. 
   Capacitor  210  is disposed between the transmit circuit ground node  254  and receive circuit ground node  256  in order to form a ground current return path across the isolation barrier. This path is required because the clock recovery buffer input impedance, although high, is not infinite. Therefore a small current must flow across the barrier and back in order to couple the digital logic signal across the barrier. Furthermore, capacitor  209  must deliver charge to the active diode circuit  640  ( FIG. 2 ) in order that a supply voltage for several receive circuit sections can be provided. The current associated with this transfer of charge from the transmit circuit to the receive circuit must have a path to return to the transmit circuit. 
   The single-ended communication system described above is insensitive to voltage signals that may exist between the transmit circuit ground  254  and receive circuit ground  256  provided that the rate of change of such voltage signals is substantially less than the frequency of the digital signal transmitted across the barrier. The single-ended method is also insensitive to resistive and capacitive impedances that may exist between the transmit circuit ground  254  and receive circuit ground  256 . The system can be desensitized to inductive impedances that may exist between the transmit circuit ground  254  and receive circuit ground  256  by adding resistive elements in series with capacitor  210 , in series with the transmit ground connection  254 , in series with the receive ground connection  256 , or any combination of these. 
     FIG. 13B  shows an example of a suitable differential driver  258  for unidirectional digital communication across a capacitive isolation barrier. The inverter  260  that drives capacitor  209  is driven by the digital signal output from the transmit encoder circuit  213 , while inverter  261 , which drives capacitor  210 , is driven by the complement  231  of the digital signal output from transmit encoder circuit  213 . Clock recovery input buffer  262  presents high impedances to the receive sides of capacitors  209  and  210 , allowing the differential digital transmit voltages to couple across the isolation barrier. In this differential communication method, both capacitors  209  and  210  provide return current paths across the isolation barrier. The differential digital communication system described above is largely insensitive to voltage signals and impedances that may exist between the transmit circuit ground  254  and receive circuit ground  256 , since these voltages and impedances appear as common mode influences in differential communication. 
   Bidirectional communication across the barrier can be supported by additional driver and receive buffer structures, similar to those shown in  FIG. 13 , without the need for any additional isolation elements, providing that inverters  250 ,  260 ,  261 , which drive the high voltage isolation capacitors, can be tri-stated generally in accordance with the timing diagram shown in  FIG. 4  or any other suitable coding and timing scheme. In some embodiments, additional capacitor driving inverters that can be tri-stated may be provided in a receive-side driver circuit  713  ( FIG. 7 ) and input buffers may be provided in a transmit side decoder circuit  714 . 
   In presently preferred embodiments, the actual isolation barrier comprises a pair of isolation capacitors  209  and  210 , which are high voltage capacitors that may be chosen for a particular application to prevent DC and low frequency current flow across the barrier and protect the isolated circuitry from high voltage faults and transients, while permitting data at selected transmission frequencies to cross the barrier. The capacitors must be capable of withstanding anticipated voltages that may appear due to faults in the powered circuitry  225 , in order to provide the protective function that is the purpose of the barrier. For example, in preferred embodiments ordinary 2000 volt capacitors with capacitance on the order of 100 pF may be utilized in the isolation barrier. In a barrier system in accordance with the present invention it is not necessary to use high precision capacitors, because the system is very tolerant of variations in capacitor performance due to environmental influences, such as variations in voltage and temperature. 
   A preferred embodiment for a clock recovery circuit  216  for use in this invention is detailed in FIG.  5  and described below. One section of the clock recovery circuit may be a phase locked loop (“PLL”) circuit, consisting of phase/frequency detector  531 , charge pump  532 , resistor  533 , capacitor  534 , and voltage controlled oscillator (“VCO”)  535 . The other section of the clock recovery block is data latch  542  operating outside the phase locked loop to re-time the digital data received across the isolation barrier. Circuitry for performing these functions is well known to those skilled in the art. See, for example, F. Gardner,  Phaselock Techniques , 2d ed., John Wiley &amp; Sons, N.Y., 1979; and R. Best,  Phase - Locked Loops , McGraw-Hill, 1984, which are incorporated herein by reference. The data input to the receive system from the isolation capacitors may be derived from a differential signal present at the barrier by passing the differential signal through MOS input buffers (not shown), which are well known in the art, and providing a single-ended binary output signal  530  to the clock recovery circuit. 
   The illustrated exemplary phase/frequency detector  531  receives a digital input  530  from the isolation barrier and an input  536  from the output of VCO  535  and performs a phase comparison between these two inputs. If the VCO phase lags the input data phase, a speed up signal  538  is supplied to charge pump  532 . If the input data  530  phase lags the VCO output  536  phase, a slow down signal  540  is supplied to charge pump  532 . In response to “speed up” inputs from phase/frequency detector  531 , charge pump  532  delivers a positive current to the loop filter consisting of resistor  533  and capacitor  534  connected in series. In response to “slow down” inputs from the phase/frequency detector, charge pump  532  sinks a positive current from the loop filter. The output voltage of the loop filter at node  542  drives voltage controlled oscillator  535 , which increases its operation frequency as the input voltage increases. The output of VCO  535  is fed back as input  536  to phase/frequency detector  531 , and it is also used to re-time the input data  530  by serving as the clock input to flip-flop latch  542 , thus providing a clock signal to the isolated circuitry and also providing data signal  546  that is synchronized to clock signal  544 . A divider circuit may be included in the feedback path  536 . 
   The phase/frequency detector and charge pump operate to increase loop filter voltage  542  and VCO frequency if VCO phase  536  lags input data phase  530 . Conversely, the VCO frequency is decreased if the VCO phase leads input data phase. In this manner, the VCO output phase is adjusted until phase lock is achieved with input data. Consequently, the VCO frequency is driven to be substantially identical to the input data frequency. 
   If noise interference occurs at the isolation barrier, the input data transitions will occur at points in time that are noisy, or jittered, relative to the transition times of the transmit circuit driver. These jittered data edges will cause a noise component in the charge pump current that drives the loop filter. The loop filter and VCO, however, low-pass filter this noise component, substantially attenuating the effects of this input data jitter. Consequently, the VCO output signal, while frequency locked to the input data, contains substantially less phase noise than the noisy input data. The bandwidth of the phase noise filtering operation may be set independently of the bandwidth of the analog signal to be communicated across the isolation barrier. Since the filtered, phase locked loop output clock signal  544  is used to latch or re-time the noisy input data at flip flop  542 , the effects of noise interference at the capacitive isolation barrier are substantially eliminated. Finally, the filtered, phase locked loop output clock signal  544  is used as the timebase or clock for the other receive circuits, including decoder  217  and delta-sigma DAC  208  shown in  FIG. 2 , resulting in an analog output  218  of the capacitive isolation system that is substantially free from any noise interference that may have been introduced at the capacitive isolation barrier. 
   Preferred embodiments of active diode bridge circuit  640  of  FIG. 2  are detailed in  FIG. 6A  for single-ended digital communication and  FIG. 6B  for differential digital communication across the isolation barrier. The active diode bridge generates a DC power supply voltage V DD , which may be used to operate the clock recovery and receiver decoder circuits, in response to the digital data received across the capacitive isolation barrier. An active diode bridge circuit is distinguished from a standard or passive diode bridge in that the gating elements are active transistors rather than passive elements such as bipolar diodes. 
   Referring to the exemplary circuit illustrated in  FIG. 6A , isolation capacitor  209  is connected to node  625  and isolation capacitor  210  is connected to node  626 . The source of n-channel MOSFET  621  and the source of p-channel MOSFET  622  are connected to node  625 . Also connected to node  625  is the input of standard CMOS inverter  623 . The output of inverter  623  drives the gates of MOSFETS  621  and  622 . The drain of n-channel MOSFET  621  is connected to node  626 , the receive circuit ground node, while the drain of p-channel MOSFET  622  connects to node  627 , which provides V DD  voltage for the isolated circuitry. Also connected to V DD  node  627  are load capacitor C L    624  and the power supply input of CMOS inverter  623 . In a preferred embodiment, the power supply inputs of clock recovery circuit  216  and decoder circuit  217  shown in  FIG. 2  are also connected to V DD  node  627 . 
   Referring to the exemplary embodiment illustrated in  FIG. 6A , the operation of the active diode bridge circuit used in single-ended digital communication will now be described. A digital logic signal is coupled across capacitor  209  from the transmit section. When a digital “high” signal is received through capacitor  209 , node  625  goes high. The logic “high” signal on node  625  forces the CMOS inverter  623  output node to go low, turning off device  621  and turning on device  622 . Consequently, current flows through capacitor  209 , device  622 , and from V DD  to receive circuit ground through capacitor C L  and through clock recovery and decoder circuitry shown in FIG.  2 . The circuit is completed by current flow returning across the isolation barrier through capacitor  210 . The current demand by circuitry on V DD  through capacitors  209  and  210  must be limited so that the voltage on node  625  relative to node  626  can still be recognized as a digital high logic level. When a digital “low” signal is received through capacitor  209 , CMOS inverter  623  turns off device  622  and turns on device  621 . Consequently, current flows across the isolation barrier through capacitor  210 , through device  621 , and returns across the isolation barrier through capacitor  209 . Therefore, although no average current flows through capacitors  209  and  210 , average current can be supplied from V DD  to receive circuit ground to operate clock recovery circuit  216  and decoder circuit  217 . Load capacitor  624  operates to minimize supply ripple on the DC supply voltage established on node V DD . 
   Referring to the embodiment shown in  FIG. 6B , isolation capacitor  209  connects to node  646  and isolation capacitor  210  connects to node  647 . The source node of n-channel MOSFET  641  and the source node of p-channel MOSFET  642  connect to node  646 . Also connected to node  646  are the gates of n-channel MOSFET  643  and p-channel MOSFET  644 . The source node of n-channel MOSFET  643  and the source node of p-channel MOSFET  644  connect to node  647 . Also connected to node  647  are the gates of n-channel MOSFET  641  and p-channel MOSFET  642 . The drains of devices  641  and  643  are connected to the ground node of the receiving circuit. The drains of devices  642  and  644  are connected to the node  220 , which provides V DD  voltage for the isolated circuitry. Also connected to V DD  node  220  are load capacitor C L    645  and the power supply inputs of clock recovery circuit  216  and decoder circuit  217  as shown in FIG.  2 . 
   Referring to the exemplary embodiment illustrated in  FIG. 6B , the operation of the active diode bridge used in differential digital communication will now be described. A differential digital signal is received through capacitors  209  and  210 . When a digital ‘high’ signal is received through capacitor  209 , a corresponding digital ‘low’ signal is received through capacitor  210 , and node  646  goes high while node  647  goes low. This condition turns on devices  642  and  643  while turning off devices  641  and  644 . Consequently, current flows through capacitor  209 , device  642 , from V DD  to ground through capacitor C L  and through clock recovery circuitry  216  and decoder circuitry  217  shown in FIG.  2 . The circuit is completed from receive circuit ground  650 , through device  643  and finally returning across the isolation barrier through capacitor  210 . The current demand on V DD  must be limited so that the voltage on node  646  relative to node  650  can be recognized as a high logic level signal by the clock recovery and decoder circuitry. 
   When a digital ‘low’ signal is received through capacitor  209 , a digital ‘high’ signal is received through capacitor  210 , and node  646  goes low while node  647  goes high. This condition turns on devices  641  and  644  while turning off devices  642  and  643 . Consequently current flows through capacitor  210  and device  644  to V DD  node  220 , and from there to ground through capacitor  645  and through clock recovery and decoder circuitry shown in FIG.  2 . The circuit is completed from ground  650 , through device  641  and finally returning across the isolation barrier through capacitor  209 . Therefore, in either logic state, and independently of the current flow direction through capacitors  209  and  210 , current flows in the same direction from V DD  to ground. Therefore, an average or DC supply voltage is established on node V DD , and adequate current can be supplied to operate clock recovery circuit  216  and decoder circuit  217 . Load capacitor  645  operates to minimize power supply ripple, providing a filtering operation on V DD . An added benefit of the ability to power sections of the isolated circuitry from the digital signal transmitted across the capacitive isolation barrier from the powered circuitry is that it allows isolated power-up and power-down control of isolated circuitry sections on an as-needed basis. 
   Parasitic bipolar transistors may result from typical CMOS processes. If they are not controlled, these bipolar transistors can discharge the power supply  627  shown in  FIG. 6A  during the initial power up time. If the discharge current from the parasitic bipolar transistors is larger than the current delivered to the power supply  627  through transistor  622 , then the circuit may not power up to the desired full voltage level. The beta of a lateral bipolar transistor in any CMOS process is a function of layout. With appropriate layout (i.e., large base region), the beta can be kept small enough to minimize undesired discharge currents. Further care needs to be taken in the design of any circuit that is connected to power supply  627 . The circuits connected to power supply  627  cannot draw more current from the power supply than is available from the active diode bridge, even before the supply has ramped to the full value. Circuit design techniques to address these issues are common and well known in the art. 
   In the illustrative embodiment shown in  FIG. 2 , delta-sigma digital to analog converter (DAC)  208  receives input data from decoder  217  and synchronous clock input from clock recovery circuit  216 . Analog output signal  218  is generated by DAC  208  in response to the digital data that is communicated across the capacitive isolation barrier. The output signal  218  is highly immune to amplitude and phase noise that may be introduced in the barrier circuitry because the signal that is communicated across the isolation capacitors is a synchronous digital signal, and because the received data is resynchronized to the recovered, jitter-filtered clock signal. The DAC is also timed by that clock signal. Delta-sigma DAC technology is well known in the art, and selecting a suitable DAC circuit will be a matter of routine design choice directed to the intended application of the barrier circuit. See, for example, P. Naus et al.,  A CMOS Stereo  16- Bit D/A Converter for Digital Audio , IEEE Journal of Solid State Circuits, June 1987, pp. 390-395, which is incorporated herein by reference. 
     FIG. 7  illustrates a preferred bidirectional embodiment of the present invention. It will be recognized that other unidirectional and bidirectional isolation barriers may be designed by persons skilled in the art using the principles described herein, and that such barriers will fall within the scope of this invention. In the illustrated and described embodiment, the capacitive isolation system comprises a “transmit” system to the left of center, a “receive” system to the right of center, and a capacitive isolation barrier in the center of the figure comprising two high voltage capacitors  705  and  706 . Note that the terms “transmit” and “receive” are used to identify the powered and isolated sides of the barrier, respectively, and that in this embodiment data may be conveyed across the barrier in both directions. Many of the components in this bidirectional embodiment are identical or similar to those in the unidirectional embodiment described above with reference to FIG.  2 . 
   The transmit system includes delta-sigma analog-to-digital converter  701  operable on the analog input  720  of the transmit circuit and synchronized to clock signal  722  from oscillator  704 . The analog input  720  of the transmit system is an analog signal containing information to be transmitted across the isolation barrier, which may be for example an analog voice signal to be coupled to a telephone system. Digital output  724  of the delta-sigma ADC may be time-division multiplexed with digital control input  726  by the encoder circuit  702 . Digital control input  726  is a digital signal containing additional information to be transmitted across isolation barrier  705 ,  706 . Digital control input  726  may include control information for analog circuitry on the receiving side of the isolation barrier. Encoder circuit  702  also formats the resulting data stream into a coding scheme that allows for robust clock recovery on the receiving side of the isolation barrier, as is described above. 
   Encoder circuit  702  also receives a clock signal  722  from oscillator  704 . Driver circuit  703  of the transmit system drives the encoded signal to isolation capacitors  705  and  706  in response to the output of encoder circuit  702 . 
   The isolation barrier comprises two high voltage capacitors  705 ,  706 . In one embodiment, capacitor  705  is driven bidirectionally by drivers  703 ,  713  while capacitor  706  provides a return path across the isolation barrier. In another embodiment of the present invention, capacitors  705  and  706  are differentially driven by digital driver circuits  703 ,  713 . 
   A preferred embodiment of the receive system, shown to the right of isolation capacitors  705 ,  706  in  FIG. 7  includes clock recovery circuit  707 , whose inputs are connected to isolation capacitors  705 ,  706 . The clock recovery circuit recovers a clock signal from the digital data driven across the isolation barrier and provides synchronized clock signal  730  to the various circuits in the receive system. The recovered clock operates as the time base for decoder  708  and delta-sigma digital-to-analog converter  709 . Decoder section  708  separates the time division multiplexed data and control information, providing digital control output  732  to other circuitry, and providing synchronous data signal  734  as an input to delta-sigma DAC  709 . The delta-sigma DAC  709 , with digital input  734  supplied by decoder  708 , and clock signal  730  supplied by clock recovery section  707 , operates synchronously with the transmit system delta-sigma ADC  701  and provides analog output  736  on the receiving side of the isolation barrier. Active diode bridge  710  is connected to isolation capacitors  705  and  706  and supplies a DC power supply voltage to clock recovery circuit  707  and decoder circuit  708  by drawing current from the digital signal transmitted across the isolation barrier, as is described in detail above. Driver  713  must remain tri-stated until decoder  708  has detected a valid frame, indicating successful power-up of the receive circuit sections. 
   The embodiment shown in  FIG. 7  also enables communication from the receive system to the transmit system, or from right to left across the isolation capacitors as illustrated. The receive system encoder circuit  712  and driver circuit  713  cooperate to communicate information back from the receive system to the decoder circuit  714  in the transmit system. Receive system encoder section  712  receives a clock input  730  from clock recovery section  707 , and is thereby synchronized to the transmit system oscillator  704  and encoder  702 . This synchronization allows transmission in each direction to occur in distinct time slots. In time slots where transmit driver  703  is operable to transmit information from the transmit system to the receive system, receive driver  713  is tri-stated or disabled. Alternatively, in time slots where receive driver  713  is operable to transmit information back from the receive system to the transmit system, transmit driver  703  is tri-stated or disabled. In this manner, bidirectional communication may be established across a single pair of high voltage isolation capacitors. 
   Digital control input  738  of the receive system is a digital signal containing information to be communicated across the isolation barrier, including control information for analog circuitry on the transmit system side of the barrier. The receive system also includes delta-sigma ADC  711  operable on analog input signal  740  so that the information contained in analog signal  740  on the receive system side of the isolation barrier can be conveyed across the barrier in digital form and then accurately reproduced on the transmit system side of the barrier. The receive system delta-sigma ADC  711  receives its clock input from clock recovery circuit  707 , and is thereby synchronized with transmit system oscillator  704 . Digital output signal  742  generated by receive system ADC  711  may be time-division multiplexed with receive system digital control input  738  in encoder section  712 . 
   In the transmit system, decoder circuit  714  is connected to isolation capacitors  705 ,  706  to receive signals therefrom; identify signals representing information coming from the receive system. Decoder  714  then extracts the digital control information from the data stream received from the receive circuit, and passes data signal  744  generated by delta-sigma ADC  711  to transmit system delta-sigma DAC  715 . Decoder  714  also latches and retimes the data received across the barrier to synchronize it with clock signal  722 , which is generated by oscillator  704 , thereby eliminating the effects of phase noise interference and other sources of jitter in the synchronous digital signal. Circuits that are suitable for performing these decoder functions are well known in the art. 
   Transmit system delta-sigma DAC  715  receives its clock input from oscillator  704  and is thereby synchronized to receive system ADC  711 . Transmit system DAC  715  provides a reconstructed analog data output signal  746 , thereby completing the communication of analog information back from the receive system to the transmit system. 
   In summary,  FIG. 7  describes a bidirectional communication system for conveying analog and digital information across a capacitive isolation barrier. The barrier itself is inexpensive, since only two high voltage isolation capacitors are required for synchronous, bidirectional communication. The barrier is a reliable communication channel because the digital signals communicated across the barrier are insensitive to amplitude and phase noise interference that may be introduced at the isolation barrier. 
   A more detailed description of a clock recovery circuit suitable for use in this invention with the coding scheme of  FIG. 4  will now be provided, with reference to FIG.  8 . Clock recovery PLL  805  has data input  530 , data output  546  and recovered clock signal output  544 . Phase detector  810  has inputs DATA  530  and feedback clock signal CK 2   545 . The outputs of phase detector  810  are SPEED-UP 1  and SLOW-DOWN 1  signals, both of which are connected to inputs of phase detector charge pump  816 . Frequency detector  818  has inputs DATA  530  and output clock signal CK 4   544 . The outputs of frequency detector  818  are signals designated SPEED-UP 2  and SLOW-DOWN 2 , which are connected to the inputs of frequency detector charge pump  824 . The outputs of phase detector charge pump  816  and frequency detector charge pump  824  are connected together and are also connected to the input of voltage controlled-oscillator (“VCO”)  535  and one terminal of resistor  533 . The other terminal of resistor  533  is connected to one terminal of capacitor  534 . The other terminal of capacitor  534  is connected to ground. The output of VCO  535  is the CK 2  signal  545 . The clock input of flip-flop  826  is connected to CK 2   545 . The Q-bar output of flip-flop  826  is connected to the D input of flip-flop  826 . The Q and Q-bar outputs of flip-flop  826  are connected to the inputs of multiplexer (mux)  828 . The control input  830  of mux  828  is called MUX CONTROL and comes from the framing logic, which is described elsewhere in this specification. The output of mux  828  is the CK 4  signal  544 . The D input of flip-flop  542  is connected to data input  530 . The clock input of flip-flop  542  is connected to the CK 4  signal  544 . The Q output of flip-flop  542  is the resynchronized DATAOUT signal  546 , which is sent to the frame detect logic. 
   Frequency detector  818  is dominant over phase detector  810  when the frequency of the DATA and CK 4  signals are different. Once the frequency of the DATA and CK 4  signals are substantially similar, the SPEED-UP 2  and SLOW-DOWN 2  signals become inactive and phase detector  810  becomes dominant. Separate charge pumps for the phase detector and frequency detector allow for independent control of the gain of the phase detector and frequency detector circuits. Alternatively, if independent gains are not required, then the SPEED-UP 1  and SPEED-UP 2  signals could be logically ORed together to drive one charge pump. And likewise the SLOW-DOWN 1  and SLOW-DOWN 2  signals could be logically ORed together to drive the other input to the charge pump. 
   The output of VCO  535  is the CK 2  signal, which is divided by two in frequency by flip-flop  826 . Since CK 2  is divided by two to generate the bit rate clock signal CK 4 , there can be two phases of CK 4  with respect to the start of a bit period. The phase of CK 4  that will yield correct operation of the frequency detector is the one where the rising edge of CK 4  aligns with the start of a bit period. The frame-detect logic is needed to detect the start of a bit interval and is used to select the appropriate phase of CK 4  using mux  828 . 
   It will be appreciated that a clock recovery circuit according to this invention, such as that illustrated in  FIG. 8  or  FIG. 15 , may be beneficially used to recover and stabilize a clock signal on the isolated side of the barrier where the clock signal is conveyed via isolation elements that are separate from the isolation elements that are used to transfer the data signal. 
   A preferred embodiment of a decoder circuit  708  is shown in FIG.  11 . Shift register  840  has an input connected to the DATAOUT signal  546  from clock recovery circuit  805  and is clocked by recovered clock signal CK 4 . Multi-bit output  842  of shift register  840  is connected to frame-detect logic  844  and to demux logic  846 . Frame detect logic  844  has one output connected to mux control logic  848  and one output connected to demux logic  846 . Demux logic  846  is clocked by CK 4 . Counter  850  is also clocked by CK 4 . The output of counter  850  is connected to mux control logic  848 . The output of mux control logic  848  is the MUX-CONTROL signal  830  sent to the clock recovery PLL  805  to select the proper phase for the CK 4  signal. The outputs of demux logic  846  are the DEMUXED DATA signal and the CONTROL signal. 
   Shift register  840  stores a predetermined number of bits of the serial DATAOUT signal  546 . Frame-detect logic  844  operates on this data and detects when a frame signal is received. Many possible framing signal formats can be used. A format that may be used in a presently preferred embodiment is shown in FIG.  12 . Data  860  is alternated with framing signals  862  and control signals. In the framing format shown in this figure, one control signal (off hook)  864  is sent for every eight data bits. The remaining seven bits in the frame of sixteen are used for frame synchronization. The illustrated framing signal is six ones followed by a zero in the control signal field. The data signal may be guaranteed to not have more than five ones in a row so that it will not be mistaken for a framing signal. Many other framing formats are possible to allow for different data signal properties and to permit the use of additional control bits. 
   Once the frame detect logic  844  detects six one&#39;s followed by a zero in the control signal field, mux control logic  848  is set to maintain the phase of the CK 4  signal. If after a predetermined number of CK 4  clock cycles a framing signal is not detected, then counter  850  will cause mux control logic  848  to change the phase of CK 4  using mux  828  (FIG.  8 ). Counter  850  will then be reset, and frame detect logic  844  will again attempt to detect the selected framing signal so as to achieve synchronization. Only the correct phase of CK 4  will achieve frame synchronization. Once frame synchronization is achieved, demux logic  846  can correctly decode control and data signals. 
   The specific structure and operation of frame detect logic  844 , demux logic  846 , and mux control logic  848  is dependent upon the selected framing format, the selected multiplexing scheme, and other design choices. The detailed design of this circuitry is within the ordinary skill in the art and is omitted from this description of a preferred embodiment. 
   Exemplary embodiments of phase and frequency detectors  810 ,  818  are shown in  FIGS. 9 and 10 . Referring to  FIG. 9 , phase detector  810  has input signals CK 2  and DATA and output signals SPEED-UP 1  and SLOW-DOWN 1 . A two input NAND gate  860  has inputs DATA and CK 2  and its output is connected to one input of NAND gate  862 . A two input NOR gate  864  also has inputs DATA and CK 2  and its output is connected to the input of inverter  866 . A two input NAND gate  868  has one input connected to the output of the inverter  866  and one input connected to the output of NAND gate  862 . NAND gate  862  has one input that is connected to the output of NAND gate  860  and the other input connected to the output of NAND gate  868 . A three input AND gate  870  has one input connected to the output of inverter  872 , another input connected to the DATA signal and another input connected to the output of NAND gate  862 . The output of AND gate  870  is the SLOW-DOWN 1  signal. The input of inverter  872  is connected to the CK 2  signal. A three input AND gate  874  has one input connected to the output of NAND gate  862 , another input is connected to the CK 2  signal and another input is connected to the output of inverter  876 . The output of AND gate  874  is the SPEED-UP 1  signal. The input of inverter  876  is connected to receive the DATA signal. 
   In the illustrated embodiment, phase detector  810  compares the phase on the falling edges of DATA and CK 2  after both signals are high at the same time. NAND gates  862  and  868  form a set-reset type latch. The latch gets “set” such that the output of NAND gate  862  is high when both the DATA and CK 2  signals are high. The latch gets “reset” such that the output of NAND gate  862  is low when both DATA and CK 2  are low. When the latch is “set” (i.e., both DATA and CK 2  are high), AND gates  870  and  874  are enabled. Once the AND gates  870  and  874  are enabled they can compare the falling edges of CK 2  and DATA to determine which signal goes low first. If DATA goes low first, then the SPEED-UP 1  signal will go high until CK 2  also goes low, indicating that oscillator  535  needs to oscillate faster in order to achieve phase alignment with the DATA signal. If the CK 2  signal goes low first then the SLOW-DOWN 1  signal will go high until DATA also goes low, indicating that oscillator  535  should oscillate slower in order to achieve phase alignment with the DATA signal. The SPEED-UP 1  and SLOW-DOWN 1  signals are connected to phase detector charge-pump  816 . 
   A preferred embodiment of frequency detector  818  is shown in FIG.  10 . The inputs to frequency detector  818  are the DATA and CK 4  signals and the outputs are the SPEED-UP 2  and SLOW-DOWN 2  signals. Delay cell  880  has its input connected to CK 4  and output connected to one input of NOR gate  882 . The delay cell  880  consists of an even number of capacitively loaded inverter stages or other delay generating circuitry and is well known in the art. The output of inverter  884  is connected to the other input of NOR gate  882  and the input of inverter  884  is connected to CK 4 . The output  886  of NOR gate  882  is reset pulse that occurs on the rising edge of CK 4 , and is connected to the reset input of D flip-flops  888 ,  890 , and  892 . The input of inverter  895  is connected to DATA. The output of inverter  895  is connected to the clock input of D flip-flops  888 ,  890 , and  892 . The D input of flip-flop  888  is connected to V DD . The D-input of flip-flop  890  is connected to the Q-output of flip-flop  888 . The D-input of flip-flop  892  is connected to the Q-output of flip-flop  890 . D flip-flops  894  and  896  have their clock inputs connected to CK 4 . The D input of flip-flop  894  is connected to the Q output of flip-flop  888 . The D-input of flip-flop  896  is connected to the Q-output of flip-flop  890 . The input of inverter  898  is connected to the Q-output of flip-flop  894 , and the output of inverter  898  is the SLOW-DOWN 2  signal. OR gate  900  provides the SPEED-UP 2  signal. One input of OR gate  900  is connected to the Q-output of flip-flop  896 , and the other input is connected to the Q-output of flip-flop  892 . The SPEED-UP 2  and SLOW-DOWN 2  signals are connected to the frequency-detector charge pump  824 . 
   The illustrated embodiment of frequency detector  818  counts the number of DATA pulses within one CK 4  cycle. The frequency of CK 4  should equal to the bit rate of the DATA pattern. Suitable encoding used for the DATA signal will ensure that there will be only one CK 4  rising edge for each data pulse falling edge, if the frequency of CK 4  is equal to the data rate. If the CK 4  frequency is equal to the data rate then the Q-output of flip-flop  888  will be high prior to each rising edge of CK 4  and the Q-outputs of flip-flops  890  and  892  will be low prior to each rising edge of CK 4 . If the Q-output of flip-flop  888  is low prior to the rising edge of CK 4  then the SLOW-DOWN 2  signal will go high for the duration of the next CK 4  cycle, signaling that oscillator  535  should slow down. If the Q-output of flip-flop  890  is high prior to the rising edge of CK 4 , then the SPEED-UP 2  signal will go high for the duration of the next CK 4  cycle signaling that the oscillator should speed up. 
   Another exemplary data coding scheme that may be used in an isolation system constructed in accordance with this invention is shown in FIG.  14 . In this scheme, each bit period  570  is split into four fields. The first field  572  is referred to as the clock field and is always high independent of the data being transferred. The second field  574 , which may occupy the second quarter of the bit period  570 , contains the forward-going (from transmit side to receive side) data bit. This data bit can be either the delta-sigma data bit or a control bit or any desired type of encoding bit, in accordance with the requirements of the application in which the invention is used. The third field  576 , which may occupy the third quarter of the bit period, is always low to ensure enough signal transitions to provide for power transmission in the forward path along with the first two fields, at least one of which is high in each bit period. The forward (transmit side) driver circuit is tri-stated during the fourth field  578 , thus allowing for data transmission in the opposite direction across the isolation capacitor. Of course, this particular coding scheme is provided as an example, and many other coding schemes may be devised that will be operable in the various embodiments of the present invention. 
   It is desirable to use the logic “1” that is present at the beginning of each bit period for clock recovery, since it is always present at periodic intervals. However, if the reverse data bit from the previous bit period is a one, the rising edge at the beginning of the next bit period will not be readily seen by a logic gate and therefore will not be, useful for clock recovery. To mitigate this effect and to allow reliable clock recovery, every fourth bit in the reverse field may be guaranteed to be zero by the encoding algorithms that are employed. The total frame length can be increased if more control bits need to be sent across the barrier in the reverse direction. Every fourth clock edge (the one associated with a zero in the previous reverse bit field ) may then be used for clock recovery. 
   A block diagram of an exemplary PLL circuit that can perform clock recovery in accordance with the coding scheme of  FIG. 14  is shown in FIG.  15 . The forward data (conveyed from the transmit side to the receive side) is connected to divide-by-four counter  800 . The output of counter  800  is connected to phase-frequency detector  801 . The output of phase-frequency detector  801  is connected to charge pump  802 . The output of charge pump  802  is connected to the input of loop filter  803 . The output of loop filter  803  is connected to the input of voltage controlled oscillator (VCO)  804 . The output of VCO  804  is the bit clock used for synchronizing the received data signal and for providing a clock signal to the receive side circuitry. The output of VCO  804  is also connected to the input of divide-by-four counter  805 . The output of counter  805  is connected to the other input of phase-frequency detector  801 . The phase-frequency detector  801  and the other circuits in the illustrated clock recovery circuit of  FIG. 15  are well known in the art, and the specific circuitry selected for a particular application would be a matter of routine design choice. 
     FIG. 16  is a block diagram showing DC holding circuitry  1600  according to the present invention located within phone line side circuitry  118  that may be part of direct access arrangement (DAA) circuitry, which may utilize the isolation barriers discussed above. The phone line side circuitry  118  communicates with the public phone system through lines  1602  and to the isolation barrier  120  through lines  124 . 
     FIG. 17  is a circuit diagram of DC holding circuitry  1600  with an external power dissipating resistor (R EXT )  1710  according to the present invention. Nodes  1722 ,  1726 ,  1728  and  1730  are connections external to the integrated circuit chip interface  1720 . External node  1728  is connected to internal node  1734 . External node  1726  is connected to internal node  1736 . A large transistor  1708  (M 1 ), which is a PMOS device in the embodiment depicted, has its gate connected to an operational amplifier (OPAMP)  1706 . The drain of transistor  1708  (M 1 ) is connected to external node  1722 , and its source is connected to internal node  1734 . The negative terminal of OPAMP  1706  is connected to internal node  1734  through voltage reference source (V 2 )  1705 , and the positive terminal of OPAMP  1706  is connected to internal node  1736 . Node  1734  is the positive voltage terminal of the internal CMOS power supply  1718 . The DC loop current  1702  is the current drawn by the DC holding circuitry  1600  and the other CMOS circuits connected to internal CMOS voltage supply  1718 . The power dissipating resistor  1710  (R EXT ) is connected between external node  1722  and the CMOS ground  1716  for the phone line side circuitry  118 . 
   Resistor  1704  (R 1 ) and a voltage reference source (V 1 )  1703  are connected between the internal node  1736  and the CMOS ground  1716 . It is noted that the resistor  1704  (R 1 ) and the voltage reference source (V 1 )  1703  may be implemented with a circuit which provides a Thevinin equivalent circuit, such as a current source connected in parallel with a resistor. Capacitor  1712  (C 1 ) is connected to external node  1726 , and resistor  1714  (R E ) is connected to external node  1728 . The other terminals of capacitor  1712  (C 1 ) and resistor  1714  (R E ) provide connections  1730  that may be connected to phone line interface circuitry. For example, connections  1730  may be separately coupled to two output nodes from bipolar hookswitch transistors configured as a Darlington transistor pair, as shown in Ser. No. 09/034,620, entitled “Caller ID Circuit Powered Through Hookswitch Devices” by Jeffrey W. Scott et al., filed concurrently herewith. Alternatively, connections  1730  may be coupled together to a single output node from a single bipolar hookswitch transistor. 
   The DC voltage inherent in the telephone line signal powers the CMOS integrated circuit that makes up the phone line side circuitry  118 . Connections  1730  are ultimately to a positive DC voltage of the phone line through additional phone line interface circuitry, such as a diode bridge, which may directly connect to the tip and ring lines of a telephone network. A conventional diode bridge may be used to make sure that the voltage supply provided to the devices within the phone line side circuitry  118  are powered by voltages of the correct polarity. The DC holding circuitry  1600  is powered by this voltage across external node  1730  and the CMOS ground  1716 . The rest of the CMOS circuits within the CMOS integrated circuit of the phone line side circuitry  118  are connected to and powered by the internal CMOS voltage supply  1718 . The internal CMOS power supply  1718  provides a DC supply voltage approximately equal the voltage reference source (V 1 )  1703  plus the voltage reference source (V 2 )  1705 , which may be for example about 4.0 volts. 
   Because the transistor  1708  (M 1 ) will sink a considerable amount of current, it may be implemented as a large MOS device, for example, a PMOS transistor with a W/L=6000/0.8 μm. In operation, the transistor  1708  (M 1 ) sinks the loop current not used by the rest of the CMOS integrated circuit attached to the DC power supply  1718 . The small resistor  1714  (R E ), which may be for example 51 Ω, establishes the correct DC current/voltage characteristics for phone line termination. The high pass filter formed by R 1  (which may be for example 70 kΩ) and C 1  (which may be for example approximately 0.47 μF) forces the voltage across and current through R E  to remain substantially constant at voiceband frequencies. The equivalent inductive characteristic resulting from R 1 , R E  and C 1  has a value given by L eq =R E ·C 1 ·R 1 . This equivalent inductor value (L eq ) is approximately 1.65 H for the example component values mentioned above. This provides the inductive behavior desired for DC termination of the phone lines. 
   In operation, the power dissipating resistor  1710  (R EXT ) diminishes the power dissipation burden of the CMOS circuits that make up the CMOS integrated circuit chip, which is within the chip interface lines  1720 . For example, assuming typical operating specifications, such as an internal DC power supply voltage  1718  of about 4.0 volts and a maximum DC loop current  1702  of about 100 mA, the power dissipated by the CMOS integrated circuit would be about 400 mW. Without resistor  1710  (R EXT ), most of this power would be dissipated on-chip by the transistor  1708  (M 1 ). In contrast, with the resistor  1710  (R EXT ) in place, much of this power is dissipated off-chip by the resistor  1710  (R EXT ). 
   In choosing a value for the resistor  1710  (R EXT ), consideration is given to the voltage requirements of the CMOS circuitry. Assuming a maximum signal swing of 1.5 volts peak on the power supply voltage applied to DC holding circuitry  1600 , the minimum instantaneous power supply voltage should be approximately 2.5 volts. Further assuming a 1.0 volt “on” voltage for the transistor  1708  (M 1 ) at a maximum expected DC loop current  1702  of about 100 mA, the resulting voltage that may appear across the resistor  1710  (R EXT ) is 1.5 volts. This voltage leads to a value for the external power dissipation resistor  1710  (R EXT ) of R EXT =V/I=1.5 V/100 mA=15 Ω. Thus, a 15 Ω value may be selected for the resistor  1710  (R EXT ) while still keeping the transistor  1708  (M 1 ) in its saturated “on” region under worst case signal swing conditions. Choosing this value for external resistor R EXT , the DC loop current power dissipation requirement of the CMOS integrated circuit is reduced from 400 mW to 250 mW at the maximum expected DC loop current  1702  of 100 mA. The 150 mW dissipated by resistor  1710  (R EXT ) represents a significant reduction in the power dissipation requirements of the transistor  1708  (M 1 ) without an appreciable increase in cost. 
     FIG. 18  is a circuit diagram of loop current monitor circuitry according to the present invention for the DC holding circuitry  1600  of  FIG. 17. A  MOS transistor (M L )  1802 , which is a PMOS device in the embodiment depicted, is connected in parallel with the transistor (M 1 )  1708 . The gate of the transistor (M L )  1802  is connected to the output of OPAMP  1706 , and the source of the transistor (M L )  1802  is connected to internal node  1734 . The drain of the transistor (M L )  1802  provides a current signal  1804 . The monitored DC loop current  1806  is preferably a known ratio (1:m) of the DC loop current  1702  flowing between internal node  1734  and internal node  1716 , which make up the internal CMOS power supply  1718 . The transistor (M L )  1802  may be a small MOS transistor sized to achieve the desired ratio, such that the current passing through the transistor (M L )  1802  is 1/m times the current passing through the transistor (M 1 )  1708 . Because the transistor (M L )  1802  and the transistor (M 1 )  1708  have the same gate-source (V GS ) voltage (assuming both transistors operate in the saturated mode), their relative source-drain currents will be in the ratio of the device sizes. For example, if transistor (M L )  1802  is sized at W/L=100/0.8 μm and the transistor (M 1 )  1708  is sized as above, the current ratio will be 1/m=1/60. 
   The drain current of the transistor (M L )  1802  may be used as a loop current monitor signal  1804  that is indicative of the DC loop current in the phone line. The loop current (I LOOP )  1702  is equal to the current (I M1 ) through the transistor (M 1 )  1708  plus the current (I OTHER ) through the internal voltage supply  1718 . This relationship may be represented by the equation I LOOP =I M1 +I OTHER . Substituting the current (I ML ) through the transistor (M L )  1802  as a measure of the current (I M1 ) through the transistor (M 1 )  1708 , the equation becomes I LOOP =(I ML /α)+I OTHER , where α=1/m. Although the current (I M1 ) through the transistor (M 1 )  1708  is not the entire DC loop current (I LOOP )  1702  because of the additional current (I OTHER ) drawn through the internal DC power supply voltage  1718  by the other CMOS circuitry, this additional current (I OTHER ) is typically small and known and may either be accounted for or ignored. In this way, the current (I ML ) through the transistor (M L )  1802  may be used as a measure of the DC loop current (I LOOP )  1702 . 
   Because a robust communication of signals across a capacitive isolation barrier prefers the signals to be in a digital format, the loop current monitor signal is preferably digitized by the CMOS integrated circuit prior to transmission of the information across the capacitive isolation barrier.  FIG. 19  is a block diagram of an analog-to-digital converter  1902  for converting the analog information from the loop current monitor circuitry of  FIG. 18  to digital information for transmission across the isolation barrier. The loop current monitor signal  1804  is received by an analog-to-digital converter (ADC)  1902 . The ADC  1902  may be a low resolution ADC, such as a 4-bit ADC, and have a DC reference current  1904  as an additional input. The ADC  1902  may also include, if desired, an off-set term to account for the current drawn by other CMOS circuitry through the internal voltage supply  1718  as mentioned above. 
   In operation, the ADC  1902  compares the loop current provided by the loop current monitor signal  1804  to the DC reference current  1904  and provides a digitized value of the DC loop current in the form of digital output  1906 . Once digitized, the loop current value may be transmitted across the isolation barrier as digital information. The loop current monitor circuitry of the present invention, therefore, allows for the phone line loop current to be directly measured, then digitized and sent across the isolation barrier. 
   Alternatively, the voltage across the external power dissipation resistor (R EXT )  1710  may be used as an indication of the DC loop current (I LOOP )  1702 . Because the value of the external resistor (R EXT )  1710  will likely be known, a measure of a voltage associated with this external resistor will provide an indication of the current through the transistor (M 1 )  1708 . This voltage may be used as the loop current monitor signal. In addition, if a voltage is used for the loop current monitor signal, the ADC  1902  may be designed to convert voltage values rather than current values to digital information for transmission across the isolation barrier. 
   Referring now to  FIG. 20 , a detailed circuit diagram is depicted for an embodiment of the ADC  1902  in FIG.  19 . The embodiment depicted is a low-precision analog successive approximation (SAR) analog-to-digital converter (ADC)  1902 . The analog SAR ADC  1902  may be used, for example, to convert the loop current monitor signal  1804  to digital information for transmission across the isolation barrier. It is noted that the input  1804  may be a current signal, such as that obtained from the drain of the MOS transistor (M L )  1802 , or a voltage signal, such as that associated with the external resistor (R EXT )  1710 . In the embodiment depicted, the input signal is a voltage signal. 
   The input signal (V IN )  1804  is supplied as an input to each of the comparators  2002 ,  2004 , and  2006 . These comparators have a single-bit digital output, with a logic “1” representing the condition when the input signal exceeds the input reference signal and a logic “0” representing the condition when the input signal does not exceed the input reference signal. The reference voltage inputs to these comparators are generated by the reference circuitry  2020 , which is connected between a reference voltage (V REF )  1904  and the CMOS ground  1716 . It is noted that the reference voltage (V REF )  1904  selected will likely depend upon the nature of the input signal provided to the analog SAR ADC  1902 . 
   In the embodiment depicted, reference circuitry  2020  includes eight matched resistors (R) connected in series and thereby provides evenly divided reference voltage outputs  2030 ,  2032 ,  2034 ,  2036 ,  2038 ,  2040 , and  2042 . In particular, reference voltage  2030  is (⅞)V REF , reference voltage  2032  is (¾)V REF , reference voltage  2034  is (⅝)V REF , reference voltage  2036  is (½)V REF , reference voltage  2038  is (⅜)V REF , reference voltage  2040  is ( 1/4 )V REF , and reference voltage  2042  is (⅛)V REF . Reference voltage  2036  is connected as the reference input to comparator  2002 . Reference voltages  2032  and  2040  are connected as inputs to multiplexer (MUX)  2008 . And reference voltages  2030 ,  2034 ,  2038 , and  2042  are connected as inputs to multiplexer (MUX)  2012 . 
   The comparators  2002 ,  2004  and  2006  are in effect connected in series to provide a 3-bit digital output. In the embodiment depicted, the output  1906   c  is the least-significant-bit (LSB) of a 3-bit ADC output  1906  of the low-precision analog SAR ADC  1902 . If desired, the reference circuitry  2020  may be expanded and additional MUXs and comparators may be added to increase the precision of the ADC  1902 . Similarly, the reference circuitry  2020  may be simplified and fewer MUXs and comparators may be used to reduce the precision of the ADC  1902 . 
   The output of comparator  2002  represents the most-significant-bit (MSB)  1906   a  of the output  1906  of ADC  1902 . This output is also provided as a control input to MUX  2008  and as a control input to MUX  2012 . In operation, if the input signal  1804  exceeds the reference voltage (½)V REF    2036 , then the output of comparator  2002  becomes a logic “1” and the reference voltage (¾)V REF    2032  is selected as the output  2010  of MUX  2008 . Otherwise, the output of comparator  2002  is a logic “0” and the reference voltage (¼)V REF    2040  is selected as the output  2010  of MUX  2008 . The output  2010  of MUX  2008  is then provided as the reference input to comparator  2004 . 
   The output of comparator  2004  represents the most-significant-bit less one (MSB−1)  1906   b  of the output  1906  of ADC  1902 . This output is also provided as the control input to MUX  2012 . In operation, if the input signal  1804  exceeds the reference input to comparator  2004 , then the output  1906   b  of comparator  2004  becomes a logic “1.” If the output  1906   a  of comparator  2002  was a logic “1,” then the reference voltage (⅞)V REF    2030  is selected as the output  2014  of MUX  2012 . If the output  1906   a  of comparator  2002  was a logic “0,” then the reference voltage (⅝)V REF    2034  is selected as the output  2014  of MUX  2012 . If the input signal  1804  does not exceed the reference input to comparator  2004 , then the output  1906   b  of comparator  2004  becomes a logic “0.” If the output  1906   a  of comparator  2002  was a logic “1,” then the reference voltage (⅜)V REF    2038  is selected as the output  2014  of MUX  2012 . If the output  1906   a  of comparator  2002  was a logic “0,” then the reference voltage (⅛)V REF    2042  is selected as the output  2014  of MUX  2012 . In other words, the output  1906   a  of comparator  2002  and the output  1906   b  of comparator  2004  act as a 2-bit selection signal controlling the output  2014  of comparator  2012 . The output  2014  of MUX  2012  is provided as the reference input to comparator  2006 . 
   The output of comparator  2006  represents the most-significant-bit less two (MSB−2)  1906   c  of the output  1906  of ADC  1902 . In operation, if the input signal  1804  exceeds the reference input to comparator  2006 , then the output  1906   c  of comparator  2006  becomes a logic “1.” Otherwise, the output  1906   c  of comparator  2006  becomes a logic “0.” 
   Turning now to  FIG. 21 , a detailed circuit diagram is depicted for an alternative embodiment for the ADC  1902  in FIG.  19 . As with  FIG. 20 , the embodiment depicted in  FIG. 21  is a low-precision analog successive approximation (SAR) analog-to-digital converter (ADC)  1902 . It is again noted that the input  1804  may be a current signal, such as that obtained from the drain of the MOS transistor (M L )  1802 , or a voltage signal, such as that associated with the external resistor (R EXT )  1710 . In the embodiment depicted, the input signal is a current signal. 
   The current input signal (I IN )  1804  is copied with current mirror devices  2112 ,  2114  and  2116  to each of the three stages. The reference current (I REF )  2108  is copied and scaled for each of the stages with device  2122  for the first stage, devices  2124  and  2126  for the second stage, and devices  2128 ,  2130  and  2132  for the third stage. The reference and input currents are summed together in each stage, depending upon the states of the switches  2136 ,  2138 , and  2139 . The voltage node (V MSB )  2140 , the voltage node (V MSB−1 )  2142 , and the voltage node (V MSB−2 )  2144  will either go to ground (GND)  1716  or to the supply voltage (V DD )  1734  depending upon the size of the input current (I IN )  1804  compared to the reference currents  2123 ,  2127  and  2133  in each stage. This allows simple CMOS inverters to be used for comparators  2102 ,  2104  and  2106 , which will have trip points roughly at V DD /2. The outputs of comparators  2102 ,  2104  and  2106  provide the output  1906  of ADC  1902 , which is a 3-bit output in the embodiment depicted. In addition, the output  1906   a  of the first stage is used as a control signal for switch  2136  in the second stage and for switch  2138  in the third stage, and the output  1906   b  of the second stage is used as a control signal for switch  2139  in the third stage. This circuitry can be extended or reduced depending upon the number of bits desired for the output  1906 . 
   The embodiment depicted in  FIG. 21  will now be described in more detail. The current input signal (I IN )  1804  is supplied as an input to the drain of an NMOS transistor  2110  having a width to length ratio of a selected value (Y), such that W/L=Y. The gate and drain of transistor  2110  are connected together. The gate of transistor  2110  is also connected to the gate of NMOS transistors  2112 ,  2114 , and  2116  through line  2118 , which also have a width to length ratio of W/L=Y. In this way, the current input signal (I IN )  1804  is mirrored for each stage and is coupled to the voltage node (V MSB )  2140  in the first stage, the voltage node (V MSB−1 )  2142  in the second stage, and the voltage node (V MSB−2 )  2144  in the third stage. The voltage nodes  2140 ,  2142 , and  2144  are connected, respectively, to comparators  2102 ,  2104 , and  2106 . These comparators have a single-bit digital output, with a logic “1” representing the condition when the input current signal exceeds the reference current signal and a logic “0” representing the condition when the input current signal does not exceed the reference current signal. The reference current signals are also connected to voltage nodes  2140 ,  2142 , and  2144 . 
   The reference current inputs are generated by reference current generation circuitry from the reference current (I REF )  2108 . The reference current (I REF )  2108  is connected between ground (GND)  1716  and the drain of PMOS transistor  2120 . The source of transistor  2120  is connected to the internal supply voltage (V DD )  1734 , and the gate of transistor  2120  is connected to its drain. The transistor  2120  may have a width to length ratio of a selected value (Z), such that W/L=Z. The gate of transistor  2120  is also connected to the gate of PMOS transistors  2122 ,  2124 ,  2126 ,  2128 ,  2130 , and  2132  through line  2134 . In this way, the reference current (I REF )  2108  is provided to each of the three subsequent stages. 
   The first stage reference current  2123  is generated from PMOS transistor  2122 , which has its source connected to the supply voltage (V DD )  1734  and its drain connected to the voltage node (V MSB )  2140 . The size of transistor  2122  is selected to be W/L=Z/2 so that the first stage current  2123  through transistor  2122  is equal to (½)I REF . If the input current (I IN )  1804  is greater than the first stage reference current  2123 , then the first stage voltage node (V MSB )  2140  will move towards ground. The output (MSB)  1906   a  of the CMOS inverter/comparator  2102  will then become a logic “1”. Conversely, if the input current (I IN )  1804  is less than the first stage reference current  2123 , then the first stage voltage node (V MSB )  2140  will move towards the supply voltage. The output (MSB)  1906   a  of the CMOS inverter/comparator  2102  will then become a logic “0”. The output (MSB)  1906   a  of the CMOS inverter/comparator  2102  is applied as a control to switch  2136  within the second stage circuitry and is applied as a control to switch  2138  within the second stage circuitry. 
   The second stage reference current  2127  is generated from PMOS transistor  2124 , PMOS transistor  2126 , and switch  2136 . Switch  2136  will be closed and allow current flow when the output (MSB)  1906   a  of CMOS inverter/comparator  2102  is a logic “1”. Transistor  2124  has its source connected to the supply voltage (V DD )  1734  through switch  2136  and its drain connected to the voltage node (V MSB−1 )  2142 . Transistor  2126  has its source connected to the supply voltage (V DD )  1734  and its drain connected to the voltage node (V MSB−1 )  2142 . The size of transistor  2124  is selected to be W/L=Z/2, and the size of transistor  2126  is selected to be W/L=Z/4. 
   In operation, if switch  2136  is closed, the second stage current  2127  connected to voltage node (V MSB−1 )  2142  will be equal to (½)I REF +(¼)I REF . Otherwise, the second stage current  2127  connected to voltage node (V MSB−1 )  2142  will be equal to (¼) I REF . If the input current (I IN )  1804  is greater than the second stage reference current  2127 , then the second stage voltage node (V MSB−1 )  2142  will move towards ground. The output (MSB−1)  1906   b  of the CMOS inverter/comparator  2104  will then become a logic “1”. Conversely, if the input current (I IN )  1804  is less than the second stage reference current  2127 , then the second stage voltage node (V MSB−1 )  2142  will move towards the supply voltage. The output (MSB−1)  1906   b  of the CMOS inverter/comparator  2104  will then become a logic “0”. The output (MSB−1)  1906   b  of the CMOS inverter/comparator  2104  is applied as a control to switch  2139  within the third stage circuitry. 
   The third stage reference current  2133  is generated from PMOS transistor  2128 , PMOS transistor  2130 , PMOS transistor  2132 , and switches  2136  and  2139 . Switch  2138  will be closed and allow current flow when the output (MSB)  1906   a  of CMOS inverter/comparator  2102  is a logic “1”. Switch  2139  will be closed and allow current flow when the output (MSB−1)  1906   b  of CMOS inverter/comparator  2104  is a logic “1”. Transistor  2128  has its source connected to the supply voltage (V DD )  1734  through switch  2138  and its drain connected to the voltage node (V MSB−2 )  2144 . Transistor  2130  has its source connected to the supply voltage (V DD )  1734  through switch  2139  and its drain connected to the voltage node (V MSB−2 )  2144 . Transistor  2132  has its source connected to the supply voltage (V DD )  1734  and its drain connected to the voltage node (V MSB−2 )  2144 . The size of transistor  2128  is selected to be W/L=Z/2. The size of transistor  2130  is selected to be W/L=Z/4. And the size of transistor  2132  is selected to be W/L=Z/8. 
   In operation, if switches  2138  and  2139  are closed, the third stage current  2133  connected to voltage node (V MSB−2 )  2144  will be equal to (½)I REF +(¼)I REF +(⅛)I REF . If switch  2138  is closed and switch  2139  is open, the third stage current  2133  connected to voltage node (V MSB−2 )  2144  will be equal to (½)I REF +(⅛)I REF . If switch  2138  is open and switch  2139  is closed, the third stage current  2133  connected to voltage node (V MSB−2 )  2144  will be equal to (¼)I REF +(⅛)I REF . Finally, if both switches  2138  and  2139  are open, the third stage current  2133  connected to voltage node (V MSB−2 )  2144  will be equal to (⅛)I REF . If the input current (I IN )  1804  is greater than the third stage reference current  2133 , then the third stage voltage node (V MSB−2 )  2144  will move towards ground. The output (MSB−2)  1906   c  of the CMOS inverter/comparator  2106  will then become a logic “1”. Conversely; if the input current (I IN )  1804  is less than the third stage reference current  2133 , then the third stage voltage node (V MSB−2 )  2144  will move towards the supply voltage. The output (MSB−2)  1906   c  of the CMOS inverter/comparator  2106  will then become a logic “0”. 
   In the embodiment depicted, the output  1906  of ADC  1902  is a 3-bit value and the current reference circuitry provide eight possible current reference levels. The output of comparator  2102  represents the most-significant-bit (MSB)  1906   a  of the output of ADC  1902 . The output of comparator  2104  represents the most-significant-bit less one (MSB−1)  1906   b  of the output  1906  of ADC  1902 . And The output of comparator  2106  represents the most-significant-bit less two (MSB−2)  1906   c  of the output  1906  of ADC  1902 . It is noted that additional stages may be added or removed as desired, with respective changes to the current reference generation circuitry, to achieve more or less resolution in the SAR ADC  1902 . In other words, a desired N-bit output value may be implemented with N stages providing 2 N  possible current reference levels. 
   Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. It is to be understood that the forms of the invention herein shown and described are to be taken as the presently preferred embodiments. Various changes may be made in the shape, size and arrangement of parts. For example, equivalent elements may be substituted for those illustrated and described herein, and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention.