PATENT ABSTRACT
An emitter-follower bias circuit supplying a bias voltage to the base of an amplification transistor includes: a depletion mode FET boosting a reference voltage; and an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET.

PATENT DESCRIPTION
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an emitter-follower type bias circuit supplying a bias voltage to a base of an amplification transistor, and in particular to an emitter-follower type bias circuit which can operate at a low reference voltage. 
     2. Background Art 
     Currently, GaAs-HBT power amplifiers are increasingly being used for CDMA-based cellular phones, wireless LAN or the like (e.g., see Japanese Patent Laid-Open No. 2004-343244). 
     Conventional power amplifiers receive a reference voltage from outside as input. Since the reference voltage determines an idle current of each power amplifier, the reference voltage needs to be kept constant with high accuracy (e.g., on the order of 2.85 V±0.1 V) irrespective of any variation in a power supply voltage. There is a demand in recent years that a reference voltage should be generated inside the power amplifier. In this case, the reference voltage is generated inside the power amplifier in response to an enable signal (a digital signal to turn ON/OFF the power amplifier) given from outside. 
     Furthermore, there is also a demand in recent years that an enable signal should be generated at a lower voltage. That is, power amplifiers are conventionally operated with an enable signal on the order of 2.6 V, but it is only recently that power amplifiers are required to be operated with an enable signal on the order of 1.4 V. 
     SUMMARY OF THE INVENTION 
     When a reference voltage generation circuit using a GaAs-based BiFET (HBT+FET) process is designed such that a reference voltage rises with a low enable signal, the reference voltage outputted by the reference voltage generation circuit is lower. When, for example, the enable signal is on the order of 1.4 V, the reference voltage is on the order of 2 V. However, conventional emitter-follower type bias circuits require a reference voltage of at least on the order of 2.7 V and there is a problem that the bias circuits cannot be driven at such a low reference voltage. 
     In view of the above-described problems, an object of the present invention is to provide an emitter-follower type bias circuit which can operate at a low reference voltage. 
     According to the present invention, an emitter-follower type bias circuit supplying a bias voltage to a base of an amplification transistor, comprises: a depletion mode FET boosting a reference voltage; and an emitter-follower circuit generating the bias voltage according to the reference voltage boosted by the depletion mode FET. 
     The present invention makes it possible to operate at a low reference voltage. 
     Other and further objects, features and advantages of the invention will appear more fully from the following description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating a power amplifier according to First embodiment. 
         FIG. 2  is a diagram illustrating an emitter-follower type bias circuit according to First embodiment. 
         FIG. 3  is a diagram illustrating a reference voltage generation circuit according to First embodiment. 
         FIG. 4  is a diagram illustrating enable voltage dependency of the reference voltage generated by the reference voltage generation circuit in  FIG. 3 . 
         FIG. 5  is a diagram illustrating the emitter-follower type bias circuit according to Second embodiment. 
         FIG. 6  is a diagram illustrating the emitter-follower type bias circuit according to Third embodiment. 
         FIG. 7  is a diagram illustrating an idle current of an amplification transistor to which the bias circuit in  FIG. 6  is applied. 
         FIG. 8  is a diagram illustrating the emitter-follower type bias circuit according to Fourth embodiment. 
         FIG. 9  is a diagram illustrating the emitter-follower type bias circuit according to Fifth embodiment. 
         FIG. 10  is a diagram illustrating the emitter-follower type bias circuit according to Six embodiment. 
         FIG. 11  is a diagram illustrating the emitter-follower type bias circuit according to Seventh embodiment. 
         FIG. 12  is a diagram illustrating the emitter-follower type bias circuit according to Eighth embodiment. 
         FIG. 13  is a diagram illustrating the emitter-follower type bias circuit according to Ninth embodiment. 
         FIG. 14  is a diagram illustrating the emitter-follower type bias circuit according to Tenth embodiment. 
         FIG. 15  is a diagram illustrating a reference voltage generation circuit according to Tenth embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First Embodiment 
       FIG. 1  is a diagram illustrating a power amplifier according to First embodiment. This power amplifier is a two-stage amplifier formed through a BiFET process whereby an HBT and an FET are formed on the same substrate. 
     A GaAs chip is shown enclosed by a dotted-line frame and circuit elements outside the dotted-line frame are formed of chip parts and lines on a module substrate. A Tr 1  which is a first-stage amplification element that amplifies an input signal and a Tr 2  which is a second-stage amplification element that amplifies an output signal of the Tr 1  are formed on the same GaAs substrate. The Tr 1  and Tr 2  are GaAs-HBTs (heterojunction bipolar transistors). 
     A Bias 1  is a first-stage bias circuit that supplies a bias current to the base of the Tr 1  and a Bias 2  is a second-stage bias circuit that supplies a bias current to the base of the Tr 2 . An IN is an RF signal input terminal, an OUT is an RF output signal terminal, R 2  to R 4  are resistors, C 1  to C 10  are capacitors, and L 1  and L 2  are inductors. L 3  to L 8  are lines having specific electric lengths and operate as inductors. A Vc 1  is a collector power supply terminal for the Tr 1 , a Vc 2  is a collector power supply terminal for the Tr 2 , a Vcb is a power supply terminal of the Bias 1  and Bias 2 , and a Vref is a terminal that applies a reference voltage to the Bias 1  and Bias 2 . 
     The C 3 , C 4  and L 2  constitute an inter-section matching circuit connected between the drain of the Tr 1  and the base of the Tr 2 . Recently, the C 1 , C 2  and L 1  constituting an input matching circuit, and C 3 , C 4  and L 2  constituting the inter-section matching circuit are also often integrated on the GaAs chip to reduce the size of the module. 
       FIG. 2  is a diagram illustrating an emitter-follower type bias circuit according to First embodiment. Here, the first-stage bias circuit will be described, but the same will apply to the circuit configuration of the second-stage bias circuit, too. 
     An Fdb 1  is a depletion mode PET, an Feb 1  is an enhancement mode FET, Trb 1  to Trb 5  are GaAs-HBTs, Rbb 1  to Rbb 7  are resistors and a Ven is a terminal to which an enable signal is inputted. 
     The drain of the Fdb 1  is connected to a power supply terminal Vcb, the gate of the Fdb 1  is connected to a terminal Vref. The collector of the Trb 1  is connected to the power supply terminal Vcb and the base of the Trb 1  is connected to the source of the Fdb 1  via the Rbb 1  and the emitter of the Trb 1  is connected to the base of the Tr 1  via the Rbb 2 . The collector of the Trb 2  is connected to the emitter of the Trb 1  via the Rbb 3  and the emitter of the Trb 2  is grounded. The collector of the Trb 3  is connected to the power supply terminal Vcb via the Rbb 4  and the base of the Trb 3  is connected to the base of the Trb 1  and the Rbb 1  via the Rbb 5 . The emitter of the Trb 3  is connected to the base of the Trb 2 . 
     The drain of the Feb 1  is connected to the emitter of the Trb 3  via the Rbb 6 , the gate of the Feb 1  is connected to the terminal Ven via the Rbb 7  and the source of the Feb 1  is grounded. The base and collector of the Trb 4  are connected to the base of the Trb 1  and the Rbb 1 . The base and collector of the Trb 5  are connected to the emitter of the Trb 4  and the emitter of the Trb 5  is grounded. 
     The Fdb 1  boosts a reference voltage inputted from the terminal Vref. The emitter-follower circuit generates a bias voltage according to the reference voltage boosted by the Fdb 1 . The emitter-follower circuit operates so that an idle current of the Tr 1  (bias current when no RP signal is inputted) is kept constant irrespective of any temperature variation. 
       FIG. 3  is a diagram illustrating a reference voltage generation circuit according to First embodiment. This reference voltage generation circuit is integrated on the same GaAs chip as the above described bias circuit using a BiFET process. Furthermore, this reference voltage generation circuit can operate with a low enable signal on the order of 1.4 V. 
     Fgd 1  to Fgd 3  are depletion mode FETs, Fge 1  and Fge 2  are enhancement mode FETs, Rg 1  to Rg 5  are resistors, Dg 1  and Dg 2  are Schottky barrier diodes, a Vcg is a terminal to which a power supply voltage (normally on the order of 3.4 V) is applied. 
     The drain of the Fgd 1  is connected to the terminal Vcg and the gate of the Fgd 1  is connected to the terminal Ven via the Rg 1 . The drain of the Fdg 2  is connected to the source of the Fgd 1 , the gate of the Fdg 2  is connected to one end of the Rg 2  and the source of the Fdg 2  is connected to the other end of the Rg 2 . 
     The drain of the Fge 1  is connected to one end of the Rg 2  via the Rg 3 , the drain of the Fgd 3  is connected to the terminal Vcg, the gate of the Fgd 3  is connected to the source of the Fgd 2  via the Rg 4 . The source of the Fdg 3  is connected to the gate of the Fge 1 , the drain and gate of the Fge 2  via the Dg 1  and the Rg 5 . The source of the Fge 1  and the source of the Fge 2  are grounded via the Dg 2 . 
     In this reference voltage generation circuit, the Fgd 1  functions as a switch to turn ON/OFF the reference voltage generation circuit. The source voltage of the Fdg 2  is outputted as a reference voltage. 
       FIG. 4  is a diagram illustrating enable voltage dependency of the reference voltage generated by the reference voltage generation circuit in  FIG. 3 . A Ven′ represents a minimum enable voltage to output a desired reference voltage Vref′. 
     Since the source voltage of the Fgd 1  (drain voltage of the Fgd 2 ) changes with the enable voltage, the source voltage (reference voltage) of the Fgd 2  is limited by the enable voltage in a low enable voltage region. Therefore, when the reference voltage is made to rise at a lower enable voltage Ven″ (Ven′→Ve″), the reference voltage is lowered (Vref′→Vref″). When, for example, the circuit is made to operate at an enable voltage on the order of 1.4 V, the reference voltage is approximately on the order of 2 V. However, a reference voltage of at least on the order of 2.7 V is necessary to drive the conventional emitter-follower type bias circuit. Therefore, the reference voltage generation circuit in  FIG. 3  cannot drive the conventional emitter-follower type bias circuit. 
     By contrast, the emitter-follower type bias circuit in  FIG. 2  can be driven even by the reference voltage generation circuit in  FIG. 3 . Hereinafter, the operation of the emitter-follower type bias circuit in  FIG. 2  will be described. 
     The reference voltage generated by the reference voltage generation circuit in  FIG. 3  is inputted to the gate of the Fdb 1 . The gate-source voltage of the Fdb 1  is determined according to a current Iref that flows into the emitter-follower circuit. Since the Fdb 1  is a depletion mode FET, the source has a higher voltage than the gate. When, for example, a threshold voltage is on the order of −0.9 V, the voltage at point A is higher than the gate voltage (reference voltage) of the Fdb 1  by on the order of 0.8 V. 
     When the reference voltage generated by the reference voltage generation circuit in  FIG. 3  is assumed to be on the order of 2 V, the voltage inputted to the emitter-follower circuit (voltage at point A) is on the order of 2.8 V and can drive the emitter-follower circuit. Thus, the Fdb 1  plays a role of boosting the reference voltage. Therefore, the emitter-follower type bias circuit according to the present embodiment can operate at a lower reference voltage than the conventional one. That is, the emitter-follower type bias circuit can be combined with the reference voltage generation circuit in  FIG. 3  that can operate with a low enable signal. 
     Furthermore, when the enable voltage is 0 V (shut down state), the output voltage (reference voltage) of the reference voltage generation circuit does not become 0 V and a residual voltage of a little less than 1 V is generated. The emitter-follower type bias circuit does not normally operate at this reference voltage. However, if no Feb 1  exists, a minimal leakage current Ibb 1  is generated. The Feb 1  turns ON when the enable voltage is higher than a threshold voltage of the Feb 1  (during operation) and turns OFF when the enable voltage is lower than the threshold voltage of the Feb 1  (at the time of shut down), and can thereby suppress leakage current. 
     Second Embodiment 
     An emitter-follower type bias circuit according to Second embodiment will be described with reference to the attached drawing. Components similar to or corresponding to those in First embodiment will be assigned the same reference numerals and descriptions thereof will be omitted. 
       FIG. 5  is a diagram illustrating the emitter-follower type bias circuit according to Second embodiment. Fdb 1 A and Fdb 1 B are depletion mode FETs, VrefA and VrefB are terminals to which reference voltages are applied and Rbb 1 A and Rbb 1 B are resistors. Unlike First embodiment, the bias circuit according to the present embodiment has two reference voltage input systems. 
     The Rbb 1 A and Rbb 1 B have different resistance values and, for example, the resistance value of the Rbb 1 B is greater than the resistance value of the Rbb 1 A. Complementary reference voltages are inputted to the terminal VrefA and the terminal VrefB. The Fdb 1 A boosts a first reference voltage inputted from the terminal VrefA. The Fdb 1 B boosts a second reference voltage inputted from the terminal VrefB. The boosted first reference voltage is inputted to the emitter-follower circuit via the Rbb 1 A and the boosted second reference voltage is inputted to the emitter-follower circuit via the Rbb 1 B. 
     When a high level reference voltage is inputted to the terminal VrefA and a low level reference voltage (=0 V) is inputted to the terminal VrefB, the Fdb 1  operates and the Fdb 2  turns OFF, and therefore the resistor corresponding to the Rbb 1  of First embodiment is the Rbb 1 A (small resistance value). On the other hand, when a low level reference voltage (=0 V) is inputted to the terminal VrefA and a high level reference voltage is inputted to the terminal VrefB, the Fdb 1  turns OFF and the Fdb 2  operates, and therefore the resistor corresponding to the Rbb 1  of First embodiment is the Rbb 1 B (large resistance value). 
     In the present embodiment, any one of the Rbb 1 A and Rbb 1 B of different resistance values can be selected and therefore the idle current of the Tr 1  can be changed. Although the present embodiment assumes that the same high level voltage is inputted to the terminal VrefA and the terminal VrefB, an equivalent effect can also be obtained even when different high level voltages are inputted. 
     Third Embodiment 
     An emitter-follower type bias circuit according to Third embodiment will be described with reference to the attached drawings. Components similar to or corresponding to those in first and second embodiments will be assigned the same reference numerals and descriptions thereof will be omitted. 
       FIG. 6  is a diagram illustrating the emitter-follower type bias circuit according to Third embodiment. Trb 6  to Trb 9  are transistors, RbbB to Rbb 13  are resistors and a Vx is a terminal to which an external voltage is applied. The present embodiment corresponds to the bias circuit of Second embodiment plus a circuit that internally generates gate voltages of the Fdb 1  and Fdb 2  (two complementary reference voltages) from one reference voltage based on an external voltage added to the terminal Vx. 
       FIG. 7  is a diagram illustrating an idle current of an amplification transistor to which the bias circuit in  FIG. 6  is applied. The external voltage applied to the terminal Vx only causes the Trb 6  and Trb 7  to turn ON/OFF, and therefore need not be as accurate as the reference voltage. Two states of idle current can be created by only applying one voltage to the terminal Vx. 
     Fourth Embodiment 
     An emitter-follower type bias circuit according to Fourth embodiment will be described with reference to the attached drawing. Components similar to or corresponding to those in first and second embodiments will be assigned the same reference numerals and descriptions thereof will be omitted. 
       FIG. 8  is a diagram illustrating the emitter-follower type bias circuit according to Fourth embodiment. Fdb 3  and Fdb 4  are depletion mode FETs and VxA and VxB are terminals to which an external voltage is applied. The present embodiment corresponds to the bias circuit of Second embodiment with Fdb 2 A and Fdb 2 B added to the drains of the Fdb 1 A and Fdb 1 B. 
     By applying a voltage to the terminals VxA and VxB and causing the Fdb 2 A and Fdb 2 B to turn ON/OFF, it is possible to control whether or not to operate the Fdb 1 A and Fdb 1 B respectively and select any one of Rbb 1 A and Rbb 1 B of different resistance values. The voltage applied to the terminals VxA and VxB only causes the Fdb 2 A and Fdb 2 B to turn ON/OFF and therefore need not be as accurate as the reference voltage applied to the terminals VrefA and VrefB of Second embodiment. 
     Fifth Embodiment 
     An emitter-follower type bias circuit according to Fifth embodiment will be described with reference to the attached drawing. Components similar to or corresponding to those in First embodiment will be assigned the same reference numerals and descriptions thereof will be omitted. 
       FIG. 9  is a diagram illustrating the emitter-follower type bias circuit according to Fifth embodiment. An Fdb 5  is a depletion mode FET, an Rbb 14  is a resistor and a Vy is an external power supply. The present embodiment corresponds to the bias circuit of First embodiment plus a function capable of turning ON/OFF the bias circuit using the external power supply Vy. 
     The Fdb 5  is a switch for controlling whether or not to connect the Fdb 1  and the emitter-follower circuit according to an external voltage. When the Fdb 5  is ON, a reference voltage is supplied to the emitter-follower circuit but no reference voltage is supplied when the Fdb 5  is OFF. Therefore, it is possible to turn ON/OFF the idle current of the Tr 1 . As described in First embodiment, since the voltage at point A is on the order of 2.8 V, the external voltage necessary to turn ON the Fdb 5  is on the order of 2.8 V. 
     Six Embodiment 
     An emitter-follower type bias circuit according to Six embodiment will be described with reference to the attached drawing. Components similar to or corresponding to those in First embodiment will be assigned the same reference numerals and descriptions thereof will be omitted. 
       FIG. 10  is a diagram illustrating the emitter-follower type bias circuit according to Six embodiment. The present embodiment corresponds to the emitter-follower circuit of First embodiment with the Trb 2 , Trb 3 , Rbb 3  to Rbb 7  and Feb 1  removed. These removed parts play a role of reducing a temperature variation of the idle current. Therefore, the temperature variation of the idle current increases in the present embodiment, but since the number of components of the bias circuit is drastically reduced, the chip size can be reduced. Furthermore, since no enhancement mode FET is used, it is possible to reduce an idle current variation caused by a manufacturing variation of the enhancement mode FET. 
     Seventh Embodiment 
     An emitter-follower type bias circuit according to Seventh embodiment will be described with reference to the attached drawing. Components similar to or corresponding to those in First embodiment will be assigned the same reference numerals and descriptions thereof will be omitted. 
       FIG. 11  is a diagram illustrating the emitter-follower type bias circuit according to Seventh embodiment. A Trb 10  is a transistor. The present embodiment corresponds to the bias circuit of First embodiment with the Feb 1  replaced by the Trb 10 . 
     The Trb 10  suppresses a leakage current as in the case of the Feb 1  of First embodiment. Since the bias circuit can be configured without using any enhancement mode FET, it is possible to suppress manufacturing variations or costs caused by the enhancement mode FET. 
     Eighth Embodiment 
     An emitter-follower type bias circuit according to Eighth embodiment will be described with reference to the attached drawing. Components similar to or corresponding to those in First embodiment will be assigned the same reference numerals and descriptions thereof will be omitted. 
       FIG. 12  is a diagram illustrating the emitter-follower type bias circuit according to Eighth embodiment. Trb 11  and Trb 12  are transistors, Rbb 15  to Rbb 18  are resistors and Feb 2  is an enhancement mode FET. 
     The collector of the Trb 11  is connected to the power supply terminal Vcb. The base of the Trb 11  is connected to the output terminal of the Fdb 1  via Rbb 15 . The collector of the Trb 12  is connected to the output terminal of the Fdb 1  via the Rbb 16 . The base of the Trb 12  is connected to the emitter of the Trb 11 . The emitter of the Trb 12  is grounded. The drain of the Feb 2  is connected to the emitter of the Trb 11  via the Rbb 17 , the gate is connected to the terminal Ven via the Rbb 18  and the source is grounded. 
     When the voltage at point A increases, the base voltage of the Trb 11  increases, and therefore the collector current of the Trb 11  increases. Therefore, since the base voltage of the Trb 12  increases, the collector current of the Trb 12  increases. Furthermore, since the collector of the Trb 12  is connected to point A via the resistor Rbb 16 , the drain current of the Fdb 1  increases and the source voltage of the Fdb 1  (voltage at point A) decreases. 
     Since the circuit added in the present embodiment provides feedback for a voltage variation at point A, it is possible to reduce variations of idle current irrespective of any variation in the reference voltage and threshold voltage of the Fdb 1  or the like. 
     Ninth Embodiment 
     An emitter-follower type bias circuit according to Ninth embodiment will be described with reference to the attached drawing. Components similar to or corresponding to those in first and eighth embodiments will be assigned the same reference numerals and descriptions thereof will be omitted. 
       FIG. 13  is a diagram illustrating the emitter-follower type bias circuit according to Ninth embodiment. Trb 13  and Trb 14  are transistors, an Fdb 6  is a depletion mode FET, an Feb 3  is an enhancement mode FET, Rbb 19  to Rbb 22  are resistors and a Db 1  is a Schottky barrier diode. 
     The drain of the Fdb 6  is connected to the power supply terminal Vcb, the gate and source of the Fdb 6  are mutually connected via the Rbb 19 . The collector and base of the Trb 13  are connected to the source of the Fdb 6  and the emitter is grounded via the Feb 3 . The Rbb 20  is connected between the collector and the emitter of the Trb 13 . 
     The collector of the Trb 14  is connected to the output terminal of the Fdb 1  via the Rbb 1 , Rbb 21  and Db 1 . The base of the Trb 14  is connected to the base of the Trb 13  and the emitter is grounded via the Feb 3 . The gate of the Feb 3  is connected to the terminal Ven via the Rbb 22 . 
     When a threshold voltage of the depletion mode FET deepens, the output voltage of the Fdb 1  increases, but at the same time the drain current of the Fdb 6  also increases. Therefore, the collector current of the Trb 13  also increases. Furthermore, since the base of the Trb 14  is connected to the base of the Trb 13 , the collector current of the Trb 14  also increases. Accordingly, the voltage effect at the Rbb 1  increases and the base voltage of the Trb 1  decreases. Thus, the idle current of the Tr 1  decreases. 
     Since the circuit added in the present embodiment functions in the direction of canceling a variation of the idle current against a variation in the threshold voltage of the depletion mode FET, it is possible to reduce an idle current variation due to a manufacturing variation in the threshold voltage. 
     Tenth Embodiment 
     An emitter-follower type bias circuit and a reference voltage generation circuit according to Tenth embodiment will be described with reference to the attached drawings. Components similar to or corresponding to those in First embodiment will be assigned the same reference numerals and descriptions thereof will be omitted. 
       FIG. 14  is a diagram illustrating the emitter-follower type bias circuit according to Tenth embodiment. Fdb 7  and Fdb 8  are depletion mode FETs and an Rbb 23  is a resistor. The drain of the Fdb 7  is connected to the power supply terminal Vcb. The drain of the Fdb 8  is connected to the gate and source of the Fdb 7 . The gate of the Fdb 8  is connected to the terminal Ven via the Rbb 23  and the source of the Fdb 8  is connected to the base of the Trb 10 . The circuit added in the present embodiment is a level shift circuit for an enable voltage. This allows the circuit to operate at a lower enable voltage than the threshold voltage of the Trb 10 . 
       FIG. 15  is a diagram illustrating a reference voltage generation circuit according to Tenth embodiment. Fgd 4  to Fgd 6  are depletion mode FETs, Trg 1  to Trg 3  are transistors and Rg 5  to Rg 7  are resistors. The Trg 3  functions to suppress a leakage current as in the case of the Trb 13  of Ninth embodiment. The Fgd 5  is disposed between the terminal Ven and the base of the Trg 3  so as to be able to operate at a low enable voltage as in the case of the Fdb 8  in  FIG. 14 . 
     Although the circuit scale is larger than First embodiment, the reference voltage generation circuit according to the present embodiment has a circuit configuration without using any enhancement mode FET. Therefore, with the power amplifier incorporating the reference voltage generation circuit, it is possible to suppress any manufacturing variation and manufacturing cost caused by the enhancement mode FET. 
     Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described. 
     The entire disclosure of a Japanese Patent Application No. 2010-021073, filed on Feb. 2, 2010 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.