PATENT ABSTRACT
A pattern forming method of forming a desired pattern on a semiconductor substrate is disclosed, which comprises extracting a first pattern of a layer, extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern, calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation, determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns, and correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin.

PATENT DESCRIPTION
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2003-110254, filed Apr. 15, 2003, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a mask pattern. In particular, the present invention relates to a pattern forming method and system, which are suitable for forming patterns having a sufficient process margin, and to a method of manufacturing a semiconductor device using the pattern forming method. 
         [0004]    2. Description of the Related Art 
         [0005]    Recently, high integration and high-speed performance of semiconductor devices have advanced. For this reason, the requirements for pattern formation of semiconductor integrated circuits are very severe. 
         [0006]    In semiconductor integrated circuits, the design rule representing the design and manufacture minimum line width becomes narrow with the improvement of nano-fabrication techniques. At present, semiconductor integrated circuits having a line width of less than 100 nm are manufactured. 
         [0007]    If a range satisfying the foregoing design rule is given, designers can freely make a design of the circuit pattern. 
         [0008]    Semiconductor integrated circuits are manufactured by etching various material films formed on a semiconductor substrate using resist patterns formed by a lithography technique as masks. For this reason, predetermined rule (pattern rule) is required in the pattern critical dimensions of each exposure mask and relative pattern critical dimensions between exposure masks. 
         [0009]    For example, when the layout of the semiconductor integrated circuits is designed, the following matters are determined as the pattern arrangement rule. One is the minimum processing dimension, and another is dimension change (difference in processing conversion) before and after processing. Another is alignment accuracy when overlapping different exposure masks. 
         [0010]    However, the circuit pattern is micronized, thereby influencing the semiconductor device characteristic resulting from the following reason. The pattern formed on the exposure mask is transferred onto the semiconductor substrate in the lithography process in the manufacture of semiconductor devices. In this case, deviation is given due to optical proximity effect (OPE) between design dimension and actual dimension when transferred onto the semiconductor substrate. 
         [0011]    For example, even if the pattern satisfies the design rule, the acute portion of the pattern is not fully transferred; as a result, it becomes round. In addition, line dimension changes due to isolated and nested distribution of the line pattern. 
         [0012]    In order to correct the deviation, the following method, that is, the optical proximity correction (OPC) technique, has been known. According to the OPC technique, the pattern critical dimensions on the exposure mask are corrected using optical simulation. For example, the pattern width is partially thickened, or a dummy pattern is provided. 
         [0013]    However, the OPC technique corrects the pattern critical dimensions on the exposure mask so that the pattern formed on the semiconductor substrate is formed as design pattern critical dimensions. Thus, the OPC technique is not suitable for increasing the process margin in the lithography process. 
         [0014]    Consequently, the OPC technique is not effective with respect to a patterns having process margin, which does not satisfy the reference value. The process margin shows an allowable range where the pattern is formed based on the dimensions having no problem on the semiconductor device characteristic even if the following condition is given. The condition is that exposure parameters, for example, exposure and focal length vary from their proper value when the pattern is transferred onto the semiconductor substrate. 
         [0015]    The pattern forming method to solve the foregoing problem is disclosed in JPN. PAT. APPLN. KOKAI Publication No. 2002-131882 (pages 5 to 8, FIG. 2), for example. 
         [0016]    The pattern forming method disclosed in the Publication No. 2002-131882 will be explained with reference to  FIG. 17  to  FIG. 20 .  FIG. 17  is a flowchart to explain the pattern forming method.  FIG. 18  is a view showing the layout before circuit patterns are corrected.  FIG. 19  is a layout view showing circuit the patterns of maximum and minimum line dimension when conditions such as an exposure amount and a focal length are varied to the circuit patterns shown in  FIG. 18 .  FIG. 20  a view showing the layout after the circuit patterns shown in  FIG. 18  are corrected. 
         [0017]    As shown in  FIG. 18  to  FIG. 20 , the pattern is composed of lines and spaces. More specifically, patterns  102  to  104  are arranged in parallel on an exposure mask  101 . The pattern  102  has a line dimension L 1 . The pattern  103  has a line dimension L 2 , and is formed via a space dimension S 1 . The pattern  104  has a line dimension L 3 , and is formed via a space dimension S 2 . 
         [0018]    First, the design pattern data is read from a data recorder, and a process margin is obtained from the relation between lines and spaces. Thereafter, the pattern having process margin, which does not satisfy the reference value, is extracted from the design pattern. 
         [0019]    More specifically, lithography simulation is carried out while changing the exposure and focal length by predetermined ratio. By doing so, variables δ 1  to δ 3  of line dimensions L 1  to L 3  of patterns  102  to  104  are determined. 
         [0020]    In the foregoing Publication No. 2002-131882, it is determined that δ 2  and δ 3  are larger than δ 1 , and each process margin of patterns  103  and  104  does not satisfy the reference value (step S 101 ). 
         [0021]    The pattern is corrected so that the process margin satisfies the reference value (step. S 102 ). More specifically, both edges  103   a  and  103   b  of the pattern  103  are shifted to their sides so that the line dimension L 2  is widened to L 2 ′. An edge  104   a  of the pattern  104  is shifted to the side so that the line dimension L 3  is widened to L 3 ′. 
         [0022]    The pattern is corrected, and thereafter, a check is made whether or not the pattern pitch is kept constant (step S 103 ). 
         [0023]    If the pattern pitch is not kept constant, the procedure returns to step S 102 , and then, the pattern is again corrected in the following manner. Space dimensions S 1  and S 2  are narrowed down to S 1 ′ and S 2 ′ in accordance with the line dimension correction so that the pattern pitch before and after correction is kept constant. 
         [0024]    Then, it is determined whether or not the wiring capacitance of the corrected pattern is in an allowable range (step S 104 ). This is because the following matter is taken into consideration. In correcting the process margin of the pattern, the line dimension is widened, and thereby, there is a possibility described below. Parasitic capacitance (wiring capacitance) generated between top and bottom layers exceeds an allowable value in multi-layer interconnection. 
         [0025]    If the wiring capacitance is not in the allowable range, the procedure returns to step S 102 , and then, the pattern is again corrected. 
         [0026]    If the wiring capacitance is in the allowable range, it is determined whether or not the corrected pattern satisfies the design rule. More specifically, it is determined whether or not the line and space dimensions of the corrected pattern are more than the minimum line and space dimensions predetermined in the design rule (step S 105 ). 
         [0027]    If the corrected pattern does not satisfy the design rule, the procedure returns to step S 102 , and then, the pattern is again corrected to satisfy the design rule. 
         [0028]    On the other hand, if the corrected pattern satisfies the design rule, the optical proximity correction (OPC) is carried out with respect to the necessary portions of the corrected pattern (step S 106 ). 
         [0029]    Finally, an exposure mask is prepared based on the corrected design pattern data (step S 107 ). 
         [0030]    The Publication No. 2002-131882 discloses the method of another embodiment taking the relation of one contact hole pattern with the space between adjacent contact hole patterns. According to the method of another embodiment, a pattern having a process margin, which does not satisfy the reference value is extracted. Thereafter, the extracted pattern is corrected to satisfy the process margin. 
         [0031]    As described above, the pattern forming method disclosed in the Publication No. 2002-131882 improves the process margin of the following patterns. The patterns are patterns (line patterns) to be formed on the same exposure mask or patterns in the same exposure mask such as a contact hole pattern. 
         [0032]    However, higher accuracy is required in pattern transfer to the semiconductor substrate, and in addition, further technical development is required to manufacture high-integrated semiconductor devices. 
         [0033]    The foregoing pattern forming methods have a problem that it is not suitable for improving the process margin between patterns to be formed using a plurality of exposure masks. 
       BRIEF SUMMARY OF THE INVENTION 
       [0034]    According to an aspect of the present invention, there is provided a pattern forming method of forming a desired pattern on a semiconductor substrate comprising: 
         [0035]    extracting-a first pattern of a layer; 
         [0036]    extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern; 
         [0037]    calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation; 
         [0038]    determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns; and 
         [0039]    correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin. 
         [0040]    According to another aspect of the present invention, there is provided a mask pattern forming method of forming a desired pattern on a semiconductor substrate comprising: 
         [0041]    extracting a first design pattern of a layer; 
         [0042]    extracting a second design pattern of one or more layers overlapped with the layer, the second design pattern being arranged close to or overlapped with the first design pattern; 
         [0043]    correcting the first design pattern in accordance with a correction rule of a design pattern defined by at least one of widths of the first and second design patterns on one hand and a distance between the first and second design patterns on the other hand; and 
         [0044]    forming a mask pattern by further correcting the first design pattern having corrected in accordance with the correction rule, by process proximity effect correction. 
         [0045]    According to a further aspect of the present invention, there is provided a pattern forming system of forming a desired pattern on a semiconductor substrate comprising: 
         [0046]    an extracting section configured to extract a first pattern of a layer; 
         [0047]    an extracting section configured to extract a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern; 
         [0048]    a calculating section configured to calculate a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation; 
         [0049]    a determining section configured to determine whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns; and 
         [0050]    a correcting section configured to correct, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin. 
         [0051]    According to a further aspect of the present invention, there is provided a mask pattern forming system of forming a desired pattern on a semiconductor substrate comprising: 
         [0052]    an extracting section configured to extract a first design pattern of a layer; 
         [0053]    an extracting section configured to extract a second design pattern of one or more layers overlapped with the layer, the second design pattern being arranged close to or overlapped with the first design pattern; 
         [0054]    a correcting section configured to correct the first design pattern in accordance with a correction rule of a design pattern defined by at least one of widths of the first and second design patterns on one hand and a distance between the first and second design patterns on the other hand; and 
         [0055]    a forming section configured to form a mask pattern by further correcting the first design pattern having corrected in accordance with the correction rule, by process proximity effect correction. 
         [0056]    According to a further aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: 
         [0057]    extracting a first pattern of a layer; 
         [0058]    extracting a second pattern of one or more layers overlapped with the layer, the second pattern being arranged close to or overlapped with the first pattern; 
         [0059]    calculating a distance between the first and second patterns on a semiconductor substrate in consideration of a predetermined process variation; 
         [0060]    determining whether or not the distance between the first and second patterns satisfy an allowable margin given for the distance between the first and second patterns; 
         [0061]    correcting, if the distance does not satisfy the allowable margin, at least one of the first and second patterns to satisfy the allowable margin; 
         [0062]    forming an exposure mask according to the at least one corrected pattern; and 
         [0063]    forming a semiconductor device on the semiconductor substrate via a lithography process by using the exposure mask. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0064]      FIG. 1  is a flowchart of a pattern forming method according to a first embodiment of the present invention; 
           [0065]      FIG. 2  is a view showing the appearance of exposure masks, for explaining the pattern forming method according to the first embodiment of the present invention, and shows patterns formed on the exposure masks; 
           [0066]      FIG. 3  is a view showing an example of a circuit pattern obtained by overlapping the exposure masks shown in  FIG. 2 ; 
           [0067]      FIG. 4  is a view showing an example of a circuit pattern obtained by overlapping the exposure masks of  FIG. 2 ; 
           [0068]      FIG. 5  is a view showing an example of a circuit pattern obtained by overlapping the exposure masks of  FIG. 2 ; 
           [0069]      FIG. 6  is a view showing an example of a circuit pattern obtained by overlapping the exposure masks of  FIG. 2 ; 
           [0070]      FIG. 7  is a view showing a circuit pattern, for explaining a first modification example of the first embodiment of the present invention; 
           [0071]      FIG. 8  is a view showing a circuit pattern, for explaining a second modification example of the first embodiment of the present invention; 
           [0072]      FIG. 9  is a view showing a circuit pattern, for explaining a third modification example of the first embodiment of the present invention, in which the layout is before being corrected; 
           [0073]      FIG. 10  is a view showing the circuit pattern of  FIG. 9 , for explaining the third modification example of the first embodiment of the present invention, in which the layout is after being corrected. 
           [0074]      FIG. 11  is a flowchart to explain a pattern forming method according to a second embodiment of the present invention; 
           [0075]      FIG. 12  is a flowchart following  FIG. 11  to explain the pattern forming method according to the second embodiment of the present invention; 
           [0076]      FIG. 13  is a view showing a circuit pattern for explaining the pattern forming method according to the second embodiment of the present invention; 
           [0077]      FIG. 14  is a block diagram showing the configuration of a pattern forming system according to a third embodiment of the present invention; 
           [0078]      FIG. 15  is a flowchart to explain a process of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention; 
           [0079]      FIG. 16  is a cross sectional view for explaining the manufacturing method according to the fourth embodiment of the present invention; 
           [0080]      FIG. 17  is a flowchart to schematically explain a conventional pattern forming method; 
           [0081]      FIG. 18  is a view showing the layout before circuit patterns are corrected; 
           [0082]      FIG. 19  is a layout view showing circuit the patterns of maximum and minimum line dimension when conditions such as an exposure amount and a focal length are varied to the circuit patterns shown in  FIG. 18 ; and 
           [0083]      FIG. 20  a view showing the layout after the circuit patterns shown in  FIG. 18  are corrected. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0084]    Embodiments of the present invention will be described below with reference to the accompanying drawings. 
       First Embodiment 
       [0085]    A pattern forming method according to a first embodiment of the present invention will be described below. 
         [0086]      FIG. 1  is a flowchart to explain the pattern forming method according to the first embodiment of the present invention. The flowchart of  FIG. 1  shows the processes until exposure mask writing data is prepared from design pattern data of a semiconductor device. 
         [0087]    As shown in  FIG. 1 , layout pattern design data (design pattern data) of the semiconductor device formed on a semiconductor substrate according to a predetermined design rule is acquired from a design pattern data recorder (step S 01 ), and circuit patterns are selected from the acquired design data. The selected circuit patterns are composed of patterns to be formed in a plurality of exposure masks. 
         [0088]    First, a first target pattern having a process margin to be checked is extracted from patterns to be formed on a first exposure mask (step S 02 ). 
         [0089]    Then, a second target pattern to be formed on a second exposure mask is extracted (step S 03 ). The second target pattern is positioned close to the first target pattern when the second exposure mask is overlapped with the first exposure mask. 
         [0090]    A Process margin for variation of the first and second target patterns due to the change of conditions of the exposure parameters caused when the first and second target patterns are transferred onto a semiconductor wafer, is determined (step S 04 ). 
         [0091]    The process margin is found out of the difference between maximum and minimum pattern critical dimensions when exposure and focal length is changed within a predetermined range according to lithography simulation. 
         [0092]    In step S 05 , it is determined whether or not the process margin satisfies a given reference value. If the process margin does not satisfy the reference value, pattern correction is required; for this reason, the process proceeds to step S 06 . On the other hand, if the process margin satisfies the reference value, no pattern correction is required; therefore, the process jumps to step S 10 . 
         [0093]    If the process margin does not satisfy the reference value, a distance between the first and second target patterns is determined (step S 06 ). Thereafter, it is determined whether or not the distance is larger than the minimum design rule. 
         [0094]    In this case, the minimum design rule means the minimum one of the design rules in a layer of the semiconductor device, in which the target pattern exists. 
         [0095]    If the distance between the first and second target patterns is larger than the minimum design rule, the pattern edge is shifted so that the process margin is widened to form a corrected new pattern (step S 08 ). On the other hand, if the foregoing distance is smaller than the minimum design rule, a rule for correcting pattern is prepared according to lithography simulation or experiment. In this case, the rule is prepared within a range of having no influence on the device characteristic. Thereafter, the pattern edge is corrected according to the predetermined rule (step S 09 ). 
         [0096]    In either case, optical proximity correction (OPC) of the pattern is carried out (step S 10 ), and thereafter, exposure mask writing data is prepared (step S 11 ). 
         [0097]    The foregoing pattern forming process is carried out with respect to each of all circuit patterns existing in design pattern data. The design pattern data is used as exposure mask pattern data finally written to exposure mask. 
         [0098]    The following is a detailed explanation about the case of correcting the circuit pattern according to the pattern forming method to improve the process margin. 
         [0099]      FIG. 2  is a view showing the appearance of three exposure masks used in the lithography process of semiconductor device, and, in particular, shows each circuit pattern formed on three exposure masks.  FIG. 3  shows a pattern obtained by overlapping three exposure masks shown in  FIG. 2 . The pattern is composed of a diffusion layer by ion implantation, a gate wiring and a contact hole, which are arranged close to each other. 
         [0100]    As illustrated in  FIG. 2 , an ion implantation layer pattern  12  for forming a diffusion layer by ion implantation is formed on a first exposure mask  11 . A gate pattern  14  for forming a gate wiring is formed on a second exposure mask  13 . A contact hole pattern  16  for forming a contact hole is formed on a third exposure mask  15 . 
         [0101]    More specifically, using the first exposure mask  11 , the ion implantation layer pattern  12  is formed at a predetermined region of a resist film formed on a semiconductor substrate, by lithography technique. Thereafter, ion implantation and an activation process are carried out. Subsequently, the semiconductor substrate is formed with insulating film and gate wiring film, and thereafter, the gate pattern  14  is formed in the gate wiring film using the second exposure mask  13 . Further, the contact hole pattern  16  is opened at the insulating film using the third exposure mask  15 . 
         [0102]    As seen from  FIG. 3 , the circuit pattern has the following edges. One is edges  16   a  to  16   d  of the contact hole pattern  16  of the third exposure mask  15 . Another is closely facing edges  14   a ,  14   b  of the gate pattern  14  of the second exposure mask  13 . Another is edges  12   a  to  12   d  of the ion implantation pattern  12  of the first exposure mask  11 . Here, in the circuit pattern, the distance between the edge  16   a  of the contact hole pattern and the edge  14   a  of the gate pattern  14  is set as L 1 . The distance between the edges  16   b  and  12   b  is set as L 2 . The distance between the edges  16   c  and  12   c  is set as L 3 . The distance between the edges  16   d  and  12   d  is set as L 4 . 
         [0103]    If it is determined that the contact hole pattern  16  of the third exposure mask  15  has process margin less than the reference value in the lithography process according to the flowchart shown in  FIG. 1 , the following procedure is taken. Design pattern distances (L 1 , L 2 , L 3 , L 4 ) between exposure masks are found, and based on the result, correction for forming a new circuit pattern is carried out to widen the process margin. 
         [0104]      FIG. 4  to  FIG. 6  is views to explain modification rule of the circuit pattern. For example, if all of L 1  to L 4  are larger than the minimum design rule (Lmin) as depicted in  FIG. 4 , edges  16   a  to  16   d  of the contact hole pattern  16  are shifted to edges  12   a  to  12   d , respectively. By doing so, the dimension of the contact hole pattern  16  is made large so that the process margin is taken larger than the reference value. 
         [0105]    If the distance L 1  between the edge  16   a  of the contact hole pattern and the edge  14   a  of the gate pattern  14  is equal to Lmin as shown in  FIG. 5 , the following procedure is taken. The edge  16   a  is fixed while other edges  16   b  to  16   d  are shifted to edges  12   b  to  12   d , respectively. By doing so, the dimension of the contact hole pattern  16  is made large so that the process margin is taken larger than the reference. 
         [0106]    If the distance L 3  between the edges  16   c  of the contact hole pattern  16  and the edge  12   c  of the ion implantation pattern  12  is equal to Lmin as shown in  FIG. 6 , the following procedure is taken. The edge  16   c  is fixed while other edges  16   a ,  16   b  and  16   d  are shifted to edges  12   a ,  12   b  and  12   d , respectively. In this way, the dimension of the contact hole pattern  16  is made large so that the process margin is taken larger than the reference. 
         [0107]    If the distance L 2  between the edges  16   b  of the contact hole pattern  16  and the edge  12   b  of the ion implantation pattern  12  and the distance L 4  between the edge  16   d  thereof and the edge  12   d  thereof or several distances L are equal to Lmin, the same procedure as above is taken. Edges on which other distances L is larger than Lmin are shifted. By doing so, the dimension of the contact hole pattern  16  is made large so that the process margin is taken larger than the reference. 
         [0108]    Here, each edge shift is determined by simulation or experiment in accordance with the situation, using a value when each of distances L 1  to L 4  is equal to the minimum design rule as the upper limit. 
         [0109]    According to the pattern forming method of the first embodiment of the present invention, patterns positioned close to each other or overlapped with each other when a plurality of exposure masks having the patterns are used to form a pattern, are extracted. Pattern correction is carried out in accordance with the distance between the patterns of the masks, and thereby, the process margin between the patterns of the masks is improved. Consequently, the transfer accuracy of the pattern of the masks to a semiconductor substrate is improved, so that semiconductor devices can be readily manufactured. 
         [0110]    In the first embodiment, the first to third exposure mask  11 ,  13  and  15  are formed with ion implantation layer pattern  12 , gate pattern  14  and contact hole pattern  16 , respectively. The patterns may be via layer, metal layer, isolation layer, gate layer, etc. Modification example will be described below. 
       Modification Example of First Embodiment 
       [0111]      FIG. 7  shows a circuit pattern according to a first modification example of the first embodiment of the present invention. The modification example differs from the first embodiment in that a metal wiring line is formed with via hole. More specifically, the second exposure mask  13  is formed with a metal pattern  24 , and the third exposure mask  15  is formed with a via hole  26 . According to the modification example, in order to make correspondence to the first embodiment, exposure mask formed with the circuit pattern calls the second exposure mask while exposure mask formed with the via hole pattern calls the third exposure. In this case, the given wring pattern comprises two exposure masks, and not three exposure masks. 
         [0112]    As shown in  FIG. 7 , the metal pattern  24  is formed at predetermined region of the semiconductor substrate formed with a metal wiring film by lithography technique using the second exposure mask  13 . The via hole pattern  26  is opened in the metal wiring using the third exposure mask  15 . 
         [0113]    The circuit pattern has edges  24   a  to  24   d  of the metal pattern  24  of the second exposure mask  13  and edges  26   a  to  26   d  of the via hole pattern  26  of the third exposure mask  15 . Here, in the circuit pattern, the distance between edges  24   a  and  26   a  is set as L 1 , and the distance between edges  24   b  and  26   b  is set as L 2 . The distance between edges  24   c  and  26   c  is set as L 3 , and the distance between edges  24   d  and  26   d  is set as L 4 . 
         [0114]    If it is determined that the via hole pattern  26  of the third exposure mask  15  has process margin less than the reference value in the lithography process according to the flowchart shown in  FIG. 1 , the following procedure is taken. Design pattern distances (L 1 , L 2 , L 3 , L 4 ) between the second and third exposure masks  13  and  15  are found, and based on the result, correction for forming a new circuit pattern is carried out to widen the process margin. 
         [0115]    For example, if the distance L 2  between the edge  24   b  of the metal pattern  24  and the edge  26   b  of the via hole pattern  26  and the distance L 4  between the edge  24   d  thereof and the edge  26   d  thereof are both equal to Lmin, the following procedure is taken. The edges  26   b  and  26   d  are fixed while other edges  26   a  and  26   c  are shifted to edges  24   a  and  24   c , respectively. By doing so, the dimension of the via hole pattern  26  is made large so that the process margin is taken larger than the reference value. 
         [0116]    According to the present first modification example, a metal pattern and a via hole pattern overlapped with each other when a plurality of exposure masks are used to provide a pattern, are extracted. Pattern correction is carried out in accordance with the distance between the patterns of the masks, and thereby, the process margin between the patterns of the masks is improved. Consequently, the transfer accuracy of the patterns of the masks to the semiconductor substrate is improved, so that semiconductor devices can be readily manufactured. 
         [0117]    In the modification example, edges  26   a  and  26   c  are corrected in the case where distanced L 2  and L 4  are equal to Lmin. Correction target edge is not limited to the foregoing case. Edges to be shifted may be variously selected within a range satisfying the condition that each of distances L 1  to L 4  between edges is larger than the minimum. 
       Modification Example of Second Embodiment 
       [0118]      FIG. 8  shows a circuit pattern according to a second modification example of the first embodiment of the present invention. The present modification example differs from the first embodiment in that a contact hole is formed to be sandwiched by two gate wiring lines. More specifically, the second exposure mask  13  is formed with two gate patterns  34  and  38 , and the third exposure mask  15  is formed with a contact hole pattern  36 . According to the modification example, in order to make correspondence to the first embodiment, exposure mask formed with the gate patterns calls the second exposure mask while exposure mask formed with the contact hole pattern calls the third exposure. In this case, the given wring pattern comprises two exposure masks, and not three. 
         [0119]    As shown in  FIG. 8 , the gate patterns  34  and  38  are formed at predetermined region of the semiconductor substrate formed with a gate wiring film by lithography technique using the second exposure mask  13 . The contact hole pattern  36  is opened to be sandwiched by the two gate wiring lines, using the third exposure mask  15 . 
         [0120]    The circuit pattern has edges  34   a  and  38   a  of the gate patterns  34  and  38  of the second exposure mask  13  and edges  36   a  to  36   d  of the contact hole pattern  36  of the third exposure mask  15 . Here, in the circuit pattern, the distance between edges  34   a  and  36   a  is set as L 1 , and the distance between edges  38   a  and  36   c  is set as L 2 . 
         [0121]    If it is determined that the contact hole pattern  36  of the third exposure mask  15  has process margin less than the reference value in the lithography process according to the flowchart shown in  FIG. 1 , the following procedure is taken. Design pattern distances (L 1 , L 2 ) between the second and third exposure masks  13  and  15  are found, and based on the result, correction for forming a new circuit pattern is carried out to widen the process margin. 
         [0122]    For example, if the distance L 1  between the edge  34   a  of the gate pattern  34  and the edge  36   a  of the contact hole pattern  36  and the distance L 2  between the edge  38   a  of the gate pattern  38  and the edge  36   c  of the contact hole pattern  36  are both equal to Lmin, the following procedure is taken. The edges  36   a  and  36   c  are fixed while other edges  36   b  and  36   d  are shifted in a direction parallel to edges  34   a  and  38   a , respectively. By doing so, the dimension of the contact hole pattern  36  is made large so that the process margin is taken larger than the reference value. 
         [0123]    According to the present second modification example, two gate patterns and a contact hole pattern close to each other when a plurality of exposure masks are used to provide a pattern, are extracted. Pattern correction is carried out in accordance with the distance between the patterns of the masks, and thereby, the process margin between the patterns of the masks is improved. Consequently, the transfer accuracy of the patterns of the masks to the semiconductor substrate is improved, so that semiconductor devices can be readily manufactured. 
       Modification Example of Third Embodiment 
       [0124]      FIG. 9  shows a circuit pattern according to a third modification example of the first embodiment of the present invention, in which the layout is before being corrected, and  FIG. 10  shows the circuit pattern according to the third modification example of the first embodiment of the present invention, in which the layout is after being corrected. The modification example differs from the first embodiment in that two closely arranged ion implantation diffusion layer patterns are formed with contact hole patterns, respectively. 
         [0125]    More specifically, the first exposure mask  11  is formed with two ion implantation diffusion layer patterns  41  and  42 , and the third exposure mask  15  is formed with two contact hole patterns  46  and  47 . According to the modification example, in order to make correspondence to the first embodiment, exposure mask formed with the ion implantation diffusion layer patterns calls the first exposure mask while exposure mask formed with the contact hole patterns calls the third exposure. In this case, the given wring pattern comprises two exposure masks, and not three. 
         [0126]    As shown in  FIG. 9 , the two ion implantation diffusion layer patterns  41  and  42  are formed at predetermined region of the semiconductor substrate formed with a resist film by lithography technique using the first exposure mask  11 , followed by ion implantation and ion activation. Thereafter, an insulating film is formed on the semiconductor substrate, and then two contact hole patterns  46  and  47  are opened in the insulating film by lithography technique, using the third exposure mask  15 . 
         [0127]    The circuit pattern has edges  41   a  to  41   d  of the ion implantation diffusion layer patterns  41 , edges  42   a  to  42   d  of the ion implantation diffusion layer patterns  42 , edges  46   a  to  46   d  of the contact hole patterns  46 , and edges  47   a  to  47   d  of the contact hole patterns  47 . Here, in the circuit pattern, the distance between edges  41   c  and  46   c  is set as L 1 , the distance between edges  42   a  and  47   a  is set as L 2 , and the distance between edges  41   c  and  42   a  is set as L 3 . 
         [0128]    If it is determined that the two ion implantation diffusion layer patterns  41  and  42  of the first exposure mask  11  has process margin less than the reference value in the lithography process according to the flowchart shown in  FIG. 1 , the following procedure is taken. Design pattern distances (L 1 , L 2 , L 3 ) between the first and third exposure masks  11  and  15  are found, and based on the result, correction for forming a new circuit pattern is carried out to widen the process margin. 
         [0129]    For example, if the distance L 1  between the edge  41   c  of the ion implantation diffusion layer pattern  41  and the edge  46   c  of the contact hole pattern  46  and the distance L 2  between the edge  42   a  of the ion implantation diffusion layer pattern  42  and the edge  47   a  of the contact hole pattern  47  are both equal to Lmin, the following procedure is taken. A part of the edge  41   c  and a part of the  42   a  are shifted toward each other while the distance between the edges  41   c  and  42   a  is widen from L 3  to L 4 . By doing so, the process margin is taken larger than the reference value. 
         [0130]    Here, the shift amount of the edges  41   c  and  42   a  is defined by lithography simulation or experiment. The distance L 5  between the edges  46   b  and  41   e  and the distance L 6  between the edges  47   b  and  42   e  are set to be larger than Lmin to keep the minimum design rule of the patterns  41 ,  42 ,  46  and  47 . 
         [0131]    According to the present third modification example, two ion implantation diffusion layer patterns and contact hole patterns overlapped with each other when a plurality of exposure masks are used to provide a pattern, are extracted. Correction of the implantation diffusion layer patterns is carried out in accordance with the distance between the patterns of the masks, and thereby, the process margin between the patterns of the masks is improved. Consequently, the transfer accuracy of the patterns of the masks to the semiconductor substrate is improved, so that semiconductor devices can be readily manufactured. 
       Second Embodiment 
       [0132]      FIG. 11  and  FIG. 12  are flowcharts to explain a pattern forming method according to a second embodiment of the present invention. The flowchart of  FIG. 11  and  FIG. 12  shows the processes until exposure mask writing data is prepared from design pattern data of semiconductor device. In the second embodiment, the same reference numerals are used to designate the constituent parts identical to the first embodiment, and the details are omitted. Only different parts will be explained. 
         [0133]    The second embodiment differs from the first embodiment in the following point. If it is determined that circuit-patterns to be formed in the first and second exposure masks both have smaller process margin, correction is made with respect to both first and second target patterns. 
         [0134]    As shown in  FIG. 11 , design pattern data (referred to as GDS 1 ) to be formed in the first exposure mask is acquired from a design pattern data memory according to predetermined design rule (step S 21 ). In addition, design pattern data (referred to as GDS 3 ) to be formed in the second exposure mask is acquired from the design pattern data memory (step S 22 ). 
         [0135]    The same procedures described in steps S 04  to S 09  of the flowchart shown in  FIG. 1  are carried out. More specifically, a circuit pattern is extracted from the GDS 1 , the process margin is found, and pattern edge is shifted so that the process margin is take larger than the reference value (steps S 23  to S 28 ). 
         [0136]    Based on the corrected result, new exposure mask data (referred to as GDS 2 ) of the GDS 1  is prepared (step S 29 ). 
         [0137]    Then, the same procedures described in steps S 10  and S 11  of the flowchart shown in  FIG. 1  are taken. More specifically, OPC pattern is given to necessary portion of the corrected circuit pattern, and optical proximity correction is carried out to obtain exposure mask writing data of the GDS 1  (steps S 30  and S 31 ). 
         [0138]    As depicted in  FIG. 12 , a pattern corresponding to the GDS 1  in step S 23  is extracted from the GDS 3  in the same manner as steps S 04  to S 09  of the flowchart shown in  FIG. 1 , and thereafter, the process margin is found. Pattern edge is shifted so that the process margin is taken larger than the reference value (steps S 32  to S 37 ). 
         [0139]    The different from the first embodiment is to find the distance between GDS 2  and DGS 3  patterns using the DGS 2  prepared in step S 29  (step S 34 ). 
         [0140]    Based on the corrected result, new exposure mask data (referred to as GDS 4 ) of the GDS 3  is prepared (step S 38 ). 
         [0141]    Finally, an OPC pattern is given to necessary portions of the corrected circuit pattern in the same manner as steps S 10  and S 11  of the flowchart shown in  FIG. 1 . Optical proximity correction is carried out to obtain exposure mask data of the GDS 3  (steps S 39  and S 40 ). 
         [0142]    The foregoing pattern forming processes are repeatedly carried out with respect to all circuit patterns existing in design pattern data GDS 1  and GDS 3 , and exposure mask writing data is finally given. 
         [0143]    The following is a detailed explanation of the case of correcting circuit pattern by the pattern forming method to improve process margin. 
         [0144]      FIG. 13  is a view showing a pattern obtained by overlapping two exposure masks, in which a metal electrode pattern and a contact hole pattern are arranged in a state of being coaxially overlapped in similar figures. 
         [0145]    As seen from  FIG. 13 , a metal electrode pattern  51  is arranged as GDS 1  in the first exposure mask  11 , and a contact hole pattern  52  is arranged as GDS 3  in the second exposure mask  13 . 
         [0146]    As shown in  FIG. 13 , the semiconductor substrate is formed with a metal film, and thereafter, the metal electrode pattern  51  is formed by lithography technique, using the first exposure mask  11 . Further, the semiconductor substrate is formed with metal film, and thereafter, the contact hole pattern  52  is opened in the metal film by lithography technique, using the second exposure mask  13 . 
         [0147]    Here, the distance between the edge  51   a  of the metal electrode pattern  51  and the edge  52   a  of the contact hole pattern  52  is set as L 1 . 
         [0148]    If it is determined that the metal electrode pattern  51  of the first exposure mask  11  has process margin less than the reference value in the lithography process according to the flowchart shown in  FIG. 11 , the following procedure is carried out. Edges  51   a  to  51   d  of the metal electrode pattern  51  are shifted outside by ΔL 1 . By doing so, the dimension of the metal electrode pattern  51  is made large so that the process margin is taken larger than the reference value. 
         [0149]    The procedure described above is carried out, and thereby, a corrected new metal electrode pattern (GDS 2 )  53  shown by an imaginary line is obtained. Based on the obtained pattern, first exposure mask writing data is prepared. 
         [0150]    Likewise, if it is determined that the contact hole pattern  52  of the second exposure mask  13  has process margin less than the reference value in the lithography process according to the flowchart shown in  FIG. 12 , the following procedure is taken. The design pattern distance L 1  between exposure masks is determined, and thereafter, based on the result, correction for forming a new pattern is made to widen the process margin. 
         [0151]    For example, if the distance L 1  between the edge  51   a  of the metal electrode pattern  51  and the edge  52   a  of the contact hole pattern  52  is equal to Lmin, it is impossible to shift the edge  52   a . For this reason, the distance L 2  between the edge  53   a  of the corrected new metal electrode pattern (GDS 2 )  53  and the edge  52   a  of the contact hole pattern  52  is measured. Edges  52   a  to  52   d  of the contact hole pattern  52  are shifted outside by ΔL 2 . By doing so, the dimension of the contact hole pattern  52  is made large so that the process margin is taken larger than the reference value. 
         [0152]    The procedure described above is carried out, and thereby, a corrected new contact hole pattern (GDS 4 )  54  shown by an imaginary line is obtained. Based on the obtained pattern, first exposure mask writing data is prepared. 
         [0153]    According to the pattern forming method of the second embodiment of the present invention, patterns coaxially overlapped with each other in similar figures when a plurality of exposure masks are used to provide a pattern, are extracted. Pattern correction is carried out in accordance with the distance between the patterns of the masks, and thereby, the process margin between the patterns of the masks is improved. Consequently, the transfer accuracy of the patterns of the masks to the semiconductor substrate is improved, so that semiconductor devices can be readily manufactured. 
       Third Embodiment 
       [0154]    The pattern forming system according to a third embodiment of the present invention will be explained below with reference to  FIG. 14 . The pattern forming system according to the third embodiment is used for realizing the pattern forming method described in the first and second embodiments of the present invention. 
         [0155]      FIG. 14  is a block diagram showing the configuration of the pattern forming system according to the third embodiment of the present invention. 
         [0156]    As shown in  FIG. 14 , a pattern forming system  61  of the present embodiment comprises design-pattern data memory section  62 , program storage section  63 , mask writing data memory section  64 , processing control section  65 , output and input devices  67  and  68 . More specifically, the design pattern data memory section  62  stores the layout design pattern data of the semiconductor device. The program storage section  63  stores programs for correcting exposure mask pattern to form a new pattern. The mask writing data memory section  64  stores obtained exposure mask writing data. The processing control section  65  includes means for carrying out a series of mask pattern correction processing. The output device  67  outputs processing results via an input-output control section  66 , and the input device  68  inputs instructions to the processing control section  65 . 
         [0157]    The foregoing design pattern data memory section  62 , program storage section  63  and mask writing data memory section  64  may be partially composed of main memory device built in a computer. In addition, these sections  62  to  64  may be composed of memory devices such as semiconductor memory, magnetic disk, magnetic tape and optical disk, which are connected to the computer. 
         [0158]    The processing control section  65  constitutes part of the central processing unit of the computer system, and is operated by a centralized or distributed processing type computer system. 
         [0159]    The processing control section  65  is composed of pattern extraction section  69 , pattern determination section  70 , pattern correction section  71 , optical proximity correction section  72  and mask writing data preparing section  73 . More specifically, the pattern extraction section  69  reads circuit patterns to be formed in first and second exposure masks from the design pattern data memory section  62 . Thereafter, the pattern extraction section  69  extracts first and second target patterns from the circuit patterns to be formed in the first and second exposure masks. The pattern determination section  70  determines whether or not process margin satisfies a predetermined reference value with respect to variations of exposure parameters. The pattern correction section  71  corrects a pattern, which is determined as having no process margin satisfying the reference value so that the process margin is widened. The optical proximity correction section  72  gives OPC pattern to necessary portion of the corrected design pattern to carry out optical proximity correction (OPC). The mask writing data preparing section  73  prepares exposure mask writing data for forming the final pattern on the exposure mask. In this case, the final pattern has improved process margin larger than the reference value, and already receives the optical proximity correction. 
         [0160]    The foregoing pattern extraction section  69 , pattern determination section  70 , pattern correction section  71 , optical proximity correction section  72  and mask writing data preparing section  73  are previously stored in the program storage section  63  as software. These sections are operated by the central processing unit of the computer system according to the procedure. In this case, these sections may be operated by dedicated hardware. 
         [0161]    In the pattern forming system according to the present third embodiment, pattern correction is made in accordance with the distance between the patterns positioned close to each other or overlapped with each other when a plurality of exposure masks having the patterns are used to provide a pattern. By doing so, it is possible to obtain exposure mask formed with the patterns having high process margin. 
       Fourth Embodiment 
       [0162]    The method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be explained with reference to  FIG. 15 . According to the method of manufacturing a semiconductor device according to the fourth embodiment, semiconductor devices are manufactured using the pattern forming system described in the third embodiment.  FIG. 15  is a flowchart to explain the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention. 
         [0163]    Function design, logical circuit design and layout pattern design for semiconductor devices to be manufactured are made (step S 71 ). 
         [0164]    In other words, function design is made in a manner of clarifying functions necessary for realizing the objects and effects of semiconductor devices to be manufactured, and designing mutual linkage with various functions such as logic memory for performing the function and input-output interface. 
         [0165]    Logical circuit design for designing electronic circuits is made based on various functions and relationship. Then, layout design is made to arrange various electronic circuits on a semiconductor chip. Thereafter, circuit patterns to be formed on several exposure masks used in a serial manufacture processes of semiconductor wafer is designed to satisfy the design rule. 
         [0166]    The layout design pattern data is sent to the design pattern memory section, and thereafter, circuit patterns having process margin less than the reference value described in the first and second embodiments is extracted. The circuit patterns are corrected so that the process margin is taken larger than the reference value. 
         [0167]    More specifically, a first target pattern is extracted from patterns to be formed on the first exposure mask (step S 72 ). A second target pattern to be formed close to the first target pattern is extracted from patterns to be formed on the first exposure mask (step S 73 ). 
         [0168]    A pattern having process margin less than the predetermined reference value is extracted based on process variations of the first and second target patterns (step S 74 ). Pattern correction is made in a manner of shifting each edge of the first or second target pattern to widen the process margin (step S 75 ). 
         [0169]    Then, optical proximity correction (OPC) pattern is added to necessary portion of the corrected design pattern to carry out optical proximity correction (step S 76 ). 
         [0170]    Exposure mask writing data for forming the final pattern having improved process margin and receiving optical proximity correction on exposure mask is prepared. Based on the prepared exposure mask writing data, exposure mask is manufactured (step S 78 ). 
         [0171]    Semiconductor devices are collectively formed on the semiconductor wafer via the following processes (wafer process) (step S 79 ). One of the processes is a deposition process of depositing insulating film, semiconductor film and metal films onto the semiconductor substrate. Another is a lithography process to the semiconductor substrate using the foregoing exposure mask, as shown in  FIG. 16 . Another is an etching process and a series of wafer manufacture processes repeating ion implantation. Thereafter, the semiconductor devices are manufactured via dicing, bonding and inspection processes (assembly and testing process). 
         [0172]    According to the method of manufacturing the semiconductor device of the present fourth embodiment, patterns are transferred to the semiconductor substrate using a plurality of exposure masks having a high process margin between the patterns. Therefore, semiconductor devices can be manufactured with high yield. 
         [0173]    As is evident from the foregoing description, according to the embodiments of the present invention, process margin between patterns positioned close to each other or overlapped with each other when a plurality of exposure masks having the patterns are used to provide a pattern, is improved. 
         [0174]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.