PATENT ABSTRACT
A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel, a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.

PATENT DESCRIPTION
FIELD OF THE INVENTION  
         [0001]    The invention relates generally to improved semiconductor imaging devices and in particular to an imaging device which can be fabricated using a standard CMOS process. Particularly, the invention relates to a CMOS imager having a storage capacitor formed in parallel with a light sensitive node of the CMOS imager.  
         BACKGROUND OF THE INVENTION  
         [0002]    There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays. CCDs are often employed for image acquisition and enjoy a number of advantages which makes it the incumbent technology, particularly for small size imaging applications. CCDs are also capable of large formats with small pixel size and they employ low noise charge domain processing techniques. However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there has been some attempts to integrate on-chip signal processing with the CCD array, these attempts have not been entirely successful. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes time. CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer which also results in image smear.  
           [0003]    Because of the inherent limitations in CCD technology, there is an interest in CMOS imagers for possible use as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.  
           [0004]    The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD since standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.  
           [0005]    A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate, photoconductor or photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.  
           [0006]    In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate. For photodiodes, image tag can be eliminated by completely depleting the photodiode upon readout.  
           [0007]    CMOS imagers of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12) pp. 2046-2050, 1996; Mendis et al, “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452-453, 1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515, which are herein incorporated by reference.  
           [0008]    To provide context for the invention, an exemplary CMOS imaging circuit is described below with reference to FIG. 1. The circuit described below, for example, includes a pliotogate for accumulating photo-generated charge in an underlying portion of the substrate. It should be understood that the CMOS imager may include a photodiode or other image to charge converting device, in lieu of a photogate, as the initial accumulator for photo-generated charge.  
           [0009]    Reference is now made to FIG. 1 which shows a simplified circuit for a pixel of an exemplary CMOS imager using a photogate and having a pixel photodetector circuit  14  and a readout circuit  60 . It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, that in practical use there will be an MxN array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.  
           [0010]    The photodetector circuit  14  is shown in part as a cross-sectional view of a semiconductor substrate  16  typically a p-type silicon, having a surface well of p-type material  20 . An optional layer  18  of p-type material may be used if desired, but is not required. Substrate  16  may be formed of, for example, Si, SiGe, Ge, and GaAs. Typically the entire substrate  16  is p-type doped silicon substrate and may contain a surface p-well  20  (with layer  18  omitted), but many other options are possible, such as, for example p on p− substrates, p on p+ substrates, p-wells in n-type substrates or the like. The terms wafer or substrate used in the description includes any semiconductor-based structure having an exposed surface in which to form the circuit structure used in the invention. Wafer and substrate are to be understood as including , silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure or foundation.  
           [0011]    An insulating layer  22  such as, for example, silicon dioxide is formed on the upper surface of p-well  20 . The p-type layer may be a p-well formed in substrate  16 . A photogate  24  thin enough to pass radiant energy or of a material which passes radiant energy is formed on the insulating layer  22 . The photogate  24  receives an applied control signal PG which causes the initial accumulation of pixel charges in n+ region  26 . The n+ type region  26 , adjacent one side of photogate  24 , is formed in the upper surface of p-well  20 . A transfer gate  28  is formed on insulating layer  22  between n+ type region  26  and a second n+ type region  30  formed in p-well  20 . The n+ regions  26  and  30  and transfer gate  28  form a charge transfer transistor  29  which is controlled by a transfer signal TX. The n+ region  30  is typically called a floating diffusion region. It is also a node for passing charge accumulated thereat to the gate of a source follower transistor  36  described below. A reset gate  32  is also formed on insulating layer  22  adjacent and between n+ type region  30  and another n+ region  34  which is also formed in p-well  20 . The reset gate  32  and n+ regions  30  and  34  form a reset transistor  31  which is controlled by a reset signal RST. The n+ type region  34  is coupled to voltage source VDD, e.g., 5 volts. The transfer and reset transistors  29 ,  31  are n-channel transistors as described in this implementation of a CMOS imager circuit in a p-well. It should be understood that it is possible to implement a CMOS imager in an n-well in which case each of the transistors would be p-channel transistors. It should also be noted that while FIG. 1 shows the use of a transfer gate  28  and associated transistor  29 , this structure provides advantages, but is not required.  
           [0012]    Photodetector circuit  14  also includes two additional n-channel transistors, source follower transistor  36  and row select transistor  38 . Transistors  36 ,  38  are coupled in series, source to drain, with the source of transistor  36  also coupled over lead  40  to voltage source VDD and the drain of transistor  38  coupled to a lead  42 . The drain of row select transistor  38  is connected via conductor  42  to the drains of similar row select transistors for other pixels in a given pixel row. A load transistor  39  is also coupled between the drain of transistor  38  and a voltage source VSS, e.g. 0 volts. Transistor  39  is kept on by a signal VLN applied to its gate.  
           [0013]    The imager includes a readout circuit  60  which includes a signal sample and hold (S/H) circuit including a S/H n-channel field effect transistor  62  and a signal storage capacitor  64  connected to the source follower transistor  36  through row transistor  38 . The other side of the capacitor  64  is connected to a source voltage VSS. The upper side of the capacitor  64  is also connected to the gate of a p-channel output transistor  66 . The drain of the output transistor  66  is connected through a column select transistor  68  to a signal sample output node VOUTS and through a load transistor  70  to the voltage supply VDD. A signal called “signal sample and hold” (SHS) briefly turns on the S/H transistor  62  after the charge accumulated beneath the photogate electrode  24  has been transferred to the floating diffusion node  30  and from there to the source follower transistor  36  and through row select transistor  38  to line  42 , so that the capacitor  64  stores a voltage representing the amount of charge previously accumulated beneath the photogate electrode  24 .  
           [0014]    The readout circuit  60  also includes a reset sample and hold (S/H) circuit including a S/H transistor  72  and a signal storage capacitor  74  connected through the S/H transistor  72  and through the row select transistor  38  to the source of the source follower transistor  36 . The other side of the capacitor  74  is connected to the source voltage VSS. The upper side of the capacitor  74  is also connected to the gate of a p-channel output transistor  76 . The drain of the output transistor  76  is connected through a p-channel column select transistor  78  to a reset sample output node VOUTR and through a load transistor  80  to the supply voltage VDD. A signal called “reset sample and hold” (SHR) briefly turns on the S/H transistor  72  immediately after the reset signal RST has caused reset transistor  31  to turn on and reset the potential of the floating diffusion node  30 , so that the capacitor  74  stores the voltage to which the floating diffusion node  30  has been reset.  
           [0015]    The readout circuit  60  provides correlated sampling of the potential of the floating diffusion node  30 , first of the reset charge applied to node  30  by reset transistor  31  and then of the stored charge from the photogate  24 . The two samplings of the diffusion node  30  charges produce respective output voltages VOUTR and VOUTS of the readout circuit  60 . These voltages are then subtracted (VOUTS-VOUTR) by subtractor  82  to provide an output signal terminal  81  which is an image signal independent of pixel to pixel variations caused by fabrication variations in the reset voltage transistor  31  which might cause pixel to pixel variations in the output signal.  
           [0016]    [0016]FIG. 2 illustrates a block diagram for a CMOS imager having a pixel array  200  with each pixel cell being constructed in the manner shown by element  14  of FIG. 1. Pixel array  200  comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array  200  are all turned on at the same time by a row select line, e.g., line  86 , and the pixels of each column are selectively output by a column select line, e.g., line  42 . A plurality of rows and column lines are provided for the entire array  200 . The row lines are selectively activated by the row driver  210  in response to row address decoder  220  and the column select lines are selectively activated by the column driver  260  in response to column address decoder  270 . Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the control circuit  250  which controls address decoders  220 ,  270  for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry  210 ,  260  which apply driving voltage to the drive transistors of the selected row and column lines.  
           [0017]    [0017]FIG. 3 shows a simplified timing diagram for the signals used to transfer charge out of photodetector circuit  14  of the FIG. 1 CMOS imager. The photogate signal PG is nominally set to 5V and pulsed from 5V to 0V during integration. The reset signal RST is nominally set at 2.5V. As can be seen from the figure, the process is begun at time to by briefly pulsing reset voltage RST to 5V. The RST voltage, which is applied to the gate  32  of reset transistor  31 , causes transistor  31  to turn on and the floating diffusion node  30  to charge to the VDD voltage present at n+ region  34  (less the voltage drop Vth of transistor  31 ). This resets the floating diffusion node  30  to a predetermined voltage (VDD-Vth). The charge on floating diffusion node  30  is applied to the gate of the source follower transistor  36  to control the current passing through transistor  38 , which has been turned on by a row select (ROW) signal, and load transistor  39 . This current is translated into a voltage on line  42  which is next sampled by providing a SHR signal to the S/H transistor  72  which charges capacitor  74  with the source follower transistor output voltage on line  42  representing the reset charge present at floating diffusion node  30 . The PG signal is next pulsed to 0 volts, causing charge to be collected in n+ region  26 . A transfer gate voltage TX, similar to the reset pulse RST, is then applied to transfer gate  28  of transistor  29  to cause the charge in n+region  26  to transfer to floating diffusion node  30 . It should be understood that for the case of a photogate, the transfer gate voltage TX may be pulsed or held to a fixed DC potential. For the implementation of a photodiode with a transfer gate, the transfer gate voltage TX must be pulsed. The new output voltage on line  42  generated by source follower transistor  36  current is then sampled onto capacitor  64  by enabling the sample and hold switch  62  by signal SHS. The column select signal is next applied to transistors  68  and  70  and the respective charges stored in capacitors  64  and  74  are subtracted in subtractor  82  to provide a pixel output signal at terminal  81 . It should also be noted that CMOS imagers may dispense with the transfer gate  28  and associated transistor  29 , or retain these structures while biasing the transfer transistor  29  to an always “on” state.  
           [0018]    The operation of the charge collection of the CMOS imager is known in the art and is described in several publications such as Mendis et al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172, pp. 19-29 1994; Mendis et al., “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems,” IEEE Journal of Solid State Circuits, Vol. 32(2), 1997; and Eric R, Fossum, “CMOS Image Sensors: Electronic Camera on a Chip,” IEDM Vol.95 pages 17-25 (1995) as well as other publications. These references are incorporated herein by reference.  
           [0019]    Prior CMOS imagers suffer from poor signal to noise ratios and poor dynamic range as a result of the inability to fully collect and store the electric charge collected by the photosensitive area. Since the size of the pixel electrical signal is very small due to the collection of photons in the photo array, the signal to noise ratio and dynamic range of the pixel should be as high as possible. There is needed, therefore, an improved active pixel photosensor for use in an APS imager that exhibits improved dynamic range, a better signal-to-noise ratio, and improved charge capacity for longer integration times. A method of fabricating an active pixel photosensor exhibiting these improvements is also needed.  
         SUMMARY OF THE INVENTION  
         [0020]    The present invention provides a CMOS imager having a storage capacitor connected to the light sensitive node to improve collected charge storage. The storage capacitor is formed in parallel with the light sensitive node of the imager and may be any type of capacitor formed on the pixel cell over a non-light sensitive area. Also provided are methods for forming the CMOS imager of the present invention.  
           [0021]    Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    [0022]FIG. 1 is a representative circuit of a CMOS imager.  
         [0023]    [0023]FIG. 2 is a block diagram of a CMOS pixel sensor chip.  
         [0024]    [0024]FIG. 3 is a representative timing diagram for the CMOS imager.  
         [0025]    [0025]FIG. 4 is a representative pixel layout showing a 2×2 pixel layout.  
         [0026]    [0026]FIG. 5 is a cross-sectional view of a pixel sensor according to one embodiment of the present invention.  
         [0027]    [0027]FIG. 6 is a cross-sectional view of a semiconductor wafer according to FIG. 5 undergoing the process of an embodiment of the invention.  
         [0028]    [0028]FIG. 7 shows the wafer of FIG. 6 at a processing step subsequent to that shown in FIG. 6.  
         [0029]    [0029]FIG. 8 shows the wafer of FIG. 6 at a processing step subsequent to that shown in FIG. 7.  
         [0030]    [0030]FIG. 9 shows the wafer of FIG. 6 at a processing step subsequent to that shown in FIG. 8.  
         [0031]    [0031]FIG. 10 shows the wafer of FIG. 6 at a processing step subsequent to that shown in FIG. 9.  
         [0032]    [0032]FIG. 11 shows the wafer of FIG. 6 at a processing step subsequent to that shown in FIG. 10.  
         [0033]    [0033]FIG. 12 shows the wafer of FIG. 6 at a processing step subsequent to that shown in FIG. 11.  
         [0034]    [0034]FIG. 13 shows the wafer of FIG. 6 at a processing step subsequent to that shown in FIG. 12.  
         [0035]    [0035]FIG. 14 shows the wafer of FIG. 6 at a processing step subsequent to that shown in FIG. 13.  
         [0036]    [0036]FIG. 15 is a cross-sectional view of a pixel sensor according to another embodiment of the present invention.  
         [0037]    [0037]FIG. 16 is a cross-sectional view of a semiconductor wafer according to FIG. 15 undergoing the process of an embodiment of the invention.  
         [0038]    [0038]FIG. 17 shows the wafer of FIG. 16 at a processing step subsequent to that shown in FIG. 16.  
         [0039]    [0039]FIG. 18 shows the wafer of FIG. 16 at a processing step subsequent to that shown in FIG. 17.  
         [0040]    [0040]FIG. 19 shows the wafer of FIG. 16 at a processing step subsequent to that shown in FIG. 18.  
         [0041]    [0041]FIG. 20 shows the wafer of FIG. 16 at a processing step subsequent to that shown in FIG. 19.  
         [0042]    [0042]FIG. 21 shows the wafer of FIG. 16 at a processing step subsequent to that shown in FIG. 20.  
         [0043]    [0043]FIG. 22 shows the wafer of FIG. 16 at a processing step subsequent to that shown in FIG. 21.  
         [0044]    [0044]FIG. 23 is a cross-sectional view of a pixel sensor according to another embodiment of the present invention.  
         [0045]    [0045]FIG. 24 is an illustration of a computer system having a CMOS imager according to the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0046]    In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.  
         [0047]    The terms “wafer” and “substrate” are to be understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, or gallium arsenide.  
         [0048]    The term “pixel” refers to a picture element unit cell containing a photosensor and transistors for converting electromagnetic radiation to an electrical signal. For purposes of illustration, a representative pixel is illustrated in the figures and description herein, and typically fabrication of all pixels in an imager will proceed simultaneously in a similar fashion. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.  
         [0049]    The structure of the pixel cell  114  of a first embodiment is shown in more detail in FIG. 5. The pixel cell  114  may be formed in a substrate  116  having a doped layer  120  of a first conductivity type, which for exemplary purposes is treated as a p-type substrate. A field oxide layer  115 , which serves to surround and isolate the cells may be formed by thermal oxidation of the doped layer  120 , or by chemical vapor deposition of an oxide material. This field oxide layer  115  may be formed before or after the gate stacks (described below) are formed. The doped layer  120  is provided with five doped regions  110 ,  126 ,  130 ,  134  and  155 , which are doped to a second conductivity type, which for exemplary purposes is treated as n type. The first doped region  110  underlies photogate  102 , which is a thin layer of material transparent to radiant energy, such as polysilicon. The second doped region  126  electrically connects photogate transistor  125  to the transfer transistor gate  128 . An insulating layer  100  of silicon dioxide, silicon nitride, or other suitable material is formed over a surface of the doped layer  120  of the substrate  116 .  
         [0050]    The third doped region  130  is the floating diffusion region, sometimes also referred to as a floating diffusion node. The floating diffusion region  130  is connected to the source follower transistor  136  by a contact line  144  which is typically a metal contact line. The source follower transistor  136  outputs a signal proportional to the charge accumulated in the floating diffusion region  130  to a readout circuit  60  when the row select transistor  138  is turned on as shown above in FIG. 1. While the source follower transistor  136  and transistor  138  are illustrated in FIG. 5 in circuit form above substrate  120 , it should be understood that these transistors are typically formed in substrate  120  in a similar fashion to transistors  128  and  132 .  
         [0051]    The fourth doped region  134  is the drain of the reset transistor  131 , and is also connected to voltage source VDD. The pixel cell thus far described with reference with FIG. 5 operates in a manner similar to the pixel cell described above with reference to FIGS.  1 - 4  in terms of collecting and reading out charges to the readout circuit  60 . In addition, FIG. 5 also shows a fifth doped region  155  which is formed adjacent to the photogate  102  and serves to transfer charge to a storage capacitor  162  from the photosensitive area under the photogate by contact  150 .  
         [0052]    One means of forming the storage capacitor  162  is shown in FIG. 5. The storage capacitor  162  is formed over the substrate  116  as described below. An insulating layer  106  is formed over the substrate containing the pixel cell active area, including the photogate and the pixel transistors. The insulating layer  106  may be formed of BPSG (borophosphorosilicate glass), BSG (borosilicate glass), PSG (phosphorosilicate glass), USG (undoped silicate glassy or the like as described further below provided that the material does not block light to the photosensor (in the illustrated embodiment, this is a photogate). A portion of the insulating layer  106  is etched away to form a conduit which is filled with conductive material forming a contact  150 . Contact  150  connects the region  155  which is coupled to the charge accumulation area under the photogate  102  to a first electrode  156  of storage capacitor  162 . The storage capacitor  162  is illustrated in FIG. 5 as a planar plate capacitor. The storage capacitor  162  has first electrode  156 , a second electrode  160 , and a dielectric layer  158  formed therebetween. Second electrode  160  is preferably connected to a ground potential source. The storage capacitor  162  is formed such that it does not block the photosensitive area of the imager. As shown in FIG. 5, the storage capacitor  162  overlies at least a portion of the field oxide  115 ; however, it should be understood that the storage capacitor  162  may be formed over any non-photosensitive area, such as, for example, over the transfer gate  128 , the reset gate  132 , the source follower transistor  136 , or the row select transistor  138  where the capacitor would additionally and advantageously also function as a light shield.  
         [0053]    The CMOS imager illustrated in FIG. 5 is fabricated by a process described as follows, and illustrated by FIGS. 6 through 14. Referring now to FIG. 6, a substrate  116 , which may be any of the types of substrates described above, is doped to form a doped substrate layer  120  of a first conductivity type, which for exemplary purposes will be described as p-type. The substrate layer  120  is masked and doped region  110  is formed in the substrate  120 . Any suitable doping process may be used, such as ion implantation.  
         [0054]    Referring now to FIG. 7, an insulating layer  100  is now formed over the substrate  116  by thermal growth or chemical vapor deposition, or other suitable means. The insulating layer  100  may be of silicon dioxide, silicon nitride, or other suitable insulating material, and has a thickness of approximately 2 to 100 nm. It is formed to completely cover the substrate  116 , and to extend to the field oxide layer  115 .  
         [0055]    Referring now to FIG. 8, the transfer gate stack  128 , reset transistor gate stack  132 , and photogate  102  are now formed. The photogate  102  includes silicon dioxide or silicon nitride insulator  100  on the doped layer  120  and a conductive layer  108  over the insulating layer. Conductive layer  108  is formed of a doped polysilicon or other transparent conductors. The thickness of the conductive layer  108  in photogate  102  may be any suitable thickness, e.g., approximately 200 to 5000 Angstroms.  
         [0056]    Conductive layers  108  in gates  128  and  132  may be formed of doped polysilicon, a refractory metal silicide such as tungsten, tantalum, or titanium silicides or other suitable materials such as a barrier/metal. The conductive material is formed by CVD or other suitable means. A silicide or barrier/metal layer (not shown) may be used as part of the polysilicon layer, if desired. The gate stacks may be formed by applying layers  108  (and a silicide layer, if used) over the substrate and then etching them to form gate stacks  102 ,  128  and  132 . Insulating sidewalls  112  are also formed on the sides of the gate stacks  102 ,  128 ,  132 . These sidewalls may be formed of, for example, silicon dioxide, silicon nitride, or ONO: While these gate stacks may be formed before or after the process of the photogate  102  described below, for exemplary purposes and for convenience the photogate formation has been described as occurring during transistor gate stack formation.  
         [0057]    After spacer formation  112 , doped regions  126 ,  130 ,  134  and  155  are then formed in the doped layer  120 . Any suitable doping process may be used, such as ion implantation. A resist and mask (not shown) are used to shield areas of the layer  120  that are not to be doped. Four doped regions are formed in this step: doped region  126 , which forms a transfer region; doped region which is floating diffusion region  130  (which connects to the source follower transistor  136  by contact  144  as shown in FIG. 5); doped region which is a drain region  134 ; and doped region  155  which serves to connect the photocollection area with the storage capacitor  162 . The doped regions  126 ,  130 ,  134  and  155  are doped to a second conductivity type, which for exemplary purposes will be considered to be n-type. Several masks may be used to implant the regions  126 ,  130 ,  134  and  155  to the same or different doping concentrations. Preferably, the doped regions  126 ,  130 ,  134  and  155  are heavily n-doped with arsenic, antimony or phosphorous at a dopant concentration level of from about 1×10 15  ions/cm 2  to about 1×10 16  ions/cm 2 .  
         [0058]    Reference is now made to FIG. 9. The photosensor cell is essentially complete at this stage, and conventional processing methods may now be used to form contacts and wiring to connect gate lines and other connections in the pixel cell. The entire surface of the substrate  116  is covered with an insulating layer  106  of, e.g., silicon dioxide, USG, BPSG, PSG, BSG or the like which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts to the photogate, reset gate, and transfer gate. Conventional multiple layers of conductors and insulators may also be used to interconnect the structures in the manner shown in FIG. 1.  
         [0059]    Reference is now made to FIG. 10 to show how contact  150  and capacitor  162  are formed. A resist and mask (not shown) are applied to the insulating layer  106  and photolithographic techniques are used to define the area to be etched out to form holes for contact  150  to the fourth doped layer  155 . This etching may be done at the same time as the etching for the contact holes for the photogate, reset gate and transfer gate contacts as described above The contact  150  may be formed in the etched hole by depositing therein a conductive material, such as doped polysilicon, or a metal such as titanium/titanium nitride/tungsten.  
         [0060]    Reference is now made to FIG. 11. After the etched hole has conductor  150  formed therein a first conductive layer  156 , which forms a first electrode of the capacitor  162 , is deposited over the insulating layer  106  after application of a resist and mask (not shown). The term electrode, as used herein, shall be understood to mean any material that is electrically conducting. The conductive layer  156  may be formed of any conductive material. Non-limiting examples of materials that may be used to form the conductive layer  156  are doped polycrystalline silicon (referred to herein as polysilicon or poly), platinum, tungsten, TiN, refractory metals, RuO 2 , Ir, IrO 2 , Rh, RhO X , and alloys, such as Pt—Ru or Pt—Rh. The conductive layer  156  may be formed on the insulating layer  106  by CVD, LPCVD, PECVD, MOCVD, sputtering or other suitable deposition techniques. The conductive layer  156  formed during deposition which overlies the photogate is next removed from the insulating layer  106  by known techniques, such as wet or dry etching.  
         [0061]    Reference is now made to FIG. 12. A dielectric layer  158  is formed over conductive layer  156 . The term dielectric or insulator as used herein shall be understood to mean any solid, liquid or gaseous material that can sustain an electrical field for use in the capacitor of an integrated circuit device containing a capacitor. The dielectric layer  158  may be formed of any insulating material such as oxides, such as silicon oxide, nitrides, such as silicon nitride, ONO, NO (nitride oxide), ON (oxide nitride), high-k dielectrics such as Ta 2 O 5  or BST, ferroelectrics or the like. The preferred dielectric layer is a nitride layer which can be formed using various known methods such as CVD deposition, rapid thermal nitridation (RTN) processing or the like.  
         [0062]    Reference is now made to FIG. 13. A second conductive layer  160 , which forms the second electrode of the capacitor  162 , is patterned and formed over the dielectric layer  158  in a method similar to that of the first conductive layer  156 . The second conductive layer  160  may be formed of the same or difference conductive materials from those used for the first conductive layer  156 . Preferably, both the first and second conductive layers are formed of doped polysilicon with a nitride dielectric layer  158  formed between the two conductive layers  156 ,  160 . A passivation layer  164  is then deposited over the capacitor  162  as shown in FIG. 14. The passivation layer  164  may be any material, such as USG, BPSG, PSG, BSG, provided that the material does not interfere with the collection of light in the photoarea. A hole is etched and a metal contact  166  is formed therein in the passivation layer  164  to connect the second electrode  160  of the capacitor  162  to an electrical circuit, e.g., a ground source potential. As set forth above, the storage capacitor  162  may be formed over any non-photosensitive area of the pixel cell  114 . For example, the storage capacitor  162  may be formed over the transfer transistor  128 , the reset transistor  132 , the source follower transistor  136  or the row select transistor  138 .  
         [0063]    It should be understood that fabrication of the FIG. 5 structure is not limited to the methods described with reference to the attached figures. For example, the doped regions  110 ,  126 ,  130 ,  134  and  155  may be formed in the doped layer  120  after the transistor gates  102 ,  128 ,  132  are formed over the substrate, as discussed below, by masking the transistor gates  102 ,  128  and  132  and forming the doped regions  110 ,  126 ,  130 ,  134  and  155  in the doped layer  120  so as to form self-aligned gates. Additionally, the first conductive layer  156 , the dielectric layer  158  and the second conductive layer  160  may be deposited together and over the entire substrate and then etched away to form capacitor  162 .  
         [0064]    The structure of a pixel cell of a second embodiment of the present invention is shown in FIG. 15. The pixel cell  314  may be formed in a substrate  316  having a doped layer  320  of a first conductivity type, which for exemplary purposes is treated as a p-type substrate. A field oxide layer  315 , which serves to surround and isolate the cells may be formed by thermal oxidation of the doped layer  320 , or by chemical vapor deposition of an oxide material. The doped layer  320  is provided with five doped regions  310 ,  326 ,  330 ,  334  and  355 , which are doped to a second conductivity type. For exemplary purposes regions  326 ,  330 ,  334 , and  355  are treated as n+type. The first doped region  310  is formed under photogate  302  to collect charge and may also be doped n+. Second doped region  326  serves to electrically connect the photosite diffusion  310  to the transfer gate transistor  322 . An insulating layer  300  of silicon dioxide, silicon nitride, or other suitable material is formed between the photogate  302  and the photosensitive diffusion  310 , and extends to the pixel-isolating field oxide region  315  and over a surface of the doped layer  320  of the substrate  316 .  
         [0065]    The third doped region  330  is the floating diffusion region, sometimes also referred to as a floating diffusion node. The floating diffusion region  330  is connected to source follower transistor  336  by a diffusion contact line  344  which is typically a metal contact line. The source follower transistor  336  outputs the charge accumulated in region  326  via the floating diffusion region  330  and diffusion contact line  344  via transistor  338  to a readout circuit as discussed above.  
         [0066]    The fourth doped region  334  is the drain of the reset transistor  332 , and is also connected to voltage source VDD. The pixel cell thus far described with reference with FIG. 15 operates in a manner similar to the pixel cell described above with reference to FIGS.  1 - 4  in terms of collecting and reading out charges to the readout circuit  60 . In addition, FIG. 15 shows a fifth doped region  355  which is formed adjacent to the photogate  302  and serves to transport charge to a trench storage capacitor  362  from the photosensitive area under the photogate.  
         [0067]    The trench storage capacitor  362  is formed in the substrate  316 . The trench storage capacitor  362  is formed of a first electrode  356  and a second electrode  360  with a dielectric layer  358  therebetween. The second electrode  360  is preferably connected to a ground source. The trench storage capacitor  362  is formed in the pixel cell  314  such that it takes up as little area of the photocollection area as possible. The CMOS imager of the invention is manufactured by a process described as follows, and illustrated by FIGS. 16 through 22. Referring now to FIG. 16, substrate  316 , which may be any of the types of substrates described above, is doped to form a doped substrate layer  320  of a first conductivity type, which for exemplary purposes will be described as p-type. The substrate layer  320  is masked and doped region  310  is formed in the substrate  320 . Any suitable doping process may be used, such as ion implantation.  
         [0068]    Referring now to FIG. 17, an insulating layer  300  is now formed over the substrate  316  by thermal growth or chemical vapor deposition, or other suitable means. The insulating layer  300  may be of silicon dioxide, silicon nitride, or other suitable insulating material, and has a thickness of approximately 2 to 100 nm. It is formed to completely cover the substrate  316 , and to extend to the field oxide layer  315 .  
         [0069]    Referring now to FIG. 18, the transfer gate stack  328 , reset transistor gate stack  332 , and photogate  302  are now formed. The photogate  302  includes silicon dioxide or silicon nitride insulator  300  on the doped layer  320  and a conductive layer  308  over the insulating layer. Conductive layer  308  is formed of a doped polysilicon or other transparent conductors. The thickness of the conductive layer  308  in photogate  302  may be any suitable thickness, e.g., approximately  200  to  5000  Angstroms.  
         [0070]    Conductive layers  308  in gates  328  and  332  may be formed of doped polysilicon, a refractory metal silicide such as tungsten, tantalum, or titanium silicides or other suitable materials such as a barrier/metal. The conductive material is formed by CVD or other suitable means. A silicide or barrier/metal layer (not shown) may be used as part of the polysilicon layer, if desired. The gate stacks may be formed by applying layers  308  (and a silicide layer, if used) over the substrate and then etching them to form gate stacks  302 ,  328  and  332 . Insulating sidewalls  312  are also formed on the sides of the gate stacks  302 ,  328 ,  332 . These sidewalls may be formed of, for example, silicon dioxide, silicon nitride, or ONO. While these gate stacks may be formed before or after the process of the photogate  302  described below, for exemplary purposes and for convenience the photogate formation has been described as occurring during transistor gate stack formation.  
         [0071]    The doped regions  326 ,  330 ,  334  and  355  are then formed in the doped layer  320 . Any suitable doping process may be used, such as ion implantation. A resist and mask (not shown) are used to shield areas of the layer  320  that are not to be doped. Four doped regions are formed in this step: doped region  326 , which forms a transfer region; doped region which is floating diffusion region  330  (which connects to the source follower transistor  336  by contact  344  as shown in FIG. 15); doped region which is a drain region  334 ; and doped region  355  which connects the photocollection area with the trench storage capacitor  362 . The doped regions  326 ,  330 ,  334  and  355  are doped to a second conductivity type, which again for exemplary purposes will be considered to be n-type. Preferably, the doped regions  326 ,  330 ,  334  and  355  are heavily n-doped with arsenic, antimony or phosphorous at a dopant concentration level of from about 1×10 15  ions/cm 2  to about 1×10 16  ions/cm 2 .  
         [0072]    Reference is now made to FIG. 19. An insulating layer  367  e.g., silicon dioxide or BPSG, which is CMP planarized, is formed over the device. A trench  366  is next formed in the insulating layer  367  and doped layer  320 . A resist and mask (not shown) are applied, and photolithographic techniques are used to define the area to be etched-out. A directional etching process such as Reactive Ion Etching (RIE), or etching with a preferential anisotropic etchant is used to etch into the doped layer  320  to a sufficient depth, e.g., about 200 to 2000 nm, to form a trench  366 . The depth of the trench  366  should be sufficient to form the trench capacitor  362  of the present invention therein. The resist and mask are removed, leaving a structure that appears as shown in FIG. 19.  
         [0073]    Reference is now made to FIG. 20. A first conductive layer  356 , which forms a first electrode of the capacitor  362 , is deposited in the trench  366 . The conductive layer  356  may be formed of any conductive material. The conductive layer  356  is coupled to the charge accumulation area under the photogate  302  by fourth doped region  355  by the conductive layer  356  being formed adjacent and in contact with fourth doped region  355 . Non-limiting examples of materials that may be used to form the conductive layer  356  are doped polysilicon, platinum, tungsten, TiN, refractory metals, RuO 2 , Ir, IrO 2 , Rh, RhO X , and alloys, such as Pt—Ru or Pt—Rh. The conductive layer  356  may be formed in the trench  366  by CVD, LPCVD, PECVD, MOCVD, sputtering or other suitable deposition techniques.  
         [0074]    Reference is now made to FIG. 21. A dielectric layer  358  is formed over conductive layer  356 . The dielectric layer  358  may be formed of any insulating material such as oxides, including silicon oxide, nitrides, such as silicon nitride, ONO, NO, ON, high-k dielectrics, such as Ta 2 O 5 , BST and ferroelectrics or the like as described above. A second conductive layer  360 , which forms the second electrode of the capacitor  362 , is formed over the dielectric layer  358  in a method similar to that of the first conductive layer  356 , as shown in FIG. 22. The first and second conductive layers  356 ,  366  may be formed of the same or different materials.  
         [0075]    The pixel cell  314  of the second embodiment is essentially complete at this stage, and conventional processing methods may then be used to form contacts and wiring to connect gate lines and other connections in the pixel cell  314 . For example, the entire surface may then be covered with an insulating layer of, e.g., silicon dioxide or BPSG, which is CMP planarized and etched to provide contact holes, which are then metallized to provide contacts to the photogate, reset gate, and transfer gate. Conventional multiple layers of conductors and insulators may also be used to interconnect the structures in the manner shown in FIG. 1.  
         [0076]    It should be understood that fabrication of the FIG. 15 structure is not limited to the methods described with reference to the attached figures. For example, the doped regions  310 ,  326 ,  330 ,  334  and  355  may be formed in the doped layer  320  after the transistor gates  302 ,  328 ,  332  are formed over the substrate, as discussed below, by masking the transistor gates  302 ,  328  and  332  and forming the doped regions  310 ,  326 ,  330 ,  334  and  355  in the doped layer  320  so as to form self-aligned gates.  
         [0077]    A third embodiment of the present invention is described with reference to FIG. 23. It should be understood that similar reference numbers correspond to similar elements as previously described with reference to FIGS. 614 and 16- 22 . The structure set forth in FIG. 23 differs from the above described embodiments in that a stacked storage capacitor  373  is formed in the insulating layer  106  to store charge collected under photogate  102 . The processing of the third embodiment is similar to the processing described above with reference to FIGS.  6 - 9 . A hole is etched in the insulating layer  106  down to the fourth doped region  155  and a conductor is formed therein as shown in FIG. 10 to create contact  375 ; however the etched hole is not filly filled with the conductive material which forms contact  375 . The conductor may be formed as a doped polysilicon plug, or as a metallized conductor. A trench  378  is then formed, for example, by etching, in the insulating layer  106  similar to that formed in the substrate as shown in FIG. 19 and a storage capacitor  373  is then formed as described above with reference to FIGS.  19 - 22 . A first conductive layer  376  is formed in the trench  378  which contacts with the fourth doped region  155  through contact  375 . A dielectric layer  379  is formed over the first conductive layer  376 . A second conductive layer  380  is then formed over the dielectric layer  379  to form the storage capacitor  373 . Non-limiting examples of materials that may be used to form the conductive layers  376  and  380  are doped polysilicon, platinum, tungsten, TiN, refractory metals, RuO 2 , Ir, IrO 2 , Rh, RhO X , and alloys, such as Pt—Ru or Pt—Rh. The conductive layers  376  and  380  may be formed in the trench  366  by CVD, LPCVD, PECVD, MOCVD, sputtering or other suitable deposition techniques. The storage capacitor  373  formed in the insulating layer  106  has the advantages that the storage capacitor  373  is formed in the insulating layer  106  and not in the substrate thereby improving the charge storage capacity of the imager without reducing the size of the photosensitive area.  
         [0078]    It should be understood that while the illustrated embodiments show the storage capacitors  162 ,  362 ,  373  connected to the substrate through doped region  155 ,  355 , it is also possible to dispense with region  155 ,  355  and have the storage capacitors  162 ,  362 ,  373  connect directly with region  126  using the same basic structure illustrated in FIGS. 5, 15 and  23 .  
         [0079]    A typical processor based system which includes a CMOS imager device according to the present invention is illustrated generally at  400  in FIG. 24. A processor based system is exemplary of a system having digital circuits which could include CMOS imager devices. Without being limiting, such a system could include a computer system, camera system, scanner, machine vision system, vehicle navigation system, video telephone, surveillance system, auto focus system, star tracker system, motion detection system, image stabilization system and data compression system for high-definition television, all of which can utilize the present invention.  
         [0080]    A processor system, such as a computer system, for example generally comprises a central processing unit (CPU)  444  that communicates with an input/output (I/O) device  446  over a bus  452 . The CMOS imager  442  also communicates with the system over bus  452 . The computer system  400  also includes random access memory (RAM)  448 , and, in the case of a computer system may include peripheral devices such as a floppy disk drive  454  and a compact disk (CD) ROM drive  456  which also communicate with CPU  444  over the bus  452 . CMOS imager  442  is preferably constructed as an integrated circuit which includes pixels containing a photosensor such as a photogate or photodiode formed in a trench, as previously described with respect to FIGS.  5  through  12 . The CMOS imager  442  may be combined with a processor, such as a CPU, digital signal processor or microprocessor, in a single integrated circuit.  
         [0081]    As can be seen by the embodiments described herein, the present invention encompasses a photosensor including a storage capacitor connected in parallel to the charge collection area of the imager. The imager has an improved charge capacity due to the increase in the charge storage by the capacitor.  
         [0082]    It should again be noted that although the invention has been described with specific reference to CMOS imaging circuits having a photogate and a floating diffusion region, the invention has broader applicability and may be used in any CMOS imaging apparatus. Also, although exemplary capacitor structures have been described and illustrated many variations in capacitor structure could be made. Similarly, the processes described above are merely exemplary of many that could be used to produce the invention. The above description and drawings illustrate preferred embodiments which achieve the objects, features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Any modification of the present invention which comes within the spirit and scope of the following claims should be considered part of the present invention.