PATENT ABSTRACT
A fine granularity, wide-range variable gain amplifier (“VGA”) comprises an attenuator, a high gain signal path, a low gain signal path and a gain adjustment control to adjust a gain of the VGA, wherein the gain adjustment control is configured to cause a selective activation of at least a portion of the low gain signal path or the high gain signal path to achieve a desired overall gain.

PATENT DESCRIPTION
CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims priority under 35 U.S.C. §119(e) to Provisional Patent Application 60/840,123, filed Aug. 25, 2006, and titled “Digital Electronic Dispersion Compensation for Multi-Mode Fiber.” 

   TECHNICAL FIELD 
   This description relates to analog circuits. In particular, this description relates to an amplifier and associated circuit topology for achieving variable gain amplification with high bandwidth and fine granularity promoting high linearity. 
   BACKGROUND 
   In many applications it may be necessary to amplify an analog signal exhibiting a wide amplitude range. For example, a wide range of input signals may be present at the receiving end of a multi-mode fiber optic cable. Such a signal may require analog conditioning or digital signal processing to correct for degradation introduced by the physical medium of transmission, i.e., the optical cable itself. 
   In many signal conditioning systems especially communication links, in order to compensate for a wide amplitude range of received information bearing signals, the input signals are subjected to amplitude adjustment using a VGA (“Variable Gain Amplifier”). A VGA allows for the selection and adjustment of gain to be applied to an input signal. Amplitude adjustment or so called gain adjustment of an incoming signal by a VGA is used to achieve an amplitude level well above the noise and offset thresholds. Without the application of gain adjustment, it may not be feasible to perform further post processing of an incoming signal, such as adaptive equalization. 
   Cascading gain stages may provide a wide range of amplification and/or attenuation. However, each additional stage may be undesirable as it will introduce harmonic distortion. Harmonic distortion typically arises due to non-linearities inherent in each stage. 
   Thus, it is desirable to devise an amplitude adjustment scheme using a VGA with a low number of gain stages such that the VGA is suitable for high bandwidth and high linearity applications with a wide amplitude adjustment range. 
   SUMMARY 
   According to one general aspect, a high bandwidth, a fine granularity variable gain amplifier (“VGA”) is described comprising a gain block, the gain block comprising at least one input node, a low gain output tap and a high gain output tap, a parallel gain block, wherein the parallel gain block comprises a low gain signal path and a high gain path, the low gain signal path and the high gain signal path respectively coupled to the low gain output tap and the high gain output tap of the attenuator, a cascaded gain block, wherein the low gain signal path and the high gain signal path are coupled to an input of the cascaded gain block, and a gain adjustment control to adjust a gain of the VGA, wherein the gain adjustment control is configured to cause a selective activation of at least a portion of the low gain path or the high gain path in the parallel gain path to achieve a desired overall gain. 
   According to another general aspect, a method for providing variable gain amplification of an input signal with high bandwidth and high linearity is described comprising configuring a low gain signal path and a high gain signal path, receiving an input signal, passively generating a first attenuated signal and a second attenuated signal from the input signal, the first attenuated signal having a larger attenuation than the second attenuated signal, generating a low gain amplified signal from the first attenuated signal and a high gain amplified signal from the second attenuated signal via respectively the low gain signal path and the high gain signal path, generating a composite signal by combining the low gain signal and the high gain signal, and amplifying the composite signal to generate a VGA output signal. 
   The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a VGA for achieving a high gain output signal from a received input signal with high bandwidth and linearity. 
       FIG. 2  is a flowchart illustrating example operations of the VGA topology of  FIG. 1 . 
       FIG. 3  is a schematic of a VGA with high bandwidth and high linearity that incorporates differential signaling. 
       FIG. 4  is schematic of a cascaded gain stage. 
       FIG. 5  is a schematic of a parallel gain block. 
       FIG. 6  is a schematic of a differential pair that may be utilized as a gm element in a parallel gain stage or a cascade gain stage. 
       FIG. 7  is a flowchart of a process for selecting a gain for a VGA. 
   

   DETAILED DESCRIPTION 
     FIG. 1  is a block diagram of a VGA topology  100  for achieving a high gain output signal  122  having substantially high bandwidth and linearity from a received input signal  120 . The VGA topology may receive an input signal  120  which is passed to a gain block  102 , a parallel gain block  112 , and a cascade gain block  110  to produce a VGA output signal  122 . Although  FIG. 1  depicts single-ended signals, it will be understood by skilled practitioners that the topology shown in  FIG. 1  may be utilized with differential signals. 
   The gain block  102  may compensate for a wide range of input signal  120  amplitudes. The gain block  102  may provide gain greater than unity, in which case it may function as an amplifier. Alternatively, the gain block  102  may provide gain less than unity in which case it may function as an attenuator. 
   According to one embodiment, the gain block  102  may be an attenuator that comprises passive components to achieve attenuation of the input signal with high bandwidth. For example, the gain block  102  may comprise a resistive ladder, including a plurality of resistors (described below with reference to  FIG. 3 ). The gain block  102  may comprise a plurality of output taps (e.g.,  124 ,  126 ) that provide output signals at various attenuation amplitudes. For example, output tap  124  may provide a high gain output (ATT 1 ) feeding high gain signal path  120  while output tap  126  may provide a low gain output (ATT 2 ) feeding low gain signal path  122 . 
   The parallel gain block  112  may include a plurality of parallel gain stages  104 ,  106 . Although only two parallel gain stages  104 ,  106  are shown in  FIG. 1 , it will be understood by skilled practitioners that the parallel gain block may include an arbitrary number of parallel gain stages (e.g.,  104 ,  106 ). As described below, the parallel gain stages  104 ,  106  may each respectively comprise a plurality of gm cells (not shown in  FIG. 1  but described below). Gm refers to a transconductance of a simple amplification circuit in which a voltage signal is received at an input to generate a current signal at an output. Both parallel gain stages  104 ,  106  may be identical comprising identical gm stages with identical current densities and to minimize phase delay between the respective outputs of the gain stages  104 ,  106 . 
   The parallel gain stages  104 ,  106  in parallel gain block  112  may respectively be placed in the high gain signal path  120  and the low gain signal path  122 . In particular, the high gain signal path  120  may be coupled to the high gain output tap  124  of gain block  102  while the low gain signal path  122  may be coupled to the low gain output tap  126  of the gain block  102 . As described below, depending upon the particular combination of gm stages comprising each of the parallel gain stages  104 ,  106  that may be selectively activated, various amplification levels may be achieved at summing block  108 . The number of combinations of gm stages that may be activated may directly provide fine granular control of the amplification level (e.g., each combination may provide a varying level of gain adjustment). A digital control block  124  may be utilized to control the activation of gm stages within parallel gain block  112 . One particular example of a process for selecting a gain for a VGA is illustrated below with respect to  FIG. 7 . 
   The outputs of the parallel gain block  112  (e.g., parallel gain stages  104 ,  106 ) may be summed at a summing block  108  to provide an input to a cascade gain block  110 . Although  FIG. 1  shows only two summed gain stages ( 104 ,  106 ), it will be understood by skilled practitioners that any arbitrary number of parallel gain stages comprising a parallel gain block  112  may be summed at the summing block  108 . 
   The summed output signals from the parallel gain block  112  may be received by a cascade gain block  110  where the summed signal is amplified by one or more cascaded gain stages (e.g.,  114 ( 1 ),  114 ( 2 ),  114 ( 3 )). Although the cascade gain block  110  shown in  FIG. 1  shows three cascaded gain stages  114 ( 1 ),  114 ( 2 ) and  114 ( 3 ), it will be understood by skilled practitioners that the cascade gain block  110  may include any number of cascaded gain stages. The output signal  122  of the cascade gain block  110  may then further processed. Inductive peaking may be utilized at the output of every gain stage in order to reduce phase delay problems and increase bandwidth. 
     FIG. 2  is a flowchart illustrating example operations of the VGA topology of  FIG. 1 . The process is initiated ( 202 ). A low gain signal path and a high gain signal path may be configured ( 204 ). As described with respect to  FIG. 1 , the low gain signal path and high gain signal path may each respectively comprise a separate gain stage further, each gain stage further comprising a plurality of amplification elements. Each of the amplification elements may be selectively activated or deactivated via the digital control block  124 . An input signal that is to be amplified may be received ( 206 ). A low gain attenuated signal and a high gain attenuated signal may be respectively generated ( 208 ). The generation of the low and high gain attenuated signals may be achieved via the gain block  102 . A low gain amplified signal and a high gain amplified signal may be respectively generated from the low gain attenuated signal and the high gain attenuated signal via the low gain signal path and the high gain signal path ( 210 ). A composite signal may be generated by combining the low gain amplified signal and the high gain amplified signal ( 212 ). This combination may be achieved, for example, by summing the low gain amplified signal and the high gain amplified signal at a common node. The composite signal may then be further amplified to generate a VGA output signal ( 214 ). This further amplification may be achieved in a cascaded fashion. VGA amplification may now be completed ( 216 ). 
     FIG. 3  is a schematic of a VGA amplifier  300  with high bandwidth and high linearity that incorporates differential signaling.  FIG. 3  provides a specific example of the topology shown in  FIG. 1 . The VGA may include a gain block  102 , a parallel gain block  112  and a cascade gain block  110 . A differential signal (not shown in  FIG. 3 ) may be received via differential inputs Inp  302  and Inn  304  at gain block  102 . The gain block  102  may be an attenuator that comprises a resistive ladder having a plurality of resistors (e.g., R 1   304 , R 2   306 , R 3   308 , R 4   310 , R 5   312  and R 6   314 ). 
   The gain block  102  may provide various output taps for generating differential output signals having various levels of attenuation. For example, the gain block  102  may generate high gain differential signals (ATT 1 P  316 , ATT 1 N  318 ) and low gain differential signals (ATT 2 P  322 , ATT 2 N  324 ). Thus, the gain block  102  may include output taps  316  generating signal ATT 1 P, output tap  318  generating signal ATT 1 N, output tap  322  generating signal ATT 2 P and output tap  324  generating signal ATT 2 N. In the case where the gain block  102  is an attenuator using passive components, the various amplitude output signals from the gain block  102  may be generated via the technique of a voltage divider using a resistive ladder as shown in  FIG. 3 . The ATT 1 N and ATT 2 N signals shown in  FIG. 3  may correspond to the following amplitudes: 
   
     
       
         
           
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   Similarly the ATT 2 N and ATT 2 P signals shown in  FIG. 3  may correspond to the following amplitudes: 
   
     
       
         
           
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   High gain differential signal (ATT 1 P, ATT 1 N) and low gain differential signal (ATT 2 P, ATT 2 N) may be respectively provided to parallel block  112 . In particular, as shown in  FIG. 3  the high gain differential signal (ATT 1 P, ATT 1 N) may be provided to a first differential parallel gain stage  326  while low gain differential signal (ATT 2 P, ATT 2 N) may be provided to a second differential parallel gain stage  328 . Each of the differential parallel gain stages ( 326 ,  328 ) may provide amplification of their respective input signals. According to one embodiment, parallel gain stages  326  and  328  may be identical providing identical amplitude gain and phase delay. It is also possible to achieve a unity gain by omitting resistor R 1 . 
   The differential outputs of the parallel gain block  112  may be provided to a cascade gain stage  110  where they are summed at respective common differential node inputs ( 338 ,  340 ). The differential signal provided to cascade gain block  110  may then be amplified by any number of cascaded gain stages (e.g.,  330 ( 1 ),  330 ( 2 ),  330 ( 3 ),  330 ( 4 )) to generate differential outputs  342  and  344 . Although  FIG. 3  shows only four cascaded gain stages, it will be understood that cascade gain stage  110  may include any arbitrary number of cascaded gain stages. 
     FIG. 4  is schematic of a cascaded gain stage  110 . Any number of cascaded gain stages  330  may be included in a cascade gain block  110 . Each cascaded gain stage  330  may include any number of gm elements  408 ( 1 )- 408 ( m ) (described below with reference to  FIG. 6 ), which in aggregate operation achieve a gain for the cascaded gain stage  330 . In particular, each gm element  408 ( 1 )- 408 ( m ) may be selectively activated or deactivated to adjust an overall gain for the cascaded gain stage  330 . Each of the gm elements may be viewed as a separate amplification element for the stage. Each of the gm elements  408 ( 1 )- 408 ( m ) may be a differential pair arranged in a common source configuration as described below with reference to  FIG. 6 . 
   The gm elements  408 ( 1 )- 408 ( m ) may all respectively be coupled at their source nodes to a tail transistor  402  that may operate as a current source. Further, the gm elements  408 ( 1 )- 408 ( m ) may all respectively be coupled to a load block ZLOAD  416 , which may comprise either a passive load such as a resistor or an active load possibly generated using one or more MOSFET transistors. 
   A voltage source AVDD  406  may be coupled to the load block ZLOAD  416 , to provide a voltage bias. The source of the tail transistor  404  may be coupled to a common voltage reference AVSS  404 . Differential input signal INP 1   338  and INN 1   340  may be provided as input to each of the gm elements  408 ( 1 )- 408 ( m ). The input differential signal INP 1   338  and INN 1   340  may be amplified by each of the gm elements  408 ( 1 )- 408 ( m ) to generate a composite amplified differential signal OUTP 1   410  and OUPTN 1   412 . 
     FIG. 5  is a schematic of a parallel gain block  112 . The parallel gain block  112  may include a first differential parallel gain stage  326  and a second differential parallel gain stage  328 . Each parallel gain stage  326 ,  328  may include any number of gm elements (respectively  408 ( 1 )- 408 (n) and  408 (n+1)- 408 (n+o)) (described below with reference to  FIG. 6 ), which in aggregate operation achieve a gain for each of the parallel gain stages  326  and  328  in the parallel gain block  112 . In particular, each gm element  408 ( 1 )- 408 ( n ) and  408 ( n+ 1)- 408 ( n +o) may be selectively activated or deactivated to adjust an overall gain for their respective gain stages  326 ,  328 . Each of the gm elements  408 ( 1 )- 408 ( n ) and  408 ( n+ 1)- 408 ( n+o ) may be a differential pair arranged in a common source configuration as described below with reference to  FIG. 6 . 
   The gm elements  408 ( 1 )- 408 ( n ),  408 ( n+ 1)- 408 ( n+o ) may all respectively be coupled to a tail transistor  514  that may operate as a current source. Further, the gm elements  408 ( 1 )- 408 ( n ),  408 ( n+ 1)- 408 ( n+o ) may all respectively be coupled to a load block ZLOAD  516 , which may comprise either a passive load such as a resistor or an active load possibly generated using one or more MOSFET transistors. 
   A voltage source AVDD  406  may be coupled to the load block ZLOAD  516 , to provide a voltage bias. The source of the tail transistor  514  may be coupled to a common voltage reference AVSS  404 . Differential input signal INP 2   502 , INN 2   504  may be provided as input to the first parallel gain stage  326 , while differential input signal INP 3   518 , INN 3   520  may be provided as an input to the second differential parallel gain stage  328 . Each of the differential signals (INP 2   502 , INN 2   504  and INP 3   518 , INN 3   520 ) may be amplified by the respective parallel gain stages  326 ,  328  to generate respective outputs (not shown in  FIG. 5 ), which are combined at a common node to produce a differential output signal OUTP 2   510 , OUTN 2   512 . 
     FIG. 6  is a schematic diagram of a differential pair that may be utilized as a gm element in a parallel gain stage or a cascade gain stage. The differential pair  600  may include a first input transistor  602  and a second input transistor  604  respectively receiving input signals Inp  606  and Inn  608 . Although the differential pair  600  shown in  FIG. 6  utilizes nmos transistors for input transistors  602 ,  604 , the input transistors  602 ,  604  may also be pmos transistors. The substrate of each of the input transistors  602 ,  604  may be coupled to a common substrate node Vsub  606 . 
     FIG. 7  is a flowchart that illustrates a process for increasing or decreasing the gain achieved with a VGA. The process is initiated in step  702 . In step  704 , a set of gm elements in the low gain path  122  may be activated. In step  706 , the gain may be increased by turning on a set of gm elements in the cascade block  110 . In step  708 , the gain may be further increased by turning on gm elements in the high gain path  120  while correspondingly turning off the same number of gm elements in the low gain path  122 . By turning on and off corresponding numbers of gm elements in the low gain  122  and high gain paths  120  insures maintenance of a fixed common mode. Of course the overall gain for the VGA may be lowered by following the process as shown in  FIG. 7  in reverse order. 
   The source nodes of each of the input transistors  602 ,  604  may both be coupled together at a common node  610 , which is also coupled to a third transistor Mena  612 . The third transistor Mena  612  may itself be coupled to a current source, for example a common current source transistor such as Mtail  514  shown in  FIG. 5 . The differential pair  600  may be selectively activated or deactivated by respectively turning transistor Mena  612  on or off. Gain may be achieved for the differential pair  600  by steering current from the source/drain of transistor Inp  606  and the source/drain of transistor Inn  608 . The third transistor Mena  612  may receive bias signal Vena  614 , with its substrate node biased by a signal Vsub_ena  610 . 
   The various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Furthermore, these techniques may also be implemented as a computer program product, i.e., a computer program tangibly embodied in an information carrier, e.g., in a machine-readable storage device or in a propagated signal, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple computers. A computer program, such as the computer program(s) described above, can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network. 
   Method steps may be performed by one or more programmable processors executing a computer program to perform functions by operating on input data and generating output. Method steps also may be performed by, and an apparatus may be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). 
   Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Elements of a computer may include at least one processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also may include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory may be supplemented by, or incorporated in special purpose logic circuitry. 
   To provide for interaction with a user, implementations may be implemented on a computer having a display device, e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. 
   Implementations may be implemented in a computing system that includes a back-end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front-end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation, or any combination of such back-end, middleware, or front-end components. Components may be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), e.g., the Internet. 
   While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the various embodiments.