PATENT ABSTRACT
Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator.

PATENT DESCRIPTION
TECHNICAL FIELD 
     The present disclosure relates to circuitry, such as oscillators, for wireline and wireless communications. 
     BACKGROUND 
     The crystal oscillator is typically the source of frequency stability for various communications systems. The crystal is typically made of quartz and has resonating capabilities. Quartz is a material with piezoelectric properties that can be cut at certain angles and thicknesses to provide electrical and mechanical stability in radio frequency (RF) circuit designs. A typical crystal oscillator can be manufactured to achieve tolerances of less than 10 ppm (parts per million), but larger tolerances tend to be less expensive to manufacture. The crystal can be “tuned,” that is, adjusting the resonant frequency to a desired frequency through open-loop or closed-loop control in order to achieve tighter tolerances or to ease manufacturing requirements. 
     Because the crystal oscillator is an inherently stable resonator, this oscillator can be used in many types of electronic oscillator circuit topologies. For example, these oscillator circuit topologies can include the Colpitts, Hartley, and Pierce oscillator circuit topologies. 
     SUMMARY 
     The present disclosure describes techniques and systems for digitally tuning a crystal oscillator circuit. In general, in one aspect, embodiments of the invention feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. 
     These and other embodiments can optionally include one or more of the following features. The method can involve adjusting a capacitance of the tuning capacitor with the digitally-modulated output signal to tune the frequency of the crystal oscillator. The adjustment of the capacitor can involve modulating a switch for the tuning capacitor, and the tuning capacitor can include an array of switched capacitors. The method can include any combination of oversampling, noiseshaping, or oversampling and noiseshaping. 
     In some embodiments, the method can involve adjusting a capacitance of the switched capacitor array with the digitally-modulated output signal to tune the frequency of the crystal oscillator circuit. The tuning capacitor can include adjusting a capacitance of a varactor. The adjustment can include producing an equivalent control voltage for generating an average capacitance of the varactor. The average capacitance of the varactor can be a function of an average of reference voltages that are switched by the digitally-modulated output signal. The digital modulator can be a delta-sigma modulator, a delta modulator, a pulse-width modulator, a differential modulator, or a continuous-slope delta modulator. The method may also include adding a dithering signal to the digitally-modulated output signal to minimize error in the digitally-modulated output signal by reducing fixed pattern noise in the digitally-modulated output signal. 
     In general, in another aspect, embodiments of the invention feature a tuning circuit for digitally tuning a frequency of a crystal oscillator circuit having a quartz crystal. The tuning circuit includes a modulator circuit to produce a digitally-modulated output signal by noiseshaping or oversampling a multi-bit input signal. The modulator includes an input for the multi-bit input signal and an output that has a lower number of bits than the input. The circuit also includes a tuning capacitor coupled with the crystal oscillator circuit, in which the output of the modulator circuit is coupled to the tuning capacitor for the digitally-modulated signal to adjust a capacitance of the tuning capacitor to tune the frequency of the crystal oscillator circuit. 
     Particular embodiments of the invention can be implemented to realize one or more of the following advantages. The tuning capacitor can be a switched capacitor, where the switched capacitor can include a capacitor coupled with a switch that is configured to be switched with the digitally-modulated output signal. In some embodiments, the tuning capacitor can include a first tuning capacitor that has a capacitance that is configured to be adjusted by circuitry to generate an average of switched-reference voltages, where the reference voltages can be switched by the digitally-modulated output signal. The tuning capacitor can have an array of switched capacitors, in which the switched capacitors can be configured to be modulated with the output of the modulator circuit. 
     In some embodiments, the digital modulator can be any of a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous slope delta modulator. The tuning capacitor may include a varactor. The tuning circuit can include circuitry to produce an equivalent control voltage for an average capacitance of the varactor. The circuit may also include a dithering circuit with a dithering output coupled to the output of the modulator circuit to add a dithering signal to the digitally-modulated output signal to minimize error in the digitally-modulated output signal. 
     In general, in another aspect, embodiments of the invention feature a system that includes a crystal oscillator circuit comprising a quartz crystal, and a modulator circuit to produce a digitally-modulated output signal. The modulator includes an input for the multi-bit input signal and an output having a lower number of bits than the input. The modulator includes a delta-sigma or oversampling modulator to noiseshape or oversample the digitally-modulated output signal. The system includes a tuning capacitor coupled with the crystal oscillator circuit, in which the output of the modulator circuit is coupled to the tuning capacitor for the digitally-modulated signal to adjust a capacitance of the tuning capacitor to tune the frequency of the crystal oscillator circuit. The system includes a dithering circuit with a dithering output, and a summing circuit to couple the dithering output with the output of the modulator circuit to add the dithering signal to the digitally-modulated output signal for error reduction in the digitally-modulated signal. 
     Particular embodiments of the invention can be implemented to realize one or more of the following advantages. The dithering output can have a lower number of bits than the digitally-modulated output signal, and the summing circuit can be configured to add the dithering signal to a number of least significant bits (LSBs) in the digitally-modulated output signal. The summing circuit can be configured to reduce an energy of fixed pattern noise and/or spurious responses in the digitally-modulated output signal. The crystal oscillator circuit can be coupled in a receiver or transceiver architecture, in which the receiver or transceiver can have an architecture that includes a superheterodyne receiver, an image-rejection receiver, a zero-intermediate frequency (IF) receiver, a low-IF receiver, a direct-up transceiver, or a two-step up transceiver. 
     Particular implementations may provide one or more following advantages for implementing digital frequency control of crystal oscillators. In some implementations, for example, the disclosed tuning technique can use digital modulation to tune the frequency of crystal oscillators to achieve fine frequency resolution in excess of ten bits while keeping manufacturing costs and circuitry area low. The digital modulation can include various forms of oversampling modulators, such as delta sigma modulators. By employing single-bit control or control with a low number of bits, the frequency of the crystal oscillator can be controlled to a much higher equivalent number of bits. 
     Also disclosed is a method to integrate the digital frequency control for the crystal oscillator in a lower-cost and higher-accuracy design with low process variation and sensitivity than is achievable in conventional circuit designs. Another potential advantage is that the techniques disclosed can require a lower amount of die area than designs for conventional oscillator tuning techniques. For example, when compared to conventional techniques, the disclosed techniques and systems can result in a lower number of capacitors that are used for tuning the crystal oscillator. As a result, the amount of die area required for tuning capacitor designs and layouts can be reduced. 
     Details of one or more implementations are set forth in the accompanying drawings and the description herein. Other features, aspects, and advantages will be apparent from the description, the drawings, and the claims. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a model of a crystal device as a passive L and C network. 
         FIG. 2  shows a model of a conventional crystal oscillator circuit. 
         FIG. 3  is a model of a conventional digitally-controlled crystal oscillator. 
         FIG. 4  is an example embodiment of the disclosed technique for the crystal oscillator. 
         FIG. 5  is an example embodiment of the disclosed technique for the crystal oscillator. 
         FIG. 6  is an example embodiment of the disclosed technique for the crystal oscillator. 
         FIG. 7  is an example embodiment of the disclosed technique for the crystal oscillator. 
         FIG. 8  is an example block diagram of a delta-sigma modulator. 
     
    
    
     Like reference numbers and designations in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
       FIG. 1  shows a simplified model  100  of the crystal device as a passive L and C network, with capacitor elements C 1   110 , Co  120 , and inductor element L  115 . Capacitor Co  120  represents the parallel plate capacitance, such as the capacitance from wires and contacts. Capacitor C 1   110  and inductor L  115  represent the energy storage in the model. Since the quartz crystal has a high Q value, the series capacitance C 1   110  is very low and the series inductance L  115  is very high. 
     There are a few conventional methods of controlling the crystal oscillator frequency. By modeling the crystal as a high quality L-C resonator as in  FIG. 1 , the resonant frequency of the crystal can be “pulled” by adding parallel and/or series resonant components, such as capacitors as loads to the resonant circuit. The pulling can be done, for example, through analog controlling a variable capacitor device (varactor) or through digital means via tuning a weighted array of capacitor. 
       FIG. 2  shows a model  200  of a conventional crystal oscillator circuit.  FIG. 2  shows an example where the resonant frequency of the crystal can be “pulled” through analog control of a variable capacitor device, varactor  217 . In  FIG. 2 , an inverting amplifier  213  is put in parallel with a crystal  215  to form a crystal oscillator circuit. The parallel load capacitors  211  and  212  are used to set a nominal fixed frequency of the resonant circuit. The varactor  217  is tuned by an analog control voltage  220 , V AFC , which is used to tune the frequency of the crystal oscillator. The varactor  217  is coupled to the crystal  215  through a capacitor  219 . Analog control circuit topologies other than the model  200  shown in  FIG. 2  may be designed, such as topologies using dual varactors or topologies that couple the varactor to the crystal  215  with resistors instead of capacitors. 
       FIG. 3  shows a model  300  of a conventional crystal oscillator circuit.  FIG. 3  shows an example where the resonant frequency of the crystal can be “pulled” through digital means by tuning a weighted array of capacitors. An advantage of using digital control (e.g.,  FIG. 3 ) in contrast with analog control (e.g.,  FIG. 2 ) is that the digital control circuits can be more easily implemented and integrated into an overall integrated circuit system, especially for circuit implementations using digital process technologies. Another advantage that digital control has over analog control is that the digital control can be more easily controlled since the digital control is performed through digital processor circuitry rather than analog techniques. The digitally-controlled frequency tuning design may be referred to as a digitally-compensated crystal oscillator (DCXO). In some implementations, by using a switched capacitor array for load capacitance, the range of tuning can be improved over what is achievable with an analog varactor. 
     The model  300  of  FIG. 3  shows the amplifier  213  in parallel with the crystal  215 .  FIG. 3  also has a digitally programmable parallel capacitor array  321  that can be used as a tunable load with 2 k  possible values. The array  321  has a k-bit control word from the digital frequency control input  330 , V DFC . Even though a single-ended load is shown in the embodiment of the model  300 , a single-ended or differential load can be implemented. 
     In order for the conventional design to achieve a large number of bits of digital control and to achieve monotonic accuracy, the conventional design will use a substantial amount of die area in the implementation. Due to sensitivity in process variations, monotonic operation cannot be achieved using a design that only has a binary-weighted capacitor array to enhance precision when the number of bits of accuracy desired is greater than eight bits. As a result, techniques such as mixed binary and linear weighting for capacitors have been implemented. However, these conventional capacitor matching techniques also result in large die area penalties for the capacitor layout. Since the amount of capacitor mismatch from manufacturing variations is inversely proportional to device area, a large die area is required for the capacitors to have good matching characteristics. In conventional designs, good matching characteristics of the capacitors are required to achieve good monotonic accuracy, precision, and control. 
       FIG. 4  is an example embodiment of a model  400  for the disclosed technique for a crystal oscillator. In  FIG. 4 , the inverting amplifier  213  is in parallel with the crystal  215 , and the capacitor loads  331  and  332  are fixed tuning capacitors loads. A digital modulator  337  converts a k-bit digital control word  330  at the digital frequency control input, V DFC , to a one-bit switched control signal that is of a modulated frequency. The modulator  337  can be a conventional delta-sigma modulator or some other conventional oversampling or noise-shaping modulator. Sigma-delta modulators can also refer to delta-sigma modulators. Switch  338  is used to switch node  339  between reference voltages VREF 1  and VREF 2  based on a value of the one bit digital modulator output. Node  339  is the node that couples a first tuning capacitor  335  with the varactor  336 , and is used as a control node for setting the varactor capacitance. If VREF 1  is switched to couple to node  339  when the output of the digital modulator is 1 and VREF 2  is switched to couple to node  339  when the output of the digital modulator is 0, an average value of the digitally modulated signal, K av , is impressed upon the control node  339  to provide an equivalent voltage control value of (K av *VREF 1 +(1−K av )*VREF 2 ) at which the average capacitance of the varactor  336  can be determined. 
     The bit resolution of the capacitance tuning can be increased by using oversampling or noise-shaping techniques, which trade-off bit resolution with sampling frequency, well known in the art for data conversion. An advantage of using oversampling or noise-shaping techniques is that the digital bit resolution is relatively insensitive to device matching characteristics. Another advantage of implementing oversampling or noise-shaping techniques is that the amount of die area required to implement the oversampling or noise-shaping controller and digital circuitry is much lower when compared to conventional designs for achieving high levels of resolution. 
       FIG. 5  is another example embodiment of the disclosed technique for tuning the frequency of the crystal oscillator. In this embodiment, the inverting amplifier  213  is placed in parallel with crystal  215 , and fixed capacitors  331  and  332  provide a nominal tuning of the oscillator frequency. The resonant circuit within this example embodiment includes components  213 ,  215 ,  331 , and  332 . 
     A digital modulator  337  converts a k-bit digital control word  330  at the digital frequency control input, V DFC  to a one-bit switched control signal that has a modulated frequency. The digital modulator  337  can be a delta-sigma modulator or some other type of oversampling or noise-shaping modulators. The one-bit modulator output is used to control switch  549  to switch a load capacitor C L    548  in parallel with the resonant circuit. The average value of the digitally modulated signal, K av , from the modulator  337  modulates the parallel capacitance load of capacitors  331  and  332  by K av *C L . The combination of the switch  549  in series with the load capacitor C L    548  can be referred to as a switched capacitor. 
       FIG. 6  shows a different example embodiment of the disclosed technique for tuning the frequency of the crystal oscillator. In this embodiment, the inverting amplifier  213  is placed in parallel with crystal  215 , and fixed capacitors  331  and  332  provide a nominal tuning of the oscillator frequency. The resonant load within this example embodiment includes components  213 ,  215 ,  331 , and  332 . In particular,  FIG. 6  shows an example block diagram of an oversampling or a noise-shaping digital modulator  650  that has a k-bit input control word  330  at the digital frequency control input, V DFC  and an n-bit output, where n&lt;k. Such an oversampling or a noise-shaping modulator can be used to control an array  651  of n switches to modulate the resonant load of the circuit. The array  651  may also be referred to as an array of switched capacitors. 
       FIG. 7  shows an example of a block diagram where a dithering signal is added to the output of the digital modulator to improve modulation performance of the digital tuning technique. Typical digital modulators can produce fixed pattern noise in the n-bit output signal as a result of limit cycles or other repetitive digital patterns that may derive from imperfections in the digital modulator implementation. In particular,  FIG. 7  shows an embodiment of the disclosed technique that includes a digital modulator  650 , a dithering circuit  758 , and a summing circuit  765 . A dither signal can be referred to as a form of noise or data which is added to digitally modulated data for the purpose of minimizing error in the output signal of the digital modulator  650 . The dither signal may be a pseudo-random generated sequence with white noise characteristics. The digital modulator  650  has a k-bit input control word  330  at the digital frequency control input, V DFC , and an n-bit output. The dithering circuit  758  has an m-bit noise code output. In some implementations, the m bits may only be a few bits and may be added to a few least significant bits (LSBs) of the n-bit output of the digital modulator  650 . The addition of the dither signal to the output signal of the digital modulator can randomize low spur levels and reduce error in the output signal of the digital modulator  650 . 
     In  FIG. 7 , the n-bit output of the digital modulator  650  can be modified by adding a dithering signal of m bits at the summing circuit  765  to produce a p-bit output signal  777  to reduce the energy of fixed pattern noise that would ordinarily result in spurious responses and lower resolution. In some implementations, the m-bit-signal does not substantially alter the nature of the n-bit signal from the digital modulator  650 . In these implementations, when the m-bit signal is summed with the n-bit signal, the nature of the p-bit signal does not substantially differ from the n-bit signal. As a result, the number of bits for the p-bit signal can be equal to the number of bits in the n-bit signal, and in some implementations, can be somewhat greater than n, or even somewhat less than n if truncation of the LSB is desired. In some implementations, the p-bit signal  777  can be substituted for the signal at the output of the digital modulator  650  for  FIG. 6  and the digital modulator  337  for  FIGS. 4-5 . In general, p should be less than k to have a useful tradeoff between increasing oversampling frequency and reducing the number of output bits. 
       FIG. 8  shows an example of a first-order delta-sigma modulator implementation that shapes the noise of the digital modulator  859 . Noise-shaping digital modulators can improve the in-phase noise performance, however, at the cost of higher out-of-band noise. An oversampling or a noise-shaping digital modulator can be relatively insensitive to device tolerances and matching. Higher oversampling ratios for digital modulators can give higher equivalent bit resolution. This disclosure provides an advantage in that the high quality factor of the resonant crystal circuit has a natural filtering capability of out-of-band noise so that the noise-shaping modulator can be used without any additional filters. In an another benefit, higher order delta-sigma modulators can be used to reduce the impact of spurious responses due to limit cycles. Some higher order delta-sigma modulators can include MASH and cascade modulators. In some embodiments, other types of modulators that can be used include delta modulators, pulse-width modulators, differential modulators, and continuous-slope delta modulators. 
     While all of the implementations presented herein use single-ended structures, differential structures can be used in their place with the added advantages of improved symmetry and increased robustness to noise. In addition, various types of oversampling or noise-shaping modulators, including delta-sigma modulators of various orders, numbers of output bits, structures, and implementations can be used. Fractional accumulators and other digital modulators could be used as well. Various topologies for oscillators and parallel or series resonant loads for tuning the oscillator can also be used. The exemplary designs shown are not limited to CMOS process technology, but may also use other process technologies, such as BiCMOS (Bipolar-CMOS) process technology, or Silicon Germanium (SiGe) technology. The disclosed techniques can be used in oscillators for many systems, including wireless communication systems. For example, the disclosed techniques can be used in oscillators for receivers and transceivers, such as the receiver and transceiver architectures for superheterodyne receivers, image-rejection (e.g., Hartley, Weaver) receivers, zero-intermediate frequency (IF) receivers, low-IF receivers, direct-up transceivers, two-step up transceivers, and other types of receivers and transceivers for wireless technologies. When implementing the oscillators in these architectures with the disclosed tuning techniques, the system can have a lower die area and power dissipation when compared to conventional tuning techniques for crystal oscillators. Other modifications are within the scope of the following claims.