PATENT ABSTRACT
A method and system for multiplexing data signals is provided. A first circuit is operable to generate a plurality of serialized data signals and is operable to adjust a phase of at least one of the serialized data signals to adjust bit and byte alignment. A second circuit is coupled to the first circuit to receive the plurality of serialized data signals from the first circuit. The second circuit has a multiplexer operable to generate a multiplexed output signal from the received serialized data signals. The first circuit is further coupled to the second circuit by a back channel operable to carry information regarding bit alignment and byte alignment of the received serialized data signals.

PATENT DESCRIPTION
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. patent application Ser. No. 11/391,537, filed Mar. 28, 2006 now U.S. Pat. No. 7,742,507, entitled METHOD AND SYSTEM FOR PHASE AND BYTE ALIGNMENT ON A MULTIPLEXED HIGH SPEED BUS, the entire contents of which is incorporated herein by reference. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     n/a 
     FIELD OF THE INVENTION 
     The present invention relates to high speed signal multiplexing, and in particular to a method and system for maintaining phase (bit) and byte alignment among multiplexed signals such as may be found in a 40 giga-bit (Gbit) per second system. 
     BACKGROUND OF THE INVENTION 
     As demand for greater bandwidth and data throughput increases, so too does the demand placed on integrated circuits to accommodate the processing and transmission speeds needed to support increased data throughput. Such is particularly the case where semi-conductor integrated circuits are used within optical transmission systems. Because optical transmission systems can operate at speeds of 40 Gbits per second, semi-conductor integrated circuits must also be able to generate data streams at that rate in order to supply a constant supply of data to optical modulators. In other words, an optical modulation system that can modulate a signal to optically transmit at a 40 Gbit/Sec. rate must be supplied with a data stream of 40 Gbit/Sec. This requires that the underlying electronic components be capable of generating a 40 Gbit/Sec. data stream. 
     Proposed 40 Gbit/Sec. optical transmission schemes contemplate a complimentary metal-oxide semiconductor (“CMOS”) silicon pre-processor application-specific integrated circuit (“ASIC”) providing 4×10 Gbit/Sec. data channels to a bipolar or BiCMOS ASIC which then multiplexes the 4 channels together to create one 40 Gbit/Sec. stream of data. This 40 Gbit/Sec. stream of data is then sent to an optical driver chain and ultimately appears as an optical signal on a fiber optic cable. 
     A problem with this scheme is that the 4×10 Gbit/Sec. data streams can become skewed with respect to one another between the CMOS preprocessing ASIC and the 40 Gbit/Sec. multiplexing ASIC. In other words, for a given bit, e.g., bit  0 , that bit in each of the data streams does not arrive at the 40 Gbit/Sec. multiplexing ASIC at the same time. The result is that the bits become jumbled and out of sequence when they are multiplexed, thereby throwing the streams out of byte alignment. In addition, if the timing at the input ports of the 40 Gbit/Sec. multiplexing ASIC is not correct for all 4 10 Gbit/Sec. channels, the data within each individual data stream can be corrupted as well. This problem results in the individual data streams being out of bit alignment. As such, for the 40 Gbit/Sec. multiplexing ASIC to work correctly, it must be able to sample the 4×10 Gbit/Sec. data channels for which the bit alignment may be more than 50% out of alignment and for which the word alignment may also be out of sync. 
     Proposals have been made to solve this problem. The first requires that the ASIC vendors provide a transmission port in which 4×10 Gbit/Sec. output streams are both bit and byte aligned. For this scheme to work, the package and track matching must be maintained to better than 20 picoseconds. However, current ASIC and field programmable gate array (“FPGA”) vendors do not provide full bit and byte alignment in their devices even at 2.5 Gbit/Sec., let alone 10 Gbits/Sec. In part, this is because current suppliers treat each transmission port as an independent port without regard to subsequent multiplexing. In addition, bus margining at 10 Gbit/Sec. is quite difficult leaving an overall small timing margin. 
     Another proposal involves using the 10 Gbit/Sec. independent transmit devices on the silicon preprocessor ASIC described above. The 40 Gbit/Sec. multiplexing ASIC must then have an interface capable of fully recovering bit and byte alignment from the incoming data. A proposal has been made to use 4×10 Gbit/Sec. data channels with a 5 th  10 Gbit/Sec. data channel used to carry alignment data. This scheme has several drawbacks itself. As an initial matter, the scheme only works if the 40 Gbit/Sec. multiplexing ASIC is implemented in a BiCMOS technology such that the short macros that must be provisioned can be instantiated. This immediately limits the choice of semiconductor technology for the 40 Gbit/Sec. multiplexing ASIC and clock generation function to a fully bipolar technology. However, bipolar devices that are optimized for 40 Gbit/Sec. cannot be used. This arrangement also means that the BiCMOS device has to make a 10 Gbit/Sec. serializer/deserializer (“SERDES”) link available in order to build the short port. For the most part, the CMOS device suppliers are only making 10 Gbit/Sec. links available in either 65 nanometer (“nm”) or 45 nm CMOS-only technologies. SERDES devices are high speed devices used to convert parallel data to a serial data stream and vice versa and can be stand alone devices or incorporated in ASIC. However, in the case of prior art devices, a SERDES device in the ASIC may have only limited availability. In addition, SERDES devices are not simple to build. Also, if indium phosphide (“InP”) technology or a gallium arsenide (“GaAs”) process in which flip-flops are implemented in order to combine the 40 Gbit/Sec. multiplexing function with the modulator driver function is used, then the aforementioned SERDES devices cannot be implemented. Thus the second proposed solution seriously limits semiconductor technology selection. 
     In order to function in known operating environments, the aforementioned SERDES device can not operate at 10 Gbit/Sec. and must demultiplex the incoming 10 Gbit/Sec. data streams down to 340 Mbit/Sec. or 170 Mbit/Sec. in order to process the data and correct byte alignment. The 40 Gbit/Sec. multiplexing ASIC must then first remultiplex each data stream back up to 10 Gbit/Sec. and then to 40 Gbit/Sec. This represents a significant increase in power for the 40 Gbit/Sec. multiplexing ASIC. Multiple power supply levels must also be supported in such a case. 
     Both of the above schemes imply that the two alignments which must be achieved, namely detailed bit alignment to allow correct sampling of incoming bits, and byte alignment must be solved within the 40 Gbit/Sec. multiplexing ASIC. This assumption impairs technology choices, technology availability, and increases power and complexity. It is therefore desirable to have a method and system for a high speed multiplexing system, such as a 40 Gbit/Sec. multiplexing system, that preserves bit and byte alignment among the multiplexed data streams and which minimizes power consumption while allowing transmission system designers flexibility in the technology underlying the semiconductor devices that implement the multiplexing system. 
     SUMMARY OF THE INVENTION 
     The present invention advantageously provides a method and system for a multiplexing system that preserves bit and byte alignments in a high speed, e.g., 40 Gbit/Sec. environment, while allowing semiconductor technology choice and low power. The system includes a high speed integrated circuit and a low speed integrated circuit in which the functions used to achieve the above-described result are located in the most appropriate integrated circuit. 
     In accordance with one aspect, the present invention provides a system for multiplexing is which a first circuit is operable to generate a plurality of serialized data signals and is operable to adjust a phase of at least one of the serialized data signals to adjust bit and byte alignment. A second circuit is coupled to the first circuit to receive the plurality of serialized data signals from the first circuit. The second circuit has a multiplexer operable to generate a multiplexed output signal from the received serialized data signals. The first circuit is further coupled to the second circuit by a back channel operable to carry information regarding bit alignment and byte alignment of the received serialized data signals. 
     In accordance with another aspect, the present invention provides a serialized data source element for a multiplexing system. A plurality of outputs transmits serialized data signals to a multiplexing element. At least one input receives information regarding bit alignment and byte alignment of the serialized data signals on a back channel from the multiplexing element. A phase adjustment element is operable to adjust a phase of at least one of the serialized data signals to adjust bit and byte alignment of at least one serialized data signal. 
     In accordance with yet another aspect, the present invention provides a multiplexing element for a multiplexing system in which the multiplexing system has a serialized data source. The multiplexing element has a plurality of inputs for receiving serialized data signals from the serialized data source, a multiplexer operable to generate a multiplexed output signal from the received serialized data signals and a bit alignment and byte alignment information generator operable to generate information regarding bit alignment and byte alignment of the received serialized data signals for transmission on a back channel to the serialized data source. 
     In accordance with still another aspect, the present invention provides a multiplexing method in which a first circuit is operated to generate a plurality of serialized data signals. A second circuit is operated to receive the plurality of serialized data signals, generate a multiplexed output signal from the plurality of serialized data signals and transmit information regarding bit alignment and byte alignment of the received serialized data signals on a back channel to the first circuit. The first circuit is further operated to adjust a phase of at least one of the serialized data signals to adjust bit and byte alignment based on the information transmitted on the back channel. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete understanding of the present invention, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein: 
         FIG. 1  is a block diagram of a system constructed in accordance with the principles of the present invention; 
         FIG. 2  is a diagram of a multi-channel bit stream showing bit and byte alignment; 
         FIG. 3  is a block diagram of a multi-channel low speed device constructed in accordance with the principles of the present invention; and 
         FIG. 4  is a block diagram of a high speed device constructed in accordance with the principles of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawing figures in which like reference designators refer to like elements, there is shown in  FIG. 1  a block diagram of high speed multiplexing system constructed in accordance with the principles of the present invention and designated generally as “ 10 ”. System  10  includes low speed device  12  and high speed device  14 . Low speed device  12  includes input signals  16   a ,  16   b ,  16   c  and  16   d  (referred to collectively herein as input signals  16 ), and high speed device  14  outputs a high speed output signal  18  that is a multiplexed version of input signals  16 . Low speed device  12  can be a high gate count CMOS ASIC device. Input signals  16  are typically provided at the byte level, i.e., parallel signals, but are shown as a single line for simplicity. Output signal  18  can, for example, be supplied to optical modulators and other circuitry used to generate an optical signal for communication on a fiber optic cable. 
     Although it is contemplated that devices  12  and  14  can receive an input, communicate at any suitable data rate via serialized data signals  20   a ,  20   b ,  20   c  and  20   d  (referred to collectively herein as serialized data signals  20 ), input signals and output a multiplexed stream via output signal  18  at any suitable rate, the present invention is explained with reference to four 10 Gbit/Sec. serialized data streams  20   a - d , and a 40 Gbit/Sec. multiplexed output signal  18 . In other words, low speed device  12  outputs four 10 Gbit/Sec. serialized data streams and high speed device outputs a single a 40 Gbit/Sec. multiplexed output signal  18 . 
     As is shown in  FIG. 1 , reference clock  22  and phase correction signal  24  are supplied by low speed device  12  to high speed device  14  and a phase data and byte snapshot back channel signal  26  is supplied by high speed device  14  to low speed device  12 . These signals are explained in detail below. 
     Phase data and byte snapshot back channel signal  26  creates a reverse or back channel from the high speed device  14  to low speed device  12 . The data on back channel signal  26  includes phase information as to the detailed bit alignment on each of the incoming 4×10 Gbit/Sec. serialized data signals  20  as well as periodic snapshots of the 10 Gbit/Sec. data which the high speed device  14  is multiplexing to 40 Gbit/Sec. Partitioning the bit and byte alignment control in this method advantageously places the complex high gate count circuitry on low speed device  12 , e.g., a CMOS preprocessing ASIC, thus minimizing the circuitry on high speed device  14 , e.g., the 40 Gbit/Sec. multiplexing ASIC to the point that high speed device  14  can be implemented using a purely bipolar or GaAs technology. 
     Achieving byte alignment is then accomplished as a core digital function on low speed device  12 . Because low speed device  12  is responsible for and can determine what the data byte alignment is, it can compare the byte alignment returned for the snapshot bits and barrel shift the transmitted data until the returned snapshot is correct. The gates to perform the comparison can be implemented in any technology which can support SERDES devices, such as 10 Gbit/Sec. SERDES device (also referred to as “macros”) even if the SERDES devices are fully independent. Also, because the cost in terms of gates to have high speed device  14  take a snapshot of the transmitted bits is small, i.e., no more than 25 flip-flops, the snapshot function can be implemented in a fully bipolar technology, a GaAs technology or a BiCMOS technology even if that technology does not have 10 Gbit/Sec. SERDES macros available. This is the case because, as is explained below in detail, no SERDES devices are used on high speed device  14 . 
     Bit (phase) and byte alignment achieved by the present invention is explained with reference to  FIG. 2 .  FIG. 2  shows a multi-channel bit stream having four bit streams  28   a ,  28   b ,  28   c  and  28   d  (referred to collectively herein as bit streams  28 ) such as of the type that may be carried by serialized data signals  20   a ,  20   b ,  20   c  and  20   d , respectively. Each bit stream  28  shows an 8 bit byte in which each bit, i.e. bit  0 , within each bit stream is aligned with the corresponding bit  0  in the other bit streams so that a given bit in each of the bit streams arrives at high speed device  14  at the same time. This is referred to as byte alignment. The present invention provides such an arrangement 
     The present invention is also arranged such that each bit within a given bit stream, e.g. bit  1   a  in bit stream  28   a , is clocked into high speed device  14  in a manner in which it can be accurately read and not misinterpreted as the subsequent bit, e.g. bit  2   a  in bit stream  28   a , or the previous bit, e.g. bit  0   a  in bit stream  28   a . The result is that the bits in a given data stream are read into high speed device  14  in the correct sequential order. As is described below in detail, phase data and byte snapshot back channel signal  26  is used by low speed device  12  to adjust the phase of each serialized data signal  20  to preserve bit and byte alignment. 
     An exemplary multi-channel low speed device  12  constructed in accordance with the principles of the present invention is explained with reference to  FIG. 3 . Low speed device  12  includes a byte shift  30  (shown as byte shifts  30   a ,  30   b ,  30   c  and  30   d ) for each corresponding input signal  16 . Each byte shift  30  is coupled to a respective SERDES  32  (shown as SERDES  32   a ,  32   b ,  32   c  and  32   c ). Because the present invention is explained with reference to 10 Gbit/Sec. serialized data signals  20 , each SERDES  32  generates a 10 Gbit/Sec. signal. Byte shifts  30  align the bits by shifting bits until the snapshot returned from high speed device  14  via back channel  26  matches the intended byte alignment. SERDES  32  can be any CMOS SERDES operating to output a serialized channel at the desired signal rate, e.g., 10 Gbit/Sec. The present invention can be implemented using independent SERDES  32  devices, i.e., SERDES  32   a  is independent of SERDES  32   b.    
     The exemplary multi-channel low speed device  12  shown in  FIG. 3  also includes clock buffer  34 , low speed control port  36 , byte comparator  38  and digital filter  40 . Clock buffer  34  can be any clock unit associated with SERDES devices. Clock buffer  34  outputs reference clock signal  22  to high speed device  14 . 
     Low speed control port  36  includes those components needed to transmit phase correction signal  24  to high speed device  14  and receive phase data and byte snapshot back channel signal  26  from high speed device  14 . Methods for incorporating low speed control ports into ASICs, such as CMOS ASICs are known. Low speed control port  36  passes the byte snapshot received from high speed device  14  to byte comparator  38 . Byte comparator  38  compares the intended byte alignment with the alignment returned in the snapshot to determine if the two are the same. If they are not, byte comparator  38  instructs the corresponding byte shifts  30  to shift the byte alignment. This process continues until the intended byte alignment is the same as the alignment returned in the snapshot. 
     Low speed control port  36  also passes phase data received from high speed device  14  to digital filter  40 . Digital filter  40  analyzes the phase data and generates phase correction data. The phase correction data is sent to low speed control port  36  for subsequent transmission to high speed device  14 . As is discussed below in detail, high speed device  14  uses the phase correction data to control phase shift units therein. 
     The above-described components of low speed device  12  can be fabricated using CMOS technology in order to achieve the high gate count needed to implement all of the described components. However, because high speed (relative to a 40 Gbit/Sec. output) is not needed, it is not necessary to construct low speed device using the same technology as high speed device  14 . 
     An exemplary high speed device  14  constructed in accordance with the principles of the present invention is described with reference to  FIG. 4 . High speed device  14  includes phase detector  42   a ,  42   b ,  42   c  and  42   d  (referred to collectively as phase detectors  42 ) which compare the phase of each incoming data stream  20   a ,  20   b ,  20   c , and  20   d , respectively, with a local clock (not shown). The phase state of each incoming data stream  20  is provided to a low speed control port  44  in high speed device  14  for transmission to digital filter  40  in low speed device  12 . Of note, although not shown for the sake of simplicity of  FIG. 4 , each phase detector  42   a ,  42   b ,  42   c  and  42   d  is coupled to low speed control port  44 . 
     Phase detectors  42  are included in high speed device  14  to achieve bit alignment. Because phase detectors also have low gate counts, phase detectors  42  can also be built in a fully bipolar or GaAs technology without the requirement for CMOS. As described above, the alteration of the phase based on the phase detected by the phase detectors in high speed device  14  is performed by low speed device  12 . 
     High speed device  14  also includes data retimers  46  (shown in  FIG. 4  as data retimers  46   a ,  46   b ,  46   c  and  46   d ) and clock shifters  48  (shown in  FIG. 4  as clock shifters  48   a ,  48   b ,  48   c  and  48   d ). Data retimers  48  receive the serialized data signals from a corresponding phase detector  42  and, in conjunction with a corresponding clock shift  48 , retime the data stream onto the local sampling clock. Phase locked loop (“PLL”) and divider  50  generates the high speed clock for high speed, i.e. 40 Gbit/Sec., functions from an external reference and supplies the clock to clock shifters  48 . In the case of the described embodiment, the external reference is clock buffer  34  in low speed device  12 . It is also contemplated that the reference clock can be included in high speed device  14  and used to source PLL  50  as well as low speed device  12 . 
     A method for achieving correct bit alignment uses the clock shifters  48 . As these are very low gate count devices, the presence of clock shifters  48  does not impede the semiconductor technology choice available to circuit designers. Clock shifters  48  adjust the sample clock on the associated 10 Gbit/Sec. input port such that the data is properly sampled. Although not shown, the state of each clock shifter  48  is controlled from the low speed device  12  via phase correction signal  24 . 
     High speed device  14  also includes master clock retime and snapshot devices  52   a ,  52   b ,  52   c  and  52   d  (referred to collectively as master clock retime and snapshot devices  52 ) which receive a retimed serialized data stream from a corresponding data retimer  46  and, after retiming the data stream onto the master clock and capturing intermittent data snapshots, provides the serialize data streams to multiplexer  54 . Of note, although not shown for the sake of simplicity of  FIG. 4 , each master clock retime and snapshot device  52   a ,  52   b ,  52   c  and  52   d  is coupled to low speed control port  44 . 
     Multiplexer  54  multiplexes the incoming serialized and retimed data streams for output as multiplexed output signal  18 . In the embodiment described herein, multiplexer  54  outputs a 40 Gbit/Sec. signal and includes the hardware needed to drive output signal  18  to another device in the system, such as an optical modulator. Multiplexer  54  is coupled to PLL  50  for clock and timing synchronization. Although not shown, multiplexer  54  can also accumulate phase information to allow periodic transmission of that information to low speed device  12  via low speed control port  44 . 
     The present invention advantageously provides reverse byte timing such that the ultimate timing of serialized data signals  20  is controlled by low speed device  12  based on feedback from high speed device  14 . This arrangement reduces the gate count requirements of high speed device  14  and places a high gate count requirement on low speed device  12 , where such a requirement can be met using CMOS technology. In addition, because low speed device  12  can be implemented using CMOS technology, standard CMOS SERDES devices  32  can be used. 
     The present invention also advantageously provides a modified reverse clock timing. Prior art systems return clocks on matched paths. However, this arrangement is not accurate enough for 10 Gbit/Sec. speeds. The present invention implements reverse clock timing by making a phase measurement on high speed device  14  and sending the clock phase result to low speed device  12  for processing and clock phase adjustment. 
     Of note, it is presumed that one of skill in the art of ASIC design can design the specific circuitry needed to implement the blocks and functions described herein. The present invention advantageously provides a method and system that achieves bit and byte alignment for a multiplexed input bus, such as a 4×10 Gbit/Sec. input bus that is input to a high speed, i.e., 40 Gbit/Sec. multiplexing ASIC, in a manner that does not incur a high gate count penalty. The present invention also allows the use of bipolar or GaAs semiconductor technology in the high speed multiplexing ASIC while allowing the high speed multiplexing ASIC to function as the high speed multiplexer, generate a 40 GHz clock and drive the resultant multiplexed 40 GHz signal. 
     The present invention also advantageously allows processing to correct/maintain bit and byte alignment to occur on the low speed ASIC where having a high semiconductor gate count is not an issue. The present invention also avoids the need to demultiplex the underlying low speed data signals, i.e., the individual 10 GBit/Sec. signals in order to process them for bit (phase) and byte alignment status. 
     Unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. Significantly, this invention can be embodied in other specific forms without departing from the spirit or essential attributes thereof, and accordingly, reference should be had to the following claims, rather than to the foregoing specification, as indicating the scope of the invention.