PATENT ABSTRACT
A battery voltage monitoring apparatus monitoring a voltage of an assembled battery, the assembled battery including a plurality of battery cells, comprising; a first voltage sensor module that monitors voltages of a plurality of battery cells arranged at a high voltage side; and a second voltage sensor module that monitors voltages of a plurality of battery cells arranged at a low voltage side, wherein the second voltage sensor module comprises a voltage sensor that is connected to a terminal and detects a voltage of a battery cell connected to the terminal, the terminal being supplied with a power source potential of the second voltage sensor module, the voltage sensor comprises a comparator including a first terminal and a second terminal, the first terminal being supplied with a voltage according to the voltage of the battery cell, the second terminal being supplied with a reference voltage.

PATENT DESCRIPTION
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a Continuation application of U.S. patent application Ser. No. 13/675,567, filed on Nov. 13, 2012, which is a Continuation application of U.S. patent application Ser. No. 12/007,028, filed on Jan. 4, 2008, now U.S. Pat. No. 8,330,469, which is based on Japanese Patent Application No. 2007-000411 filed on Jan. 5, 2007, the entire contents of which are hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates to a battery voltage monitoring apparatus for detecting battery voltage of a power supply apparatus. The battery voltage monitoring apparatus includes a plurality of secondary batteries connected in series. Particularly, this invention relates to a battery voltage monitoring apparatus for detecting disconnection of a single line which is used for potential measurement. 
         [0004]    2. Description of Related Art 
         [0005]    An electric vehicle and hybrid vehicle are known as an eco-friendly one. In the electric vehicle and hybrid vehicle, a motor is used as driving force. Rechargeable secondary batteries are connected to the motor as electric power source. A direct current supplied from the secondary battery is converted into an alternating current, and the motor is driven by the alternating current. High voltage is required to drive the motor. Generally, the secondary battery is formed as an assembled battery including a plurality of battery cells connected in series. 
         [0006]    A plurality of voltage sensors are used for detecting each battery cell voltage in the assembled battery. A moderate number of voltage sensors are assembled and modularized. When a large number of battery cells are connected in series such as the electric vehicle or the like, a large number of voltage sensors are also provided and connected in series. An apparatus monitoring assembled battery voltage like this is shown in Japanese Unexamined Patent Application Publication Nos. 2003-208927, 2003-111284, and 2005-117780. 
         [0007]    An apparatus for monitoring potentials of the assembled batteries is described hereinafter in detail. In the apparatus, a module including a plurality of voltage sensors is configured as one semiconductor device (IC). A plurality of semiconductor devices are connected in series. Each semiconductor device (IC) has the plurality of battery sensors. 
         [0008]      FIG. 11  shows a schematic view of the conventional voltage monitoring apparatus. As shown in  FIG. 11 , one IC is able to detect voltages of four battery cells. Each input terminal of IC is connected to a battery cell C 101 -C 108  through lines for voltage measurement L 101 -L 109 . The IC  101  in  FIG. 11  operates with a positive terminal (a node N 101 ) of the battery cell C 101  as a power supply potential and a negative terminal of the battery cell C 104  (a positive terminal of battery cell C 105 , a node N 102 ) as ground potential. An IC  102  is connected to the IC  101  in series. Hence, the IC  102  operates with a positive terminal (a node N 102 ) of battery cell C 105  as power supply potential, and a negative terminal (a node N 103 ) of battery cell C 108  as ground potential. When each IC detects that the monitored battery cell becomes excess voltage or low voltage, the IC outputs an excess voltage detect signal or low voltage detect signal. 
         [0009]    Taking IC  102  of  FIG. 11  for instance, the operation of a voltage sensor module outputting the excess voltage detect signal or low voltage detect signal is explained.  FIG. 12  shows a configuration of conventional IC  102  in  FIG. 11 . As shown in  FIG. 12 , the voltage sensor module comprises a plurality of voltage sensors SEN 101 -SEN 104  and output logic circuits LOG 101  and LOG 102 . When each voltage sensor SEN 101 -SEN 104  detects excess voltage or low voltage of the battery cell to be monitored, the voltage sensor outputs high level signal as the excess voltage detect signal or low voltage detect signal, for example. When any voltage sensor outputs the excess voltage detect signal or low voltage detect signal, output of OR circuit of output logical circuit LOG 101  turns into high level from low level, for example. With this operation, the IC  102  outputs the excess voltage detect signal or low voltage detect signal. When any voltage sensor detects low voltage, the output logic circuit LOG 101  outputs high level, for example. When any voltage sensor detects excess voltage, the output logic circuit LOG 102  outputs low level, for example. 
         [0010]    For the apparatus monitoring the assembled battery voltage with the plurality of series-connected ICs, the apparatus monitoring the assembled battery voltage can be configured as follows. When a line connecting the battery cells and the voltage monitoring apparatus is disconnected, the voltage sensor connected to the disconnected line monitors abnormal potential to detect disconnection. For example, this configuration is shown in our Japanese Unexamined Patent Application Publication No. 2006-275928. However, for example, when the line corresponding to a connect portion between ICs like L 105  in  FIG. 11  is disconnected, there are problems as follows. 
         [0011]    When disconnection happens to the line L 105  in  FIG. 11 , voltage supply from the battery cell is not supplied to a node N 104  in  FIGS. 11 and 12 . Hence, current flowing out from VSS 101  of IC 101  flows into a VCC 102  and V 105  of IC  102 . If the circuit is configured so that the uppermost voltage sensor SEN 101  detects a defect of excess voltage for detecting disconnection, potential of the node N 104  rises at disconnecting of the L 105 . The voltage sensor SEN 101  detects excess voltage and logic output of output logic circuit LOG 102  is inverted. At this time, in logic circuit LOG  102 , leak current flows between VCC 102  as voltage supply of IC 102  and VSS 102 . When leak current flows, power supply potential VCC 102  becomes fall and potential of node N 104  becomes lower. When potential of node N 104  becomes lower, the voltage sensor SEN 101  does not detect excess voltage. Hence, output potential becomes lower. When output potential of voltage sensor SEN 101  becomes lower than threshold of logic circuit LOG 102 , output logic circuit LOG 102  outputs low level again. Hence, IC 102  does not output excess voltage detect signal. As a result, disconnection cannot be detected. In some cases, after that, the operation is repeated, that excess voltage is detected because leak current is decrease. Then, there is the case in which output of the IC 102  may be switched between high level and low level. 
         [0012]    As described above, because of disconnection of lines, a detect signal of voltage sensor module is output incorrectly. Hence, there is a case, for battery voltage monitoring apparatus, output becomes unstable. 
       SUMMARY 
       [0013]    In one embodiment, there is provided a battery voltage monitoring apparatus monitoring an assembled battery voltage, the assembled battery including a plurality of battery cells, includes; a voltage sensor detecting potential of the plurality of battery cells; an output logic circuit outputting a potential detect signal based on an output of voltage sensor, the potential detect signal representing that abnormal potential is detected; and a delay circuit adding certain delay to the output of the voltage sensor and outputting the delayed voltage detect signal to the output logic circuit; in which, the voltage sensor includes at least one comparator having hysteresis characteristic, and detects the potential of the battery cell based on an output of the comparator. 
         [0014]    In another embodiment, there is provided a battery voltage monitoring apparatus monitoring an assembled battery voltage, the assembled battery including a plurality of battery cells, includes; a voltage sensor detecting potential of the plurality of battery cells; an output logic circuit outputting a potential detect signal based on an output of voltage sensor, the potential detect signal representing that abnormal potential is detected; and a delay circuit adding certain delay to the output of the voltage sensor and outputting the delayed voltage detect signal to the output logic circuit; in which, the voltage sensor includes a comparator operating with output potential of battery cell as potential source, the battery cell being an object to be monitored, and the comparator has hysteresis characteristic. 
         [0015]    In still another embodiment, there is provided a battery voltage monitoring apparatus monitoring an assembled battery voltage, the assembled battery including a plurality of battery cells, includes; a comparator detecting potential of the battery cell, and outputting a potential signal representing results of detection based on certain hysteresis characteristic; a delay circuit adding certain delay to the potential signal; and a logic circuit outputting a potential detect signal based on an output of the delay circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0017]      FIG. 1  is a schematic diagram of a voltage monitoring apparatus comprising function of detecting disconnection; 
           [0018]      FIG. 2  is a circuit diagram of the voltage monitoring apparatus comprising function of detecting disconnection; 
           [0019]      FIG. 3  is a circuit diagram of the voltage monitoring apparatus according to a first embodiment in this invention; 
           [0020]      FIG. 4A  is a drawing of operation waveform of the voltage monitoring apparatus according to the first embodiment in this invention; 
           [0021]      FIG. 4B  is a drawing of operation waveform of the voltage monitoring apparatus for reference; 
           [0022]      FIG. 5  is a drawing of a voltage monitoring apparatus according to a second embodiment in this invention; 
           [0023]      FIG. 6  is a drawing of the voltage monitoring apparatus according to the second embodiment in this invention; 
           [0024]      FIG. 7  is an operation waveform of the voltage monitoring apparatus according to the second embodiment in this invention; 
           [0025]      FIG. 8  is a diagram of a variant embodiment of the voltage monitoring apparatus in this invention; 
           [0026]      FIG. 9  is a diagram of a voltage monitoring apparatus according to a third embodiment in this invention; 
           [0027]      FIG. 10  is a diagram of a level shift circuit according to the third embodiment; 
           [0028]      FIG. 11  is a drawing of a conventional voltage monitoring apparatus; and 
           [0029]      FIG. 12  is a drawing of a conventional voltage monitoring apparatus. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0030]    The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
       First Embodiment 
       [0031]    Hereinafter, embodiments of this invention are described with drawings.  FIG. 1  shows a schematic diagram for explaining a voltage monitoring apparatus  10  according to the first embodiment of the invention. The voltage monitoring apparatus  10  of this embodiment includes a plurality of voltage sensor modules. Here, the voltage sensor module is defined as an electrical element including one or more voltage sensors. In this embodiment, one module is configured as one semiconductor device (IC).  FIG. 1  shows an instance of the voltage monitoring apparatus  10  including two voltage sensor modules IC 1  and IC 2 . Hereinafter, the voltage sensor module is also called IC. Hereinafter, with taking a case in which one IC detects four battery cell voltages as an example, a first embodiment will be described. 
         [0032]    As  FIG. 1  shows, in this embodiment, eight battery cells C 1 -C 8 , which are objects to be monitored by the voltage monitoring apparatus, are connected in series. The IC 1  operates on the condition that a positive terminal potential of battery cell C 1  (see a node N 1  in  FIG. 1 ) is a first source potential (a higher source potential) and a positive terminal potential of battery cell C 5  (see a node N 2  in  FIG. 1 ) is a second source potential (a lower source potential). Because the IC 2  is connected to the IC 1  in series, the IC 2  operates on the condition that a positive terminal potential of battery cell C 5  (see a node N 2  in  FIG. 1 ) is a first source potential and a negative terminal potential of battery cell C 8  (see a node N 3  in  FIG. 1 ) is a second source potential (a ground potential). 
         [0033]    Each positive terminal of battery cells is connected to input terminals V 1 -V 8  of IC through each line L 1 -L 8 . As shown in  FIG. 1 , the input terminals V 1 -V 4  are input terminals of IC 1 , and the input terminals V 5 -V 8  are input terminals of IC 2 . As described above, the IC 1  operates on the condition that the positive terminal potential of battery cell C 1  is the first source potential. Hence, the positive terminal of battery cell C 1  is also connected to a first source terminal VCC 1  of battery cell IC 1  through line L 1 . In other words, the line L 1  also functions as a source line for the voltage sensor module IC 1 . As the positive terminal potential of battery cell C 5  is the second source potential for IC 1  and the first source potential for IC 2 , the positive terminal of battery cell C 5  is connected to a second source terminal VSS 1  of IC 1 , the first source terminal VCC 2  of IC 2 , and the input terminal V 5  of IC 2  through line L 5 . That is, the line L 5  functions as a source line for IC 1  and IC 2 . A negative terminal of battery cell C 8  is connected to a second source terminal VSS 2  of IC 2  through a source line L 9 . 
         [0034]      FIG. 1  shows the voltage monitoring apparatus comprising a function for detecting disconnection for example. The voltage monitoring apparatus in  FIG. 1  is based on our earlier Patent Application Publication No. 2006-275928. Firstly, with reference to  FIG. 1  and  FIG. 2 , the IC comprising the function of detecting disconnection in the earlier publication will be described briefly.  FIG. 2  shows an IC 1  based on the earlier publication. 
         [0035]    As shown in  FIG. 2 , the IC of the first embodiment comprises constant current sources Iref 1 -Iref 4  corresponding to the number of the monitored battery cells. The IC also comprises voltage sensors SEN 1 -SEN 4  corresponding to the number of battery cells. Each voltage sensor comprises a voltage divider resistor for excess voltage detection, a voltage divider resistor for low voltage detection, a reference potential circuit, a comparator for excess voltage detection, and a comparator for low voltage detection. An explanation about detailed operation of the voltage sensor is omitted. In the voltage sensors used in this embodiment, there is no or little current change like leak current caused by potential detection. 
         [0036]    In the IC 1  as shown in  FIG. 2 , the constant current source Iref 1  supplies a constant current Iref from the source terminal VCC 1  of IC 1  to the input terminal V 2  connected to the negative terminal of battery cell C 1 . The constant current source Iref 2  supplies a constant current Iref from the source terminal VCC 1  of IC 1  to the potential input terminal V 3  connected to the negative terminal of battery cell C 2 . The other constant current sources are sequentially connected in the same way. The constant current source Iref 4  supplies a constant current from the first source terminal VCC 1  to the second source terminal VSS 1 . The IC 2  comprises constant current sources Iref 5 -Iref 8  as the IC 1 . But, the constant current sources of IC 2  are connected so that current flows from input terminals V 6 -V 8  to the second source terminal VSS 2  (see  FIG. 1 ). A switch SW 1  (a switch SW 2 ) is provided to a current path between the first source terminal VCC 1  of IC 1  (the first source terminal VCC 2  of IC 2 ) and the second source terminal VSS 1  (VSS 2 ). The switch SW 1  (the switch SW 2 ) makes current of constant current source Iref 4  (Iref 8 ) to selectively flow. As shown in  FIG. 1 , in this embodiment, the switch SW 1  of IC 1  is set to be conduction state, and the switch SW 2  of IC 2  is set to be non-conduction state. 
         [0037]    Hereinafter, the IC 1  in  FIG. 2  is described as an example. During normal operation, current Iref generated by the constant current source flows through the input terminals V 2 -V 4 , VSS 1 , and lines L 2 -L 5  to the negative terminal of battery cell (see an arrow in  FIG. 2 ). That is, in this embodiment, when there is no disconnection in lines L 1 -L 8 , current Iref generated by constant current source constantly flows into each input terminal. 
         [0038]    When disconnection is caused in the line L 3 , current, which has flowed from VCC 1  to V 3 , does not flow into the input terminal V 3 , but it flows into voltage sensor side (see a dashed arrow in  FIG. 2 ). As a result, node potential (see M in  FIG. 2 ) between the voltage sensors rises and the voltage sensor outputs a value which is not detected during normal operation. With this operation, disconnection of lines connected between the battery cells and the voltage monitoring apparatus can be detected. 
         [0039]    Hereinafter, the description will be made on the case in which the line L 5  is disconnected in the voltage sensor module. As described above, the constant current source Iref 4  is provided between the VCC 1  and VSS 1  of IC 1 , and the switch SW 1  is set to be conduction state. Hence, if the line L 5  does not come down, the current Iref generated by Iref 4  flows to a negative terminal side of the battery cell C 4  through the source terminal VSS 1  and L 5 . On the other hand, when disconnection is caused in the line L 5 , current which is generated by Iref 4  flows toward the input terminal V 5  (node N 4 ) and VCC 2  of IC 2 . Therefore, potential of the input terminal V 5  rises, and potential between the input terminals V 5  and V 6  rises. That is, in the voltage monitoring apparatus  10  configured as  FIG. 1 , when disconnection is caused in the line L 5  connected to source potential of voltage sensor module, potential of input terminal V 5  becomes increase. 
         [0040]    In the voltage monitoring apparatus configured as described above, the voltage sensor module in this embodiment is configured as follows.  FIG. 3  shows the voltage sensor module IC 2  of the first embodiment of this invention. Hereinafter, in drawings used for explaining the embodiments, if not otherwise specified, the current source for detecting disconnection as described above is omitted. However, the current source for detecting disconnection is actually connected.  FIG. 3  shows the case in which disconnection is caused in the line L 5 . 
         [0041]    As shown in  FIG. 3 , the voltage sensor module IC 2  comprises a plurality of voltage sensors SEN 1 -SEN 4 , and output logic circuits LOG 1  and LOG 2 . Each voltage sensor detects excess voltage and low voltage of battery cell, so as to output the excess voltage signal and the low voltage signal. When the lines L 5 -L 9  to connect the battery cells and the voltage sensor modules come down, each voltage sensor also detects abnormal potential and outputs the excess voltage signal and the low voltage signal. Hereinafter, in order to distinguish the excess voltage detect signal from low voltage detect signal output from IC 1  and IC 2 , detect signals output from comparators are simply called as excess voltage signal and a low voltage signal or potential signal. When any voltage sensor outputs the excess voltage signal or the low voltage signal, the output logic circuit LOG 1  or LOG 2  outputs the excess voltage detect signal or the low voltage detect signal as IC 2  based on the voltage signal of the voltage sensor. In this embodiment, the output logic circuit comprises an OR circuit and a plurality of invertors which operate between VCC 2  and VSS 2 . 
         [0042]    Each voltage sensor SEN 1 -SEN 4  comprises a voltage divider resistor for low voltage detection R 1 , a voltage divider resistor for excess voltage detection R 2 , a reference potential circuit VREF, a comparator for low voltage detection CMP 1 , and a comparator for excess voltage detection CMP 2 . The comparator for excess voltage detection CMP 2  compares a divided point potential (described as A in  FIG. 3 ) of the voltage divider resistor for excess voltage detection R 2  and an output potential Vref of reference potential circuit VREF. When the divided point potential is higher than the output potential Vref, the comparator for excess voltage detection CMP 2  outputs the excess voltage signal. In the same way, the comparator for low voltage detection CMP 1  compares a potential of the divided point voltage of the voltage divider resistor for low voltage detection R 1  and the output potential Vref of the reference potential circuit. When the divided point potential is lower than the output potential Vref, the comparator for low voltage detection CMP 1  outputs the low voltage signal. The comparators CMP 1  and CMP 2  are driven with operation potential between VCC 2  and VSS 2 . 
         [0043]    In this embodiment, the voltage sensor SEN 1  which is the uppermost voltage sensor of IC 2  further comprises a switch for hysteresis HSW 1 . This switch HSW 1  operates based on the output of the comparator for excess voltage detection CMP 2 . In this embodiment, the switch for hysteresis HSW 1  is connected so that a part of resistors between a divided point A and the node N 4  is shorted. For example, when the comparator for excess voltage detection outputs high level signal, the switch for hysteresis HSW 1  is set to be conduction state. Hence, output of comparator for excess voltage detection CMP 2  has hysteresis characteristic. That is, a comparator having hysteresis characteristic is configured with the switch HSW 1 , the uppermost resistor of resistor R 2  and the comparator for excess voltage detection CMP 2 . A delay circuit D 1  is provided between the comparator for excess voltage detection CMP 2  of uppermost voltage sensor SEN 1  and the output logic circuit LOG 2 . 
         [0044]    Hereinafter, operations of voltage monitoring apparatus  10  configured described above will be explained.  FIG. 4A  shows a node N 4  potential (terminal V 5 ), a divided point A potential, output of comparator for excess voltage detection CMP 2  in the voltage sensor SEN 1 , output of output logic circuit LOG 2  and leak current flowing through the output logic circuit.  FIG. 4A  shows waveforms of these signals on the condition in which the line L 5  is disconnected in this embodiment.  FIG. 4B  shows waveforms when there is not switch for hysteresis HSW 1  and the delay circuit D 1  in this embodiment for the sake of comparison. A voltage F in  FIG. 4B  corresponds to the node N 4  potential in  FIG. 4A , a voltage G to the divided point A potential, a voltage H to the output of comparator for excess voltage detection, a voltage I to the output of output logic circuit, and a voltage J to the leak current of output of output logic circuit. Each voltage f-j in  FIG. 4B  shows enlarged portion of the voltage F-J. 
         [0045]    It is assumed that the line L 5  comes down at the time T 1  in  FIG. 4A . When disconnection is caused in the line L 5  at the time T 1 , the node N 4  potential becomes to increase with the current source Iref 4 . The divided point A potential rises based on the increase of node N 4  potential. Hence, when the divided point A potential is higher than the reference potential Vref at a time T 2 , output of comparator for excess voltage detection turns high level (see output of comparator for excess voltage detection in  4 A). 
         [0046]    Because output of comparator for excess voltage detection is high level, the switch for hysteresis HSW 1  becomes conduction state. As part of resistors between the node N 4  and the divided point A is shorted by the switch HSW 1 , the divided point A potential rises (see divided point A potential in  FIG. 4A ). 
         [0047]    Output of comparator for excess voltage detection CMP 2  is input to the OR circuit of output logic circuit LOG 2  through the delay circuit D 1 . As the delay circuit D 1  is provided between the comparator for excess voltage detection CMP 2  of voltage sensor SEN 1  and the output logic circuit LOG 2 , the OR circuit of output logic circuit LOG 2  outputs high level at the time T 3  (see output of output logic circuit). At the time T 3 , a certain time is passed from when the comparator for excess voltage detection CMP 2  outputs high level. 
         [0048]    At this time, leak current flows between VCC 2 -VSS 2  (see leak current of output logic circuit), and the VCC 2  potential becomes low. Hence, the node N 4  potential connected to the VCC 2  becomes low. The divided point A potential becomes low as potential of the node N 4  falls. However, in this embodiment, when the comparator for excess voltage detection CMP 2  outputs high level at the time T 2 , the switch for hysteresis HSW 1  turns conduction state. This operation sets the divided point A potential increase. Hence, even if leak current flows to the output logic circuit, the divided point A potential does not become Vref or below. Further, change does not occur in the output of comparator for excess voltage detection CMP 2  (see divided point A potential and output of output logic circuit in  FIG. 4A ). 
         [0049]    On the other hand, it is assumed that there is no delay circuit D 1  as  FIG. 4B , the comparator for excess voltage detection CMP 2  outputs high level, and almost at the same time, the OR circuit outputs high level. The comparator for excess voltage detection detects excess voltage, and at the same time, leak current flows. As a result, this leak current makes VCC 2  low. In this configuration, because of lowering of VCC 2  caused by leak current, divided potential becomes Vref or below. Hence, output of comparator for excess voltage detection oscillates and it makes operation unstable. The voltages f-j of  FIG. 4B  is waveforms around time T 2 , when output of comparator for excess voltage detection oscillates. As shown in upper portion of chart, in this case, output of comparator for excess voltage detection turns high level and low level repeatedly, because the divided point A potential increases and decreases from reference potential Vref. As a result, operations become unstable. 
         [0050]    As described above, in this embodiment, hysteresis characteristic is set for the voltage sensor SEN 1  corresponding to a connect portion between ICs. And after the predefined time is passed from when the comparator for excess voltage detection detects excess voltage (after outputting the excess voltage signal), output of output logic circuit is set to be inverted. This operation can prevent the false operation as follows from taking place. The voltage monitoring apparatus can not detect disconnection caused by leak current flowing into output logic circuit LOG 2  and unstable output is caused. 
       Second Embodiment 
       [0051]      FIG. 5  shows a voltage monitoring apparatus according to a second embodiment in this invention.  FIG. 5  shows the voltage monitoring apparatus of second embodiment comprising IC 3 , which has the same configuration as IC 1 , connected to the IC 2  of  FIG. 1  and  FIG. 3 . Hereinafter, the case will be explained in which disconnection is caused in a line L 9  corresponding to the connect portion between IC 2  and IC 3  in this voltage monitoring apparatus  20 . 
         [0052]    When the line L 9  comes down, current from positive terminal of battery cell C 9  does not flow into current sources Iref 9 -Iref 12  of IC 3 . When disconnection is caused in the line L 9 , current from VSS 2  terminal (node N 5 ) flows into Iref 9 -Iref 12 . Hence, VSS 2  terminal potential becomes lower and potential between V 8  and VSS 2  in IC 2  becomes larger. As a result, a voltage sensor connected between V 8  and VSS 2  of IC 2  detects excess voltage and outputs the excess voltage detect signal. This embodiment prevents false operation of IC 2 . 
         [0053]      FIG. 6  shows a circuit diagram of IC 2  according to the second embodiment. In this embodiment, in addition to the voltage sensor SEN 1 , a switch for hysteresis HSW 2  is provided also in a voltage sensor SEN 4 . A delay circuit D 2  is provided between output of comparator for excess voltage detection CMP 2  of a voltage sensor SEN 4  and output logic circuit LOG 2 . For explaining, a part of numbers is omitted.  FIG. 6  has the same configuration as the circuit in  FIG. 3  except the switch HSW 2  and the delay circuit D 2 . 
         [0054]    In this embodiment, when the comparator for excess voltage detection of voltage sensor SEN 4  outputs detection of excess voltage as the first embodiment, the switch for hysteresis HSW 2  turns conduction state.  FIG. 7  shows a node N 5  potential, a divided point B potential, output potential Vref of reference potential circuit VREF, output of comparator for excess voltage detection CMP 2  in the voltage sensor SEN 4 , output of output logic circuit LOG 2 , and leak current flowing into output logic circuit on the condition that disconnection happens to the line L 9  in the voltage monitoring apparatus  20  of the second embodiment. 
         [0055]    It is assumed that disconnection is caused in the line L 9  in  FIG. 6  at the time T 21  of  FIG. 7 . When disconnection is caused in the line L 9  at the time T 21 , the node N 5  potential becomes down based on the current source IC 3 . The reference potential Vref and the divided point B potential fall down according to fall of node N 5  potential (terminal VSS 2  potential). At this time, falling gradient of node N 5  potential has slower pace than the reference potential Vref because of the potential divide resistor R 2  (see divided point B potential in  FIG. 7 ). When the divided point B potential becomes higher than Vref at the time T 22 , output of comparator for excess voltage detection CMP 2  becomes high level (see output of comparator for excess voltage detection in  FIG. 7 ). 
         [0056]    Because output of comparator for excess voltage detection becomes high level, the switch for hysteresis HSW 2  turns conduction state. With the switch for hysteresis HSW 2 , a part of resistors between the terminal V 8  and the divided point B potential is set to be shorted. Hence, the divided point B potential increases at the time T 22  (see divided point B potential in  FIG. 7 ). 
         [0057]    Output of comparator for excess voltage detection CMP 2  is input to the OR circuit of output logic circuit LOG 2  through the delay circuit D 2 . The delay circuit D 1  is provided between the comparator for excess voltage detection CMP 2  of voltage sensor SEN 4  and the output logic circuit LOG 2 . Hence, the OR circuit of output logic circuit LOG 2  outputs high level at the time T 23 . At the time T 23 , a certain time is passed from when the comparator for excess voltage detection  24  outputs high level (see output of output logic circuit). 
         [0058]    At this time, leak current flows between VCC 2  and VSS 2  (see leak current of output logic circuit in  FIG. 7 ) and VSS 2  and Vref rise. However, in this embodiment, when the comparator for excess voltage detection CMP 2  outputs high level at the time T 2 , the switch for hysterisis HSW 2  becomes conduction state. This operation sets the divided point B potential increase. Hence, even if leak current flows into the output logic circuit LOG 2 , the divided point B potential does not become Vref or below, and output of comparator for excess voltage detection CMP 2  does not change (see divided point B potential and output of output logic circuit in  FIG. 7 ). 
         [0059]    As described above, this invention can be applied to the voltage sensor SEN 4  connected to the line, which is the connect portion between IC 2  and lower voltage sensor module (IC 3 ). It can prevent false operation of voltage sensor module. 
       Variant Embodiment 1 
       [0060]      FIG. 8  shows a variant embodiment of voltage monitoring apparatus according to embodiments of this invention. The variant also has function of detecting disconnection. This embodiment differs from the first and the second embodiments in the way of detecting disconnection. In the voltage monitoring apparatus shown in  FIG. 8 , a resistor is connected between input terminals of voltage sensor. The value of resistor R 3  connected between input terminals of voltage sensor SEN 1  is different from the value of resistor R 4  connected between input terminals of voltage sensor SEN 2 . The resistors R 3  and R 4  are connected alternately between input terminals of the other voltage sensors below. 
         [0061]    Hereinafter, operation of detecting disconnection in the voltage monitoring apparatus configured as described above is explained. The resistor R 4  having low resistance value is connected to a forth voltage sensor which is not shown of IC 1 . The resistor R 3  having high resistance value is connected to the voltage sensor SEN 1  in  FIG. 8 . For example, if disconnection is caused in the line L 5 , on the condition that resistance value connected to resistors R 3  and R 4  in parallel is sufficiently large, the node N 4  potential becomes the divided potential, divided by resistance ratio of resistors R 3  and R 4  between potential difference of two battery cells C 4  and C 5 . Therefore, when the resistor value of resistor R 3  is larger, the node N 4  potential rises and excess voltage is detected. 
         [0062]    When excess voltage is detected based on disconnection as described above, setting hysteresis, operation of delay circuit and else for stabilizing output of IC 2  is the same as the circuit shown in  FIG. 3 . Hence, explanation of setting hysteresis, operation of delay circuit and else is omitted. 
         [0063]    The case in which potential is detected based on potential change caused by current source is described as above. However, this invention can be also applied to the other case. 
       Third Embodiment 
       [0064]      FIG. 9  shows a voltage monitoring apparatus according to a third embodiment. In the first and second embodiments as described above, the case is explained in which the comparator for excess voltage detection CMP 2  operates between the potential source VCC 2  and VSS 2  of voltage sensor module (IC 2 ). On the other hand, in this embodiment, the comparator for excess voltage detection CMP 2  and the comparator for low voltage detection CMP 1  operate with potential source of one battery cell.  FIG. 9  shows the case in which disconnection is caused in the line L 2  of voltage monitoring apparatus connected as shown in  FIG. 1 , for example. In this case, the terminal V 2  potential rises with the current source Iref 1  and excess voltage is detected. 
         [0065]    When the comparators for low voltage detection CMP 1  and excess voltage detection CMP 2  operate with potential source of one battery cell, outputs of those become the terminal V 2  potential at high level, and the terminal V 3  potential at low level. However, the output logic circuits LOG 1 , LOG 2 , which are connected to output side, operate between VCC 1  and VSS 1 . Output of comparator, operating with potential difference of one battery cell, can not drive the output logic circuit. Hence, in this embodiment, the level shift circuits LS 1 , LS 2 , which change potential level for outputs of comparators for low voltage detection CMP 1  and excess voltage detection CMP 2 , are provided in the both comparators. 
         [0066]    Hereinafter, leak current of level shift circuit will be described. False operation may be caused by leak current of level shift circuit. 
         [0067]      FIG. 10  shows a general level shift circuit. The level shift circuit comprises an inverter INV 1 , a first level shift circuit LS 2   1 , and a second level shift circuit LS 2   2 . Taking the case in which the level shift circuit is connected between V 2  and V 3  in  FIG. 9  for instance. Leak current flows through the level shift circuit. The comparator outputs a signal of terminal V 2  level as high level or a signal of terminal V 3  level as low level. Using the inverter INV 1  in the level shift circuit LS 2 , the signal output from the comparator is converted to a pair of complementary signals. The pair of complementary signals is input to the first level shift circuit LS 2   1 . As the inverter INV 1  is provided between terminals V 2  and V 3 , output level of inverter INV 1  is also terminal V 2  level or terminal V 3  level. The first level shift circuit LS 2   1  converts terminal V 2  level representing high level into VCC 1  level and outputs VCC 1  level. At this time, terminal V 3  level representing low level is output without being converted. When low level is input to the second level shift circuit LS 2   2 , the second level shift circuit LS 2   2  converts terminal V 3  level representing low level into VSS 1  level. In this way, the level shift circuit LS 2  converts the signal of terminal V 2  level representing high level and the signal of terminal V 3  level representing low level into the signal of VCC 1  level representing high level and the signal of VSS 1  level representing low level and outputs them. 
         [0068]    In the level shift circuit as described above, an inversion signal of input signal is generated in the first inverter. Hence, when the inverter inverts the input signal, leak current flows between V 2  and V 3 . This leak current changes terminal V 2  potential and terminal V 3  potential as leak current does in the other embodiments. As a result, false operation of the comparator for excess voltage detection or else may be caused. 
         [0069]    In this embodiment, a switch for hysteresis HSW 3  is provided so that a part of voltage divider resistor for excess voltage detection is shorted to terminal V 2  side. A delay circuit is provided between the comparator for excess voltage detection CMP 2  and the level shift circuit LS 2 . When the comparator for excess voltage detection CMP 2  outputs high level, hysteresis characteristic is given to output signal of the comparator CMP 2  with this configuration. After this operation, with outputting high level to the level shift circuit LS 2 , it can prevent false operation of the voltage monitoring apparatus. 
         [0070]    In this embodiment, hysteresis is set for the comparator for excess voltage detection in addition to the situation in which line corresponding to connect portion between ICs is disconnected. And certain delay time is set before the comparator for excess voltage detection outputs signal. Hence, it can prevent false operation of the voltage monitoring apparatus. 
         [0071]    In these embodiments described above, configuration of delay circuit is not explained. However, a delay circuit configured with a plurality of series-connected inverters or else is not preferable because leak current flows into these inverters. Hence, it is preferable that the delay circuit using resistance component and capacitor component is applied to these embodiments. However, if the line between output of comparator and input of logic circuit has predefined delay property, this portion can be used as the delay circuit. 
         [0072]    In this embodiment, with using the switch for hysteresis, hysteresis is set for the comparator. However, if the comparator itself has hysteresis, advantages of this invention can also be obtained without using the switch for hysteresis. As described above, embodiments of this invention are described in detail, but the configuration can be changed in many ways in this invention. For example, the case is described above in which false operation is caused in at detecting excess voltage, but this invention can also be applied to the operation in detecting low voltage. 
         [0073]    It is apparent that the present invention is not limited to the above embodiment, but may be modified and changed without departing from the scope and spirit of the invention.