PATENT ABSTRACT
A non-volatile memory device includes a memory cell array including memory cells, each memory cell being defined at an intersection of a word line and a bit line. A page buffer is coupled to the memory cell array via a sensing line. The page buffer comprises a first latch unit including a first latch circuit and coupled to the sensing line, the first latch unit being configured to be activated during a copy-back program operation to read data stored in a first memory cell and reprogram the data to a second memory cell that is different from the first memory cell. The page buffer also includes a second latch unit including a second latch circuit and coupled to the sensing line, the second latch unit being configured not to be activated during the copy-back operation and be activated during program, read, and verification operations, the second latch unit configured to receive data to be programmed in the memory cells and store the data during the program operation, the second latch unit configured to read the data programmed in the memory cells and store the read data during the read and verification operations.

PATENT DESCRIPTION
BACKGROUND OF THE INVENTION  
       [0001]     The present invention relates to non-volatile memory devices and methods for operating them. More particularly it relates to a NAND-type flash memory device capable of shortening a copy-back program time by changing an operation of a page buffer, and a method for operating the page buffer.  
         [0002]     Recently, there has been increasing demand for semiconductor memory devices which do not require periodic refresh operations and are electrically programmable and erasable. A program operation writes data to the memory cells.  
         [0003]     To achieve high integration of semiconductor memory devices, NAND-type flash memory devices have a plurality of memory cells that share a common connection. In other words, neighboring cells share a drain and source with each other. Unlike NOR-type flash memory cells, NAND-type flash memory cells are capable of reading out information sequentially.  
         [0004]     NAND-type flash memory devices employ a page buffer in order to store large quantities of information or read out stored data within a short time. The page buffer receives a large amount of data from I/O (Input/Output) PAD to provide the data to a memory cell or store the data in the memory cell to output it. In general, page buffers are comprised of a single register so as to temporarily store data. Recently, NAND-type flash memory devices with a dual register have been introduced for the purpose of improving programming speed when programming a large amount of data.  
         [0005]     Copy-back program operation refers to transmiting data stored in a defective cell to a normal cell utilizing page buffers.  
         [0006]      FIG. 1  is a block diagram illustrating a copy-back program operation of a conventional NAND-type flash memory device.  
         [0007]     With reference to  FIG. 1 , a conventional copy-back program operation is carried out as follows. Data stored in a defective cell is read out to a first latch unit  24  of a page buffer  20 . The data read out from the first latch unit  24  is transmitted to a second latch unit  25 . The transmitted data in the second latch unit  25  is programmed to another memory cell that presumably functions properly (or “normal cell”).  
         [0008]      FIG. 2  is a block diagram illustrating program, read, and verification operations of a conventional NAND-type flash memory device.  
         [0009]     With reference to  FIG. 2 , if the first latch unit  24  is selected from the first and second latch units  24  and  25 , the second latch unit  25  is inactivated, and program operation  51  and read and verification operation  52  are carried out in the first latch unit  24 . In contrast, if the second latch unit  25  is selected, the first latch unit  24  is inactivated, and program operation  61  and read, and verification operation  62  are carried out in the second latch unit  25 .  
         [0010]     In the above-mentioned copy-back program operation, there is a high probability that errors occur in transmitting data between the first latch unit  24  and the second latch unit  25 . Accordingly, a timing margin may not be sufficiently secured during a copy-back program operation.  
       BRIEF SUMMARY OF THE INVENTION  
       [0011]     According to embodiments of the present invention, there is provided a non-volatile memory device capable of eliminating errors and reducing copy-back program operation time by changing operations of latch units at page buffers in transmitting data between latch units during a copy-back program operation and a method for operating the page buffers thereof.  
         [0012]     In further embodiments of the present invention, a non-volatile memory device comprises an array including memory cells disposed at intersections of word lines and bit lines and a plurality of page buffers connected to the array by a sensing line. Each of the page buffers comprises a first latch unit and a second latch unit. The first latch unit becomes activated during a copy-back program operation and reads data programmed to a defective memory cell to store the data in a normal cell. The second latch unit is inactivated during the copy-back operation and activated during program, read, and verification operations. In addition, the second latch unit is configured to receive data to be programmed in the memory cells and store the data during the program operation. Furthermore, the second latch unit is configured to read the data programmed in the memory cells and store the read out data during the read and verification operations.  
         [0013]     In another embodiment of the present invention, a method for operating a page buffer of a non-volatile memory device comprises an array including memory cells disposed at intersections of word lines and bit lines and a plurality of page buffers connected to the array by a sensing line and having first and second latch units. The method according to the present invention comprises activating the first latch unit of the page buffer and inactivating the second latch unit of the page buffer during a copy-back program operation and activating the second latch unit and inactivating the first latch unit during program, read, and verification operations. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings:  
         [0015]      FIG. 1  is a block diagram illustrating a copy-back program operation of a conventional NAND-type flash memory device;  
         [0016]      FIG. 2  is a block diagram illustrating program, read, and verification operations of a conventional NAND-type flash memory device;  
         [0017]      FIG. 3  is a block diagram illustrating a copy-back program operation of a NAND-type flash memory device according to one embodiment of the present invention;  
         [0018]      FIG. 4  is a block diagram illustrating program, read, and verification operations of a NAND-type flash memory device according to one embodiment of the present invention;  
         [0019]      FIG. 5  is a circuit diagram the NAND-type flash memory device shown in  FIGS. 3 and 4 ;  
         [0020]      FIG. 6  is a circuit diagram illustrating the copy-back program operation of the NAND-type flash memory device shown in  FIG. 5 ; and  
         [0021]      FIG. 7  is a circuit diagram illustrating program, read, and verification operations of the NAND-type flash memory device shown in  FIG. 5 .  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]     The present invention will be described below in more detail using specific embodiments and the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided for illustrative purposes to those skilled in the art. Like numerals refer to like elements.  
         [0023]     Hereinafter, the invention will be described with reference to an exemplary embodiment of the present invention in conjunction with the accompanying drawings.  
         [0024]      FIG. 3  is a block diagram illustrating a copy-back program operation of a NAND-type flash memory device according to a preferred embodiment of the present invention.  
         [0025]     With reference to  FIG. 3 , a copy-back program operation is performed as follows. Data is read out from a defective cell by charging a sensing line S 0  utilizing a precharging unit  220  to store the read out data in a first latch unit  230  (step S 401 ). Then, the read out data stored in the first latch unit  230  is reprogrammed to a normal cell (step S 402 ).  
         [0026]     As stated above, the NAND-type flash memory device performs a copy-back program operation utilizing the first latch  230  and not the second latch  240 .  
         [0027]      FIG. 4  is a block diagram illustrating program, read, and verification operations of a NAND-type flash memory device according to a preferred embodiment of the present invention.  
         [0028]     With reference to  FIG. 4 , program  410 , read  420 , and verification  430  operations are performed by the second latch unit  240 . The first latch unit  230  is in an inactivated state during the program, read, and verification operations.  
         [0029]      FIG. 5  is a detailed circuit diagram showing the NAND-type flash memory device of  FIGS. 3 and 4 .  
         [0030]     With reference to  FIG. 5 , the NAND-type flash memory device includes a memory cell array  100 , a page buffer  200 , and a column selection unit  300 .  
         [0031]     In the memory cell array  100 , BLe indicates even numbered bit lines, and BLo indicates odd numbered bit lines. A multiplicity of memory cells MC 1  through MCn are connected to the bit line BLe, and the remainder of memory cells are connected to the bit line BLo. The memory cells connected to one word line (e.g., WL 1 ) forms one page.  
         [0032]     The page buffer  200  is connected between the memory cell array  100  and the column selection unit  300 . Although only one page buffer is shown in  FIG. 5 , a plurality of page buffers  200  may be present in the flash memory device. The page buffer  200  is connected through the sensing line S 0  to the bit lines BLe and BLo and includes a bit line selection unit  210 , the precharging unit  220 , the first latch unit  230 , and the second latch unit  240 .  
         [0033]     The bit line selection unit  210  includes transistors N 11  through N 14 . One end of the transistor N 11  is connected to the bit line BLe, and the other end of that is connected to a line providing a power supply signal VIRPWR. The transistor N 11  is turned on/off by applying a gate control signal DISCHe to a gate. This transistor N 11  is turned on by the gate control signal DISCHe so as to apply a power voltage VCC as the power supply signal VIPWR to the bit line BLe and program the corresponding memory cells. One end of the transistor N 12  is connected to the bit line BLo, and the other end of is connected to a line providing a power supply signal VIRPWR. The transistor N 12  is turned on/off by applying the gate control signal DISCHo to a gate. This transistor N 12  is turned on by the gate control signal DISCHo so as to apply the power voltage VCC as the power supply signal VIRPWR to the bit line and program the corresponding memory cells. The NMOS transistor N 13  connects the bit line BLe to the sensing line S 0  in response to a bit line selection signal BSLe. The NMOS transistor N 14  connects the bit line BLo to the sensing line S 0  in response to a bit line selection signal BLe.  
         [0034]     The precharging unit  220  is connected between the power voltage VCC and the sensing line S 0  and includes a PMOS transistor P 11  turned on/off by receiving a precharge signal PRECHb. The PMOS transistor P 11  precharges the sensing line S 0  to the power voltage VCC in reading out data stored in the memory cell.  
         [0035]     The first latch unit  230  is activated only during copy-back program operation and includes NMOS transistors N 21  through N 24 , a first latch circuit LT 1 , and an inverter IV 3 . The first latch circuit LT 1  comprises inverters IV 1  and IV 2  and stores data read from the memory cells. The NMOS transistor N 23  is connected between a node QA of the first latch circuit LT 1  and a ground voltage VSS. In addition, the NMOS transistor N 23  initializes the node QA to “0” and the node QAb to “1” when a reset signal MRST is applied to its gate. The NMOS transistor N 21  is turned on/off in response to a signal of the sensing line S 0 , and the NMOS transistor N 22  is turned on/off in response to a latch signal MLCH. Turning on the NMOS transistor N 21  and the NMOS transistor N 22  at the same time, changes the node QAb to “0” and the node QA to “1”. The inverter IV 3  inverts data of the node QA and then outputs the data. The NMOS transistor N 24  is turned on by a copy-back signal CPBK during a copy-back program operation to transmit data outputted by the inverter IV 3  to a selected bit line (e.g., BLe) through the sensing line S 0 .  
         [0036]     The second latch unit  240  is activated during program, read, and verification operations. The second latch unit  240  includes NMOS transistors N 31  through N 37 , a second latch circuit LT 2 , and an inverter IV 6 . The second latch circuit LT 2  includes inverters IV 3  and IV 4  and stores data that is read out from the memory cells. The NMOS transistor N 33  is provided between a node QA of the second latch circuit LT 2  and a ground voltage VSS. In addition, the NMOS transistor N 33  initializes the node QB to “0” and the node QBb to “1” when a reset signal CRST is applied to its gate. The NMOS transistor N 31  is turned on/off in response to a signal of the sensing line S 0 , and the NMOS transistor N 32  is turned on/off in response to a latch signal CLCH. Turning both NMOS transistor N 31  and NMOS transistor N 32  on at the same time changes the node QBb to “0” and the node QB to “1”. The inverter IV 6  inverts data of the node QBb and then outputs the data. The NMOS transistor N 34  transfers the data that is received from a data line DL to the second latch circuit LT 2  in response to a data input signal DL. The NMOS transistor N 35  transfers the data that received from the data line DL to the second latch circuit LT 2  in response to a data input signal nDI. The NMOS transistor N 36  is turned on by a program signal PGM during a program operation, thereby transferring data outputted from the inverter IV 6  to the sensing line S 0  in order to program the data to the memory cells, i.e., the memory cells that that are associated with the selected bit line BLe or BLo. The NMOS transistor N 37  is turned on by a read-out signal PBD 0  during a read operation, thereby transferring data outputted to the selected bit line BLe or BLo, that is, data outputted from the inverter IV 6  to the data line DL by the column selection unit  300 . A PMOS transistor P 13  is connected between the power voltage VCC and a node nWD 0  and is turned on/off by applying data of the node QB of the second latch circuit LT 2  to the gate. The PMOS transistor P 13  verifies pass/fail of a program according to whether the node nWD 0  is in a floating state or logically high.  
         [0037]     The NMOS transistor N 38  is turned on by a signal CELLIV during a test operation and employed to measure voltage and current of the page buffer.  
         [0038]     The column selection unit  300  connected between the page buffer  200  and the data line DL includes two NMOS transistors N 41  and N 42 , which are controlled by column selection signals YA and YB. The column signal YA and YB are generated by a column addressing unit (not shown).  
         [0039]      FIG. 6  is a circuit diagram illustrating a copy-back program operation of the NAND-type flash memory device according to a preferred embodiment of the present invention.  
         [0040]     A copy-back program operation proceeds in accordance with the following steps. A word line WL 1  is enabled, and stored data in the memory cell MC 1  is read out by selecting the bit line BLe in order to reprogram the stored data to the memory cell MC 2 .  
         [0041]     Nodes QA and QAb of the first latch circuit LT 1  are initialized to “0” and “1”, respectively. Then, the PMOS transistor P 11  is turned on, thereby precharging the sensing line S 0  to a level of the power voltage VCC. Since the memory cell MC 1  is a programmed cell, the sensing line S 0  is maintained in a precharged state.  
         [0042]     The NMOS transistors N 21  and N 22  are turned on so that the nodes QA and QAb of the first latch circuit LT 1  are inverted to “1” and “0”, respectively (Read operation  401 ). Data “1” of the node QA of the first latch circuit LT 1  is inverted to “0” by the inverter IV 3  to be outputted. In this case, the NMOS transistor N 24  is turned on by the copy-back signal CBPK, so that data “0” outputted from the inverter IV 3  is transmitted to the selected bit line BLe by the sensing line S 0 . As a result, the memory cell MC 2  is reprogrammed (Program operation  402 ).  
         [0043]     As mentioned above, the copy-back program operations  401  and  402  are carried out by the first latch unit  230 .  
         [0044]      FIG. 7  is a circuit diagram illustrating program, read, and verification operations of the NAND-type flash memory device according of one embodiment of the present invention.  
         [0045]     For example, a method for programming data in a memory cell selected by the word line WL 1  and the bit line BLo (Program operation  410 ) will be explained herein.  
         [0046]     During a program operation, if data “0” transmitted from the data line DL is inputted to the NMOS transistor N 35  by the column selection unit  300 , the NMOS transistor N 35  is turned on by the data input signal nDI, thereby storing the data “0” in the second latch circuit LT 2 . As a result, the nodes QB and QBb of the second latch circuit LT 2  become “0” and “1”, respectively. At this time, the inverter IV 6  inverts data “1” of the node QBb of the second latch node LT 2  to “0”. The NMOS transistor N 38  is turned on by the program signal PGM to program data in the memory cell by applying the data “0” to the selected bit line (e.g., BLo) by the sensing line S 0 .  
         [0047]     Next, a method for reading data stored in a memory cell selected by the word line WL 1  and the bit line BLo (Read operation  420 ) will be explained.  
         [0048]     During a read operation, the PMOS transistor P 11  is turned on to precharge the sensing line S 0  to power voltage VCC. In this case, if the sensing line S 0  is maintained in a precharged state, the NMOS transistors N 31  and N 32  are turned on. As a result, the nodes QBb and QB of the second latch circuit LT 2  become “0” and “1”. At this time, the inverter IV 6  inverts data “0” of the node QBb of the second latch circuit LT 2  to output data “1”. Contemporaneously, the NMOS transistor N 37  is turned on by the read out signal PBD 0 , thereby transmitting the data “1” to the data line DL through the column selection unit  300 .  
         [0049]     Next, a method for verifying whether data is normally programmed in a memory cell selected by the word line WL 1  and the bit line BLo (Verification operation  430 ) will be explained.  
         [0050]     The PMOS transistor P 11  is turned on to precharge the sensing line S 0  to power voltage VCC. In this case, if the sensing line S 0  is maintained in a precharged state, the NMOS transistors N 31  an N 32  are turned on, so that the nodes QBb and QB of the first latch circuit LT 2  become “0” and “1”, respectively. If so, the PMOS transistor P 13  is turned off by data “1” of the node QB of the second latch circuit LT 2 . Consequently the node nWD 0  is placed in a floating state and the program result is evaluated as “pass”. By contrast, if the sensing line S 0  is discharged, the NMOS transistors N 31  and N 32  become turned off, so that the nodes QBb and QB of the second latch circuit LT 2  are initially maintained to “1” and “0”. Thus, the PMOS transistor P 13  is turned on by data “0” of the node QB of the second latch circuit LT 2 . Consequently the node nWD 0  is raised to the power voltage VCC, and the program result is evaluated as “fail”.  
         [0051]     As previously mentioned, data is read out from a defective memory cell to be stored in a first latch unit. Then, the stored data of the first latch unit is not transmitted to a second latch unit but directly transmitted to a selected bit line. The transmitted data can then be reprogrammed in a memory cell. Therefore, the copy-back program operation speed is advantageously improved over a convention method where the second latch unit is used to reprogram the data.  
         [0052]     The present invention has been described in connection with the specific embodiments of the present invention and the accompanying drawings. It will be apparent to those skilled in the art that various substitution, modifications and changes may be made thereto without departing from the scope and spirit of the invention.