PATENT ABSTRACT
Disclosed is a variable drive current driver circuit, comprising: a pair of push-pull circuits for driving a load circuit complementarily; a first current source circuit for having a bias current flow into the pair of push-pull circuits; a second current source circuit for having the bias current flow out of the pair of push-pull circuits; and a control circuit for varying both the bias current flowed by the first current source circuit and the bias current flowed by the second current source circuit according to a control signal.

PATENT DESCRIPTION
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a variable drive current driver circuit.  
           [0003]    2. Description of the Prior Art  
           [0004]    According to the conventional standards, such as IEEE 1394 standards, a drive current of a signal transmitted between electronic devices, such as personal computers, video movies, or mini-disc players, connected mutually via a cable or the like is determined so as to become either of two kinds. When a certain electronic device is connected to another electronic device via a cable, the former have the latter notify the former of the standard of a signal that can be received by the latter, and the former transmits data with a drive current determined on the basis of this notification.  
           [0005]    [0005]FIG. 1 is a diagram showing a conventional driver circuit that is capable of varying a drive current of a signal. In the conventional technique, as shown in FIG. 1, either a driver circuit for a standard A or a driver circuit for a standard B is driven on the basis of, for example, a control signal of “0” or “1” so as to be able to cope with both a case where the electronic device of the opposite party receives a signal of one of two kinds of drive current defined by the standard and another case where the electronic device of the opposite party receives a signal of the other of the two kinds.  
           [0006]    In other words, if a control signal of “1” is inputted to the standard A driver circuit and the standard B driver circuit, then the standard A driver circuit is enabled and the standard B driver circuit is disabled. If a control signal of “0” is inputted to the standard A driver circuit and the standard B driver circuit, then the standard A driver circuit is disabled and the standard B driver circuit is enabled.  
           [0007]    In the conventional technique, however, it is necessary to prepare as many driver circuits as the number of kinds of the drive current defined by the standard. As a result, the circuit scale becomes large as the number of kinds of the drive current increases. Especially in such an electronic device that transmission and reception of a plurality of data are performed using one physical layer LSI, it is desired to prevent the circuit scale from becoming large.  
         SUMMARY OF THE INVENTION  
         [0008]    Therefore, an object of the present invention is to provide a variable drive current driver circuit having a small circuit scale.  
           [0009]    According to a first aspect of the present invention, there is provided a variable drive current driver circuit, comprising: a pair of push-pull circuits for driving a load circuit complementarily; a first current source circuit for having a bias current flow into the pair of push-pull circuits; a second current source circuit for having the bias current flow out of the pair of push-pull circuits; and a control circuit for varying both the bias current flowed by the first current source circuit and the bias current flowed by the second current source circuit according to a control signal.  
           [0010]    In the variable drive current driver circuit, the first current source circuit may comprise a current mirror circuit, and the control circuit may control an input current of the current mirror circuit according to the control signal.  
           [0011]    In the variable drive current driver circuit, the control circuit may control the input current by controlling a control terminal voltage of a transistor for flowing the input current.  
           [0012]    In the variable drive current driver circuit, the control of the control terminal voltage may be performed by changing, by a transistor which turns on or off according to the control signal, a magnitude of a load in which a current flowing out of a third current source flows.  
           [0013]    In the variable drive current driver circuit, the second current source circuit may comprise a transistor, and the control circuit may control a control terminal voltage of the transistor according to the control signal.  
           [0014]    In the variable drive current driver circuit, the control of the control terminal voltage may be performed by changing, by a transistor which turns on or off according to the control signal, a magnitude of a load in which a current flowing out of a third current source flows.  
           [0015]    According to a second aspect of the present invention, there is provided a variable drive current driver circuit, comprising: a pair of push-pull circuits for driving a load circuit complementarily; a first current source circuit for having a first bias current flow into the pair of push-pull circuits; a second current source circuit for having the first bias current flow out of the pair of push-pull circuits; a third current source circuit capable of having a second bias current flow into the pair of push-pull circuits; a fourth current source circuit capable of having the second bias current flow out of the pair of push-pull circuits; and a control circuit for varying both the second bias current flowed by the third current source circuit and the second bias current flowed by the fourth current source circuit according to a control signal.  
           [0016]    In the variable drive current driver circuit, the control circuit mayhave the third current source circuit have the second bias current flow nor not flow into the pair of push-pull circuit, and the control circuit may have the fourth current source circuit have the second bias current flow or not flow out of the push-pull circuit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 is a diagram showing a variable drive current driver circuit according to a conventional technique;  
         [0018]    [0018]FIG. 2 is a diagram showing such a state that electronic devices each incorporating a variable drive current driver circuit according to an embodiment of the present invention are connected to each other;  
         [0019]    [0019]FIG. 3 is a circuit diagram showing the configuration of a variable drive current driver circuit according to a first embodiment of the present invention;  
         [0020]    [0020]FIG. 4 is a circuit diagram showing the configuration of a variable drive current driver circuit according to a second embodiment of the present invention; and  
         [0021]    [0021]FIG. 5 is a circuit diagram showing the configuration of a variable drive current driver circuit according to a third embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]    Hereinafter, embodiments of the present invention will be described with reference to the drawings.  
         [0023]    [0023]FIG. 2 is a block diagram showing the configuration of a transmission system of the first embodiment according to the present invention. FIG. 2 shows a state that electronic devices  10  and  20  are connected to each other via a cable  30 . The electronic devices  10  and  20  include LSIs  12  and  22 , and instruction sections  11  and  21  for monitoring the operation of the LSIs  12  and  22  and instructing generation, transmission and reception of data mutually transmitted to the electronic devices  20  and  10 , respectively. The LSIs  12  and  22  incorporate variable drive current driver circuits  13  and  23  for transmitting data adjusted in drive current so that the data are received by the electronic devices  20  and  10 , and control circuits  14  and  24  for generating and outputting control signals to control drive currents of data transmitted by the variable drive current driver circuits  13  and  23 , respectively.  
         [0024]    Each of the instruction sections  11  and  21  is controlled by a CPU, which operates according to software and which is not illustrated. The control circuits  14  and  24  are incorporated in the LSIs  12  and  22  together with the variable drive current driver circuits  13  and  23 , respectively.  
         [0025]    [0025]FIG. 3 is a circuit diagram showing the first embodiment of the variable drive current driver circuit shown in FIG. 2.  
         [0026]    With reference to FIG. 3, the variable drive current driver circuit according to the first embodiment is supplied with a constant current Ia from a constant current source  100 . On the basis of the constant current Ia, the variable drive current driver circuit generates an output current. First, a current Ic is generated by a current mirror formed of transistors NMOS  11 , NMOS  12  and NMOS  15 . From the current Ic, a constant current Id1 is further generated by a current mirror formed of transistors PMOS  11  and PMOS  12 . Concurrently with them, a constant current Id2 is generated by a current mirror formed of transistors NMOS  11 , NMOS  12  and NMOS  16 . In this case it is necessary to design the drive circuit so as to satisfy the relation Id1=Id2 in order to balance the output currents. The current Id1 is outputted from the driver circuit to the outside, passed through resistors R 11  and R 12 , and drawn in as the current Id2. The output voltage is determined by the value of the current Id1 and values of the resistors R 11  and R 12 . A node Ve between the resistor R 11  and the resistor R 12  is a node of a common level. This node is supplied with a constant potential from a constant voltage source mainly including an operational amplifier.  
         [0027]    By the way, transistors PMOS  13  and NMOS  17  form a first push-pull circuit, whereas transistors PMOS  14  and NMOS  18  form a second push-pull circuit. Since a signal inputted to gates of the transistors PMOS  13  and NMOS  17  is complementary to a signal inputted to gates of the transistors PMOS  14  and NMOS  18 , the first push-pull circuit and the second push-pull circuit complementarily drive the resistors R 11  and R 12  serving as a load circuit.  
         [0028]    In accordance with the present invention, transistors NMOS  13  and NMOS  14  and a control signal input terminal are further added. The logic values of a control corresponds to CMOS levels. According to the logic value, the value of the drive current changes. In a case where the logic value of the control signal is “ 1 ,” a current Ib flows and a voltage Va becomes Va1. On the other hand, in a case where the logic value of the control signal is “0,” the current Ib does not flow and the voltage Va becomes Va2, wherein Va2&gt;Va1. The currents Ic, Id1 and Id2 when the logic value of the control signal is “0” are larger than those when the logic value of the control signal is “1”, respectively. As a result, two kinds of drive current according to the control signal can be implemented.  
         [0029]    [0029]FIG. 4 is a circuit diagram showing a second embodiment of a variable drive current driver circuit shown in FIG. 2.  
         [0030]    Comparing FIG. 4 with FIG. 3, it is apparent that the variable drive current driver circuit according to the second embodiment differs from the variable drive current driver circuit according to the first embodiment in that a control circuit is added to an output stage including transistors PMOS  24 , PMOS  25 , PMOS  26 , NMOS  25 , NMOS  26  and NMOS  27 . In the variable drive current driver circuit according to the first embodiment, the control circuit is added not to the output stage but to the constant current source side. In FIG. 4, the voltage Va is constant. In a case where the logic value of the control signal is “1,” currents Ic 1  and Ic 2  flow. In a case where the logic value of the control signal is “0,” currents Ic 1  and Ic 2  do not flow. When the logic value of the control signal is “1,” therefore, the sum of currents Ic 1  and Id1 or the sum of currents Ic 2  and Id2 becomes the drive current. When the logic value of the control signal is “0,” only the current Id1 or Id2 becomes the drive current. In the same way as the variable drive current driver circuit according to the first embodiment, the variable drive current driver circuit according to the second embodiment has two kinds of drive current controlled by the control signal.  
         [0031]    [0031]FIG. 5 is a circuit diagram showing the third embodiment of a variable drive current driver circuit shown in FIG. 2.  
         [0032]    Comparing FIG. 5 with FIG. 3, it is apparent that the variable drive current driver circuit according to the third embodiment is structured by preparing a plurality of sets of the transistors NMOS  13  and NMOS  14  of the variable drive current driver circuit according to the first embodiment and connecting the sets in parallel. Transistors NMOS  131 , NMOS  141 , NMOS  132 , NMOS  142 , . . . , NMOS  13 N and NMOS  14 N correspond to the plurality of sets of the transistors NMOS  13  and NMOS  14 . Gates of the transistors NMOS  141 , NMOS  142 , . . . , NMOS  14 N are supplied with their respective control signals. Therefore, the variable drive current driver circuit according to the third embodiment can drive its load with not only either of drive currents of two kinds but also any of drive currents of many kinds.  
         [0033]    It is a matter of course that the variable drive current driver circuit according to the second embodiment can be expanded so as to be capable of corresponding to many kinds of drive current, in the same way as expanding the variable drive current driver circuit according to the first embodiment to obtain the variable drive current driver circuit according to the third embodiment. In this case, a plurality of sets of the transistors PMOS  22 , PMOS  23  and NMOS  28  are prepared. The plurality of sets are connected in parallel with the transistor PMOS  24 . A plurality of sets of the transistors NMOS  23 , NMOS  24  and PMOS  27  are prepared. The plurality of sets are connected in parallel with the transistor NMOS  25 .