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shailja
/
fine-tuned-codegen-16B-Verilog
like
10
Text Generation
Transformers
PyTorch
shailja/Verilog_GitHub
codegen
code
Eval Results
Inference Endpoints
arxiv:
2212.11140
License:
bigcode-openrail-m
Model card
Files
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Community
3
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af0f1d3
fine-tuned-codegen-16B-Verilog
Commit History
uploading 16B Verilog LLM
af0f1d3
shailja-thakur
commited on
Dec 30, 2022
initial commit
c3b0acc
shailja
commited on
Dec 30, 2022
