Court Opinion

ID: 9515930
Source: CourtListenerOpinion
Date Created: 2023-08-06 23:10:27.755124+00
Date Added: 2024-06-11T09:09:07.783553
License: Public Domain

WALLACH, Circuit Judge,
dissenting.
The Board’s conclusion that the patent is anticipated is supported by substantial evidence, and therefore I dissent from the majority’s decision.
The dispositive question in this case is whether substantial evidence supports the Board’s finding that Farmwald discloses the step of “providing a signal to the memory device, wherein the signal indicates when the memory device is to begin sampling write data ....” '109 patent col. 42 11. 61-63. It is uncontested that Farm-wald’s DRAM contains “access-time registers” with various delay values. Farm-wald teaches sending a “request packet” from a memory controller to the DRAM with control information that, inter alia, selects an access-time register. The Board found that this request packet was a “signal” that “indicates” when the DRAM “is to begin sampling write data.” This is supported by substantial evidence. Although the delay value choices are stored in the DRAM, a reasonable person could conclude that the request packet is a “signal” that “indicates” when the DRAM “is to begin sampling write data.” Id. col. 42 11. 61-63; see Consol. Edison Co. v. Nat’l Labor Relations Bd., 305 U.S. 197, 229, 59 S.Ct. 206, 83 L.Ed. 126 (1938) (Substantial evidence “means such relevant evidence as a reasonable mind might accept as adequate to support a conclusion.”); In re Kotzab, 217 F.3d 1365, 1369 (Fed.Cir.2000) (“Substantial evidence is something less than the weight of the evidence but more than a mere scintilla of evidence.”).
The majority says that although Farm-wald’s request packets contain a bit, that bit merely selects an access-time register; it does not contain any timing information itself. However, given the Board’s broad construction of the term “signal,” which the majority accepts, see Maj. Op. 906, the bit in the request packet provides a signal by selecting an access-time register which indicates when the DRAM is to begin an operation. It is the bit that selects an *909access-time register, and therefore indicates “when the memory device is to begin sampling write data.” '109 patent col. 42 11. 62-63. That is, the request packet includes a bit, a “value,” that tells the memory device to wait x amount of time after receiving the command to write data. The fact that the x is stored within the memory device does not change what the value represents. Without the value in the request packet the memory device would not know when to begin sampling; it is that bit which instructs the memory device when to begin. Farmwald teaches that the request packet controls the timing of writing data either by directly “select[ing] a certain register in the slave DRAM memory device which stores the (delay value) timing information” or indirectly by “indicating] pre-selected (delay value) access times.” See J.A. 8 (citing Farmwald col. 9 1. 46 — col. 10 1. 5). Contrary to the majority’s characterization, no subsequent steps or signals are necessary. See Maj. Op. 906-07. Once the specified amount of time elapses, sampling begins. Farmwald col. 27 11. 19-20 (Claim 25 specifies “outputting the data to the memory device after a delay time transpires.”).
The second basis for the Board’s reasoning is that the claim language does not require sequential reading of the first two steps. The first two steps state:
Providing control information to the memory device, wherein the control information includes a first code which specifies that a write operation be initiated in the memory device;
Providing a signal to the memory device, wherein the signal indicates when the memory device is to begin sampling write data, wherein the write data is stored in the memory core during the write operation....
'109 patent col. 41 1. 64-col. 42 1. 64. The “write operation” instruction does not need to come before the claimed “signal” since that signal only indicates when the “write operation” is to happen. There is no reason the write instruction and the signal indicating the timing of the write operation could not come at the same time — like they do in Farmwald’s request packet.
The majority states that “a plain reading of claim 1 evinces a specific order,” because “[i]t would make no sense for the second step to be performed first — telling the memory device to begin sampling write data — before the memory device was even instructed to perform a ‘write’ operation.” Maj. Op. 907. However, it is not clear, as a matter of “logic or grammar,” that all of the steps in claim 1 must be performed in the order written. See Altiris, Inc. v. Symantec Corp., 318 F.3d 1363, 1369-71 (Fed.Cir.2003). “[Although a method claim necessarily recites the steps of the method in a particular order, as a general rule the claim is not limited to performance of the steps in the order recited, unless the claim explicitly or implicitly requires a specific order.” Baldwin Graphic Sys., Inc. v. Siebert, Inc., 512 F.3d 1338, 1345 (Fed.Cir.2008). The third step, “providing a first bit of the write data to the memory device during an even phase of a clock signal,” and the fourth step, “providing a second bit of the write data to the memory device diming an odd phase of the clock signal,” have parallel structure and sequential language. '109 patent col. 42 11. 66-67; col. 43 11. 1-2. But the same cannot be said for the first two steps of claim 1. The first step describes a “first code” but the claim fails to identify a “second code.” There is no sequential language in the first two steps to indicate that they must occur in the order written. The broadest reasonable interpretation of signal indicates when the operation is to happen, but does not necessarily require immediate initiation. Therefore, in instances like the '109 patent’s delay value embodiment, wherein the signal instructs the *910DRAM to wait some number of clock cycles before initiating action, it does not matter whether the DRAM has been instructed to do a write operation until the specified period of time elapses.
The role of this court is not to determine if the record could support a different outcome, but to determine if the Board’s findings are supported by substantial evidence. In re Jolley, 308 F.3d 1317, 1320 (Fed.Cir.2002) (If “the evidence in [the] record will support several reasonable but contradictory conclusions,” then this court “will not find the Board’s decision unsupported by substantial evidence simply because the Board chose one conclusion over another plausible alternative.”). Because the Board’s findings on anticipation are supported by substantial evidence, I respectfully dissent.