Court Opinion

ID: 8676946
Source: CourtListenerOpinion
Date Created: 2022-11-25 02:41:38.00481+00
Date Added: 2024-06-11T16:57:19.902740
License: Public Domain

LOURIE, Circuit Judge.
Nazomi Communications, Inc. (“Nazo-mi”) appeals from the decisions of the United States District Court for the Northern District of California construing disputed claim limitations and granting summary judgment of noninfringement of U.S. Patents 7,080,362 (“the '362 patent”) and 7,225,436 (“the '436 patent”) (collectively, “the hardware patents”) and U.S. Patent 6,338,160 (“the '160 patent” or “the software patent”). See Nazomi Comm., Inc. v. Nokia Corp., No. C-10-04686, 2013 WL 2951039 (N.D.Cal. June 14, 2013) (“Claim Construction Order I”)-, id., 2013 WL 3146796 (N.D.Cal. June 18, 2013) (“Summary Judgment Order /”); Nazomi Comm., Inc. v. Samsung Telecomms., Inc., No. C-10-05545, 2013 WL 4067595 (N.D.Cal. Aug. 8, 2013) (“Claim Construction Order II”); id., 2013 WL 4066847 (N.D.Cal. Aug. 8, 2013) (“Summary Judgment Order II ”).
Nazomi owns the hardware patents, which relate to a hardware Java accelerator that expedites the conversion, of stack-based instructions into register-based instructions for processing by a central processing unit. Nazomi also owns the software patent, which relates to a method of running Java programming language that resolves references to a constant pool at runtime. In 2012, Nazomi sued various technology companies that incorporated ARM’s Jazelle Revision 3 design into their processors, alleging infringement of the hardware patents, and various technology companies that produced devices running *1077Google’s Android operating system, alleging infringement of the software patent.
The claims at issue in this appeal are claims 1,15,17, 22, 26, 48, and 66-70 of the '362 patent; claims 1, 5, 12, and 14 of the '436 patent; and claims 11, 15, 18, and 21 of the '160 patent. Claim 1 of the '362 patent is representative of the hardware patents’ claims and reads as follows:
I. A method for processing instructions in a central processing unit (CPU) capable of executing instructions of a plurality of instruction sets, including a stack-based and a register-based instruction set, the method comprising:
maintaining data for register-based instructions from the register-based instruction set and an operand stack for operands associated with stack-based instructions from the stack-based instruction set in a first register file, wherein at least some of the operands are moved between the register file and memory via at least one of an overflow and underflow mechanism; maintaining an indication of a depth of the operand stack; and processing the register-based instructions including generating a first output, and processing the first output in an execution unit using the data from the first register file; and processing the stack-based instructions including generating a second output, and processing the second output in the execution unit using the operands from the first register file; and generating exceptions in respect of selected stack-based instructions.
'362 patent col. 7 11. 36-58 (emphases added). Claim 11 of the '160 patent is representative of the software patent claims and reads as follows:
II. A method of executing an instruction comprising: obtaining from an instruction storage location, an instruction that references an entry in a constant pool, the constant pool entry storing an indication of a reference that may need resolution;
obtaining data from the constant pool entry including data from a resolution data field;
using data from the resolution data field to determine whether to do a resolving step; and thereafter, if the data in the data resolution field indicates that the reference was not resolved, resolving the reference and, thereafter, modifying the data in the constant pool entry including modifying the data in the resolution data field to indicate that the reference is resolved, wherein the data in the instruction storage location is not modified.
'160 patent col. 9 1. 44-col. 10 1. 16 (emphases added).
In November 2012, the district court held hearings to construe disputed claim limitations and to consider the technology companies’ motion for summary judgment of noninfringement. Claim Construction Order I, 2013 WL 2951039, at *1; Summary Judgment Order I, 2013 WL 3146796, at *1; Summary Judgment Order II, 2013 WL 4066847, at *1.
With respect to the hardware patents, the district court construed the claim limitation “instructions” to mean “either stack-based instructions that are to be translated into register-based instructions, or register-based instructions that are input to the CPU pipeline.” Claim Construction Order I, 2013 WL 2951039, at *8. The court reasoned that, among other things, (1) Na-zomi failed to overcome the presumption that courts should construe the same term consistently across related patents, id. at *1078*4-5, noting that we had affirmed a claim construction of “instructions” in a prior case with a similar specification, and (2) “the specification clearly limited the scope of the claimed invention to executing stack-based instructions by translating them into register-based instructions,” id. at *6-7.
In light of that construction, Nazomi stipulated to a lack of literal infringement and only argued for infringement under the doctrine of equivalents. Summary Judgment Order I, 2013 WL 3146796, at *3. The court excluded those arguments, however, because Nazomi failed to comply with the Patent Local Rules by only providing boilerplate language in its infringement contentions. Id. at *4-5. Accordingly, the court granted the technology companies’ motion for summary judgment of noninfringement of the hardware patents.
With respect to the software patent, the court construed the claim limitation “constant pool” (“the constant pool limitation”) to mean “a data structure attached to a single loaded class that encodes the names that can be used by any method in the loaded class.” Claim Construction Order II, 2013 WL 4067595, at *5. The court reasoned that, at the time of the invention, the term “constant pool” was a term of art unique to Java. Id. at *3. Thus, lacking any guidance in the .specification, the court used the definition provided by the Java Virtual Machine Specification. Id. at *4.
The court then construed “an indication of a reference that may need resolution” (“the indication of a reference limitation”) to mean “an identification of a location {e.g., an address) within the constant pool that stores the name, or ‘label,’ of a reference that needs resolution.” Id. at *8. The court reasoned that the plain language of the claim and the specification emphasize that the “indication of a reference” requires an address that “directs the system to a location within the constant pool.” Id. at *7-8. And that address is necessarily distinct, the court stated, from the “resolution data field,” which only shows whether a reference has been resolved by entering a[0] or a[l]. Id. at *7, *9.
In light of that construction, Nazomi stipulated to a lack of literal infringement of the constant pool limitation. Summary Judgment Order II, 2013 WL 4066847, at *4-5. And the court found that Nazomi failed to establish how the accused devices operated in “substantially the same way” under the doctrine of equivalents. Id. at *5. Accordingly, the court granted • the technology companies’ motion for summary judgment of noninfringement based on the constant pool limitation. Id. The court alternatively granted the technology companies’ motion for summary judgment of noninfringement based on the indication of a reference limitation, finding that the accused devices did not identify a location within the constant pool. Id. at *6.
Nazomi timely appealed, and we have jurisdiction pursuant to 28 U.S.C. § 1295(a)(1).
Nazomi made a variety of arguments on appeal, supporting its view that the district court erred in its claim constructions and hence its judgments of non-infringement. We have considered all of Nazomi’s arguments and find them unpersuasive. On the basis of the district court’s reasoning, we therefore find no error in the district court’s claim constructions that (1) “instructions Construed Term: Instructions” means “either stack-based instructions that are to be translated into register-based instructions, or register-based instructions that are input to the *1079CPU pipeline”; * (2) “constant pool Construed Term: Constant pool” means “a data structure attached to a single loaded class that encodes the names that can be used by any method in the loaded class”; and (3) “an indication of a reference that may need resolution Construed Term: An indication of a reference that may need resolution” means “an identification of a location (e.g., an address) within the .constant pool that stores the name, or ‘label,’ of a reference that needs resolution.”
In addition to their defense of the district court’s claim constructions, the technology companies asserted collateral es-toppel with respect to the district court’s construction of “instructions.” Specifically, they suggested that this court’s construction of “instructions” in an earlier litigation involving U.S. Patent 6,332,215— of which the hardware patents are continuations and share similar disclosures — controls, and that Nazomi cannot now reliti-gate that issue. Appellees’ Br. 37-39. Nazomi responded that the earlier litigation focused on a narrower issue with respect to the meaning of “instructions,” and thus collateral estoppel should not apply here. Appellant’s Br. 58-61. We do not need to decide that question here. Whether or not collateral estoppel applies, the prior decision at the very least adds force to support the district court’s construction of “instructions” in the instant ease, which we have affirmed.
We also conclude that the district court did not abuse its discretion by excluding Nazomi’s doctrine of equivalents arguments under the Patent Local Rules, and thus correctly granted summary judgment of noninfringement of the hardware patents, and that the district court correctly granted summary judgment of nonin-fringement of the software patent. We therefore affirm the judgments of the district court.
AFFIRMED

 The district court also construed “processing the stack-based instructions including generating a second output,” "execution unit,” and "hardware accelerator to process stack based instructions,” which are at issue in this appeal. Claim Construction Order I, 2013 WL 2951039, at *9, *11, *13. Nazomi has argued that those constructions turn only on the same "translation of stack-based instructions to register-based instructions” limitation that the court required for "instructions.” Appellant’s Br. 48, 62-63. Because we affirm the court's construction of "instructions,” and thus its stack-to-register translation limitation, we necessarily affirm the court’s remaining constructions for those additional terms.