Patent Application: US-66948700-A

Abstract:
a charge - based frequency measurement bist for clock circuits and oscillator circuits is described that requires no outside test stimulus and produces a digital test output . the cf - bist technique performs structural and defect - oriented testing and uses existing blocks to save die area . the technique adds a multiplexer to the non - sensitive digital path . the system uses the existing vco as the measuring device and divide - by - n as a frequency counter to reduce the area overhead . the described technique produces an efficient pass / fail evaluation , low - cost and practical implementation of on - chip bist structure .

Description:
the fundamental theory of the bist technique for a pll is shown in fig1 . a constant current source is injected to the cut ( circuit under test ) as an input stimulus . the resulting signature output is measured and evaluated by the output evaluation block . the cut in this case consists of analog circuitry with a relatively low input impedance . the output of the cut is usually a voltage value which is the multiply of the input current injected and the impedance of the cut circuit . thus , any change in the impedance will affect the signature output of the cut , where cut impedance can be altered by any type of faults including physical defects . this testing scheme can be adapted to a pll for testing the entire pll , by designating the loop - filter of the pll as the cut block . thus , the relationship between the constant current input i to the corresponding voltage output v can be written as in equation ( 1 ) for a simple rc loop - filter , where t denotes the duration of time the input current is applied . v = ri + 1 c · ∫ t ⁢ i ⁢ ⁢ ⅆ t ( 1 ) thus , a fault can be screened by comparing the magnitude of the output voltage v against a mask ( base value ). for a more detailed description of this technique , a pll with an open loop configuration as in fig2 is described . for a constant current source used in this test , the existing charge - pump in the pll is preferably utilized which generates a current source by digitally controlling the input of the charge - pump circuit . other current sources may be used , but then the charge pump must also be tested . by using the existing charge - pump , there are three major advantages : it eliminates the need for on - chip precision current source which will occupy a relatively large die area . the charge - pump itself is tested for possible faults . this saves the overall test time by performing a single test for multiple blocks . the sensitive loop - filter input node is not altered since the current source which is the output of the charge - pump is already connected to the loop - filter . this ensures the sensitive analog node is not loaded which is a common problem in previous pll bist techniques [ 6 ],[ 10 ],[ 13 ]. the existing vco and the divide - by - n block is used as an example for the output voltage measuring device to measure the output voltage signature of the loop - filter . any counter may be used as the voltage measuring device . the vco generates an output frequency according to the loop - filter &# 39 ; s output voltage , the vco output is then fed to the divide - by - n block which acts as a frequency counter . thus , by retrieving the binary data store in the counter , the output frequency of the vco which represents the output signature of the loop - filter is read digitally . some advantages of using the existing vco and divide - by - n as a measuring device are : it eliminates the need for an on - chip precision voltage measuring device , which can take up considerable die area . as the output voltage of the loop - filter is being measured , the vco and divide - by - n blocks are also tested for possible faults . the vco is tested without any change to its sensitive analog feedback loop . the test output is in a digital form , thus enabling the test controller and evaluation blocks to be constructed with only the digital parts . this method can test all the analog blocks in a pll for possible faults and can test for the location of the fault in the circuit . the location of faults in the circuit can be determined by variation in output values , as known to one of ordinary skill in the art . one major advantage of the technique described herein is that it uses mostly existing blocks for testing and measurement , thus minimizing the area overhead . furthermore , the test output is transformed into a digital value which can be evaluated with relatively reliable digital circuitry . an example of one embodiment of the invention is the cf - bist block diagram shown in fig3 , where a controller / grabber block and a multiplexer are added to the existing pll . this example is described in further detail below . the multiplexer ( mux ) is added to the output of existing phase - detector block and provides input controls for stimulating the loop - filter . one embodiment of the mux is shown in fig4 . in normal pll operation , the mux is set to bypass the phase - detector output signals . in test mode , the mux provides charge - pump control signals generated by the controller / grabber block to the charge - pump input . the vco then oscillates according to the output voltage of the loop - filter . the oscillation frequency reflects the faults in the loop - filter , charge - pump , and the vco . the deviation of the oscillation frequency from its nominal value ( base ) indicates a faulty circuit in the loop . this test method does not require any analog test signals . furthermore , the oscillation frequency is measured on - chip using the existing divide - by - n block which acts as a counter . thus , the final output is a pure digital value which increases the precision of the test . also , the described method does not alter any exiting analog circuitry , it only needs a slight modification in the digital part which can be added during the pll design . when the bist system is active , the controller / grabber block controls the multiplexer in the phase - detector to provide proper stimulus for the loop - filter . it consists of two sub - blocks which are the state - machine and the grabber , and the entire block consists of digital components , thus , it is highly reliable compared to analog counterparts . the divide - by - n , which is used in a pll to shift the output frequency to the input dynamic range , is utilized as a frequency counter in the described bist system . when the bist system is in the self - test mode , the divide - by - n counts the output frequency of the vco and the resulting digital value is grabbed and stored by the controller / grabber block . the digital frequency data stored in the controller / grabber block can be scanned out using the ieee 1149 . 1 boundary scan path or any scan path available . in order to measure the output voltage of the loop - filter , normally a voltage sample - and - hold circuit is needed to hold the ramping voltage value at a certain time . unfortunately , sample - and - hold circuits are expensive to include in a chip in terms of die area . described here is a simple average - count method . the simple average - count method used to obtain the voltage value does not need any additional circuit components , it performs a sample - and - hold function using the existing vco and divide - by - n block . fig5 is shown to better understand the method . fig5 shows the vco output frequency transition during the test . t a is the time when the output voltage value should be sampled - and - held ; t 0 is the time the divide - by - n which acts as a counter starts to count . counting starts by simply enabling the counter &# 39 ; s flip - flops which were cleared in the initial stage . t 1 represents the time when the counter halts counting and keeps its binary values . f ( v 0 ) and f ( v 1 ) are vco output frequencies due to input voltages v 0 and v 1 , respectively , which occurred at time t 0 and t 1 , respectively . where t is the time period when the counter is active , and f is the frequency of the input during t . by using the relations shown in equations ( 2 ) and ( 3 ), we can write f = f ⁡ ( v 1 ) + f ⁡ ( v 0 ) 2 = f ⁡ ( v a ) f ⁡ ( v a ) = c t 1 - t 0 ( 5 ) equation ( 5 ) implies that if the counter counts t 0 to t 1 , it will have the average frequency value f ( v a ) during the count . therefore , the voltage value v a , which was the target voltage to sample - and - hold , is measured and stored in the counter after t period . the above explanation shows that the method described herein does not need a sample - and - hold block to obtain a voltage value v a from the loop - filter output . instead , it only needs a proper enable signal for the counter which is the divide - by - n block . this enable signal is easily generated by the state - machine in the controller / grabber block . to determine the test clock frequency and the bit - width of the counter , three input specifications are needed for calculation : f max maximum vco output frequency f min minimum vco output frequency a accuracy of the measurement in (%). from f max and the test duration t , the maximum counter output c max is given by c max = t 1 / ( f max ) ( 6 ) where t is the amount of time the counter is enabled for a measurement . if the resolution of the measurement a in equation ( 6 ) is included , it gives the following relationship : c max - 1 = t 1 f max - ( f max - f min ) · a ( 7 ) where ( f max − f min ) a represents the minimum value of frequency that can be measured with the counter . combining equation ( 6 ) and ( 7 ) gives c max = f max ( f max - f min ) · a ( 8 ) to count up to c max , the counter must have at least c b bits , where : the test duration t can be calculated using the following equation : f max = 900 mhz f min = 400 mhz a = 0 . 01 ( 1 % resolution in measurement ), then from equation ( 8 ), c max is 180 which yields the counter bit - width of 8 bits . further through the procedure yields f test to be 5 mhz which is the test clock speed . hence , 8 bit wide counter and 5 mhz test clock are the only information needed to construct the cf - bist structure in this example . if the bit with is not sufficient , the test can still be performed , but is not as accurate . if the clock frequency is not correct , the count values will be drastically different from the expected values . this is easily detectable . adequate bit width for the desired function and for testing can be designed in the circuit . in order to better understand the concept of cf - bist technique , a simplified schematic diagram of the charge - pump and the loop - filter ( fig6 ) is used . the charge - pump injects a constant current for a certain period of time to the loop - filter , creating a output voltage variation in the loop - filter . this is then converted in to a frequency value by the vco . finally , the divide - by - n which acts as a counter converts the frequency value into a digital data for a simple test output evaluation . the detailed test procedure is as follows : 1 . dc voltage generation : a dc voltage is generated by closing both the up and down current transistors to form a voltage divider . the generated dc voltage should be around mid - point voltage . since this mid - point value is used as a reference value instead of an absolute value , it is not necessary to be at the exact mid - range . 2 . voltage measurement : the generated dc voltage is converted to frequency by the vco and counted by the divide - by - n block . the dc voltage value which is now in a digital form , is grabbed and stored in the controller / grabber block which is the reference - count ( f 1 ) in fig7 . 3 . stimulus injection : in order to discharge the loop - filter , the up - current switch is opened while the down - current switch is kept closed . this down - current acts as the input stimulus for the loop - filter test . 4 . voltage measurement : at the end of the discharge period , the output voltage of the loop - filter is measured with the vco and the counter . this value is stored in the controller / grabber block as down - count ( f 2 ) which can be scanned out using the scan path at the final test step . 5 . stimulus injection : in order to charge the loop - filter , the down - current switch is opened while the up - current switch is kept closed . this up - current acts as the input stimulus for the loop - filter test . 6 . voltage measurement : at the end of the charge period , the output voltage of the loop - filter is measured with the vco and the counter , and this digital value is grabbed and stored in the controller / grabber block as up - count ( f 3 ) which will be used in the next step . in fig7 , a flow chart is drawn to help understand the overall test procedure described in the example . the control signals et , tup and tdn controls the charge - pump which are generated by a state - machine in the controller / grabber block . et , which is the test enable signal , should remain high during the test period . it sets the mux at the end of the phase - detector block in the test mode . tup controls the up - current switch in the charge - pump when et is high . it is active - low , since the p - type mos transistor is used for up - current switch . tdn is the control signal for the down - current switch which is the n - type transistor . 7 . scan out : using any existing scan path as in fig8 , the three stored digital values ( f 1 , f 2 , f 3 ) in the controller / grabber block are scanned out for test evaluations . then , the | f 1 - f 2 | and | f 3 - f 2 | are evaluated for possible faults in the pll blocks according to the flowchart in fig7 . the base values for c 1 , c 2 and m 1 are determined by logic or behavioral simulations , as is well known in the art and performed without undue experimentation . one example of a useful logic simulator is verilog . one example of a useful behavioral simulator is matlab . other simulators may be used , as known in the art . 8 . self checking : an alternative way of evaluation , if a scan path is not available in the chip or the bist has to incorporate the self - checking ability , is adding a subtracter and a comparator to form a self - checker in the controller / grabber block . this is shown in fig9 , where the subtracted values are compared with the preset values ( base values ) to make a go / no - go decision . the go / no - go decision is determined by a significant difference between the subtracted value and the preset value . fig1 shows the overall timing of the controller / grabber block , the signals shown are related to the multiplexer and the controller / grabber block . the only input signals are test - clock and start - test signals . the enable - test and measure -& amp ;- store - enable signal are internal signals generated by the controller . the output signals are up - test and down - test which controls the up - current switch and the down - current switch of the charge - pump , respectively . in fig1 , tests for faulty and fault - free cases are shown using the pll provided by the national semiconductor corp . which has the operating range around 900 mhz with a single 3 . 3 volt power supply . it shows the output voltage of the loop - filter as well as the actual measured frequency data at each measurement points . these binary data are evaluated using the above test evaluation process ( step 4 ). table 1 shows the calculated differences between f 1 , f 2 and f 3 which are used to make a final decision . for the faulty cases , the difference between f 1 and f 2 were 53 and 125 , where in the fault - free case showed 87 . also , the difference between f 2 and f 3 measured 69 and 141 for the faulty cases , 103 for the fault - free case . the values of | f 1 - f 2 | and | f 3 - f 2 | for faulty case show more than 33 % deviations from the fault - free case value . therefore , table 1 and the graph shown in fig1 clearly demonstrates the fault detectability of the described bist technique . the effects of the process variations for the differences of the measured digital counts in two tests , which are charge test and discharge test have been analyzed . fig1 shows monte - carlo results for the charge test , both fault - free and faulty cases are displayed for comparison . in this case , we chose drain - open fault in vco , since its test results showed the least separation from the fault - free test results . thus , it is the worst case for the monte - carlo analysis . as it can be observed in both fig1 and 13 , the output of the faulty case varies well within the tolerance window , which means that the fault stays detectable even with the presence of process variations . a structural fault model of national &# 39 ; s pll ( national semiconductor corporation , santa clara , calif .) which includes complete set of catastrophic ( hard ) faults has been built to demonstrate the effectiveness of cf - bist technique in detecting structural faults . the hard faults include : gate - to - source short ( gss ) gate - to - drain short ( gds ) drain - to - source short ( dss ) resistor - short ( rs ) capacitance - short ( cs ) gate - open ( go ) drain - open ( do ) source - open ( so ) resistor - open ( ro ) a transistor short is modeled by a small resistance ( 1ω ) between the shorted terminals . a transistor open is modeled as a large resistance ( 10 mω ) in series with the opened terminals . the small resistance value ( 1ω ) and the large resistance value ( 10 mω ) are widely used values in structural fault simulations [ 11 ],[ 14 ],[ 15 ]. the gate - open is modeled by disconnecting the gate from other nodes and placing a large resistance ( 10 mω ) between gate and the other two terminals . in the previous works [ 11 ],[ 14 ], the gate - open is modeled using only one large resistance which is placed between the gate and the source . this causes the faulty transistor to be always in the off - state which is not a realistic model for a gate - open fault . the total number of structural faults ( defects ) was 395 . these served as a practical fault model of the pll for evaluating the cf - bist described here . to demonstrate the efficiency of the cf - bist technique , all 395 faults were used and simulations were carried out to evaluate the fault coverage for each configuration . table 2 presents the fault coverage results . as it can be observed in table 2 , the cf - bist structure described here clearly shows the effectiveness of the fault test . therefore , it provides a low - cost and highly - effective bist solution for detecting structural faults . although the description above contains many specificities , these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently - preferred embodiments of this invention . for example , the technology described herein can be used to implement structural fault - based testing , performance testing , jitter measurements and parametric phase - locked loop measurements for computer and telecommunications systems , as well as other applications known in the art at any frequency . the disclosed invention can be used to test any clock circuit or oscillator circuit in systems such as computer systems or telecommunications systems . any modifications necessary to use the technique in systems other than those described specifically herein are well known to one of ordinary skill in the art and are performed without undue experimentation using the teachings described herein . all references cited herein are hereby incorporated by reference to the extent not inconsistent with the disclosure herewith . m . abramovici , m . a . breuer , a . d . friedman , “ digital systems testing and testable design ,” computer science press , pp . 395 - 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