Patent Application: US-53321505-A

Abstract:
a nonvolatile memory cell , memory cell arrangement , and method for production of a nonvolatile memory cell is disclosed . the nonvolatile memory cell includes a vertical field - effect transistor . the fet contains a nanoelement arranged as a channel region and an electrically insulating layer . the electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate - insulating layer . the electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer .

Description:
the following text , referring to fig1 a to fig1 c , describes a method for fabricating a memory cell in accordance with a first exemplary embodiment of the invention . to obtain the layer sequence 100 shown in fig1 a , a material which is catalytically active for the growth of carbon nanotubes ( e . g . nickel , cobalt or iron ) is deposited on a glass substrate 101 ( a silicon substrate etc . may also be used as an alternative ) and patterned in such a manner that a first source / drain region 102 is formed on the glass substrate 101 as a result . furthermore , a first electrically insulating layer 102 is formed on the layer sequence obtained in this way by the deposition of silicon nitride material . alternatively , this layer may also be produced from another dielectric material , for example silicon oxide or aluminum oxide . in a further method step , aluminum material is deposited on the layer sequence obtained and patterned using a lithography process and an etching process , in such a manner that a gate region 104 is formed as a result . alternatively , it is also possible for polysilicon material , tantalum nitride material , etc . to be used instead of aluminum material . to obtain the layer sequence 110 shown in fig1 b , a second electrically insulating layer 111 is deposited on the layer sequence 100 and planarized using a cmp ( chemical mechanical polishing ) process , with the gate region 104 as stop layer . furthermore , using a lithography process and an etching process , via holes 112 are introduced into the gate region 104 and into the first electrically insulating layer 103 . this obviously forms a porous mask , with the pores or via holes 112 being used as templates for the growth of carbon nanotubes in a subsequent method step . to obtain the nonvolatile memory cell 120 in accordance with a first exemplary embodiment of the invention shown in fig1 c , first of all a gate - insulating charge storage layer 121 is formed by thermal oxidation on uncovered surface regions of the gate region 104 formed from aluminum material . therefore , the gate - insulating charge storage layer 121 is formed from aluminum oxide material . alternatively , it is possible to carry out conformal deposition of a dielectric material , followed by an anisotropic etchback in order to form the gate - insulating charge storage layer 121 . the gate - insulating charge storage layer 121 simultaneously serves as gate - insulating region of the field - effect transistor and as charge storage layer of the memory cell 120 , into which charge storage layer 120 electrically charge carriers can be selectively introduced and / or from which charge storage layer 120 electrical charge carriers can be selectively removed . furthermore , the gate - insulating charge storage layer 121 is designed in such a manner that the electrical conductivity of a carbon nanotube that is subsequently to be formed can be influenced in a characteristic way by means of electrical charge carriers introduced in the gate - insulating charge storage layer 121 . in a further method step , semiconducting carbon nanotubes 122 are grown in the via holes 112 using a cvd ( chemical vapor deposition ) process , with the nickel material of the first source / drain region 102 catalytically assisting the growth of the carbon nanotubes 122 . in an optional further method step , additionally electrically insulating material can be deposited in order to fill any cavities between the gate - insulating charge storage layer 121 and the carbon nanotubes 122 formed in a respective via hole 112 . the layer sequence obtained in this way is planarized using a cmp process . furthermore , the deposited material is reactively etched back in order , in accordance with fig1 c , to uncover upper end portions of the carbon nanotubes 122 for the purpose of contact - connection to a source / drain region that is subsequently to be applied . thereafter , nickel material is deposited as second source / drain region 123 , in such a manner that the uncovered upper portions of the carbon nanotubes 122 are contact - connected to the material of the second source / drain region 123 . this produces the nonvolatile memory cell 120 shown in fig1 c . this memory cell includes two carbon nanotubes 121 . of course , it is possible for a memory cell according to the invention to be formed using just one carbon nanotube or more than two carbon nanotubes . electrical charge carriers can be selectively introduced into the gate - insulating charge storage layer 121 by fowler - nordheim tunneling or by tunneling of hot electrons ( or hot holes ). when charge carriers of this type have been permanently introduced into the gate - insulating charge storage layer 121 made from aluminum oxide material , the electrical properties ( e . g . threshold voltage ) of the associated transistor have been changed in a characteristic way , so that when a predeterminable electric voltage is applied between the two source / drain regions 102 , 123 , the level of electric current which flows through the channel region 122 is dependent in a characteristic way on the number and sign of the charge carriers introduced in the gate - insulating charge storage layer 121 . the nonvolatile memory cell 120 can therefore be operated as a permanent memory cell with a long hold time , in which information can be stored in the charge storage layer 121 with a short programming time by the application of suitable electrical potentials to the source / drain regions 102 , 123 and to the gate region 104 . furthermore , information can be removed or read out by application of suitable electrical potentials to the source / drain regions 102 , 123 and to the gate region 104 with a sufficiently fast erase or read time . the following text , referring to fig2 a to fig2 f describes a method for fabricating a memory cell in accordance with a second exemplary embodiment of the invention . to obtain the layer sequence 200 shown in fig2 a , nickel material which has a catalytic activity for the growth of carbon nanotubes is deposited as first source / drain region 102 on a glass substrate 100 . to obtain the layer sequence 210 shown in fig2 b , a silicon oxide layer 211 is deposited on the surface of the layer sequence 200 and patterned with a predeterminable porous mask using a lithography process and an etching process , in such a manner that via holes 122 are introduced into the silicon oxide layer 211 . as a result , surface regions of the nickel material of the first source / drain region 102 , which is catalytically active for the growth of carbon nanotubes , are uncovered . furthermore , the via holes 112 serve as a mechanical guide for the subsequent growth of carbon nanotubes . to obtain the layer sequence 220 shown in fig2 c , semiconducting carbon nanotubes 122 are grown vertically in the via holes 122 using a cvd process ; on account of the catalytic action of the nickel material of the first source / drain region 102 for the growth of carbon nanotubes , the latter start to grow from the source / drain region 102 . to obtain the layer sequence 230 shown in fig2 d , the dielectric material of the silicon oxide layer 211 is removed using a selective etching process . furthermore , a gate - insulating charge storage layer 231 having a storage function for electrical charge carriers is deposited on the carbon nanotubes 122 and the first source / drain region 102 using a conformal deposition process ( e . g . using an ald ( atomic layer deposition ) process )). according to the exemplary embodiment described , the gate - insulating charge storage layer 231 is realized as a silicon oxide / silicon nitride / silicon oxide layer sequence ( ono layer sequence ). using the ald process , it is possible to set the thickness of a layer deposited to an accuracy of even one atomic layer , i . e . to an accuracy of a few angstroms , and consequently a homogeneous thickness of the ono layer sequence over the carbon nanotubes 122 is ensured . furthermore , an electrically conductive layer 232 of tantalum nitride ( or alternatively of doped polysilicon material ) is deposited on the layer sequence obtained in this way and then processed in such a manner that it serves as gate region of the field - effect transistors of the memory cell . to obtain the layer sequence 240 shown in fig2 e , a silicon nitride layer 241 is deposited on the layer sequence 230 and planarized using a cmp process , in such a manner that an upper end portion , as seen in fig2 e , of the carbon nanotubes 122 is uncovered . to obtain the nonvolatile memory cell 250 shown in fig2 f , a surface region of the electrically conductive layer 232 serving as gate region is etched back using a selective etching process . furthermore , dielectric material is deposited on the surface of the layer sequence obtained in this way and planarized using a cmp process . electrically insulating decoupling elements 251 are formed as a result . dielectric material can optionally be etched back . then , nickel material is deposited on the surface of the layer sequence obtained in this way and patterned , with the result that a second source / drain region 123 is formed at the surface of the nonvolatile memory cell 250 . the second source / drain region 123 is now coupled to upper end portions , as seen in fig2 f , of the carbon nanotubes 122 . clearly , in the exemplary embodiment described with reference to fig2 a to fig2 f , the pore structure is removed following growth of the carbon nanotubes 121 , and the further components of the memory cell are deposited on the uncovered carbon nanotubes 122 . this has the advantage that in principle any desired materials can be used for the gate - insulating charge storage layer 231 . the following text , referring to fig3 a , fig3 b , describes a method for fabricating a nonvolatile memory cell in accordance with a third exemplary embodiment of the invention . to obtain the layer sequence 300 shown in fig3 a , a first source / drain region 102 is deposited on a glass substrate 101 . in accordance with the exemplary embodiment described , this first source / drain region 102 is produced from a material which is electrically conductive and ( unlike in the first two exemplary embodiments ) does not have a strongly catalytic action for the growth of carbon nanotubes ( for example polysilicon material ). a thin nickel layer is applied to the first source / drain region 102 and patterned using a lithography process and an etching process , in such a manner that catalyst material spots 301 formed from nickel material , which has a catalytic action for the growth of carbon nanotubes , are formed on the surface of the layer sequence 300 . the catalyst material spots 301 have a dimension of approximately 50 nm and evidently serve as nuclei for the growth of carbon nanotubes . in other words , the catalyst material spots 301 define the locations where carbon nanotubes 122 will subsequently be grown . to obtain the layer sequence 310 shown in fig3 b , carbon nanotubes 122 are grown on the catalyst material spots 301 using a cvd process . on account of the strong catalytic action of the catalyst material spots 301 , carbon nanotubes 122 grow substantially vertically on the first source / drain region 102 even without the provision of pores . proceeding from the layer sequence 310 , the processing can be continued in the same way as proceeding from fig2 c following the removal of the silicon oxide layer 211 . the following text , referring to fig4 , describes a memory cell array 400 with four memory cells 401 to 404 in accordance with a preferred exemplary embodiment of the invention . first source / drain regions 405 of the memory cells 401 to 404 are formed on a glass substrate 101 , electrically insulated from one another by means of a first electrically insulating auxiliary layer 406 . a vertical carbon nanotube 408 is formed between each first source / drain region 405 and second source / drain region 412 on the surface of the memory cell array 400 , and the carbon nanotube 408 is coupled to in each case two source / drain regions 405 , 412 . each of the carbon nanotubes 408 is surrounded by an aluminum oxide layer as gate - insulating charge storage layer 410 . a gate region 409 that is common to the four memory cells 401 to 404 shown in fig4 is formed around the gate - insulating charge storage layer 410 . the gate region 409 is electrically decoupled from the source / drain regions 405 and 412 by means of second and third electrically insulating layers 407 and 411 , respectively . each of the memory cells 401 to 404 can be driven individually by means of the separate source / drain regions 405 , 412 of each memory cell 401 to 404 . furthermore , the electrical conductivity of the channel region 408 of each memory cell 401 to 404 can be controlled by applying a corresponding electrical voltage to the gate region 409 . an information item of one bit can be programmed into , erased from or read of each of the memory cells 401 to 404 , which information item is coded in the quantity and charge carrier type of electrical charge carriers introduced into a respective gate - insulating charge storage layer 410 . corresponding electrical potentials can be applied to the corresponding terminals 405 , 410 , 412 of a respective memory cell 401 to 404 for programming , erasing or reading , in the same way as in a conventional nrom memory . the memory cell array 400 constitutes a layer sequence made up of a multiplicity of substantially planar layers which are arranged above one another and through which the nanoelements 408 extend vertically . the nanoelements 408 are electrically contact - connected on both sides by means of first and second wiring planes 405 and 412 . the modular circuit architecture shown in fig4 allows complex circuits to be constructed with little outlay . harris , p . j . f . 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