Patent Application: US-201314412709-A

Abstract:
we have demonstrated controlled growth of epitaxial h - bn on a metal substrate using atomic layer deposition . this permits the fabrication of devices such as vertical graphene transistors , where the electron tunneling barrier , and resulting characteristics such as on - off rate may be altered by varying the number of epitaxial layers of h - bn . few layer graphene is grown on the h - bn opposite the metal substrate , with leads to provide a vertical graphene transistor that is intergratable with si cmos technology of today , and can be prepared in a scalable , low temperature process of high repeatability and reliability .

Description:
the data in table i demonstrates the significant impact of substrate / graphene interactions on graphene properties , including strong interfacial charge transfer , and band gap formation . charge transfer may strongly impact carrier mobility in graphene [ 7 ], while graphene band gap formation at zero applied voltage may have both positive ( increased on / off ratio ) and negative ( decreased carrier mobility ) implications for graphene - based fet - like devices . additionally , graphene growth on magnetic oxides has substantial implications for induced graphene magnetic behavior [ 8 ]. the data in table i demonstrates that graphene / substrate interactions can profoundly affect graphene properties . graphene was grown by cvd on a monolayer of h - bn ( 0001 ) formed by atomic layer deposition ( ald ) on ru ( 0001 ) [ 1 ]. scanning tunneling spectroscopy ( sts ) and low energy electron diffraction ( leed ) data showed significant orbital hybridization at the bn / ru and graphene / bn interfaces [ 1 ] ( fig2 ). inverse photoemission and a ˜ 350 cm - 1 redshift in the raman 2d feature [ 3 ] indicate significant substrate → graphene charge transfer that fills the graphene π * band . such band - filling may have important implications for graphene electron and hole mobilities [ 7 ]. in contrast to graphene / monolayer h - bn ( 0001 )/ r ( 0001 ), the raman spectra for graphene grown on h - bn nanoflakes by flame pyrolysis indicate negligible charge transfer . these results strongly suggest that increasing the thickness of the bn layer will allow systematic “ tuning ” of charge transfer , as well as substrate / graphene tunneling or leakage interactions . unfortunately , such multilayers are difficult to obtain by the conventional route of borazine thermal cvd , as the formation of the first complete layer typically yields a surface inert to further reaction [ 9 , 10 ]. in contrast , h - bn polycrystalline films have been grown using ald , employing cycles of bcl3 and nh3 [ 11 ]. we have used this process to obtain epitaxial multilayer films on ru ( 0001 ). stm and leed data are shown ( fig3 ) for a trilayer h - bn ( 0001 ) film formed by 6 bcl3 / nh3 cycles at 550 k , followed by annealing at 1000 k to induce long - range order . the data in fig3 demonstrates the capability to grow epitaxial h - bn ( 0001 ) substrates by ald . the data in fig3 also demonstrates the potential for multilayer epitaxial growth of h - bn ( 0001 ) layers on suitable substrates with atomic precision , thus permitting the fine - tuning of graphene / substrate interactions . although density functional theory calculations have suggested [ 12 ] the formation of a small (˜ 0 . 05 ev ) band gap for graphene on bn , none was observed at room temperature [ 1 , 2 ]. in contrast a band gap of ˜ 0 . 5 − 1 ev has been observed for single [ 13 ] and few - layer graphene films [ 2 ] grown on mgo ( 111 ). band gaps of this magnitude are suitable for fet applications [ 14 , 15 ]. importantly , these graphene films display c3v symmetry , while graphene films grown on other dielectric substrates ( table i ), and on ru ( 0001 ) display leed with six - fold symmetry [ 3 ]. the relationship between c3v leed symmetry and substrate - induced graphene band gap formation is shown in fig4 . in the isolated graphene lattice , the a and b sites are crystallographically distinct but chemically equivalent [ 17 ]. this leads to homo / lumo degeneracy , c6v leed symmetry ( fig4 a , b ), and zero band gap at the dirac point ( fig4 c ). however , suitable graphene / substrate interactions ( fig4 d ) lift a site / b site chemical equivalence , yielding c3v leed symmetry ( fig4 e ) and a band gap at the dirac point ( fig4 f ). a puzzling aspect of graphene on mgo is the persistence of c3v leed and a sizeable band gap in both single and few layer films [ 2 , 3 , 14 ]. this strongly suggests a commensurate interface lifting a site / b site chemical equivalence , as in fig5 d . however , the o — o nearest neighbor distance at the bulk - terminated mgo ( 111 ) surface is & gt ; 2 . 8 å , compared to the graphene lattice constant of ˜ 2 . 5 å . in the absence of surface reconstruction , the oxide / graphene interface is incommensurate , and graphene a and b sites should see a similar distribution of substrate environments , leading to a site / b site average equivalence , c6v leed symmetry , and zero band gap . the experimental results [ 2 , 3 , 13 ] therefore strongly suggest a commensurate graphene / mgo ( 111 ) interface , and therefore mgo ( 111 ) surface reconstruction [ 17 ]. the mgo ( 111 ) surface is prone to reconstruction , as the ( 111 ) surface is either entirely o anion or mg cation in nature , yielding an unstable madelung potential , and reconstruction during metallization [ 18 , 19 ]. experimental results , including leed [ 3 ], and core level photoemission [ 17 ] are at least consistent with such a reconstruction . in contrast to mgo ( 111 ), the growth of graphene on co3o4 ( 111 ) yields an incommensurate grapheme / oxide lattice , and c6v leed symmetry , consistent with fig5 d , e . no experimental evidence of band gap formation has been obtained , although transport measurements are in progress . the apparent lack of a band gap for graphene / co3o4 ( 111 ) corresponds to the more stable spinel structure for that oxide , especially due to cation / anion relaxations at the surface that enhance this stability [ 20 ]. in summary , the model shown schematically in fig4 predicts the absence of a band gap for graphene / co3o4 ( 111 ), consistent with existing experimental data . however , this model also suggests that band gap formation might be observed for graphene / nio ( 111 ), as well as for other oxides with the rock salt structure . theoretical work [ 8 ] suggests that graphene in proximity to a ferromagnetic oxide would exhibit substrate - induced ferromagnetism . further , such an effect appears to be relatively insensitive to graphene / oxide orbital hybridization . recent room temperature reflectivity / magneto - optic kerr effect ( moke ) measurements have verified this effect for 3 monolayers ( ml ) graphene / co3o4 ( 111 )/ co ( 0001 ) ( fig5 ). the sample consists of ˜ 3 ml graphene / 3 ml oxide /˜ 30 å co ( 111 ) grown on sapphire ( 0001 ) [ 4 ]. the reflectivity data , sensitive to the graphene π → π * transition ( red laser light ) indicate a distinct hysteresis loop ( fig5 , red trace ), and reversible polarization of the graphene conduction electrons in the plane perpendicular to the sample ( fig5 inset ). moke data for the oxide — at 260 k above its néel temperature ( fig5 , blue )— indicate a corresponding antiferromagnetic hysteresis loop , with cation spins adjacent to the graphene interface polarized perpendicular to the sample , yielding strong ferromagnetic exchange interactions with the graphene conduction electrons . ( the co ( 111 ) surface orders in plane as expected — data not shown .) the above data have significant implications for graphene charge and spin devices . in the absence of a band gap , transistors formed from graphene / sic exhibit on / off ratios of ˜ 30 — hardly practical for most applications [ 21 ]. while a band gap & gt ; 0 . 5 ev is suitable for non - tunneling transistor applications [ 14 , 15 ], the formation of a band gap would alter the dispersion near the dirac point ( fig4 f ), increasing the electron effective mass and lowering mobility . thus , graphene applications involving si cmos fets face a dilemma : finding a suitable band gap / mobility trade - off that leads to both useful on / off ratios ( e . g ., & gt ; 103 ) and mobility substantially greater than the ˜ 103 v / cm2 - sec value for electrons in si . in this respect , the recently proposed vertical graphene base transistor [ 22 ], which does not depend on a graphene band gap for high on / off ratios , would seem to offer considerable opportunity . the data shown in fig5 have significant consequences for graphene spin valves . such devices have been formed from graphene physically transferred to sio2 [ 23 , 24 ] but exhibit magnetoresistance values of only ˜ 10 %, and at cryogenic temperatures . this is due to the necessity of injecting individual spins from the source into the drain via diffusion through the graphene lattice — an extremely inefficient process [ 23 , 25 ]. in contrast , the uniform polarization of graphene conduction electrons would lead to coherent spin transport , as recently suggested for graphene with intercalated ferromagnetic layers , resulting in calculated magnetoresistance values & gt ; 200 % at room temperature [ 26 ]. taking this forward , graphene deposition on magnetic oxides provides an avenue for a new generation of practical , low power spintronic devices based on coherent spin transport . although work on graphene / substrate interface effects will continue along a number of avenues , the results reflected here on the first reported growth of multilayer epitaxial h - bn on a metal substrate provides an immediate route to “ tunable ” band - gap free vertical transistors . deposition using the methods described herein should work for most metals , possibly excepting copper , which is chlorine - loving but does not interact well with the nitrogen or n — h used in ald . suitable substrates include silicon , as well as metals overlying silicon , including beyond ruthenium , cobalt , chrome , nickel and iron . other candidate metals include platinum and palladium . all are consistent with the above - disclosed ald formation of multi - layer h - bn . thus , a useful working device includes a silicon substrate , or possibly a silicon substrate with an overlying metal such as those described above . generally , the h - bn stack will comprise from 3 - 10 epitaxial layers of h - bn , but larger stacks can be envisioned to turn the transistor to particular needs or materials . the ability to epitaxially deposit multiple h - bn layers is of importance beyond the ability to “ tune ” the resulting device , however . single lay h - bn , such as the advances reported by ferguson et al , [ 11 ] is susceptible to orbital hybridization , with a substrate . this is particularly the case with transition metal substrates , such as those employed herein , which exhibit partially filled “ d ” orbitals . this hybridization phenomenon has been shown repeatedly for monolayer born nitride . orbital hybridization leads to undesirable charge transfer between the substrate and the graphene , even if the device incorporating the transistor is “ off ”— there is no bias between the graphene and the bn . by increasing the number of bn layers , employing the method and structures disclosed herein , orbital hybridization and the resulting charge transfer phenomena is regulated . accordingly , in the claimed invention , a metal substrate is selected . this substrate might be silicon prepared according to common methods , or a metal , or a metal on silicon from the correct emitter . in some embodiments , the metal formation on silicon will lead to the formation of a silicide layer , such as a co / cosi 2 / si substrate . on the active surface of the substrate , multiple monolayers of h - bn are formed , to provide a tunneling barrier of height and “ shape ” necessary for the preferred application , as described above using ald . graphene is deposited , by cvd or mbe , on the h - bn stack , followed by the provision of suitable leads . the leads may be of any conductor , but are preferably of , or compatible with , the metal of the substrate . there is general agreement that for logic applications , a graphene fet needs to exhibit on - off rates at room temperature in excess of 10 4 . the devices described here will exhibit on - off rates at room temperature of about 10 5 - 10 6 . while this is not as great as values currently exhibited by some advanced silicon based fets , it is easily high enough to be used in current arrays and incorporated into current devices . the ability to integrate new graphene fets into existing designs , rather than redesigning existing arrays and devices to suit the characteristics of graphene fets , is critical for commercial adoption . these “ vertical transistors ” satisfy that need for on - of rations . in a vertical transistor of the type disclosed and claimed herein , traditional carrier mobilities are not of importance . graphene carrier mobilities are traditionally very high , even at room temperature . lateral mobilities in the devices disclosed , with graphene deposited / grown on a h - bn substrate , rather than transferred , will exceed 2000 cm 2 / v - sec , on up to about 5 , 000 cm 2 / v - sec or more . the resulting devices should exhibit high , and adjustable , on - off rates approaching those exhibited by conventional devices , while providing high , and again , adjustable , lateral mobility . the ability to change the h - bn barrier and thereby balance speed and on - off rates while suppressing charge transfer between the substrate and graphene offers an opportunity to take advantage of the superior electrical properties of graphene without the existence of a band gap in a method consistent with current fabrication and architecture employed in si cmos technology . this will permit the preparation of transistors with predetermined desirable characteristics , including on - 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