Patent Application: US-18241802-A

Abstract:
a secure microprocessor is designed using quad - coded logic which is similar to dual - rail encoded asynchronous logic except that the ‘ 11 ’ state propagates an alarm . the alarm signal obliterates secure data in its path . quad - coded logic provides resilience to power glitches and single - transistor or single - wire failures . the already low data dependency of the power consumption makes power analysis attacks difficult , and they are made even more difficult by inserting random delays in data and control paths , and by a set - random - carry instruction which enables software to make a non - deterministic choice between equivalent instruction sequences . these features are particularly easy to implement well in quad - coded logic .

Description:
we define ‘ quad - coded data ’ as follows . we use two wires to represent every logical bit . this is similar to dual - rail ( sometimes called double - rail ) encoded data [ 15 ] used in speed independent circuit design , except that we use the fourth state to propagate an alarm signal ( see fig1 ). obviously the binary encodings and their assigned meanings may be permuted to suit the requirements of a particular implementation , but for clarity we will illustrate our design using just this encoding . a processor pipeline with a quad - coded data - path may be constructed using well known dual - rail pipelining techniques [ 3 ]. alarm signals can be inserted using an or function of the data and with a sense signal from a sensor ( see fig1 ). one sensor in our invention is based on an instruction counter ; the processor software can check that the expected number of instructions have been executed and alarm if this is riot the case ( as might happen , for example , under destructive probing attack ). in the single circuit implementing the instruction by which this alarm is executed , we depart from the quad - coded logic rules described herein so that an alarm hardware state may be generated from a non - alarm hardware state . other sensors are outside the scope of this patent but may typically be designed to detect out - of - bounds environmental parameters such as over - and under - voltage and low temperature . this or function can be combined with the combinational function indicated to assist the usual gate minimisation process . once an alarm signal has been injected into the data - path it obliterates the data in the pipeline since any dyadic function of a valid logic level ( 01 2 or 10 2 ) with an alarm signal ( 11 2 ) will result in an alarm signal . logical inversion ( not ) of quad - coded data requires no gates — the wires just have to be swapped . thus , a quad - coded not function has no overhead . further , inverting an alarm signal ( 11 2 ) outputs an alarm signal . it is well known that logic functions and , nand , or and nor can all be constructed from one and gate plus not functions using de morgan &# 39 ; s law . since not functions propagate alarm signals , we just have to demonstrate that a quad - coded and gate also propagates alarm signals . the circuit for a quad - coded and gate is illustrated in fig2 and it can be seen that if one or both inputs are alarm signals then the result will be an alarm signal . xor and xnor functions can be constructed from nand gates in the usual manner . functions of more than two inputs can be constructed from these two input functions , though more efficient versions which still propagate the alarm signal correctly are easy to define . to ensure that alarm signals are propagated as quickly as possible , there are places in the chip where additional circuitry is used to detect the presence of an alarm ( using an and gate ( 5 ) in fig1 ) and then injecting that signal into another circuit as though it had originated from an attack sensor . the placement of these alarm propagators can be worked out by someone skilled in the microprobing art as described in [ 9 ]. as discussed in the previous section , quad - coded not functions are implemented by swapping wires ; no gates are required and so no power is consumed . other functions can be constructed from quad - coded and gates + quad - not functions . the and gate of fig2 consumes the same amount of power regardless of the logical values on the inputs to the gates . it follows that the power consumed during a computation will be largely independent of the data being processed . the most notable exception will be when data values affect the control flow . for example , when computing a digital signature the critical computation is often x y modulo n , where y is the secret value . as exponentiation is implemented using repeated squaring and doubling , depending on whether the bits in the binary expansion of y are zero or 1 , an opponent who can tell the difference between squaring and doubling by studying the chip &# 39 ; s power consumption can deduce the secret value y . however , given a processor of sufficient performance , this residual vulnerability can be dealt with using defensive programming techniques , such as computing both the squaring and the doubling operation at each step and copying only the desired one of the two results to the next stage of the computation . self timed logic has the potential for substantially better performance than clocked logic in a smartcard environment , as the speed of the computation is limited only by the underlying silicon process rather than the externally supplied clock . the quad - coded circuits and defensive programming technique described so far will reduce the data dependent power usage . however , data dependent timing behaviour may be visible . to counteract this effect , additional random delays are added to the data path and control path . this is possible because these circuits are speed independent . the effect is far more subtle than known clocked equivalents which slow the device by a whole clock period which is a predictable unit of time [ 7 ]. random delays in the data - path or the control - path may be inserted using a the circuit in fig3 . a standard pseudo random number generator may be used to provide the random bit values ( 6 ). data or control signals are fed in at ( 9 ). contention between the random bit values and input ( 9 ) may cause the rs flip - flop ( 7 ) to go metastable but the filter ( 8 ) will prevent this metastable signal from propagating to the data / control output ( 10 ). the time it takes for the flip - flop to stabilise is non - deterministic and adds further randomness to the timing of the circuit . finally , in order to support the use of software defensive measures which can further reduce the intelligibility of any residual data dependent power signal , our microprocessor has an additional instruction : set - random - carry . this supports the idea in [ 10 ] whereby a random choice is made between two equivalent but different sequences of instructions . the processor can jump to the two sequences using branch - carry - set and branch - carry - clear instructions . the implementation of the set - random - carry instruction is greatly facilitated by the use of quad - coded logic because a free running pseudo - random number generator based on a shift register ( or without loss of generality and oscillator ) produces pseudo - random bits with a timing independent of the processor instruction execution , and this bit stream is sampled when the set - random - carry instruction is executed . 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