Patent Application: US-15991402-A

Abstract:
one embodiment of the invention relates to a microfluidic apparatus for controlling fluid flow velocity during electroosmotic flow . according to one aspect of the invention , a voltage applied to a gate electrode modulates flow velocity within an associated microchannel , where the gate voltage is separate from any voltage used to induce electroosmotic flow . according to another aspect of the invention , the flow control apparatus combines multiple gate electrodes to control flow in a microfluidic network . according to one embodiment of the invention , the flow control apparatus is fabricated in a planar silicon substrate . according to another embodiment of the invention , the flow control apparatus is fabricated using polymer materials .

Description:
according to an aspect of the invention , depicted schematically in fig1 a gate control voltage v gate 100 applied at a gate electrode modifies the zeta potential 102 within a microchannel by acting through a capacitive voltage divider network consisting of a capacitor c d 104 is formed across the electrical double layer between the zeta potential at the microchannel wall and the bias voltage v channel 106 within the bulk fluid of the microchannel . the gate control voltage is applied across a capacitor c wall 108 formed by a dielectric layer separating the zeta potential from v gate . by varying the gate voltage , the capacitive divider formed by c wall and c d result in modulation of the zeta potential ( ζ ) through the following approximate relationship : δζ =( c wall / c d ) v gate . according to an embodiment of the invention illustrated in fig2 a , a field - effect flow control apparatus using a doped silicon electrode in a silicon substrate is provided . fefc apparatus may comprise a microchannel 200 in a planar silicon substrate 202 which may be doped with a p - type dopant . a selected gate region 204 of the silicon surrounding the microchannel may be heavily doped with an n - type dopant . a p - n diode junction is thereby formed between the p - type substrate and n - type gate region . in some preferred aspects , the substrate material may be formed from n - type silicon , with the gate region selectively doped with a p - type dopant . in either case , reverse biasing the p - n junction will prevent significant current leakage between the gate and substrate , providing electrical isolation between multiple gate regions in a single substrate . a thin insulating dielectric layer 206 is formed on the surface of the microchannel . this dielectric layer may be grown directly within the channel region , for example by selective electrodeposition or vapor deposition of a polymer before or after sealing the microchannel , or it may be deposited along the entire surface of the substrate including the exposed microchannel surfaces . a variety of materials may be employed as the dielectric layer . typically , the dielectric layer will be selected based on compatibility with the microfabrication process , with the fluid and biological molecules within the fluid , and with the range of conditions to which the dielectric layer will be exposed such as variations in ph , temperature , salt concentration , radial and longitudinal electric field , etc . typical material choices may include silicon dioxide , silicon nitride , a variety of polymers , etc . a sealing layer 208 prevents fluid from escaping from the top of the microchannel . the sealing layer may be a bonded silicon , glass , or rigid plastic substrate . alternately , the sealing layer may be fabricated using a polymer film , such as poly ( dimethylsiloxane ) ( pdms ), or a laminated plastic film . as with the dielectric layer , selection of the sealing layer material will depend on compatibility with the microfabrication process , compatibility with the fluid and biological molecules within the fluid , and compatibility with the range of conditions to which the dielectric layer will be exposed . a first hole in the sealing layer 210 allows the connection of a power supply 212 to the gate for application of a gate voltage , v gate . a second hole in the sealing layer 214 allows the connection of a power supply 216 to the non - gate region of the substrate for application of a bias voltage to the substrate , v bias . the bias voltage is selected to maintain a small reverse bias across the p - n junction between the gate and substrate regions . the holes are formed by either removing material from the sealing layer and insulating layer after integration of each layer into the overall system , or by patterning each layer prior to their integration . the mechanisms for patterning depend on the material choice for each layer , e . g . wet hydrofluoric acid etching of a silicon dioxide insulating layer , hot phosphoric acid etching of a silicon nitride insulating layer , micromolding of a pdms sealing layer , or similar technique . while it is understood that this invention applies to systems of multiple and potentially interconnected microchannels , an apparatus with a single microchannel is depicted in fig2 b for clarity of description . one end of the microchannel is connected to a first reservoir 218 . the reservoir is typically fabricated in the sealing layer , but may also be fabricated in the substrate with an access port placed in the sealing layer to allow fluid to be supplied to or removed from the reservoir . the other end of the microchannel is connected to a second reservoir 220 . a power supply 222 used to generate a separation potential along the . length of the microchannel is placed into contact with fluid in the first reservoir using an external electrode . in another embodiment , a thin film metal electrode integrated into the microfluidic system may be used to form an electrical connection between the power supply and fluid within the microchannel . a similar electrical connection 224 is made to the second reservoir to provide a grounding path for the separation potential . an additional embodiment is shown in fig3 . in this case , a substrate 300 is formed from an insulating or high - resistivity material , for example a rigid or flexible plastic , or undoped silicon . a conductive layer 302 is deposited over the substrate . the conductive electrode layer may be selectively deposited over a specified region of the substrate , for example by using a shadow mask during evaporation or sputtering of a metallic thin film , or deposited over the entire substrate and removed from regions where it is not desired , for example by using photolithography and etching of the unwanted electrode material . an insulating layer 304 is deposited on top of the conductive electrode . the insulating layer may be formed from a number of materials , for example an electrodeposited or vapor - deposited polymer . a sealing layer 306 is applied to the top surface of the substrate , enclosing a microchannel 308 . a hole 310 opens the sealing layer and insulating layer to provide a means for electrical connection to the conductive layer 302 . the conductive layer acts as a gate electrode , and a gate voltage 312 is applied to the electrode in order to modulate the zeta potential within the channel . in another aspect of the invention , there are various possibilities with regard to the geometry of the substrate , gate electrode , insulating layer , and sealing layer . fig4 depicts a field - effect flow control microchannel device with sloped channel sidewalls . these sidewalls could be produced by using bulk - etched silicon as the substrate material , by using a bulk - etched silicon template as a mold for embossing a sloped microchannel feature into a rigid plastic substrate ( such as polycarbonate ), or by using a bulk - etched silicon template as a mold for forming a sloped microchannel feature in an in - situ polymerizable plastic ( such as pdms ). according to one embodiment , as illustrated in fig5 the apparatus may comprise one or more gate electrodes 500 positioned in between a first insulating planar substrate 502 and a second planar substrate containing one or more microchannels 506 . a gate dielectric layer 508 may be included to prevent direct electrical connection between the gate electrodes and fluid within the microchannels . in this embodiment , there is considerable freedom in the choice of materials for the various components of the apparatus . the substrate materials may be rigid plastic , soft plastic , silicon , glass , or similar material . furthermore , the gate electrodes may be thin film metal , metal foil , conductive epoxy , conductive polymer , metal wire , conductive ink , or other conductive material . furthermore , the gate dielectric layer may be a spin - on polymer such as pdms , a vapor - deposited polymer such as parylene , or another material which may be readily applied to the substrate and which preferably provides a high dielectric constant and electrical breakdown strength . furthermore , based on the choice of substrate material , the methods available for fabrication of the microchannels are also considerable . for example , microchannels may be fabricated in a polymer substrate ( such as polycarbonate or acrylic ) using hot embossing or injection molding techniques . similarly , chemical etching may be used to fabricate microchannels in a glass substrate which may then be bonded to the gate dielectric film . according to one embodiment , as illustrated in fig6 the apparatus may comprise one or more gate electrodes 600 positioned on the exterior surface of a first insulating planar substrate . in this embodiment , the substrate acts as the gate dielectric layer . other embodiments , uses , and advantages of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein . the specification should be considered exemplary only , and the scope of the invention is accordingly intended to be limited only by the following claims . 1 . d . j . harrison , a . manz , z . fan , h . ludi , h . m . widmer , “ capillary electrophoresis and simple injection systems integrated on a planar glass chip ”, anal . chem ., 64 , 1926 ( 1992 ). 2 . d . j . harrison , k . fluri , k . seiler , z . fan , c . s . effenhauser , a . manz , “ micromachining a miniaturized capillary electrophoresis - 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