Patent Application: US-201213537527-A

Abstract:
a method is provided for deriving an rtl a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position . in this , an error requirement to meet for the design rounding position is derived . for each of the cct and the vct implementation a number columns to discard is derived and a constant to include in the sum addends . for an lms implementation , a number of columns to discard is derived . after discarding the columns and including the constants as appropriate , an rtl representation of the sum of addends operation is derived for each of the cct , vct and lms implementations and a logic circuit synthesized for each of these . the logic circuit which gives the best implementation is selected for manufacture .

Description:
the task of creating faithfully rounded multipliers which introduce an error into the synthesis falls under the category of lossy synthesis as opposed to a traditional synthesis which would be classed as lossless . the structure of the proposed lossy multiplier synthesiser is found in fig2 . this comprises a lossy multiplier rtl generator to which is provided a known error constraint for the multiplication . this provides a plurality of alternative rtl outputs to an rtl synthesiser 22 which produces a netlist of gates for the manufacture of each rtl output with known synthesis constraints . these netlists of gates are then provided to a selection unit 24 which selects the best of the netlists , which is usually the one which can be manufactured with fewest gates and therefore less silicon . embodiments may provide the creation of three faithfully rounded multiplier schemes for the cct , vct and lms architectures ( so in this case the error requirement will be faithful rounding ). cct uses a single constant as compensation . column promoting truncated multiplication ( vct ) takes f ( a , b ) to be the most significant column of δ k ( notated col k − 1 ). lms promotes elements from col k − 1 but leaves the most extreme 4 elements behind as well as introducing a constant of 2 n - k − 1 . algebraically we can represent these as : fig3 shows the sum of addends array for a cct multiplier to implement a and b with k columns truncated and n bits to discard from the result to produce the desired precision . in this case δ k − 2 k f ( a , b )= δ k − 2 k c . to produce bounds on this object we need bounds on δ k ( the value of the bits being discarded ). when a k − 1 : 0 = b k − 1 : 0 = 0 then δ k is entirely full of zeroes , hence δ k ≧ 0 . when a k − 1 : 0 = b k − 1 : 0 = 2 k − 1 then δ k is entirely full of ones , hence δ k ≦ σ t = 0 k − 1 ( 2 k − 2 i )=( k − 1 ) 2 k + 1 . so we can provide the following tight bounds : − c 2 k ≦ δ k − 2 k c ≦( k − c − 1 ) 2 k + 1 t is bounded by 0 ≦ t ≦ 2 n − 2 k and we will show that it can take any value when δ k takes its extreme values . if a k : 0 = 2 k then t =(( a n - 1 : k + 1 2 k + 1 + 2 k ) b + c 2 k ) mod 2 n t 2 − k − c =( 2 a n - 1 : k + 1 + 1 ) b mod 2 n - k now 2a n - 1 : k − 1 + 1 is odd hence coprime to 2 n - k ( hence regardless of the value of c we can always find a and b such that any given t can be achieved when δ k is minimal . when δ k is maximal a k − 1 : 0 = b k − 1 : 0 = 2 k − 1 , under these conditions : t =(( a n - 1 : k 2 k + 2 k − 1 )( b n - 1 : k 2 k + 2 k − 1 )+ c 2 k − max ( δ k )) mod 2 n t 2 − k − a n - 1 : k ( 2 k − 1 )− c − 2 k + k + 1 = b n - 1 : k ( a n - 1 : k 2 k + 2 k − 1 ) mod 2 n - k now a n - 1 : k 2 k + 2 k − 1 is odd hence coprime to 2 n - k hence regardless of the value of c we can always find a n - 1 : k and b n - 1 : k such that any given t can be achieved when δ k is maximal . so we can present the following tight bounds for the error of the cct scheme : − c 2 k ≦ ε cct ≦ 2 n −( c − k + 2 ) 2 k + 1 given these bounds we work out the necessary and sufficient conditions for the faithful rounding of cct multipliers : this can then be used to derive a constant to add to include in a truncated sum of addends array for k columns truncated fig4 shows the sum of addends array for a vct multiplier . in this , the constant to include in the least significant column of the sum of addends is the bits of the most significant of the truncated columns , shifted by one bit . thus a total of t columns are truncated from the result , giving a y bit result . in this case δ k − 2 k f ( a , b )= δ k − 2 k col k − 1 − 2 k c . we will provide tight bounds on this object . we first claim that μ = δ k − 2 k col k − 1 takes its maximal value when col k − 1 = 0 and col k − 2 is an alternating binary sequence . to see that col k − 1 = 0 , consider that μ can be written as ( for an arbitrary function g ): μ = 2 j a j (− 2 k − 1 - j b k − 1 - j + b k − 2 - j : 0 )+ g ( a k − 1 : j + 1 , a j - 1 : 0 , b ) if we set j = 0 in this equation and maximise μ over a 0 and b k − 1 we find a 0 = 1 and by symmetry b 0 = 1 . then , in the general case , if we maximise μ over a j and b k − 1 - j keeping in mind that b k − 2 - j & gt ; 0 as b 0 = 1 then we find that μ is maximised when a j ≠ b k − 1 - j and hence col k − 1 = 0 . to see that col k − 2 is an alternating binary sequence consider the case when there are two adjacent zeroes in col k − 2 so we have a location where : assuming that a j ≠ b k − 1 - j for all j and , by symmetry , we may assume a j - 1 = 1 solving the above equations means a j : j - 1 =“ 11 ” and b k − j : k − j - 2 = 0 . if however we set a j : j - 1 =“ 01 ” and b k − j : k − j - 2 =“ 010 ” we would actually increase μ by : hence when μ is maximal , adjacent zeroes never appear in col k − 2 . further if adjacent ones were to appear in col k − 2 then there would be a one in column col k − 1 , which contradicts the previous assumption . conclude that col k − 1 = 0 and col k − 2 is an alternating binary sequence when μ is maximal . these two conditions uniquely determine a and b , from which can be calculated the bounds : the lower bound on μ is achieved when a j = b k − 1 - j for all j , a 0 = b 0 and the interior of a and b are alternating binary sequences . we will demonstrate each of these properties in turn . μ = 2 j a j (− 2 k − 1 - j b k − 1 - j + b k − 2 - j : 0 )+ g ( a k − 1 : j + 1 , a j - 1 : 0 , b ) if a j ≠ b k − 1 - j and a j = 1 then μ can be decreased by 2 k − 1 - j − b k − 2 - j : 0 & gt ; 0 by setting b k − 1 - j = 1 , hence μ being minimal implies a j = b k − 1 - j for all j . secondly if a 0 = b k − 1 = 0 then μ can be decreased by 2 k − 1 − b k − 2 : 0 & gt ; 0 by setting a 0 = 1 . finally we need to show that the interior of a and b are alternating binary sequences when μ is minimal . first we introduce some notation : where x = x m - 1 . . . x 1 x 0 / 2 m & lt ; 1 and y = y q - 1 . . . y 1 y 0 / 2 q & lt ; 1 , we will then show various strings within a never occur : γ ( 010 )− γ ( 000 )=( x + y )/ 2 − 1 & lt ; 0 so “ 000 ” never occurs γ ( 101 )− γ ( 111 )=−( x + y )& lt ; 0 when k & gt ; 3 so “ 111 ” never occurs if “ 1001 ” were feasible then γ ( 1001 )≦ γ ( 1010 ), γ ( 0101 ), γ ( 1011 ), γ ( 1101 ) this would imply but the only solution to this is x = y = ⅓ which is not possible given that x and y are finite binary numbers . hence “ 1001 ” never occurs . but the only solution to this is x = y = ⅔ which is not possible given that x and y are finite binary numbers . hence “ 0110 ” never occurs . the fact that these strings never occur implies that the interior of a and b are alternating binary sequences . the fact that a j = b k − 1 - j for all j , a 0 = b 0 and the interior of a and b are alternating binary sequences uniquely determine a and b , from which can be calculated the bounds : we are now in a position to tightly bound δ k − 2 k col k − 1 − 2 k c : we will now show that t can take any value whenever μ is extreme . if μ is maximal then col k − 1 = 0 and col k − 2 is an alternating binary sequence . these conditions uniquely determine a k − 1 : 0 and b k − 1 : 0 up to swapping . when k is odd these conditions imply a k − 1 : 0 =( 2 k − 1 1 )/ 3 and b k − 1 : 0 =( 2 k + 1 )/ 3 , t is then defined by : now a n - 1 : k 2 k +( 2 k − 1 − 1 )/ 3 is odd hence coprime to 2 n - k ( hence regardless of the value of c we can always find a and b such that any given t can be achieved when μ is maximal and k is odd . similarly when k is even we have a k − 1 : 0 = b k − 1 : 0 =( 2 k − 1 )/ 3 or a k − 1 : 0 = b k − 1 : 0 =( 2 k − 1 + 1 )/ 3 and the argument proceeds in an identical manner . hence we conclude that regardless of the value of c we can always find a and b such that any given t can be achieved when μ is maximal . if μ is minimal then a 0 = b 0 = 1 , a 1 = b k − 1 - j for all j and the interior of col k − 1 is an alternating binary sequence . these conditions uniquely determine a k − 1 : 0 and b k − 1 : 0 up to swapping . when k is even these conditions imply a k − 1 : 0 =( 5 * 2 k − 1 − 1 )/ 3 and b k − 1 : 0 =( 2 k + 1 + 1 )/ 3 , t is then defined by : now a n - 1 : k 2 k +( 5 * 2 k − 1 − 1 )/ 3 is odd hence coprime to 2 n - k hence regardless of the value of c we can always find a and b such that given t can be achieved when μ is minimal and k is even . similarly when k is odd we have a k − 1 : 0 = b k − 1 : 0 =( 2 k + 1 − 1 )/ 3 or a k − 1 : 0 = b k − 1 : 0 =( 5 * 2 k − 1 + 1 )/ 3 and the argument proceeds in an identical manner . hence we conclude that regardless of the value of c we can always find a and b such that any given t can be achieved when μ is minimal . given t can take any value when μ is extreme allows us to state the error the vct scheme : given these bounds we work out the necessary and sufficient conditions for the faithful rounding of vct multipliers : | ε vct |& lt ; 2 n 3 * 2 n - k + 1 − k − 2 & lt ; 6 c & lt ; k − 7 thus for a given error we can derive a number of columns k to discard from the sum of addends and a constant c to add from the most significant columns discarded fig5 shows the sum of addends array for a for an lms multiplier . in this , some of the bits from the least significant non - truncated column is shifted to the next least significant column for inclusion in the sum of addends the error bounds on this scheme were first reported in [ 16 ] and can be summarised by : as stated in [ 16 ], in absolute value , the most negative error dominates . from this condition we can derive the necessary and sufficient condition for faithful rounding of the lms scheme : | ε lms |& lt ; 2 n 9 * 2 n - k + 1 & lt ; 6 k + 3 +(− 1 ) k now we have the necessary and sufficient conditions for faithful rounding of the cct , vct and lms truncated multiplier schemes we can show how to construct a lossy multiplier rtl generator . in each case we want to choose the value of k and c which minimises the hardware costs . the cost of the hardware is directly related to the number of bits that need to be summed . so we wish to maximise the size of k and minimise the number of ones in the binary expansion of c while maintaining the property that the multiplier is faithfully rounded . so we can create the following algorithms which define the conditions which are required to achieve this for the known error bounds : where minhamm ( x : condition ) calculates the smallest value within the set of all x that meet the condition with smallest hamming weight . so as an embodiment of the invention consider the case where n = 8 . the lossy multiplier rtl generator will first calculate all the relevant parameters : and then produce the cct , vct and lms rtl which use those parameters . the lossy synthesiser will then use standard rtl synthesis to produce the gate level netlists . from which the netlist which exhibits the best quality of results according to the synthesis constraints can be chosen . 1 . determine a faithful rounding precision and error bounds required for a multiplier . 2 . determine k and c for a cct implementation . 3 . determine k and c for a vct implementation . 4 . determine k for an lms implementation . 5 . derive an rtl representation of each of the cct , vct and lms implementations . 6 . use rtl synthesis to produce gate level netlists for each of the implementations . 7 . select the netlist which gives the best implementation according to desired factors such as number of gates , amount of silicon , power consumption , speed of operation . 8 . manufacture the thus selected netlist as a multiplier in an integrated circuit . in the embodiments described above the derivation of k and c and the rtl generation and synthesis can take place on a general purpose computer loaded with appropriate software . alternatively , it can take place on a programmable rtl generator loaded with appropriate software . 1 ) in the embodiment above it was assumed that error requirement was faithful rounding . the error bounds can be used to calculate the necessary and sufficient conditions where a different error requirement is needed . say we had the generic requirement : where α & gt ; ½ this would then give us the following necessary and sufficient conditions on k and c for this to hold : so the parameter creation part of the lossy multiplier rtl generator will take α as an extra input . the lossy multiplier rtl generator can be designed to cope with more complex error constraints and is not limited to faithful rounding 2 ) the lossy multiplier rtl generator can also produce an error report detailing the worst case error , worst case error vectors and other properties of the error . in the case of cct it can be shown that when 2c − k + 1 & lt ; 2 n - k there are 2 n - k worst case error vectors , these are constrained by : where pa = 1 mod 2 n - k . otherwise there are ( k + x + 1 ) 2 n - 1 worst case error vectors where x is the number of times 2 divides c , for m = 0 , 1 , 2 . . . , k + x these are constrained by : a n - k − x + m - 1 : m b n - m - 1 : k + x - m + c / 2 x = 0 mod 2 n - k − x in the case of vct it can be shown that there are always 2 n - k + 1 worst case error vectors which are constrained by : b n - 1 : k =− p ( c + x / 18 + a n - 1 : k b k − 1 : 0 ) mod 2 n - k where pa = 1 mod 2 n - k and a k − 1 : 0 , b k − 1 : 0 and x are defined in table 1 . 3 ) instead of simply an n by n multiplication returning an n bit answer , we can generalize this to an n by m multiplication returning a p bit answer . in the case of cct it can be shown that the necessary and sufficient conditions for faithfully rounding are : 4 ) integer multiplication is used in many other datapath components , for example they are central to floating point multipliers . for example it can be shown that the following code will result used as the integer part of a floating point multiplier will be correct to 1 unit in the last place if truncmult ( a , b , n + 2 ) returns a faithful rounding of the top n + 2 bits of product of a and b : fig6 shows schematically how the method described above can be implemented in the rtl generator of fig2 . for a given multiplier , a required bitwidth n for a rounding accuracy is supplied in parallel to each of a cct parameter creating unit 60 , a vct parameter creation unit 62 , and an lms parameter creation unit 64 . these also receive the error requirements as shown in fig2 and using the create respectively c and k for the vct and cct units and k for the lms unit . these values are then supplied to respective cct , vct and lms rtl synthesis units ( 66 , 68 , 70 ) which produces a netlist for each scheme . this is passed to the selection unit 24 of fig2 which is controlled to select the best netlist for manufacture . as discussed above , all this can be implemented in dedicated rtl generators or in programmable generators or in software on a general purpose computer . once the best netlist has been selected , it can be incorporated in the design of an integrated circuit . m . j . schulte and j . earl e . swartzlander , “ truncated multiplication with correction constant ,” in workshop on vlsi signal processing , vol . vi , no . 20 - 22 , october 1993 , pp . 388 - 396 . s . s . kidambi , f . ei - guibaly , and a . antoniou , “ area - efficient multipliers for digital signal processing applications ,” ieee transactions on circuits and systems ii : analog and digital signal processing , vol . 43 , no . 2 , pp . 90 - 95 , february 1996 . e . j . king and j . earl e . swartzlander , “ data - dependent truncation scheme for parallel multipliers ,” in thirty - first asilomar conference on signals , systems & amp ; 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