Patent Application: US-201515110064-A

Abstract:
a method of programming a fpga , wherein the fpga comprises an array of macrocells , each comprising at least a configurable hardware block and a configurable interconnection network , the method comprises the steps of : providing a high - level configuration file containing : first data defining a set of macrocells and their relative positions ; second data defining a configuration of the hardware blocks of the macrocells ; and third data defining interconnections between the macrocells ; wherein said high - level configuration file contains neither data defining an absolute position of the macrocells within the fpga , nor local routing information fully defining a configuration of their interconnection networks ; converting said high - level configuration file into a bitstream file ; and uploading the bitstream file into the fpga . a semiconductor chip comprising a fpga and a device configured for programming the fpga are provided .

Description:
although the invention will be described by considering the specific example of a simple island - style architecture ( fig1 a and 1b discussed above ) it should be stressed that it can be easily adapted to any possible fpga architecture , e . g . hierarchic , coarse - grain and row - based architectures . in order to illustrate the vbs concept , it is necessary to introduce , starting from the general architecture of fig1 a , the notion of “ macrocell ”. as illustrated on fig2 a , a macrocell mc is constituted by a logic block lb ( more generally , a reconfigurable hardware block ), and a “ local ” configurable interconnection network licn comprising a portion of an x - channel and of an y - channel adjacent to said logic block , the switches connecting said portions of x - and y - channels to said logic block lb and to adjacent logic blocks , and the switchbox swb interconnecting said portions of x - and y - channel . it is easy to check that the whole logic fabric of fig1 a is obtained by repeating the macrocell of fig2 a horizontally and vertically , and more specifically that the “ whole ” interconnection networks icn is obtained by repeating the “ local ” interconnection network licn of the macrocells . fig2 b only represents the interconnection network part of a macrocell . it shows that this local interconnection network licn has a plurality of “ ports ” which are connected to the logic block lb , to logic blocks lb ′, lb ″ of adjacent macrocells or to local interconnection networks licn ′, licn ″, licn ′″, licn ″″ of adjacent macrocells . for macrocells disposed at the edges of the logic fabric , some ports may be connected to dedicated input / output blocks . fig2 c shows a more abstract view of the interconnection network licn of the macrocell , hiding its internal structure ; the network appears as a “ black box ” with ( 4w + l ) ports labeled p 0 − p 4w + l − 1 , where w is the width of the x - and y - channels and l the number of input / output ports of each logic block ( l = k + 1 for a logic block with k inputs and 1 output ). switches sw are ignored at this level of abstraction ; the configuration of the local interconnection network licn is only defined by indicating the connection between its ports ( e . g . by indicating that port p 3 is connected to port p 5 and port p 5 to ports p 7 and p 12 ). this abstraction is instrumental in making the vbs independent from local routing , and allows a reduction of the data required to describe the macrocell configuration . the raw number nrawof bits required to fully configure a macrocell mc of a fpga having the architecture of fig1 a , 1b with k input luts and w routing channels is given by : n raw = n lut + n lb + 6 ×[ n s + n c + ]+ 3 ×[ n ct ] n lut is the lut content , n lut = 2 k ; n lb is the value of the sel command , n lb = 1 ; n s is the number of configurable switches in a switch box , n s = w ; n c + is the number of 4 - way configurable switches per channel , n c =( k + 1 )·( w − 1 ), and n ct is the number of 3 - way configurable switches per channel , n ct =( k + 1 ). table 1 summarizes the raw data size n raw for different architectures whose lut - size ranges from k = 3 to k = 9 and channel width ranges from w = 2 to w = 10 . while the main goal of the invention is to allow an unfinalized “ virtual ” bitstream to be placed anywhere on the logic fabric , it is also very useful to reduce the size of the virtual bit stream in order to lower the download time from an external memory . even with powerful compression schemes , the raw data entropy of an almost empty macrocell ( i . e . a macrocell with a low count of routed wires ) is still high since the lack of connections of some of the connection blocks is also information . according to an embodiment of the invention , the macrocell configuration data is modeled as a list of point - to - point wires by specifying a list of entry point and output point in the local routing network for each of these wires . the data size of each list member depends on the number l of inputs and outputs . in the following , it will be considered that l = k + 1 . table 2 is a report of the connection word size n cw for various channel width ( w ) and lut size ( 2k = 2l − 1 ) combinations . it is very advantageous to design the architecture as a trade - off between the w and k parameters in order to keep the “ bit waste ” as low as possible : the parameter combination should be chosen so that the corresponding connection word size is on an upper limit . table 3 states the percentage of the previously discussed “ wasted bits ”. this percentage is expressed as the remaining ( unused ) entropy in the final coding of the connection word size . for vbs compression purposes , it is preferred to choose a target word size and then select the better architecture ( w , k )— e . g . ( 4 , 3 ), ( 6 , 7 ), ( 7 , 3 ), etc — i . e . that with the lowest “ bit waste ” percentage , and therefore the highest compression ratio . it is easy to see that , for a 5 - bit macrocell connection word size , optimal use of the available entropy is reached for architectures ( 6 , 7 ) and ( 7 , 3 ); on the contrary ( 3 , 4 ) would be a poor choice with more than 18 % of the bit wasted . from a memory occupation point of view , replacing raw data with a connection list is only advantageous if the number n ptp of point - to - point connections within each macrocell is much lower than the theoretical maximum n th =( w + k + 1 )·( w + k )/ 2 . more precisely , table 4 shows the maximum number n max of point - to - point connections leading to a vbs connection list smaller than the raw dataset for a given ( w , k ) pair : for example , for w = 4 , k = 4 the maximum value of n ptp for which a connection list is shorter than the corresponding raw data is n max = 13 , while the theoretical maximum number of point to point connections is n th = 210 . however , in practice , the condition n ptp & lt ; n max is usually satisfied . a virtual bitstream containing — beside logic block configuration bits — a list of point - to - point connections representing in compact form the configuration of a portion of the fpga interconnection network may come in different formats . three of them , of increasing complexity and compactness , will now be described ; an unlimited number of different formats falling within the scope of the invention might be devised . a first possible binary format for a virtual bitstream comprises a raw list of the lut content of each macro , aside with a list of its local connections . table 5 summarizes this format : each indent of the fields denotes a repetitive block . the field preceding the block denotes the number of expected repetitions . the size in bits of each field is fixed for a given architecture ; it is given in function of : the with w and height h , expressed in number of macrocells , of the portion to be configured of the fpga logic fabric ; the number n logic of bits required to configure a logic block ( n logic = 2 k + 1 in the case of a logic block having the structure illustrated on fig1 b ); the number l of input / output ports of each logic block ( l = k + 1 in the case of a logic block having the structure illustrated on fig1 b ). “ size x ” and “ size y ” represent the width and height of the of the portion of the fpga logic fabric to be configured and take the values “ w ” and “ h ” respectively ; macrocountwxh is the number of macrocells to be configured . the following data are repeated for each macrocell (“ list of macrocells ”): “ posx ”, “ posy ” represent the position of a given macrocell within the portion of the fpga logic fabric to be configured “ logic data ” is the raw configuration data of the logic block of the macrocell , routecount represents the number n ptp of point - to - point connections between the ports of the ( local ) interconnection network of the macrocell . for each said connection (“ list of connection ”), the “ in ” and “ out ” ports are identified . the ebnf notation of this first virtual bitstream ( vbs ) format is : vbs =& lt ; header & gt ;, & lt ; macrocell - list & gt ; header =& lt ; sizex & gt ;, & lt ; sizey & gt ; macrocell - list =& lt ; macrocount & gt ;, {& lt ; macrocell & gt ;} macrocell =& lt ; posx & gt ;, & lt ; posy & gt ;, & lt ; logic data & gt ;, & lt ; connection - list & gt ; connection - list =& lt ; routecount & gt ;, {& lt ; connection - data & gt ;} connection - data =& lt ; input & gt ;, & lt ; output & gt ;. a second possible binary format for a virtual bitstream is especially designed to have a higher compression ratio for dense interconnection networks . what is different from the first format is the structure and size of the “ list of connections ”. a “ connection present ” bit and its associated “ connection data ” represent each connection ( see table 6 ). the ports of the interconnection network are numbered and the connection list sorted by input port number . it is supposed that different connection cannot share a same input ports ; this condition can always be satisfied by switching the input and output ports of some connection , which is allowed as the connections are bidirectional . for each possible input , taken in order , of the local interconnect network , the following two exclusive cases may happen : there is a connection in the list that uses this input : the connection present bit is set to 1 , the connection data field is set to the corresponding output of the connection . the connection present bit is set to 0 , the connection data field is set to the next used connection input of the list . for example , let us consider the case where port 1 of the local interconnect network is connected to port 6 ; ports 2 and 3 are not used and port 4 is connected to port 5 , the total number of ports being 6 . then , the list of connections would be the following : connection present flag = 1 ( meaning that port 1 is the input port of a point - to - point connection ), connection data = 6 ( meaning that port 1 is connected to port 6 ). connection present flag = 2 ( meaning that port 2 does not take part to any point - to - point connection ), connection data = 4 ( meaning that the next used input port is n ° 4 ; there is no entry corresponding to port 3 , which is not used as the input of a connection ). connection present flag = 0 ( port 5 is used as an output port , not an input one , although this distinction is arbitrary ), connection data = 0 ( any other port of the interconnection network is used as an input port ). a third possible binary format for a virtual bitstream can be considered an enhanced version of the second one wherein the size of the virtual bitstream is further reduced through the use of lists for each x and y axis of macrocells of the hardware task . the connection list of each macrocell is coded accordingly to the vbs format version 2 . however , instead of providing the macrocell data with their respective positions as a heap , they are ordered in two kinds of lists : y - lists and x - lists . multiples x lists are contained in a single y - list . a 0 bit , meaning that the current line does not contain any macrocell , or a 1 bit , in which case an x list follows . a 0 bit indicates the absence of a macrocell at this x position , and a 1 bit is followed by macrocell data as in the second format . fig3 illustrates how , according to an embodiment of the present invention , virtual bitstreams can be used for programming a fpga . an external memory em — e . g . a mass storage memory of a computer — stores multiple virtual bitstreams vbs 1 - vbsn corresponding to different hardware task to be implemented in a fpga indicated by reference plc . a device according to an embodiment of the invention , called “ reconfiguration controller ” and indicated by reference rc loads one or more virtual bitstreams from the external memory em ( step 1 ), stores them into a local ( cache ) memory lm ( step 2 ), “ de - virtualizes ” them — i . e . it decompresses vbs data an re - map the routing information and logic data to the target logic fabric , which results in actual , architecture - and location - dependent bitstreams — and finally loads the resulting bitstream into the configuration memory of the fpga ( step 3 ). in the exemplary embodiment of fig3 , the reconfiguration controller , the local memory and the fpga are co - integrated on a single semiconductor chip , but this is not essential . fig4 shows a synoptic of the reconfiguration controller rc . it can be seen that four distinct functional modules may be identified : a core logic module clm , a fetching module fm , a de - virtualizing module dvm and a logic mapping module llm . the core logic and fetching modules are largely independent from the fpga architecture , while the de - virtualizing and the logic mapping module are architecture - dependent . the core logic module clm , which can be implemented as a soft processor or a hardware state machine , manages the others modules through the use of control signals in order to synchronize their operation . the core logic module is also in charge of interfacing with an external control unit extu ( e . g . a suitably - programmed general - purpose computer ) which configures and commands the whole configuration controller . the core logic is also in charge of determining whether a task can be charged on the fpga — and in the affirmative of calculating the location where it will be implemented — and whether a task is already implemented and can therefore be unloaded ; it can also carry out a defragmentation of the logic fabric i . e . a displacement of the task to allow a better utilization of the hardware resources of the fpga . these operations are performed by using known placing algorithm ; they require the loading of task metadata stored in the external memory em and the keeping a list of already - implemented tasks . the expression “ task metadata ” refers to all the pieces of information on a vbs other than routing data and configuration bits of the logic blocks , e . g . task size , vbs size , number of macrocells used to implement the task etc . placing algorithms suitable to be implemented by the core logic unit are known e . g . from [ bazargan 1999 ], [ steiger 2003 ], [ tabero 2003 ], [ tabero 2006 ] and [ hu 2010 ]. fig5 shows the state diagram of a finite state machine ( fsm ) modeling the core logic module clm of a reconfiguration controller according to an embodiment of the invention . different embodiments may use different fsms , and more particularly simpler ones comprising less states and exchanging less messages with the external control unit extu . the “ wait ” state waits for messages from the external control unit extu : “ load task ”, “ unload task ” and “ get information ”. the “ load task ” message triggers the loading from external memory em of task metadata in order to determine if enough space is left on the target fpga , then it activates the de - virtualizing module to starts the de - virtualization process before activating the logic mapping module for loading the finalized bitstream on the logic fabric ( see infra ) and sending an acknowledgement (“ send ack ”) to the external control unit extu . if there is no space left on the logic fabric , an error is detected ; then the finite state machine returns to its “ wait ” state . the “ unload task ” message also triggers a load of the specified task &# 39 ; s metadata in order to check if a given task is already loaded on the logic fabric . if this is the case , the configuration area corresponding to this task is invalidated by replacing it by an “ empty ” bitstream and an acknowledgement is sent to the external control unit extu (“ send ack ”). otherwise , an error is detected ; then the finite state machine returns to its “ wait ” state . the ( optional ) “ get information ” message is used to fetch various pieces of information from the controller on the reconfigurable fabric ( occupancy , consumption , temperature ). these data , e . g . obtained by sensors in the fpga , can be used by the core logic for task placement . the fetching module fm is mainly responsible for loading a specific virtual bitstream from the external memory em to the local memory lm , and for extracting task metadata and providing them to the core logic module . the de - virtualizing module dvm is in charge of reading the virtual bitstreams from the local memory lm and of saving in the same ( or a different ) local memory the resulting raw bitstream . the operation of the de - virtualizing module dvb may be expressed as a de - virtualization algorithm , which maps the connection list of a given macrocell to the configuration bits of a logic fabric macrocell . the actual implementation of the algorithm is strongly dependent on the virtual bitstream format and on the fpga architecture . however , at high - level , it can be expressed by the following pseudocode : “ configuration ” is the raw bitstream to be generated , which is in the form of an array of bits . the “ connection_list ” is a list of point - to - point connection extracted from the virtual bitstream , as explained above . each connection is characterized by an input port — output port pair . the first “ for ” loop goes through this list ; the second “ for ” loop searches , for each ( input , output ) pair , all the possible routes of the local configuration network connecting the “ input ” port to the “ output ” port . each route is defined by the status of a number of configurable switches of the macrocell . each route which is found is tested for conflicts with already identified ones . the first route ( i . e . switch configuration ) which is found to be free from collisions is selected to implement the ( input , output ) connection . these operations are repeated for all the point - to - point connections of a given macrocell , and for all the macrocells of the virtual bitstream . the de - virtualization algorithm is simple and straightforward as the most complex operations are deported at the virtual bitstream elaboration stage . time consuming operations , like the enumeration of each possible route between a given input and output , can be implemented in a look - up table in the controller , since the result set is finite and fixed in advance for a given architecture . it should be noted that the de - virtualization algorithm might find itself in a dead end if all the possible routes implementing a given connection collide with other routes . to avoid such a situation , de - virtualization is preferably tested offline for each specific target fpga architecture . if it turns out that the de - virtualization cannot be carried out successfully , the order of the connections within the virtual bitstream is changed , until de - virtualization becomes possible . the logic mapping module lmm is in charge of inserting a raw bitstream , read from the local memory , into a specific location ( calculated by the core logic module , as discussed above ) of the configuration memory of the fpga . depending on the target architecture , the logic mapping module may : configure a specific serial path in the configuration memory in order to insert bitstream data at the correct location ; program the targeted location in the configuration memory by direct addressing ; or trigger a memory exchange upon configuration of the hardware task , in the case of a dual configuration memory layout . it should be understood that the four modules may not be implemented in the form of separate , physically distinguishable units . for example , a single processor or circuit may perform the tasks of two or more said “ functional ” modules . an advantageous feature of the invention is that the reconfiguration controller is intrinsically parallelizable . fig6 a and 6b illustrate two possible parallelized organization of the reconfiguration controller . fig6 a illustrates a reconfiguration controller wherein only the virtual bitstream de - virtualization is parallelized . in such a controller , n & gt ; 1 de - virtualizing modules dvm 1 - dvm n operate in parallel to simultaneously de - virtualize n portions of a same virtual bitstream , corresponding to respective macrocells or groups of macrocells . a tradeoff has to be found between the number n of parallel de - virtualizers and the time taken by the de - virtualization of a single macrocell , so that the fetching module or the logic mapper do not become bottlenecks . fig6 b illustrates a different reconfiguration controller comprising n & gt ; 1 processing units pu 1 - pun , each comprising a fetching module ( fm 1 , . . . , fmn ), a de - virtualizing module ( dvm 1 , . . . , dvmn ) and a logic mapping module ( lmm 1 , . . . , lmmn ) for simultaneously de - virtualizing multiple virtual bitstreams . this requires that the surrounding environment of the reconfiguration controller also supports multiple concurrent access : the external and local memories should have n read / write interfaces and the logic fabric should also be designed to allow multiple bitstreams to be programmed in parallel . the two parallelization scheme may be combined ; in this case , each processing unit pui will comprise multiple parallel de - virtualizing modules . fig7 a to 7d illustrate the application of a fpga programming method according to an embodiment of the invention for implementing a simple combinatorial logic circuit , namely a two - bit adder with carry . the truth table of such a circuit is given in table 8 : the adder is described , placed and routed using the vpr ( versatile place and route ) academic software on a fpga architecture of the kind illustrated on fig1 a , 1b with : w = 4 , k = 4 , l = 5 . the number of bits required to configure each logic bloc is 2 k + 1 = 17 . fig7 a shows the routing network of the architecture with the adder placed , as generated by the place - and - route tool . three logic blocks , arranged on a 2 × 2 array with one unused block , are required to compute the three output bits — z 1 , z 2 and r . the place - and - route tools considers input / output blocks spread on the outer ring of the fpga , while in the present application input and output must be spread on the logic fabric . therefore , additional macrocells have to be introduced to account for the routing channels at the leftmost and bottommost sides of the design . indeed , since the macrocell only contains the logic elements and its surrounding local routing network , the leftmost and bottommost channels are left orphan and must be included in a dedicated macrocell , even if they don &# 39 ; t include a logic element . fig7 b shows the equivalent reconfigurable fabric needed to place the adder . for the reasons discussed above , a 3 × 3 array of macrocells mc 1 - mc 9 is used . only the logic blocks of macrocells mc 3 , mc 5 and mc 6 are used for computation ; the other ones are unused . fig7 c shows the fully routed design , featuring the necessary routes between the inputs and the logic blocks as well as the outputs routing . fig7 d depicts the same network using the conventions of fig1 a . dotted elements are physically part of the task but are not needed . the data contained in a virtual bitstream defining the logic fabric configuration are the following : connection from 16 to 8 connection from 6 to 9 connection from 6 to 13 connection from 7 to 20 connection from 7 to 17 connection from 0 to 18 connection from 2 to 16 connection from 7 to 3 connection from 7 to 17 connection from 5 to 19 connection from 13 to 20 plus the 3 × 17 bits required to configure the logic blocks of macrocells mc 3 ( 16 bits defining the truth table for z 1 plus a “ sel ” bit for choosing the combinatorial output of the logic block ), mc 5 ( 16 bits defining the truth table for r plus a “ sel ” bit for choosing the combinatorial output of the logic block ) and mc 6 ( 16 bits defining the truth table for z 2 plus a “ sel ” bit for choosing the combinatorial output of the logic block ). table 9 presents the full representation of the virtual bitstream using the first format described above ( see table 5 ): the size of the raw bitstream is 1323 bits that of the virtual bitstream is : 513 bits if the first format is used ( 38 . 7 % of the raw size ), 503 ( 38 %) for the second format and 479 ( 36 . 2 %) for the third format . the second and third formats are really interesting for dense routing networks , which is not the case here . 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