Patent Application: US-37542895-A

Abstract:
a recording medium having a sync for synchronizing with data and a dcc for suppressing a dc component of a wave form of a signal recorded on the recording medium , the sync and the cdd being adjacently recorded on the recording medium . both the sync and dcc are patterns that are not present in a data portion . a signal recording apparatus , comprising a dsv calculating means for calculating a dsv of a signal wave form recorded on the recording medium , a cancel code generating means for generating a cancel code for suppressing a dc component of the signal wave form corresponding to the dsv calculated by the dsv calculating means , and a recording means for connecting a synchronous code and record data to the cancel code generated by the cancel code generating means and recording the cancel code , the synchronous code , and the record data on the recording medium so that the cancel code and the synchronous code are adjacently disposed , the synchronous code being adapted for synchronizing with data . a signal reproducing apparatus , comprising a reading means for reading the signal from the recording medium , and a synchronous code detecting means for detecting a predetermined pattern contained in a continuous pattern of the synchronous code and the cancel code as a significant synchronous code for synchronizing with data from the signal read by the reading means .

Description:
next , with reference to the accompanying drawings , embodiments of the present invention will be described . fig1 is a schematic diagram showing the construction of a data / ecc portion in a sector format of an optical disc according to an embodiment of the present invention . fig2 is a schematic diagram showing the relation of the positions of a sync ( synchronous code ) and a dcc ( dc cancel code ) in the data / ecc portion of fig1 and signal lengths thereof . as shown in fig1 and 2 , at the beginning of each frame of the data / ecc portion , the sync 13 and the dcc 14 are adjacently disposed . in other words , at the beginning of the frame , the dcc 14 is disposed . the dcc 14 is followed by the sync 13 . the signal length of the sync 13 is 27 bits . the signal length of the dcc 14 is 9 bits . thus , the total signal length of the sync 13 and the dcc 14 is 36 bits . fig3 is a schematic diagram showing patterns of the sync 13 and the dcc 14 . referring to fig3 in the &# 34 ;*&# 34 ; portion , the value of &# 34 ; 0 &# 34 ; or &# 34 ; 1 &# 34 ; is placed . the sync 13 and the dcc 14 are represented with predetermined patterns that are not present in the data portion , namely the 4 - 9 modulation code . thus , a continuous pattern composed of the sync 13 and the dcc 14 can be treated as a single sync pattern . in this example , as a pattern that is not present in the data portion , a pattern with the code inversion lengths for 17t , 4t , 4t and 6t is used . thus , in the optical disc according to this embodiment , since the continuous pattern composed of ( sync 13 + dcc 14 ) can be treated as a single sync pattern , the signal length of the sync 13 can be reduced for the signal length of the dcc 14 , thereby improving the recording density without deteriorating the function of the dcc 14 . next , a signal recording apparatus that records the continuous pattern composed of the sync 13 and the dcc 14 will be described . fig4 is a block diagram showing the construction of a signal recording apparatus according to the present invention . referring to fig4 the signal recording apparatus comprises a data modulating portion 41 , a dsv calculating portion 42 , a dcc determining portion 43 , a sector composing portion 44 , an nrzi modulating portion 45 , and a signal recording portion 46 . the data modulating portion 41 performs the 4 - 9 modulation for the input data and supplies a 4 - 9 modulation signal to the dsv calculating portion 42 and the sector composing portion 44 . the dsv calculating portion 42 calculates a dsv ( digital sum value ) corresponding to the input 4 - 9 modulation signal and supplies the dsv to the dcc determining portion 43 . the dsv is obtained , block by block ( for example , as blocks of d1 to d10 , d11 to d20 , and d21 to d30 of fig1 ). whenever the dsv is obtained , the dcc is determined . for example , as shown in fig5 a and 5b , now assume that two dcc values (&# 34 ; 010001000 &# 34 ; and &# 34 ; 000001000 &# 34 ;) are used so as to calculate dsvs for these values . thereafter , the absolute values of the dsvs are compared and the dcc with the smaller absolute value is determined as the dcc 14 to be recorded . the sector composing portion 44 adds the determined dcc 14 to the record data along with the sync 13 . thereby the sector format shown in fig1 is composed . thereafter , the nrzi modulating portion 45 performs the nrzi modulation for the 4 - 9 modulation signal composed of the dcc 14 , the sync 13 , and the record data . the signal recording portion 46 records the 4 - 9 modulation signal on a recording medium ( optical disc ) d . next , a signal reproducing apparatus that reproduces a signal from the recording medium will be described . fig6 is a block diagram showing the construction of the signal reproducing apparatus . referring to fig6 the signal reproducing apparatus comprises a signal reading portion 61 , an nrzi demodulating portion 62 , a sector decomposing portion 63 , a synchronous code extracting portion 64 , a data synchronizing portion 65 , and a data demodulating portion 66 . the signal reading portion 61 reads a signal that has been recorded on a recording medium d and supplies the signal to the nrzi demodulating portion 62 . the nrzi demodulating portion 62 performs nrzi demodulation for the read signal and supplies the demodulation signal that is a 4 - 9 modulation signal to the sector decomposing portion 63 . the sector decomposing portion 63 extracts a data portion from the 4 - 9 modulation signal that composes the sector format and supplies the data portion to the data demodulating portion 66 . the synchronous code extracting portion 64 extracts dcc 14 + sync 13 from the 4 - 9 modulation signal and supplies them to the data synchronizing portion 65 . the data synchronizing portion 65 includes a sync detecting circuit . the sync detecting circuit detects a significant sync pattern necessary for synchronizing with data from dcc 14 + sync 13 . the sync detecting circuit will be described later in more detail . the data synchronizing portion 65 generates a data extracting timing for the data demodulating portion 66 corresponding to the detected result of the sync pattern so that the data demodulating portion 66 performs the 4 - 9 demodulation for the data , byte by byte . thus , reproduced data is output . fig7 is a schematic diagram showing a construction of the sync detecting circuit . the sync detecting circuit comprises a shift register and some logic gates . in other words , the sync detecting circuit inputs serial data that has been nrzi demodulated whenever a bit clock takes place . when the input pattern accords with the above - described sync pattern , the sync detecting circuit outputs a sync detection signal . tables 1 and 2 show pairs ( a ) to ( j &# 39 ;) of the significant sync pattern and detected bit sequences . the upper row of each pair represents the significant sync pattern composed of 36 bits of dcc + sync . the lower row of each pair represents part of the significant sync pattern . for example , the lower row of the pair ( a ) represents that 26 bits other than the high order five bits and the low order five bits of the significant sync pattern composed of 36 bits of dcc + sync are detected bits of the significant sync pattern . the 26 - bit pattern is the minimum required number of bits for pattern comparison since the first bit is an inversion point of the value of the dcc and the last bit is the start bit of a sequence of 6t of the pattern of sequences of 17t , 4t , 4t , and 6t ( that are not present in the data portion ). the lower row of the pair ( j &# 39 ;) represents that all bits of dcc + sync are detected bits of the significant sync pattern . in other words , a bit sequence as the significant sync pattern can be selected from the minimum bit number of the lower row of the pair ( a ) in table 1 to all the bits of dcc + sync of the lower row of the pair ( j &# 39 ;) of table 2 . in this embodiment , the dcc 14 is disposed at the first block of frames that contain the sync 13 . in addition , the dcc 14 is disposed at the beginning of each block . conventionally , the dcc is added so as to suppress the dc component when a signal is recorded . thus , when data is reproduced , the dcc is not necessary . according to the present invention , since the dcc 14 is disposed at the beginning of each block along with the first block , the dcc 14 can be used as auxiliary information that allows data to be synchronized between each sync 13 . thus , even if the sync 13 cannot be detected due to a burst error and thereby data cannot be synchronized , with the dcc 14 of each block , the data can be synchronized . consequently , the synchronism restoring time can be more shortened than the case that data is synchronized with only the sync pattern . when the synchronism restoring time is shortened , the amount of data that is processed can be increased and the reliability of the data can be improved . when only the sync pattern is used , an incorrectable error may take place . however , when data is synchronized using the dcc 14 of each block , the probability of which the error is corrected is increased . the situation that the error cannot be corrected is remarkably reduced , thereby reducing the load applied to the error correcting side . in the embodiment , a significant sync pattern contained in the continuous pattern of sync 13 + dcc 14 is detected so as to synchronize with data . however , as shown in fig8 not only the sync pattern , but a pattern of the dcc 14 may be detected so as to synchronize with data . in fig8 reference numeral 81 is a sync pattern detecting portion . as with the above - described sync detecting circuit , the sync pattern detecting portion 81 detects a significant sync pattern contained in the continuous pattern of sync 13 + dcc 14 and supplies the detected signal to an and gate 82 . reference numeral 83 is a dcc pattern detecting portion that detects only a pattern of the dcc 14 and outputs the detected signal to the and gate 82 . thus , in this construction , only when both the patterns of the sync 13 and the dcc 14 are detected , the sync is detected . consequently , the accuracy of detecting the sync is raised and thereby the reliability of synchronism of data can be improved . in the first embodiment , the sync pattern contains a sequence of a code inversion length for 17t . however , the sync pattern may contain a sequence of a code inversion length for 18t . in the first embodiment , the 4 - 9 modulation system is used . however , as long as the sector format contains the sync 13 and the dcc 14 , a variety of modulation systems such as another rll ( run length limited ) modulation system may be applied to the present invention . in the first embodiment , the dcc 14 is disposed at the beginning of each frame and followed by the sync 13 . however , the sync 13 may be disposed at the beginning of each frame and followed by the dcc 14 . as described above , in the recording medium , the signal recording apparatus thereof , and the signal reproducing apparatus thereof according to the present invention , the amount of data that is recorded on the recording medium can be increased without shortening the bit length of the synchronous pattern to be detected and without deteriorating the function of the cancel code . in addition , since part or all of the cancel code is contained in the synchronous pattern to be detected , when data is reproduced , it can be securely synchronized , thereby improving the reliability of the reproduced signal . although the present invention has been shown and described with respect to a best mode embodiment thereof , it should be understood by those skilled in the art that the foregoing and various other changes , omissions , and additions in the form and detail thereof may be made therein without departing from the spirit and scope of the present invention . table 1__________________________________________________________________________ ( a ) 0 * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 ( b ) 0 * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 ( c ) 0 * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 ( d ) 0 * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 ( e ) 0 * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 ( f ) 0 * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 ( g ) 0 * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 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