Patent Application: US-201113183954-A

Abstract:
a processor comprising : an instruction processing pipeline , configured to receive a sequence of instructions for execution , said sequence comprising at least one instruction including a flow control instruction which terminates the sequence ; a hash generator , configured to generate a hash associated with execution of the sequence of instructions ; a memory configured to securely receive a reference signature corresponding to a hash of a verified corresponding sequence of instructions ; verification logic configured to determine a correspondence between the hash and the reference signature ; and authorization logic configured to selectively produce a signal , in dependence on a degree of correspondence of the hash with the reference signature .

Description:
within a single software execution module ( programs and functions linked statically ), the legal control flow paths can be specified as a series of segments from the each entry point to the module to the next instruction that can change the flow of control , as well as between consecutive instructions that can change the control flow . each segment is essentially a basic block of instructions — with a single entry point and a single exit point . validating the execution of the program module can be done continuously at run time by computing an md - 5 digest ( or another hash function , such as sha - 2 or the proposed sha - 3 ) on instructions executed at the point when the last instruction in the basic block commits . the actual behavior of the branch instructions are also recorded to identify the segment ( that is basic block ) that is entered following a control transfer instruction . these md - 5 digests can be compared at run - time against the corresponding values derived from a reference , validated module . the information for the reference module can be stored in an ( encrypted ) table , called the validation table . fig2 a depicts a simple example , with the basic blocks for a module labeled as a , b , c . d and e . a is the block executed on entry into the module ( which has a single entry point ) and e is the exit block . the directed edges show the control flow paths . we assume that at the end of each basic block , we have conditional branch instructions labeled ba , bb , bc , bd and be , respectively . the lower arrow coming out of each basic block shown in fig2 a corresponds to the branch at the end of the block being taken , while the upper arrow corresponds to the not - taken path . the legal execution paths within this module are shown in fig2 b . the run - time validation of the execution of this module requires the equivalent of the following information to be stored in the validation table : ( i ) the address of the branches that leads into each basic block , ( iii ) the md - 5 digest of all instructions in a basic block , including the branch instruction at the end of each basic block . the validation table has an entry for every instruction that can change the flow of control ( these are conditional branch instructions for the example of fig2 a ). the entry for each such instruction in the validation table needs to store one md - 5 digest for each path that led into the basic block which that instruction terminates . alternative structures for the validation table are also possible , but an analysis of the spec benchmarks showed that this particular format of the validation table is the most efficient one in terms of storage and lookup effort . as a specific example , the vt entry of the branch bd at the end of basic block d needs to store three addresses for the branches bb , bc and bd that lead into the basic block d as well as the md - 5 digest for the basic block d . the validation of the execution of the module proceeds as follows . a running md - 5 digest is generated as every instruction commits . this md - 5 digest is reset at the entry point of the module or when a control flow instruction that terminates a basic block successfully commits . as a result of this scheme , it is difficult , even if the md - 5 digest is imperfect as a cryptographically sound tool , to produce a malicious or modified set of instructions that would generate the same running md - 5 digest as an authentic set of instructions , given all of the other constraints for a useful program . a successful commitment of a branch instruction according to the present scheme refers to a normal commitment , along with the successful validation of the execution thus far . the hardware also maintains a register alct ( address of last control transfer instruction ) containing the address of the last committed control transfer instruction ( or the entry point into the module , if we have entered a module and not yet encountered a branch ). when the control transfer instruction at the end of a basic block is committed , the vt entry for this branch is looked up using the address of the instruction . all branch addresses ( for the predecessor branches or the entry point ) stored in this entry are compared , preferably in parallel , against the value of the alct register . a content - addressable memory architecture may be used to implement this parallel comparison . if the execution was not compromised , exactly one of these addresses stored in the vt will match the value of the alct , validating the control flow path as correct . if no stored address value matches , a situation where execution has been compromised by following a different control flow path has been detected . the next step in the validation process compares the computed md - 5 digest for the block against what is stored in the retrieved vt entry . a match in this case validates that the execution is validated thus far — the control flow path , as well as the instructions in the last executed basic block ( as well as prior ones ) are as expected . when control is transferred from one module to another ( as in a call to a dynamically bound library function or a system call ), an additional validation is needed to ensure that the target module can be legally called by the program . within the functions in the called module , validation of the execution at run - time proceeds as for a single module , similar to the scheme described in example 1 . the control flow signature for a series of instruction can be computed in a variety of ways as described below : 1 . as a hash function of the complete bit patterns that represent individual instructions , such as , but not limited to , an md - 5 digest function , or a cyclic redundancy code ( crc ) function , of these bit patterns . the bit patterns of the instructions can be padded to equalize ( or normalize ) their length , for the purpose of computing their signatures . additionally , some default or pre - assigned initial value can be optionally used as the initial value of the variable used to hold the computed signature . 2 . as a hash function of a subset of each of the complete bit patterns representing individual instructions , such as , but not limited to , an md - 5 digest function or a cyclic redundancy ( crc ) function of these bit patterns . the bit patterns of the instructions can be padded to equalize ( or normalize ) their length for the purpose of computing their signatures . additionally , some default or pre - assigned initial value can be optionally used as the initial value of the variable used to hold the computed signature . 3 . as a hash function that hashes all or parts of the bit patterns representing individual instructions and additional information , such as , but not limited to , the addresses of the individual instructions . as before , the hash function can be a md - 5 digest or a crc function or any appropriate function that generates an unambiguous signature . the control flow signatures can be computed and validated on a per - basic block basis or a cumulative control flow signature maintained as control flows through a series of basic blocks , as the program executes . control flow signatures are computed and verified on a per - basic block basis in this variation , the control flow signatures are computed for the instructions within each individual basic block , and the computed signature for each executed basic block is verified against an expected signature of that basic block . each computed signature thus has no dependency with the signatures of its preceding basic blocks . when the control flow signatures are computed and validated on a per basic block basis , each basic block should be identified uniquely . a unique identifier can be assigned for each basic block in the program by the compiler or any software module that identified each basic block in the program and computes their expected signatures . the unique identifier for a basic block can be either the address of its first instruction or the address of the last instruction in the block , or the address on an instruction within the block that triggers the signature validation process for the entire block . these signatures can be stored in an encrypted form , encrypted using a secret key , as a table , with one entry for each unique basic block . the entries can be identified using the unique identifier for each basic block using some appropriate function known to the art . additionally , hardware artifacts internal to the processor can be used to cache the encrypted or decrypted forms of the basic block signatures . these expected signatures are fetched from the aforementioned memory - resident table , for potential reuse — in validating signatures for recently - executed basic blocks . specific variants are : signatures can be prefetched into a dedicated processor internal structure as the processor prefetches instructions along a predicted control flow path . the processor internal table for caching basic block signatures can be organized as a set - associative structure or in one of the many forms well known to the art . as an alternative to this specialized processor - internal cache for holding the basic block signatures , one can use the existing processor caches . it is also possible to use the specialized processor - internal signature cache along with the normal processor caches . in this variation , the control flow signatures are computed and accumulated into a single variable as control flows through each basic block in the course of executing a program . the control flow signature , at any point in this case , is thus a function of the control flow path across all of the basic blocks encountered thus far at this point . the control flow signature expected at the end of a basic block , say , b is a function of the control flow signature computed at the point of exit from each of its preceding basic blocks that leads into b . if there are n such preceding basic blocks , the expected control flow signatures at the end of the basic block b should have n different values and one of these should match the computed control flow signature . as in the case of variation 1 , similar hardware structures can be used to hold the expected signature . however , instead of one expected signature per control flow instruction at the end of a basic block ( as we have in variation 1 ), we need to have an efficient way of storing the multiple expected signatures . there are several ways to do this , and such techniques are generally known to those proficient in the art . for example : store the signature in a hash table , indexed by the address of the control flow instruction at the end of a basic block , and use a linked list and / or an array to hold the multiple expected signatures (“ hash bucket ”), starting with the location identified using the hash value computed . the hash function can accept several inputs to compute an index into the hash table : a ) all or some of the bits in the address of the control instruction . b ) all or some of the bits in the address of the control instruction , combined with information that indicates the outcome of the immediately preceding one or more control flow instruction ( s ). c ) all or some of the bits in the computed control flow signature . d ) all or some of the bits in the computed control flow signature , combined with information that indicates the outcome of the immediately - preceding one or more control flow instruction ( s ). e ) a suitable combination of bits from the computed control flow signature , and the address of the control flow instruction . f ) a suitable combination of bits from the computed control flow signature , and the address of the control flow instruction , combined with information that indicates the outcome of the immediately preceding one or more control flow instruction ( s ). as in variation 1 , dedicated structures or caches can be used to hold the expected signatures within the processor for fast validation of the control flow signatures . an additional structure can be used to speed up the access to the stored expected signatures within the main memory . the various artifacts mentioned above can be implemented outside the cpu core as well . the expected signatures can be decrypted using a secret key ( stored in a secure storage ) as they are fetched from memory or they can be decrypted when one needs to compare them against a generated control flow signature . the storage for this secret key can be implemented , for example , using the tpm mechanism . the control flow signatures are computed as the program executes and when a control instruction at the end of a basic block commits , the computed instruction is compared against an expected signature stored within the hardware artifacts , according to the variations mentioned above . if a computed signature does not match the expected signature , normal instruction processing steps are suspended and appropriate actions are taken . these actions include , but are not limited to : generation of an interrupt to invoke an appropriate handler that suspends further execution of the program and restores the system to a known stable state ( or a previous checkpoint ); and transparently logging execution details into a secure log area on detecting the first mismatch , without any updates to the architectural state of the processor / system . although specific embodiments have been illustrated and described herein , it will be appreciated by those of ordinary skill in the art that any arrangement that achieve the same purpose , structure , or function may be substituted for the specific embodiments shown . this application is intended to cover any adaptations or variations of the example embodiments of the invention described herein . it is intended that this invention be limited only by the claims , and the full scope of equivalents thereof . fig3 depicts the generic structure of a pipeline that includes an embodiment of the invention . the reference signatures of each basic block in the program are pre - computed and stored in an encrypted form in memory . as a program is processed by the pipeline , the instructions invoked in the program are fetched from the memory hierarchy in the usual manner , going through one or more levels of caches . the fetched instructions are processed in the usual way by the pipeline and are simultaneously fed into a signature generator ( sg ) that generates a signature for each basic block of instructions encountered along the path of fetched instructions . as the instruction terminating a basic block is to be committed , the signature generated for the basic block is compared against a reference signature for the same basic block , as stored in an on - chip signature cache ( sc ). if a reference signature for the basic block is available in the signature cache , it is compared against the signature generated by sg as the last instruction in the basic block is being committed . the authentication succeeds if the generated signature of the basic block , as generated by the sg , matches the signature stored in the signature cache . on a mismatch , the authentication is unsuccessful and corrective actions are taken . if the reference signature is not available in the signature cache , instruction commitment is stalled pending the fetching of a reference signature for the basic block into the signature cache . the location of the encrypted reference signature of the basic block in the memory is computed . this computation is performed by a separate logic ( not shown ) and can generate the address of the encrypted reference signature of the basic block based on the address of either the first or the last instruction in a basic block . using the address of the encrypted reference signature for the basic block , the encrypted reference signature for the basic block is fetched from the memory hierarchy , decrypted using on - chip decryption logic as shown in the figure and installed into the signature cache after decryption . if instruction commitment was stalled pending the availability of a reference signature in the signature cache sc , instruction commitment commences after a successful authentication , following the installation of the reference signature from the memory hierarchy . the processing logic associated with the authentication logic or the signature cache itself can generate signals that indicate whether the reference signature is available in the sc , whether a fetch of the reference signature into the sc is pending and if the authentication check has been successful or not . these signals are used the pipeline control logic . the processing pipeline may also be augmented by additional pipeline stages in the figure to accommodate any delay in the authentication process ( such as the stage shown as ck ) or to buffer instructions from the basic block till the authentication of a basic block succeeds ( such as the stages shown as l1 and l2 ). in alternative embodiments , encrypted reference signatures can be fetched into the sc based on instruction pre - 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