Patent Application: US-68576307-A

Abstract:
reconfigurable computers can leverage the synergism between conventional processors and fpgas by combining the flexibility of traditional microprocessors with the parallelism of hardware and reconfigurability of fpgas . multiple challenges must be resolved to develop efficient and viable solutions of reconfigurable computing applications . this paper has developed virtual configuration management techniques for discovering and exploiting spatial and temporal processing locality at run - time for rcs . the developed techniques extend cache and memory management techniques to reconfigurable platforms and augmented them with other concepts such as data mining using association rule mining . we have demonstrated the applicability and the effectiveness of the proposed concepts by applying them to representative image processing applications . simulations , as well as emulation using the cray xd1 reconfigurable high - performance computer were used for the experimental study . the results show a significant improvement in performance using the proposed techniques . this improvement can be assessed by computing the speedup . this speedup shows that the proposed segmentation technique is almost twice as fast as the function - by - function scenario and more than three times faster than the full reconfiguration scenario depending on the working conditions . the physical restrictions on pages size have been overcome by using segmentation . segmentation achieved better performance than paging by a factor of 30 %. preliminary studies of the concept of dual - track execution have been investigated . the results have shown modest improvement of about 29 %. future work will include investigating more sophisticated dual track execution policies that may even be targeted to produce even better performance .

Description:
partial run - time reconfiguration ( prtr ) is considered in this work . in this scenario , the application is divided into a set of independent modules that need not to operate concurrently . each module is implemented as a distinct configuration ( function ) which can be downloaded into the fpga as necessary at run - time during application execution . modules can be dynamically uploaded and deleted from the fpga chip without affecting other running modules . developing applications for prtr requires both hardware and software programming . the application is written in a sequential high level language like c with calls to some hw functions ( modules ) from a predefined domain - specific hardware library . this maintains a familiar view seen by application scientists and programmers of conventional computers and reduces the development life - cycle of reconfigurable applications . at the reconfigurable hardware level , the hw functions library can be developed using a hardware description language . this library contains the fine - grain processing basic building blocks ( e . g . fft , edge detection , and / or wavelet decomposition ) independent of the applications . applications only deal with the application program interface ( api ) for the library . segmentation refers to the grouping of configurations ( functions ) into variable size segments . segmentation is intended to exploit spatial processing locality and segment replacement is to exploit temporal locality . a segment is defined as a set of hardware functions to be placed at the same time on the device . segmentation exploits spatial processing locality by arranging related hw functions into blocks . spatial processing locality would arise from functions that are typically used together in a given application . for example , morphological operators such as opening and closing in image processing , and convolution and decimation in discrete wavelet decomposition can be grouped together as one block . data mining techniques , such as association rule mining ( arm ), are used to derive meaningful rules that can be useful for creating the blocks . these rules are used to determine the degree of correlation between the reconfigurable functions in order to group the highly related functions together into one block . at run - time , when the application requests any hw function , the system configures the entire segment . by configuring the entire segment , the system pre - fetches other functions that exist in the same block . when the application requests another function from the same block , which is likely , the system starts executing it directly without the need to configure a new bitstream . the segment size is not constrained , and it can be placed at any arbitrary empty location on the fpga , unlike paging . in the paging scenario , the fpga chip is divided into n fixed - size contiguous partitions ( pages ). a single block at any given point of time can be placed in any partition . the page size should be lager than or equal to the largest function size . however , blocks are constrained by the page size . association rule mining ( arm ) is an advanced data mining technique that is useful in deriving meaningful rules from a given data set [ 7 ]. it is frequently used in areas such as databases and data warehouses . given a number of transactions of item sets , association rule discovery finds the set of all subsets of items that frequently occur in many database records or transactions , and extracts the rules telling us how a subset of items correlates to the presence of another subset . one example is the discovery of items that sell together in a supermarket . a management decision based on such findings could be to shelve these items close to one another . there are two important basic measures for association rules , support and confidence . since the database is large and users are concerned about only those frequently purchased items , usually thresholds of support and confidence are pre - defined by users to drop those rules that are not as interesting or useful . the a priori algorithm is an efficient association rule mining algorithm , developed by agrawal et al , for finding all association rules [ 7 ]. the principle of this algorithm is that any subset of a frequent item set must be frequent . the first step of the algorithm is to discover all frequent items that have support above the minimum support required . the second step is to use the set of frequent items to generate the association rules that have high enough confidence . fig2 shows an example of a database with 4 transactions , and it is required to find all rules with minimum support of 50 %. a segment is defined as a set of hardware functions to be placed at the same time on the device . these functions are highly correlated to each other . to create the segments , off - line software profiling of realistic executions is used to determine typical processing needs . each application is considered as one transaction , and the executed hardware functions in that application are considered as the items . the profiler stores the transactions and their items in a table called transaction table . the a priori algorithm is executed off - line on the transaction table with a specified support and confidence . it generates a small table that has the necessary information ( all rules between hardware functions ) for the block generation . the algorithm generates a set of segments and a hash table to be used at run - time . in other words , when the system needs to execute a function that does not already exist on the fpga chip ; it uses the hash table to select the suitable segment and then upload it to the fpga . hashing is a process where data items are stored in a hash table data structure . the hash table is used to map the requested function to a certain block . assuming that we have a hardware library of n functions ; we define a hash matrix as a three - dimensional array . each dimension has a length n . a hash function maps a key to the entry in the hash table that holds the data item referenced to by the key as shown in fig3 . the hash function takes the index of the most recently three hardware functions as input and returns the block that has highly related functions to these three functions . system can find the suitable block in a constant time o ( 1 ). retrieving the suitable block takes one line of code : where a , b , c are the indexes of three hardware functions . fig4 shows a 3d hash table example . for each entry of the hash table , the algorithm reads the three corresponding functions ( one function for each index of the hash table ), generates a new empty block , and inserts the first function into this block . then , it adds the new block to the blocks table , and points the corresponding hash table entry to this block . after that , it searches for rules that contain either three , first and second , or only the first of these functions , preserving this search sequence , and adds other functions that appear in the retrieved rules to the new block . the algorithm stops adding functions to the block when the rules confidence reaches a minimum threshold . the confidence threshold value is pre - selected . to illustrate the segmentation mechanism , we consider an image processing hardware library that has 10 functions as shown in table 1 , and four applications written in a sequential high level language with calls to some hw functions from the library . the four applications are image convolution , image registration using exhaustive search , wavelet - based image registration , and hyperspectral dimension reduction . table 2 shows the transaction table generated by profiling these applications . table 3 shows the generated rules after applying arm algorithms to the transaction table . each row shows the related functions and the confidence of this relation . fig5 shows the contents of both the blocks table and the hash table during the blocks creation process . initially both tables are empty . after loop starts , it reads the first three functions which correspond to the fft function . the algorithm creates a new block ( blk 1 ), inserts fft into this block , and points the entry ( 0 , 0 , 0 ) of the hash table to blk 1 . then , it searches the rules table for rules that have fft and its confidence is greater than or equal 25 % ( assuming that the confidence threshold is 25 %). rules 3 , 4 , and 12 satisfy the constraints . the algorithm adds other functions in these rules to blk 1 . the mat_mul and ifft functions are added to blk 1 as shown in fig5 ( a ). in the 2nd loop iteration ; the algorithm reads ifft , and fft . the algorithm creates a new block ( blk 2 ), inserts ifft into this block , and points the entry ( 1 , 0 , 0 ) of the hash table to blk 2 . then , it searches the rules table for rules that have both ifft , and fft and confidence greater than or equal 25 %. rules 4 , and 12 satisfy the constraints . the algorithm adds other functions in these rules to blk 2 if the block can accommodate them . the function mat_mul is added to blk 2 as shown in fig5 ( b ). the algorithm continues iterating till it completes filling the hash table . all grouped functions ( segments ) in the hash table are then compiled into final usable binary bitstream files . a middleware referred to as the run - time reconfiguration manager ( rtrm ) is used to integrate all of the concepts . the rtrm is responsible for receiving the incoming functions ( hw function calls ) and making the reconfiguration and scheduling decisions . fig6 shows a simplified flow chart of rtrm algorithm . upon receiving a request for a hw function from an application , the system checks whether this function already exists on the chip . when the function does exist and is not executing a function the system starts executing this particular function . if the function in not present on the fpga or it is currently executing a function , the system faces a function fault . in this case , the system uses the requested function and the two previous executed functions from the same application as indexes to the hash table and retrieves the suitable segment . this segment has the group of functions that most likely appear with this sequence of functions . after that , the system has to choose a block ( victim segment ) to be removed from the fpga to make room for the block that has to be brought in . while it would be possible , using page replacement algorithms , to pick a random segment to evict at each segment fault , the overall system performance is much enhanced if a segment that is not heavily used is chosen . if a heavily used segment is removed , it will probably have to be brought back in quickly , resulting in extra overhead ( re - configuration time ). the rtrm as suggested by most of the page replacement algorithms try to predict which segment will be referenced aftermost in future . the knowledge of past and / or the present behavior of the program is used to choose the victim segment . after choosing the victim segment , those algorithms dictate that the system configures this segment with the new block and starts executing the function . if all of the current uploaded blocks are currently executing other functions , the system adds the requested function to the function queue and waits for any function to finish its execution . the use of both reconfigurable computing and conventional microprocessor resources could be adapted at run - time to achieve the best possible performance . one aspect of this adaptability is to allow the conventional processor to elect at run - time to perform some of the functions that are intended for execution on the reconfigurable engine , which can enhance the overall performance . two dual - track techniques have been implemented technique with lru . the 1st technique removes the functions queue from the system , and starts executing any requested function on the micro processor directly if the fpga is not ready . fpga is not ready , if the requested function does not already exist ( configured ) on the fpga , or if the function is configured but another application is using it . the 2nd technique keeps the functions queue and starts executing the requesting function on the microprocessor if the fpga is not ready . at the same time it adds the requested function to the function queue . later , when the fpga becomes ready , the system checks the remaining time to finish executing the function on the microprocessor and compares it with the execution time on fpga plus the reconfiguration time , if reconfiguration is needed . the system then decides to continue executing on microprocessor or terminating it and starts executing on the fpga . this technique is called look - aside . fig7 , 8 show simplified flow charts of dual track algorithms . the experimental verification of the proposed approaches has been performed by first implementing an image processing library . this hardware library has been realized for xilinx virtex - ii device . each function in the library operates at an execution rate of 100 mhz . table 1 lists some of the implemented library functions . in addition , we have implemented some of the image processing applications for rcs using this library . to support dual track execution , we have also implemented the library in software . higher performance , in case of rc implementation , compared to xeon 2 . 8 ghz implementation has been achieved [ 9 , 10 , 11 ]. table 4 lists the implemented applications and their performance . simulation and emulation , using the cray xd1 reconfigurable high - performance computer , were used to verify our algorithms . the cray xd1 machine [ 12 , 13 ] is a multi - chassis system . each chassis contains up to six nodes ( blades ). each blade consists of two 64 - bit amd opteron processors at 2 . 2 ghz , one rapid array processor ( rap ) that handles the communication , an optional second rap , and an optional application accelerator processor ( aap ). data from one opteron is moved to the rap via a hyper transport link . the aap consists of a single xilinx virtex - ii pro xc2vp50 - 7 fpga with a local memory of 16 mb qdr - ii sram . the application acceleration subsystem acts as a coprocessor to the amd opteron processors , handling the computationally intensive and highly repetitive algorithms that can be significantly accelerated through parallel execution . in order to use the fpga , the developer needs to produce the binary file that encodes the required hardware design , the binary bitstream file , using standard fpga development tools . cray provides templates in vhdl that allow fast generation of bitstreams . it also provides cores that interface the user logic to the cray xd1 system . the proposed system assumes the fpgas permit partial reconfiguration . although recent generations of fpgas support partial reconfiguration , most rcs vendors allow only full fpga reconfiguration . this is the case on the used test bed , the cray xd1 . in order to overcome this problem , we have implemented an emulation model on cray - xd1 machine . the cray - xd1 has six compute nodes , and each node has an fpga . we considered the six fpgas as one fpga device , and each fpga can hold one block ( page or segment ) as shown in fig9 . this allows us to emulate partial reconfiguration , where we can reconfigure one fpga ( block ) while other fpgas ( blocks ) are executing other functions . we have removed all mpi communication overheads from the measured performance . a random job ( application ) generator was implemented to fire jobs to the rtrm and applications arrival was poisson distributed . it randomly ( uniformly ) selects an image processing application from the applications list and inserts a delay ( poisson ) before the next arrival . each application requires on the average a few hardware functions . the average execution time for each hardware function is 7 ms . we have measured the average speedup against classical hardware implementation function - by - function basis without caching . throughput , mean response time , turn - around time , and average hit rate have been reported . six replacement techniques for blocks replacement have been implemented . these techniques are , random , first in first out ( fifo ), the least recently used ( lru ), second - chance ( clock ), not recently used ( nru ), and the optimal algorithms . the random job generator fires 400 applications from our image processing applications list . the average application length is 4 functions . the average function execution time is 7 ms . the average function size is 15 % of the fpga chip area . the average submission delay is 4 ms . fig1 ( a ) shows the speedup gained using paging compared to the full - reconfiguration hardware implementation for different number of pages and different replacement techniques . a maximum speedup of 2 . 8 × have been achieved . the results show that the best performance can be achieved when the page size is one third of the chip size . when the number of pages is small , we have larger page sizes that can accommodate more functions . in this case , the system exploits only spatial locality and can suffer high configuration penalty . this explains the lower performance when the number of pages is 1 . on the other hand when the number of pages is large , the page sizes are small , and cannot accommodate a reasonable number of functions . this explains the drop in performance after the peak . in this case , the system exploits only the temporal locality . the best performance can be observed in the middle of curve when the number of pages is chosen such that they allow a decent number of functions . in this case , the system can take advantage of both temporal and spatial locality at a low configuration penalty cost . this behavior depends on the fpga size , hardware functions size , average function execution time , and functions arrival rate . such parameters can be obtained from offline workload characterization and improved from dynamic system profiling . fig1 ( b ) shows the average hit rate versus the number of pages . the hit rate can be defined as the ratio of finding the requested function on the fpga to the total number of requests . hit rate depends strongly on the grouping algorithm . if the grouping algorithm managed to group the highly correlated functions in the same group , this will improve the hit rate . results show that the best hit rate ( 98 %) can be achieved when the number of pages is one , fig1 ( b ), although this does not produce the best performance , fig1 ( a ). this is because the page size is large and the miss penalty ( configuration time ) is high with big size pages . in both figures , random replacement technique gives poor performance as compared to lru . fifo removes the oldest page which might still be in use . lru achieves the best performance as expected . it removes the pages that have been unused for the longest time . the same set of experiments has been repeated with the same operating conditions and assumptions for the segmentation approach . fig1 ( a ) shows the speedup of segmentation compared to the full - reconfiguration scenario , given different confidence threshold levels . when the confidence threshold is very small , the result is equivalent to paging with one page . in this case , the system exploits spatial locality only . when the confidence is very high , it is difficult to find many functions to group . thus , the segments become very small , and the system will exploit temporal locality only . the middle case can be observed when the segment size allows for the accommodation of decent number of functions . in this case , the system can take advantage of both temporal and spatial locality . fig1 ( b ) shows the speedup of segmentation compared to function - by - function scenario . the curve behaves similar to fig1 ( a ) for the same reasons . in this case , segmentation has achieved a maximum speedup of 2 . 95 × compared to the full chip reconfiguration scenario , and a speedup of 1 . 8 × compared to the function - by - function implementation scenario . fig1 ( c , d , e ) show the throughput , the mean response time and the average turn - around time of the application versus the number of pages on the fpga . the throughput , mean response time , and the average turn - around time of the same experiment using the function - by - function technique are 4 applications / sec , 28 . 5 sec , and 28 . 7 sec respectively . fig1 ( f ) shows the average hit rate . a maximum of 98 % of the configuration latency overhead has been eliminated . results show that the best hit rate can be achieved with small confidence threshold , although this does not produce the best performance . this is because the segments size is large and the miss penalty ( configuration time ) is high with small confidence , while the segment size is small and miss penalty is low with high confidence . fig1 shows the speedup obtained by using dual - track execution paradigm . the first technique , with no functions queue , is not performing well , whiles the second technique , look - ahead , and improves the performance slightly . this shows that it is not always better to execute on microprocessor when the fpga is not ready . if the fpga is not ready , two types of overheads may be introduced . the reconfiguration overhead and the scheduling delay overhead . sometimes it is better to wait to reconfigure the chip than start executing on the microprocessor . if the chip has no space to configure the new function , and we have to wait long time till other functions end , it might be better to start executing on the micro processor . the first technique is not performing well because it execute on microprocessor when the fpga is not ready . second technique tries do decide between executing on fpga or microprocessor depending on which one will finish earlier . this gives us better results . in order to study the effect of the function size and submission delay on performance , a simulation model has been implemented and the experiments have been repeated with different function sizes and different submission delays . fig1 shows the speedup vs . the average applications submission delay for paging , segmentation , and dual - track cases . in this experiment , the fpga chip was divided into 3 pages , and the average task size was 15 % of the chip size . this shows that the performance improves when the system submits applications faster . when submission delay becomes slower , the system waits for new submission . in this case , the system is not benefiting from caching or parallelism and the performance will be similar to the function - by - function case . thus , the speedup saturates also at 1 . fig1 shows the speedup vs . the function size ratio ( avg . function size / chip size ) for the same three cases ( paging , segmentation , segmentation with dual - track ). the experiment has been repeated for the paging case with different page size . this shows that the performance improves when the function size is getting smaller , where pages / segments can accommodate more functions and more parallelism can be exploited . if the function size becomes larger than the page size , the system cannot create page that can accommodate the function , and the application cannot run . thus , paging algorithm with fixed size page can not work well with all functions size . segmentation does not have this problem as the segment size can grow up to the chip size . results show that segmentation performs better than the best paging in all cases by a factor of 30 %. segmentation with dual track execution paradigm improves the performance by another 29 %. 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[ 11 ] m . taher , e . el - araby , t . el - ghazawi , k . gaj , “ image processing library for reconfigurable computers ”, acm / sigda thirteenth international symposium on field programmable gate arrays ( fpga 2005 ), monterey , calif ., usa , february , 2005 ( poster presentation ). van der steen , aad j . and jack dongarra , “ overview of recent supercomputers ,” 2004 . the above references are incorporated by reference herein in their entirety . it will be clear to a person of ordinary skill in the art that the above embodiments may be altered or that insubstantial changes may be made without departing from the scope of the invention . accordingly , the scope of the invention is determined by the scope of the written description herein , including descriptions of systems , computer architectures , methods , computer readable media associated therewith , as well as the following claims and their equitable equivalents .