Patent Application: US-201514885462-A

Abstract:
an analog implementation is proposed of an adaptive signal processing model of a kind requiring a plurality of randomly - set variables . in particular , following a digital to analog conversion of a digital input signal , analog processing is used to transform the data input to the model into data which is subsequently processed by an adaptively - created layer of the model . in the analog processing , multiplication operations involving the randomly - set variables are performed by analog circuitry in which the randomly - set variables are the consequence of inherent tolerances in electrical components . this eliminates the need for the randomly - set variables to be implemented in some other way , for example as random variables stored in memory .

Description:
referring to fig2 , a first embodiment of the invention is illustrated . a micro - electrode array ( mea ) 1 has been implanted into the brain of a subject . the mea includes : a unit 2 comprising electrodes for recording of neural signals ; a transmitting / receiving ( tx / rx ) unit 3 for transmitting the neural recordings out of the subject ( and optionally receiving control signals and / or power ); and a power management unit 4 for controlling the units 2 , 3 . the subject also wears a portable external device ( ped ) 5 comprising : a tx / rx unit 6 for receiving the neural recordings from the unit 3 of the mea 1 ; a microcontroller unit ( mcu ) 7 for pre - processing them , and a machine learning co - processor ( mlcp ) 8 for processing them as described below . the control output of the mlcp 8 is transmitted by the unit 6 to control a prosthesis 9 . in a second embodiment of the invention , the mlcp 8 is located not in the ped 5 but in the implanted mea 1 this dramatically reduces the data which the unit 3 has to transmit out of the subject , and thus dramatically reduces the power which has to be provided by the power management unit 4 . as described below , certain embodiments of the invention are integrated circuits which are suitable for use as the mlcp in such a scenario . turning to fig3 , a network architecture is shown of a two - layer neural network which can be used by the mlcp 8 , in an adaptive model known as the elm algorithm . the network includes d input neurons with associated values x 1 , x 2 , . . . , x d , which can also be denoted as a vector x with d components . thus , d is the dimension of the input to the network . the outputs of these d input neurons are input to a hidden layer of l hidden neurons having an activation function g : r → r . [ 4 ] without loss of generality , we consider a scalar output in this case . the output o of the network is given by : note that in a variation of the embodiment , there are multiple outputs , each having an output which is a scalar product of { h i } with a respective vector of l weights β i . in general , a sigmoidal form of g ( ) is assumed though other functions have also been used . compared to traditional back propagation learning rule that modifies all the weights , in elm w i and b i are set to random values and only the output weights , β i need to be tuned based on the desired output of n items of training data t =[ t 1 . . . , tn , . . . t n ], where t n is the desired output for n - th input vector x n . therefore , the hidden - layer output matrix h is actually unchanged after initialization of the input weights , reducing the training of this single hidden layer feed - forward neural network into a linear optimization problem of finding a least - square solution of β for hβ = t , where β is output weights and t is the target of the training . the desired output weights , { circumflex over ( β )} are then the solution of the following optimization problem : ( 2 ) where β =[ β 1 . . . β l ] and t =[ t 1 . . . t n ]. the elm algorithm proves that the optimal solution { circumflex over ( β )} is given by { circumflex over ( β )}= h † t where h † denotes the moore penrose generalized inverse of a matrix . the simple training algorithm brings advantages such as fast training speed and better generalization . more importantly for this invention , the reduction of the number of parameters that need to be tuned enables a simple hardware implementation . the output weights can be implemented using digital circuits , facilitating tuning . the fixed random input weights , however , can be realized by exploiting transistor mismatch which already commonly exists and becomes even profounder in the scaling of a modern deep sub - micrometer cmos process . a microchip suitable for use in the invention is described in a later section to elaborate this point . the architecture of the proposed classifier of the mlcp 8 that exploits the d × l random weights of the input layer is shown in fig4 . a decoder 10 receives the neural recordings and separates it into d data signals indicative of different sensors . the bootstrap and 50 nagen are for generating the reference current used in the dacs of the ihc . the processing portion of the classifier has 3 parts —( a ) input handling circuits ( ihc ) to convert digital input to analog current , ( b ) a current mirror synapse array 11 for multiplication of the d input currents with random weights and sum up the results along the columns of the array and ( c ) l current controlled oscillator ( cco ) neuron based adcs . the second layer of the network is performed digitally on the output of the ccos by the mcu 7 in fig2 . typically , the determination of output weights is done offline and the learnt weights are downloaded to the mcu 7 . the mcu 7 performs multiplications using these pre - determined weights as one input and the output of the ccos as the second input . fig5 shows the structure of two adjacent ihc units . serial input data is decoded by the decoder 10 , and a respective signal is transmitted to each ihc . the ihc can handle the input in three different ways as shown by the three dotted paths in fig5 . first , if the input is directly a binary encoded data , it can take the top path and be sent directly to a register for an n - bit dac . we choose a current splitting dac for its compact size [ 18 ]. for most machine learning examples , we have found 10 bits to be sufficient . these 10 - bit dacs will split a fixed current ( which can be selected based on a 5 bit master splitter with a maximum value of 50 na ) according to the input data value . second , for pfe data , it can follow either the middle dotted path , or the lowermost dotted path . which path is taken depends on a 1 - bit control signal — s ext . first , a counter is used to count the number of pulses in the pfe signal in a fixed time window . a moving average of this count is calculated using a sliding window and the final moving average is input to the dac for this channel . for neural decoding application , we have used a 6 - bit dac and 20 ms moving window . the input samples for the neural signal decoder are spike sequences from the neural recording channels . the positive pulses in the sequence indicate the timing of spike firing of one or a few neurons around the electrodes . the ihc is therefore needed to convert the spike sequences into input features that can be processed by following circuits . the function of the ihc in this case is to count the number of spikes in a moving window with a time step of t s , and a window length of 5 × t s , where t s is determined by input clock t in . the entire decoder is therefore a discrete time system with sampling period of t s . the 4 - bit input counter and registers are all driven by input clock t in . the results of counting in the window of t s are stored in sequence in 6 4 - bit registers that connected in series . at every time step , a 6 - bit full adder and a 6 - bit full subtractor performs q n = q n - 1 + c n - 1 − c n - 8 when s ext = 0 , equivalently counting number of spikes in a moving window with length of 5 × t s . the q n is then stored in a 6 - bit register and is used as the input of a 6 - bit current - mode digital - to - analog converter ( dac ), the output current of which is used as input feature of the neural network based on the extreme learning machine . also , the counters are kept as 4 - bit for a maximum input frequency of 800 hz which is more than sufficient for neural decoding . it can be modified according to application needs and does not hurt the generality of the architecture . lastly , for time series data , by setting s ext = 1 , a delayed version of the count signal of the m - th channel can be sent to the dac of the succeeding or ( m + 1 )- th channel ( i . e . the lowermost dotted path in fig5 ). the desired delay can be chosen from 5 options between 20 - 100 ms using a 3 - bit digital selection . this data can be further delayed and fed to the ( m + 2 )- th channel and this daisy chain can be selected as desired based on the setting of s ext per channel . in this case , if there was data meant for the ( m + 1 )- th or ( m + 2 )- th channel , they can be sent to the next free channel by changing the setting of the decoder . thus the dimension of input to elm can be artificially increased by adding delayed samples . though we show this only for the count signal , a binary encoded time series data may also be handled in this way by feeding it into the 4 - bit register after the counter . as illustrated in fig5 , the same embodiment may be operative to handle both binary encoded data and pfe data by appropriate switching . however , in other embodiments , the ihc is operative only to handle one of these two sorts of data , and is used only for in data of the appropriate sort . the random input weights are realized by a current mirror matrix . the analog current from ihc is copied over to every neuron using current mirror based analog synapses . in each row , the gates of the transistors are all connected to the diode - connected nfet that sinks the input current . and in each column , the drains of the transistors are connected to the input of the hidden - layer neuron of the column , so that the input current of each row is mirrored into the hidden - layer neuron . the summation of weighted input features is automatically done due to the current - mode operation . minimum sized transistors are employed in these current mirrors to exploit vlsi mismatch which is necessary for the generation of random input weights w i and bias b i of elm . for example , in the i - th input channel , output of the dac is assumed to be while the total input current of neuron j is given by i in , i w 0 e δvt , ij / ut where ut is the thermal voltage , w 0 is the nominal current mirror gain while δvt , ij denotes the mismatch of the threshold voltage for the transistor copying the i - th input current to the j - th neuron . this last term is a random variable with a gaussian distribution and hence the input weights w get mapped to random variables with a log - normal distribution . in this ic , d = l = 128 , i . e . we can have a maximum of 128 input dimensional data as well as a maximum of 128 hidden layer neurons . there is a provision for turning off unused input channels and hidden neurons to avoid wastage of power . the output current from the synapses are the input to the neuronal current controlled oscillator ( cco ) [ 19 ] shown in fig6 . the neuron has to provide a saturating , monotonically increasing transfer function between input current and output frequency . the output counter counts the number of firing of the cco - neuron in a certain time window . combining these two blocks , the hidden - layer neuron convert the input current randomly projected by input weights into spike numbers , which is transmitted out of the microchip for further processing . 2 digital bits are kept to choose 4 values for each of the capacitors . the saturation of the output value is also digitally selected by stopping the counter once it reaches the pre - set saturation value . the saturation count can be programmed in the range of 2 6 to 2 13 . another nonlinearity can be introduced through the leak current from transistor m 1 that creates a threshold offset in the neuron transfer curve . the spiking neuron outputs can be used to clock a counter and thus in a certain sampling time t s , if each neuron i spikes h i times , the counter outputs will be a quantized version of neuron output frequency . as noted above , a digital controller in the form of the mcu 7 can then perform the computation in second stage to produce o = σ 1 β 1 h i , a close approximation of o in equation ( 1 ). the digital controller will also reset the neuron and the counter every cycle making this architecture a locally asynchronous globally synchronous ( lags ) one . fig7 shows the measured transfer functions of the 128 neurons where only one row of synapses are used to provide the input current . the mismatch in the transfer curves is due to both the synaptic and neuronal mismatches . the statistical variation in the 128 × 128 synapse array is shown in fig8 ( a ) by plotting the counter output when the input is a fixed digital code . the same data is plotted in fig8 ( b ) as a histogram to show the probability distribution of weight is log - normal as expected from theory . the hardware implementation of elm for binary encoded digital input has been verified in applications of regression and classification . for the regression task , the network was given a set of noisy samples and had to approximate the underlying function . as shown in fig9 , the proposed method could achieve a regression accuracy of about 98 % which is at par with software implementations [ 20 ]. the classification performance has been verified on several datasets from the uci machine learning repository [ 21 ]. the classification problems can be divided into several categories based on input dimension and size of training data set : small size and low dimensions ( pima indians diabetes , statlog australian credit ), small size and high dimensions ( leukemia data set ), large size and low dimensions ( star / galaxy - bright data set ), large size and high dimensions ( adult data set ). these categories are shown in the first column of table i . in the table , the second column shows the number of features in these data sets , or the dimension of the input data ( corresponding to the number of input channels used ). the third and fourth columns show the size of training data and testing data . the fifth column illustrates the classification performance , or mis - classification rate of the software elm system with ideal sigmoid function as the hidden layer neuron . the last two columns are the performance of the system when we implement silicon cco neuron in the hidden layer . from this table , we could see the device measurement results are quite similar to the simulation one , as well as the software elm with sigmoid function . we can also use the same chip to classify inputs with dimensions higher than 128 — for such cases , the input data has to be divided into sub - parts and the chip has to be reused to produce the results separately for each part before combining it back . the algorithm and microchip for the neural signal decoding are verified by dexterous finger movement classification using data recorded from monkey cortex . in the experiment described in detail by a . poliakov and m . schieber [ 22 ], the monkey is trained to perform tasks of flexing or extension of the fingers and the wrist of right hand according to the clues given . in the meanwhile , the neural signal of from the m 1 region of monkey brain is recorded by the implanted mea . thus , the samples with input spike sequences and the correct movement are given for the training and testing of the neural signal decoding algorithm and microchip in the invention . the training accuracy after training is around 96 . 7 %. the decoding accuracy in the operational phase is 95 . 0 %. this verification is done in the case where number of input channels is 40 and number of output channels is 60 . the power consumption of the microchip is determined by the number of input channels and the number of hidden - layer neurons used . the decrease of the dimension , either of inputs or of outputs would lead to a reduction of the power consumption . it , however , will also cause the decrease of the classification accuracy . a trade - off between accuracy and power consumption is involved here , requiring optimization according to the requirement of the system in which the decoding microchip is used . the fig1 shows how the classification accuracy changes with input feature dimension in ( a ) and the number of hidden - layer neurons in ( b ). finally , the system measurement result is shown in fig1 comparing classification accuracy of decoding with and without input dimension increase by inducing delayed spike sequences . the cortex data is the same as mentioned above . the lines in the fig1 show the decoding accuracy as the input dimension increases in both cases of with and without input dimension increase by delay . furthermore , as shown in fig1 , the decoding accuracy with input dimension increase is higher than the one without input dimension increase , and reaches a saturation of decoding accuracy earlier . fig1 ( a ) is a die photo of a 4 . 95 mm × 4 . 95 mm mlcp in 0 . 35 μm cmos implementation which is an embodiment of the invention supporting both d and l up to 128 . a summary of its specifications is given in fig1 ( b ) . according to measurements , the power dissipation of the elm in a neural decoding problem was 0 . 4 μw at a 50 hz classification rate . this resulted in an energy efficiency of 290gmacs / w where mac stands for a multiply - and - accumulate operation . a machine learning system which is an embodiment of the present invention can be used in any application requiring data based decision making in low - power . we have already shown the example of neural signal decoding in bmi . here , we outline several other possible use cases : there has been a huge increase in wearable devices that monitor ecg / ekg / blood pressure / glucose level etc . in a bid to promote healthy and affordable life styles . typically , these devices operate under a limited energy budget with the biggest energy hog being the wireless transmitter . an embodiment of the invention may either eliminate the need for such transmission or drastically reduces the data rate of transmission . as an example of a wearable device , consider a wireless eeg monitor that is worn by epileptic patients to monitor and detect the onset of a seizure . an embodiment of the invention may cut down on wireless transmission by directly detecting seizure onset in the wearable device and triggering a remedial stimulation or alerting a caregiver . in the realm of implantable devices , we can take the example of a cortical prosthetic aimed at restoring motor function in paralyzed patients or amputees . the amount of power available to such devices is very less and unreliable — being able to decode the motor intentions within the body in a micropower budget enable drastic reduction in data to be transmitted out . wireless sensor nodes are used to monitor structural health of buildings and bridges or for collecting data for weather prediction or even in smart homes to intelligently control air conditioning . in all such cases , being able to take decisions on the sensor node through intelligent machine learning will enable long life time of the sensors without requiring a change of batteries . in fact , the power dissipation of the node can reduce sufficiently for energy harvesting to be a viable option . this is also facilitated by the fact that the weights are stored in a non - volatile manner in this architecture . today , data centres are becoming more prevalent due to the increasing popularity of cloud based computing . but power bills are the largest recurring cost for a data centre [ 23 ]. hence , low - power machine learning solutions could enable data centres of the future by cutting their energy bills drastically . a number of variations of the invention are possible within the scope and spirit of the invention , as will be clear to a skilled reader . an elm is closely related to a class of adaptive networks referred to as a reservoir computer system . in general , a reservoir computing system refers to a time variant dynamical system with two parts —( 1 ) a recurrent connected set of nodes ( referred to as the “ liquid ” of “ the reservoir ”) with fixed connection weights to which the input is connected and ( 2 ) a readout with tunable weights that is trained according to the task . two major types of reservoir computing systems are popularly used — the liquid state machine ( lsm ) [ 24 ] and the echo state network ( esn ) [ 25 ]. fig1 shows a depiction of a lsm network where the input signal u ( t ) is connected to the “ liquid ” of the reservoir which implements a function l m on the input to create internal states x m ( t ), i . e . x m ( t )=( l m u )( t ). the states of these nodes , xm ( t ) are used by a trainable readout f m , which is trained to use these states and approximate a target function . the major difference between lsm and esn is that in lsm , each node is considered to be a spiking neuron that communicates with other nodes only when its local state variable exceeds a threshold and the neuron emits a “ spike ” whereas in esn , each node has an analog value and communicates constantly with other nodes . in practice , the communication between nodes for esn and state updates are made at a fixed discrete time step . extreme learning machines ( elm ) can be considered as a special case of reservoir learning where there are no feedback or recurrent connections within the reservoir . also , typically the connection between input and hidden nodes is all - to - all in elm while it may be sparse in lsm or esn . finally , the neurons or hidden nodes in elm have an analog output value and are typically not spiking neurons . however , they may be implemented by using spiking neuronal oscillators followed by counters as shown in the patent draft . next , we briefly explain how lsm or esn may be implemented in hardware as embodiments of the invention , replacing the elm . to implement the lsm , hidden nodes can be any spiking neuron circuit that can convert input analog signals to a digital pulse or spike . several examples of such circuits are described in [ 26 ]. the input pulses ( u ( t )) as well as the pulses generated by the hidden nodes ( x m ( t )) may be connected to ihc circuits that accept a pulse as an input and converts it to an analog signal . as an example , if the mode of representing analog signal is currents , the circuit shown in fig1 may be used to convert an input digital pulse or spike to an analog current isyn . several other such circuits are described in [ 27 ]. this current is scaled by random factor and supplied to the input of other hidden nodes . as described in the present invention , this may be done by exploiting the inherent mismatch in current mirror circuits . note that in this case no counters are needed in the ihc or after the spiking neuronal oscillators of the hidden node . to implement esn , the hidden node can implement a spiking neuronal oscillator followed by a counter just as described above for an elm . this digital value ( x m ( t )) is sampled at every discrete time step of updating states and can be applied to the input of the network through a dac producing output currents . to implement the random scaling of the inputs , again mismatch in current mirrors may be utilized , as in the embodiment explained in detail above . also , if the input ( u ( t )) is a binary encoded digital signal , it can be applied to a current dac followed by random scaling using current mirrors . otherwise , if it is a current signal , it can be directly applied to the current mirrors through a diode connected transistor as the ihc . one task for which an embodiment of the invention can be employed is recognising motions . fig1 shows a variation of the elm which can be used for this purpose . the first hidden layer of the elm is the same as explained above . however , the second layer has two sections : a first section containing m outputs , o 1 , . . . o m where m is greater than 1 , and a second section with just one output o m + 1 . the input to the network may be the outputs of brain sensors sensing neuronal activity in the brain of a subject . as noted above , each of the m outputs is defined using a corresponding vector of second layer weights . the first section of the second layer is trained , in the way explained above , to recognise one of m types of movements . the output of this section of the second layer is the one of the m outputs o 1 , . . . , o m having the highest value . this is referred to as s ( t k ). the second section of the second layer is used to recognise the onset of the motion . the output o m + 1 is trained by regression , and the target is a trapezoidal fuzzy membership function which gradually rises from 0 to 1 representing the gradual evolution of biological neural activity . this output o m + 1 is thresholded to produce the final output g ( t k ) at time t k as g ( t k )= 1 is o m + 1 is above a threshold θ8 , and zero otherwise . the threshold θ is optimized as a hyper - parameter . moreover , to reduce spurious classification and produce a continuous output , the primary output g ( tk ) is processed to create g track ( tk ) that is high only if g is high for at least λ times over the last τ time points . further , to reduce false positives , another detection is prohibited for t r milliseconds after a valid one . the final decoded output , f ( t k ) is obtained by a simple combination of the two classifiers as f ( t k )= g track ( t k )× s ( t k ). it is observed that for some computational tasks , the value of { circumflex over ( β )} given by eqn . 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