Patent Application: US-87268201-A

Abstract:
a microprocessor structure for performing a discrete wavelet transform operation , said discrete wavelet transform operation comprising decomposition of an input signal comprising a vector of r × k m input samples , r , k and m being non - zero positive integers , over a specified number of decomposition levels j , where j is an integer in the range 1 to j , starting from a first decomposition level and progressing to a final decomposition level , said microprocessor structure having a number of processing stages , each of said number of processing stages corresponding to a decomposition level j of the discrete wavelet transform operation and being implemented by a number of basic processing elements , the number of basic processing elements implemented in each of said processing stages decreasing by a factor of k from a decomposition level j to a decomposition level j + 1 .

Description:
to describe architectures proposed in this invention we first need to define the dwt and to present the basic algorithm that is implemented within the architectures . there are several alternative definitions / representations of dwts such as the tree - structured filter bank , the lattice structure , lifting scheme or matrix representation . the following discussion uses the matrix definition and a flowgraph representation of dwts which is very effective in designing efficient parallel / pipelined dwt architectures . a discrete wavelet transform is a linear transform y = h · x , where x =[ x 0 , . . . , x n − 1 ] t and y =[ y 0 , . . . , y n − 1 ] t are the input and the output vectors of length n = 2 m , respectively , and h is the dwt matrix of order n × n which is formed as the product of sparse matrices : h = h ( j ) h ( j − 1 ) · . . . · h ( 1 ) , 1 ≦ j ≦ m ; h ( j ) = ( d j 0 0 i 2 m - 2 m - j + 1 ) , j = 1 , … ⁢ , m ( 1 ) where i k is the identity ( k × k ) matrix ( k = 2 m − 2 m − j + 1 ), and d j is the analysis ( 2 m − j + 1 × 2 m − j + 1 ) matrix at stage j having the following structure : d j = ⁢ ( l 1 l 2 … l l 0 0 … 0 0 0 l 1 l 2 … l l … 0 h 3 … h l 0 0 … h 1 h 2 ) = ⁢ p j · ( l 1 l 2 … l l 0 0 … 0 h 1 h 2 … h l 0 0 … 0 0 0 l 1 l 2 … l l … 0 0 0 h 1 h 2 … h l … 0 l 3 … l l 0 0 … l 1 l 2 h 3 … h l 0 0 … h 1 h 2 ) ( 2 ) where lp =[ l 1 , . . . , l l ] and hp =[ h 1 , . . . , h l ] are the vectors of coefficients of the low - pass and of the high - pass filters , respectively ( l being the length of the filters ), and p j is the matrix of the perfect unshuffle operator ( see [ 31 ]) of the size ( 2 m − j + 1 × 2 m − j + 1 ). for the sake of clarity both filters are assumed to have the same length which is an even number . the result may be readily expanded to the general case of arbitrary filter lengths . in the general case ( that is where n = r × k m rather than n = 2 m ), where k is not equal to two ( that is there are other than two filtering operations carried out in each pe and there are other than two outputs from each pe ), a suitable stride permutation rather than the unshuffle operation is applied . adopting the representation ( 1 )-( 2 ), the dwt is computed in j stages ( also called decomposition levels or octaves ), where the jth stage , j = 1 , . . . , j , constitutes multiplication of a sparse matrix h ( j ) by a current vector of scratch variables , the first such vector being the input vector x . noting that lower right corner of every matrix h ( j ) is an identity matrix and taking into account the structure of the matrix d j , the corresponding algorithm can be written as the following pseudocode where x lp ( j ) =[ x lp ( j ) ( 0 ), . . . , x lp ( j ) ( 2 m − j − 1 )] t , and x hp ( j ) =[ x hp ( j ) ( 0 ), . . . , x hp ( j ) ( 2 m − j − 1 )] t , j = 1 , . . . , j , are ( 2 m − j x1 ) vectors of scratch variables , and the notation [( x l ) t , . . . , ( x k ) t ] t stands for concatenation of column vectors x l , . . . , x k . 2 . for i = 0 , ... , 2 m − j − 1 , computation of algorithm 1 with the matrices d j of ( 2 ) can be demonstrated using a flowgraph representation . an example for the case n = 2 3 = 8 , l = 4 , j = 3 is shown in fig2 . the flowgraph consists of j stages , the j - th stage , j = 1 , . . . , j , having 2 m − j nodes ( depicted as boxes on fig2 ). each node represents a basic dwt operation ( see fig2 ( b )). the ith node , i = 0 , . . . , 2 m − j − 1 , of stage j = 1 , . . . , j has incoming edges from l circularly consecutive nodes 2i , 2i + 1 , ( 2i + 2 ) mod 2 m − j + 1 . . . , ( 2i + l − 1 ) mod 2 m − j + 1 of the preceding stage or ( for the nodes of the first stage ) from inputs . every node has two outgoing edges . an upper ( lower ) outgoing edge represents the value of the inner product of the vector of low - pass ( high - pass ) filter coefficients with the vector of the values of incoming edges . outgoing values of a stage are permuted according to the perfect unshuffle operator so that all the low - pass components ( the values of upper outgoing edges ) are collected in the first half and the high - pass components are collected at the second half of the permuted vector . low pass components then form the input to the following stage or ( for the nodes of the last stage ) represent output values . high - pass components and the low pass components at that stage represent output values at a given resolution . essentially , the flowgraph representation provides an alternative definition of discrete wavelet transforms . it has several advantages , at least from the implementation point of view , as compared to the conventional dwt representations such as the tree - structured filter bank , lifting scheme or lattice structure representation . however , the flowgraph representation of dwts as it has been presented has a disadvantage of being very large for bigger values of n . this disadvantage can be overcome based on the following . assuming j & lt ; log 2 n i . e . in the level of decomposition is & lt ;& lt ; number of points in the input vector ( in most applications j & lt ;& lt ; log 2 n ) one can see that the dwt flowgraph consists of n / 2 j similar patterns ( see the two hatching regions on fig2 ). each pattern can be considered as a 2 j - point dwt with a specific strategy of forming the input signals to each of its octaves . the 2 m − j + 1 input values of the j - th , j = 1 , . . . , j , octave are divided within the original dwt ( of length n = 2 m ) into n / 2 j = 2 m − j non - overlapping groups consisting of 2 j − j + 1 consecutive values . this is equivalent to dividing the vector x lp ( j − 1 ) of ( 3 ) into subvectors x ( j − 1 , s ) = x lp ( j − 1 ) ( s · 2 j − j + 1 :( s + 1 )· 2 j − j + 1 − 1 ), s = 0 , . . . , 2 m − j − 1 , where here and in the following the notation x ( a : b ) stands for the subvector of x consisting of the a - th to b - th components of x . then the input of the j - th , j = 1 , . . . , j , octave within the s - th pattern is the subvector { circumflex over ( x )} ( j − 1 , s ) ( 0 : 2 j − j + 1 + l − 3 ) of the vector , x ^ ( j - 1 , s ) = [ ( x lp ( j - 1 , s ⁢ ⁢ mod ⁢ ⁢ 2 m - j ) ) t , ( x lp ( j - 1 , ( s + 1 ) ⁢ mod ⁢ ⁢ 2 m - j ) ) t , … ⁢ , ( x lp ( j - 1 , ( s + q j ) ⁢ mod ⁢ ⁢ 2 m - j ) ) t ] t ( 4 ) being the concatenation of the vector x lp ( j − 1 , s ) with the circularly next q j vectors where q j =┌( l − 2 )/ 2 j − j + 1 ┐. if the 2 m − j patterns are merged into a single pattern , a compact ( or core ) flowgraph representation of the dwt is obtained . an example of a dwt compact flowgraph representation for the case j = 3 , l = 4 is shown in fig3 . the compact dwt flowgraph has 2 j − j nodes at its j - th , stage , j = 1 , . . . , j , where a set of 2 m − j temporally distributed values are now assigned to every node . every node has l incoming and two outgoing edges like in the (“ non - compact ”) dwt flowgraph . again incoming edges are from l “ circularly consecutive ” nodes of the previous stage but now every node represents a set of temporally distributed values . namely , the l inputs of the ith node of the j - th , stage , j = 1 , . . . , j , for its sth value , s = 0 , . . . , 2 m − j − 1 are connected to the nodes ( 2i + n ) mod 2 j − j + 1 , n = 0 , . . . , l − 1 of the ( j − 1 ) st stage which now represent their ( s + s ′) th values where s ′=└( 2i + n )/ 2 j − j + 1 ┘. also , outputs are now distributed over the outgoing edges of the compact flowgraph not only spatially but also temporally . that is , each outgoing edge corresponding to a high - pass filtering result of a node or low - pass filtering result of a node of the last stage represents a set of 2 m − j output values . note that the structure of the compact dwt flowgraph does not depend on the length of the dwt but only on the number of decomposition levels and filter length . the dwt length is reflected only in the number of values represented by every node . it should also be noted that the compact flowgraph has the structure of a 2 j - point dwt with slightly modified appending strategy . in fact , this appending strategy is often used in matrix formulation of the dwt definition . let { circumflex over ( d )} j denote the main ( 2 j − j + 1 ×( 2 j − j + 1 + l − 2 ))- minor of d j ( see ( 2 )), j = 1 , . . . , j that is let { circumflex over ( d )} j be a matrix consisting of the first 2 j − j + 1 rows and the first 2 j − j + 1 + l − 2 columns of d j . for example , if j − j + 1 = 2 and l = 6 , then { circumflex over ( d )} j is of the form : d ^ j = ( l 1 l 2 l 3 l 4 l 5 l 6 0 0 0 0 l 1 l 2 l 3 l 4 l 5 l 6 h 1 h 2 h 3 h 4 h 5 h 6 0 0 0 0 h 1 h 2 h 3 h 4 h 5 h 6 ) adopting the notation of ( 4 ), the computational process represented by the compact flowgraph can be described with the following pseudocode . for s = 0 , ... , 2 m − j − 1 implementing the cycle for s in parallel yields a parallel dwt realisation . on the other hand , by exchanging the nesting order of the cycles for j and s and implementing the ( nested ) cycle for j in parallel it is possible to implement a pipelined dwt realisation . however , both of these realisations would be inefficient since the number of operations is halved from one octave to the next . however , combining the two methods yields very efficient parallel - pipelined or partially parallel - pipelined realisations . to apply pipelining to the algorithm 2 , retiming must be applied since computations for s include results of computations for s + 1 , . . . , s + q j − 1 meaning that the jth octave , j = 1 , . . . , j , introduces a delay of q j steps . since the delays are accumulated , computations for the jth octave , j = 1 , . . . , j , must start with a delay of s * ⁡ ( j ) = ∑ n = 1 j ⁢ q n . ( 5 ) during the steps s = s *( j ), . . . , 2 m − j + s *( j )− 1 . thus , computations take place starting from the step s = s *( 1 ) until the step s = s *( j )+ 2 m − j − 1 . at steps s = s *( 1 ), . . . , s *( 2 )− 1 computations of only the first octave are implemented , at steps s = s *( 2 ), . . . , s *( 3 )− 1 only operations of the first two octaves are implemented , etc . starting from step s = s *( j ) until the step s = s *( 1 )+ 2 m − j − 1 ( provided s *( j )& lt ; s *( 1 )+ 2 m − j ) computations of all the octaves j = 1 , . . . , j are implemented , but starting from step s = s *( 1 )+ 2 m − j no computations for the first octave are implemented , starting from step s = s *( 2 )+ 2 m − j no computations for the first two octaves are implemented , etc . in general , at step s = s *( 1 ), . . . , 2 m − j + s *( j )− 1 computations for octaves j = j 1 , . . . , j 2 are implemented where j 1 = min { j such that s *( j )≦ s & lt ; s *( j )+ 2 m − j } and j 1 = max { j such that s *( j )≦ s & lt ; s *( j )+ 2 m − j }. the following pseudocode presents the pipelined dwt realisation which is implemented within the architectures proposed in this invention . 2 . for s = s *( 1 ), ... , 2 m − j + s *( j ) − 1 for j = j 1 , ... , j 2 do in parallel in this invention , general parametric structures of two types of dwt architectures , referred to as type 1 and type 2 core dwt architectures are introduced , as well as general parametric structures of two other dwt architectures which are constructed based on either a core dwt architecture and are referred to as the multi - core dwt architecture and the variable resolution dwt architecture , respectively . all the architectures can be implemented with a varying level of parallelism thus allowing a trade - off between the speed and hardware complexity . depending on the level of parallelism throughputs up to constant time implementation ( one 2 m - point dwt per time unit ) may be achieved . at every level of parallelism the architectures operate with approximately 100 % hardware utilisation thus achieving almost linear speed - up with respect to the level of parallelism compared with the serial dwt implementation . the architectures are relatively independent on the dwt parameters . that is , a device having one of the proposed architectures would be capable of efficiently implementing not only one dwt but a range of different dwts with different filter length and , in the case of variable resolution dwt architecture , with a different number of decomposition levels over vectors of arbitrary length . many different realisations of the proposed architectures are possible . therefore , their general structures are described at a functional level . realisations of the general structures at the register level are also presented . these realisations demonstrate the validity of the general structures . the proposed architectures are essentially different in terms of functional description level from known architecures . the type 1 and type 2 core dwt architectures implement a 2 m - point dwt with j ≦ m octaves based on low - pass and high pass filters of a length l not exceeding a given number l max where j and l max ( but not m or l ) are parameters of the realisation . both type 1 and type 2 core dwt architectures comprise a serial or parallel data input block and j pipeline stages , the jth stage , j = 1 , . . . , j , consisting of a data routing block and 2 j − j processing elements ( pes ). this will be described in relation to fig4 . the jth pipeline stage , j = 1 , . . . , j , of the architecture implements the 2 m − j independent similar operations of the jth dwt octave in 2 m − j operation steps . at every step , a group of 2 j − j operations is implemented in parallel within 2 j − j pes of the pipeline stage . the pes can be implemented with varying level of parallelism , which is specified by the number p ≦ l max of its inputs . a single pe with p inputs implements one basic dwt operation ( see fig2 ,( b )) in one operation step consisting of ┌ l / p ┐ time units where at every time unit the results of 2p multiplications and additions are obtained in parallel . thus the time period ( measured as the intervals between time units when successive input vectors enter to the architecture ) is equal to 2 m − j [ l / p ] time units where the duration of the time unit is equal to the period of one multiplication operation . this is 2 j /┌ l / p ┐ times faster than the best period of previously known architectures [ 12 - 26 ] and 2 j − 1 /┌ l / p ┐ faster than the architectures described in [ 30 ]. the efficiency ( or hardware utilisation ) of both architectures is equal l /( p ┌ l / p ┐)· 100 %≈ 100 %. in the case of p = l = l max the period is 2 m − j time units which is the same as for the lpp architecture which , however , depends on the filter length l ( i . e . the lpp architecture is only able to implement dwts with filters of a fixed length l ). the two types of core dwt architecture differ according to the absence ( type 1 ) or presence ( type 2 ) of interconnection between the pes of one pipeline stage . possible realisations of the two types of core dwt architectures are presented in fig5 to 10 . the two types of core dwt architecture described above may be implemented with a varying degree of parallelism depending on the parameter p . further flexibility in the level of parallelism is achieved within multi - core dwt architectures by introducing a new parameter r = 1 , . . . , 2 m − j . the multi - core dwt architecture is , in fact , obtained from corresponding ( single -) core dwt architecture by expanding it r times . its general structure is presented in fig1 . the architecture consists of a serial or parallel data input block and j pipeline stages , the jth pipeline stage , j = 1 , . . . , j , consisting of a data routing block and r2 j − j pes . the time period of the multi - core dwt architecture is equal to ( 2 m − j [ l / p ])/ r time units which is r times faster than that of single - core dwt architecture , i . e . a linear speed - up is provided . the efficiency of the multi - core dwt architecture is the same as for single - core architectures , that is , approximately 100 %. note that in the case of p = l = l max and r = 2 m − j the period is just one time unit for a 2 m - point dwt . similar performance is achieved in the fpp architecture which can be considered as a special case ( p = l = l max and r = 2 m − j ) of a possible realisation of the multi - core dwt architecture . ep / us ] the ( single - and multi -) core dwt architectures are relatively independent of the length of the input and on the length of the filters , which means that dwts based on arbitrary filters ( having a length not exceeding l max ) over signals of arbitrary length can be efficiently implemented with the same device having either type 1 or type 2 core dwt architecture . however , these architectures are dependent on the number of dwt octaves j . they may implement dwts with smaller than j number of octaves , though with some loss in hardware utilisation . the variable resolution dwt architecture implements dwts with arbitrary number of octaves j ′ and the efficiency of the architecture remains approximately 100 % whenever j ′ is larger than or equal to a given number . the variable resolution dwt architecture comprises a core dwt architecture corresponding to j min decomposition levels and an arbitrary serial dwt architecture , for , instance , an rpa - based architecture ( see fig1 ,( a )). the core dwt architecture implements the first j min octaves of the j ′- octave dwt and the serial dwt architecture implements the last j ′− j min octaves of the j ′- octave dwt . since the core dwt architecture may be implemented with a varying level of parallelism it can be balanced with the serial dwt architecture in such a way that approximately 100 % of hardware utilisation is achieved whenever j ′≧ j min . a variable resolution dwt architecture based on a multi - core dwt architecture may also be constructed ( see fig1 ,( b )) in which a data routing block is inserted between the multi - core and serial dwt architectures . this section presents the general structures of two types of dwt architecture , referred to as type 1 and type 2 core dwt architectures , as well as two other dwt architectures which are constructed based on either core dwt architecture and are referred to as the multi - core dwt architecture and the variable resolution dwt architecture , respectively . the multi - core dwt architecture is an extension of either one of the core dwt architectures , which can be implemented with a varying level of parallelism depending on a parameter m , and in a particular case ( m = 1 ) it becomes the ( single -) core dwt architecture . for ease of understanding the presentation of the architectures starts with a description of the ( single -) core dwt architectures . both types of core dwt architecture implement an arbitrary discrete wavelet transform with j decomposition levels ( octaves ) based on low - pass and high - pass filters having a length l not exceeding a given number l max . their operation is based on algorithm 3 presented earlier . the general structure representing both types of core dwt architecture is presented in fig4 , where dashed lines depict connections , which may or may not be present depending on the specific realisation . connections are not present in type 1 but are present in type 2 . in both cases the architecture consists of a data input block and j pipeline stages , each stage containing a data routing block and a block of processor elements ( pes ) wherein the data input block implements the step 1 of the algorithm 3 , data routing blocks are responsible for step 2 . 1 , and blocks of pes are for computations of the step 2 . 2 . the two core architecture types mainly differ by the possibility of data exchange between pes of the same pipeline stage . in the type 2 core dwt architecture pes of a single stage may exchange intermediate data via interconnections while in the type 1 core dwt architecture there are no interconnections between the pes within a pipeline stage and thus the pes of a single stage do not exchange data during their operation . in general many different realisations of data routing blocks and blocks of pes are possible . therefore , in one aspect , the invention can be seen to be the architectures as they are depicted at the block level ( fig4 , 11 , and 12 ) and as they are described below at the functional level independent of the precise implementation chosen for the pes and data routing blocks . however , some practical realisations of the proposed core dwt architectures at register level are presented by way of example with reference to fig5 to 10 . these exemplary implementations demonstrate the validity of the invention . fig4 presents the general structure of the type 1 and type 2 core dwt architecture . as explained in the foregoing , type 1 and type 2 differ only in the lack or presence of interconnection between the pes within a stage . the data input block of both core dwt architectures may be realized as either word - serial or word - parallel . in the former case the data input block consists of a single ( word - serial ) input port which is connected to a shift register of length 2 j ( dashed lined box in fig4 ) having a word - parallel output from each of its cells . in the latter case the data input block comprises 2 j parallel input ports . in both cases the data input block has 2 j parallel outputs which are connected to the 2 j inputs of the data routing block of the first pipeline stage . in fig6 an example of a word - parallel data input block is presented while fig7 and 10 present an example of a word - serial data input block . the basic algorithm implemented within the type 1 core dwt architecture is algorithm 3 with a specific order of implementing step 2 . 2 . the structure of the 2 j − j + 1 × 2 j − j + 1 matrix { circumflex over ( d )} j is such that the matrix - vector multiplication of step 2 . 2 can be decomposed into 2 j − j pairs of vector - vector inner product computations : x ( j , s − s *( j )) ( i )= lp ·{ circumflex over ( x )} ( j − 1 ,( s − s *( j ))) ( 2 i : 2 i + l − 1 ), x ( j , s − s *( j )) ( i + 2 j − j )= hp ·{ circumflex over ( x )} ( j − 1 ,( s − s *( j ))) ( 2 i : 2 i + l − 1 ), which can be implemented in parallel . on the other hand , every vector - vector inner product of length l can be decomposed into a sequence of l p =┌ l / p ┐ inner products of length p with accumulation of the results ( assuming that the coefficient vectors and input vectors are appended with appropriate number of zeros and are divided into subvectors of consecutive p components ). as a result , algorithm 3 can be presented with the following modification of the previous pseudocode . 2 . for s = s *( 1 ), ... , 2 m − j + s *( j ) − 1 for j = j 1 , ... , j 2 do in parallel 2 . 2 . for i = 0 , ... , 2 j − j − 1 do in parallel for n = 0 , ... , l p − 1 do in sequential note that given s and j , the group of operations ( 6 ) and ( 7 ) involve the subvector { circumflex over ( x )} ( j − 1 , s − s *( j )) ( 0 : 2 j − j + 1 + p − 3 ) for n = 0 , the subvector { circumflex over ( x )} ( j − 1 , s − s *( j )) ( p : 2 j − j + 1 + 2p − 3 ) and , in general , the subvector { circumflex over ( x )} ( j − 1 , sj , n ) ={ circumflex over ( x )} ( j − 1 , s − s *( j )) ( np : 2 j − j + 1 +( n + 1 ) p − 3 ) for n = 0 , . . . , l p − 1 . in other words , computations for n = 0 , . . . , l p − 1 involve the first 2 j − j + 1 + p − 2 components of the vector { circumflex over ( x )} ( j − 1 , sj , n ) which is obtained from the vector { circumflex over ( x )} ( j − 1 , s − s *( j )) by shifting its components left by np positions . it should also be noted that computations for a given i = 0 , . . . , 2 j − j − 1 always involve the components 2i , 2i + 1 , . . . , 2i + p − 1 of the current vector { circumflex over ( x )} ( j − 1 , sj , n ) . the general structure of the type 1 core dwt architecture is presented in fig4 . in the case of this architecture , the dashed lines can be disregarded because there are no connections between pes of a single stage . the architecture consists of a data input block ( already described above ) and j pipeline stages . in general , the jth pipeline stage , j = 1 , . . . , j , of the type 1 core dwt architecture comprises a data routing block having 2 j − j + 1 inputs i ps ( j ) ( 0 ), , i ps ( j ) ( 2 j − j + 1 − 1 ) forming the input to the stage , and 2 j − j + 1 + p − 2 outputs o drb ( j ) ( 0 ), , o drb ( j ) ( 2 j − j + 1 + p − 3 ) connected to the inputs of 2 j − j pes . every pe has p inputs and two outputs where p ≦ l max is a parameter of the realisation describing the level of parallelism of every pe . consecutive p outputs o drb ( j ) ( 2i ), o drb ( j ) ( 2i + 1 ), . . . , o drb ( j ) ( 2i + p − 1 ) of the data routing block of the jth , j = 1 , . . . , j , stage are connected to the p inputs of the ith , i = 0 , . . . , 2 j − j − 1 , pe ( pe j , i ) of the same stage . the first outputs of each of 2 j − j pes of the jth pipeline stage , j = 1 , . . . , j − 1 , form the outputs o ps ( j ) ( 0 ), , o ps ( j ) ( 2 j − j − 1 ) of that stage and are connected to the 2 j − j inputs i ps ( j + 1 ) ( 0 ), , i ps ( j + 1 ) ( 2 j − j − 1 ) of the data routing block of the next , ( j + 1 ) st , stage . the first output of the ( one ) pe of the last , jth , stage is the 0th output out ( 0 ) of the architecture . the second outputs of the 2 j − j pes of the jth pipeline stage , j = 1 , . . . , j , form the ( 2 j − j ) th to ( 2 j − j + 1 − 1 ) st outputs out ( 2 j − j ), . . . , out ( 2 j − j + 1 − 1 ) of the architecture . the blocks of the type 1 core dwt architecture are now described at the functional level . for convenience , a time unit is defined as the period for the pes to complete one operation ( which is equal to the period between successive groups of p data entering the pe ) and an operation step of the architecture is defined as comprising l p time units . the functionality of the data input block is clear from its structure . it serially or parallelly accepts and parallelly outputs a group of components of the input vector at the rate of 2 j components per operation step . thus , the vector x lp ( 0 , s ) is formed on the outputs of the data input block at the step s = 0 , . . . , 2 m − j − 1 . the data routing block ( of the stage j = 1 , . . . , j ,) can , in general , be realized as an arbitrary circuitry which at the first time unit n = 0 of its every operation step parallelly accepts a vector of 2 j − j + 1 components , and then at every time unit n = 0 , . . . , l p − 1 of that operation step it parallelly outputs a vector of 2 j − j + 1 + p − 2 components np , np + 1 , . . . ,( n + 1 ) p + 2 j − j + 1 − 3 of a vector being the concatenation ( in chronological order ) of the vectors accepted at previous { circumflex over ( q )} j steps , where { circumflex over ( q )} j =┌( l max − 2 )/ 2 j − j + 1 ┐ j = 1 , . . . , j . ( 8 ) the functionality of the pes used in the type 1 core dwt architecture is to compute two inner products of the vector on its p inputs with two vectors of predetermined coefficients during every time unit and to accumulate the results of both inner products computed during one operation step . at the end of every operation step , the two accumulated results pass to the two outputs of the pe and new accumulation starts . clearly , every pe implements the pair of operations ( 6 ) and ( 7 ) provided that the correct arguments are formed on their inputs . it will now be demonstrated that the architecture implements computations according to algorithm 3 . 1 . in the case where l & lt ; l max an extra delay is introduced . the extra delay is a consequence of the flexibility of the architecture that enables it to implement dwts with arbitrary filter length l ≦ l max . this should be compared with algorithm 3 . 1 which presents computation of a dwt with a fixed filter length l . in fact , the architecture is designed for the filter length l max but also implements dwts with shorter filters with a slightly increased time delay but without losing in time period . s ^ ⁡ ( 0 ) = 0 , s ^ ⁡ ( j ) = ∑ n = 1 j ⁢ q ^ n + j - 1 , j = 1 , … ⁢ , j . ( 9 ) during operation of the architecture , the vector x lp ( 0 , s ) is formed on the outputs of the data input block at step s = 0 , . . . , 2 m − j − 1 and this enters to the inputs of the data routing block of the first pipeline stage . to show that the architecture implements computations according to algorithm 3 . 1 it is sufficient to show that the vectors x lp ( j , s − ŝ ( j )) are formed at the first outputs of pes of the jth stage ( which are connected to the inputs of the ( j + 1 ) st stage ) and the vectors x hp ( j , s − ŝ ( j )) are formed at their second outputs at steps s = ŝ ( j ), . . . , ŝ ( j )+ 2 m − j − 1 provided that the vectors x lp ( j − 1 , s − ŝ ( j − 1 )) enter to the jth stage at steps s = ŝ ( j − 1 )+ 2 m − j − 1 ( proof by mathematical induction ). thus , it is assumed that the data routing block of stage j = 1 , . . . , j , accepts vectors x lp ( j − 1 , s − ŝ ( j − 1 )) at steps s = ŝ ( j − 1 ), . . . , ŝ ( j − 1 )+ 2 m − j − 1 . then , according to the functional description of the data routing blocks , the components np , np + 1 , . . . ,( n + 1 ) p + 2 j − j + 1 − 3 of the vector x ~ ( j - 1 , s - s ^ ⁡ ( j ) ) = ⁢ [ ( x lp ( j - 1 , s - s ^ ⁡ ( j + 1 ) ⁢ mod ⁢ 2 m - j ) ) t , ⁢ ( x lp ( j - 1 , s - s ^ ⁡ ( j - 1 ) + 2 ) ⁢ mod ⁢ 2 m - j ) ) t , … ⁢ , ⁢ ( x lp ( j - 1 , s - s ^ ⁡ ( j - 1 ) ) ⁢ mod ⁢ 2 m - j ) ) t ] t ( 10 ) being the concatenation of the vectors accepted at steps s −{ circumflex over ( q )} j , s −{ circumflex over ( q )} j + 2 , . . . , s , respectively , will be formed on the outputs of the data routing block at the time unit n = 0 , . . . , l p − 1 of every step s = ŝ ( j ), . . . , ŝ ( j )+ 2 m − j − 1 . since ŝ ( j )≧ s *( j ) ( compare ( 3 ) and ( 9 )), the vector { circumflex over ( x )} ( j − 1 , s − ŝ ( j )) ( defined according to ( 4 )) is the subvector of { tilde over ( x )} ( j − 1 , s − ŝ ( j )) so that their first 2 j − j + 1 + l − 3 components are exactly the same . thus the vector { circumflex over ( x )} ( j − 1 , sj , n ) ={ circumflex over ( x )} ( j − 1 , s − ŝ ( j )) ( np : 2 j − j + 1 +( n + 1 ) p − 3 ) is formed at the time unit n = 0 , . . . , l p − 1 of the step s = ŝ ( j ), . . . , ŝ ( j )+ 2 m − j − 1 at the outputs of the data routing block of stage j = 1 , . . . , j . due to the connections between the data routing block and pes , the components 2i , 2i + 1 , . . . , 2i + p − 1 of the vector { circumflex over ( x )} ( j − 1 , sj , n ) which are , in fact , arguments of the operations ( 6 ) and ( 7 ), will be formed on the inputs of the pe j , i , i = 0 , . . . , 2 j − j − 1 at the time unit n = 0 , . . . , l p − 1 of the step s = ŝ ( j ), . . . , ŝ ( j )+ 2 m − j − 1 . thus , if pes implement their operations with corresponding coefficients , the vector x lp ( j , s − ŝ ( j )) will be formed on the first outputs of the pes and the vector x hp ( j , s − ŝ ( j )) will be formed on their second outputs after the step s = ŝ ( j ), . . . , ŝ ( j )+ 2 m − j − 1 . since the first outputs of pes are connected to the inputs of the next pipeline stage this proves that the architecture implements computations according to the algorithm 3 . 1 albeit with different timing ( replace s *( j ) with ŝ ( j ) everywhere in algorithm 3 . 1 ). from the above considerations it is clear that a 2 m - point dwt is implemented with the type 1 core dwt architecture in 2 m − j + ŝ ( j ) steps each consisting of l p time units . thus the delay between input and corresponding output vectors is equal to t d ( c 1 )=( 2 m − j + ŝ ( j )[ l / p ] ( 11 ) time units . clearly the architecture can implement dwts of a stream of input vectors . it is therefore apparent that the throughput or the time period ( measured as the the intervals between time units when successive input vectors enter the architecture ) is equal to performance of parallel / pipelined architectures is often evaluated with respect to hardware utilization or efficiency , defined as e = t ⁡ ( 1 ) k · t ⁡ ( k ) · 100 ⁢ % ( 13 ) where t ( 1 ) is the time of implementation of an algorithm with one pe and t ( k ) is the time of implementation of the same algorithm with an architecture comprising k pes . it can be seen that t ( 1 )=( 2 m − 1 )[ l / p ] time units are required to implement a 2 m - point dwt using one pe similar to the pes used in the type 1 core dwt architecture . together with ( 11 ) and ( 12 ), and taking into account the fact that there are in total k = 2 j − 1 pes within the type 1 core dwt architecture , it can be shown that approximately 100 % efficiency ( hardware utilisation ) is achieved for the architecture both with respect to time delay or , moreover , time period complexities . it should be noted that an efficiency close to the efficiency of the fpp architecture is reached only in a few pipelined dwt designs ( see [ 17 ]) known from the prior art whereas most of the known pipelined dwt architectures reach much less than 100 % average efficiency . it should also be noted that a time period of at least o ( n ) time units is required by known dwt architectures . the proposed architecture may be realized with a varying level of parallelism depending on the parameter p . as follows from ( 12 ) the time period complexity of the implementation varies between t l ( c1 )= 2 m − j and t 1 ( c1 )= l2 m − j . thus the throughput of the architecture is 2 j / l to 2 j times faster than that of the fastest known architectures . the possibility of realising the architecture with a varying level of parallelism also gives an opportunity to trade - off time and hardware complexities . it should also be noted that the architecture is very regular and only requires simple control structures ( essentially , only a clock ) unlike , e . g . the architecture of [ 17 ]. it does not contain a feedback , switches , or long connections that depend on the size of the input , but only has connections which are at maximum only o ( l ) in length . thus , it can be implemented as a semisystolic array . a possible structure of the jth pipeline stage , j = 1 , . . . , j , for the type 1 core dwt architecture is depicted in fig5 . two examples of such realisation for the case l max = 6 , j = 3 are shown in fig6 and 7 , where p = l max = 6 and p = 2 , respectively . it should be noted that a particular case of this realisation corresponding to the case p = l max and , in particular , a slightly different version of the example on fig6 has been presented which is referred to as a limited parallel - pipelined ( lpp ) architecture . it should be noted that the type 1 core dwt architecture and its realisation in fig5 are for the case of arbitrary p . referring to fig5 , it can be seen that in this realisation the data routing block consists of { circumflex over ( q )} j chain connected groups of 2 j − j + 1 delays each , and a shift register of length 2 j − j + 1 + l max − 2 which shifts the values within its cells by p positions upwards every time unit . the 2 j − j + 1 inputs to the stage are connected in parallel to the first group of delays , the outputs of which are connected to the inputs of the next group of delays etc . outputs of every group of delays are connected in parallel to the 2 j − j + 1 consecutive cells of the shift register . the outputs of the last { circumflex over ( q )} j th group of delays are connected to the first 2 j − j + 1 cells , outputs of the ({ circumflex over ( q )} j − 1 ) st group of delays are connected to the next 2 j − j + 1 cells , etc ., with the exception that , the first q j =( l max − 2 )−({ circumflex over ( q )} j − 1 ) 2 j − j + 1 inputs of the stage are directly connected to the last q j cells of the shift register . the outputs of the first 2 j − j + 1 + p − 2 cells of the shift register form the output of the data routing block and are connected to the inputs of the pes . in the case p = l max ( see fig6 ) no shift register is required but the outputs of the groups of delay elements and the first q j inputs of the stage are directly connected to the inputs of the pes . on the other hand , in the case of p = 2 ( see fig7 ) interconnections between the data routing block and the pes are simplified since in this case there are only 2 j − j + 1 parallel connections from the first cells of the shift register to the inputs of the pes . it will be apparent to one of ordinary skill in the art that the presented realization satisfies the functionality constraint for the data routing block of the type 1 core dwt architecture . indeed , at the beginning of every step , the shift register contains the concatenation of the vector of data accepted { circumflex over ( q )} j steps earlier with the vector of the first l max − 2 components from the next accepted vectors . then during l p time units it shifts the components by p positions upwards every time . possible structures of pes for the type 1 core dwt architecture are presented in fig8 for the case of arbitrary p , p = 1 , p = 2 , and p = l max , ( fig8 ,( a ),( b ),( c ), and ( d ), respectively ). again it will be apparent to one of ordinary skill in the art that these structures implement the operations of ( 6 ) and ( 7 ) and , thus , satisfy the functionality description of the pes . it should again be noted that these structures are suitable for a generic dwt implementation independent of the filter coefficients and pe structures optimized for specific filter coefficients can also be implemented . the type 2 core dwt architecture implements a slightly modified version of the algorithm 3 . 1 . the modification is based on the observation that operands of operations ( 6 ) and ( 7 ) are the same for pairs ( i 1 , n 1 ) and ( i 2 , n 2 ) of indices i and n such that 2i 1 + n 1 p = 2i 2 + n 2 p . assuming an even p ( the odd case is treated similarly but requires more notation for its representation ), this means that , when implementing the operations of ( 6 ) and ( 7 ), the multiplicands required for use in time unit n = 1 , . . . , l p − 1 within branch i = 0 , . . . , 2 j − j − p / 2 − 1 can obtained from the multiplicands obtained at step n − 1 within branch i + p / 2 . the corresponding computational process is described with the following pseudocode where we denote l k ′ = { ⁢ l k ⁢ ⁢ for ⁢ ⁢ k = 0 , … ⁢ , p - 1 ⁢ l k / l k - p , for ⁢ ⁢ k = p , … ⁢ , l - 1 ; ⁢ h k ′ = { ⁢ h k ⁢ ⁢ for ⁢ ⁢ k = 0 , … ⁢ , p - 1 ⁢ h k / l k - p , for ⁢ ⁢ k = p , … ⁢ , l - 1 2 . for s = s *( 1 ), ... , 2 m − j + s *( j ) − 1 for j = j 1 , ... , j 2 do in parallel 2 . 2 . for i = 0 , ... , 2 j − j − 1 do in parallel set z lp ( i , 0 , k ) = l k { circumflex over ( x )} ( j − 1 , s − s *( j )) ( 2i + k ); z hp ( i , 0 , k ) = h k { circumflex over ( x )} ( j − 1 , s − s *( j )) ( 2i + k ) for n = 1 , ... , l p − 1 do in sequential the general structure of the type 2 core dwt architecture is presented in fig4 . in this case connections between pes ( the dashed lines ) belonging to the same pipeline stage are valid . as follows from fig4 the type 2 core dwt architecture is similar to the type 1 core dwt architecture but now except for p inputs and two outputs ( later on called main inputs and main outputs ) every pe has additional p inputs and 2p outputs ( later on called intermediate inputs and outputs ). the 2p intermediate outputs of pe j , i + p / 2 are connected to the p intermediate inputs of pe j , i , i = 0 , . . . , 2 j − j − p / 2 − 1 . the other connections within the type 2 core dwt architecture are similar to those within the type 1 core dwt architecture . the functionality of the blocks of the type 2 core dwt architecture are substantially similar to those of the type 1 core dwt architecture . the functionality of the data input block is exactly the same as for the case of the type 1 core dwt architecture . the data routing block ( of the stage j = 1 , . . . , j ,) can , in general , be realized as an arbitrary circuitry which at the first time unit n = 0 of its every operation step accepts a vector of 2 j − j + 1 components in parallel , and parallelly outputs a vector of the first 2 j − j + 1 + p − 2 components 0 , 1 , . . . , 2 j − j + 1 + p − 3 of a vector which is the concatenation ( in the chronological order ) of the vectors accepted at the previous { circumflex over ( q )} j steps , where { circumflex over ( q )} j is defined in ( 8 ). then at every time unit n = 0 , . . . , l p − 1 of that operation step the data routing block parallelly outputs the next subvector of p components 2 j − j + 1 + np − 2 , . . . , 2 j − j + 1 +( n + 1 ) p − 3 of the same vector on its last p outputs . the functionality of the pes used in the type 2 core dwt architecture at every time unit n = 0 , . . . , l p − 1 of every operation step is to compute two inner products of a vector , say , x , either on its p main or p intermediate inputs with two vectors of predetermined coefficients , say lp ′ and hp ′ of length p as well as to compute a point - by - point product of x with lp ′. at the time unit n = 0 the vector x is formed using the main p inputs of the pe and at time units n = 1 , . . . , l p − 1 vector x is formed using the intermediate inputs of the pe . results of both inner products computed during one operation step are accumulated and are passed to the two main outputs of the pe while the results of the point - by - point products are passed to the intermediate outputs of the pe . similar to the case of the type 1 core dwt architecture , it can be seen that the type 2 core dwt architecture implements algorithm 3 . 2 with time delay and time period characteristics given by ( 11 ) and ( 12 ). the other characteristics of the type 1 and type 2 architectures are also similar . in particular , the type 2 architecture is very fast , may be implemented as a semisystolic architecture and with a varying level of parallelism , providing an opportunity for creating a trade - off between time and hardware complexities . a difference between these two architectures is that the shift registers of data routing blocks of the type 1 core dwt architecture are replaced with additional connections between pes within the type 2 core dwt architecture . a possible structure of the jth pipeline stage , j = 1 , . . . , j , for the type 2 core dwt architecture is depicted in fig9 . an example of such a realisation for the case l max = 6 , j = 3 and p = 2 is shown in fig1 . in this realisation the data routing block consists of q j chain connected groups of 2 j − j + 1 delays each , and a shift register of length l max − 2 which shifts the values upwards by p positions every time unit . the 2 j − j + 1 inputs to the stage are connected in parallel to the first group of delays , the outputs of which are connected to the inputs of the next group of delays etc . the outputs of the last { circumflex over ( q )} j th group of delays form the first 2 j − j + 1 outputs of the data routing block and are connected to the main inputs of the pes . the outputs of the ({ circumflex over ( q )} j − t ) th group of delays , t = 1 , . . . , { circumflex over ( q )} j − 1 , are connected in parallel to the 2 j − j + 1 consecutive cells of the shift register . the outputs of the ({ circumflex over ( q )} j − 1 ) st group of delays are connected to the first 2 j − j + 1 cells , the outputs of the ({ circumflex over ( q )} j − 2 ) nd group of delays are connected to the next 2 j − j + 1 cells etc . however , the first q j =( l max − 2 )−( q j − 1 ) 2 j − j + 1 inputs of the stage are directly connected to the last q j cells of the shift register . the outputs from the first p − 2 cells of the shift register form the last p − 2 outputs of the data routing block and are connected to the main inputs of the pes according to the connections within the general structure . it can be shown that the presented realization satisfies the functionality constraint for the data routing block of the type 2 core dwt architecture . indeed , at the beginning of every step , the first 2 j − j + 1 + p − 2 components of the vector being the concatenation ( in the chronological order ) of the vectors accepted at previous { circumflex over ( q )} j steps are formed at the outputs of the data routing block and then during every following time unit the next p components of that vector are formed at its last p outputs . a possible pe structure for the type 2 core dwt architecture for the case of p = 2 is presented in fig1 , b . it will be apparent to one of ordinary skill in the art that structures for arbitrary p and for p = 1 , p = 2 , and p = l max , can be designed similar to those illustrated in fig8 ,( a ),( b ),( c ), and ( d ). it should be noted that in the case p = l max this realisation of the type 2 core dwt architecture is the same as the realisation of the type 1 core dwt architecture depicted in fig6 . the two types of core dwt architectures described above may be implemented with varying levels of parallelism depending on the parameter p . further flexibility in the level of parallelism is achieved within multi - core dwt architectures by introducing a new parameter r = 1 , . . . , 2 m − j . the multi - core dwt architecture is , in fact obtained from a corresponding single - core dwt architecture by expanding it r times . its general structure is presented on fig1 . the architecture consists of a data input block and j pipeline stages each stage containing a data routing block and a block of pes . the data input block may be realized as word - serial or as word - parallel in a way similar to the case of core dwt architectures but in this case it now has r2 j parallel outputs . which are connected to the r2 j inputs of the data routing block of the first pipeline stage . the functionality of the data input block is to serially or parallelly accept and parallelly output a group of components of the input vector at the rate of r2 j components per operation step . consider firstly the type 1 multi - core dwt architecture . in this case , the jth pipeline stage , j = 1 , . . . , j , consists of a data routing block having r2 j − j + 1 inputs i ps ( j ) ( 0 ), ), i ps ( j ) ( r2 j − j + 1 − 1 ) forming the input to the stage , and r2 j − j + 1 + p − 2 outputs o drb ( j ) ( 0 ), , o drb ( j ) ( r2 j − j + 1 + p − 3 ) connected to the inputs of r2 j − j pes . every pe has p inputs and two outputs where p ≦ l max is a parameter of the realisation describing the level of parallelism of every pe . consecutive p outputs o drb ( j ) ( 2i ), o drb ( j ) ( 2i + 1 ), . . . , o drb ( j ) ( 2i + p − 1 ) of the data routing block of the jth , j = 1 , . . . , j , stage are connected to the p inputs of the ith , i = 0 , . . . , r2 j − j − 1 , pe ( pe j , i ) of the same stage . first outputs of r2 j − j pes of the jth pipeline stage , j = 1 , . . . , j − 1 , form the outputs o ps ( j ) ( 0 ), , o ps ( j ) ( r2 j − j − 1 ) of that stage and are connected to the r2 j − j inputs i ps ( j + 1 ) ( 0 ), , i ps ( j + 1 ) ( r2 j − j − 1 ) of the data routing block of the next , ( j + 1 ) st , stage . first outputs of r pes of the last , jth , stage form first r outputs out ( 0 ), . . . , out ( r − 1 ) of the architecture . second outputs of r2 j − j pes of the jth pipeline stage , j = 1 , . . . , j , form the ( r2 j − j ) th to ( r2 j − j + 1 − 1 ) st outputs out ( r2 j − j ), . . . , out ( r2 j − j + 1 − 1 ) of the architecture . the data routing block ( of the stage j = 1 , . . . , j ,) can , in general , be realized as an arbitrary circuitry which at the first time unit n = 0 of its every operation step parallelly accepts a vector of r2 j − j + 1 components , and then at every time unit n = 0 , . . . , l p − 1 of that operation step it parallelly outputs a vector of r2 j − j + 1 + p − 2 components np , np + 1 , . . . ,( n + 1 ) p + r2 j − j − 3 of a vector being the concatenation ( in chronological order ) of the vectors accepted at previous { circumflex over ( q )} j steps ( see ( 8 )). the functionality of the pes is exactly the same as in the case of the type 1 core dwt architecture . consider now the type 2 multi - core dwt architecture . the data input block is exactly the same as in the case of the type 1 multi - core dwt architecture . pes used in the type 2 multi - core dwt architecture and interconnections between them are similar to the case of the type 2 ( single )- core dwt architecture . the difference is that now there are r2 j − j ( instead of 2 j − j ) pes within the jth pipeline stage , j = 1 , . . . , j , of the architecture . data routing block has now r2 j − j + 1 inputs and r2 j − j + 1 + p − 2 outputs with similar connections to pes as in the case of the type 1 multi - core dwt architecture . the data routing block ( of the stage j = 1 , . . . , j ,) can , in general , be realized as an arbitrary circuitry which at the first time unit n = 0 of its every operation step parallelly accepts a vector of r2 j − j + 1 components , and parallelly outputs a vector of the first r2 j − j + 1 + p − 2 components 0 , 1 , . . . , r2 j − j + 1 + p − 3 of a vector being the concatenation ( in the chronological order ) of the vectors accepted at previous { circumflex over ( q )} j steps . then at every time unit n = 0 , . . . , l p − 1 of that operation step it parallelly outputs next subvector of p components r2 j − j + 1 + np − 2 , . . . , r2 j − j + 1 +( n + 1 ) p − 3 of the same vector on its last p outputs . the both types of multi - core dwt architectures are r times faster than the single - core dwt architectures , that is a linear speed - up with respect to the parameter r is achieved . the delay between input and corresponding output vectors is equal to t d ( c 1 )=( 2 m − j + ŝ ( j )[ l / p ]/ r ( 14 ) time units . thus further speed - up and flexibility for trade - off between time and hardware complexities is achieved within multi - core dwt architectures . in addition , the architectures are modular and regular and may be implemented as semisystolic arrays . as a possible realisation of the multi - core dwt architecture for the case of p = l = l max and r = 2 m − j the dwt flowgraph itself ( see fig2 ) may be considered where nodes ( rectangles ) represent pes and small circles represent latches . the above - described architectures implement dwts with the number of octaves not exceeding a given number j . they may implement dwts with smaller than j number of octaves though with some loss in hardware utilisation . the variable resolution dwt architecture implements dwts with an arbitrary number j ′ of octaves whereas the efficiency of the architecture remains approximately 100 % whenever j ′ is larger than or equal to a given number j min . the general structure of the variable resolution dwt architecture is shown on fig1 ( a ). it consists of a core dwt architecture corresponding to j min decomposition levels and an arbitrary serial dwt architecture , for , instance , an rpa - based one ([ 14 ]-[ 17 ], [ 19 ]-[ 20 ], [ 22 ]). the core dwt architecture implements the first j min octaves of the j ′- octave dwt . the low - pass results from the out ( 0 ) of the core dwt architecture are passed to the serial dwt architecture . the serial dwt architecture implements the last j ′− j min octaves of the j ′- octave dwt . since the core dwt architecture may be implemented with varying level of parallelism it can be balanced with the serial dwt architecture in such a way that approximately 100 % of hardware utilisation is achieved whenever j ′≧ j min . to achieve the balancing between the two parts the core dwt architecture must implemement a j min - octave n - point dwt with the same throughput or faster as the serial architecture implements ( j ′− j min )- octave m - point dwt ( m =( n / 2 j min )). serial architectures found in the literature implement a m - point dwt either in 2m time units ([ 14 ], [ 15 ]) or in m time units ([ 14 ]-[ 19 ]) correspondingly employing either l or 2l basic units ( bus , multiplier - adder pairs ). they can be scaled down to contain an arbitrary number k ≦ 2l of bus so that an m - point dwt would be implemented in m ┌ 2l / k ┐ time units . since the ( type 1 or type 2 ) core dwt architecture implements a j min - octave n - point dwt in n ┌ l / p ┐/ 2 j min time units the balancing condition becomes ┌ l / p ┐≦┌ 2l / k ┐ which will be satisfied if p =┌ k / 2 ┐. with this condition the variable resolution dwt architecture will consist of a total number a = 2 ⁢ p ⁡ ( 2 j min - 1 ) + k = { ⁢ k2 j min , if ⁢ ⁢ k ⁢ ⁢ is ⁢ ⁢ even ⁢ ( k + 1 ) ⁢ 2 j min - 1 , if ⁢ ⁢ k ⁢ ⁢ is ⁢ ⁢ odd a variable resolution dwt architecture based on a multi - core dwt architecture may also be constructed ( see fig1 ( b )) where now a data routing block is inserted between the multi - core and serial dwt architectures . the functionality of the data routing block is to parallelly accept and serially output digits at the rate of r samples per operation step . the balancing condition in this case is rp =┌ k / 2 ┐, and the area time characteristics are a = 2 ⁢ pr ⁡ ( 2 j min - 1 ) + k = { ⁢ k2 j min , if ⁢ ⁢ k ⁢ ⁢ is ⁢ ⁢ even ( k + 1 ) ⁢ 2 j min - 1 , if ⁢ ⁢ k ⁢ ⁢ is ⁢ ⁢ odd , table 1 presents a comparative performance of the proposed architectures with some conventional architectures . in this table , as it is commonly accepted in the literature , the area of the architectures was counted as the number of used multiplier - adder pairs which are the basic units ( bus ) in dwt architectures . the time unit is counted as time period of one multiplication since this is the critical pipeline stage . characteristics of the dwt architectures proposed according to the invention shown in the last seven rows in table 1 , are given as for arbitrary realisation parameters l max , p , and r as well as for some examples of parameter choices . it should be mentioned that the numbers of bus used in the proposed architectures are given assuming the pe examples of fig8 ( where pe with p inputs contains 2p bus ). however , pes could be further optimized to involve less number of bus . for convenience , in table 2 numerical examples of area - time characteristics are presented for the choice of the dwt parameters j = 3 or j = 4 , n = 1024 , and l = 9 ( which corresponds to the most popular dwt , the daubechies 9 / 7 wavelet ). table 3 presents numerical examples for the case j = 3 or j = 4 , n = 1024 , and 5 ( the daubechies 5 / 3 wavelet ). the gate counts presented in these tables have been found assuming that a bu consists of a 16 - bit booth multiplier followed by a hierarchical 32 - bit adder and thus involves a total of 1914 gates ( see [ 37 ]). fig1 gives a graphical representation of some rows from table 2 . it should be noted that the line corresponding to the proposed architectures may be continued much longer though these non - present cases require rather large silicon area which might be impractical at the current state of the technology . as follows from these illustrations , the proposed architectures , compared to the conventional ones , demonstrate excellent time characteristics at moderate area requirements . advantages of the proposed architectures are best seen when considering the performances with respect to at p 2 criterion , which is commonly used to estimate performances of high - speed oriented architectures . note that the first row of the tables represent a general purpose dsp architecture . architectures presented in the next two rows are either non - pipelined or restricted ( only two stage ) pipelined ones and they operate at approximately 100 % hardware utilisation as is the case for our proposed architectures . so their performance is “ proportional ” to the performance of our architectures which however are much more flexible in the level of parallelism resulting in a wide range of time and area complexities . the fourth row of the tables presents j stage pipelined architectures with poor hardware utilisation and consequently a poor performance . the fifth to seventh rows of the tables present architectures from previous publications which are j stage pipelined and achieve 100 % hardware utilisation and good performance but do not allow a flexible range of area and time complexities as do the architectures proposed according to the invention . in the foregoing there has been discussion of general structures of “ universal ” wavelet transformers which are able to implement the wavelet transform with arbitrary parameters such as the filter lengths and coefficients , input length , and the number of decomposition levels . further optimisation of architectures for a specific discrete wavelet transform ( corresponding to a specific set of above parameters ) is possible by optimizing the structure of processing elements ( pes ) included in the architecture . the invention can be implemented as a dedicated semisystolic vlsi circuit using cmos technology . this can be either a stand - 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