Patent Application: US-201514808506-A

Abstract:
a routing architecture for fast interconnections between look - up tables in a group of basic logic elements , whereby a size of the group ranges from 1 to k + 1 , where k is the number of inputs of a lut , and luts in the group are indexed from 1 to k + 1 , and whereby an output of a lut i , 1 ≦ i ≦ k , connects to one of the inputs of routing multiplexers of lut j , i & lt ; j ≦ k + 1 , hence creating a fast interconnection between luts , each routing multiplexer of lut m , 2 ≦ m ≦ k + 1 , has only one input that is connected to the output of an other lut , the output of lut being devoid of any connection to any one of the inputs of the routing multiplexers ; a subset of the inputs of lut 1 are connected to the outputs of other luts by means of fast interconnections , leaving the remaining inputs of lut 1 free of any fast interconnection , whereby for lut p , 2 ≦ p ≦ k + 1 , p − 1 inputs of the lut p are connected to the outputs of lut q , 1 ≦ q ≦ j , by means of fast interconnections ; and a cluster - based logic block contains at least one group of luts .

Description:
ii . background in this section , the classical cluster - based logic block architecture and clustering algorithms are reviewed . modern fpgas use an island - style architecture , where logic blocks are surrounded by pre - fabricated routing resources . the logic block themselves are composed of basic logic elements ( bles ) and a fully interconnected local routing [ 1 ]. fig1 illustrates the architecture of a classical cluster - based logic block . a cluster - based logic block consists of a number n of bles . each ble contains a k - input lut , a dff and a 2 : 1 multiplexer . a ble realizes fine - grain combinational or sequential operations . its mode of operation ( combinational or sequential ) is controlled by the 2 : 1 multiplexer . local routing , composed of a large set of multiplexers , can route any outputs of bles to their inputs , enhancing the inner logic block routability . the logic block features i inputs that come from the global routing . given k and n , setting i = k ( n + 1 )/ 2 ensures that 98 % bles are utilized on average [ 5 ]. to efficiently pack luts and dffs into cluster - based logic block , clustering algorithms are of fundamental importance . modern fpga clustering algorithms can be grouped into two categories : seed - based and partition - based . seed - based clustering algorithms select a seed ble with the highest criticality , pack it into a logic block and continue to absorb bles until the logic block cannot accommodate any more . different seed - based packers use different criticality and at - traction functions to achieve diverse objective efficiencies . vpack [ 6 ] aims to absorb as much nets as possible . t - vpack [ 7 ] adds critical path optimization . to improve routability , t - rpack [ 8 ] and irac [ 9 ] absorb low - fanout nets . partition - based clustering algorithm , such as ppack [ 10 ] and t - ppack [ 10 ] depends on a graph partitioner [ 11 ] to cut the circuits into small parts and then modify the results to fit clb capacity . hd - pack [ 12 ] carries out seed - based clustering algorithm after a virtual placement with graph partitioner . nevertheless , the above packers only support classical logic blocks [ 1 ]. developed for general purpose packing , aa - pack [ 14 ] adapts the techniques used in hd - pack , irac and tv - pack to pack heterogeneous logic blocks and supports flexible local routing architectures inside the logic blocks , bringing novel opportunities to study the inner logic block routing . therefore , we focus on introducing aa - pack . aa - pack groups luts and dffs into logic blocks in two steps . in the first step , called pre - pack , luts and dffs are packed into bles , as shown in fig2 . note that in fig2 ( b ), an additional ble has to be created due to the limited fanout of the ble architecture [ 1 ]. in combinational mode , the pre - packing step increases the critical path . indeed , the lut output has to pass through the 2 : 1 multiplexer before reaching the local routing , while additional luts may be inserted to accommodate large fanouts . in circuits with short critical path , for instance control - intensive circuits , the critical path can be prolonged significantly . after pre - pack , timing analysis is carried out and timing slacks are marked for each ble , preparing for timing - driven clustering . aa - pack 7 . 0 con - ducts accurate timing - analysis by considering the architecture physical information and modeling the inner - cluster delay and inter - cluster delay . in the second step , aa - pack pack bles into logic blocks . it starts by initializing an empty logic block , then chooses a seed and uses an attraction function to select the candidate block , b , to fill in . the attraction function is composed of two parts : the first part is used in tv - pack [ 7 ] as criticality and the second is the attraction function used in aa - pack 6 . 0 [ 13 ]. the parameter a yields good performance [ 13 ] when sets to 0 . 75 . when two candidates b1 and b2 have the same attraction , aa - pack selects the one with largest number of critical / near critical paths , called pathaffects [ 1 ], passing through . if the two candidates have the same pathaffects , aa - pack selects the one with largest depth from critical path source , called d source [ 1 ]. in aa - pack 7 . 0 , each time the most “ attractive ” candidate is chosen , a local router is speculatively called to determine whether the candidate can be accepted . when the logic block is full , aa - pack starts another iteration until all bles are packed . besides , aa - pack 7 . 0 enhances routability by intra - logic block placement , which is out of the scope of this paper , and thus not discussed . in this section , we introduce our novel pattern - based fpga logic block architecture . patterns are defined as groups of luts , among which there exist fast combinational interconnections . in the first part , we investigate the combinational interconnections among luts . in the second part , the new logic block architecture is presented . to improve the routing of combinational paths , we study the different interconnection possibilities between luts . we first formulate the following characteristics of luts : c1 ) all the inputs of a lut are logic equivalent , and thus are swappable . c2 ) luts ( actually any combinational logic gate ) cannot have combinational loops , which means that the interconnections among luts are acyclic . c3 ) any two inputs of a lut ( actually any combinational logic gate ) cannot share the output of a same lut , otherwise these shared inputs can be reduced to one . c4 ) combining c2 with c3 , there should be only one combinational connection between two luts . thanks to the above characteristics , the number of combinational interconnection patterns between luts is limited . we define m as the size of the pattern . it corresponds to the number of luts involved in the pattern . note that we limit our study to k ≧ m . in the following , we study the cases of pattern - 2 and pattern - 3 , then we generalize to pattern - m . 1 ) pattern - 2 : fig3 illustrates all possible interconnection cases between two k - luts and demonstrates the pattern covering all possibilities . more specifically , fig3 ( a ) and 3 ( b ) contain 2 k - luts that are directly connected ; fig3 ( c ) contains 2 k - luts that are independent , fig3 ( d ) contains 2 k - luts that are indirectly connected , and fig3 ( e ) contains an interconnection pattern covering ( a )( b )( c )( d ). given two k - luts ( tagged 1 and 2 ), only two cases can be identified for their interconnections . first , a direct connection may exist between the output of one lut and one of the inputs of the second lut . in fig3 ( a ), the output of lut1 is connected to an input of lut2 . from c4 , there should be only one interconnection between lut1 and lut2 , and by applying c1 , we can always keep the output of lut 1 connected to the input in0 of lut2 . note that when using local routing in cluster - based logic block , lut1 and lut2 are swappable . thus , fig3 ( b ) can be regarded as equivalent to fig3 ( a ). second , inputs of lut1 and lut2 can be fully independent as shown in fig3 ( c ). for instance , all the lut inputs are connected to different primary inputs , luts or dffs . fig3 ( d ) presents a possibility where the output of lut1 is connected to the input of lut2 through other luts . fig3 ( c ) and ( d ) can be regarded as equivalent because they are all connected through the local routing . therefore , when two luts are considered , only two cases ( fig3 ( a ) and ( c )) should be considered . hence , we can create a universal structure able to map these different configurations by adding one multiplexer as shown in fig3 ( e ). this structure is called pattern - 2 , and can realize all the interconnection patterns between 2 luts . 2 ) pattern - 3 to pattern - m : based on the pattern - 2 organization , we can extend the structure to three luts ( tagged 1 , 2 and 3 ). referring to fig4 , this illustrates all possible combinational interconnections between 3 k - luts . fig4 ( a ) and 4 ( b ) contain 3rd k - lut that is independent ; fig4 ( c ) shows one example of 3rd k - lut connected to one of the other luts ; fig4 ( d ) shows 3rd k - lut that is connected to all the other luts ; fig4 ( e ) shows an interconnection pattern covering ( a )( b )( c )( d ); and fig4 ( f ) shows an interconnection pattern of m luts . first , fig4 ( a ) shows the case where the inputs of lut3 are fully independent from lut1 and lut2 . then , we can repeat the same reasoning that previously for direct connections between luts . fig4 ( b )( c )( d ) list all the possible cases where the inputs of lut3 are connected to the outputs of lut1 and lut2 . the cases where the output of lut3 is connected to the inputs of lut 1 and lut2 are not listed but can be regarded as equivalent to fig4 ( b )( c )( d ) by swapping lut3 with lut1 or lut2 . considering all the cases in fig4 ( a )( b )( c )( d ), pattern - 3 is proposed in fig4 ( e ). on a general basis , we can extend the pattern size from 3 to m . since pattern -( m − 1 ) covers all possible interconnections among ( m − 1 ) luts , pattern - m can be achieved by adding another lut ( tagged m ). the number of inputs of lut m connected to pattern -( m − 1 ) ranges from 0 to ( m − 1 ). hence , ( m − 1 ) 2 : 1 multiplexer can be added to each input of lut m as depicted in fig4 ( f ). to build a logic block based on a pattern - m , the extra 2 : 1 multiplexers of the patterns can be included ( i ) in an independent layer between local routing and bles , providing ultra - fast shortcuts at the cost of more delay from logic block inputs to luts ; or ( ii ) merged into the local routing . in this paper , we study the second case for simplicity . the ble architecture remains unchanged and we simply feedback the outputs of luts to the local routing . the signal feedback increases the size of half of local routing multiplexers by one additional input . modern fpga architectures typically use 6 - input luts in their logic blocks . we therefore employ a pattern - 7 organization . the schematic of a pattern - 7 logic block is given in fig5 . the use of larger multiplexers leads to 0 . 45 % area overhead . the fast combinational interconnections between luts are highlighted in thicker lines . note that a pattern - based logic block can also contain multiple pattern - m . in this paper , we focus only on single pattern logic blocks to evaluate the efficiency of the approach . to support the introduced pattern - based architecture , we develop a new clustering algorithm . while inspired from seed - based algorithms , it aims at attracting patterns rather than single bles . a pattern candidate is composed of a seed ble and its unpacked predecessors . the predecessor selections is bounded by the maximum pattern size available in the cluster . our pattern - based algorithm adapts the attraction functions as well as pathaffects identification of aa - pack . let lb denotes the logic block , p a pattern and b i the bles involved in the pattern p . as each time we absorb a pattern including a number of b i ble candidates . we define the attraction function as the sum of the attraction ( 1 ) of each candidate b i . area attraction function is modified to increase the absorption of logic block outputs : where share_input_nets ( lb , b i ) is the number of input nets shared by lb and b i , and absorbed_output_nets denotes the number of output nets of lb absorbed by b i . in our experiments , parameters ( α , β )=( 0 . 75 , 0 . 9 ) yield good performance . similarly , we define pathaffects ( p ) as the average of the pathaffect of each candidate b i : and d source of a pattern as the average of the d source of each candidate b i . the pseudo code of the clustering algorithm is shown in algorithm 1 . during the pre - pack stage , additional luts are added to those have more combinational outputs than the maximum size of interconnection patterns supported by the logic block . then , a new empty logic block is instantiated and we select suitable pattern candidate . the patterns are selected according to the maximum size that the current logic block can support . for the example in fig5 , if all the bles are not yet assigned , the maximum pattern size is 7 . searching from largest pattern size to the lowest , i . e ., a single ble , we select the candidate with the largest attraction ( 2 ). exceptionally for seed pattern , average attraction ( 2 ) is used to achieve better routability . if the chosen pattern passes the local router test , the pattern is inserted into logic block . this procedure is iterated until the netlist is mapped . in this section , experimental results are presented . experimental methodology is first introduced , and followed by the discussion of the results . modern fpgas use 6 - input luts . therefore , we consider pattern - 7 as a reasonable size to investigate the new logic block architecture . logic block architecture is set as k = 6 , n = 7 , i = k ( n + 1 )/ 2 = 24 . as for routing architecture and physical design parameters , we refer to the altera stratix iv gx device at 40 - nm technology , available from ifar [ 16 ]. routing architecture uses single - driver length - 4 wires [ 17 ], with f c ( in )= 0 . 15 , f c ( out )= 0 . 10 . benchmark set includes the 20 biggest mcnc benchmarks [ 18 ], mcnc finite state machine ( fsm ) benchmarks [ 18 ] and some opencores projects [ 19 ]. we evaluate the pattern - based architecture and clustering algorithm by running 3 sets of experiments : 1 ) the standard cad flow shown in fig6 ( a ) with a standard baseline architecture to serve as reference ; 2 ) the same standard flow with the novel pattern - based architecture to evaluate the promises of the novel architecture ; and 3 ) the pattern - based cad flow shown in fig6 ( b ) with pattern - based architecture to evaluate the joint efforts of architecture and clustering algorithm . all benchmarks pass through logic synthesis by abc [ 20 ]. then they are packed by pattern - based packer or aa - pack , and placed and routed by vpr 7 [ 13 ]. table 1 lists the results of the 3 sets of experiments . we first compare the results obtained using the standard flow , then we comment on the new flow . 1 ) standard architecture — standard flow vs . pattern architecture — standard flow : in this comparison , we evaluate the potential of pattern architecture by using standard flow . table i compares the area , critical delay and wirelength between a standard architecture and the novel pattern architecture using the same cad flow . in mcnc fsm benchmarks , pattern architecture with standard flow increases area by 5 %, critical delay by 5 % with a 9 % reduction in wirelength , on average . in mcnc big20 benchmarks , pattern architecture consumes additional 9 % area , 1 % delay and 9 % wirelength on average . in opencores projects , pattern architecture with standard flow gains a 10 % in delay at a cost of 34 % area and 11 % wirelength overheads . aa - pack has no preference in taking the advantages of the fast combinational paths in pattern while the additional fanout offered by patterns alters the area attraction [ 15 ], and results in performance loss . in opencores projects , pattern architecture obtains decent reduction in delay which implies that pattern architecture can instruct aa - pack to produce better performance even without utilizing the fast combinational paths . in some benchmarks , such as mark1 , ac 97ctrl and pci conf cyc addr dec , pattern architecture produces very significant gain in delay and wirelength . 2 ) standard architecture — standard flow vs . pattern architecture — pattern flow : in this comparison , we evaluate the performance of our pattern - based flow . as shown in table i , we compare the area , critical delay and wirelength between standard flow with standard architecture and pattern - based flow with pattern - based architecture . in mcnc fsm benchmarks , compared to the standard flow in fig6 ( a ), pattern - based flow achieves a 16 % delay reduction , a 24 % wirelength reduction with only 1 % area overhead on average . most mcnc fsm benchmarks can be packed into less than 10 logic blocks , clearly indicating the strong potential of pattern - based architecture . taking the example of circuit lion that consists of 3 luts , pattern - based flow achieves 40 % gain in delay . for mcnc big20 benchmarks , pattern - based flow perform slightly worse than standard , with 1 % overhead in area , 4 % in delay , and 5 % in wirelength on average . in opencores projects , pattern - based flow increases 3 % area and shrinks 14 % in delay and 8 % in wirelength on average . compared to the results gathered with the standard flow , the pattern - based packer reduces the area overhead and increases the gain in delay . delay improvements are accounted for the fast combinational paths and for the reduction of additional luts to accommodate large fanouts . critical paths of mcnc fsm benchmarks and selected opencores projects are shorter compared to mcnc big20 , which makes delay gain significant . the limited area loss comes from the pattern - based candidate selection , which tends to group luts that are intensively connected to each other instead of simply greedily absorbing the nets . wirelength gains are accounted for ( i ) the novel logic block that can absorb more nets , and for ( ii ) the pattern - based clustering algorithm that packs the circuits with a global optimization instead of local scope on optimality . in the present description , we investigated the interconnection patterns of luts inside standard cluster - based logic blocks and proposed a novel pattern - based logic block architecture . providing fast combinational path between luts , pattern - based logic block generates 0 . 45 % area overhead when lut size is 6 . to take the advantage of fast combinational paths , a pattern - based clustering algorithm is proposed . experimental results demonstrate that in mcnc fsm benchmarks and opencores projects , pattern - based logic block architecture and clustering algorithm contribute to 14 % reduction in critical delay and 8 % shrink in wirelength with 3 % area overhead , on average , compared to standard logic block architecture . this work has been partially supported by the erc senior grant nanosys erc - 2009 - adg - 246810 . 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