Patent Application: US-201313899666-A

Abstract:
this invention describes a novel electronic device consisting of one — or more — vertically stacked gate - all - around silicon nanowire field effect transistor with two independent gate electrodes . one of the two gate electrodes , acting on the central section of the transistor channel , controls on / off behavior of the channel . the second gate , acting on the regions in proximity to the source and the drain of the transistor , defines the polarity of the devices , i . e . p or n type . the electric field of the second gate acts either at the interface of the nanowire - to - source / drain region or anywhere in close proximity to the depleted region of the sinw body , modulating the bending of the schottky barriers at the contacts , eventually screening one type of charge carrier to pass through the channel of the transistor . this is achieved by controlling the majority carriers passing through the transistor channel by regulating the schottky barrier thicknesses at the source and drain contacts .

Description:
three non - limiting examples of processes , which can be used with the present invention , are presented below . in a 1 st example , the main steps of the device fabrication procedure are listed in fig1 a . generally , the process includes creating a device channel , that is , a transistor channel 1 ( fig2 j below ), which can be composed of a vertical stack of a variable number of horizontal semiconducting nanowires , a parallel array of vertical stacks of horizontal nanowires , a fin - like structure ( from which a finfet transistor would be obtained ) or a graphene ribbon . we will use the nanowire stack further on in this description as an example . fig2 b shows a cross section of the nanowire stack , with two pillar - like structures sustaining the nanowires , while fig2 a shows the top view of such stack . after the channel structure is fabricated , a first gate insulator covering the channel section of the transistor is created . this gate insulator can be produced by direct oxidation of the transistor channel , or by deposition of various high - k dielectric materials . a 1st gate electrode is deposited over the 1st gate insulator , and patterned to obtain a gate structure covering the side regions of the transistor channel ( fig2 c and 2d ). this 1st gate structure will approach or partly overlap the regions where source / drain contacts will be formed . after the first gate electrode is fabricated , a second gate insulator is created in order to isolate the center region of the device , and a second gate electrode is deposited and patterned to act on the central region of the device . this second gate can be created by self - alignment to the 1 st gate electrode ( fig2 e and 2f ). after the second gate is formed , a spacer is formed by deposition and etching of a dielectric material such as silicon nitride ( fig2 g and 2h ), in order to isolate gate electrodes and source / drain regions further on , when contacts will be formed . finally , an interface region 2 of the device is covered with a metal exhibiting near mid - gap work - function with respect to the channel semiconductor material ( fig2 i and 2j . by annealing , a silicide can be formed to create desired a schottky barrier interface 3 at the two sides of the device channel , that is , the transistor channel 1 , so that source / drain schottky barriers approach or are covered by the first gate electrode ( fig2 k and 2l ). in a 2 nd example , a single si nanowire with double independent gates , that is , schottky barrier interfaces 4 , is fabricated ( see top view of fig3 a ). a low doping p - type ( n a ˜ 10 15 atoms / cm 2 ) soi wafer with 1 . 5 μm device layer is spin coated . the photoresist is then patterned in 1 . 5 um wide lines ( see fig3 b ) and used as mask for a next isotropic si etching . a si plasma etching recipe is tuned to form a triangular 75 nm wide si nanowire lying on top of the buried oxide ( box ) layer ( fig3 c ). the si nanowire is a transistor channel 5 in this embodiment . then a 30 nm thick gate oxidation and a 150 nm polysilicon layer are deposited with a low - pressure chemical vapor deposition ( lpcvd ) method to form a main gate with 7 . 5 μm length ( gate 1 , fig3 d ). 300 nm lpcvd low temperature oxide ( lto ) is used to isolate the main gate . a second 500 nm polysilicon layer is then deposited . then a thick photoresist is spun over the wafer and planarized using a chemical mechanical polishing procedure . this method leaves a protective polymer layer that is used to etch a second polysilicon gate self - aligned within the cavity thanks to the topography ( see gate 2 in fig3 e ). after standard cleaning steps , one additional patterning of gate 2 is performed to remove the unnecessary polysilicon and to form areas for the contacts ( see the top view of the device in fig3 a ). in fig3 f a focused ion beam cross - section of the triangular sinw channel , that is , a depleted region 6 , with the double independent gate stack is shown . then source / drain contacts are formed by means of nisi silicidation in a horizontal wall furnace in forming gas at 400 ° c . finally al metal lines and pad area are defined for the electrical characterization . in a 3 rd example , vertical si nanowires with double independent gate all - around are fabricated ( see fig4 a ). the si nanowires are vertically etched in parallel on 10 soi wafers after having patterned a sio2 hard mask by lithography ( fig4 b and fig4 c ). the si nanowire are then freestanding and anchored at the bottom where a si layer is still left for subsequent processing ( fig4 c ). then a sio 2 or a si 3 n 4 layer is deposited all - around by lpcvd method on 9 and 1 soi wafer , respectively . then sio 2 / si 3 n 4 spacers are formed by vertical plasma etching in a dry etching tool ( fig4 d ). at this stage , the si nanowires are surrounded by a sio 2 or a si 3 n 4 dielectric , while the planar layer on top of the buried oxide and the top section of the si nanowires reveal a non - passivated si surface or with a native si oxide thinner than 10 angstroms . then another lithography defines the bottom layer that is etched in order to isolate the si nanowires ( fig4 e ). subsequently , a ni metal layer is deposited by electron beam evaporation and annealed at 450 ° c . in a rapid thermal annealing furnace with constant n2 flow for 20 seconds . the annealing process is carried out in order to form a thin nisi layer at the top and at the bottom of the si nanowires ; thus ni alloys with si due to the contact with si . for the si regions masked by the thick sio 2 or si 3 n 4 spacer , the ni metal cannot react with si . the sample is then dipped into a hot piranha solution in order to strip the unreacted ni layer , leaving only the nisi schottky barrier interface 7 and the si nanowire , that is , the depleted region 8 , structure surrounded by the dielectric mask , thanks to the etching selectivity between ni and nisi , si , sio 2 or si 3 n 4 in hot piranha solution ( see fig4 f ). for 8 soi wafers the sio2 surrounding the si nanowire is stripped by vapor hf method and replaced by one of the following high - k dielectrics , one per each soi wafer : 1 . hfo 2 ; 2 . tio 2 ; 3 . al 2 o 3 ; 4 . zro 2 ; 5 . hfsio ; 6 . hfsion ; 7 . ta 2 o 5 ; 8 . lead - zirconate - titanate ( pzt ); all the high - k dielectrics are deposited by atomic layer deposition ( ald ) system . subsequently to the high - k dielectric deposition , a 10 nm thin tin is deposited in the same ald equipment without breaking the vacuum . then the high - k samples are processed in a conventional dry etcher tool in order to remove the high - k material and the tin on top of the nisi regions ( fig4 g ). a transistor channel 9 is formed . then all the 10 soi wafers are covered by a 50 nm thick amorphous si layer deposited by lpcvd followed by a spin coating of a 50 nm thick hsq layer . after the hsq exposure in an e - beam lithography system , excessive amorphous si is etched isotropically in a dry etcher with a sf 6 / c 4 f 8 plasma with low bias to minimize ion bombardment and maximize the chemical reaction between sf , ions with the amorphous si . at this stage a first amorphous si gate surrounds the si nanowire portion close to the bottom nisi contact ( see fig4 h for sio 2 or si 3 n 4 dielectrics and fig4 i for high - k dielectrics ). then the amorphous si deposition step and hsq lithography are repeated in order to define a second independent gate ( see fig4 j for sio 2 / si 3 n 4 and fig4 k for the high - k / tin stack ). then another layer of amorphous si is deposited after capping the second independent gate with a dielectric . in this way the first gate is extended to the region in proximity of the top nisi to sinw contact ( see fig4 l for sio 2 / si 3 n 4 and fig4 m for the high - k / tin stack ). the tin in the high - k samples is then removed by dipping into a rca1 chemical solution at 60 ° c . for 60 s , thus isolating the two gates and the nisi contacts . then , the si nanowire structures are passivated in a low temperature oxide matrix deposited by lpcvd and via holes are etched on top of the nisi contacts and the gate vias . finally , chemical mechanical polishing and lift - off are used respectively to define w plugs and al wires . 1 . jia chen and edward j . nowak . “ complementary carbon nanotube triple gate technology ”, may 2007 . 2 . dimitris e . ioannou , souvick mitra , and akram salman . “ double gate ( dg ) soi ratioed logic with intrinsically on symmetric dg - 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