Patent Application: US-41732703-A

Abstract:
the present invention relates to a substantially planar substrate for use in patch clamp analysis of the electrophysiological properties of a cell membrane comprising a glycocalyx , wherein the substrate comprises an aperture having a rim , the rim being adapted to form a gigaseal upon contact with the cell membrane , the invention further provides a method of making such a substrate and method for analysing the electrophysiological properties of a cell membrane comprising a glycocalyx .

Description:
the present invention identifies three factors that are important for gigaseal formation and whole cell establishment in patch clamp measurements performed on living cells containing glycocalyx in the cell membrane : 1 . the length of the aperture should be sufficiently long in order to prevent the relatively elastic cells to be moved through the orifice upon application of suction . 2 . there also appears to exist an optimal aperture size for gigaseal formation and whole cell establishment which relates to the elastic properties of the cell membrane and the cell type being studied . 3 . the aperture of the planar substrate should be defined by a rim capable of displacing the glycocalyx when approaching the cell surface . the length ( i . e . depth ) of the aperture , defined by the membrane thickness of the chip , is also important . low aspect ratio designs ( short apertures ) suffer from the disadvantage that cells , upon positioning and subsequent suction , have a tendency to move through the hole due to their inherent elasticity . studies have demonstrated that this problem may be effectively obviated by using longer apertures , typically in excess of 2 μm ( data not shown ). to determine the optimal aperture size for obtaining gigaseal and whole cell configurations we have compared the success rates for achieving them in a standard patch - clamp set - up , using patch pipettes of varying size . the experiments were performed on hek293 cells adhered to coverslips , immersed in sodium ringer solution , borosilicate capillaries ( hilgenberg , cat no . 1403573 , l = 75 mm , od = 1 . 5 mm , id = 0 . 87 mm , 0 . 2 mm filament ) were used to make pipettes . pipette resistance was used as an indicator of relative aperture size ; pipettes with intended resistances of 0 . 5 , 1 , 2 , 5 , 10 and 15 mω were fabricated . at the time of measurement , the actual pipette resistance was noted and the average actual pipette resistance for each set , along with the standard deviation from the mean , is shown in fig3 . fig4 shows the dependence of gigaseal and whole - cell success rates on the pipette aperture resistance aperture size ). the number of experiments performed for each data set is shown above the data points . the results show that pipettes with a resistance of 5 mωwere optimal for both gigascal formation and whole cell establishment , while resistances above 5 , and up to 15 mω , resulted in an approximately 20 % drop in the success rate . reduction of pipette resistance below 5 mω was more deleterious ; a resistance of 2 mω gave a success rate or 50 %, 37 % lower than for 5 mω , while resistances of 1 mω or below resulted in virtually no gigaseal formation at all . fig5 shows the percentage of whole - cells formed from experiments in which gigaseals were successfully formed ( i . e . discounting those that did not reach gigaseal ). data indicate that although 5 mωpipettes had the highest whole - cell success rate , the other aperture sizes had only slightly lower successes . the effect of pipette resistance on the time taken to reach a gω resistance was also examined ( see fig6 ). the results show that the 2 mω pipettes took significantly longer to reach gigaseal than did pipettes of 5 , 10 or 15 mω . the similarity of the results for the 5 , 10 and 15 mω pipettes indicates that increasing the aperture size within this range does not affect the time take to reach gigaseal . the results clearly show that the success of gigaseal formation is dependent on the size of the pipette aperture . the 5 mω pipettes had the optimal aperture size , and sizes greater than this ( i . e . with lower resistances ) resulted in a marked reduction is successful gigaseal formation . although the above experiments were performed using conventional glass micropipettes , the results can be extrapolated to planar substrates for use in patch clamp experiments . thus , the results indicate that apertures in the chip system should , in general not measure larger than the apertures of the 5 mω pipettes . however , pipettes smaller than the 5 mω ones still performed fairly well , although they were significantly worse . therefore , making the chip aperture slightly smaller than the 5 mω pipettes would be less deleterious than making it larger . varying the pipette aperture size appeared to have less effect on whole - cell formation . although the success of whole - cell formation was highest in 5 mω pipettes , for pipettes from 2 mω to 15 mω , there was only a slight reduction in success rate . it was also observed that the pipette aperture size had an effect on the time taken to reach a gω resistance . pipettes of 5 and 15 mω took similar times to reach gigaseal , but those of 2 mω took 2 . 5 to 3 times longer . microscopy of the glass pipettes used in the experiments revealed that pipettes exhibiting 5 mω resistance had an aperture size of the order of 0 . 5 – 1 μm . it is , however , expected that the optimal aperture size is related to the cell type and cell size . the success - rate for obtaining gigaseals in conventional patch clamp experiments is typically high , often around 90 %, when patching cultured cells like hek or cho . based on the above considerations , it is expected that comparable success - rate on planar chips may be achieved using an aperture geometry mimicking that of a conventional pipette tip orifice . such a geometry would comprise a protruding rim flaking a 0 . 5 to 1 μm aperture hole . moreover , the length ( i . e . depth ) of the aperture should preferably be in excess of 2 μm . a preferred method of producing the planer patch - clamp substrates of tie invention is by using silicon ( si ) wafer micro - fabrication and processing methods , which allow si surfaces to be coated with silicon oxide effectively forming a high quality glass surface . preferably , long pores and the surface modification can be made by using icp ( inductively coupled plasma ) and lpcvd ( low pressure chemical vapour deposition ). long apertures with a protruding rim can be made by using icp to make the poreand rie ( reactive ion etch ) to form the protruding rim , combined with lpcvd to make the surface modification . ( a ) example process recipe for long apertures with a protruding rim in the plane of the surface using icp and lpcvd for surface modification ( fig1 a and fig1 b ). 1 . starting substrate : single crystal silicon wafer , crystal orientation & lt ; 100 & gt ;. 2 . one surface of the silicon is coated with photoresist and the pattern containing the aperture locations and diameters is transferred to the photoresist through exposure to uv light . 3 . the aperture pattern is transferred to the silicon with deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in deep vertical pores with a depth of 1 – 50 μm . 4 . the silicon surface is coated with a etch mask that will with stand koh or tmah solution . as an example this could be silicon oxide or silicon nitride . 5 . the opposite side of the wafer ( the bottom side ) is coated with photoresist and a pattern containing the membrane defining openings in the silicon nitride is transferred to the photoresist through exposure to uv light . 6 . the wafer is etched away on the bottom side of the wafer in the regions defined by the openings in the photoresist , using a suitable pattern transfer process . as an example this could be reactive ion etch ( rie ). 7 . the wafer is etched anisotropically in a koh or tmah solution , resulting in a pyramidal opening on the bottom side of the wafer . the timing of the etching defines the thickness of the remaining membrane of silicon at the topside of the wafer . alternatively boron doping can be used to define an etch stop , giving a better control of the thickness . 8 . the etch mask is remove selectively to the silicon substrate . 9 . the silicon is coated with silicon oxide , either through thermal oxidation , with plasma enhanced chemical vapor deposition ( pecvd ) or with lpcvd . 1 . starting substrate : single crystal silicon wafer . 2 . one surface of the silicon is coated with photoresist and the pattern containing the aperture locations and diameters is transferred to the photoresist through exposure to uv light . 3 . the aperture pattern is transferred to the silicon with deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in deep vertical pores with a depth of 1 – 50 μm . 4 . the opposite side of the wafer ( the bottom side ) is coated with photoresist and a pattern containing the membrane definitions is transferred to the photoresist through exposure to uv light . 5 . the wafer is etched anisotropically using deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in a cylindrical opening on the bottom side of the wafer . the timing of the etching defines the thickness of the remaining membrane of silicon at the topside of the wafer . 6 . the silicon is coated with silicon oxide , either through thermal oxidation , with plasma enhanced chemical vapor deposition ( pecvd ) or with lpcvd . 1 . starting substrate : silicon on insulator ( soi ) with a buried oxide layer located 1 – 50 μm below the top surface , carrier crystal orientation & lt ; 100 & gt ;. 2 . one surface of the silicon is coated with photoresist and the pattern containing the aperture locations and diameters is transferred to the photoresist through exposure to uv light . 3 . the aperture pattern is transferred to the silicon with deep reactive ion etch ( drie ) or advanced silicon etching ( asp ) using an inductively coupled plasma ( icp ), resulting in deep vertical pores down to the depth of the buried oxide layer . 4 . the silicon surface is coated with a etch mask that will with stand koh or tmah solution . as an example this could be silicon oxide or silicon nitride . 5 . the opposite side of the wafer ( the bottom side ) is coated with photoresist and a pattern containing the membrane defining openings in the silicon nitride is transferred to the photoresist through exposure to uv light . 6 . the wafer is etched away on the bottom side of the wafer in the regions defined by the openings in the photoresist , using a suitable pattern transfer process . as an example this could be reactive ion etch ( rie ). 7 . the wafer is etched anisotropically in a koh or tmah solution , resulting in a pyramidal opening on the bottom side of the wafer . the buried oxide will act as an etch stop for the process , hence thickness of the topside silicon layer defines the thickness of the remaining membrane . 8 . the exposed regions of the buried oxide layer are removed through rie , wet hydrofluoric acid ( hf ) etch , or hf vapor etch . this will ensure contact between the top and bottom openings in the wafer . 9 . the etch mask is remove selectively to the silicon substrate . 10 . the silicon is coated with silicon oxide , either through thermal oxidation , with plasma enhanced chemical vapor deposition ( pecvd ) or with lpcvd . 1 . starting substrate : silicon on insulator ( soi ) with a buried oxide layer located 1 – 50 μm below the top surface . 2 . one surface of the silicon is coated with photoresist and the pattern containing the aperture locations and diameters is transferred to the photoresist through exposure to uv light . 3 . the aperture pattern is transferred to the silicon with deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in deep vertical pores down to the depth of the buried oxide layer . 4 . the opposite side of the wafer ( the bottom side ) is coated with photoresist and a pattern containing the membrane definitions is transferred to the photoresist through exposure to uv light . 5 . the wafer is etched anisotropically using deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in vertical cavities on the bottom side of the wafer . the buried oxide will act as an etch stop for the process , hence thickness of the topside silicon layer defines the thickness of the remaining membrane . 6 . the exposed regions of the buried oxide layer are removed through rie , wet hydrofluoric acid ( hf ) etch , or hf vapor etch . this will ensure contact between the top and bottom openings in the wafer . 7 . the silicon is coated with silicon oxide , either through thermal oxidation , with plasma enhanced chemical vapor deposition ( pecvd ) or with lpcvd . 1 . starting substrate : glass or pyrex wafer . 2 . one surface of the silicon is coated with photoresist and the pattern containing the aperture locations and diameters is transferred to the photoresist through exposure to uv light . 3 . the aperture pattern is transferred to the wafer with deep reactive ion etch ( drie ) or advanced oxide etching ( aoe ) using an inductively coupled plasma ( icp ), resulting in deep vertical pores with a depth of 1 – 50 μm . 4 . the opposite side of the wafer ( the bottom side ) is coated with photoresist and a pattern containing the membrane definitions is transferred to the photoresist through exposure to uv light . 5 . the wafer is etched anisotropically using deep reactive ion etch ( drie ) or advanced oxide etching ( aoe ) using an inductively coupled plasma ( icp ), resulting in vertical cavities on the bottom side of the wafer . the timing of the etching defines the thickness of the remaining membrane of glass or pyrex at the topside of the wafer . 6 . the silicon is coated with silicon oxide , either through thermal oxidation , with plasma enhanced chemical vapor deposition ( pecvd ) or with lpcvd . ( b ) example process recipe for long pores with a protruding rim out of the plane of the surface using icp and lpcvd for surface modification ( fig1 ) 1 . starting substrate : single crystal silicon wafer , crystal orientation & lt ; 100 & gt ;. 2 . one surface of the silicon is coated with photoresist and the pattern containing the aperture locations and diameters is transferred to the photoresist through exposure to uv light . 3 . the aperture pattern is transferred to the silicon with deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in deep vertical pores with a depth of 1 – 50 μm . 4 . the silicon surface is coated with silicon nitride using low pressure chemical vapour deposition ( lpcvd ) or plasma enhanced chemical vapour deposition ( pecvd ). 5 . the opposite side of the wafer ( the bottom side ) is coated with photoresist and a pattern containing the membrane defining openings in the silicon nitride is transferred to the photoresist through exposure to uv light . 6 . the silicon nitride is etched away on the bottom side of the wafer in the regions defined by the openings in the photoresist , using reactive ion etch ( rie ). 7 . the wafer is etched anisotropically in a koh or tmah solution , resulting in a pyramidal opening on the bottom side of the wafer . the timing of the etching defines the thickness of the remaining membrane of silicon at the topside of the wafer . alternatively boron doping can be used to define an etch stop , giving a better control of the thickness . 8 . rie on rear side , removing the si - nitride mask on the rear side of the wafer and opening the rear end of the aperture . 9 . rie on front side , removing the si - nitride on the front side leaving a protruding si - nitride rim on the orifice . 10 . the silicon is coated with silicon oxide , either through thermal oxidation , with plasma enhanced chemical vapor deposition ( pecvd ) or with lpcvd . 1 . starting substrate : single crystal silicon wafer . 2 . one surface of the silicon is coated with photoresist and the pattern containing the aperture locations and diameters is transferred to the photoresist through exposure to uv light . 3 . the aperture pattern is transferred to the silicon with deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in deep vertical pores with a depth of 1 – 50 μm . 4 . the silicon surface is coated with silicon nitride using low pressure chemical vapour deposition ( pcvd ) or plasma enhanced chemical vapour deposition ( pecvd ). 5 . the opposite side of the wafer ( the bottom side ) is coated with photoresist and a pattern containing the membrane defining openings in the silicon nitride is transferred to the photoresist through exposure to uv light . 6 . the silicon nitride is etched away on the bottom side of the wafer in the regions defined by the openings in the photoresist , using reactive ion etch ( rie ). 7 . the wafer is etched anisotropically using deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in a cylindrical opening on the bottom side of the wafer . the timing of the etching defines the thickness of the remaining membrane of silicon at the topside of the wafer . 8 . rie on rear side , removing the si - nitride mask on the rear side of the wafer and opening the rear end of the aperture . 9 . rie on front side , removing the si - nitride on the front side leaving a protruding si - nitride rim on the orifice . 10 . the silicon is coated with silicon oxide , either through thermal oxidation , with plasma enhanced chemical vapor deposition ( pecvd ) or with lpcvd . 1 . starting substrate : silicon on insulator ( soi ) with a buried oxide layer located 1 – 50 μm below the top surface , carrier crystal orientation & lt ; 100 & gt ;. 2 . one surface of the silicon is coated with photoresist and the pattern containing the aperture locations and diameters is transferred to the photoresist through exposure to uv light . 3 . the aperture pattern is transferred to the silicon with deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in deep vertical pores down to the depth of the buried oxide layer . 4 . the silicon surface is coated with silicon nitride using low pressure chemical vapour deposition ( lpcvd ) or plasma enhanced chemical vapour deposition ( pecvd ). 5 . the opposite side of the wafer ( the bottom side ) is coated with photoresist and a pattern containing the membrane defining openings in the silicon nitride is transferred to the photoresist through exposure to uv light . 6 . the silicon nitride is etched away on the bottom side of the wafer in the regions defined by the openings in the photoresist , using reactive ion etch ( rie ). 7 . the wafer is etched anisotropically in a koh or tmah solution , resulting in a pyramidal opening on the bottom side of the wafer . the buried oxide will act as an etch stop for the process , hence thickness of the topside silicon layer defines the thickness of the remaining membrane . 8 . the exposed regions of the buried oxide layer are removed through rie , wet hydrofluoric acid ( hf ) etch , or hf vapor etch . this will ensure contact between the top and bottom openings in the wafer . 9 . rie on rear side , removing the si - nitride mask on the rear side of the wafer and opening the rear end of the aperture . 10 . rie on front side , removing the si - nitride on the front side leaving a protruding si - nitride rim on the orifice . 11 . the silicon is coated with silicon oxide , either through thermal oxidation , with plasma enhanced chemical vapor deposition ( pecvd ) or with lpcvd . 1 . starting substrate : silicon on insulator ( soi ) with a buried oxide layer located 1 – 50 μm below the top surface . 2 . one surface of the silicon is coated with photoresist and the pattern containing the aperture locations and diameters is transferred to the photoresist through exposure to uv light . 3 . the aperture pattern is transferred to the silicon with deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in deep vertical pores down to the depth of the buried oxide layer . 4 . the silicon surface is coated with silicon nitride using low pressure chemical vapour deposition ( lpcvd ) or plasma enhanced chemical vapour deposition ( pecvd ). 5 . the opposite side of the wafer ( the bottom side ) is coated with photoresist and a pattern containing the membrane defining openings in the silicon nitride is transferred to the photoresist through exposure to uv light . 6 . the silicon nitride is etched away on the bottom side of the wafer in the regions defined by the openings in the photoresist , using reactive ion etch ( rie ). 7 . the wafer is etched anisotropically using deep reactive ion etch ( drie ) or advanced silicon etching ( ase ) using an inductively coupled plasma ( icp ), resulting in vertical cavities on the bottom side of the wafer . the buried oxide will act as an etch stop for the process , hence thickness of the topside silicon layer defines the thickness of the remaining membrane . 8 . the exposed regions of the buried oxide layer are removed through rie , wet hydrofluoric acid ( hf ) etch , or hf vapor etch . this will ensure contact between the top and bottom openings in the wafer . 9 . rie on rear side , removing the si - nitride mask on the rear side of the wafer and opening the rear end of the aperture . 10 . rie on front side , removing the si - nitride on the front side leaving a protruding si - nitride rim on the orifice . 11 . the silicon is coated with silicon oxide , either through thermal oxidation , with plasma enhanced chemical vapor deposition ( pecvd ) or with lpcvd . mayer , m ( 2000 ). screening for bioactive compounds : chip - based functional analysis of single ion channels & amp ; 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