Patent Application: US-201615078275-A

Abstract:
method including receiving first and second identification data relative to data blocks to be transmitted via data bus between processor and system memory . listening data transmitted via data bus to detect block data corresponding to the first or second identification data ; storing in a first location of temporary storage a first data block transmitted via bus and corresponding to first identification data ; storing in a second location of temporary storage a second data block transmitted via bus and corresponding to the second identification data . the storing of the first and second data blocks being performed without disturbing transfer of the first and second data blocks via data bus . when the first and / or second data blocks are stored in the temporary storage activating their respective signature calculator connected to the location of the temporary storage to compute a signature of the data block , and storing the signature in a result memory .

Description:
in fig2 , a hash module is built around a bus snooping device that is connected to the system memory bus . the snooping device sees all the transactions passing to and from system memory . it can capture io data at the same time as they are stored in system memory . this architecture has two main advantages over conventional systems : only one data transfer ( to memory destination ) is performed , and minimum latency is achieved . the hash calculation is mathematically complex and a relatively slow operation . it is much slower than the time to transfer an io block to its destination in memory . as the data appear only once on the system bus , they should be captured when they appear without stopping system data transfers . stopping transfers by the data bus would greatly decrease overall system performance ). the hash module mhash is shown in fig3 . the hash module comprises the following building blocks : a bus snoop module , an internal data cache memory , several hash calculators . hc0 - hcn − 1 , and a register block . the task of the bus snoop module is to observe on - going transactions over system bus or bus segment and capture the data corresponding to snoop configuration parameters . the snoop configuration parameters consists of the following parameters : target address in system memory of the data block , data block length ( expressed either in the number of bytes or in the number of data blocks to be captured ), and transfer direction ( read or write ). when the bus snoop module sees data corresponding to the snoop configuration parameters on the system bus , it captures such data and copies them into the data cache memory on the fly . the system bus can be for example of the type amba or axi . the bus snoop module is configured to capture data on - the - fly on the system bus without affecting bus functioning in any way . when the end of the data block to be captured is reached , the bus snoop module stops and waits for another input from software . example : target address = 0x40000 , io data block length = 6 ( each io data block length = 512 bytes ), direction = write . this configuration means that the snoop module looks for a write operation to system memory to address 0x40000 . when such a write operation happens , it captures all bytes starting from the address 0x40000 and ending at the address 0x401ff ( 512 bytes ) as the first io data block bytes and from address 0x40200 to 0x403ff as the second one etc . data snooping and capturing stops when the last address defined by the snoop parameters ( i . e . 0x40bff ) is reached . the io data blocks to be captured by the snoop module should reside continuously in the system memory . in order to avoid this limitation , an input gather dma can be implemented ( see below ). the internal data cache memory serves as a temporary storage for data blocks captured by the bus snoop module . data blocks are stored in the cache memory until their signatures are calculated . the data cache memory should store at least one io data block for each hash calculator hc0 - hcn − 1 . physically , the data cache memory may be implemented as a single contiguous memory block or as several separate memory blocks ( depending upon implementation environment : asic , fpga . . . .) each of the hash calculators is configured to execute a signature or hash calculation over one io data block at the time . hash calculators are independently started ; they also function in completely independent manner from one another . each hash calculator hc0 - hcn − 1 retrieves data from a corresponding cache memory block io blk 0 - n ( or a segment inside cache memory if the latter is implemented as a single contiguous block ). the hash calculation is always performed over a whole data block , and starts as soon as a last byte of the data block is captured in the data cache memory . the register block is accessed via a separate bus interface and comprises control , status and result registers . control registers may include snoop configuration and start / stop control . status registers return information such as the number of processed io data blocks , and the number of calculated hashes or signatures . the calculated signatures are stored in the result registers . each hash calculator hc0 - hcn − 1 has its own set of result registers . result registers can be accessed by the processor at any time in order to retrieve the calculated signatures . the signatures written to results registers can be retrieved by the processor and passed down the processing chain . according to an exemplary implementation , the sha160 algorithm is chosen for computing signatures of the io blocks . sha algorithms are well - known algorithms ([ 4 ]) with very low collision probability . the hash calculators hc0 - hcn − 1 are configured to compute a 160 - bit signature from every incoming 4 kb io data block . however , the actual io block size does not matter . storage devices use various block sizes such as 512 bytes , 8 kb and others . all implementation details above - presented apply to other hash algorithms and any other io data block size as well . other additional features could be implemented to simplify and accelerate result management . the simplest solution is to store the computed signatures in the result registers ( inside the register block ). the result registers are accessed by the software to recover the computed signatures from time to time . the software may access these registers during precise time windows in order to read correct values . in the following , other additional features could be implemented for minimizing software intervention . instead of result registers , the computed signatures are written into a result memory block implemented inside the hash module mhash . the result memory block may be located inside the register block and can be accessed by software via a register interface . this feature greatly increases the time window of results availability . also , the result memory can be accessed more efficiently ( using long burst transfers ) than individual result registers . every time a signature is calculated , an internal dma engine sends it from the hash result registers or memory block to a result table in a predefined location of the system memory . the signatures are transferred via a separate interface . the processor may then access signatures directly in the system memory . the hash module implements a signature counter accessible by the processor and providing a number a calculated signatures . in systems that do not comprise a separate interface , e . g . with a single memory controller , all data transfers ( incoming data blocks and signatures ) are routed via a same interconnect . in such systems , different priorities can be assigned to signature transfers and data transfers , for performance reasons . for example , the priority assigned to signature transfers can be lower than the priority assigned of data transfers . fig4 represents another embodiment hash module mhash . this dma can be used for gathering io data blocks residing in non - continuous memory addresses . such dma can be controlled using an extended snoop configuration : configuration pointer register points to the location in memory where a list descriptor table is stored , a table length register stores a number of descriptors in the list descriptor table , and each descriptor describes one continuous block in the system memory where 10 data blocks reside . each descriptor comprises a base address and a length of the block . smooth and efficient operation of the hash module mhash may be achieved using the following event flow : the processor provides the snoop parameters as above - described and starts the hash module mhash ; the hash module mhash starts snooping io data ; snooped io data are filled in the cache memory ( starting from block 0 in the cache memory ); once a data block is fully filled in the cache memory , a corresponding hash calculator hc0 - hcn − 1 starts automatically . a block counter status register is incremented to indicate the number of captured io data blocks ; once a signature calculation finishes , the signature counter status register is incremented ; and the snooping of the data bus stops once the last byte indicated by the snoop parameters is captured . signature processing stops once the number of captured io data blocks equals the number of calculated signatures . a system interrupt may be issued to inform the processor of such event . fig5 shows an example of the sequence of events and signature calculation times , when four hash calculators hc0 - hc3 are used . it should be noted that the result registers contain valid information during a results availability window which lasts from the end of one signature calculation until the end of the following one . the minimum duration of the availability window is therefore equal to the one signature calculation time . if the result of a signature calculation is not read by the processor during its availability window , this result is lost . the processor may employ a tracking strategy to periodically access the results registers to recover results ( the implementation of the results dma frees system designer of such a constraint ). in order for system to be balanced , hash calculation should take no longer than the time it takes to transmit n − 1 data blocks over the system bus , where n is the number of independent calculators hc0 - hc3 in the hash module ). this avoids a potential memory conflict where an incoming io block has to be written over an existing io block in the cache memory and the hash calculation over the latter is not yet finished . provided that this requirement is satisfied , the system can run at full bandwidth for an indefinite period of time ( see below for result storing requirements ). actual transfer and calculation times may greatly vary ; they depend among others on the following parameters : system bus width , system bus clock speed , and hash module architecture and clock speed . the hash module may be configured to calculate the number of io blocks programmed in a control registers ( other approaches are also possible such as go until stop arrives etc .) the present invention can also be applied to other domains requiring fast signature calculation over data blocks of fixed size , such as , but not limited to : data watermarking , intrusion detection cryptography duplicate records search bloom filter implementations n . mandagere , pin zhou , mark a smith , s . uttamchandani , demystifying data deduplication , proceedings of the acm / ifip / usenix middleware &# 39 ; 08 f . guo and p . efstathopoulos . building a high - performance deduplication system . in usenix - atc &# 39 ; 11 : proceedings of the 2011 usenix conference on usenix annual technical conference 2011 b . debnath , s . sengupta , jin li , chunkstash : speeding up inline storage deduplication using flash memory , proceedings of 2010 usenix annual technical conference ( atc ), june 2010 national institute of standards and technology , “ secure hash standard ,” fips 180 - 1 , april 1995 . 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