Patent Application: US-63058509-A

Abstract:
an all - digital phase locked loop generates a feedback word representing a continuous - time oscillating signal . the adpll includes a time - to - digital converter configured to be input with the continuous - time oscillating signal and a reference signal . the reference signal is a function of a reference clock signal . the tdc is configured to generate a digital word , the feedback word being a function of the digital word . the adpll includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous - time oscillating signal and to be controlled by a first dither signal .

Description:
a first embodiment with an object to cancel the spurious tones introduced at the output due to the finite reapproach of the tdc ( quantization ) is depicted in fig5 . in this figure , the signal ( a ) is obtained with an integer counter alone , the signals ( b ) with an integer counter and an infinite reapproach fractional counter , and the signals ( c ) with an integer counter and a 4 - level fractional counter . as may be observed , although the tdc has perfectly linear quantization steps , the finite reapproach causes the ε [ n ] signal to have periodic information , that produces spurious tones at the synthesizer output . to cancel these tones , according to a first embodiment , the output c f [ n ] is corrupted by a dither signal such that the quantization error becomes randomized . this can be achieved , for example , by injecting a dither signal with a small amplitude , for example , of about one quantization step of the tdc , either as a variable analog delay element immediately before the tdc on the reference path ( fig6 ) or on the dco path ( fout in fig6 ), or in a second embodiment ( not depicted ) as a digital signal added to the tdc output fout / fref . because the signal path from the injected dither signal to the adpll output is low - pass , a shaped dither signal is preferably used to avoid a negative impact to the in - band noise . more particularly , a dither signal whose energy increases with frequency is preferably used , such that the in - band contribution is negligible and the low - pass nature of the loop counteracts the higher noise power out of band . independent of whether the spectral density of the dither signal is white or high - pass shaped , a multi - level dither is more effective than a two - level dither . a multi - level dither can be done by using a programmable delay element ( or any alternative means for phase programmability ) with a fine delay granularity . mismatches in the extra delay element itself do not negatively affect performances . the technique of this disclosure removes spurious tones due to temporal quantization inherent in the tdc , while requiring minimal hardware modifications to a tdc - based adpll . by placing a variable delay element before the tdc and providing a properly shaped dither signal , as shown in fig7 , minimal impact to in - band noise performance is achieved . an injected dither signal of relatively small amplitude is sufficient to break the periodicity of the quantization error signal on ε [ n ], however such a dither signal is insufficient to counteract the effects of tdc nonlinearity , which is another major cause of spurious tone increase in tdc based adplls . in order to counteract tdc nonlinearity ( as exemplified in fig8 ), a dither signal of sufficient magnitude should be introduced . in doing so , a reduction of spurious tone power is traded for an increase of the in - band noise floor , which is no longer dominated by tdc output noise , as it was in the case of the previous embodiment . in a hardware implementation of the algorithm , instead of a truly random dither signal , a pseudorandom dither signal generated by a linear feedback shift register ( lfsr ) of sufficient length with respect to the fractional periodicity is used . the technique of this disclosure increases the amplitude of the dither signal and uses a multi - level dither sequence and allows reduction of spurious tones due to non linearity of the tdc below the in - band noise floor , trading for an increase of the in - band noise power . another improvement includes compensating the undesired effect of the voluntarily injected dither , i . e . the effect of increasing the in - band noise floor . in fact , if the input dither is a pseudorandom sequence , it is always possible to predict the resulting injected phase error , and thus , to compensate it , as shown in fig9 . in this embodiment , it is possible to choose an arbitrary dither signal for effectively reducing the spurious tone increase due to tdc nonlinearities . the gain α relating the analog delays to the digital compensation signal is a high - reapproach word , and thus can be precisely controlled . this is an additional advantage over an analog calibration approach , wherein the adjustable gain to be calibrated cannot be determined precisely because of analog mismatches . even a rough estimation of the value of the gain α is enough to obtain significant compensation effectiveness . according to another embodiment , digitally cancelling the introduced dither using a digital feed - forward path achieves the same reduction of spurious tones due to both quantization and non - linearity without penalizing significantly the in - band noise power . according to yet another embodiment , a technique for an accurate estimation of the gain α used for compensation is used to make the in - band noise floor equal to that of an undithered adpll . according to this method , during an initial digital estimation phase , a delay value of the additional variable delay element is chosen to be the “ reference delay .” then , a different delay value to be calibrated against the “ reference delay ” is alternated for many samples with the “ reference delay ,” as shown in fig1 , for the simplified case of a short periodicity channel with a large number of tdc quantization levels . at the end of this sample collection phase , each sample is subtracted from the previous one for measuring the relative time difference between the delays in terms of tdc output values tdc out . the absolute values of the results are averaged , obtaining an accurate measurement of the relative time difference between the delays for various tdc output values . by taking a plurality of samples and choosing an appropriate channel for the calibration phase , it is possible to ensure that the full range of the tdc is swept , and thus , all nonlinearities are substantially averaged out . by computing the digital value corresponding to each analog delay level of the additional variable delay element instead of using a single constant a for various delay levels , a look - up table is filled in and is used for canceling effects of nonlinearities in the additional delay element itself . this method produces an accurate matching between the analog delay element and the digital feed - forward path . this technique , based on a digital estimation potentially executed at the start - up of the disclosed adpll , relaxes analog precision requirements of the delay element of the embodiments disclosed hereinbefore . one embodiment of the proposed method is , in practice , a self - calibrating spurious tone reduction method for adplls with no impact to the in - band noise floor . let us consider an exemplary test case of an adpll used to synthesize fractional channels around 3 ghz , starting from a 25 mhz reference frequency , with closed loop bandwidth of about 1 mhz , using a 25 bit fcw ( 7 bits for the integer part , 18 bits for the fractional part ). a 42 level fractional tdc is used , i . e . with a reapproach of 333 ps / 42 = 8 ps . as an example , a 3 khz fractionality channel ( fcw = 120 + 2 5 / 2 18 ) is selected . to show the effectiveness of the first proposed embodiment ( fig6 ), let us consider the case of an ideal adpll . only the tdc quantization effect is kept into account inside the adpll loop . the applied dither signal has a dynamic range equal to ± 1 lsb of the fractional tdc (± 8 ps ) and a step of 1 ps ( 16 levels ). the effect of white and 1 st order shaped dither on the adpll phase noise around the carrier is compared in fig1 . to show the effectiveness of the second proposed embodiment , consider the case of a real adpll . also the tdc mismatch effect is kept into account inside the adpll model . a white dither is applied . the effects of a dither dynamic range equal to ± 1 lsb of the fractional tdc (± 8 ps ) and of ± 8 lsb of the fractional tdc (± 64 ps ), with a step of 1 ps ( 16 vs 64 levels ), are compared in fig1 . to show the effectiveness of the third proposed embodiment ( fig9 ), consider the case of a real adpll . also the tdc mismatch effect is kept into account inside the adpll loop . a white dither is applied , with a dither dynamic range equal to ± 8 lsb of the fractional tdc (± 64 ps ) and a nominal step of 8 ps ( 16 levels ). mismatches between the dither levels are kept into account . the effects of a compensation based on the nominal step value and without the compensation are compared in fig1 . to show the effectiveness of another embodiment , consider the case of a real adpll . also the tdc mismatch effect is kept into account inside the adpll loop . a white dither is applied , with a dither dynamic range equal to ± 8 lsb of the fractional tdc (± 64ps ) and a nominal step of 8 ps ( 16 levels ). mismatches between the dither levels are kept into account . the effects of a compensation based on the nominal step value and with the estimated value using the proposed digital estimation algorithm are compared in fig1 . a . v . rylyakov , j . a . tierno , d . z . turker , j .- o . plouchart , h . a . ainspan , d . friedman , “ a modular all - digital pll architecture enabling both 1 to 2 ghz and 24 - to - 32 ghz operation in 65 nm cmos ,” 2008 ieee international solid - state circuits conference , session 28 , non - volatile memory & amp ; digital clocking , 28 . 6 , pages 516 - 517 . r . b . staszewski , d . leipold , c .- m . hung , p . t . balsara , “ tdc - based frequency synthesizer for wireless applications ,” 2004 ieee radio frequency integrated symposium , pages 215 - 218 . r . b . staszewski , j . l . wallberg , s . rezeq , c .- m . hung , o . e . eliezer , s . k . vemulapalli , c . fernando , k . maggio , r . staszewski , n . barton , m .- c . lee , p . cruise , m . entezari , k . muhammad , d . leipold , “ all - digital pll and transmitter for mobile phones ,” ieee journal of solid - state circuits , vol . 40 , no . 12 , december 2005 , pages 2469 - 2482 . r . tonietto , e . zuffetti , r . castello , i . bietti , “ a 3 mhz bandwidth low noise rf all digital pll with 12 ps reapproach time to digital converter ,” proceedings of the esscirc 2006 , sep . 18 - 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