Patent Application: US-41918306-A

Abstract:
a complementary metal oxide substrate active pixel sensor imaging chip includes a combination circuit , an active pixel sensor array and a watermark generating circuit . also disclosed are methods of using the cmos aps imager for watermarking images .

Description:
the present invention provides for a method and system for creating a watermark in a digital image created by a cmos sensor . when describing the present invention , all terms not defined herein have their common art - recognized meanings . to the extent that the following description is of a specific embodiment or a particular use of the invention , it is intended to be illustrative only , and not limiting of the claimed invention . the following description is intended to cover all alternatives , modifications and equivalents that are included in the spirit and scope of the invention , as defined in the appended claims . a digital watermark is created in the present invention by the combination of a pseudo - noise stream to an image at the chip level . the level of noise is kept low enough that the addition does not change the image in a perceptible manner . the minimal effect on image quality can be seen in the examples shown in fig1 . fig1 a is an original 256 × 256 bitmap image , while fig1 b has random 2 - bit values added to each pixel . fig1 c is the same image with random 4 - bit values added to each pixel . even with random 4 - bit values the image quality is quite good . the architecture of one embodiment of the chip ( 10 ) is shown in fig3 . the central component is a conventional active pixel sensor ( aps ) array ( 12 ). the output of the array is digitized by column parallel adcs and passed along to a combination circuit , such as an adder ( 14 ). the watermark generation circuit ( 16 ) creates a unique bit stream based on an input key . the adder ( 14 ) takes the watermark and the output of the adc and adds them together before passing the watermarked image on to the rest of the system . the output of the array may be digitized in any adc such as column parallel adc , a pixel parallel or , a single adc for the whole chip . the mode of digitization is not critical , as long as a digital value is produced . the combination of the digital watermark and the digitized array output may be any logical operation such as addition , subtraction or masking . although in the preferred embodiment described herein , the implementation of the watermark is digital , in an alternative embodiment , an analog implementation is possible . for example , a random small voltage may be combined with the aps output before digitization . the aps array ( 12 ) forms the photosensitive component of the chip . in one embodiment , a traditional three transistor circuit incorporating an n - well photodiode is used , as shown in fig4 [ 14 ]. the photogeneration of carriers deep in the substrate can lead to pixel crosstalk if the carriers diffuse to a neighbouring pixel [ 15 ]. this phenomenon can be minimized via symmetry . in one embodiment , the n - well diode used in a layout as illustrated in fig5 is octagonal and the surrounding transistors are arranged in an ‘ l ’ fashion to give the diode approximately the same substrate perspective from each direction . in one embodiment , 3 . 3v transistors are preferably used in the pixel in order to allow for greater dynamic range . the pixel pitch may be 5 . 62μm × 5 . 62μm and the fill factor may be 20 %. random access pixel control may be enabled through the use of row and column decoders . the pixel configuration illustrated in fig4 and 5 , and described herein , are illustrative only , and not intended to limit the claimed invention . as is known in the art , an 8 - bit single slope adc may be provided for each column of pixels in the array [ 16 - 18 ]. a small differential circuit takes the pixel signal from the column bus and compares it to a global ramp signal . a digital count continues throughout the digitization cycle , and when the ramp exceeds the pixel signal , the resulting comparator output triggers a bank of flip - flops to latch the digital value for that column . the value is stored in the flip - flops until the column is selected by the decoding logic and tri - state buffers feed the value onto a global output bus . in preferred embodiment , the digital components operate at 1 . 8v to minimize power consumption . in one embodiment , the watermark is a stream of pseudorandombits , such as a stream generated by a linear - feedback shift register ( lfsr ). an lfsr operates by performing an operation such as xor on the bit values from certain register positions . the result is fed back into the beginning of the shift register . as a result , the values streaming out of the last register position seem random but are completely deterministic on the initial state of the shift register . the value of the initial state is used as a key to reproduce the watermark for detection at a later time . it is important that the key is unique to the sensor and that it remain private otherwise false verification is possible . the length of the initial key may be also be set by the user . the lfsr or other means provides a stream of bits dependent on the key . the key can be either provided by , or , preferably , dependent on the imager itself . for instance , the key can be a derivation of the fpn ( fixed pattern noise ) of the imager ). usually the fpn is eliminated , but in this embodiment , some derivation of the raw values can be used as a key . such a derivation can be , for instance , all the values of all pixels corresponding to a certain illumination ( uniform field ) value , or a combination of these values , such as an average over blocks , part of blocks , rows or columns , depending on the length of initial key decided upon . there are multiple ways to obtain an initial key for the lfsr . in one embodiment , bit values from the adc can be fed into the lfsr , generating an initial state . these values are also the watermark key . performing an extended dark field exposure on a specific row of the array should generate reasonably reproducible values . a similar procedure with a uniform light - field should allow elements of the fixed pattern noise to be extracted for use as an initial key . alternatively , either of these operations can be combined with random pixel access to allow the key to be obtained from points spread across the array . in order to mitigate the potential problem of the watermark obscuring the image , the watermark bits are added only to the lesser bits produced by the adc . in a preferred embodiment , 2 - bits , and more preferably 4 - bits , are added to each pixel value of the output image . the bit - stream produced by the lfsr will be grouped into 4 - bit vectors and added to the 8 - bit adc output . preferably , precautions to ensure the addition operation does not overflow the dynamic range should be taken . the following examples are intended to illustrate aspects of the invention and are not intended to limit the claimed invention in any manner . one embodiment of the imaging chip was developed by incorporating a 64 × 64 cmos aps array in a 0 . 18u cmos process . the layout was accomplished using the cadence design system environment ( cadence corporation , san jose , calif .) and a final chip design is shown in fig6 . simulations were conducted using spectre . the device is being fabricated in the tsmc 0 . 18u1 . 8v / 3 . 3v process through the canadian microelectronics corporation ( kingston , ontario , canada ). the final chip size ( including pads ) is intended to be 1122μm by 1302μm . the watermarking algorithm was tested with matlab ( the mathworks , natick , mass .). the results are shown in fig1 and 2 . as mentioned , the 4 - bit strength was chosen because it offered greater probability of successful detection while sacrificing a minimal loss in clarity . linear correlation with the watermark at a later time gives an indication of the presence or absence of the watermark . fig2 shows the distribution of correlation coefficients for 100 watermarked test images . in both 2 - bit and 4 - bit cases , there is a clear separation between groups with a watermark and those without . the addition of 4 - bit values gives a wider separation and hence easier , more reliable selection of a present / absent threshold on the correlation coefficient . the following references are referred to herein as numbers in square brackets and each is incorporated herein as if reproduced in their entirety . g . friedman . “ the trustworthy digital camera : restoring credibility to the photographic image ” ieee trans . on cons . elec . 39 ( 10 ) november 1993 pp . 905 - 910 [ 2 ] f . bartolini , a . tefas , m . barni , and i . pitas . “ image authentication techniques for surveillance applications ” proc . ieee 89 ( 10 ) pp . 1403 - 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