Patent Application: US-13622608-A

Abstract:
the present invention relates to an analog - to - digital converter , especially to a pipelined analog - to - digital converter with calibration of capacitor mismatch and finite gain error . comparing with the conventional pipelined analog - to - digital converter , the new analog - to - digital converter comprises more circuit blocks including an extra sub - converter stage , a control clock generator and an error detector , resulting in that each sub - converter stage has two operation modes : normal conversion mode and calibration mode . all of the sub - converter stages share one error detector which amplifies the output of the sub - converter stage in calibration mode . furthermore , to store the output of the error detector , a memory is used in each sub - converter stage for controlling the gain of amplifier in order to make the error generated by the finite gain of amplifier and the error generated by the capacitance mismatch have the same size but opposite sign . as a result , the two errors can compensate each other to achieve an error - free conversion stage .

Description:
according to the present invention , a block diagram of the embodiments is shown in fig4 , where the pipelined adc is with a 1 . 5 - bit / stage architecture and the resolution is , for example , 10 bits ( n = 10 ). comparing with the conventional adc 100 illustrated in fig1 , the new adc 400 comprises one more sub - converter stage 410 and an extra control clock generator 440 . the control clock generator 440 receives the clock input and produces suitable timing phases to control the operations of optional sample - and - hold 401 , sub - converter stages 402 - 410 , final flash stage 420 and digital error correction circuit 430 . conventionally , eight sub - converter stages are needed for a 10 - bit pipeline adc , besides the last 2 - bit flash one . in this structure , nine stages 402 - 410 are utilized in order to perform the calibration task periodically . in fig4 , the input of stage - 1 402 is the output of optional sample - and - hold 401 which receives the analog input signal . the outputs of sample - and - hold 401 and stage - 1 402 are the two inputs of stage - 2 403 . at least one of the other sub - converter stages from stage - 3 404 to stage n − 1 410 has two different inputs , and for any stage i with two different inputs , one of the two inputs is the output of stage i − 1 and the other is the output of stage i − 2 . the input ( s ) of final flash stage 420 is the output of stage n − 1 410 or the outputs of stage n − 2 409 and stage n − 1 410 , respectively . the control clock generator 440 is connected with sample - and - hold 401 , sub - converter stages from stage - 1 402 to stage n − 1 410 and flash stage 420 , and receives clock input to produce suitable clock timing phases to control the operations of those circuit blocks . sub - converter stages from stage - 1 402 to stage n − 1 410 and flash stage 420 are connected with the digital error correction circuit 430 . here , n is used to define the resolution of the adc which can be any integer larger than 2 . if sub - converter stage n − 1 410 is with only normal conversion mode , the input of final flash stage 420 is the output of stage n − 1 410 . when sub - converter stage n − 1 410 comprises a calibration mode besides the normal conversion mode , the final flash stage 420 has two inputs which are the outputs of stage n − 2 409 and stage n − 1 410 , respectively , and the output of stage n − 1 410 is valid if stage n − 1 410 is in normal conversion mode , or the output of stage n − 2 409 is valid if stage n − 1 410 is in calibration mode . in this structure , n − 1 stages 402 - 410 are utilized in order to perform the calibration task periodically . the sub - converter stage - 1 402 and at least one of sub - converter stages from stage - 2 403 to stage n − 1 410 have two operation modes : normal conversion mode and calibration mode . those stages with two operation modes are controlled by clock timing phases to be in calibration mode by turns , guaranteeing that n − 2 sub - converter stages are always in normal pipeline conversion mode which means a quasi real - time calibration periodically without interrupting the normal conversion . those stages with two operation modes operate as follows . at first , stage - 1 402 is removed from the pipeline for calibration . when calibration finishes , stage - 1 402 joins back to the pipeline and stage - 2 403 is removed in the same way , and so on . after the last stage is calibrated , the process repeats again . fig5 a , fig5 b , fig5 c and fig5 d show schematic diagrams of a sub - converter stage . the sub - converter stage - 2 and at least one of sub - converter stages from stage - 3 to stage n − 1 comprise two inputs , and those stages with two inputs have a little difference with conventional stages shown in fig2 a and fig2 b . because there are two analog inputs v in1 and v in2 during sampling phase in the sub - converter stage , a switch unit 530 is incorporated before amplifier 501 and comparators 510 and 511 . for details , the sub - converter stage with two inputs comprises an amplifier 501 , two capacitors c 1 and c 2 , two comparators 510 and 511 , a digital unit 520 , a switch unit 530 , and a memory 540 , as illustrated in fig5 a . the voltage vctr stored in the memory 540 is used for adjusting the gain of the amplifier 501 . in sampling phase , one of the two analog inputs v in1 and v in2 is selected by switch unit 530 to be valid . the output of sub - converter stage - 1 402 is selected to be valid as the input of stage - 2 403 if stage - 1 402 is in normal conversion mode , and the output of sample - and - hold 401 is selected to be valid as the input of stage - 2 403 if stage - 1 402 is in calibration mode . for the sub - converter stages from stage - 3 404 to stage n − 1 410 , the output of stage i − 1 is selected to be valid as the input of stage i if stage i − 1 is in normal conversion mode , and the output of stage i − 2 is selected to be valid as the input of stage i if stage i − 1 is in calibration mode . the sub - converter stage - 1 402 has no such a switch unit . the input analog signal of sub - converter stage - 1 402 is connected directly with the bottom plate of c 1 and also fed to the two comparators 510 and 511 . conventionally , two capacitors are used for input sampling . in this present architecture , only one capacitor c 1 = 2c with an approximately double value as that of c 2 = c − δc is adopted for input sampling , as shown in fig5 a . during the sampling phase , the input analog signal is connected with the bottom plate of c 1 and c 2 is reset ( shorted to a dc voltage , for example , ground ). the output and inverting input of amplifier 501 are connected together with the top plates of both c 1 and c 2 . the two comparators 510 - 511 and digital unit 520 operate similarly as those in conventional sub - converter stages . during the holding phase , as shown in fig5 b , the amplifier 501 is in amplification mode and its inverting input is still connected with the top plates of both c 1 and c 2 . the bottom plate of c 2 is connected with the output of amplifier 501 . depending on the value of d i (− 1 , 0 or 1 ), the bottom plate of c 1 is connected with different reference signals in this phase , we obtain the output v out as here , v in is the effective input analog signal during the sampling phase and a is the dc gain of amplifier 501 . δc is capacitance mismatch ( error ). if customized values of δc / c and a are selected to make the following expression stand which is the same with ( 1 ), i . e ., the condition that dc gain and capacitors must satisfy , here the input signal is multiplied by two accurately which is perfect for the 1 . 5 - bit / stage pipelined adc . this means that the finite amplifier gain error and capacitor mismatch error are compensated each other , resulting in an error - free sub - converter stage . one problem in the preferred embodiment of this invention is that the capacitance ratio δc / c is inconstant due to the imperfection of manufacture process . therefore , the dc gain a of amplifier must be tunable to adapt to the capacitance ratio , as illustrated in fig5 c and fig5 d which show schematic diagrams of a sub - converter stage in calibration mode according to a preferred embodiment of the present invention . in the sampling phase of calibration mode , a reference signal v ref / 2 is sampled on c 1 , and c 2 is reset ( the bottom plate is connected to a dc voltage , for example , ground ), as shown in fig5 c . here , the amplifier 501 and two capacitors c 1 and c 2 are the same as those in fig5 a . in the holding phase of the calibration mode , the bottom plate of c 1 is connected with a dc voltage , for example , ground , and c 2 turns to be the feedback capacitor , as shown in fig5 d . the output v rout of amplifier 501 is expressed as here , a is the dc gain of amplifier 501 . in fig5 d , the error detector 550 senses the difference between v rout and reference signal v ref . the output of the error detector 550 is stored in the memory 540 for adjusting the gain of the amplifier 501 . the dc gain of error detector 550 is designed to be very high . consisting of amplifier 501 , error detector 550 , capacitors c 1 and c 2 , and memory 540 , the closed loop settles with v rout being equal to v ref , which means the above expression ( 3 ) stands . as a result , the dc gain a of amplifier 501 is customized perfectly to make the finite amplifier gain error and capacitor mismatch compensated each other . furthermore , sub - converter stages with two operation modes among stages 402 - 410 can share one error detector 550 for saving power and chip area . the embodiments of the invention are exemplary and are described in detail to enable those skilled in the art to practice the implementation . it is to be understood that numerous modifications , variations and rearrangements can be readily made to achieve substantially equivalent results , without departing from the spirit or scope of the invention as defined in the appended claims . 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