Patent Application: US-201615095730-A

Abstract:
superconductor analog - to - digital converters offer high sensitivity and large dynamic range . one approach to increasing the dynamic range further is with a subranging architecture , whereby the output of a coarse adc is converted back to analog and subtracted from the input signal , and the residue signal fed to a fine adc for generation of additional significant bits . this also requires a high - gain broadband linear amplifier , which is not generally available within superconductor technology . in a preferred embodiment , a distributed digital fluxon amplifier is presented , which also integrates the functions of integration , filtering , and flux subtraction . a subranging adc design provides two adcs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30 - 35 db .

Description:
the subranging approach is widely used for high - performance adcs to increase dynamic range . in a subranging adc , the signal to be digitized is split , going to a coarse adc and a fine adc . the output from the coarse adc is subtracted from the input , forming a residue signal that is essentially the coarse adc &# 39 ; s quantization error . upon digitization of this residue signal with finer resolution in a fine adc , we can sum the two adc outputs and get cancellation of the coarse quantization error . therefore , we simultaneously obtain the high maximum signal level of the coarse adc and the fine quantization steps of the fine adc , resulting in a much higher dynamic range than either adc . in other words , the outputs from the coarse and fine adc &# 39 ; s form the most significant bits ( msb ) and least significant bits ( lsb ) respectively of the subranging architecture . with only one type of modulator , such as a low - pass delta modulator based on the principle of phase modulation - demodulation ( pmd ), we can obtain enhanced dynamic range by residue amplification . a typical modulator generates an oversampled 1 - bit differential code that represents the discrete derivative of the input signal . this 1 - bit oversampled code needs to be integrated first to reconstruct the digital equivalent of the input signal , and then averaged further and read out at the decimated rate to reduce the output bandwidth and increase the effective number of bits . these m bits form the most significant bits ( msb ) of the subranging adc . in order to extract the least significant bits ( lsb ), the oversampled single bit stream from the coarse adc output is converted back to the analog domain in a dac and subtracted from the input signal to generate a residue signal representing the error of the coarse adc . the error signal is then digitized by the fine adc to get the lsbs . ideally , the residue signal has a dynamic range equivalent to the dynamic range of the fine adc . in a known implementation of a subranging adc , the residue signal is extremely small , and needs to be amplified to the full - scale range of the fine adc . the n - bit digital output of the fine adc is divided by the amplification factor and summed with the coarse adc output to yield a digital output with a larger dynamic range ( more effective bits ). instead of amplifying the analog residue , one can move the amplification before the subtraction function in the digital domain . to do this , we divide the signal between the two adcs ( fig4 ), coupling a small fraction to the coarse adc and the rest to the fine adc . thus , the division is typically unequal , thus supporting a large dynamic range for each of the coarse and fine adcs . now , the coarse adc output needs to be amplified by the same factor ( k ) to match the amplitude of the analog signal being applied to the subtractor . in a preferred embodiment , the interface between the two adcs , called the inter - range mixed - signal processor , performs several signal processing functions : subtraction , filtering , amplification , and in the case of using a delta modulator in the coarse adc , integration . the amplification and filtering functions can be done in both analog and digital domains . digital amplification , or multiplication , ensures linearity , and is particularly preferred . additional digital processing to compensate for nonidealities of subsequent analog components , such as the subtractor , may also be performed in the digital domain . the analog filter performs digital - to - analog conversion of the single - bit oversampled data stream ; no explicit device is needed . following digital integration and filtering , the coarse adc output is multiplied by k and summed with the similarly processed fine adc output . superconductor low - pass delta modulators have demonstrated high linearity in data conversion . fig4 b shows a subranging adc comprising two delta modulators ( see reference 4 ). the output of such a delta modulator is a stream of single flux quantum pulses . the corresponding inter - range mixed - signal processor includes a fluxon amplifier and a flux subtractor . any other digital processing , such as filtering , of the coarse adc &# 39 ; s delta modulator will have to be performed with appropriate digital logic , such as rapid single flux quantum logic ( rsfq ). our current preferred implementation of a superconductor delta modulator uses the phase modulation - demodulation ( pmd ) architecture ( reference 4 ). the pmd delta modulator uses a stream of flux quanta at half the maximum fluxon transport rate of one φ 0 every clock period as the phase modulation carrier . in the simplest case , this carrier is generated by pumping flux in the phase modulator circuit at half the sampling clock rate ( f clk / 2 ). the flux pump allows unipolar digital coding : when the input signal is absent the output is a pattern of alternating 1 &# 39 ; s and 0 &# 39 ; s , when the input signal is present the output has more 1 &# 39 ; s ( 0 &# 39 ; s ) when the signal derivative is positive ( negative ). therefore , this carrier must be subtracted before subtraction from the analog input signal . one method of doing this is to construct a differential fluxon amplifier that receives the coarse adc &# 39 ; s pmd delta modulator output and a copy of the carrier ( or flux pump ) at its two differential inputs ( fig4 c ). another method of subtracting the carrier is to do it digitally and generate two differential unipolar streams ( fig4 d ). the subtraction function is performed by subtracting magnetic flux produced by the analog input and the amplified digital output from the coarse adc &# 39 ; s pmd delta modulator using a set of coupled coils . for example , we can construct three sets of coils , the first carrying the analog input signal , the second carrying the output of the digital fluxon amplifier , and the third carrying the residue into a fine adc ; the coupling of the first ( pick - up coil ) and the second ( fluxon injector coil , which may comprise multiple taps ) to the third ( residue coil ) must have opposite sense for subtraction . the digital amplifier produces a bipolar signal of magnitude kφ 0 / 2 of either polarity and injects the corresponding flux into a residue coil . the effect of unfiltered quantization noise is particularly severe on a delta adc , since the slew - rate contribution is proportional to the frequency of the noise component extending all the way up to f clk / 2 , which may be 2 - 3 orders of magnitude higher than the rf signals - of - interest . if we set a performance criterion of 90 - db snr in 10 - mhz bandwidth , a 2 nd - order low - pass filter is adequate for input frequencies less than 200 mhz . over 200 - mhz , the filtering requirement for a delta + delta subranging adc will be severe ( requiring a 7 th order bandpass filter for f = 500 mhz , according to initial simulations ). one way of avoiding this required level of filtering is to use a delta - sigma modulator , which is not slew - rate limited , as the fine adc ( fig5 ). a functional matlab simulink model , as shown in fig6 , was developed for the subranging architecture and used to carry out simulations to anticipate the improvement in performance of a two - range subranging adc over a single - range adc , using two identical low - pass pmd delta modulators . as seen from fig6 , the output from the coarse adc is passed through a low - pass bessel filter and integrated in an analog integrator . to match delay and amplitude attenuation , the analog input signal is also filtered before being applied to the fine adc . the phase modulation carrier is subtracted also . the resultant signal is amplified and then subtracted from the analog input before being digitized by the second ( fine ) adc . the oversampled data from the coarse and fine adc are integrated and averaged further in a digital decimation filter . the coarse adc output needs to be delayed to compensate for the delay through the inter - range mixed - signal processor before being summed with the fine adc output . fig7 a shows the simulated power spectrum for the phase modulation - demodulation delta adc and phase modulation - demodulation subranging delta adc . the spectrum is for a 9 . 6875 mhz sine wave being sampled at 20 . 48 ghz and decimated by a factor of 256 . the cutoff frequency of the analog low - pass filter is 80 mhz . the amplification factor ( k ) is 128 . as seen from fig7 a , the noise floor of the subranging adc is significantly lower than that of the regular low - pass pmd adc . at the signal peak , the two traces overlap , confirming correct operation . both the coarse and fine adcs use a single channel synchronizer ( reference 4 ). fig7 b plots the calculated signal - to - noise ratio ( snr ) as a function of the amplification factor ( k ). for lower amplification values ( up to 8 ), the performance of the subranging adc is similar to that of the single modulator adc . one plausible explanation is that the amplitude attenuation in the lowpass filter nullifies any performance enhancement . for simulation , a simple bessel filter from the simulink tool box was employed . improved design of the analog filter , reducing the passband attenuation , would enable enhanced snr even for lower amplification ratios . fig8 plots the snr for a pmd delta adc and a two - range pmd delta subranging adc as a function of the signal power ( in db full scale ). to justify the accuracy of simulation , measured results for the pmd adc are also plotted . the measured results are in close agreement with the simulated performance . the subranging adc shows a 32 db gain in snr at signal power close to the slew rate limit . the simulation does not take into account implementation losses like the imperfections in phase delay matching which might drop the projected gain in performance ; however , a digitally controlled phase delay network may be employed as necessary ( not shown in the figures ), and therefore this is not an insurmountable practical limitation in implementation . such a delay network may be adaptive , especially if there is an overlay in the range of the coarse and fine adc , since this permits a correlator to find and maintain an ideal phase delay to maximize the correlation of the lower coarse adc bits and upper fine adc bits in the overlapping range . typically , a controllable phase delay network would not be required , and a fixed delay in a static design would suffice . fig9 a and 9b show the simulated power spectra for a 28 mhz and a 156 mhz sinusoidal input respectively , both clocked at 40 ghz with an amplification factor ( k ) of 128 . the two - range pmd delta subranging adc is slew - rate limited . therefore , its snr drops as the input analog signal frequency is increased . fig1 shows a plot of the snr in the full output bandwidth of 312 . 5 mhz ( f clk / 2r , where the sampling clock frequency f clk is 40 ghz and the decimation ratio r is 64 ), as a function of input analog signal frequency . another subranging adc implementation , substituting the delta modulator with a sigma - delta modulator in the fine adc , improves the performance at higher analog signal frequency . fig1 shows the corresponding matlab simulink model . a second - order low - pass bessel filter is used to reject out - of - band quantization noise . in order to avoid phase mismatch between coarse adc output and analog input signal due to the low - pass filter , the filter is moved after the subtractor . a compensating delay is inserted in the coarse adc output path to avoid misaligned phases while summing the coarse and fine adc outputs . a current - to - voltage converter converts the residue current to voltage which is further digitized by the sigma - delta modulator . the coarse and fine adc outputs are added in software and their spectra are analyzed . extensive simulations of the subranging adc architectures were carried out using a delta pmd adc modulator for the coarse and a delta - sigma modulator for the fine sections of the subranging adc . simulation for input frequencies 8 , 28 , 88 , 116 , 156 , 223 , 273 , 323 , 377 , 423 , 477 , 523 mhz was performed . simulations were done for clock frequencies of 40 . 96 ghz and amplification coefficients of 128 . representative spectra ( fig1 a , 12b , and 12c ) and a summary of snr as a function of signal frequency with 10 mhz instantaneous bandwidth ( fig1 ) are shown . the inter - range mixed - signal processor performs several functions : subtraction , amplification , integration , filtering , and delay . the basic concept of a flux subtractor is shown in fig1 a . the analog input and the coarse adc outputs are inductively coupled to two serially connected coils with opposite polarity . the difference or the residue signal , φ residue = φ in − φ coarse , is fed to the fine adc . the raw single - bit oversampled coarse delta adc output needs to be integrated first to reconstruct the input signal . furthermore , in a pmd adc , a carrier signal ( called flux pump ) is added to the input at the rate of φ 0 f clk / 2 . this may be thought of as an offset ‘ ramp ’ which upon integration yields a dc offset equal to half of full - scale . before subtraction from the analog input , the flux pump needs to be subtracted also . this is done by injecting the coarse adc output and the flux pump from the opposite ends of a large inductor ( l int ) that also performs the integration function . a lowpass filter , which is not shown in the schematic , is provided to reject the out - of - band quantization noise . fig1 b shows the scheme corresponding to digital carrier subtraction shown in fig4 d . however , the extremely higher inductance ( l int ) required to integrate the full - scale signal results in very low energy coupling to the residue coil ( l res ). a preferred approach is to couple a small fraction of the input signal to the coarse adc and then amplify its output before subtraction with the rest of the analog input . the best way to ensure linearity in amplification is to perform it in the digital domain by producing k copies of the sfq pulse stream and injecting them into the residue coil . a structure for this amplification is a network of active josephson transmission line ( jtl ) splitters . instead of a single coil carrying the coarse adc output ( and the flux pump ), a series of fluxon injector coils are provided , each being driven by a splitter segment , coupling to multiple residue coils in series . this is shown in fig1 . this scheme reduces the inductance of each tap to l dint = l int / k , thereby improving the energy coupling k - fold . even for a large amplification factor ( k = 128 ), the resulting l dint may still be too large for the desired high energy coupling . the higher l dint also increases the residue inductance ( l res ), and therefore , the noise floor . a preferred solution is to restrict the residue inductance to obtain a low enough noise floor . to understand the solution , it is instructive to reverse the challenge . first , we fix the total residue inductance to get the desired noise floor , which makes each segment ( l ′ res = l res / k ). in order to achieve higher energy coupling , the corresponding fluxon injector tap ( l tp ) needs to be significantly reduced . this , in turn , limits the maximum signal that can be integrated to n · φ 0 / l tp & lt ; i c , where i c is the critical current of the junctions in the injector tap . this restricts n to 2 - 3 , which is much , much less than the desired full - scale signal (˜ 40 , 000φ 0 / k for f clk = 40 ghz ). even for a large amplification factor ( k = 128 ), we have a difference of two orders of magnitude in the number of flux quanta that each fluxon injector coil can store . since we are only interested in the small difference between two large quantities , one approach is to combine the subtraction function with the amplification . a preferred solution provides distributed flux subtraction and amplification . in this scheme , the coarse adc output is integrated in multiple injector taps , each with a very small inductance . full - scale signal integration is enabled by restricting the integrated current in each tap to be below critical current ( i c ). this is accomplished by enabling distributed subtraction by coupling the pick - up coil , carrying the input analog signal , strongly to each of the k taps of the multi - tap coil carrying the amplified coarse adc output . the input signal continuously subtracts from the signal being integrated in the injector taps , thereby preventing it from exceeding the threshold i c . this distributed subtraction scheme , shown in fig1 a is different from an alternative scheme where the integration of the coarse adc output was done first , and the resultant analog signal then amplified before performing subtraction ( reference 1 ). in the present scheme shown in fig1 a , first the coarse adc output ( and the carrier ) is amplified by digital multiplication . each segment ( tap ) of this fluxon amplifier comprises a splitter that produces an sfq pulse propagating to the next segment and another that is injected into the l tp inductor . next , the integration and the subtraction functions are merged together in a set of injector tap coils . the residue current , which represents the error of the coarse adc is now integrated in these injector coils and is read out by coupling them with a common residue coil , as shown in fig1 . the residue is then digitized by the fine adc . the fluxon amplifier is divided into several blocks , each feeding a set of n tp injector tap coils . each fluxon amplifier block has a gain of n tp and has two differential inputs ( d and c ), representing the coarse adc &# 39 ; s delta modulator output and its carrier respectively . the multi - tap injector is coupled ( φ 12 ) to a pick - up coil ( p 1 ). it is also coupled ( φ 23 ) to a residue ( r 1 ). there is also direct coupling of flux ( φ 13 ) between the pick - up and the residue coils . fig1 b shows the circuit schematic of a fluxon amplifier tap . each digital input stream , representing the coarse adc &# 39 ; s delta modulator output or its carrier , is split into two copies , the first going to the fluxon injector coil and the second propagating on to the corresponding input of the next segment . another function that may be incorporated in this mixed - signal processing circuit block is low - pass filtering . the filtering is done by producing time - delayed copies of a signal and combining them . fig1 a shows a scheme for introducing the filtering function within each fluxon amplifier tap . first , a digital delay stage is introduced to delay by one or more clock periods . this acts as a digital filter , as represented in fig1 b , reducing the step - size of the staircase function of the injected flux as a function of time . second , finer analog filtering can be done by introducing a ladder of jtl splitters and adding the split fluxon in parallel inductors . the delay through the jtl may be varied by changing its bias current to obtain the best filtering . fig1 shows a fluxon amplifier block with built - in filtering and a gain equal to the number of taps ( n tp ). fig2 shows a multi - function mixed - signal block comprising a fluxon amplifier block attached to a multi - tap fluxon injector coil ( m 1 ). the multi - tap injector is coupled ( φ 12 ) to a pick - up coil ( p 1 ). it is also coupled ( φ 23 ) to a residue ( r 1 ). however , direct coupling ( φ 13 ) between the pick - up and the residue coils is inevitable and undesired . fortunately , this can be negated by using another set of coils of reversed sense in series . a transmission line structure for the input analog signal to travel between multi - function mixed - signal blocks may be created by using an appropriately valued capacitor ( c ′). in order to increase the amplification factor , several of these multi - function mixed - signal blocks are connected in series . however , the series connection proportionally increases the residue inductance and hence the noise floor of the fine adc . in order to maintain the residue inductance constant , an equal number of blocks need to be connected in parallel . thus , every doubling of the power amplification necessitates quadrupling the hardware . fig2 depicts a scheme of connecting 4 multi - function mixed - signal blocks to double the gain . the data ( d ) and the carrier ( c ) propagation have to match that of the analog input signal . this is accomplished by using a driver - receiver pair to interface sfq pulses on a passive transmission line ( ptl ) ( reference 3 ). multi - threshold delta and sigma - delta modulators produce higher intrinsic dynamic range . fig2 shows a subranging scheme for using such a multi - threshold modulator in the coarse adc . for example , the pmd adc with multi - channel synchronizer produces thermometer - coded multi - bit output , which is subsequently added to produce an m - bit binary weighted signal for interfacing with a digital processor , such as a cascaded - integrator - comb ( cic ) digital decimation filter ( reference 2 ). the inter - range mixed - signal processor for such a multi - threshold coarse adc modulator may be constructed with the same basic building blocks described for the subranging adc with single threshold modulator ( fig4 a ). in the scheme shown in fig2 , there are q bitstreams of equal significance which are amplified by a factor of n each with the digital fluxon amplifier blocks , with or without built - in low - pass filtering . these blocks are combined with a subtractor comprising a multi - tap flux injector coil also performing the function of integration . digital - to - analog conversion takes place in the boundary between the fluxon amplifiers and the fluxon injector coils . it is also possible to take the binary - weighted m - bit output after the adder in the coarse adc ( fig2 ). in this case , the bits must be amplified according to their significance . if the least significant bit is amplified n times , the most significant bit must be amplified by a factor of 2 m - 1 n . the binary - weighted numbers offer more compact digital logic implementations which are advantageous for extending the inter - range digital processing . for example , further adjustments of gain may be necessary to compensate for gain mismatches between the coarse and fine adc analog inputs and for non - ideal transformer coupling . a programmable digital look - up table placed within the inter - range processor , as shown in fig2 , provides a method to adjust gain . fig2 shows the block level schematic used to simulate the delta - delta subranging adc . two similar flux quantizers are used in the pmd coarse and fine modulators . a fraction ( 1 / k ) of the full - scale input signal (( 1 + k )/ k ) is applied to the coarse adc , while the rest is applied to the fine adc . the intrinsic slew rate limit of this flux - quantizing adc is a single flux quantum ( φ 0 ) in each sampling interval . therefore , the most natural configuration for the flux pump is to inject fluxons at φ 0 / 2 per sampling period , to accommodate bipolar input signals ± φ 0 / 2 per sampling period . this is done by pumping fluxons at a frequency of f pump = f clk / 2 . thus , in the absence of the input signal , both the quantizers pulse at the pump frequency . when an additional input signal is coupled to the quantizer loop , the pulse positions either advance or retard in proportion to the derivative of the input signal , thus producing a phase modulated pulse stream at the quantizer output . this phase modulated pulse stream is demodulated by the synchronizer , which is a clocked sampling circuit generating a ‘ 1 ’ or ‘ 0 ’ indicating whether or not a pulse arrived in a given clock period . this 1 - bit oversampled differential code from the synchronizer is then digitally integrated , filtered , and amplified by k to generate the m most significant bits of the subranging adc . this digital processing of the coarse modulator output to generate m bits appropriate significance is not shown in the schematic . to generate the additional n bits , the coarse modulator output is further processed by the inter - range mixed signal processor . the digital data from the coarse adc is amplified by digitally multiplying the sfq pulses and integrating each pulse in different taps ( l tp ) of the multi - tap coil . a 4 - tap inter - range processor is used for simulation . the unipolar to bipolar conversion of the coarse modulator is achieved by digitally subtracting the carrier by injecting it from the opposite end of each tap . the coarse modulator output needs to be lowpass filtered to reject the out of band quantization noise . the filtering functionality is merged in the amplification process by digitally delaying the inputs to the multiple taps , thus reducing the step size of the integrated signal to generate a more smoothly changing signal ( fig1 a , 18b ). similarly , to filter the carrier , two 180 degrees phase shifted carriers ( ph 1 and ph 2 ) are generated from the master clock ; ph 1 being used to subtract carrier from odd numbered taps and ph 2 being used to subtract carrier from the even numbered taps . to integrate the full - scale signal , l tp needs to be large enough to integrate a few hundred fluxons (˜ 300 for 10 mhz input signal , sampled at 40 ghz ). however , to reduce the noise floor the residue inductance should be very small , and to increase the energy coupling between each tap and the residue coil , the tap inductance needs be extremely small . hence , the saturation current of l tp is chosen so as to integrate a maximum of two fluxons per tap . on exceeding the saturation current , the fluxon is not integrated but released by unintended switching of the carrier port junction . to enable full - scale signal integration while using a very small tap inductance , the integration and subtraction functions are merged , so as to restrict the residual current per tap to be lower than the saturation limit of l tp . this is accomplished by enabling distributed subtraction by coupling the input coil strongly to each of the taps of the multi - tap coil . the input signal continuously subtracts the signal being integrated in each tap , thereby preventing it from reaching the saturation limit of the tap inductor . an inevitable and undesired consequence of this scheme is a direct coupling ( φ 13 ) between the input and the residue coils . fortunately , this can be negated by using another coil or reversed polarity in series (− 4 φ 13 in fig2 ). the residual current in each tap represents the error of the coarse adc and is integrated by coupling each tap with a common residue coil . the integrated residue is then digitized by the fine modulator ( only the fine quantizer is shown in the schematic ). in fig2 , all blocks not otherwise labeled are active josephson transmission line segments for either digital signal propagation or splitting . fig2 shows the circuit - level simulation result of the delta - delta subranging adc with a 4 - tap inter - range mixed signal processor . the same analog input is applied to the coarse and fine adc . however , the coupling coefficient of the coarse adc input transformer is k times smaller , resulting in a factor of k smaller input signal being coupled to the coarse adc . the carrier represents a copy of sfq pulses being applied to the pump which is then smoothed out by the pump to generate a slowly changing current . the carrier signal is applied at half the clock frequency . in the absence of input signal , the coarse adc output ( synchronizer ) generates a ‘ 1010 ’ pattern which is then modulated by the input signal . for example , the three consecutive ‘ 1 &# 39 ; s ’ in the coarse adc output pattern is a consequence of modulation of the carrier by the input signal . the clock phases represent the two phase shifted carriers being used for unipolar to bipolar conversion of the coarse adc output . i ( res ) represents the current in the residue inductor , which is the sum of the current due to the carrier and the integrated residual current from the multiple tap inductors . for low clock frequency simulations , two distinct changes in residual current can be identified ; one corresponds to injection of carrier , and the other corresponds to signal subtraction in the tap inductors . the fine quantizer output shows the propagation of the carrier , representing significant cancellation of the analog input to the fine adc such that the residual error being generated is smaller than the flux resolution of the fine quantizer . other simulations have verified the phase modulation of the fine carrier by the residual current . the penultimate trace shows the data and carrier pulses being injected in tap 1 . the pulses encircled with dashed lines represent the excess pulses in coarse adc output because of the input signal ; whereas the other pulses correspond to the carrier of the coarse adc . the fluxons being applied to the carrier port of the inter - range interface overlap with the carrier pulses in the coarse adc output , and are indistinguishable in the figure . finally , the last trace represents the current being integrated in the first tap . here again , two distinguishable processes can be identified : one corresponds to the increase in current corresponding to fluxon injection from coarse adc in response to input signal and the subsequent subtraction because of the coupling to the fine analog input signal , and the second process corresponds to carrier subtraction of the coarse adc in the inter - range interface that results in spikes in the tap current . it should be appreciated that changes could be made to the embodiments described above without departing from the inventive concepts thereof . it should be understood , therefore , that this invention is not limited to the particular embodiments disclosed , but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims . 1 . a . inamdar , s . rylov , a . talalaevskii , a . sahu , s . sarwana , d . e . kirichenko , i . v . vernik , t . v . filippov , and d . gupta , “ progress in design of improved high dynamic range analog - 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