Patent Application: US-69950907-A

Abstract:
a self - aligned silicon carbide power mesfet with improved current stability and a method of making the device are described . the device , which includes raised source and drain regions separated by a gate recess , has improved current stability as a result of reduced surface trapping effects even at low gate biases . the device can be made using a self - aligned process in which a substrate comprising an n + - doped sic layer on an n - doped sic channel layer is etched to define raised source and drain regions using a metal etch mask . the metal etch mask is then annealed to form source and drain ohmic contacts . a single - or multilayer dielectric film is then grown or deposited and anisotropically etched . a schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers .

Description:
as set forth above , trapping effects occur in mesfet devices when electrons get trapped by acceptor - like levels either in the semi - insulating ( si ) substrate ( which is commonly referred to as “ backgating ”) or at the surface . fig1 shows a schematic cross - section of a sic mesfet 10 fabricated on a semi - insulating substrate 12 with a p - type buffer layer 14 . as can be seen from fig1 , the sic mesfet 10 also comprises an n - type channel layer 16 , an n - type source region 18 , an n - type drain region 19 , and source 20 , gate 22 and drain 24 contacts . in fig1 , the regions where electrons can be trapped by acceptor states are indicated in the drawing by minus signs . as set forth above , various device structures have been developed that attempt to minimize the influence of interface traps on current stability by distancing the main current stream away from the surface . for example , current stability can be improved by utilizing gate - recessed or buried gate structures . however , even gate - recessed and buried gate structures cannot prevent instability of the drain current at low gate biases , when electrons flow in close vicinity to the surface . a self - aligned power sic mesfet structure with improved current stability is described herein . in this device , the influence of an electron charge trapped at the surface on the output characteristics is negligible compared to conventional mesfet structures . the device can be made using a very simple and economical fabrication process based on self - aligned technology . fig2 a shows a schematic cross - section of a self - aligned power sic mesfet structure according to a first embodiment . as shown in fig2 a , the device comprises a semi - insulating substrate 1 , a p - type sic buffer layer 2 , an n - type sic channel 3 , source and drain fingers 26 formed in the channel and separated by a gate recess 28 , and n + source and n + drain layers 4 . the device as shown in fig2 a also includes source and drain ohmic contacts 5 and a schottky contact 6 . also shown are source , drain and gate contacts 8 formed via self - aligned metallization . as also shown in fig2 a , the device structure includes a surface passivation layer 7 . fig2 b shows a schematic cross - section of a self - aligned power sic mesfet structure according to a second embodiment . the device shown in fig2 b is similar in structure to the device shown in fig2 a . this device , however , also includes an optional n - type layer 3 a . the devices shown in fig2 a and 2b include a surface passivation layer 7 . however , even under conditions where the surface trap density is high , the influence of the electron charge trapped at the surface on the drain current is virtually eliminated . a two dimensional ( 2 - d ) numerical analysis conducted on a device having a structure as shown in fig2 a revealed that current does not flow in close vicinity to the surface in the source - to - gate and gate - to - drain segments . rather , current flow in these segments of the device is shown to occur in the bulk material of the source and drain fingers . exemplary doping concentrations and thickness for the layers of the device shown in fig2 are set forth below : fig3 shows a comparison of current flows in a conventional device and in a self - aligned device as described herein . in particular , fig3 is a comparison of the current flow and dc i - v characteristics of a conventional ( left figure ) and a self - aligned ( right figure ) 4h - sic power mesfet structures on semi - insulating substrates with p - type buffer layers . the distribution of current density is simulated at zero gate bias and zero interface trap density ( on the top ), and i - v characteristics have been simulated for the different interface trap densities ( on the bottom ). the simulation was performed using a silvaco atlas ™ 2 - d device simulator for the different values of interface trap density ( d it ). in the simulation shown in fig3 , the conventional and self - aligned mesfets have the same thickness and doping concentration for the channel and buffer layers . as set forth above , the gate of a power sic mesfet can be formed using a self - aligned process . a schematic process flow for self - aligned sic mesfet fabrication is shown in fig4 . this diagram shows only the self - aligned process , and does not include , for example , the device mesa isolation and air - bridge formation process flow for the fabrication of the self - aligned sic mesfet . the process illustrated in fig4 comprises the following steps : step 3 : anisotropic plasma etching through the dielectric layers and source / drain ohmic contact anneal . step 4 : deposition of schottky contact and final metal using evaporation or other anisotropic deposition technique . device mesa isolation and air - bridge formation can be performed using known methods . fig5 illustrates the results of using a gate metallization process that allows for self - aligned metal ( e . g ., gold ) deposition . in this process , the gate thickness is limited only by the trench depth . an sem picture of test structures used for the development of the self - aligned process is shown in the right - bottom corner of fig5 . these structures that had a gate periphery of 20 × 50 λm , and source / gate line widths varying from 1 μm to 2 μm , and have received source / gate au metallization at a thickness of 5 kå . a close - up sem picture of the test structure with source / gate line widths of 1 μm / 1 μm is shown on the left side of fig5 . for the proposed self - aligned mesfet structure , the source - to - gate breakdown voltage is related to the depth of the gate recess and can be adjusted within a wide range . unlike many other so called “ self - aligned ” mesfet - related processes ( e . g ., [ 6 , 7 ]), the self - aligned process described herein is truly self - aligned because it excludes all critical alignment steps from the device fabrication . for example , structures with a 0 . 4 μm wide , 5 kå thick gate metal lines similar to the device depicted in fig5 have been made using a karl suss mjb - 3 contact aligner . the gate metallization technology described can be used for the self - aligned gate or base metal formation of vertical power switching or rf devices such as vjfets , sits , and bjts . this technology can be also used in the fabrication of lateral devices with submicron gate length such as power sic mesfets . although exemplary embodiments are shown in fig2 a - 2b and 4 , other alternatives to the are possible . for example , gan epitaxial layers ( n and p - type ) can be grown on silicon carbide , sapphire , or silicon substrates to form a starting material stack for the fabrication of the device . alternatively , a substrate material comprising a conducting sic substrate ( either of n - type or p - type ) can be used . another exemplary substrate material that can be used is a conducting sic substrate with a semi - insulating epitaxially grown buffer layer as set forth , for example , in casady , et al ., “ silicon carbide and related wide - bandgap transistors on semi - insulating epitaxy for high - speed , high - power applications ,” u . s . patent application publication no . 2002 / 0149021 - a1 , published oct . 17 , 2002 . alternatively , different types of ceramics with high thermal conductivity can be used as a substrate material ( e . g ., aln , al 2 o 3 , beo , etc .). silicon carbide crystallizes in numerous ( more than 200 ) different modifications ( polylypes ). the most important are : 3c - sic ( cubic unit cell , zincblende ); 2h - sic ; 4h - sic ; 6h - sic ( hexagonal unit cell , wurtzile ); 15r - sic ( rhombohedral unit cell ). the 4h polytype is more attractive for power devices , however , because of its higher electron mobility . although the 4h - sic is preferred , it is to be understood that the present invention is applicable to self - aligned power sic mesfets described herein made of other wide bandgap semiconductor materials such as gallium nitride , indium phosphate and other polytypes of silicon carbide , by way of example . the sic layers of the self - aligned structure can be formed by doping the layers with donor or acceptor materials using known techniques . exemplary donor materials include nitrogen and phosphorus . nitrogen is preferred donor material . exemplary acceptor materials for doping sic include boron and aluminum . aluminum is a preferred acceptor material . the above materials are merely exemplary , however , and any acceptor and donor materials which can be doped into silicon carbide can be used . the doping levels and thicknesses of the various layers of self - aligned power sic mesfet described herein can be varied to produce a device having desired characteristics for a particular application . similarly , the dimensions of the various features of the device can also be varied to produce a device having desired characteristics for a particular application . the sic layers can be formed by epitaxial growth on a suitable substrate . the layers can be doped during epitaxial growth . exemplary doping concentration ranges for the sic epitaxial layers of the device are as follows : optional n - type layer : 5 × 10 16 cm − 3 − 3 × 10 17 cm − 3 ; and p - type buffer : 1 × 10 15 cm − 3 − 3 × 10 17 cm − 3 ( e . g ., 3 × 10 15 cm − 3 − 3 × 10 17 cm − 3 ). while the foregoing specifications teaches the principles of the present invention , with examples provided for the purpose of illustration , it will be appreciated by one skilled in the art from reading this disclosure that various changes in form and detail can be made without departing from the true score of the invention . r . c . clarke and john w . palmour , “ sic microwave power technologies ,” proceedings of the ieee , vol . 90 , no . 6 , june 2002 . k . horio , y . fuseya , h . kusuki , and h . yanai , “ numerical simulation of gaas mesfet &# 39 ; s with a p - buffer layer on the semi - insulating substrate compensated by deep traps ,” ieee transactions on microwave theory and techniques , vol . 37 , no . 9 , september 1989 . n . sghaier , j . m . bluet , a . souifi , g . guilliot , e . morvan and c . brylinski , “ influce of semi - insulating substrate purity on the output characteristics of 4h - sic mesfets ,” material science forum vols . 389 - 393 ( 2002 ) pp . : 1363 - 1366 . g . y . chung , c . c . tin , j . r . williams , k . mcdonald , r . k . chanana , robert a . weller , s . t . pantelides , leonard c . feldman , o . w . holland , m . k . das , and john w . palmour , “ improved inversion channel mobility for 4h - sic mosfets following high temperature anneals in nitric oxide ,” ieee electron device letters , vol . 22 , no . 4 , april 2001 . ho - young cha , c . i . thomas , g . koley , lester f . eastman , and michael g . spencer , “ reduced trapping effects and improved electrical performance in buried - gate 4h - sic mesfets ,” ieee transactions on electron devices , vol . 50 , no . 7 , july 2003 . allen , s . t ., “ self - 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