Patent Application: US-201614997887-A

Abstract:
a switch comprising a spin - transistor and a first control wire . the spin - transistor is configured so that when a magnetic field applied to the spin - transistor is less than a threshold value , the transistor is in a conductive state in which electric current flows through the spin - transistor . when the magnetic field applied to the spin - transistor is greater than the threshold value , the spin - transistor is in a resistive state in which the electric current flowing through the spin - transistor is substantially reduced . the first control wire is for receiving a current to affect the magnetic field applied to the spin - transistor .

Description:
the present invention is directed to a very high - speed logic family exploiting a newly developed spintronic switch . the power dissipation of circuits made from this logic family is nearly independent of frequency , providing an advantage over cmos for high - speed applications . fig1 depicts an exemplary magnetoresistive semiconductor heterojunction bipolar spin - transistor 100 consistent with the present invention . although depicted as a pnp transistor , one having skill in the art will appreciate that the present invention can apply to any magnetoresistive amplifying device , such as a pnp or npn bipolar junction transistor , or an n - type or p - type metal - oxide - semiconductor field - effect transistor ( mosfet ). as a three - terminal device designed for large signal amplification , the ability to exploit spin as an additional control allows for the modification and improvement of existing logic families [ 17 ]. emitter - coupled logic ( ecl ), a bipolar junction transistor ( bjt ) family used in very high - speed electronics , can be modified and improved using spin - transistors . one having skill in the art will appreciate that the present invention can also apply to other types of transistor families , such as field - effect , semiconductor or other transistors . circuits designed with ecl and the ecl - based logic families consistent with the present invention dissipate minimal dynamic power , causing the power dissipation to be nearly frequency - independent . as depicted in fig1 , this behavior is in contrast to cmos circuits , in which dynamic power dissipation increases proportionally and deleteriously with frequency . the power dissipated by the emitter - coupled spin - transistor logic ( ecstl ) family of the present invention is significantly less than ecl across all frequencies . this characteristic results in ecstl dissipating less power than cmos at frequencies above 10 ghz , making this logic family an effective technology for high - speed applications . the improved characteristics of the logic family consistent with the present invention are derived from exploiting the magnetic characteristics of the spin - transistors . for example , ecstl circuits consistent with the present invention route ecl differential amplifier currents to create magnetic fields that control the state of spin - transistors . this technique reduces current consumption , and allows for the logic stages to be cascaded similarly to conventional ecl circuits . a smaller number of stages and devices is required to implement logic functions , producing superior logic circuits in terms of speed , power , and area without any significant tradeoffs . the novelty of this logic family lies in the fact that it : ( 1 ) is the first logic family based on magnetoresistive semiconductor heterojunction spin - transistors ; ( 2 ) has cascadable stages ; ( 3 ) is based on high - speed ecl structures making use of the spin - degree of freedom ; and ( 4 ) has the potential to make very high speed computing practical on a large scale . the ecstl logic family of the present invention utilizes magnetoresistive spin - transistors , which are notable for their large decrease in amplification under an externally applied magnetic field . current - carrying control wires can be used to apply this magnetic field , thus controlling the state of the spin - transistors . the use of these structures in a modified ecl structure produces logic gates with exceptional functionality . conventional bjts are formed by connecting two p - n junctions such that a cathode or anode is shared , forming a pnp or npn transistor , respectively . as discussed above , the pnp spin - transistor [ 16 ] is created by doping the emitter of a iii - v transistor with mn , as shown in fig1 . the spin - transistor 100 of fig1 includes a p - type mn - doped emitter 102 , an n - type base 104 , and a p - type collector 106 , each of which has a respective contact 108 , 110 , 112 . as discussed in [ 18 ], the base - emitter junction is magnetoresistive , while the base - collector junction behaves conventionally . in a standard bjt , the relative voltages on the three terminals determine the bias of the two internal diodes , and therefore the region of operation of the transistor . as discussed above , although the description of the preferred embodiment refer to bjt - type spin - transistors , one having skill in the art will appreciate that the present invention can apply to other types of spin - transistors , such as field - effect , semiconductor or other transistors . when the base - emitter junction is forward - biased , a large current flows across this junction , which proceeds across the base - collector junction . in the spin - transistor , the presence of a magnetic field causes the base - emitter junction to become resistive , preventing current from flowing across the junction [ 18 ]. therefore , in the presence of a magnetic field , a forward - biased base - emitter junction in the spin - transistor behaves similarly to a reverse - biased base - emitter junction in a conventional bjt . in both cases , the transistor will not produce large currents , and will remain cutoff rather than in the forward - active region . a more thorough discussion of the effect of a magnetic field on a spin - transistor can be found elsewhere [ 19 ]. the spin - transistor has the additional outstanding feature of a large magnetoresistance at room temperature . experimental data from the device presented in [ 16 ] shows a positive magnetoresistance in an inmnas spin - transistor . one having skill in the art will appreciate that the present invention can also apply to any device exhibiting positive or negative magnetoresistance , in a paramagnetic or ferromagnetic manner . positive magnetoresistance attenuates the current through the spin - transistor , causing the transistor to enter the cutoff region . in the room temperature data provided in fig2 , amplification decreases with increasing magnetic field . by optimizing the fabrication technique , it is possible to achieve much higher amplification in these spin - transistors , approaching those achieved with inas by wicks [ 20 ]. additionally , by increasing the mn concentration , it is possible to increase the giant magnetoresistance ( gmr ) of the junction , resulting in a greater change in amplification with magnetic field . it should be noted that the gmr increases with decreasing temperature , providing an even greater magnetoresistive effect at low temperatures . the characteristics of this exploratory spin - transistor demonstrate its suitability for advanced logic functionality . one novel aspect of the present invention is directed to cascading spin - transistors to implement logical functions . as the flow of charged particles produces a magnetic field , a current flowing near a spin - transistor affects its amplification . a control wire alongside the base - emitter junction of a spin - transistor can therefore be exploited to perform logic [ 3 ]. fig3 depicts an exemplary magnetoresistive semiconductor heterojunction bipolar spin - transistor 300 consistent with the present invention . the spin - transistor 300 includes a p - type mn - doped emitter 302 , an n - type base 304 , and a p - type collector 306 , each of which has a respective contact 308 , 310 , 312 . metal wires 314 are placed parallel to the plane of the base - emitter junction , isolated by an insulator ( not shown ). the wires 314 can be surrounded by a shield 316 to concentrate the magnetic field applied to the spin - transistor 300 , e . g ., through the spin - transistor 300 . these wires 314 control the junction &# 39 ; s magnetoresistive state , as the currents through the wires 314 create magnetic fields perpendicular to the plane of the junction . under zero or small net current , the junction is in its conductive state ; a large net control current asserts the low - amplification resistive state . depending upon the relative direction of the currents , the associated fields combine either constructively or destructively . if the currents in the two wires 314 propagate in opposite directions , the fields will add , doubly suppressing the spin - transistor amplification ; if the currents are in the same direction , the fields will cancel , allowing current to flow through the base - emitter junction . while transistor - transistor logic ( ttl ) has been made largely obsolete by the superior characteristics of cmos , ecl is the most effective logic family at high frequency . ecl consumes a relatively large amount of power , about 50 μw for a basic logic gate , but its small delay makes it useful for very high - speed applications [ 21 ], [ 22 ]. the power dissipation of ecl is roughly equivalent to cmos power dissipation at 40 ghz , making ecl the preferred logic family for computing beyond 40 ghz , as depicted in fig1 . the fundamental building block of ecl , as well as ecstl , is the differential amplifier 400 shown in fig4 . the differential amplifier 400 includes transistor 402 having a base connected to voltage input a , and transistor 404 having a base connected to voltage input b . the collector of transistor 402 is connected through resistor 406 to ground , while the collector of transistor 404 is connected through resistor 408 to ground . the emitters of transistors 402 , 404 are connected through resistor 410 to voltage source v ee . in this circuit , one transistor operates in the active region and the other transistor is in the cutoff region . the relative base voltages of the two transistors determine their states . because the differential amplifier 400 is depicted using pnp transistors , the transistor with a lower base voltage is in the active region , and the transistor with the higher base voltage is in the cutoff region . if transistor 402 is cutoff and transistor 404 is in the active region , greater current passes through transistor 404 and resistor 408 than transistor 402 and resistor 406 . there is therefore a greater voltage drop across resistor 408 than resistor 406 , resulting in a high output voltage at v 2 and a low output voltage at v 1 . this differential amplifier is used with multiple inputs to form the ecl circuits . fig5 depicts the logical gate that can be implemented with the fewest pnp transistors , i . e ., an and / nand gate 500 . and / nand gate 500 includes transistor 502 having a base connected to input a , transistor 504 having a base connected to input b , and transistor 506 having a base held at a constant voltage , v r . the collectors of transistors 502 and 504 are connected through resistor 508 to ground , and the collector of transistor 506 is connected through resistor 510 to ground . the emitters of transistors 502 , 504 and 506 are connected through resistor 512 to voltage source v ee . and / nand gate 500 serves as the basis ecl function . and / nand gate 500 accepts two ( or more ) inputs , a and b , and produces two outputs , the logical and and and of the inputs . because the base of transistor 506 is held at a constant voltage , v r transistor 506 will switch between the active and cutoff regions depending on the behavior of the rest of the circuit . if either or both of the inputs are ‘ 0 ,’ the corresponding input transistor 502 or 504 is in the active region , and transistor 506 is cutoff . there is therefore a large current through resistor 508 and a small current through resistor 510 , causing , respectively , large and small voltage drops across those resistors . therefore , the and output is ‘ 1 ’ and the and output is ‘ 0 .’ if both inputs are ‘ 1 ,’ transistor 506 is in the active region and both transistor 502 and 504 are cutoff , resulting in an and output of ‘ 1 ’ and and output of ‘ 0 .’ the spin - transistors and control wires discussed above can be used to create a modified logic family based on ecl , i . e ., ecstl . this novel logic family of the present invention replaces the standard bjts with spin - transistors and adds control wires as additional inputs . it is therefore possible to realize more complex logical functions without adding any additional circuitry . as discussed above , for a spin - transistor electrically biased in the forward - active region , the presence of a magnetic field causes the base - emitter junction to become resistive . this , in turn , causes the spin - transistor to function similarly to a cutoff transistor , and minimal current flows from the emitter to the collector . control wires determine the spin - transistor region of operation , as listed in table i below . with a sufficient positive difference between the emitter and collector voltages , the spin - transistor is in the active region if the base voltage is low and the control wires produce zero net field through the transistor . this condition can be imposed either by zero current on both of the control wires or by equal and opposite fields produced by the two control wires . in the case of a high base voltage or of a large net magnetic field , the spin - transistor is in the cutoff region . the ecstl family of the present invention is a modified ecl structure in which standard bjts are replaced by spin - transistors and the currents in the differential amplifiers are routed through the control wires of other transistors . the current through resistor 508 or 510 in the and / nand gate 500 of fig5 is routed near a spin - transistor to create an additional control signal for the spin - transistor . the differential pair amplifies the difference between the inputs of the bases ; there is a large ratio of current through the active transistor relative to the cutoff transistor . this large current ratio allows for a clear differentiation between a large and small magnetic field , within the tolerances of the spin - transistor magnetoresistance . the additional inputs to the spin - transistors allow for the compact evaluation of complex logic functions . the ability to perform a three - input logical function within a single transistor makes possible significantly more complex functions within a single stage of logic . the use of control wires does not imply the flow of additional current , as the control wire currents are already necessary for the differential amplifier and are simply rerouted to control the spin - transistors . however , the routing of the various wires in the circuit is significantly more complex than in standard ecl . current is an ecstl state variable in addition to voltage . each logic gate accepts voltage and current inputs and produces voltage and current outputs . the currents are either large or small , a ‘ 1 ’ or ‘ 0 ,’ respectively . these currents are used in the control wires of the spin - transistors and are proportional to a magnetic field [ 3 ]. in order to match the experimental data and conventional ecl quantities , conservative ‘ 1 ’ values of 5 t and 1 . 3 v are chosen , along with ‘ 0 ’ values of 0 t and 0 . 7 v . optimized ecstl devices and circuits should enable decreased current , voltage , and magnetic field , significantly reducing power consumption . fig6 depicts the general ecstl basis gate 600 in accordance with the present invention , from which any logical function may be derived . gate 600 includes spin - transistor 602 having a base connected to input voltage a , spin - transistor 604 having a base connected to input voltage b , and spin - transistor 606 having a based held at constant voltage v r . the collectors for spin - transistors 602 and 604 are connected through resistor 608 to ground , while the collector for spin - transistor 606 is connected through resistor 610 to ground . the emitters for spin - transistors 602 , 604 and 606 are connected through resistor 612 to voltage source v ee . spin - transistor 602 is depicted with two control wires 614 , 616 having current inputs c and d , spin - transistor 604 is depicted with two control wires 618 , 620 having current inputs e and f , and spin - transistor 606 is depicted with two control wires 622 , 624 having current inputs g and h . although gate 600 is depicted with two spin - transistors , one having skill in the art will appreciate that the logic circuits consistent with the present invention may only have one spin - transistor , or multiple spin transistors . also , although each spin - transistor is depicted with two control wires , one having skill in the art will appreciate that the spin - transistors included in the logic circuits consistent with the present invention may only have one control wire , or multiple control wires . in addition , the currents through each control wire may flow in either direction , and are not limited to those illustrated in fig6 . as shown , the gate 600 in fig6 includes two voltage inputs , a & amp ; b , and six current inputs , c - h , for a total of eight inputs . the presence of a net current through the control wires forces the spin - transistor into the cutoff region . a cutoff transistor has a large collector - emitter impedance , and therefore directs current elsewhere in the circuit . each spin - transistor can perform a three - input logic computation . this structure permits the computation of more complex logic within a single stage without requiring additional transistors . as each stage requires the same amount of current , the use of fewer stages implies less current flow . since fewer transistors are required to perform a logic function , there is increased circuit efficiency in terms of power dissipation , propagation delay , and physical area . the logic family of the present invention can be used to design highly compact circuits , and these logic gates can be cascaded to perform any logical function . for example , current flowing through resistor 406 or resistor 408 in differential amplifier 400 of fig4 may be used to provide the current input for a spin - transistor control wire . fig7 and 10 - 12 illustrate sample complex logic circuits consistent with the present invention . the functionality of these circuits has been verified to ensure suitable cascading characteristics . simulations based on the models discussed in [ 17 ] have been performed using synopsis hspice [ 23 ]. these simulations demonstrate the ability to create large - scale integrated ecstl circuits . as the magnetic field magnitudes bear a more direct relation to the spin - transistor models than the current magnitudes , the input and output values of the gates are discussed in terms of magnetic fields and voltages rather than currents and voltages . the simplest circuit demonstrating the principles of ecstl is the inverter / buffer 700 depicted in fig7 . inverter / buffer 700 includes spin - transistor 702 , reference transistor 704 , inverter transistor 706 and buffer transistor 708 . spin - transistor 702 has a base connected to voltage input a and a control wire 710 having a current input b . the collector for spin - transistor 702 provides the voltage input to the base of inverter transistor 706 , and is connected through resistor 712 to ground . the collector for reference transistor 704 provides the voltage input to the base of buffer transistor 708 , and is connected through resistor 714 to ground . the emitters for spin - transistor 702 and reference transistor 704 are connected through resistor 716 to voltage source v ee . the emitter for inverter transistor 706 is connected through resistor 718 to voltage source v ee , and the emitter for buffer transistor 708 is connected through resistor 720 to voltage source v ee . in the absence of a magnetic field , the circuit functions as a conventional differential amplifier . if input a is a low voltage and b produces a small field , spin - transistor 702 is in the active region , and draws more current than reference transistor 704 . the current through resistor 716 is therefore directed through resistor 712 , resulting in a ‘ 1 ’ current through resistor 712 and a ‘ 0 ’ current through resistor 714 . these currents produce a large voltage on the base of inverter transistor 706 and a small voltage on the base of buffer transistor 708 . a ‘ 1 ’ voltage is therefore propagated to the inv output and a ‘ 0 ’ voltage is propagated to the buf output . if there is a large current on the b input , spin - transistor 702 is cutoff . the current therefore flows through resistor 714 and produces opposite values for the output voltages and currents . the outputs are similar if a is a large voltage . this circuit therefore selectively performs the inverter / buffer function . while conventional electronic circuits are generally analyzed with a voltage transfer characteristic , the use of current / field outputs and inputs necessitates a more complex analysis . fig8 is a voltage transfer characteristic showing the switching of the circuit &# 39 ; s outputs in response to changing the input voltage a . in this simulation , the magnetic field input b is held constant at 0 t in order to isolate the effects of the voltage input . as the spin - transistors are not affected by a magnetic field , this circuit functions similarly to a conventional ecl inverter / buffer . when the input voltage is 0 v , the inverted output voltage and field is high and the buffered outputs are low . at slightly higher input voltages , the inverted outputs reach a peak voltage as occurs in conventional ecl [ 24 ]. when the input voltage is equal to the reference voltage , the inverted and buffered outputs are equivalent . finally , a large input voltage results in ‘ 0 ’ inverted outputs and ‘ 1 ’ buffered outputs . the response to a changing input magnetic field is shown in the field transfer characteristic of fig9 . with the input voltage a held constant at 0 . 7 v , the input field b is varied from 0 t to 5 t . as b increases , the magnetoresistive properties of the spin - transistors force spin - transistor 702 into the cutoff region , causing current to flow through resistor 714 . this results in a monotonic decrease in the inverted output magnitudes , and a monotonic increase in the buffered magnitudes . one example of the compactness of ecstl is that multiplexer circuits can be reduced to a single stage of logic . specific implementations of the general circuit 600 depicted in fig6 are discussed below which perform multiplexing functions . these multiplexer circuits are far more compact than conventional ecl multiplexer circuits , which require multiple stages of logic and at least 20 transistors . these circuits are also more compact than standard cmos circuits , which require twelve transistors and two stages , and are comparable to cmos transmission gate multiplexers , which represent one of the greatest strengths of cmos [ 25 ]. fig1 depicts a 2 : 1 multiplexer 1000 consistent with the present invention . multiplexer 1000 includes spin - transistors 1002 , 1004 and reference transistor 1006 . spin - transistor 1002 has a base connected to voltage input a and a control wire 1008 having a current input sel . spin - transistor 1004 has a base connected to voltage input b and a control wire 1010 having current input sel . the collectors for spin - transistors 1002 , 1004 are connected through resistor 1012 to ground . reference transistor 1006 has a base connected to a constant voltage source v r . the collector for reference transistor 1006 is connected through resistor 1014 to ground . the emitters for spin - transistors 1002 , 1004 and reference transistor 1006 are connected through resistor 1016 to voltage source v dd . in 2 : 1 multiplexer 1000 , when the sel wire carries current , spin - transistor 1002 is in the cutoff region . when sel does not carry current , the sel wire carries current , causing spin - transistor 1004 to be cutoff . thus , sel chooses which spin - transistor 1002 , 1004 responds to its input . the correct signal is propagated to the output in both inverted and non - inverted forms . fig1 depicts a 4 : 1 multiplexer 1100 consistent with the present invention . multiplexer 1100 includes four spin - transistors 1102 , 1104 , 1106 , 1108 and a reference transistor 1110 . spin - transistor 1102 has a base connected to voltage input a and two control wires 1112 , 1114 , where control wire 1112 receives current input sel 0 and control wire 1114 receives current input sel 1 . spin - transistor 1104 has a base connected to voltage input b and two control wires 1116 , 1118 , where control wire 1116 receives current input sel 0 and control wire 1118 receives current input sel 1 . spin - transistor 1106 has a base connected to voltage input c and two control wires 1120 , 1122 , where control wire 1120 receives current input sel 0 and control wire 1122 receives current input sel 1 . spin - transistor 1108 has a base connected to voltage input d and two control wires 1124 , 1126 , where control wire 1124 receives current input sel 0 and control wire 1126 receives current input sel 1 . the collectors for spin - transistors 1102 , 1104 , 1106 , 1108 are connected through resistor 1128 to ground . reference transistor 1110 has a base connected to a constant voltage source v r and a collector connected through resistor 1130 to ground . the emitters for spin - transistors 1102 , 1104 , 1106 , 1108 and the emitter for reference transistor 1110 are connected through resistor 1132 to voltage source v dd . the control wires 1112 - 1126 in 4 : 1 multiplexer 1100 implement a nor function to select the spin - transistor 1102 - 1108 in operation . if either of a spin - transistor &# 39 ; s control wires carries current , that spin - transistor is cutoff . therefore , exactly one spin - transistor is in operation at all times , and the selected input is propagated to the output along with its complement . hspice simulations have been performed on the 2 : 1 multiplexer 1100 shown in fig1 . as listed in table ii below , each state is characterized by a voltage and a magnetic field . the simulations show correct outputs that are clearly identifiable as a ‘ 1 ’ or ‘ 0 ,’ although different combinations of inputs produce slightly different output voltages . these slight variations are due to the presence of multiple active input transistors resulting in a stronger signal than is caused by a single active input . fig1 depicts a full adder 1200 consistent with the present invention . full adder 1200 includes seven spin - transistors 1202 - 1214 . spin - transistor 1202 has a base connected to voltage input a and two control wires 1216 , 1218 , where control wire 1116 receives current input b and control wire 1218 receives current input c in . spin - transistor 1204 has a base connected to voltage input a and two control wires 1220 , 1222 , where control wire 1220 receives current input b and control wire 1222 receives current input c in . spin - transistor 1206 has a base connected to voltage input a and one control wire 1224 that receives current input b . spin - transistor 1208 has a base connected to voltage input a and one control wires 1226 that receives current input c in . spin - transistor 1210 has a base connected to voltage input a and two control wires 1228 , 1230 , where control wire 1228 receives current input b and control wire 1230 receives current input c in . the collectors for spin - transistors 1202 , 1204 are connected through resistor 1232 to ground , and the collectors for spin - transistors 1206 , 1208 , 1210 are connected through resistor 1234 to ground . the bases for reference transistors 1212 , 1214 are connected to constant voltage source v r , and through resistor 1240 to ground and resistor 1242 to voltage source v ee . the collector for reference transistor 1212 is connected through resistor 1246 to ground , and the collector for reference transistor 1214 is connected through resistor 1248 to ground . the emitters for spin - transistors 1202 , 1204 and the emitter for reference transistor 1212 are connected through resistor 1236 to voltage source v ee . the emitters for spin - transistors 1206 , 1208 , 1210 and the emitter for reference transistor 1214 are connected through resistor 1238 to voltage source v ee . full adder 1200 contains two distinct sections , one each for the sum and c out logic . the functions have been specifically optimized for ecstl using de morgan &# 39 ; s laws : in the center of the circuit , a voltage divider sets a reference voltage v r for the two reference transistors 1212 , 1214 . for the sum logic , the control wires carry current in opposite directions , and therefore implement the xor function . spin - transistor 1202 is in the active region when both a and b ⊕ c in are ‘ 0 ,’ and is otherwise cutoff . spin - transistor 1204 is in the active region when a is ‘ 1 ’ and b ⊕ c in is ‘ 0 .’ if either or both spin - transistor 1202 or spin - transistor 1204 are in the active region , significant current flows through resistor 1232 . this current causes sum to reach a high voltage , and sum a low voltage . the logic for c out and c out functions similarly . the operating regions of spin - transistors 1206 , 1208 , 1210 depend upon the adder inputs . if at least one of these transistors is in the active region , current is diverted from resistor 1248 . there is therefore a large current through resistor 1234 with a corresponding voltage drop across resistor 1234 , resulting in a ‘ 1 ’ output for c out . if all of the input transistors are cutoff , reference transistor 1214 is in the active region and current flows through resistor 1248 , resulting in a ‘ 1 ’ output for c out . this full adder is unique in its use of only a single stage of logic to produce all of the outputs . as each stage of logic adds to a signal &# 39 ; s propagation time , the use of a single stage provides exceptional speed characteristics . it is also compact , using only 7 spin - transistors . this circuit compares favorably to a standard ecl full adder , which requires 24 transistors , and the cmos version , which requires 28 transistors . in addition , both of these conventional circuits require multiple stages of logic , limiting circuit speed . ecstl therefore provides circuits with higher performance while also dissipating less power and using less area . simulations have also been performed on the full adder shown in fig1 . as above , there are variations between ‘ 0 ’ and ‘ 1 ’ values , but there is clear differentiation between the two binary states . this can be seen in table iii below , where the voltage and field inputs are shown in relation to the outputs . adapted from [ 26 ], the primary computing metrics are power , performance , area , operating temperature , scalability , and cascading characteristics . economic factors such as yield , cost , and reliability are also important . to be effective for general - purpose computing , a logic family preferably exhibits good characteristics for all of these metrics . as mentioned above , cascading and room temperature operation are significant challenges facing spintronic computing . the primary mechanism for power dissipation in ecl and ecstl circuits is the constant flow of current from the high voltage rail , v ee , to ground . applying the standard formula for power dissipation , p = iv , where p is power , i is current , and v is voltage , a conventional ecl gate dissipates about 50 μw [ 22 ]. though the state of the various transistors within an ecl gate and the output voltage of the gate affect the current path within the gate circuit , the magnitude of the current within each gate is constant . the state of a logic gate therefore has minimal effect on its power dissipation . the power dissipation mechanisms of ecstl are identical to ecl ; the constant current flow through the differential amplifiers and voltage followers constitute the primary source of dissipated power . this power dissipation is almost completely frequency - independent . in the logic family of the present invention , as well as conventional ecl , the power dissipation of a computing circuit is proportional to the number of logic stages . as noted in the multiplexer and adder circuits , this ecstl family can execute logical functions using 20 % to 30 % of the number of devices required for conventional ecl while drawing the same amount of current per device . this implies a corresponding decrease in power dissipation of 70 % to 80 %. the gate delay of ecstl is determined by the switching time of the transistors within the gate . the high - speed ecl family from which it is derived has exceptional performance , with heterojunction bipolar transistors demonstrating functionality beyond 200 ghz [ 27 ]. the magnetic switching time is on the order of 1 ps [ 28 ]; the gate delay is therefore determined by the conventional electrical switching time of the transistors . the delay of a circuit is the summation of the delays of the individual stages , and is therefore proportional to the number of stages in the circuit . due to the compact circuits possible with ecstl , the number of stages required to perform a particular logical function is 3 × to 5 × fewer . there is therefore a proportional decrease in delay , showing the potential of this logic family for very high speed computing . as with ecl , the area consumption of the ecstl family is increased by the heavy use of resistors . however , the compact logic structures available with ecstl mitigate this issue to some degree . an additional issue related to area , not present in ecl , is the size of the control wire structure and the distances between control wires . there is also a minimum distance by which spin - transistors will need to be separated in order to prevent unintended interactions between the magnetic field of a control wire and a neighboring spin - transistor . as discussed in [ 16 ], the spin - transistor magnetoresistance is dependent on temperature . while the magnetoresistance is sufficient for room temperature logical functionality , the effect is stronger at lower temperatures . ecstl can function from very low temperatures to temperatures slightly above room temperature , roughly 350 k . at lower temperatures , less current is required , leading to decreased power consumption . in addition to being compact , this logic family can be cascaded for application to large computing systems and scaled to small dimensions without adverse effects . scaling leads to substantial speed - up and decreased power dissipation , presenting the opportunity for large - scale adaptation of ecstl . as the magnetic field created by the control wires is inversely proportional to the device size d , this technology is suitable for scaling . a constant i / d ratio produces a constant magnetic field , making it possible to decrease the current i , and therefore the power , with scaling . this behavior is in contrast to conventional circuit technologies based purely on electron charge , which are difficult to scale to ever smaller dimensions [ 29 ]. the match between the input and output voltage and field levels permit ecstl circuits to be cascaded . the voltage nodes are connected directly from an output to an input without any concern regarding the flow of current from the output to the input . the voltage followers allow for a large fan - out of the voltage outputs , as in ecl . the fan - out characteristics of the current / field outputs are more complex : many inputs can be driven by a single current / field output and the maximum number is limited by the wire parasitic impedances . as the current / field output is a leg of the differential amplifier , the parasitic resistance of the wire should be deducted from the resistor value . contemplation of the wire characteristics and routing is significantly more complex than in conventional logic families . the diverse set of input and output varieties , however , allows for highly flexible circuit design and therefore customized compact circuits . the large gain of spin - transistors provides excellent noise tolerance . a small - to - moderate deviation from the correct input of a differential amplifier does not affect the current path , as the large gain ensures that a differential pnp transistor with a slightly lower base voltage or current / field draws the lion &# 39 ; s share of the current . the output voltages of the logic gate will therefore be correct and unaffected by a noisy input . this noise attenuation exemplifies the strong signal integrity characteristics of ecstl . ecstl is a spintronic logic family that makes effective use of the spin - degree of freedom for logical computing . unlike other proposed spintronic logic families , this logic family has a clear method for cascading logic circuits in a manner that ensures signal integrity . room temperature operation is also an important feature of ecstl . given the 3 × to 5 × speedup and 70 % to 80 % decrease in power consumption , there is a 10 × to 25 × decrease in power - delay product as compared to ecl . ecl and ecstl circuits dissipate minimal dynamic power , causing the power dissipation to be nearly independent of frequency . this behavior is in contrast to cmos circuits , as depicted in fig1 [ 27 ], [ 30 ]. ecstl has an equivalent power dissipation to cmos at 10 ghz , a 50 % decrease at 20 ghz , and a 75 % decrease at 40 ghz . this greater than an order - of - magnitude improvement enhances the range of applications for which ecl - based logic is effective to provide a pathway for high - performance spintronic computing beyond 10 ghz . while various embodiments of the present invention have been described , it will be apparent to those of skill in the art that many more embodiments and implementations are possible that are within the scope of this invention . accordingly , the present invention is not to be restricted except in light of the attached claims and their equivalents . e . y . tsymbal and i . zutic , eds ., handbook of spin transport and magnetism . boca raton , fla . : crc press , 2012 . s . a . wolf , j . lu , m . r . stan , e . chen , and d . m . treger , “ the promise of nanomagnetics and spintronics for future logic and universal memory ,” proc . ieee , vol . 98 , pp . 2155 - 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