Patent Application: US-201313887949-A

Abstract:
superconducting integrated circuits require several wiring layers to distribute bias and signals across the circuit , which must cross each other both with and without contacts . all wiring lines and contacts must be fully superconducting , and in the prior art each wiring layer comprises a single metallic thin film . an alternative wiring layer is disclosed that comprises sequential layers of two or more different metals . such a multi - metallic wiring layer may offer improved resistance to impurity diffusion , better surface passivation , and / or reduction of stress , beyond that which is attainable with a single - metallic wiring layer . the resulting process leads to improved margin and yield in an integrated circuit comprising a plurality of josephson junctions . several preferred embodiments are disclosed , for both planarized and non - planarized processes . these preferred and other methods may be applied to digital circuits based on rapid single flux quantum logic , and to quantum computing using josephson junction qubits .

Description:
one preferred embodiment of the invention is obtained by modifying the standard hypres ic process shown in fig1 by including an extra al layer on the nb layers , as shown in fig2 a - 2d . this achieves , for example , a bilayer or trilayer conductor , which protects surrounding structures from the effects of e . g ., hydrogen absorbed in the niobium , and may also provide a penta ( hexa ) layer josephson junction with the niobium layers externally isolated . as noted above , the josephson junction may inherently include an aluminum layer between the underlying niobium layer and the oxide ; it is therefore possible to add a thin layer of aluminum over the oxide , to provide a generally symmetric structure . this added layer may require an additional etch step , and is not generally necessary ; likewise , the intrinsic aluminum layer within the josephson junction trilayer is typically insufficient to achieve the advantages according to aspects of the present technology . note that the aluminum layer remaining after oxidation is thin , and may be sufficiently porous to permit diffusion of gasses such as hydrogen . further , the known technique permits the aluminum layer only under the oxide , and therefore it serves no protective function from the overlayer . a first embodiment of the method replaces a standard “ trilayer ” ( nb / al / alox / nb or nb / al / alox / al / nb ) deposition over the wafer containing patterned wiring , interlayer insulator and / or resistor layers which are located below the josephson junction layer ( as dictated by circuit design and process layer sequence ) by in - situ deposition of a “ quadralayer ” m / nb / al / alox / nb or m / nb / al / alox / al / nb , where m is a normal ( nonmagnetic ) or superconducting metal other than nb . this extra metal layer works as , for example , a diffusion barrier ( stop layer ) for interlayer diffusion of impurities , a sink which absorbs impurities which diffuse to the boundary , and has a sufficiently high partition coefficient to selectively retain those impurities against further diffusion , or a reactive metal which coordinates with or bonds to the impurities and thus prevents further diffusion , in superconducting layers of integrated circuits . since the most mobile impurity is hydrogen , this extra layer should preferably prevent interlayer diffusion of hydrogen through the metal layer to adjacent layer ( s ). this can be achieved if , on one hand , the m - layer has low solubility of hydrogen or low diffusion coefficient of hydrogen , or on the other hand , a very high solubility of , or chemical reactivity toward , hydrogen . on the other hand , this layer should preferably be compatible with the basic processes , not degrade superconducting properties of nb layers in direct contact with this extra layer , and not degrade the critical current of the contact between two superconducting layers , not introduce additional mechanical stress , etc . in a particularly preferred implementation , the m - layer is an al layer with thickness from 1 nm to ˜ 10 nm . al has lower solubility of hydrogen than nb and lower diffusion coefficient . an additional benefit is that al is a more pliable ( plastic ) material than nb . therefore , such an al underlayer works also as a stress relief layer by reducing mechanical stress on the alox tunnel barrier of josephson junctions . this stress reduction also helps to improve reproducibility and yield . it is noted that the present technology may also be applied to superconducting electronic integrated circuits based on superconductivity of other materials than niobium metal , such as niobium nitride . it is also preferred that the m - layer should have good adhesion to the interlayer dielectric and to superconducting layers ( nb ). superconductivity in the m - layer is induced by the proximity effect , whereby a non - superconducting material becomes a superconductor by close proximity of a strongly superconducting material . ( note that although al becomes superconducting below about 1k , these circuits are designed to operate at 4k , so that the al layer is superconducting only by its strong contact with the nb layer at the operating temperature .) this sets some restrictions on the possible choice of normal metals . they should preferably have long enough coherence length (˜ ℏv f / k b πt ), low mismatch of the fermi velocity v f with nb , etc . so , other possible implementations provide m = mo , re , ti , zr , mg , and some other transition metals , for example cu , zn . pd or other metals may be used to coordinate with hydrogen , and form a superconductive hydride . the m - layer should also preferably be etch - compatible with superconducting electrodes ( nb ) because it is preferably patterned along with patterning of the base electrode of josephson junctions , in order to avoid additional mask steps . some superconducting alloys and compounds can also be used , e . g . superconducting nitrides or carbonitrides of nb and mo ( nbn and mon , nbcn , etc . ), nbti and nbzr alloys , nbtin , mgb 2 , etc . the typical deposition of a wiring layer ( nb ) according to the prior art over patterned josephson junctions and resistors ( over the interlayer dielectric with contacts and vias to the junctions , resistors , and other wiring layers below the junctions ), may be modified with an in - situ deposition of a wiring bi - layer m / nb , where m serves similar purposes as above and has similar target properties as indicated above . in the simplest implementation m is al ( 1 nm to ˜ 10 nm ). this bi - layer is then patterned to form wiring between the junctions , resistors and other circuit elements in one or two etch steps using the same photoresist mask . this second diffusion barrier ( diffusion stop - layer or protective layer ) and stress relief layer now protects the counter electrode of the junctions from diffusion of impurities from wiring layers above the junction layer , and from extra stress induced by upper writing layers . so in essence , any single superconducting layer may be replaced by in - situ deposited bi - layer m / nb or by a tri - layer m ′/ nb / m ″, and this may extend to each such layer . another aspect of the present invention is that it is compatible not only with a non - planarized fabrication process as shown in fig1 and 2 a - 2 d , but also with a planarized process , described in further detail below . existing superconductor digital electronics manufacturing technology lacks a superconducting plug technology , particularly a technology that is compatible with next - generation planarized processes . in the current state - of - the art , contacts between wiring layers are made by etching contact holes in interlayer dielectric , and then depositing a superconducting layer over the patterned interlayer dielectric , e . g ., as shown in fig3 a - 3b . fig3 a to 3b show a prior art process of making superconducting contacts between two superconducting layers m0 and m1 , consisting of the following steps : a ) layer m0 deposition on a base layer of dielectric ( i s ); d ) interlayer dielectric patterning consisting of lithography , etching , photoresist stripping ( fig3 a ); and e ) layer m1 deposition over the patterned interlayer dielectric ( fig3 b ). since the contact should be able to carry significant superconducting current , the second wiring layer should cover the step in the interlayer dielectric . to improve step coverage , the contact hole is usually etched with sloped walls as shown in fig3 a and 3b . this is achieved by creating a sloped photoresist profile and using photoresists which erode ( etch ) during etching of the ild , such that the contact hole opening at the bottom of the resist increases as etching progresses . however , it becomes progressively more difficult to fill contact holes when their size becomes less than ˜ 1 μm , and the critical current of such contacts usually diminishes . contact holes also create an additional topography as the number of layers in the integrated circuit increases . this topography makes it difficult to perform photolithography due to the depth of focus limitations . it also increases the thickness of metal and dielectric layers deposited over the topography in order to cover the steps formed . this restricts the total number of layers in the unplanarized structure as well as restricts the usefulness of upper ( thick ) layers as circuit inductors . therefore , a planarized process with superconducting studs ( plugs ) between superconducting and resistive layers of superconductor integrated circuits is advantageous . the superconducting contact between superconducting layers in integrated circuits is formed by the following method , shown schematically in fig4 a to 4f . fig4 a - 4f show a process of superconducting plug formation between , e . g ., layers m0 and m2 of the integrated circuit by using in - situ - deposited josephson junction trilayer m1 , which consists of m1 / be base electrode , barrier b , and m1 / ce counter electrode , not shown in fig4 a - 4f . the same process can be used to form a superconducting contact between any pair of superconducting layers . first , instead of a continuous metal layer ( as in the prior art ), a trilayer consisting of two superconducting layers separated by a stop layer is deposited in - situ over the wafer ( m0 , pl1 and m1 shown in fig4 a ). the thickness of the first layer m0 in the trilayer is equal to the desired thickness of the wiring layer m0 , the thickness of the second superconducting layer m1 is equal to the desired thickness of the interlayer dielectric i0 ( the height of the plug ), and the stop layer thickness is much smaller than the thickness of the superconducting layers m0 , m1 . in the preferred implementation , superconductor layers are nb layers with a thickness between 100 nm and 300 nm . the stop layer is a thin metal layer which may have a smaller etch rate than the superconducting layers under the etching conditions ( etch chemistry and / or etch power ) employed to etch the superconducting layers . in the preferred implementation , the etch stop layer is a thin al layer with thickness in the range of 1 - 10 nm . other possible stop layers in combination with nb layers are thin layers of mo , ti , etc . in the preferred implementation , the etch stop layer also serves as a protective ( diffusion stop ) layer . second , the superconducting stud ( plug ) is formed by using photolithography to form an etch mask , and dry etching ( rie , icp , etc .) used to remove the top superconducting layer of the trilayer in the areas not protected by the photoresist , as shown in fig4 a . the etching stops at the stop layer of the trilayer , as shown in fig4 b . third , the exposed stop layer may be removed using either a second dry etching ( in a different chemistry or with different etch parameters ), or ar ion milling , or a wet etching , as shown in fig4 b . alternately , the stop layer may be retained , for example to serve as a protective layer . fourth , a new lithographic step is performed to pattern the bottom layer m0 of the trilayer m0 - pl1 - m1 , which should have the pattern corresponding to the design pattern of layer m0 . the bottom layer is then etched using dry etching ( rie , icp , etc .). the photoresist mask is then removed by stripping the photoresist chemically or by dry etching , as shown in fig4 c - 4d . fifth , the interlayer dielectric is deposited all over the wafer . then , it is planarized by chemical mechanical polishing , as shown in fig4 e . the planarization process is stopped when the deposited dielectric has been removed ( polished away ) from tops of the plugs etched in the trilayer . a short dry etch step may follow , in order to remove the residue of the dielectric from the surface of plugs formed in the second step above . in the preferred implementation , the interlayer dielectric can be silicon dioxide sio 2 , silicon nitride ( sin x ), silicon oxinitride ( sio x n y ), and amorphous or polycrystalline silicon . sixth , the superconducting layer m2 is deposited over the entire wafer , adhering to the surface of the planarized interlayer dielectric and clean surface of superconducting studs ( plugs ) m1 as shown in fig4 f . for some applications of the process , e . g . for superconductive circuits for quantum computing , superconducting qubits , etc ., it may be advantageous to keep the etch stop layer over the bottom superconducting layer , because the stop layer can be designed such that it also protects the top surface of the bottom layer from oxidation , reaction with process gases , atmospheric moisture , etc . and hence improve the performance of superconducting qubits by reducing losses of energy and decoherence of qubits caused by the surface of superconducting layers . another implementation of the process for superconducting plugs ( studs ) between two superconducting layers , e . g ., m0 and m2 is shown in fig5 a - 5f . in this case the etch stop layer is left over the surface of layer m0 , and works as a surface protection ( surface modification ) layer enhancing the performance of layer m0 , e . g ., at microwave frequencies . after the trilayer m0 - pl1 - m1 deposition , and optical ( e - beam ) lithography ( fig5 a ), the superconducting studs ( plugs ) are etched in the top layer m1 of the trilayer . etching stops at the middle layer pl1 of the trilayer . the photoresist mask shown in fig5 b is then removed . the second photoresist is spun - on , and the second photo - ( or e - beam ) lithography is performed to form an etch mask for the bottom layer m0 of the trilayer . the middle layer pl1 of the trilayer is then etched using either dry or wet etching , or ar ion milling to expose the surface of the bottom layer m0 of the trilayer , as shown in fig5 c . the bottom layer is then etched using dry etching ( rie , icp , etc .) as shown in fig5 d . from this point on the process follows steps 5 and 6 described above , to form the planarized dielectric , and to deposit the next superconducting layer m2 , as shown in fig5 e and 5f . since the superconducting plugs in the i1b interlayer dielectric never overlap with the holes ( moats ) in the bottom superconducting layer m0 , the patterning of the top m1 and bottom m0 layers of the trilayer can also be completely reversed , as shown in fig6 a - 6f . fig6 a - 6f shows an inverted process of forming superconducting plugs ( studs ) using a trilayer m0 - pl1 - m1 . in this case , the first photoresist mask applied corresponds to the pattern required for bottom layer m0 , as shown in fig6 a - 6b . the etch stop layer pl1 is removed by dry or wet etching , or by ion milling . after etching the top layer m1 of the trilayer , the photoresist is stripped and the second photoresist mask is applied corresponding to the pattern required for superconducting plugs m1 , as shown in fig6 c . the second dry etching follows , to remove all metal layers m1 , m0 which are not protected by the second photoresist mask or etch stop layer ( the bottom layer m0 and the top layer m1 of the trilayer are being etched here simultaneously ). the etching stops on the middle layer pl1 of the trilayer , which works as an etch stop , as shown in fig6 d . idl i1b deposition and planarization is then performed , as shown in fig6 e , followed by deposition of the next superconducting layer m2 , as shown in fig6 f . the process can be easily extended if more superconducting wiring layers are required . in this case , instead of a single superconducting layer m2 as above , as shown in fig6 f , a second superconducting trilayer m2 - pl2 - m3 is deposited in - situ all over the wafer , as shown in fig7 a . their functions are exactly the same as in the first trilayer m0 - pl1 - m1 . the thickness of m2 layer is equal to the desired thickness of the second wiring layer ( in the range from ˜ 100 nm to ˜ 300 nm ), the thickness of the top layer m3 is equal to the required thickness of the second interlayer dielectric 12 . the middle layer pl2 is a thin layer ( 1 - 10 nm ) serving as an etch stop layer and surface protective layer for the second wiring layer m2 . the patterning of the top m3 , middle pl2 , and bottom m2 layers of the second trilayer m2 - pl2 - m3 is performed analogously to the pattering of the trilayer m0 - pl1 - m1 . after stripping the resist shown in fig7 a , the top layer m3 of the trilayer is etched and the resist p removed , as shown in fig7 b . a further resist layer p is deposited and patterned , as shown in fig7 c , and etching performed through the lower portion m2 of the trilayer as shown in fig7 d . the resist p is then removed , as shown in fig7 e . a second interlayer dielectric 12 is deposited over the wafer as shown in fig7 f . the dielectric 12 is planarized by using chemical mechanical polishing , as shown in fig7 g . then , a third trilayer m4 - pl3 - m5 may be deposited over the planarized surface as shown in fig7 h . the same processing continues until all superconducting layers and contacts ( plugs ) between them are formed . it can be seen from fig4 - 7 that each of the superconducting plugs formed by the proposed method contains one etch stop layer ( the middle layer of the deposited trilayers ). it is convenient to choose a material for the etch stop layers such that it also prevents diffusion of impurities between adjacent superconducting layers , that is , it also works at a diffusion stop layer . in this case , the diffusion of impurities between superconducting layers , which can only occur through contacts ( plugs ) between them , will be greatly reduced . in the preferred implementation , migrating impurities are mainly hydrogen and oxygen which can be absorbed by nb layers during wafer processing or storage due to reaction with air and moisture . a thin aluminum layer ( from ˜ 1 to 10 nm ) can significantly impede diffusion of hydrogen and oxygen , and at the same time is an excellent etch stop layer for etching in fluorine - based chemistries used for etching nb layers of superconductor integrated circuits . a molybdenum layer (˜ 1 nm to ˜ 5 nm ) is another option . a magnesium ( mg ) thin film (˜ 1 nm to 10 nm ) will work as well . al has extremely low solubility of hydrogen , ˜ 6 × 10 − 6 % at room temperatures . hydrogen diffusivity in al at room temperatures can vary by a few orders of magnitude according to different data , being in the range from 10 − 10 cm 2 / s to 10 − 7 cm 2 / s [ 22 ]-[ 24 ]. even in the worst case , it is at least two orders of magnitude lower than in nb . combined with the extremely low solubility , this makes al a very efficient diffusion barrier for hydrogen . a 10 - 50 nm thick ti layer , which acts as a getter ( hydrogen extraction layer ), may be provided which is placed such that the critical current of all contacts between superconducting layers is not reduced due to the presence of this non - superconducting ( at the temperature of circuit operation ) layer . this can be done by a lift off process when ti is removed from the places of the future contact holes between the layer , or by etching ti in these contact holes . in some cases , a thin layer of ti may remain on the surface of a superconductor , and itself be induced into a superconductive state by proximity , and therefore under these circumstances , removal is not necessary . the processes described above are designed primarily for superconductor integrated circuits based on rapid single flux quantum ( rsfq ) logic . a new class of applications relates to quantum computing , whereby the josephson junctions are formed into “ qubits ”, and it is essential to minimize qubit decoherence associated with surface and volume defects . the multilayer approaches described herein can easily be extended to provide improved performance for quantum computing . for qubit applications , one can add extra layers that may comprise layers of insulators with low dielectric loss . their purpose it to protect the surfaces of the main superconductor comprising the qubits ( e . g ., nb ) from forming lossy oxides and from absorbing gases , etc . which induce surface loss in qubits . the layers may also be formed of metals ( superconducting and nonsuperconducting ) with lower surface loss or lower reactivity with atmosphere , moisture , and processing chemicals ( e . g ., al , mo , re , w , zr , au , etc .). again , these over - layers or under - layers are deposited in - situ with the layer they serve to protect and are typically patterned together therewith . superconducting qubits typically comprise superconducting loops interrupted by one or more josephson junctions . from an electrical point of view they represent nonlinear thin - film microwave lc resonators in which the resonating inductance and capacitance include , respectively , the nonlinear inductances of josephson junctions and junction capacitance . the typical resonant frequency in the present state - of - the - art is from ˜ 1 ghz to 20 ghz . to operate as qubits , these superconducting circuits must have long coherence times , which are characterized by the energy relaxation time and the dephasing time . the dephasing time characterizes the time interval during which the phase coherence between two quantum states is lost . in general , the relaxation is determined by energy dissipation in the qubit circuit , which for superconducting qubits occurs primarily on the surfaces of superconducting layers forming the circuit , inside the tunnel barrier , in the interlayer dielectrics , and at the interfaces between superconducting and dielectric layers . the surface and the interfaces are the most significant source of energy dissipation due to the possibility of creating nonsuperconducting ( or weakly superconducting ) oxides and contaminated layers due to reaction between the surfaces of superconducting layers with air and processing chemical , or with interlayer dielectrics during the manufacturing of the quantum circuits . the surfaces are also believed to be the main source of phase decoherence due to localized electronic states and magnetic moments ( in the surface oxides and absorbed layers ) which cause charge and flux noise ( fluctuations ) affecting the qubit performance . single superconducting layers are used in the prior art for wiring and interconnects . according to one aspect of the technology , one or more , and preferably all , superconducting layers are replaced by a multilayer so the various surfaces of the superconducting layers are protected during the fabrication . the extra surface layers should be made of thin superconducting or induced superconducting layers which serve to protect the superconducting layers from the adverse effects of contaminants or to serve as etch stop layers . the process is shown in fig8 a - 8j is similar to the process described in fig7 a - 7h , except that all free layer surfaces are protected by a layer of a metal such as al , or mo , or re . in the process of fig8 a to 8j , the josephson junction trilayer m1 / be - b - m1 / ce is deposited as a penta - layer , with an additional protective layer on the top and bottom , which is preferably superconductive or induced - superconductive at integrated circuit operating temperatures . the wiring layers are deposited , not as a single layer , but as a trilayer , with the protective layer on the top and the bottom . this sequence is compatible with either a planarized ( fig8 a - 8g ) or non - planarized process ( fig8 a - 8e and fig8 h - 8j ). fig8 a shows in - situ deposition of a penta - layer pl1 - m1 / be - b - m1 / ce - pl2 m / nb / al / alox / nb / m , where m = al , mo , re , etc . fig8 b shows photolithography for patterning the base electrode m1 / be , formed of niobium . fig8 c shows etching of the top portion of the pentalayer , starting with the top protective layer pl2 ; etching of the nb counter electrode m1 / ce ; and etching of al / alox barrier b ( or al / alox / al barrier ) to leave a portion of the barrier b , such as the bottom non - oxidized aluminum metal portion only . fig8 d shows photolithography for patterning the m1 / ce , defining josephson junctions . fig8 e shows etching of the top layer of the pentalayer , in which the niobium m1 / ce and m1 / be are etched simultaneously . fig8 f shows a thick blanket interlayer dielectric i1b deposition . fig8 g shows planarization of the thick blanket interlayer dielectric i1b , which stops at the protective layer pl2 , using cmp . fig8 h shows an alternate to fig8 g , with a thin interlayer dielectric i1b ′ deposition for a non - planarized process . fig8 i shows photolithography and contact hole etching proceeding from the structures shown in fig8 h . fig8 j shows deposition of a wiring trilayer pl4 - m2 - pl3 on the structures shown in fig8 i . therefore , each niobium layer is bounded on top and bottom by a thin conductive metal layer which achieves superconductivity at 4 . 2k based on its proximity to the niobium metal layer , which may , for example , serve as a diffusion barrier , etch stop layer , as well as other purposes . the minimum thickness of protective layers was determined by observing the reduction in pattern - dependent effects in j c of jjs with various connections to circuit layers . for al it was found to be ˜ 3 nm and ˜ 5 nm for mo . the maximum thickness is determined by the desired level of the critical current of nb / pl / nb contacts . we set this level at ˜ 30 ma for circular contacts of 2 - μm diameter . this gave ˜ 10 nm upper limited for al protective later thickness and less for mo . from these considerations , a preferred thickness is ≈ 5 nm for both materials . the best results were obtained with aluminum protective layers which eliminated effects of be connection to m0 layer studied in [ 1 ]-[ 3 ] and effects of ce to ti / au contact pad connections studied in [ 4 ]-[ 6 ],[ 15 ]. with molybdenum protective layers , a substantial reduction in the value of the second effect was noted , but it was not completely eliminated , apparently due to a higher diffusivity and solubility of h in molybdenum than in aluminum . each protective layer was patterned along with the nb layer underneath it , using the same photoresist mask ( otherwise it would short the circuit ). aluminum protective layers were either etched in tetramethylammonium hydroxide solution in deionized water or dry etched in cl 2 / bcl 3 mixture , or ar ion milled . no difference was found in the results . molybdenum protective layers were dry etched in sf 6 plasma in - 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