Patent Application: US-66870996-A

Abstract:
a test board circuit for testing integrated circuit modules under stress conditions , such as temperature , humidity , and bias . the integrated circuit module under test is plugged into a test socket which is part of the test board circuit . without protection electrical shorting between test socket contacts , either from improper plugging of the module under test or from the formation of conductive deposits on the socket contacts , causes erroneous results and can damage devices in the integrated circuit module under test . the test board circuit protects the devices in the integrated circuit module under test from damage due to shorting between test socket contacts and provides a voltage signal which can be used to detect when a short has occurred .

Description:
refer now to fig5 and 6 , there is shown an embodiment of the test board circuit of this invention . as shown in fig5 the test board has a test socket with a first number , n 1 , of odd numbered connectors , 101 , 103 , 105 , etc ., and a second number , n 2 , of even numbered connectors , 102 , 104 , 106 , etc . fig5 shows only three odd numbered connectors 101 , 103 , and 105 and three even numbered connectors 102 , 104 , and 106 with additional connectors being added in the same pattern . the first number , n 1 , is either equal to the second number , n 2 , or one greater than the second number , n 2 . each of the odd numbered connectors is adjacent to one of the even numbered connectors and each of the even connectors is adjacent to one of the odd numbered connectors . the input / output pins of the integrated circuit module 10 under test are plugged into the test socket connectors , 101 , 102 , 103 , 104 , 105 , 106 , etc ., as shown in fig5 . as shown in fig5 a control node 60 is connected to a control node output terminal 18 . a low value resistor 17 , having a resistance r s of less than about 10 ohms , is connected between each of the odd numbered test socket connectors and the control node 60 , so that there are a total of n 1 low value resistors . a first supply node 62 is connected to the v dd voltage supply 12 and a second supply node 64 is connected to the v ss voltage supply 14 . the first number , n 1 , of high value resistors 15 , having a resistance r h greater than about 4000 ohms , are connected between the first supply node 62 and the control node 60 . the second supply node 64 is connected directly to each of the even numbered test socket contacts . fig6 shows the integrated circuit module under test which is plugged into the test socket . a first number of even numbered pmos and nmos pairs and a second number of even numbered pmos and nmos pairs , two pairs being shown in fig6 have the sources of the pmos transistors , 31 and 33 , connected to the v dd supply voltage 42 and the sources of the nmos transistors , 32 and 34 , connected to the v ss supply voltage 44 . the drains of the pmos transistor and nmos transistor of each pair are connected together . the gates of the pmos transistor and nmos transistor of each odd numbered pmos and nmos pair are connected to one of the odd numbered contacts 101 of the test socket . the gates of the pmos transistor and nmos transistor of each even numbered pmos and nmos pair are connected to one of the even numbered contacts 102 of the test socket . the low value resistors , r s , and high value resistors , r h , are connected as described in the preceding paragraph . under normal operation the voltage at the odd numbered test socket connectors , 101 , 103 , etc ., and the gates of the pmos transistor and nmos transistor of each odd numbered transistor pair is v dd , in this example between about 4 and 6 volts or equal to or greater than v oh min which is specified in the integrated circuit product data sheet . the voltage at the even numbered test socket connectors , 102 , 104 , etc ., and the gates of the pmos transistor and nmos transistor of each even numbered transistor pair is v ss , in this example 0 volts . under normal conditions the voltage at the control node 60 is v dd . the problem is encountered when an electrical short , shown by a dashed conductor 58 in fig5 and 6 , develops between adjacent test socket connectors such as the first odd numbered connector 101 and the first even numbered connector 102 . under the conditions of the short the voltage at both shorted contacts , 101 and 102 , becomes v ss and the voltage at the control node 60 becomes in this example where v dd is 5 volts , v ss is 0 volts , r h is 5000 ohms , r s is 5 ohms , and n 1 is 100 the voltage at the control node 60 drops to 0 . 45 volts . the voltage at the control node 60 will drop to 0 . 45 volts or less if r h /( n 1 × r s ) is equal to or greater than 10 . r h , r s , and n 1 , are chosen so that r h /( n 1 × r s ) is equal to or greater than 10 . under the condition of the electrical short between two adjacent test socket contacts the voltage at the gates of the pmos and nmos transistors in the integrated circuit module under test will be v ss and nmos transistors will be turned off . the control node 60 is connected to a control output terminal 18 . a control circuit connected to the control output terminal 18 senses the voltage drop at the control node and provides a signal that a malfunction has occurred . another embodiment of the test board circuit of this invention is shown in fig7 and 8 . in this embodiment the pmos and nmos pairs in the integrated circuit module under test are connected as described in the preceding embodiment , see fig8 . as shown in fig7 in this embodiment the odd numbered test socket contacts 101 , 103 , 105 , etc . are connected to the first supply node 62 which is connected to the v dd voltage supply 12 , in this example between about 4 and 6 volts or equal to or greater than v oh min . a control node 60 is connected to a control node output terminal 18 . a low value resistor 17 , having a resistance r s of less than 10 ohms , is connected between each of the even numbered test socket connectors , 102 , 104 , 106 , etc . and the control node 60 , so that there are a total of n 2 low value resistors . a second supply node 64 is connected to the v ss voltage supply 14 , in this example 0 volts . the second number n 2 , in this example less than 120 , of high value resistors 15 , having a resistance r h of greater than about 4000 ohms , are connected between the second supply node 64 and the control node 60 . the first supply node 62 is connected directly to each of the even numbered test socket contacts . the second number n 2 is equal to the first number n 1 or one less than the first number n 1 . under normal operation the voltage at the odd numbered test socket connectors , 101 , 103 , etc ., and the gates of the pmos transistor and nmos transistor of each odd numbered transistor pair is v dd , in this example between about 4 and 6 volts or equal to or greater than v oh min , and the voltage at the even numbered test socket connectors , 102 , 104 , etc ., and the gates of the pmos transistor and nmos transistor of each even numbered transistor pair is v ss , in this example 0 volts . under normal conditions the voltage at the control node 60 is v ss . the problem is encountered when an electrical short , shown by a dashed conductor 58 in fig7 and 8 , develops between adjacent test socket connectors such as the first odd numbered connector 101 and the first even numbered connector 102 . under the conditions of the short the voltage at both shorted contacts , 101 and 102 , becomes v dd and the voltage at the control node 60 becomes in this example where v dd is 5 volts , v ss is 0 volts , r h is 5000 ohms , r s is 5 ohms , and n 2 is 100 the voltage at the control node 60 increases to 4 . 5 volts . the voltage at the control node 60 will increase to 4 . 5 volts or greater if r h /( n 2 × r s ) is equal to or greater than 10 . r h , r s , and n 2 , are chosen so that r h /( n 2 × r s ) is equal to or greater than 10 . under the condition of the electrical short between two adjacent test socket contacts the voltage at the gates of the pmos and nmos transistors in the integrated circuit module under test will be v dd and the pmos transistors will be turned off . the control node 60 is connected to a control output terminal 18 . a control circuit connected to the control output terminal 18 senses the voltage increase at the control node and provides a signal that a malfunction has occurred . while the invention has been particularly shown and described with reference to the preferred embodiments thereof , it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention 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