Patent Application: US-24763808-A

Abstract:
the architectures derived from the proposed template are integrated in a generic system on chip and consist of reconfigurable coprocessors for executing nested program loops whose bodies are expressions of operations performed in a functional unit array in parallel . the data arrays are accessed from one or more system inputs and from an embedded memory array in parallel . the processed data arrays are sent back to the memory array or to system outputs . the architectures enable the acceleration of nested loops compared to execution on a standard processor , where only one operation or datum access can be performed at a time . the invention can be used in a number of applications especially those which involve digital signal processing , such as multimedia and communications . the architectures are used preferably in conjunction with von neumann processors which are better at implementing control flow . the architectures can be scaled easily in the number of data stream inputs , outputs , embedded memories , functional units and configuration registers . a computational system may entail several general purpose processors and several coprocessors derived from this architectural template . the coprocessors are connected either synchronously or using asynchronous first in first out memories , forming a globally asynchronous locally synchronous system . each coprocessor can be programmed by tagging and rewriting the nested loops in the original program . the programming tool produces a coprocessor configuration per each nested loop group , which is replaced in the original code with coprocessor input / output operations and control .

Description:
the coprocessors derived from the proposed architecture template are capable of manipulating n - bit data words . we distinguish between constants : single data words read from a configuration register file variables : single data words read from functional unit outputs arrays : collection of data words read from memories the architectures are capable of executing one or more consecutive nested loop groups according to the following meta - language definitions : // ‘\’ is an escape character removing the meta meaning of the top - level view of the proposed architecture template is shown in fig2 . it basically consists of an array of functional units ( fus ) and an array of embedded memories ( ems ). the data processed by the fus are sourced from the ems , system inputs or outputs of other fus by the read crossbar . each fu produces a single data output , but it may also produce some flags as a secondary output . these flags are routed by the read crossbar to other fus where they are used as control inputs . the data processed by the fus is written back to the ems or sent out to system outputs using routes defined by the write crossbar . the addresses of the memories come from the address generator . since the memory bandwidth is crucial for the performance of this system , in fig2 all embedded memories are shown as dual port memories . single port memories could also be used . a configuration register file holds a set of registers containing data that define the configuration of programmable fus , read and write crossbars , and address generation blocks . it also stores some constants used in the computation of addresses and data . the configuration register file is accessed through a configuration interface which is also used for accessing control and status registers . the configuration register file is addressable , so the system can be partially and runtime reconfigurable . the address generation block can be seen in fig3 . its architecture resembles the top level view of the architecture itself , that is , it is like a smaller reconfigurable processor inside the reconfigurable processor . instead of the fu array there is an accumulator array ( aa ), and the read and write crossbars appear as the input crossbar and output crossbar , respectively . the aa contains a collection of special accumulators which are enabled by signals coming from the timing unit . some accumulators produce addresses which are routed to the memory ports by the output crossbar . the output crossbar also routes addresses stored in certain memories to be used as addresses of other memories . this provides for extreme flexibility in the generation of addresses at the expense of memory space . other accumulators produce intermediate values which are fed back into the aa itself . the input crossbar provides for the feeding back of the intermediate values and routes constants from configuration register to the accumulators , in order to generate complex address sequences . the addresses are functions of the nested loop indices . the timing unit generates groups of signals for enabling the aa . the enable signals are routed to the aa by the enable crossbar . the enable cross bar also routes enable signals to the system inputs to time and synchronize the admission of external data . the enables of the accumulators accompany the generated address to its memory port ; in case of a read port the enable signals accompany the data read from the memory through the fus . in the fus the enable signals are delayed by the same amount as the data so that enables and data remain synchronous . the control block shown in fig3 is responsible for responding to user commands to initialize , start and poll the coprocessor . it also stalls the coprocessor in case some condition is detected in the functional units , or in case the system inputs are data starving or the outputs are overflowed . the loop indices advance by unit increments as given above in the nested loop syntax . each nested loop group uses a group of indices implemented in the timing unit using cascaded counters where the end count value is programmed . the timing unit is shown in fig4 . the programmable counters are interconnected in a matrix where the first row implements enable signals for the loop indices i , j and k . the subsequent rows produce delayed versions of the loop indices . the last row always contains the most delayed version of the loop indices . the first counter represents index i and is incremented at every clock cycle . when a counter reaches the end value it wraps around and pulses the output signal to advance the next outer counter by one . when the final counter reaches the end the outmost loop finishes and the nested loop group is done . a priority encoder identifies the outmost loop ( end_sel ) from the non null end count values programmed in the cascaded counters . this information will indicate which counter column terminates the processing and will be used in the control block . the circuit to delay the basic index i enable by programmable values is shown in fig5 . each flip - flop d delays the i_en ( t ) signal by one cycle . programmable multiplexers select the delay wanted . if there is a break condition ( see below ) the state of the delay unit is frozen by disabling the flip - flops and masking the output enables . if there are p memory ports in the system at most p different delayed versions of the enables are needed . in practice a lower number of delayed versions may be implemented . since real addresses do not advance necessarily by increments of one , the accumulator units shown in fig6 and fig7 are responsible for generating more complex address sequences of the form given by address_expression as above . the basic accumulator unit ( bau ) shown in fig6 initializes to the value specified by the start input after the restart_en signal is pulsed , and accumulates the values specified by the incr input . the accumulator current and next outputs are given by signals cnt and cnt_nxt , respectively . the complex accumulator unit shown in fig7 adds the following functionality to the bau : the accumulations are done in modulo specified by the configuration input modulo , and added to the value specified by the offset input signal . each accumulator selects its en and restart_en signals from the enable crossbar , which is driven by the enable signal groups produced in the timing unit . as shown in fig8 , first the enable group ( delayed version ) is selected and then the enable signals for en and restart_en are selected from within the selected group . a similar scheme is used to select the enable signals used to acknowledge the admission of external data in the system . in this way the input of external data can be timed and synchronized . fig9 illustrates the selection of the accumulator inputs from the input crossbar . the start , offset and incr signals can be chosen either from constants stored in the configuration registers or from the cnt and cnt_nxt signals produced by other accumulators . fig1 illustrates the selection of memory port addresses in the output crossbar . the cnt signals produced by the accumulators or data read from memories can be chosen to form the addresses of memory ports . the en and restart_en signals of the accumulators follow the produced addresses to the memory ports . if the memory port is a read port the enables accompany the data read to the functional units , or , if the data read is to be used as an address , the enables follow the data back to the output crossbar . if the memory port is a write port the en and restart_en signals are ignored . fig1 shows the selection of inputs for functional units by means of the read crossbar . inputs can come from system inputs , memory output ports , or from the outputs of other functional units . this architecture template considers that any functional unit must have a special input responsible for passing the enable signals through to the next functional unit and delaying them the same number of latency cycles as the functional unit itself . in this way the enable signals are preserved and kept near the data they refer to . functional units may be configured to route the input restart_en signal to the output en signal while losing the en signal of the input , which ceases to be relevant from that functional unit on . the usefulness of doing so will be apparent later . fig1 shows the selection of system outputs and memory inputs in the write crossbar . these are selected from functional unit outputs . note that the enables accompany the data and are to be used as memory write enables or output request signals . the control / configuration , data in and data out interfaces are shown in fig1 . the control / configuration interface has a request_in input signal to indicate it is being selected and to validate the address input vector , which is used to select internal registers . the write / not read signal chooses the intended action . the data is written to ctr_data_in ports and read from the ctr_data_out port . the request_out signal flags events such as the end of processing or that some condition has been detected and the coprocessor has been halted . the data in interface has a req_in input signal vector . each element req_in [ i ] indicates that the data in interface i is being selected and validates the data_in [ i ] vector containing the input data . the ack_in [ i ] signal is used to tell the core driving interface i that the request req_in [ i ] to read data_in [ i ] has been accepted and executed . the ack_in [ i ] signal comes from the address generator block , where it is selected by the enable crossbar . the data out interface has a req_out output signal vector . each element req_out [ i ] indicates that the data out interface i is being selected and validates the data_out [ i ] vector containing the output data . upon accepting the data sent out by this interface an acknowledge signal ack_out [ i ] must be asserted from the outside or otherwise the coprocessor will stall to prevent data loss . from an external point of view , ack_out [ i ] should always be asserted unless it was impossible to accept the data from the last request . fig1 shows a basic control register for the architectures . it contains three bits : the init bit to initialize the coprocessor , the en bit to enable the coprocessor and the req_en enable control requests from the co - processor by means of signal request_out . fig1 shows a basic status register . it contains a single busy bit to permit polling of the co - processor . a basic control unit is shown in fig1 . the coprocessor is enabled whenever the control bit en and the i / o enable bit are asserted , and remains enables until either the end ( t ) or the break signals remains unasserted . whenever these signals pulse , a logic ‘ 1 ’ is caught in a flip - flop , which disables the coprocessor . an enabled co - processor has the innermost loop index active by asserting signal i_en ( t ), which in turn enables the outer loop indices and all the delayed versions of the enable groups . if control output requests are enabled ( req_en =‘ 1 ’) then the request_out signal is asserted when either the break signal or the most delayed end ( t - dp ) pulses . the end ( t ) and end ( t - dp ) signals are the wrap around signals of the outmost loop ; a multiplexer uses signal end_sel explained in fig4 to choose the index enable from signals i_en , j_en , or k_en , both the delay free and the delayed by dp cycles versions . the busy signal of the status register is generated as shown in fig1 . the coprocessor is busy if it is either enabled , with i_en ( t ) active , or has not finished the processing , i . e ., end ( t - dp ) or break have not been asserted . the break signal is used to disable the generation of loop index enables in the delay unit ( fig4 ). it is basically a registered inverted and one cycle delayed version of the break signal . the selection of break conditions from functional units is illustrated in fig1 . for scalability reasons each functional i unit can only produce a single break condition signal cond_i . internally , functional unit i may be programmed to fire the break condition for various reasons . however , from an external perspective , there is a single break signal per functional unit . a configuration bit cond_i_en tells whether break condition cond_i is enabled . the selection of i / o dependent system enables is shown in fig1 . if the loop body expressions involve a system input i , then the co - processor can only be enabled if there is data available at that input , which is signaled by the req_in_i signal . similarly , if the results of the loop body expressions are being sent to system output j , then the co - processor can only be enabled if the data sent out is actually being read by another system , which is signaled by the ack_out_j signal . when this signal is asserted it means that the data sent in the last cycle has been read . when asserted , configuration bits no_in_i and no_out_j indicate that system input i and system output j are not present in the loop body expressions , and therefore cannot disable the system . the coprocessor programming flow is illustrated in fig1 . the user starts by writing the nested loop sequence code according to the syntax given above . the coprocessor programming tool inputs the nested loop sequence code and a description of the hardware architecture , and outputs the coprocessor configuration sequences in multiple formats : text file , software include file and configuration memory images in hardware description language ( hdl ). the text file is human readable and is used to give feedback to the user . the software include file contains the configuration memory images of the sequence ; it can be included in some program which will configure and run the coprocessor . the hdl configuration images are used in fpga emulation , for fast system verification , or hdl simulation for detailed system verification . additionally , a software model of the architecture is compiled from the hardware description files , which provides a compromise between the speed of fpga emulation and the detail of hdl simulation . the results ( output data ) produced by the software , hdl and fpga models are analyzed by the user and used to guide the refinement of the input nested loop code . the hardware architecture is described in a file which references the functional units used . the description of the functional units is placed in the functional unit store . the syntax of the hardware description file should be equivalent to the one given below : the first step is there to analyze the expressions in the nested loop bodies and to create a complete system graph sg consisting of sub - graphs for each nested loop group . this is done by function parsenlsc ( nested_loop_sequence_code ). each nested loop group gives rise to a configuration memory image . the sub - graph for each nested loop group has two parts : the data flow graph and the address flow graph . the data flow graph ( dfg ) has the following types of nodes : memory node ( data output ports ) system data input node configuration constant node the address flow graph ( afg ) has the following types of graphs : memory node ( data output ports ) timing unit node ( enable signals output ports ) configuration constant node the edges in the dfg and afg are directed from source nodes to intermediate nodes , from intermediate nodes to other intermediate nodes , and from intermediate nodes to sink nodes . the dfg and the afg can be concatenated in a single configuration graph cg by merging the memory sink nodes of the afg with the memory source nodes of the dfg . the complete system graph sg can be constructed by concatenating successive cgs . one cg is concatenated with the next cg by merging the memory sink nodes of the current cg with the memory source nodes of the next cg . this allows leaving data in the embedded memories that will be used in the next co - processor configuration . this mechanism can be called a conscious or intentional caching mechanism , which should perform better than conventional caches which exploit stochastic locality . the following example shows a nested loop group for which a cg is derived . w = (( α 1 * i + β 1 )* j + β 2 )% γ )+ δ the dfg for the nested loop group in this example is shown in fig2 . as can be seen , the dfg follows the expression in the body of the nested loop group . each node of the graph represents either an fu node or a memory node . read , write or fu operations are pipelined and the latency for each operation is indicated in fig2 . the longest path in the graph , from memory reads a [ v ] or b [ w ] to memory write d [ u ] takes 9 cycles . the path from memory read c [ x ] to memory write d [ u ] takes 4 cycles . this means that memory read c [ x ] should be delayed 9 − 4 = 5 cycles relative to memory reads a [ v ] and b [ w ] and that memory write d [ u ] should be delayed 9 − 1 = 8 cycles relative to memory reads a [ v ] and b [ w ]. with the presented architecture template there are no delays in computing the addresses . thus differences in latency come only from fus with different number of pipeline stages . however , extending this methodology to the case where the computation of addresses is affected by latency is straightforward . the afg for computing the addresses u , v , w and x is shown in fig2 . the computation of addresses advances with the enable signals i_en and j_en generated by the timing unit . the addresses that need to be delayed d cycles use a delayed enable group with signals i_en ( t - d ) and j_en ( t - d ). note that address u , v and x need only one bau to be computed , whereas address w is more complex and needs a cau fed by a bau . concatenating the dfg and the afg by merging homonym memory nodes u ( t - 8 ), v ( t ), w ( t ), and x ( t - 5 ) yields the cg for the nested loop group in this examples . had there been a sequence of nested loop groups , the respective cgs would be concatenated in a similar way to yield the complete sg . having created sg , the nodes in this graph are ordered in a list , in a breadth first fashion , from the system output nodes towards the system input nodes . for the example given the order of nodes could be : d [ u ], +−, +, c [ x ], *, x ( t - 5 ), a [ v ], b [ w ], v ( t ) and w ( t ). this is what the function createnodelist ( sg ) in the main algorithm flow does . next , function parsehw ( architecture_description ) creates a graph that describes the hardware by means of function . the hardware graph follows the architectural description given above . some hardware nodes map to sg nodes : i / o , memory , functional unit , address accumulators , configuration constants , timing unit nodes ; other hardware nodes have no correspondence to nodes in sg , but are useful for routing signals : memory port , crossbar multiplexer , functional unit port . the selections of paths all the way up from system outputs and memory inputs up to system inputs and memory outputs , passing through several levels of functional units , constitute the data for each configuration . unfolding the hardware graph as many times as the number of configurations gives us the complete hardware graph hg , onto which sg is mapped . the next step is to map the nodes in sg to nodes in hg . the recursive map procedure is outlined below . following the pseudo - code above , the first thing to do when mapping an sg node to a hg node is to get the immediate descendant nodes of that node in the graph . these nodes have already been mapped to a hg node , since the algorithm proceeds from graph sinks to graph sources . working from the descendant hg nodes , one computes the list of common immediate ascendant hg nodes which have correspondence in sg and are reachable by unused multiplexers . this is a list of possible hg nodes that can be mapped to the node in question . the nodes in this list are searched to find suitable candidates . first , the candidate hg node must be of the same type as the node : adder , multiplier , memory , etc . second , the node must not be in use . if either of these tests fail the procedure returns unsuccessfully . having performed these checks , the hg node is routed to its descendants , that is , the input multiplexers of the descendants are set to receive data from the node . if this is the last node to be mapped the procedure returns success . otherwise , the map procedure is recursively applied to the next node in sg . if successful , the procedure returns success . otherwise it means that the mapping of the next nodes can not be accomplished with the current mapping of the current or previous nodes . in this case the routes to the descendants are undone and the next candidate hg node is tried . after all candidate nodes are tried unsuccessfully the procedure returns unsuccessfully . an example of application of a reconfigurable coprocessor instance created with the present invention is presented next . the example is a mpeg 1 layer iii ( mp3 ) decoder algorithm . the algorithm has been run on ( 1 ) a conventional processor and on ( 2 ) the same conventional processor accelerated by a coprocessor instance . the processor is a 32 - bit harvard architecture with 0 , 81 dmips of performance . the coprocessor instance has been generated with the following parameterization : 2 nested loops , 32 - bit data path , 2 adders / accumulators , 2 multipliers / shifters , 3 dual port memory blocks totalling 4 kbytes of rom and 8 kbytes of ram . the experimental results from running a set of mp3 benchmarks are shown in table 1 . from the initial profiling of the algorithm on the conventional processor we find that two procedures are taking 95 % of the time : the polyphase synthesis and the inverse modified discrete cosine transform ( imdct ). thus , if we accelerate these procedures in the coprocessor the potential for acceleration is 20 . the polyphase synthesis procedure has been accelerated 18 . 7 times on average . the imdct procedure has been accelerated 43 . 9 times on average . this resulted in an overall algorithm acceleration of 11 . 9 times . the profiling of the complete system formed by the processor and coprocessor reveals a more balanced processing load distribution among the main procedures . in the complete system the polyphase synthesis and imdct procedures account for only 34 % of the processing load , in stark contrast to the 95 % processing load before acceleration . in this example the silicon area doubled as the result of adding the coprocessor instance . since the performance has been multiplied by twelve , this means that the processor - coprocessor system dissipates roughly 6 times less power , while still keeping the same level of performance . it must be clear that the present reconfigurable coprocessor architecture template merely states the principles of the invention . variations and modifications to the cited architecture can be made without moving away from the scope and principles of the invention . all these modifications and variations must be enclosed in the scope of the present invention and protected by the following claims . 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