Patent Application: US-85269304-A

Abstract:
embodiments disclosed herein include electronic device designs based upon electronic properties of group iii - n materials and quantum - mechanical effects of specialized heterostructures . such electronic device designs may include , for example , heterojunction field - effect transistors and high - electron - mobility transistors . the design concepts permit high power , high - frequency , and high - temperature operation of advanced electronic circuits , including devices for radar , collision - avoidance systems , and wireless communications . designs disclosed may include one or more aln layers and / or one or more smash superlattice barriers combined with one or more n - type delta - doped regions . alternately , in certain embodiments , one or more aln layers and one or more smash superlattice barriers may be combined without the n - type delta - doped regions .

Description:
in an embodiment , algan / gan heterojunction field - effect transistors ( hfets ) may be used in high - power , high - frequency , and high - temperature electronics , because of the fundamental characteristics of group iii - nitride materials . improved high - power hfet performance has been recently achieved and a power density of 10 . 7 w / mm at 10 ghz has been demonstrated . for high - power device applications , a high drain - source current , i ds , along with a high transconductance and a large source - drain breakdown voltage may be desirable . in an embodiment , a large source - drain current , i ds , may be achieved if the sheet charge density , n s , the carrier mobility , μ n , and the saturation drift velocity , v s , in the channel have relatively large values . currently , a large source - drain current may be achieved by using undoped or modulation - doped algan / gan structures . another method of achieving a large source - drain current may include increasing the aluminum mole fraction ( and therefore , the bandgap ) in an algan barrier . although , increasing the al mole fraction in the algan cap layer may lead to higher n s , it may also lead to a decrease in μ n . as a result , n s μ n product improvement may be limited . large source - drain current devices may be referred to as “ high - electron mobility transistors ” or hemts . recently , the use of a binary barrier of aln was reported to increase the low - field electron mobility , μ n , and n s in the channel , yielding an n s μ n product of 2 . 28 × 10 16 v - s . however , the fet device performance ( e . g ., i dsmax and g m ) did not appear to be improved compared to the performance achieved by a “ standard ” modulation - doped hfet . embodiments disclosed herein include delta - doped heterostructure fet designs . such designs may include the use of one or more aln barriers . additionally , one or more superlattice barriers may be included in delta - doped heterostructure fet designs disclosed herein . one or more aln and / or one or more superlattice barriers may be combined with one or more n - type delta - doped regions . alternately , in certain embodiments , one or more aln and one or more superlattice barriers may be combined without the n - type delta - doped regions . in embodiments that include n - type delta - doped regions , the n - type delta - doped regions may improve the current carrying capabilities of the hfet . in certain embodiments , n - type delta - doped regions have the additional benefits of reduced gate leakage , low noise , high g m , and capability of sustaining a large voltage across the drain source region ( large v ds ) prior to breakdown of the device . the structures described above may demonstrate relatively high n s μ n product , relatively large drain currents , relatively high values of extrinsic transconductance , relatively low noise figures at 17 ghz , and / or transconductance values close to the state - of - the - art . an superlattice heterostructure includes a series of alternating layers of smaller - bandgap “ quantum well layer ” and larger - bandgap “ barrier layers .” quantum mechanics predicts that an electron has a non - zero reflection probability from a barrier lower than the energy of the electron . with appropriate design of the barriers and wells , the reflected wave may be made to interfere destructively with the incident electron wave . a propagation matrix is calculated for each interface that calculates the ratio of incident wave , reflected wave and transmitted wave . for a multi - period heterostructure , these propagation matrices are multiplied together yielding the effective propagation matrix for the superlattice . such an superlattice structure effectively increases the heterojunction barrier while reducing the lattice mismatch and alloy scattering . in one embodiment , the super lattice structure may be improved by growing a specially designed superlattice heterobarrier that has a non - periodic structure . an example of one such barrier with a special increased electron reflectivity design we have developed is called a “ strain - modulated aperiodic superlattice heterobarrier ” ( smash ™) and will be described in further detail below . embodiments disclosed herein include methods to improve performance of group iii - n hfet devices in terms of power , frequency response , noise and stability . specifically , a number of hfet device structures are disclosed . for example , a first hfet device structure including delta - doped algan / aln / gan hfets using an ultra - thin aln binary superlattice barrier layer is depicted in fig2 a . other examples of hfet device structures include delta - doped and undoped strain - modulated aperiodic superlattice heterobarrier ( smash ) electron donor and confinement structures . in an embodiment , a specially designed smash barrier may be used in an hfet device to improve carrier confinement and to reduce the leakage current for high - power devices . such smash barriers may include quantum - mechanically designed barriers , which reflect electrons back into the channel . such smash barriers may further provide a high carrier density from the combined effects of the piezoelectric and polarization charges and the carriers provided by delta doping . as used herein a smash barrier generally refers to a barrier in which successive well layers generally have an increasing band gap in the conduction band energy diagram . in a strain - modulated aperiodic superlattice heterobarrier , successive well layers have an increasing band gap in the conduction band energy diagram for the smash as shown in fig1 a for the inalp / ingap / gaas system . a schematic drawing of the conduction band energy of a conventional multiple quantum barrier structure is shown in fig1 b . for the inalp / ingap / gaas system , this corresponds to an increasing amount of strain in the consecutive wells of the superlattice . if a single quantum well is sandwich between a pair of smashs , the tendency of the electrons to thermalize into the well will be enhanced significantly because of the decreasing potential of the superlattice well layers towards the single quantum well . once confined in the quantum well , the thermionic emission of the electrons will be greatly reduced due to the increased electron reflectivity of the smash . therefore , the smash enhances the collection and confinement of the carriers . these arguments are confirmed both by theoretical calculations and by experimental observations . a schematic diagram of an hfet device including a smash barrier is depicted in fig2 a , and generally referenced by numeral 100 . hfet device 100 includes superlattice charge layers and at least one aln barrier . as used herein a superlattice structure refers to a stack of repeating alternate layers . the hfet device is formed on a substrate . suitable substrates for the formation of an hfet include , but are not limited to c - plane ( 0001 ) al 2 o 3 ( sapphire ), 4h — sic , 6h — sic , thick aln / sapphire , bulk gan , aln substrates , etc . while ( 0001 ) sapphire may be used for gan growth because of its availability and relatively low cost , the lattice and thermal expansion coefficients are quite different from those of the group iii - n materials . it is believed that sic has better thermal and lattice match to the group iii - n compounds , particularly to aln , yet the crystalline quality of 6h — and 4h — sic substrates is still not as high as sapphire . furthermore , the surface roughness and subsurface damage for “ typical ” commercial sic substrates are believed to be inferior to that of sapphire . while the cost of 2 . 0 in . diameter semi - insulating 4h — sic substrates on the “ open market ” may be about forty times that of a 2 . 0 in . diameter sapphire substrate , the performance advantages of electronic devices fabricated from heteroepitaxial gan / sic films are documented . in forming a device as disclosed herein , the quality of group iii - n epitaxial layers may be directly related to the quality and lattice constant of the substrate on which the group iii - n material is grown . for the growth of group iii - n epitaxial layers on sapphire or sic substrates for high - power devices , low - pressure metalorganic chemical vapor deposition ( mocvd ) or molecular - beam epitaxy ( mbe ) may be employed . for example , in an embodiment , gan epitaxial layers may be grown in an emcore d125 reactor at pressures of ˜ 200 torr . in another embodiment , a thomas swan close coupled showerhead ( ccs ) mocvd reactor system with a seven wafer capacity may be used . other reactor systems may also be suitably used to grow such structures . algan layers may be grown in the same mocvd reactor at ˜ 50 torr in order to avoid adduct formation as much as possible . device structures may be grown in a h 2 ambient using adduct - purified trimethylgallium ( tmga ) and trimethylaluminum ( tmal ) as metal alkyl sources , and nh 3 as the nitrogen source . silane ( sih 4 ) and bis ( cyclopentadienyl )- magnesium ( cp 2 mg ) may be employed as n - type and p - type dopants , respectively . other metalorganic , hydride and dopant sources may also be used , as are known in the art . a two - temperature growth process may be employed with a low - temperature thin aln buffer layer ( bl ) for sic substrates , and with high - temperature ( ht ) layers grown for the device active region . the mocvd growth of gan on sic may begin with a ˜ 100 nm high temperature ( tg ˜ 1050 ° c .) aln buffer layer , although various “ graded algan ” conducting buffer layers have been developed for the growth of optoelectronic devices on sic . in embodiments disclosed herein , it may be desirable to grow these layers without creating cracks in the epitaxial structure ( e . g ., by the use of various types of stress - relieving buffer layer structures ). in fig2 a , an undoped gan layer is formed on a substrate of sic . undoped gan layer may be formed from trimethyl gallium and ammonia in a mocvd reactor at about 1050 ° c . a superlattice structure may be formed on top of the undoped gan layer . in one embodiment , a smash superlattice structure is formed that includes alternating layers of undoped aln and n - type doped algan layers , as depicted in fig2 a . in fig2 a , superlattice includes 8 layers of alternating aln and algan layers . aln layers are undoped and are formed by an epitaxial growth process . the algan layer is then formed on top of the aln process , with doping of the algan layer occurring by introducing sih 4 during into the reactor during the growth process . the layers are designed to create a superlattice heterobarrier that has a non - periodic structure . fig2 b depicts a schematic representation of the conduction band structure of hfet device 100 . delta - doped binary - barrier ( d 2 b 2 ) hfet structures , and smash - fets , may have several significant features . in an embodiment , a basic d 2 b 2 hfet structure incorporates a binary aln barrier and a delta - doped charge layer in the algan near this aln barrier . such a structure may allow electrons to tunnel through this barrier and to enhance the free charge in the channel . such structures may also reduce alloy scattering at the aln — gan interface as compared to an algan — gan interface . algan / gan hfets having a gate length of 0 . 2 - 0 . 5 μm have been fabricated . using the d 2 b 2 structure , improved n s × mobility product has been measured for electrons in the channel of an algan / gan hemt . for example , in one experiment using a d 2 b 2 algan / gan hfet structure , including a binary aln barrier and an algan delta - doped charge layer , a two - dimensional electron gas having a carrier mobility of μ n = 1 , 058 cm2 / v − s and a sheet carrier density of n s = 2 . 35 × 10 13 cm − 2 at room temperature were obtained , resulting in a n s μ n product of 2 . 49 × 10 16 / v − s . in experiments , algan / aln / gan hfet devices with 0 . 15 μm gate lengths exhibited maximum current densities as high as i dsmax = 1 . 8 a / mm at v g =+ 1 v . fig3 depicts a plot of i ds vs . v ds for an l g = 0 . 15 μm d 2 b 2 algan / aln / gan hfet . fig4 depicts a plot of transconductance vs . gate voltage for an l g = 0 . 15 μm d 2 b 2 algan / aln / gan hfet . fig4 shows that such devices may exhibited peak transconductance of up to g m = 350 ms / mm . fig5 shows a plot of i ds vs . v ds for an l g = 0 . 25 μm d 2 b 2 algan / aln / gan hfet . fig5 shows that algan / aln / gan hfet devices with 0 . 25 μm gate lengths exhibited g m = 240 ms / mm . fig6 depicts frequency response data for an l g = 0 . 25 μm d 2 b 2 algan / aln / gan hfet showing a current gain ( h 21 ) and unilateral figure of merit ( u ) and indicating f t = 50 ghz and f max = 130 ghz . l g = 0 . 25 μm devices have demonstrated a record low - noise power for this gate length , as demonstrated in fig7 . fig7 depicts the minimum noise figure and associated gain vs . frequency for v ds = 10 v and 15v . the noise characteristics of these devices have been measured to be about 1 . 6 db at 10 ghz , an exceptionally low value . noise characterization was performed for the frequency range of 2 - 18 ghz to determine γ opt , the noise resistance ( r n ), the minimum noise figure ( f min ), and the associated gain ( g a ). for l g = 0 . 25 μm d 2 b 2 hfets , a state - of - the - art minimum noise figure of f min = 0 . 93 db with 7 db of associated gain was obtained at 17 ghz and at 10 ghz , the noise figure of the d 2 b 2 hfet was 1 . 1 db with 10 db associated gain . these results indicate that the d 2 b 2 structure may be compatible with high current densities , as well as with high - frequency and low - noise performance desired for x - band bmd - class receivers . d 2 b 2 devices having gate lengths of between about l g = 0 . 15 μm and about 0 . 5 μm have been formed . the devices may approximate short - gate lengths ( e . g ., for high - frequency applications ) and longer - gate lengths ( e . g ., for high power devices ). the formed devices have been used to evaluate the performance of the materials used to form the devices . in experiments , algan / aln / gan hfet . fig8 depicts a plot of i ds vs . v ds for an l g = 0 . 5 μm d 2 b 2 algan / aln / gan hfet . as shown in fig8 , devices with 0 . 5 μm gate lengths exhibited maximum current densities as high as i dsmax = 1 . 5 a / mm at v ds = 9 v . fig9 depicts a plot of i ds and g m vs . v g for an l g = 0 . 5 μm d 2 b 2 algan / aln / gan hfet . as shown in fig9 , the i ds - v g curves are nearly linear , corresponding to a large , relatively flat g m vs . v g curve . the peak i dsmax = 1 . 4 a / mm and g m exceeds 230 ms / mm . it is believed that these values are record numbers for the performance of algan / gan hfets with l g approximately 0 . 5 μm ( e . g ., in the range of about 0 . 3 to 0 . 7 μm ). fig1 shows the frequency response data for an l g = 0 . 5 μm d 2 b 2 algan / aln / gan hfet indicating f t = 20 ghz and f max = about 75 ghz . fig1 depicts a plot of i ds vs . v ds for an l g = 0 . 15 μm d 2 b 2 algan / aln / gan hfet after metalization . as shown in fig1 , devices with 0 . 15 μm gate lengths exhibited maximum current densities as high as i dsmax & gt ; 1 . 8 a / mm at v ds = 9 v . fig1 and 13 , the l g = 0 . 15 μm devices exhibit even higher values of i dsmax greater than 1 . 8 a / mm and g m values as high as 330 ms / mm . it is believed that these values are record numbers for the performance of algan / gan hfets with l g approximately 0 . 15 μm . fig1 depicts a plot of i ds and g m vs . v g for an l g = 0 . 15 μm d 2 b 2 algan / aln / gan hfet after metalization . as shown in fig1 , the i ds - v g curves at v ds are nearly linear , corresponding to a large , relatively flat g m vs . v g curve . the peak i dsmax & gt ; 1 . 8 a / mm and g m exceeds 330 ms / mm . some known designs for high - power group iii - n gallium - nitride - based fets employ a single algan barrier layer to confine the electrons to the channel . this channel carries the current when the device is “ on .” at high currents , high - energy charge carriers may be injected into this barrier reducing the current in the channel , lowering the effective mobility , and / or reducing the effect of the gate voltage on the current flow . in certain embodiments disclosed herein , the effective energy barrier may be increased by a significant amount due to quantum - mechanical reflection of carriers . such reflections may enhance the performance of the device by maintaining the charge in the channel even for the high - current situations . reflection may also improve the high - frequency performance . certain embodiments may include both a superlattice and delta doping , which may provide more free charge carriers ( electrons ) to the channel than a conventional doped or undoped algan charge layer . an additional embodiment of an hfet design is represented schematically in fig1 . fig1 depicts an embodiment of an hfet that includes an aln barrier and delta - doped charge layer . while fig1 depicts a sic substrate , it should be understood that the hfet depicted in fig1 may be formed on any other type of substrate as described previously . the process of forming an hfet as depicted in fig1 includes forming a buffer layer of aln on the substrate . as shown the buffer layer may be about 100 nm in thickness . next a si doped gan layer is formed , the gan layer may be doped with sih 4 during epitaxial growth of the layer . a binary aln and delta - doped algan layer is then formed on top of the doped gan layer . in one embodiment , the aln barrier is a thin (& lt ; about 5 nm ) layer . the doped algan layer is formed on top of the barrier layer . in one embodiment , the doped algan layer has a composition of al x ga 1 - x n where x is about 0 . 2 to about 0 . 3 . the algan layer may be about 20 to 30 nm thick . an additional embodiment of an hfet design is represented schematically in fig1 . fig1 depicts an embodiment of an hfet that includes an aln / gan superlattice charge and buffer layer . while fig1 depicts a sic substrate , it should be understood that the hfet depicted in fig1 may be formed on any other type of substrate as described previously . the process of forming an hfet as depicted in fig1 includes forming a buffer layer of aln on the substrate . as shown the buffer layer may be about 100 nm in thickness . an aln / gan superlattice buffer layer is formed . the superlattice buffer layer includes alternate layers of undoped aln and gan . each of the layers may be about 2 nm or less in thickness . next a si doped gan layer is formed , the gan layer may be doped with sih 4 during epitaxial growth of the layer . an aln / gan superlattice charge layer is formed on top of the doped gan layer . the superlattice buffer layer includes alternate layers of undoped aln and n - type doped gan . each of the layers may be about 2 nm or less in thickness . an additional embodiment of an hfet design is represented schematically in fig1 . fig1 depicts an embodiment of an hfet that includes an aln barrier and delta - doped charge layer . while fig1 depicts a sic substrate , it should be understood that the hfet depicted in fig1 may be formed on any other type of substrate as described previously . the process of forming an hfet as depicted in fig5 includes forming a buffer layer of aln on the substrate . as shown the buffer layer may be about 100 nm in thickness . next a thin gan layer is formed . a thin (& lt ; 5 nm ) aln barrier layer may be formed on the gan layer . a superlattice structure may be formed on top of the undoped gan layer . in one embodiment , a smash superlattice structure is formed that includes alternating layers of undoped aln and n - type doped algan layers . doping of the algan layer occurring by introducing sih 4 during into the reactor during the growth process . the layers are designed to create a superlattice heterobarrier that has a non - periodic structure . the hfet device performance , particularly for high - power operation , depends on many factors , including the source and drain ohmic contact resistance . generally , this contact is placed upon the “ top ” of the algan “ charge layer .” in some embodiments , the algan layer has been selectively removed to provide a more direct contact . for n - type gan : si and algan : si layers , both ti / al / pt / au and ti / ag / au systems may be used to form contacts . in one embodiment , an n - type ti / al / pt / au contact scheme reproducibly shows the lowest tlm specific contact resistance using a 850c / 30s anneal . these n - type ohmic contacts have a specific contact resistance to n - type gan : si ( n − 2 × 10 18 cm ) of rc & lt ; 1 × 10 − 6 q - cm 2 . ohmic contact resistance to undoped algan ( typical of the electron barrier in hfets ) is generally higher . recently , we have identified an new ohmic contact scheme employing vanadium - based contacts for n - type algan films which may improve ohmic contacts to high al - composition al x gal 1 - x n films with specific contact resistances as low as 4 × 10 − 5 ohm - cm 2 for x = about 0 . 60 films . sin x may be used as an amorphous dielectric insulator to improve the leakage characteristics and stability of the gate for algan / gan hfets . this film may be deposited immediately after the growth of the algan charge layer in the mocvd reactor . this “ in - situ ” passivation and gate layer may provide a stable , low - leakage dielectric film to stabilize the surface charges due to the “ free algan ” surface . it is widely known that gan films “ dissociate ” during the “ cool - down ” process when the wafer is exposed to elevated temperatures in an h 2 + nh 3 environment . algan also degrades in the same way , albeit at a somewhat reduced rate . this process may be especially rapid near a screw or edge dislocation . a stable , amorphous sin x film may be grown directly on the algan layer - this will stabilize the algan surface and inhibit the increase in leakage currents and gate breakdown under high - stress operating conditions . the gate metal may be deposited upon this thin sin x layer , creating an insulated gate structure . the in - situ sin x layer may be capped with an additional plasma - enhanced chemical vapor deposition ( pecvd ) sin x film in the regions between the gate and the source and the gate and the drain to improve the stability of the surfaces in these regions as well . the in - situ - deposited sin x film may reduce the leakage contributions from these areas as well . cl - based inductively coupled plasma ( icp ) etching may be used for the device isolation processing . this is a relatively low - damage etching process . alternatively , wet etching with koh solutions is known to improve the leakage current density for p - i - n diodes and may be used for device isolation etching of hfets as well . the stability of the mesa surfaces may play a role in the operation of the device under high - power conditions . the commonly used gate metal for an hfet is ni / au because it is convenient and is compatible with submicron processing . other gate metals may be used including w or wsi . an unpassivated delta - doped , binary barrier ( d 2 b 2 ) hfet device with 0 . 15 μm - gate length was formed . the al x ga 1 - x n / gan ( x ≈ 0 . 2 , 1 . 0 ) heterostructures of this work were grown by low - pressure metalorganic chemical vapor deposition ( mocvd ) in an emcore turbodisc d125 utm high - speed rotating - disk reactor on 2 . 0 in . diameter 4h semi - insulating sic substrates . the gan epitaxial layer is grown at pressures of about 200 torr and the algan epitaxial layers are grown at about 50 torr in a hydrogen ambient using adduct - purified trimethyl gallium ( tmga ), trimethylaluminum ( tmal ), and ammonia ( nh 3 ). silane ( sih 4 ) was used for the n - type dopant . the growth process begins with a high - temperature ( about 1070 ° c .) aln buffer layer , 100 nm in thickness . the subsequent device layers are grown at about 1050 ° c ., beginning with 3 μm of undoped gan . on top of this is a 1 nm aln barrier layer , followed by a 30 nm layer of al x ga 1 - x n ( x is about 0 . 2 ). the delta doping occurs after 5 nm of growth of this last layer , with an expected si dopant concentration & gt ; 1 × 10 19 cm − 3 ( as measured by secondary ion mass spectroscopy ( sims ) analysis on similarly doped structures ). room - temperature hall - effect measurements yield an electron mobility of 1 , 066 cm 2 / v − s and a sheet carrier density of 2 . 30 × 10 13 cm − 2 , resulting in a large n s μ product of 2 . 45 × 10 16 / v − s . this is a large improvement over a similar structure without the barrier layer and delta doping : hall results were 1 , 308 cm 2 / v − s , 1 . 18 × 10 13 cm − 2 , and 1 . 54 × 10 16 v − s , for mobility , sheet charge , and n s μ product , respectively . variable - temperature hall - effect measurements were also performed over the temperature range from 77 k to 290 k . the sheet carrier density remained fairly constant over the measured temperature range , while the mobility steadily increased for lower temperatures , indicating that the 2deg dominated the electrical transport characteristics . d 2 b 2 hfet devices were then fabricated from the epitaxial heterostructures . using chlorine as the active species , a dry etch to a depth of 250 nm was performed for device isolation . a metallization scheme consisting of ti / al / ti / au was deposited by a conventional lift - off process and rapid thermal annealed at 950 ° c . to obtain ohmic contacts . from standard tlm measurements , the contact resistance was calculated to range from 0 . 68 to 0 . 87 ohms - mm . the ni / au schottky - barrier t - gate was defined by electron - beam lithography with a tri - layer resist structure ( 5 . 5 % pmma / 8 . 5 % p ( mma - maa )/ 4 % pmma ). hfet devices with gate lengths of 0 . 5 μm and 0 . 15 μm have been fabricated to investigate power device performance and high - frequency performance , respectively . the standard device has two parallel gate fingers , with a gate width of 75 μm . no passivation has been used for the devices reported here . the following references are hereby incorporated by reference as though fully set forth herein : 1 ) l . shen , s . heikman , b . moran , r . coffie , n . q . zhang , d . buttari , i . p . smorchkova , s . keller , s . p . denbaars and u . k . mishra , ieee electron device lett . 22 , 457 ( 2001 ). 2 ) a . ping , e . piner , j . redwing , m . khan , and i . adesida , electron . lett . 36 , 175 ( 2000 ). 3 ) w . lu , j . yang , m . khan , and i . adesida , ieee trans . elect . dev . 48 , 581 ( 2001 ). 4 ) k . j . schoen , j . m . woodall , j . a . cooper , and m . r . melloch , ieee trans . electron . dev . 45 , 1595 ( 1998 ). 5 ) m . trivedi , and k . shenai , j . appl . phys . 85 , 6889 ( 1999 ). 6 ) q . wahab , t . kimoto , a . ellison , c . hallin , m . tuominen , r . yakimova , a . henry , j . p . bergman , and e . janzen , appl . phys . lett . 72 , 445 ( 1998 ). 7 ) k . g . irvire , r . singh , m . j . paisley , j . w . palmour , o . kordina , and c . h . carter , jr ., mat . res . soc . symp . proc . 512 , 119 ( 1998 ). 8 ) z . z . bandic , p . m . bridger , e . c . piqutte , t . c . mcgill , r . p . vaudo , v . m . phanse , and j . m . redwing , appl . phys . lett . 74 , 1266 ( 1999 ). 9 ) g . t . dang , a . p . zhang , f . ren , x . a . cao , s . j . pearton , h . cho , j . han , j . i . chyi , c . m . lee c . c . chuo , s . n . g . chu , r . g . wilson , ieee trans . electron dev . 47 , 692 ( 2000 ). 10 ) f . ren , a . p . zhang , g . t . dang , x . a . cao , h . cho , s . j . pearton , j . i . chyi , c . m . lee , and c . c . chuo , sol . state electron . 44 , 619 ( 2000 ). 11 ) t . g . zhu , d . j . h . lambert , b . s . shelton , m . m . wong , u . chowdhury and r . d . dupuis , “ high - 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