Patent Application: US-73803208-A

Abstract:
a direct conversion radio frequency transceiver integrated circuit is provided . the ic includes a local oscillator block , a receiver block , and a transmitter block disposed on a single silicon - based integrated circuit . each of such blocks are connected to a ground plane that includes a metal located adjacent to each of such blocks , air gaps located between each section of the metal adjacent to such blocks , each section of the metal being connected to the adjacent section of metal in the group plane at a location on the edge of the ground plan corresponding to a point substantially equidistant from the two sections of metal . a system and method is provided for implementing a direct conversion integrated circuit architecture . a clock distribution system is provided , as well as a method for radio detection and ranging using a doppler radar transceiver system in the w - band . a method for noise isolation between blocks of an integrated circuit is also provided .

Description:
the present invention discloses a system and method for implementing a single chip direct conversion w - band transceiver in silicon . the present invention also discloses a system and method for providing a clock distribution architecture operable to distribute a w - band signal in silicon technology . the present invention enables the die area of a transceiver to be minimized and power consumption to be reduced , using these systems and methods . the invention is advantageous over prior art systems in that it provides a w - band transceiver that is fully integrated onto a single chip in silicon technology . another aspect of the present invention is a novel w - band single chip transceiver . from a system perspective , the receiver and the transmitter are isolated from each other to avoid leakage of the transmitter output signal through a substrate or shared power and ground signals and into the receiver ( isolation is a particular concern in the direct conversion architecture ). the present invention includes a systematic method for implementing isolation structures and techniques consistently throughout the chip . a further advantage is that the present invention overcomes the leakage problem previously preventing implementation of a single die direct conversion w - band transceiver by using novel isolation structures and techniques between the transmitter and receiver . another advantage is that the invention uses standard 3 . 3v ( for the frequency divider ) and 1 . 8v / 2 . 5v ( for the transmitter and receiver ) power supplies , which reduces system power consumption . yet another advantage of the present invention is the use of a static frequency divider that provides a wider division frequency range than other types of frequency dividers and therefore is more reliable over temperature and manufacturing variations . a further advantage of the present invention is its low manufacturing cost as , it is implemented in silicon , and requires considerably less die area than other state - of - the - art transmitters , receivers , and transceivers . additional objects , advantages , and novel features of the invention will be set forth in part in the description and drawings which follow , and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention . the objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims . the direct conversion transceiver contains all blocks required for the transceiver functionality described ( in one implementation thereof , for example , a vco , an lna , a pa , a mixer , and a static frequency divider ). these components enable fabrication of a fully integrated low voltage , w - band transceiver with phase locked loop ( pll ). fig1 illustrates a block diagram of a direct conversion transceiver in accordance with the present invention . a particular embodiment of a direct conversion transceiver of the present invention is illustrated in fig2 . it is apparent to those skilled in the art that other embodiments of a direct conversion transceiver would provide substantially similar results , while leveraging the system , method and architecture of the present invention . some other particular implementations of the present invention and embodiments are described below . generally , the direct conversion transceiver is operable as follows , in accordance with one embodiment thereof . the voltage - controlled oscillator ( vco ) ( 11 ) may generate a radio frequency signal that is amplified by the power amplifier ( pa ) ( 13 ). the signal at the output of the pa ( 13 ) may optimally be transmitted using an antenna ( 15 ). the transmitted signal may reflect off of an object a distance away from the transmitting antenna ( 15 ) back to a receiving antenna ( 17 ). the received signal is amplified by a low - noise amplifier ( lna ) ( 19 ) which is coupled to the mixer ( 21 ), which mixes ( multiplies ) the received signal with the signal generated by the vco ( 11 ). the resulting mixed signal contains a high frequency component that is filtered out in the electronics as well as a baseband signal that represents the doppler shift . an on - chip intermediate frequency ( if ) amplifier ( not shown ) provides additional gain at baseband and can drive off - chip test equipment . the present invention overcomes the obstacles previously mentioned that prevent the implementation of a single chip direct conversion w - band transceiver in silicon . more particularly , the present invention overcomes the chief concerns of the direct conversion transceiver which are ( 1 ) isolation of circuit blocks , ( 2 ) flicker noise at baseband , and ( 3 ) vco phase noise . the present invention discloses a cell based integrated circuit layout methodology that may provide isolation between adjacent circuit blocks along with high capacitance and low resistance and low inductance power , ground , and bias planes for multiple circuit blocks . simultaneously , the methodology may allow the circuit designer flexibility in both the routing of signals over , under or between metal planes , and in choosing which of the stacked metal layers commonly provided in the back - end - of - line ( beol ) are connected together , and which are not . additionally , the methodology may enable the designer to meet density rules on all layers without relying on computerized filling algorithms . finally , the methodology may allow the designer to easily insert into an existing layout circuit blocks and components with minimal modifications to any layout work already performed . fig6 illustrates a novel methodology of arranging metal planes in a mesh pattern . the mesh covers all unused area on - chip , and is designed to provide the maximum coverage allowed by design rules ( which may typically range from 70 % to 80 %). furthermore , the mesh may provide substrate contacts and is highly capacitive , which offers significant decoupling . decoupling capacitors may also be inserted into the mesh periodically , particularly near circuits . various sizes of decoupling capacitors may be used to provide decoupling at different frequencies . the mesh meets density requirements on active , poly , and all metal and via layers which simplifies chip finishing procedures . although efforts are made to minimize the mesh resistance , considerable resistance could be present in circuits that are far away from ground or power pads . decoupling capacitors may be placed immediately at the end of all inductors and transmission lines to improve the ac ground . fig3 a illustrates a square ( 23 ) of area a that may be filled to an arbitrary density by the plus shape ( 25 ) of area b . the density of fill may then be b / a . alternatively , the same density of b / a may be obtained by filling the square ( 23 ) with the hollow - square shape ( 27 ) of fig3 b . if either pattern illustrated in fig3 a and 3 b is repeated , as shown in fig3 c for example , the total area filled with the pattern is filled to the density b / a . a plane of metal with density b / a may be created over a large area of an integrated circuit layout simply by repeating the cell in a mosaic if the area b is a layout cell containing a piece of metal , as illustrated in fig3 c . the density b / a may optimally be chosen to be slightly less than the maximum allowable density the metal layer in the beol of the technology used . thus , the area filled with the metal plane may have the minimum possible resistance between any two points on it , yet may pass the density fill rules on the metal within the area of fill . no computerized fill algorithm may be required . fig4 illustrates an arrangement of multiple metal layers that may be implemented using this technique . if the plus shape ( 25 ) illustrated in fig4 b is considered to be a piece of metal 1 , and the hollow - square shape ( 27 ) illustrated in fig4 c is considered to be a piece of metal 2 , then when they are overlapped in the layout view , 3 distinct regions may be formed : ( 1 ) regions where only metal 1 may be present ( 29 ), ( 2 ) regions where only metal 2 may be present ( 31 ), and ( 3 ) regions where metal 1 and metal 2 may overlap ( 33 ). the three types of regions ( 29 , 31 , 33 ) may be used to connect stacked metals in almost arbitrary combination by choosing which metals are formed using a plus shape ( 25 ) and which are formed using a hollow - square shape ( 27 ). as illustrated in fig5 a , one or more of the tabs ( 35 ) of a plus shape ( 25 ) may be removed , which may create additional regions where some plus shapes overlap but others do not . this may allow the circuit designer to connect stacked metals almost arbitrarily without relying on the hollow - square shape ( 27 ). by utilizing pieces of metal of the hollow - square shape ( 27 ) and the plus shape ( 25 ), which may or may not comprise all four tabs ( 35 ), the circuit designer may gain a systematic freedom in stacking and connecting metals . when shapes are repeated in a regular pattern , as shown in fig6 , the different types of overlapping regions may be preserved , whereas anything underneath the pattern may be almost entirely hidden . the region underneath the pattern in an integrated circuit may be the silicon substrate . therefore , by arranging two or more stacked metals in the fashion of fig6 , the circuit designer may obscure the substrate from transmission lines and interconnects on higher metal layers . fig6 also illustrates that when implemented across a metal plane , the plus shape ( 25 ) and hollow - square shape ( 27 ) may be indistinguishable . it should also be noted that other combinations of shapes may exist that may accomplish the same or a similar outcome . such a shape may comprise a polygon shape such as a hexagon shape , for example . on - chip leakage between circuit blocks may have two primary pathways : the substrate , and shared power and bias planes including the ground plane . substrate leakage may be reduced by placing n - well and p - sub contacts between circuit blocks . for isolation at mm - wave frequencies , a pattern of small checkered n - well and p - sub regions may be preferred over a continuous n - well region . noisy power signals , such as the pa supply , may optimally have minimal contact to the substrate . a novel approach to isolate circuit blocks on integrated circuits incorporates printed circuit board ( pcb ) design methodologies . leakage through power and bias planes may be reduced . power , bias , and ground planes must be maximally capacitive , minimally inductive and resistive , and separate ( or at least split ) for circuit blocks that must be isolated . in the single chip direct conversion w - band transceiver , separate power supply domains may be used for the lna , pa , and digital ( divider ) circuitry on - chip . isolation of circuit blocks located on the same die may normally be achieved by creating distance between them . however , placing circuit blocks further apart may increase the chip area and therefore also may increase its cost . instead , the circuit blocks of the present invention may be isolated using two techniques . first , isolation structures may be placed between them . second , metal planes may be stacked . fig7 illustrates that the isolation structures may consist of a stack of metal layers ( 37 , 39 ) optionally connected to either a plurality of power , ground , and bias signals ; all connected to ground ; or all connected to power . as illustrated in fig8 , the isolation structures may also consist of a checker pattern of p - sub ( 41 ) and n - well ( 43 ) regions connected to ground . the n - well ( n - type ) ( 43 ) and p - well ( p - type ) ( 41 ) regions may ensure that noise generated by one circuit block may not easily travel through the substrate to another circuit block while the stacked , grounded metals form a faraday cage around each circuit block that may shield it from electromagnetic fields generated by other blocks . fig9 illustrates a pattern that may be used to provide substrate isolation among circuit blocks . the n - well ( 43 ) and p - well ( 41 ) regions described above may be arranged within a square of area a , which may be equivalent to the area occupied by a unit of metal as described earlier , as illustrated in fig9 b . areas of overlap between the piece of metal ( 25 ) and the n - well ( 43 ) and p - well ( 41 ) regions may be used to form connections between them . fig1 and 11 illustrate how the n - well and p - well regions may be repeated in a mosaic to isolate areas of the substrate . for example , in fig8 , substrate noise may be reduced since noise traveling from point a to point b must take a circuitous route that impedes its travel . further isolation may be achieved using highly capacitive stacked metal planes to distribute ground , power , and bias signals to all circuit blocks . as shown in fig1 a , the metal planes may be stacked to provide as much capacitance between the ground plane ( 45 ) and metal planes of other power ( 47 ) and bias ( 49 ) signals . as shown in fig1 b , the metal planes ( 51 ) used to distribute said signals to noisy circuit blocks , such as the pa ( 13 ) for example , may be separated from the metal planes used to distribute said signals to sensitive circuit blocks , such as the lna ( 19 ) for example . noise generated by the pa ( 13 ) may not travel directly to the lna ( 19 ), but may take a longer route and therefore may be highly attenuated by the time it reaches the lna ( 19 ). the present invention may be operable to overcome flicker noise problems by optionally implementing the circuit in sige hbt , for which flicker noise at baseband is minimal . vco phase noise may present a problem in doppler radar systems because it limits both the smallest doppler frequency that can be detected and also the useful range of the doppler radar . the vco phase noise must therefore be minimized . because vco phase noise performance degrades as the oscillation frequency of the vco increases , state - of - the - art silicon w - band transmitters often use a lower frequency vco to obtain superior phase noise performance . those skilled in the art generally believe the phase noise performance of w - band sige hbt vco may not be sufficient to detect doppler shifts on the order of tens or hundreds of hertz . however , using a lower frequency vco may necessitate the use of an up - converter or frequency multiplier to obtain a w - band signal . the present invention employs two novel techniques to overcome this issue . first , the vco in the present invention may achieve low phase noise by implementing the vco as a differential colpitts oscillator . the oscillator may use a single transistor topology to minimize phase noise . the use of this vco at 77 ghz , for example , may be operable to detect a doppler shift of only 55 hz . second , phase noise may be reduced in the direct conversion architecture by correlation at the lo and rf ports of the down - conversion mixer . as illustrated in fig1 , in a direct conversion receiver the phase noise , φ n ( t 1 )( 53 ), present at the lo port ( 55 ) of the mixer is produced by the same vco ( 11 ) ( as there is only one vco ) as the phase noise received at the rf port ( 57 ) of the mixer . however , due to the round trip delay time ( τ ) to the target , the phase noise present at the lo port ( 55 ) is then a time delayed version of the noise seen at the rf port ( 57 ), or φ n ( t 1 − τ ). for small values of τ , the phase noises x and y are highly correlated , and therefore the phase noise at the baseband output ( 59 ) of the mixer ( 21 ) is reduced . implementing a w - band transceiver may require that a single vco provide signals for at least three circuit blocks , if present in the direct conversion transceiver : the power amplifier , down - conversion mixer , and frequency divider . the vco must provide sufficient signal power to each block such that they all function correctly . connecting the vco directly to all circuit blocks may result in a non - functional transceiver , or at best a transceiver with significantly reduced performance because the down - conversion mixer , frequency divider and power amplifier together present a significant load that the vco cannot drive directly . furthermore , noise generated by the power amplifier can then leak backward through its connection to the vco , and into the vco , from where it can propagate directly to the down - conversion mixer and subsequently the lna . noise generated by the frequency divider may propagate similarly . a clock distribution network is needed to provide high forward gain from the vco to the down - conversion mixer , power amplifier and frequency divider while ( 1 ) simultaneously providing high reverse attenuation to prevent the back - propagation of noise from the power amplifier and frequency divider into the vco and down - conversion receiver ; and ( 2 ) allowing some physical separation of the vco , power amplifier , frequency divider , and down - conversion mixer wherein isolation structures can be inserted to further prevent the propagation of noise between circuit blocks , and power , bias , and control signals can be routed . one method for vco signal distribution is called a clock tree . a clock tree is an expanding series of buffers ( 61 ) and transmission lines ( 63 ) that splits the vco signal into several separate signals , as shown in fig1 a , where the signal splitting is accomplished using transmission lines . alternatively , as shown in fig1 b , the signal splitting can be implemented using the buffers themselves . the buffers ( 61 ) in the clock tree may amplify the vco signal to drive the various circuit blocks . a single vco ( 11 ) may not be operable to drive each circuit block without the use of the clock tree . the clock tree may also allow a w - band vco signal to be routed between circuit blocks , which allows sensitive receiver circuits , such as the lna , to be separated far from the power amplifier and the isolation structures described earlier to be placed between . another aspect of the present invention is that it implements a w - band static frequency divider in a silicon based w - band transceiver . the static frequency divider may provide an output at some fraction of the vco frequency ( one 64 th for example ), a signal operable in a phase - locked loop . the static frequency divider architecture offers a wider division frequency range than other types of frequency dividers ( for example , dynamic frequency dividers ) and therefore is more reliable over temperature and manufacturing variations . a static divider topology is , however , difficult to design from a 3 . 3v supply with sufficient design margin for use up to 125 ° c . in w - band . the implementation of the static frequency divider of the present invention is enabled by the clock distribution technique . while a static frequency divider driven directly from the vco may not be operable , the buffers in the present invention amplify the vco signal so that the divider is operable . furthermore , the self - oscillation frequency of the static divider may be designed to be the same as the vco oscillation frequency . this technique may further reduce the input power requirements of the static frequency divider . the frequency band of 77 - 81 ghz has been designated for automotive use and therefore a w - band transceiver that operates within this narrower frequency band could be used in automotive applications . fig1 illustrates a direct conversion transceiver . the doppler shift due to a moving target is indicated by a frequency shift δf ( 65 ) in the reflected lo signal . a single - chip silicon direct - conversion transceiver may contain four core components : low - noise amplifier ( lna ) ( 19 ), voltage - controlled oscillator ( vco ) ( 11 ), power amplifier ( pa ) ( 13 ), and down - conversion mixer ( 21 ), arranged as illustrated in fig1 , and fabricated together on the same silicon substrate . one embodiment of a single chip direct conversion transceiver is illustrated in fig2 . in this embodiment , the voltage - controlled oscillator ( vco ) ( 11 ) may drive a single buffer ( 67 ), which may drive a network of transmission lines ( 69 ) that may distribute the signal to the 6 - stage static frequency divider ( divider ) ( 71 ) the three stage power amplifier ( pa ) ( 73 ) and the down - conversion mixer ( mixer ) ( 75 ). the received signal may be amplified by a three stage low - noise amplifier ( lna ) ( 77 ), which may be transformer coupled ( 79 ) to the mixer ( 75 ). an on - chip intermediate frequency ( if ) amplifier ( 81 ) may provide additional gain at baseband and may drive off - chip test equipment . the transceiver may be physically implemented to occupy an area of approximately 1 . 2 mm by 0 . 9 mm , including all pads . a frequency divider may be added , as described above , to facilitate the development of systems , such as automotive radar , that may require additional circuitry relying on a divided version of the vco signal . the additional circuitry may be , for example , a phase locked loop ( pll ). yet more circuitry may be located on the chip , such as digital signal processing ( dsp ) circuitry , voltage regulators and references , analog to digital converters , or an intermediate frequency ( if ) amplifier . furthermore , some of the four core circuit blocks may be removed , albeit at a significant performance cost . for example , the lna ( 77 ) and pa ( 73 ) may be removed , however then the system would suffer from poor noise performance as the first circuit to receive the reflected signal would be the down - conversion mixer , and mixers typically may have higher noise figure ( nf ) than amplifiers . alternatively , only the pa ( 73 ) may be removed , and the vco ( 11 ) may be used as the transmitter directly . without a pa ( 73 ), however , the usable range of the transceiver would be greatly reduced . as yet another alternative , the pa ( 73 ) may be made smaller ( which reduces the transmitted power ), and the gain of the lna ( 77 ) increased , such that the overall performance of the transceiver is unaffected . likewise , the pa ( 73 ) may be made larger ( which increases the transmitted power ), and the gain of the lna ( 77 ) decreased . furthermore , both the lna ( 77 ) and pa ( 73 ) may be removed , and the system would remain a single - chip direct - conversion transceiver because it maintains the fundamental property that frequency conversion from rf to baseband is completed in a single step , and on a single chip . further still , the transceiver may be implemented without the transformer ( 79 ) coupling the lna ( 77 ) to the mixer ( 75 ). there may be further modifications to the pa ( 73 ). the pa ( 73 ) may be implemented without a pre - amplifier ( 83 ). additionally , the pa ( 73 ) may be driven differentially by the vco clock tree buffer ( 85 ) corresponding to the pa ( 73 ). furthermore , the pa ( 73 ) may be combined in parallel with additional pas to deliver more output power . the lna ( 77 ) may be modified to contain a variable attenuator . the vco ( 11 ) may be further modified . the vco ( 11 ) may be operable with differential tuning or single ended tuning . additionally , the transceiver may contain multiple vcos of different frequency ranges to implement an overall wider frequency range . for example , there may be one vco ( 11 ) with a frequency range of 77 - 79 ghz and a second vco ( 11 ) with a frequency range of 79 - 81 ghz . the two vcos may be used together to provide a transceiver operable between 77 ghz and 81 ghz . the vco ( 11 ) may be provided at a different frequency . generally a system , such as the present invention , that is operable at a given frequency is also operable at all lower frequencies . thus the vco ( 11 ) may be operable at any frequency at or below w - band . the single - chip silicon direct - conversion transceiver is separate from the implementation of the individual circuit components , so long as they are implemented on silicon together on the same substrate . for example , the lna ( 77 ) or pa ( 73 ) may contain alternate numbers of stages , any circuit block may operate from a higher or lower supply voltage , or may be implemented using different circuit topologies ( such as differential topologies , for example ) than those used in the embodiment illustrated in fig2 . furthermore , the direct conversion transceiver is independent of the performance of each circuit block . for example , the lna ( 77 ) may have more gain or improved noise figure , the pa ( 73 ) may provide greater output power , and the vco ( 11 ) may have lower phase - noise . finally , individual circuit blocks , or groups of circuit blocks ( such as the lna ( 73 ) and mixer ( 75 ), for example ) may contain novel or non - obvious improvements or modifications , but still be arranged to form a direct conversion transceiver . other embodiments of the invention may be formed by connecting the circuit blocks together in a different manner . isolation techniques may also be modified . the metal planes ( 51 ) as shown in fig1 b may be provided with greater separation such that any of the components , or each component , shown in fig1 b is isolated from the others . for example , the pa ( 13 ) may be physically separated from the frequency divider ( 87 ) shown in fig1 b . the clock distribution network may be modified . there may be provided more or less number of transmission lines ( 63 ) or buffer amplifiers ( 61 ) to drive the circuit blocks . furthermore , the clock distribution network may be removed and the vco ( 11 ) may drive the mixer ( 75 ), divider ( 71 ) and pa ( 73 ) directly . the static frequency divider ( 71 ) may be provided with a different number of stages or a different division rate . the single chip direct conversion w - band transceiver may be operable to detect the doppler shift . the use of radio - frequency transceivers for detecting the doppler shift is known to those skilled in the art . the present invention is operable to provide a doppler radar transceiver in the automotive frequency range of 77 ghz to 81 ghz and , therefore , is useful in the applications of collisions avoidance , pre - collision intelligence , lane - changing assistance , parking assistance , road surface monitoring , night and fog vision systems , and other applications employing doppler shift detection . the single chip direct conversion w - band transceiver may also be operable for mm - wave imaging . the use of radio - frequency transceivers for mm - wave imaging is known to those skilled in the art . experimental verification was conducted using a 0 . 13 μm sige bicmos process with f t / f max of 170 / 200 ghz implementing the embodiment given in fig2 . the selected frequency for the lo was 77 ghz . relative to prior art 77 ghz transceivers , the present invention experiences a relatively high linearity , relatively low noise , and low die area . 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