Patent Application: US-85083404-A

Abstract:
a test chip performs measurements to evaluate the performances of interconnects . in particular , the statistical failure distribution , the electromigration and the leakage current are measured . an algorithm detects a via failure at any of the available n metal layers . the test chip includes a rom memory array . the vias to be measured are formed in the columns of the array . via or contact failures are detected by forcing a predetermined current through both an array column and a reference column . the failure analysis is obtained by comparing the resulting voltage drops .

Description:
based on the above assumption , a basic pyramidal test scheme as schematically depicted in fig2 makes it possible to detect an interconnect failure at any level . each level 1 to n represents a metal layer except for the bottom level 0 , which represents the active silicon area . the nodes of the illustrated arrow tree diagram represent c / vs between adjacent conductive layers . the proposed structure includes an ( n + 1 ) level pyramidal topology , where n is the number of metal layers of the fabrication process under evaluation . the electrical path between any node nj ( 1 ≦ j ≦ 2 n − 1 ) and node b includes one interconnect element for any c / v level . any zero - level contact belongs to one only path , while any i - th level via is included in 2 i adjacent paths . as a result , a failure in any i - th level c / v ( i . e ., any contact or via between the i - th and the ( i + 1 )- th interconnection layer affects the path between node b and 2 i adjacent nodes n j and , hence , its overall resistance . it is evident that it is possible to detect if an interconnect failure is present in any path pj between b and n j by simply measuring the resistance between the two nodes . moreover , by measuring the resistance of all the paths connected to node b , the exact location of the failed element ( if any ) can be identified , assuming that a single failure is present in the basic structure . to be specific , fig3 depicts the possible test results obtained when sequentially scanning all the 2 n − 1 paths . for simplicity , the case of a four - metal layer technology is considered . any column in the figure represents a possible sequence of the test results referred to each individual path . a black square = a failed path ( i . e ., high - resistance ), and a non - filled square = a working path ( i . e ., low - resistance ). sequence s 15 represents the case when all paths are working . sequences s 14 to s 7 correspond to the presence of a failure at the zero contact level , i . e ., at the metal 1 - to - active area contact level . each sequence corresponds to a different location from the first to the eighth of the failed contact . sequences s 6 to s 3 refer to the case of a failure at the first via level ( metal 2 to metal 1 ). sequences s 3 and s 2 represent a failure at the second via level ( metal 3 to metal 2 ). finally , sequence 1 ( all paths failed ) corresponds to the failure at the highest via level . it is clear that , for any measured structure , the location of the failed c / v can be easily identified by looking at the failure plot . this allows the subsequent physical failure analysis to be carried out . the above considerations can be easily extended for any value of n . in the general case , the number of possible test result sequences is given by : f = 1 + ∑ i = 0 n - 1   2 i . ( 1 ) for the considered case of a four - metal process , the core of the proposed test chip may be an array of 8 sectors , each made up of 64 × 1024 elementary pyramidal structures , which can be regarded as a rom array . each contact and via in the array ( i . e ., any node of the basic tree - diagram of fig2 ) is a memory cell , wherein the stored information is the presence or the absence of an interconnect failure . any of the 1024 bit - line runs in the n - th metal layer ( in our case , n = 4 ), includes 64 pyramidal structures and , hence , 512 zero - level contacts and 511 vias , for a total of about 0 . 5 m contacts and 0 . 5 m vias per sector . each basic structure is obviously placed so as to lie under the associated bit - line . during a read operation , the required path ( from the addressed bit - line to the desired node n j ) is selected through a transistor whose gate is driven by a polycide stripe . these stripes represent the array word - lines ( wls ). to increase the number of contacts per unit area , in the test chip the bit - lines of any sector may be grouped in 512 pairs , and an interleaved approach may be followed for the zero - level contacts of any pair of bit - lines p , o and p , e ( 1 ≦ p ≦ 512 , o = odd , e = even ). a detail of a bit - line pair defined in the third level metal ( metal 3 ) is illustrated in fig4 . the selection transistor ( t h , o , 1 ≦ h ≦ 256 ) associated to any given path p h , o in an odd bit - line , connects the corresponding node n h , o to the neighboring node n h , e of the corresponding even bit - line rather than to ground , so that the number of available contacts ( and , hence , of paths n j ) is maximized . the same consideration applies to selection transistors ( t h , e ) associated to paths p h , e in the even bit - line . the decoders for “ odd ” and “ even ” word - lines ( wl h , o , and wl h , e , respectively ) may be placed at the two opposite sides of the array , to relax pitch requirements of their final stages . with an organization as described above , during a reading operation , the resistance of two series - connected paths p h , o , and p h , e is measured . it must be noted that , in this way , two zero - level contacts are included in a complete current path . to allow contact failure detection at node n h , o ( n h , e ), both selection devices connected to this node , i . e ., t h − 1 , e and t h , o ( t h , o and t h , e ), are activated by their respective word - lines . in this way , a redundant path is introduced , which places two zero - level contacts of the even ( odd ) bit - line in parallel . for example , in an h8 type process , if the width w of a transistor is 1μ , access to the relative single contact takes place through the equivalent resistance of 2μ of a minimum channel length . for n - channel transistors this is equal to about 2kω , and for p - channel transistors this is equal to about 5kω . in practice , these values define the limit of sensitivity . if a greater sensitivity is desired , width w of the array transistors must be increased by decreasing the number of transistors of the test array , and thus restricting the statistical sample for a given area dedicated to the integration of the test array structure in the test chip . of course , the test chip may be and will normally be provided with typical test mode circuitries of flash memory chips ( i . e ., read , dma , fast dma ) and it will be preferable to use reference array cells as it is normally done in common rom and eprom devices . because two series - connected paths are simultaneously assessed , to determine the location of a failure ( if any ) it is necessary to determine if the failure is related to the odd or the even bit - line . actually , the basic topology becomes that of a pair of interleaved pyramidal structures , each referring to 2 n word - lines . as a consequence , the number of possible test result sequences s i is given by : f = 1 + ( 1 + 2 n - 1 ) + 2  ∑ i = 0 n - 2   2 i . ( 2 ) [ 0048 ] fig5 illustrates the corresponding failure diagram . for simplicity , three metal layers have been assumed . the correct failure evaluation can be performed as follow . the subset s i , e ( i = 2k , 1 & lt ; k & lt ; 2 n − 1 ) refers to failures of even bit - lines whereas the subset s i , o ( i = 2k + l , 1 & lt ; k & lt ; 2 n − 1 ) refers to failures of odd bit - lines . the fault level can be obtained as in the case of single - tree structures . read operations are carried out using a sense circuit topology as shown in fig6 . a reference current i ref ( in the range of 10 μa ) is forced into the selected odd - bit bit - line p , o through device m o . the current flows through the selected path p h , o , p h , e and reaches the associated even bit - line p , e , which is connected to ground by a switch p gnd , e ( switch p comp , e is open ). the voltage v o that represents the voltage drop across the selected path ( switches p comp , o and p gnd , o are closed and open , respectively ) is compared to an adequate voltage v ref , which is obtained by injecting the same current i ref into a reference path . as depicted in fig7 the reference path is a replica of an array path and generates the phases v pol and v pol inverted and the current i ref , and includes an additional resistance r th . the value of the additional resistance r th is programmable for determining desired trigger point of the comparator comp . by adjusting the value of r th , this will allow the threshold failure to be programmed . moreover , the statistical distribution of the path resistance values can be obtained . obviously , reading can also be accomplished by injecting the current i ref into the even bit - line through device m e ( in this case , switches p comp , e and p gnd , o are closed , and switches p comp , o and p gnd , e are open ). since the dynamic range of the output voltage v o can vary from ground to v dd , a rail - to - rail input swing comparator topology [ 11 ], [ 12 ] is used . the electromigration failure test can be carried out by forcing different amounts of currents ( e . g ., up to 250 μa ) into the bit - lines ( and , hence , into the selected path ) using a device m o ( or m e ). to measure the inter - metal leakage current , the row and the column decoders of the array can address the word - lines and bit - lines in several ways . for example , it is possible to force all word - lines to v dd and all bit - lines to ground . this allows the oxide leakage currents to be measured . alternatively , the even and the odd word - lines can be forced to v dd and to ground , respectively , which allows a poly - to - poly leakage to be evaluated . metal - to - metal leakage may also be tested by forcing the even and the odd bit - lines to v dd and to ground , respectively . fig8 is a picture of the test chip layout . of course , the approach of this invention is to provide for a significant statistical analysis of problems that may arise because of different failure and degradation mechanisms that may affect the actual performance of contacts and vias produced by certain processing steps . this lends itself to a number of refinements for discriminating among the various failure and / or degradation mechanisms . to assess the quality of contacts on p - type regions , on n - type regions , and on vias , three test chips may be used . two distinct test chips may be employed for assessing and analyzing the quality of the contacts on p - type regions and on n - type regions . these two distinct test chips specifically dedicated to assessing the quality of contacts may be fabricated with only one metal level ( metal 1 ), as it is normally done . then , according to the present invention , a further test chip will be fabricated with the multi metal pyramidal addressing structure for evaluation of vias , using for this test chip n - channel transistors to enhance sensitivity . in a third test chip made according to the present invention , assuming that the cell area , for a 0 . 18 μm test array will be 0 . 7 μm 2 , the area of a 16mbit test chip will be about 15 mm 2 . this allows testing of 16 million contacts , 8 million vias in metal 1 , 4 million vias in metal 2 , and so forth . optionally , beside the three test chips used to generate enhanced statistical data , two additional test chips , respectively for contacts on the p - type regions and for contacts on the n - type regions , with a lower statistic weight and proportionally with an increased sensitivity ( for example , with a test array of one sixteenth of the total number of transistors of the main test chips and with a sixteen times enhanced sensitivity , by making the transistors sixteen times larger ) may be used for investigating the range of design contact resistance from 100 to 1000 ohms . the main advantage offered by the presented test chip is the possibility to perform failure evaluation for all the contact / via levels with the same chip . as a result silicon area and testing time are reduced . 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