Patent Application: US-5606305-A

Abstract:
low - voltage cmos circuits , suitable for analog decoders , for example , are provided . the circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals . each multiplier module generates as output signals products of the first input signals and its respective second input signals . dummy multiplier modules that respectively correspond to the multiplier modules receive the second input signals , and each dummy multiplier module forms products of the second input signal of its corresponding multiplier module and the other second input signals . the dummy multiplier modules reduce the overall voltage requirements of the circuit , thereby providing for low - voltage operation . in some embodiments , a connectivity module receives output signals from the multiplier modules and generates as output signals sums of predetermined ones of the output signals , and a renormalization module receives and normalizes the output signals from the connectivity module to generate output signals that sum to a predetermined unit value .

Description:
the sum - product algorithm [ 9 , 17 ] is a general framework for expressing probability propagation on factor graphs . the purpose of the algorithm is to compute global conditional probabilities using only local constraints . constraints are often expressed by factor graphs [ 5 , 9 , 17 ]. special cases of factor graphs include trellis graphs and tanner graphs , which are also referred to as constraint graphs . according to one embodiment of the invention , the sum - product algorithm is implemented on graphs which express boolean functions on discrete - type variables . for example , consider the implementation of graphs which can be simplified to local boolean constraints on three variables . fig1 is a factor graph of such a constraint function of three variables . the function ƒ expresses a relationship between variables x , y , z , which can take values from discrete alphabets a x , a y , a z , respectively . the function ƒ ( x , y , z ) is a boolean constraint on ( x , y , z ) if ƒ ( x , y , z ) ε { 0 , 1 } for all x , y , and z , and the constraint ƒ is said to be satisfied if and only if ƒ ( x , y , z )= 0 . the constraint ƒ and the variables ( x , y , z ) have , up to this point , been defined as deterministic . when ( x , y , z ) are random variables , denoted herein with boldface type , they are characterized by probability , masses instead of exact values . the goal of probability propagation is to determine the probability mass of z , written ρ z , based on known masses ρ x and ρ y . normal typeface for these variables indicates particular samples or values of the random variables . the local operations of the sum - product algorithm are described as follows . the constraint ƒ is mapped to a processing node which receives probability masses for . variables x and y . these variables are assumed to be independent of each other . the processing node then computes the probability mass of z based on the constraint ƒ and the masses of x and y . let s ƒ be the set of combinations of ( x , y , z ) for which ƒ ( x , y , z ) is satisfied . let sƒ ( j ) be the subset of s ƒ for which z = j , where jεa z . we then compute , for each j , the function p ⁡ ( z = j ) = η · ∑ ( k , l ) ∈ s f ⁡ ( j ) ⁢ p ⁡ ( x = k ) · p ⁡ ( y = l ) , ⁢ ρ z ⁡ ( j ) = η · ∑ ( k , l ) ∈ s f ⁡ ( j ) ⁢ ρ x ⁡ ( k ) · ρ y ⁡ ( l ) , ( 1 ) where kεa x and lεa y , η is any non - zero constant real number , and x , y , and z are random variables . the constant η is typically chosen so that σjp ( z = j )= 1 . in principle , though , the accuracy of the algorithm is indifferent to η . the local computation ( 1 ), is the heart of the sum - product algorithm . a complete sum - product decoder consists of many interconnected instances of ( 1 ). one approach for cmos analog decoder designs , elaborated in [ 10 ], has emerged as a popular topology for analog decoder designs . this topology is based on a generalized gilbert multiplier . fig2 is a block diagram of a gilbert - based sum - product circuit , comprising a renormalization module 12 , a connectivity module 14 , a of column input transistors , three of which are shown at 15 , 17 , 19 , which behave as analog current sources . because of its popularity , the architecture of fig2 is referred to herein as the canonical topology . in typical implementations of a gilbert circuit , each multiplier module 16 , 18 , 20 includes an array of source - connected transistors , such as the array 17 shown in fig3 a . in fig2 , x denotes an ordered sequence of row inputs ( voltages ) x =& lt ; x 1 , . . . , x n & gt ;, and y denotes an ordered sequence of column inputs ( voltages ) y =& lt ; y 1 , . . . , y m & gt ;. many circuit implementations convert current inputs ix i and iy k into voltage inputs x i and y k using diode - connected transistors , for example , such as shown in fig3 b , corresponding to transistors 21 , 22 and 23 , 24 . all of the transistor devices implementing the canonical topology typically have the same dimensions . for the purposes of simplifying circuit analysis , assume that ix i ∝ ρ x ( i ) and that iy j ∝ ρ x ( j ), so that the current - mode column and row inputs represent probability masses . intermediate outputs emerge from the top of the multiplier modules 16 , 18 , and 20 in fig2 . there are n × m such outputs , which will be referred to as iz ij , corresponding to one row position i and one column position j . these intermediate outputs represent multiplication of row and column inputs , iz ij ∝ ix i · iy j , thus performing the “ product ” portion of ( 1 ). to complete the computation of ( 1 ), summation of desired products is accomplished by shorting wires in the connectivity module 14 . as those skilled , in the art . will appreciate , unused products , namely those for which the constraint ƒ is not satisfied , are shorted to vdd . the gilbert multiplier consists of mos transistors biased in the sub threshold region , meaning v qs & lt ; v rh for each transistor , where v qs refers to the voltage between the gate and source of an mos device , and v th refers to the threshold voltage . in digital design , sub threshold transistors are usually regarded as “ off .” a more precise model of their behaviour is given by i d = i 0 ⁢ w l ⁢ exp ⁡ ( κ · v gs u t ) ⁡ [ 1 - exp ⁡ ( - κ · v ds u t ) ] , ( 2 ) where i 0 is a technology constant with units of amperes , w and l are the width and length of the transistor device , respectively , k ≈ 0 . 7 is a unit less technology constant , and u t ≈ 25 mv is the well - known thermal voltage . in the subthreshold region , i d is usually below 1 μa , resulting in very low power consumption . the subthreshold region is also commonly known as weak inversion , because the mobile charge density in the transistor &# 39 ; s channel is very small . circuits based on this subthreshold model were popularized by vittoz , et . al . [ 16 ]. if v ds is sufficiently large ( around 150 mv ), then it has little effect on i d in ( 2 ). when v ds is large enough to be neglected , the device is said to be in saturation . in the canonical approach , all transistors are assumed to be in saturation . to ensure this , the reference voltage v ref ≈ 0 . 3 v is used at the source of transistors 21 , 22 and other row input current to voltage conversion devices . this maintains a sufficiently high voltage at the drain of each column input transistor 15 , 17 , 19 for the column input transistors to remain in saturation . the gilbert multiplier is based on the translinear , principle . according to this principle , in a closed ( kirchoff ) loop of devices in which the current ( i d ) is an exponential function of the voltage ( v qs ), a sum of voltages is equivalent to a product of currents . because the sum of forward voltage drops equals the sum of backward voltage drops around the loop , the product of forward currents equals the product of backward currents . by taking a closed loop beginning and ending at v ref and traversing the v qs of four devices 25 , 26 , 27 , 28 as shown in fig4 , we arrive at iz ij · ix k = iz kj · ix i ⇒ iz kj = ix k ⁢ iz ij ix i . ( 3 ) if the column input transistors 15 , 17 , 19 are saturated , their drains simply replicate the current inputs at corresponding current to voltage conversion devices 23 , 24 . because the sources of their constituent transistors are all connected together , the sum of intermediate outputs from the j th multiplier module is equal to iy j . thus ∑ k ⁢ iz kj = iy j ( 4 ) ⇒ iz ij ix i ⁢ ∑ k ⁢ ix k = iy j ( 5 ) ⇒ iz ij = ix i · iy j ∑ k ⁢ ix k . ( 6 ) because the algorithm specifies probability masses as the input and output of processing nodes , it may be assumed that the denominator of ( 6 ) is equal to one , in probability terms , and thus may be neglected . the above requirement for saturation imposes a minimum allowed supply voltage on gilbert - based circuits . it is common to use one gilbert - based circuit made of nmos devices , of which the outputs are “ folded ” into a second gilbert - based circuit made of pmos devices . a “ slice ” of this topology is illustrated in fig5 . the pmos gilbert - based circuit comprises a plurality of transistors 29 , 30 , 31 , 32 , and can perform either a second sum - product operation or provide renormalization of currents to boost the output currents so that their sum equals a desired unit current . the renormalization module 12 in fig2 represents this renormalization function . the pmos transistors 29 , 30 , 31 , 32 must also be in saturation , and must have their own separate v ref . in fig5 , the separate v ref &# 39 ; s are indicated by v ref ( n ) and v ref ( p ). the operation of the folded topology shown in fig5 will be apparent to those skilled in the art . it is clear in fig5 that the terminals of four devices are traversed between vdd and ground . the transistor devices 30 , 33 , and 36 must remain in saturation for the circuit to function properly . as a rough analysis , a voltage of at least 300 mv between the drain and source of each device may be required . the drain of the device 33 is typically ˜ 350 mv below v ref ( p ). the drain of the device 30 is commonly in the range v ref ( p )± 50 mv . the source of the device 33 is typically v ref ( n )± 50 mv . assuming the extreme cases , saturation requires a supply voltage no less than 1 . 35 v . if the saturation requirement is relaxed to a v ds of 150 mv , then the supply voltage can be no less than 0 . 9 v . this result is based on the saturation assumption . in practice , saturation is only an approximate condition . the output of the folded circuit does always depend slightly on the other inputs . as v ref ( p ) is increased and v ref ( n ) is decreased , the device becomes less saturated , and the output begins to change dramatically . in the extreme case where v ref ( p )= v dd and v ref ( n )= 0 , we must use the full model expressed in ( 2 ), without neglecting v ds . when a transistor is not in saturation , the translinear principle still applies . the complete non - saturation mos device model is illustrated in fig6 . the total device current is divided into two oppositely directed components . the forward component , i ƒ , is controlled by v gs . the backward component , i r , is controlled by v gd . the total current is i d = i ƒ − i r . to solve circuits with unsaturated transistors , translinear loops must traversed v gd as well as v gs . it is clear from the foregoing that the voltage needs of the gilbert multiplier can be reduced if v ref = 0 . this results in the column input transistors 15 , 17 , 19 becoming unsaturated . this situation can be analyzed using the translinear principle . the circuit consists of the translinear loops shown in fig4 , and 8 . the first loop , shown in fig4 , was analyzed above , and yields the equation fig7 shows a column input current to voltage conversion transistor 38 connected to an unsaturated column input transistor 37 , with its additional component i r . the current i dj is defined as the role of the source - connected transistors , from ( 4 ), may be expressed as : id j = ∑ k ⁢ iz kj . ( 10 ) to solve for all currents in the circuit , we need one more equation , which is provided by the third loop , through the devices 43 , 39 , 44 shown in fig8 also shown : iz ij · if = ir · ix i ( 11 ) ⇒ ir = iy j · iz ij ix i ( 12 ) although the devices 40 , 41 , 42 are shown in fig8 for completeness , the above particular example third loop does not include these devices . id j = iy j - iy i · iz ij ix i ( 13 ) ⇒ ∑ k ⁢ iz kj = iy j - iy j · iz ij ix i ( 14 ) ⇒ iz ij ix i ⁢ ∑ k ⁢ ix k + iy j · iz ij ix i = iy j ( 15 ) ⇒ iz ij = iy j · ix i ∑ k ⁢ ix k + iy j . ( 16 ) the result ( 16 ) is almost the same as the normal gilbert multiplier output ( 6 ), except there is an additional term in the denominator . in probability terms , the denominator of ( 16 ) can no longer be neglected . to solve this problem , in accordance with an embodiment of the invention , additional transistors are provided with their sources connected to id j . if these transistors represent a current i 8 ≡ σ l ≠ j iy l , then the output becomes iz ij = iy j · ix i ∑ k ⁢ ix k + i δ + iy j ( 17 ) ⇒ iz ij = iy j · ix i ∑ k ⁢ ix k + ∑ l ≠ j ⁢ iy l + iy j ( 18 ) ⇒ iz ij = iy j · ix l ∑ k ⁢ ix k + ∑ l ⁢ iy l . ( 19 ) in probability terms , the denominator of ( 19 ) is a constant and can be neglected . the addition of redundant transistors therefore corrects the probability calculation of the gilbert multiplier when v ref = 0 . because these new transistors do not provide useful outputs , they are referred to herein as dummy transistors or dummy inputs . the drains of these transistors are preferably connected to vdd . fig9 is a block diagram of a low - voltage cmos sum - product circuit according to an embodiment of the invention , comprising a renormalization module 52 , a connectivity module 54 , a plurality of multiplier modules 56 , 58 , and 60 , a plurality of dummy multiplier modules 66 , 68 , and 70 , and a plurality of column input transistors generally designated by 71 . in fig9 , x denotes an ordered sequence of row inputs ( voltages ) & lt ; x1 , . . . , x n & gt ;, and y k denotes a set of column inputs ( voltages ) { y l } m l = 1 excluding the input y k . the members of y k need have no particular order . if necessary , current inputs ix i and iy l are converted into voltage inputs x i and y l by diode - connected transistors as shown in fig3 b and described above . all transistor devices used to implement the sum - product circuit in fig9 preferably . have the same dimensions , with the possible exception of the transistors , illustratively pmos transistors , used in the renormalization module 52 . renormalization is described in further detail below . as described above , desired products from the multiplier modules 56 , 58 , and 60 are summed together by shorting wires in the connectivity module 54 , and unused products are shorted to vdd . in a practical setting , the sum - product algorithm is carried out repeatedly in a chain of computations . the output of one computation provides input for the next . in an analog implementation , each computation is performed by a separate sum - product module . a complete analog error control decoder consists of cascades of sum - product modules . for a low - voltage decoder , renormalization of currents between modules is preferred . in a canonical gilbert - based sum - product circuit with outputs expressed by ( 6 ), the denominator is equivalent to ‘ 1 ’ and can be truly ignored . in the low voltage output expressed by ( 19 ), however , the denominator is equivalent to ‘ 2 ’, which results in substantial attenuation at the output of each circuit . while , in principle , linear attenuation will not change the . result of decoding , consistent attenuation in a large network will cause the outputs to approach zero , making it impossible to extract any results , and causing the circuit to slow to a halt . by inserting the renormalization module 52 between sum - product circuits , the current outputs are prevented from approaching zero . a renormalization circuit that may be implemented in the sum - product circuit of fig9 . is shown in fig1 . the parameters m and n indicate that the transistor &# 39 ; s width is increased by a factor of m or n relative to other transistors used in a sum - product circuit . canonical gilbert - based sum - product circuits typically use m = 1 and n = 1 . the circuit of fig1 . is basically a low - voltage sum - product circuit with only a single column input i u , which represents a global reference current , and a plurality of pmos transistors 72 , 73 , 74 , 75 , 76 , 77 . in probability terms , i u ∝ 1 . the behaviour of fig1 . is described by the equation out i = n · m · i u · in i n · i u + m · ∑ k ⁢ in k , ( 20 ) which is a generalization of ( 16 ). as demonstrated by ( 20 ), the renormalization circuit of fig1 boosts each input by a constant factor , and is thus a linear transformation . the probability information is therefore not subject to distortion due to renormalization . because sum - product circuits will normally be situated in a network , the . iterated behaviour of ( 20 ) should also be considered . this can be simplified to a one - dimensional problem by using a summary variable k for each set of probabilities , defined as k x ≡ ∑ i ⁢ ix i i u . ( 21 ) this allows the treatment of ( 20 ) as a simple one - dimensional transfer function , k out = n · m · k in n + m · k in . ( 22 ) iteration of ( 22 ) is illustrated in fig1 . the blocks 104 and 108 labeled ƒ n represent the transfer function ( 22 ), and are respectively connected to the outputs of the sum - product circuits 102 and 106 . to determine the dynamic behaviour of this system , the fixed points ( where k out = k in ) are identified , and a determination is then made as to whether they are stable . as those skilled in the art will appreciate , it can be shown that the fixed points occur at k 0 = 0 ⁢ ⁢ and ( 23 ) k 1 = n - n m . ( 24 ) it is well known that a fixed point is stable and non - oscillating if and only if the slope of the transfer function , ƒ ′ n ( k ), satisfies 0 ≦ ƒ ′ n ( k j )& lt ; 1 at the fixed point k ƒ . also , a fixed point k ƒ is unstable ( i . e . it is a repeller ) if and only if ƒ ′ n ( k ƒ )& gt ; 1 . it can also be shown that f n ′ ⁡ ( 0 ) = m ⁢ ⁢ and ( 25 ) f n ′ ⁡ ( k 1 ) = 1 m . ( 26 ) equations ( 25 ) and ( 26 ) show that there is always a stable fixed point above zero when m & gt ; 1 . known renormalizers use m = 1 , and therefore cause all currents to approach zero in a low - voltage network . by using m & gt ; 1 , this can be avoided . in a low - voltage design , use of a reset circuit is also preferred . an example of such a circuit is shown in fig1 , comprising transistors 112 , 114 , and 116 connected across inputs and outputs of a sum - product circuit 110 . the transistors 112 , 114 , and 116 provide for restoration of a sum - product network to an unbiased state when decoding of one block of information is complete . when the digital ‘ rst ’ signal in fig1 is high , all probabilities are shorted together at the inputs and outputs . of the sum - product circuit 110 , which may also be considered a local processing node . the transistors 112 , 114 , and 116 act as switches and are shown in fig1 as nmos transistors . after a short settling time , the ‘ rst ’ signal falls low again , the transistors 112 , 114 , and 116 become open switches , and the sum - product circuit 110 , as well as other such circuits connected in a network , is ready to process new information . reset circuits are well known in gilbert - based designs , having been studied , for example , in the phd theses of felix lichtenberger [ 11 ] and jie dai ( 4 ). their value seems debatable in canonical gilbert circuits . for low - voltage circuits as in fig9 . and other types of circuits that may have a stronger memory effect , the use of reset circuits is generally preferred . one very common class of decoders employ the bcjr algorithm . this algorithm is used with concatenated convolutional codes , such as turbo codes and turbo . equalizers . the bcjr algorithm [ 2 ] is a special case of the sum - product algorithm ( 1 ), as shown in [ 9 ]. in the bcjr algorithm , variables are often not binary . a trellis stage is a portion of a trellis graph which describes a boolean constraint function . the graph of a trellis stage consists of two columns of states , connected by branches . an example trellis stage is shown in fig1 a . the states on the left represent the possible values of a random state variable a . the states on the right represent branches represent the possible values of a branch variable , y . if a branch exists for a particular combination ( α i , y j , out k ), then the constraint is satisfied for that combination . an example of the low - voltage sum - product architecture for computing on trellis graphs is shown in fig1 b . as shown , the sum - product circuit comprises a renormalization module 122 having a plurality of transistor pairs 117 , 118 , 119 , 120 and a single column input transistor 121 , a connectivity module 124 , a plurality of multiplier modules 126 , 128 , 130 , 132 , a plurality of dummy multiplier modules 136 , 138 , 140 , 142 , and a plurality of column input transistors generally designated by 143 . the branch variable takes values from the set { a , b , c , d }. the sum - product equation for this particular trellis section can be written in matrix form as [ out0 out1 out2 out3 ] = [ a d b c c b d a ] × [ a0 a1 a2 a3 ] . ( 27 ) the particular trellis function is determined by the connectivity module 124 . the sum - product circuit is shown with the state probabilities as row inputs and the branch probabilities as column inputs , but these roles can be reversed without affecting the results . every stage of the bcjr algorithm consists of a matrix multiplication of the form ( 27 ). low - voltage sum - product circuits can therefore be easily produced to implement a complete bcjr decoder . decoders for binary ldpc codes are mapped from the code &# 39 ; s normalized tanner graph , which is a direct visualization of the code &# 39 ; s binary parity check matrix . the tanner graph contains two types of nodes , check nodes and variable nodes . a variable node denotes a particular bit in a codeword . a check node represents a parity check equation , which is a single row in the parity check matrix . all variables in the graph are binary . for implementations , this means that all probability masses will have only two components . fig1 a shows an example tanner graph that contains a variable node 150 and a plurality of check nodes 152 . in a normalized tanner graph ,, also known as a forney graph , equality nodes are inserted between variable nodes and check nodes [ 5 ]. this is illustrated in fig1 b , in which an equality node 156 is inserted between a variable node 154 and a plurality of cheek nodes 158 . the purpose of equality node insertion is to provide explicit representation for the constraint which occurs at variable nodes : all connected edges convey the same variable . let u i be the set of check nodes connected to variable i , and let u j be the binary value from check node j . the equality constraint is satisfied if and only if the check node is only slightly more complicated . let v j be the set of variables which are connected to check node j , and let v i be the value of variable i . parity check j is then satisfied if and only if ⊕ i ∈ v j ⁢ v i = 0 , ( 29 ) the constraints in ( 28 ) and ( 29 ) can be conveniently broken down into recursive operations , allowing , the construction of nodes with many edges by connecting 3 - edge nodes in a chain . this is illustrated in fig1 , for example , in which a 4 - edge node 160 is shown with an equivalent implementation as two 3 - edge nodes 162 and 164 . therefore , the construction of larger nodes using 3 - edge nodes will be apparent from the description of the implementation of 3 - edge nodes . for a 3 - edge check node , the constraint function is simply a logical xor operation . mapping this to a sum - product implementation , and labeling the three edges x , y , and z , we obtain . p ( z = 0 )= p ( x = 0 )· p ( y = 0 )+ p ( x = 1 )· p ( y = 1 ) ( 30 ) p ( z = 1 )= p ( x = 1 )· p ( y = 0 )+ p ( x = 0 )· p ( y = 1 ) ( 31 ) the proportionality symbol is used to indicate that the algorithm is invariant to multiplication by any non - zero normalizing constant . applying the general circuit of fig9 , and varying the connectivity to produce the appropriate functions , we arrive at the circuits of fig1 and 17 for a 3 - edge equality node and a 3 - edge check node , respectively . as above , the ‘ y ’ inputs are the column . inputs , and the ‘ x ’ inputs are the . row inputs . in fig1 and 17 , the transistors 172 , 174 , 176 , 178 and 192 , 194 , 196 , 198 form the multiplier modules , the transistors 184 , 186 and 204 , 206 are column input transistors , and the transistors 180 , 182 and 200 , 202 form the dummy multiplier modules . the renormalization module is not shown in fig1 and 17 , but is preferably present . complete decoders for linear binary block codes , including ldpc codes , can be constructed from these 3 - edge circuits . of course , as those skilled in the art will appreciate , conversion modules , voltage to current conversion modules in the example circuits shown in fig1 and 17 , may be provided between circuits where circuit outputs are to be converted for input to a next circuit . what has been described is merely illustrative of the application of the principles of the invention . other arrangements and methods can be implemented by those skilled in the art without departing from the spirit and scope of the present invention . for example , the invention is in no way limited to the particular implementations shown as illustrative examples in the drawings . alternate implementations , using different elements and / or different types of components , will be apparent to those skilled in the art . the invention may also be applied to other types of decoding . than the trellis and ldpc decoding described above . j . b . anderson and s . m . hladik . tailbiting map decoders . ieee journal on selected areas in communications , 16 ( 2 ) : 297 - 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