Patent Application: US-87503310-A

Abstract:
the disclosure relates to a method for generating uwb waveforms , each comprising a sequence of pulses , the method comprising : generating consecutive elementary pulses having durations corresponding to setpoint durations and a constant amplitude , amplifying each elementary pulse separately as a function of a respective setpoint amplitude , and combining the amplified elementary pulses to obtain a waveform successively comprising each of the amplified alternately positive and negative , elementary pulses .

Description:
a waveform s ( t ) may be split up into a series of n elementary pulses ei ( t ) of width ( or duration ) di and amplitude gi ( i varying from 1 to n ), in accordance with the following equation ( 1 ): fig1 a shows a waveform s ( t ) corresponding to the impulse response of a bandwidth bessel filter between 6 and 10 ghz . the values of amplitude gi and duration di of each elementary pulse i of the waveform s ( t ) are gathered in the following table 1 : fig1 b shows a waveform s ′( t ) corresponding to the fifth derivative of a gaussian pulse . the values of amplitude gi and duration di of each elementary pulse i of the waveform s ′( t ) are gathered in the following table 2 : fig2 shows a waveform generator pgn , according to one embodiment . in accordance with the principle for splitting up a waveform into elementary pulses , the waveform generator pgn comprises an elementary pulse generator epg comprising n inputs of setpoint signals of duration ve 1 , ve 2 , . . . ven , a trigger input vdec , and n outputs of elementary pulses e 1 , e 2 , e 3 , en each successively supplying an elementary pulse e 1 , e 2 , . . . en . each elementary pulse output is connected to an amplifier g 1 , g 2 , . . . gn . the output of each amplifier g 1 is connected to an input of an adder add . the adder add supplies an output signal s ( t ) for example to an antenna at . each signal ve 1 . . . ven defines a setpoint duration of one of the elementary pulses e 1 . . . en . each elementary pulse ei supplied by the generator epg is delayed in relation to an elementary pulse ei − 1 supplied by a previous output of the duration of the latter . thus , at time t0 , the generator epg supplies on a first output e 1 a first pulse e 1 ( t ) of duration t1 − t0 . at time t1 , the generator epg supplies on a second output e 2 a second pulse e 2 ( t − t1 + t0 ) delayed of t1 − t0 in relation to the first pulse e 1 ( t ). at time ti , the generator epg supplies on an output ei + 1 a pulse ei + 1 ( t − ti + t0 ) delayed of ti − ti − 1 in relation to the previous pulse ei and delayed of ti − t0 in relation to the pulse e 1 ( t ). each elementary pulse ei is then amplified by one of the amplifiers gi with a gain defined by an amplitude setpoint signal vai supplied in input of the amplifier . the setpoint signals va 1 . . . van may be positive or negative according to the — positive or negative — polarity of the elementary pulse to be generated . the output signals aei of the amplifiers g 1 are supplied in input of the adder add . it is to be noted that the elementary pulses supplied by the generator epg may all be of same sign , positive or negative , or alternately positive and negative . fig2 a shows the form of the signal s ( t ) obtained in output of the adder add . the combination of the elementary pulses ei ( t ) made by the adder add forms a continuous signal in which the amplified elementary pulses aei follow each other . the elementary pulses aei constituting the signal s ( t ) may be alternately positive and negative so as to generate a band - pass waveform without continuous component . fig3 shows an embodiment of the elementary pulse generator epg . the generator epg comprises a variable delay line vcdl controlled in voltage , logic gates ag 1 , . . . agi , . . . ag 2 n and output buffers bf 1 , . . . bfi , . . . bf 2 n . the delay line vcdl comprises delay cells dl 1 , . . . dli , . . . dl 2 n mounted in cascade . each cell dli receives one of the duration setpoint signals vei . a first cell dl 1 of the delay line vcdl receives the trigger signal vdec , which is propagated to the other cells dli of the delay line vcdl . each delay cell dli ( i varying from 1 to 2n − 1 ) supplies a signal ai to an input d of a gate agi and to an input c of another gate agi + 1 . the cell dl 2 n supplies a signal a 2 n only to the gate ag 2 n . each gate agi ( i varying from 1 to 2n ) combines the signals ai − 1 , ai in output of two consecutive cells dli − 1 , dli of the delay line vcdl , to form a digital elementary pulse si of duration equal to the value of the delay applied by the cell dli , the signal ao being equal to the signal vdec . each gate agi comprises an output si connected to an input of a buffer bfi . each buffer bfi of differential type comprises two complementary outputs supplying two signals ei , epi to the adder add , the signal epi being equal to the power supply voltage of the circuit minus the signal ei . each cell dli of the line vcdl may in addition receive an inhibition signal vdi allowing the cell to be inhibited if it is not used , in particular in order to reduce the electrical consumption . each gate agi may be an and gate or any other logic gate allowing two successive edges to be combined to form an elementary pulse . each buffer bfi may comprise several inverters in series to perform an adaptation between the sizes of the transistors forming the gates agi , which are small and rapid , and bigger transistors ( up to around 1000 times bigger ) of transmission gates of the adder add , so as to obtain at the buffer output a current sufficient to control the transmission gates of the adder . fig4 shows an adder add 1 according to the disclosure , which may be used to implement the adder add of fig2 . in fig4 , the adder add 1 forms an h - bridge with n = 2n branches to supply 2n elementary pulses . the adder add 1 comprises n branches connected to an output s + and n branches connected to an output s − of the adder . thus the adder add 1 comprises four groups of n transmission gates tgn 1 to tgn 2 n , tgp 1 to tgp 2 n mounted in parallel , each gate comprising a n - channel mos transistor m 1 connected in parallel with a p - channel mos transistor p 1 . the first group comprises the gates of odd rank tgn 1 to tgn 2 n − 1 which receive on one side the amplitude setpoint voltages va 1 to va 2 n − 1 respectively , and which are connected on the other side to the output s + of the adder add 1 . the gate of each transistor m 1 of the gates tgn 1 to tgn 2 n − 1 respectively receives one of the signals e 1 to e 2 n − 1 of odd rank , coming from the generator epg . the gate of each transistor p 1 of the gates tgn 1 to tgn 2 n − 1 of odd rank , respectively receives one of the signals ep 1 to ep 2 n − 1 of odd rank , coming from the generator epg . the second group comprises the transmission gates tgp 2 to tgp 2 n of even rank which are connected on one side to the output s +, and on the other side to the ground . the gate of each transistor m 1 of the gates tgp 2 to tgp 2 n of even rank , respectively receives the signals e 2 to e 2 n of even rank , coming from the generator epg . the gate of each transistor p 1 of the gates tgp 2 to tgp 2 n of even rank , respectively receives the signals ep 2 to ep 2 n of even rank . the third group comprises the gates tgn 2 to tgn 2 n of even rank , which receive on one side the amplitude setpoint voltages va 2 to va 2 n of even rank , respectively , and which are connected on the other side to the output s − of the adder add 1 . the gate of each transistor m 1 of the gates tgn 2 to tgn 2 n respectively receives the signals e 2 to e 2 n of even rank , coming from the generator epg . the gate of each transistor p 1 of the gates tgn 2 to tgn 2 n respectively receives the signals ep 2 to ep 2 n of even rank , coming from the generator epg . the fourth group comprises the gates tgp 1 to tgp 2 n − 1 of odd rank which are connected on one side to the output s −, and on the other side to the ground . the gate of each transistor m 1 of the gates tgp 1 to tgp 2 n − 1 of odd rank , respectively receives the signals e 1 to e 2 n − 1 of odd rank , coming from the generator epg . the gate of the transistors p 1 of the gates tgp 1 to tgp 2 n − 1 of odd rank , respectively receives the signals ep 1 to ep 2 n − 1 of odd rank , coming from the generator epg . the outputs s +, s − of the adder add 1 are connected to a load ld forming the antenna at . thus , the i th branch of the adder ( i varying from 1 to 2n ) is controlled by the signal ei and the complement eip thereof and the signal which goes through it is amplified as a function of the amplitude setpoint voltages vai . when an elementary pulse appears in the signals e 2 i − 1 and ep 2 i − 1 ( i varying from 0 to n ), the gates tgn 2 i − 1 and tgp 2 i − 1 of the branch b 2 i − 1 are conductive and a current i +( t ) proportional to the voltage va 2 i − 1 goes through the load ld of the antenna at , from the terminal s + to the terminal s −, thus producing an elementary pulse of amplitude substantially equal or proportional to the setpoint voltage va 2 i − 1 . then , when an elementary pulse appears in the signals e 2 i and ep 2 i ( i varying from 1 to n ), the gates tgn 2 i and tgp 2 i of the branch b 2 i are conductive and a current i −( t ) proportional to the voltage va 2 i and which polarity is opposite to the current i +( t ) goes through the load ld , from the terminal s − to the terminal s +, thus producing an elementary pulse of amplitude substantially equal or proportional to the setpoint voltage va 2 i , but with a polarity opposite to the previous elementary pulse . that way , elementary pulses of alternately positive and negative polarity follow each other in the waveform s ( t ). each elementary pulse of the signal s ( t ) having the duration of a corresponding elementary pulse generated by the generator epg . the waveform resulting from the combination of such elementary pulses has a band - pass spectrum , i . e . without continuous component if the following condition is verified : the adder add 1 which has just been described therefore performs both a weighing function ( amplification ) of each elementary pulse generated by the generator epg , with a gain which may differs from the amplification gain of the other elementary pulses , and a combination function of these elementary pulses to form the waveform s ( t ). fig5 shows the control data structure of the generator pgn . in fig5 , the data structure comprises 2n words mai corresponding to the digital values of the amplitude setpoint voltages vai fixing the amplitude of each elementary pulse forming the waveform s ( t ), 2n words vni corresponding to the digital values of the duration setpoint voltages vei fixing the width of these elementary pulses , and 2n bits di fixing the presence or absence of each inhibit voltage vdi of the cells dli . the generator pgn may then comprise digital to analog converters to convert these words into voltages va 1 . . . va 2 n , ve 1 . . . ve 2 n , vd 1 . . . vd 2 n . fig6 shows an embodiment of a cell dli of the delay line vcdl . each cell dli comprises two inverters i 1 , i 2 connected in series , and an inverter buffer bff 1 . the input of the inverter i 1 is connected to an input ip 1 of the cell dli provided to receive the signal vdec or be connected to a previous cell dli − 1 of the delay line vcdl . the output of the inverter i 1 is connected to the input of the buffer bff 2 and the input of the inverter i 2 . the output of the inverter i 2 is connected to the input of the buffer bff 1 and an output ip 2 of the cell dli provided to be connected to a following cell dli + 1 of the line vcdl . the output of the buffer bff 1 supplies the output signal ai of the cell dli . thus , the cell dli supplies on the output ip 1 thereof the signal applied in input ip 1 , delayed of a duration corresponding to the accumulated delays introduced by the inverters i 1 , i 2 . a buffer bff 2 identical to the buffer bff 1 may be provided to balance the load of the two inverters i 1 , i 2 . the two inverters i 1 , i 2 are also powered between the input of the signal vdi and the input of the signal vei . thus , if the inhibition voltage vdi is equal to the voltage vdd , the cell dli is not powered and therefore does not operate . fig7 shows an example embodiment of the inverters i 1 , i 2 . each inverter comprises two n - channel mos transistors m 4 , m 5 , a p - channel mos transistor and a capacitor c 1 . the transistors p 4 and m 4 are connected in series between the signal input vdi and the ground . the gates of the two transistors p 4 , m 4 are connected to the input of the inverter i 1 , i 2 . the drains of the transistors p 4 , m 4 are connected to the output of the inverter i 1 , i 2 , as well as the ground through the capacitor c 1 in series with the transistor m 5 . the gate of the transistor m 5 receives the signal vei . thus , the voltage vei modulates the current in the branch comprising the transistor m 5 and the capacitor c 1 , which modifies the propagation time of the signal in the inverter i 1 , i 2 . fig8 shows an example embodiment of the gates agi . in fig8 , each gate agi comprises two p - channel mos transistors p 2 , p 3 and two n - channel mos transistors m 2 , m 3 . the transistors p 2 and m 2 are mounted in series between the power supply source vdd of the circuit and the input d of the gate agi . the gates of the transistors p 2 and m 2 are connected to the input c of the gate agi . the drains of the transistors p 2 and m 2 are connected to the gates of the transistors p 3 , m 3 which are connected in series between the power supply source vdd and the ground . the drains of the transistors p 3 and m 3 are connected to the output e of the gate agi . the transistors p 2 and m 2 thus perform the logic function ( inverted c ) or d , and the transistors p 3 and m 3 form an inverter . the gate agi thus performs the logic function and c ( inverted d ) to form an elementary pulse of width tp between a rising edge in the signal supplied to the input c ( ai − 1 ) and a rising edge supplied to the input d ( ai ) of the gate agi , as shown in the chronograms of fig9 a . other types of gates agi may be provided according to the combination of edges to be made to form the elementary pulses , as shown by the chronograms of the signals c , d and e in fig9 a to 9d . thus , in fig9 a , each gate agi forms an elementary pulse of duration tp between a rising edge of the signal c and a rising edge of the signal d . each gate agi then performs the logic function c and ( inverted d ). in fig9 b , each gate agi forms an elementary pulse of duration tp between a rising edge of the signal c and a falling edge of the signal d . each gate agi then performs the logic function c and d . in fig9 c , each gate agi forms an elementary pulse between a falling edge of the signal c and a rising edge of the signal d . each gate agi then performs the logic function ( inverted c ) and ( inverted d ), equivalent to the logic function ( c or d ) inverted . in the example of fig9 d , each gate agi forms an elementary pulse between a falling edge of the signal c and a falling edge of the signal d . each gate agi then performs the logic function ( inverted c ) and d . fig1 a , 10 b , 11 a , 11 b are curves showing the operation of the waveform generator . fig1 a shows as a function of time a waveform cv 1 formed by elementary pulses generated and combined by the generator pgn . fig1 b shows the spectrum cv 2 of the waveform cv 1 and a transmission mask cv 3 , for example defined by a transmission standard . the transmission mask defines as a function of the frequency , the maximum average power spectral density in dbm / mhz for the transmission signals not to exceed . at frequencies lower than 5 ghz , the average power spectral density cv 2 is higher than the mask cv 3 and therefore is higher than the authorized limit . fig1 a shows as a function of time elementary pulses cv 4 generated and combined by the generator pgn . the elementary pulses of curve cv 4 are substantially identical to those of curve cv 1 except for the fifth elementary pulse which is slightly weakened ( at around − 0 . 3 v in fig1 a instead of − 0 . 5 v in fig1 a ). fig1 b shows the mask cv 3 and the spectrum cv 5 of the waveform cv 4 . it appears in fig1 b that the modification of the fifth elementary pulse allows a spectrum of waveform cv 5 located substantially below the mask cv 3 to be obtained . it may also be noted that the width of the elementary pulses cv 4 has been reduced in relation to that of the elementary pulses cv 1 , which has the effect of widening the bandwidth of the waveform cv 4 ( around 7 . 5 ghz in the spectrum cv 5 ) in relation to the waveform cv 1 ( around 5 ghz in the spectrum cv 2 ). in the adder add 1 shown in fig4 , the use of transmission gates tgnj and tgpj ( j varying from 1 to 2n ) allows good performances to be obtained in terms of dynamics of the signal s ( t ) obtained . however , other transmission gates may be used . thus , fig1 shows an adder add 2 according to another embodiment , which may be used to implement the adder add of fig2 . the adder add 2 differs from the adder add 1 in that each transmission gate tgnj is replaced by a simple p - channel mos transistor p 1 and each gate tgpj is replaced by a simple n - channel mos transistor m 1 . the introduction of control signals e 1 . . . e 2 n and ep 1 . . . ep 2 n into the adder add 2 thus appears simplified in relation to that of the adder add 1 . however , this simplification causes a dissymmetry in these control signals , and therefore risks of apparition of glitches which may impair the waveform quality in the output signal s ( t ). the voltages of vei , vdi and vai may be supplied by digital to analog converters receiving commands in the form of digital values . however , a significant current ( several dozens of ma ) may pass through the branches of the adder add 1 , add 2 . the result is that the voltages vai may generally not be supplied by standard digital to analog converters . so as to be able to use standard digital to analog converters to generate amplitude setpoint voltages vai , the adder may be modified in accordance with fig1 . thus , fig1 shows an adder add 3 , which may be used to implement the adder add of fig2 , and which differs from the adder add 1 in that the amplitude setpoint voltages vai are supplied to the branches of the adder in differential form by two complementary voltages vai , vapi , through mos transistors p 6 , m 6 . thus , the amplitude setpoint voltages vapi ( i varying from 1 to 2n ) are supplied to the gates of the p - channel mos transistors p 6 which sources receive the power supply voltage vdd of the circuit , and the drains are respectively connected to the transmission gates tgni . the amplitude setpoint voltages vai ( i varying from 1 to 2n ) are supplied to the gates of the n - channel mos transistors m 6 which sources are connected to the ground , and the drains are respectively connected to the transmission gates tgpi . each pair of complementary amplitude setpoint voltages vai and vapi ( i varying from 1 to 2n ) is generated by a digital to analog converter cnai receiving in input a control word mai , the voltage vapi being equal to the power supply voltage vdd minus the voltage vai . that way , the current in a branch of the adder add 3 is proportional to the voltage vai applied to the gate of the transistor p 6 of the branch and to the voltage vapi applied to the gate of the transistor m 6 of the branch . the adder add 3 may thus be controlled using digital to analog converters which are not necessarily sized to supply a significant current . in order to increase the output signal dynamics , the transistors p 6 and m 6 may be associated to another transistor m 6 ′ or p 6 ′ so as to form transmission gates . thus , fig1 shows an adder add 4 according to another embodiment , which may be used to implement the adder add of fig2 . the adder add 4 differs from the adder add 3 in that the transistors p 6 and m 6 are replaced by transmission gates , each comprising a transistor p 6 receiving on the gate thereof the amplitude setpoint voltage vapi and a transistor m 6 receiving on the gate thereof the amplitude setpoint voltage vai . other embodiments of the adder may be considered by replacing only the transistors m 6 or only the transistors p 6 of the adder add 3 by transmission gates . in order to perform bipolar or biphase modulations , the generator pgn which has just been described may generate bipolar waveforms or waveforms of opposite polarities , i . e . comprising a same number of elementary pulses , each elementary pulse in one of the waveforms having the same amplitude and a polarity opposite to the elementary pulse of same rank in the other waveform . the so - called “ positive ” waveform starts by a positive elementary pulse and the so - called “ negative ” waveform starts by a negative elementary pulse . to that end , the control voltages of the positive elementary pulses and those of the negative elementary pulses must be shifted by a branch of the adder . thus , a positive waveform is generated by successively applying the amplitude setpoint voltage va 1 to the branch b 1 , va 2 to the branch b 2 , then generally , vai to the branch b 1 , and finally van to the branch b 2 n . to generate a negative waveform , an amplitude setpoint voltage of 0 v is introduced into the branch b 1 , then the voltage va 1 is applied to the branch b 2 , then more generally , the amplitude setpoint voltage vai is applied to the branch bi + 1 . thus the generation of a negative waveform introduces a delay equal to the delay t1 − t0 corresponding to the first elementary pulse at 0 v generated by the first branch b 1 of the adder . fig1 a to 15d are chronograms of signals of the generator pgn showing the generation of bipolar waveforms . fig1 a shows a digital data signal dt to be transmitted comprising a 1 followed by a 0 . fig1 b shows an amplitude setpoint signal vai in output of one of the digital to analog converters cnai . fig1 c shows the trigger signal vdec and fig1 d shows the signal s ( t ) in output of the adder . the signal vdec comprises two rising edges f 1 , f 2 to t0 ′ and t0 which each triggers the generation of a waveform ps 1 , ps 2 consisting of a sequence of 4 elementary pulses . the waveforms ps 1 and ps 2 are in opposite phase , the waveform ps 1 being positive ( starting by a positive elementary pulse ) to transmit the data at 1 of the signal dt . the waveform ps 2 is negative ( starting by a negative elementary pulse ) to transmit the data at 0 of the signal dt . the waveform ps 2 is generated only from the instant t1 after t0 , upon the activation of the second branch b 2 of the adder . fig1 shows an elementary pulse generator epg 1 , according to another embodiment . the generator epg 1 is modified so as to suppress the time shifting t0 − t1 which may induce lines in the spectrum of the waveforms generated and which may impair the quality of the signal . to that end , the circuit epg 1 differs from the circuit epg in that it comprises a modified trigger signal input to delay by t1 − t0 the generation of the positive waveforms in relation to the negative waveforms . thus , the generator epg 1 comprises a trigger signal input vdec 1 to trigger the generation of a positive waveform and a trigger signal input vdec 0 to trigger the generation of a negative waveform . the generator epg 1 also comprises an additional delay cell dl 0 receiving the trigger signal vdec 1 , a duration setpoint signal ve 0 and an inhibition control signal vd 0 . the output ip 2 ( fig6 ) of the cell dl 0 is connected to an input of a logic gate og of or type another input of which receives the trigger signal vdec 0 . the output of the gate og is linked to the input ip 1 ( fig6 ) of the cell dl 1 . the signals vdec 0 and vdec 1 correspond for example to signals for controlling the emission of a binary data dt at 0 and at 1 . when a waveform of positive polarity must be generated , the duration setpoint signal ve 0 is equal to the signal ve 1 of the first elementary pulse of the waveform and a triggering pulse appears in the signal vdec 1 . the cells dl 0 and dl 1 receive the duration setpoint signal ve 1 and more generally , the cell dli receives the duration setpoint signal vei . in addition , the branch b 1 of the adder receives the amplitude setpoint signal va 1 ( or va 1 and vap 1 ) and more generally the branch bi of the adder receives the amplitude setpoint signal vai ( or vai and vapi ). when a negative waveform must be generated , a triggering pulse appears in the signal vdec 0 . the cells dl 1 and dl 2 receive the duration setpoint signal ve 1 and more generally , the cells dli receive the duration setpoint signal vei − 1 . in addition , the branch b 1 of the adder receives an amplitude setpoint signal at 0 v . the branch b 2 of the adder receives the amplitude setpoint signal va 1 ( or va 1 and vap 1 ) and more generally the branch bi + 1 of the adder receives the amplitude setpoint signal vai ( or vai and vapi ). that way , the initial delay with which the positive waveforms are generated is equal to the initial delay necessary for the generation of the negative waveforms . the generator epg 1 may then comprise an additional set ( or more ) of a delay cell dl 2 n + 1 , a gate ag 2 n + 1 and a buffer bf 2 n + 1 . during the generation of a negative waveform , the delay cell dl 2 n + 1 receives the signal ve 2 n and the buffer bf 2 n + 1 supplies the signals e 2 n + 1 and ep 2 n + 1 . likewise , the adder may comprise an additional branch b 2 n + 1 ( or more ) receiving the amplitude setpoint signals va 2 n ( or va 2 n and vap 2 n ), as well as the signals e 2 n + 1 and ep 2 n + 1 , during the generation of a negative waveform . it is to be noted that the generator epg , epg 1 does not necessarily comprise an even number of outputs and the adder add , add 1 , add 2 , add 3 , add 4 does not necessarily comprise an even number of branches , these numbers may also be odd , given that the waveforms generated do not necessarily comprise an even number of elementary pulses . in that case , the adder may comprise an odd branch more than the even branches . however , the number of even branches may be maintained equal to the number of odd branches in order to balance the loads . the unused branches may be controlled by applying thereto a signal vai at 0 . the waveform generator pgn which has just been described has a limitation in terms of maximal number of elementary pulses which it may combine to generate a waveform . this limitation results from the length of the connections between the branches of the adder add , add 1 - add 4 and the nodes s + and s −. the length of these interconnections is proportional to the number of branches of the adder , corresponding to the number of maximum elementary pulses to be combined . the length of these interconnections limits the maximum frequency of the pulses susceptible of being produced by the generator epg . now the narrower the bandwidth of the waveforms to be generated is , the higher the number of elementary pulses required for the generation thereof . the minimum number nm of elementary pulses necessary to generate a waveform s ( t ) depends on the central frequency f0 of the waveform and the bandwidth bw of the latter in accordance with the following equation : some examples of values of f0 , bw and nm are given in the following table 3 : fig1 shows a generator pgn 1 , according to another embodiment . the generator pgn 1 comprises an elementary pulse generator bbg and an adder add 5 supplying a signal s ( t ) to an antenna at . the generator bbg comprises an elementary pulse generation circuit ffa receiving a trigger signal vdec and a control word vn . the circuit ffa is configured to supply a stream of odd elementary pulses e 1 ( t ), e 3 ( t ), . . . on an output e 1 , and a stream of even elementary pulses e 2 ( t ), e 4 ( t ), . . . on an output e 2 , the elementary pulses having a substantially fixed amplitude and alternately appearing in the two pulse streams at a fixed frequency defined by a control word vn . the generator bbg also comprises a control voltage generation circuit agn receiving a first series of n control words ma 11 to ma 1 n respectively defining setpoint amplitudes of odd or positive elementary pulses to be successively generated , and a second series of n control words ma 21 to ma 2 n respectively defining setpoint amplitudes of even or negative elementary pulses to be successively generated . the circuit agn is configured to supply on two outputs v 1 , v 2 , voltages corresponding to the amplitudes of the elementary pulses supplied by the circuit ffa . at any time , the signal v 1 defines the amplitude of a common elementary pulse appearing at the output e 1 , and the signal v 2 defines the amplitude of a common elementary pulse appearing at the output e 2 . the outputs e 1 , e 2 , v 1 , v 2 are connected to the adder add 5 . thus , the adder add 5 receives at the same time an elementary pulse through one of the outputs e 1 , e 2 and the amplitude of this pulse through the corresponding output v 1 or v 2 . at a time t0 , the circuit agn receives the trigger signal vdec and supplies on the output v 1 a signal at the voltage va 1 corresponding to the control word ma 11 , and the circuit ffa supplies on the output e 1 a pulse e 1 ( t ) of duration t1 − t0 . between the times t0 and t1 , the circuit agn brings the voltage at the output v 2 to va 2 corresponding to the control word ma 21 . at time t1 , the circuit ffa supplies on the output e 2 a pulse e 2 ( t ) of duration t2 − t1 . between the times t1 and t2 , the circuit agn supplies on the output v 1 a signal at the voltage va 3 corresponding to the control word ma 12 . at time t2 , the circuit ffa supplies on the output e 1 a pulse e 3 ( t ) of duration t3 − t2 . between the times t2 and t3 , the circuit agn brings the voltage at the output v 2 to a voltage va 4 corresponding to the control word ma 22 . at time t3 , the circuit ffa supplies on the output e 2 a pulse e 4 ( t ) of duration t4 − t3 . the adder add 5 receives and combines the signals v 1 , v 2 , e 1 , e 2 so as to supply a waveform s ( t ) successively comprising the pulses e 1 , e 2 , e 3 and e 4 which have a same duration corresponding to the control word vn , and respective amplitudes va 1 , − va 2 , va 3 and − va 4 , as shown in fig1 a which shows a chronogram of the signal s ( t ). in other words , the adder add 5 combines the signals of v 1 , e 1 so as to supply the positive , odd elementary pulses e 1 , e 3 , in the waveform s ( t ), and combines the output signals v 2 , e 2 so as to supply the negative or even elementary pulses e 2 , e 4 in the waveform s ( t ). it is to be noted that the number of odd elementary pulses making the waveform is not necessarily equal to the number of even elementary pulses , and may be equal to n + 1 while the number of even elementary pulses is equal to n . fig1 shows the elementary pulse generation circuit ffa , according to one embodiment . the circuit ffa comprises a digital to analog converter cna 13 , an oscillator osc for example of the type voltage controlled oscillator with differential output , a counting circuit cpt and a triggering management circuit omt . the converter cna 13 receives a voltage control word vn and outputs a control voltage vt to a control input vct 1 of the frequency of the oscillator osc . the circuit omt comprises an input receiving the trigger signal vdec and two outputs supplying to the oscillator osc a reset signal r and an on / off control signal on . the oscillator osc comprises two complementary outputs cmd −, cmd +, each connected to a buffer bff 4 , bff 5 . the signal at the output cmd − is equal to the power supply voltage of the circuit vdd minus the signal at the output cmd +. the signals at the outputs cmd − and cmd + are therefore in phase opposition . the buffers bff 4 , bff 5 supply the signals e 1 , e 2 . the signals e 1 and e 2 are therefore also in phase opposition . each buffer bff 4 , bff 5 may comprise several inverters in series to perform an adaptation between the sizes of the transistors making the oscillator osc and bigger transistors ( up to around 1000 times bigger ) of transmission gates making the adder add 5 , so as to obtain at the output of the buffer a current sufficient to control the transmission gates of the adder . the counter cpt is clocked by one or the other signal e 1 , e 2 , for example the signal e 2 , and comprises a trigger input onf and a reset input rst , both receiving the signal on at the output of the circuit omt . the counter cpt supplies a carry signal cry to the circuit omt when it reaches a maximum number and returns to 0 . the value of the counter cpt is fixed to n , 2n being the number of elementary pulses to be generated . the circuit omt comprises for example a logic gate receiving in input the signals vdec and cry and supplying the signal on for example equal to vdec and ( inverted cry ). the signal r may be generated from the signal cry and delay lines defining a first delay between the apparition of the signal cry and the setting to 1 of the signal r and a second delay defining the duration during which the signal r remains at 1 . it is to be noted that the set formed by the oscillator osc and the converter cna 13 may be replaced by a digitally controlled oscillator nco . fig1 shows the voltage generation circuit agn , according to one embodiment . the circuit agn receives in input the bits 1 to p of the n control words ma 11 to ma 1 n and the n control words ma 21 to ma 2 p . the circuit agn comprises two sets rsr 1 , rsr 2 of p shift registers , and two digital to analog converters cna 11 , cn 12 . each shift register comprises n flip - flops ff for example of d type . each set rsr 1 , rsr 2 successively receives in input through switches it ( one switch per shift register ) the bits ( from 1 to p ) of the words ma 11 . . . ma 1 n or ma 21 . . . ma 2 n . the series of words ma 11 . . . ma 1 n introduced into the set rsr 1 fixes the amplitudes of n odd or positive elementary pulses , and the series of words ma 21 . . . ma 2 n introduced into the set rsr 2 fixes the amplitudes of n even or negative elementary pulses . the outputs v 11 to v 1 p or v 21 to v 2 p of each of the two sets of registers rsr 1 , rsr 2 are connected to a terminal of the switches it and to inputs in 1 to inp of one of the two converters cna 11 , cna 12 . the flip - flops ff of the set of shift registers rsr 1 receiving the control words ma 1 j are clocked by a clock signal ck , or by the signal e 2 at the output of the circuit ffa , the signal clocking the flip - flops being selected by a switch it 1 . the flip - flops ff of the set of shift registers rsr 2 receiving the control words m 2 j are clocked by the clock signal ck , or by the signal e 1 at the output of the circuit ffa , selected by a switch it 1 . the number of flip - flops ff of the shift registers of each of the sets rsr 1 , rsr 2 corresponds to the maximum number of elementary pulses , respectively odd and even , to be generated to form the waveform s ( t ). the converter cna 11 of differential type comprises two outputs supplying complementary voltages v 1 , v 1 p . the voltage v 1 corresponds to the digital value defined by the bits v 11 . . . v 1 p and the voltage v 1 p is equal to the power supply voltage of the circuit vdd minus the voltage v 1 . the converter cna 12 also of differential type , comprises two outputs supplying complementary voltages v 2 , v 2 p . the voltage v 2 corresponds to the digital value defined by the bits v 21 . . . v 2 p and the voltage v 2 p is equal to the power supply voltage of the circuit vdd minus the voltage v 2 . during an initialization phase , the switches it , it 1 are in position 1 to load the shift registers rsr 1 , rsr 2 with the bits ( from 1 to p ) of the two series of n control words ma 11 to ma 1 n and ma 21 to ma 2 n at any clock frequency ck . at the end of the initialization phase , the shift registers rsr 1 , rsr 2 contain all the digital values of the amplitudes of the elementary pulses to be generated to form a waveform . in an operating phase , the switches it , it 1 are in position 2 so as to loop the output on the input of the shift registers , and to clock the latter by the signals e 1 , e 2 . at the end of n falling edges in each of the signals e 1 , e 2 , 2n elementary pulses have been generated and the shift registers are back to their initial values , ready to generate another identical waveform in the signal s ( t ). thus during the operating phase , the signal v 1 is successively equal to the setpoint amplitudes va 1 , va 3 , . . . va 2 i − 1 , . . . of the odd pulses , and changes value at each rising edge of the signal e 1 . likewise , the signal v 2 is successively equal to the setpoint amplitudes va 2 , va 4 , . . . va 2 i , . . . of the even pulses , and changes value at each rising edge of the signal e 2 . fig2 shows the adder add 5 , according to one embodiment . the adder add 5 comprises a h - bridge with two branches , i . e . four half branches , two of which are connected between the power supply voltage source vdd and connection terminals s +, s − for connecting to the antenna at , and two of which are connected between the terminals s +, s − and the ground . each half branch comprises two transmission gates tg 11 to tg 14 and tg 21 to tg 24 connected in series , each gate comprising a p - channel mos transistor p 10 and an n - channel mos transistor m 10 . the terminals s + and s − are also linked to the ground through switches it 2 controlled by the signal r . a first half branch comprising the gates tg 11 and tg 12 in series is connected between the power supply voltage source vdd and the terminal s + of the antenna at . a second half branch comprising the gates tg 13 and tg 14 in series is connected between the terminal s − and the ground . the transistor m 10 of the gates tg 12 and tg 13 receives on the gate thereof the voltage e 1 , and the transistor p 10 of the gates tg 12 and tg 13 receives on the gate thereof the voltage e 2 . the transistor m 10 of the gates tg 11 and tg 14 receives on the gate thereof the voltage v 1 , and the transistor p 10 of the gates tg 11 and tg 14 receives on the gate thereof the voltage v 1 p . a third half branch comprising the gates tg 21 and tg 22 in series is connected between the power supply voltage source vdd and the terminal s −. a fourth half branch comprising the gates tg 23 and tg 24 in series is connected between the terminal s + and the ground . the transistor m 10 of the gates tg 22 and tg 23 receives on the gate thereof the voltage e 2 , and the transistor p 10 of the gates tg 22 and tg 23 receives on the gate thereof the voltage e 1 . the transistor m 10 of the gates tg 21 and tg 24 receives on the gate thereof the voltage v 2 , and the transistor p 10 of the gates tg 21 and tg 24 receives on the gate thereof the voltage v 2 p . the first and second half branches form a branch b 1 which is conductive when the signals v 1 and e 1 are near the power supply voltage vdd and when the signals v 1 p and e 2 are near 0 v . the third and fourth half branches form a branch b 2 which is conductive when the signals v 2 and e 2 are near the power supply voltage vdd and when the signals v 2 p and e 1 are near 0 v . as the signals e 1 and e 2 are in phase opposition , the duration of the elementary pulses in output of the adder add 5 is therefore equal to half the oscillation period of the oscillator osc . in addition , as the shift registers rsr 1 , rsr 2 are clocked by the signals e 1 and e 2 , the signals v 1 , v 1 p are synchronous with the signal e 1 , and the signals v 2 , v 2 p are synchronous with the signal e 2 . the signals v 1 , v 1 p , v 2 , v 2 p define the amplitude of the elementary pulses generated in the waveform s ( t ) and the signals e 1 , e 2 define the duration of these pulses . at the end of the generation of a waveform in the signal s ( t ), the signal r controls the closing of the switches it 2 to unload the h - bridge of the adder add 5 . the signal r is such that it closes the switches it 2 sometimes after the oscillator osc stopping to take into account the propagation time of the signals in the circuits of the generator pgn 1 . it is to be noted that the adder may also be of the type shown in fig4 with only two branches receiving the voltages v 1 and v 2 and a transmission gate per half branch receiving the signals e 1 , e 1 p or e 2 , e 2 p . fig2 shows the control data structure of the generator pgn 1 . the control data of the generator pgn 1 comprise the series of control words ma 11 to ma 1 n , ma 21 to ma 2 n fixing the amplitudes of the n odd elementary pulses and the n even elementary pulses generated in the resulting signal s ( t ), and the control word vn fixing the duration of these 2n elementary pulses . fig2 a to 22e show variation curves as a function of time of different voltages in the generator pgn 1 . these curves have been obtained with series of control words ma 11 to ma 16 and ma 21 to ma 26 such that they define respective setpoint amplitudes equal to 0 , 0 . 6 , 1 . 2 , 1 . 2 , 0 . 7 , 1 . 2 , 1 . 2 , 0 . 7 , 0 . 6 , 0 . 5 , 0 . 4 and 0 . 3 for twelve elementary pulses , the words ma 11 . . . ma 16 defining the amplitudes of the odd elementary pulses , and the words ma 21 . . . ma 26 defining the amplitudes of the even elementary pulses . fig2 a show variation curves of the voltages of the control signals cmd + and cmd −. each signal cmd +, cmd - comprises a stream of six pulses of same amplitudes and having the form of a positive square signal and which duration is equal to around 70 ps . during these pulse streams , the signals cmd + and cmd − are in phase opposition . fig2 b show variation curves of the voltages of the signals e 1 , e 2 . each signal e 1 , e 2 comprises a stream of six pulses substantially of same amplitude ( with a possible difference of 10 %) and are in phase opposition . the pulses of the signal e 1 are substantially synchronous with the pulses of the signal cmd + with a possible difference of half a period of the signal cmd + or cmd −, this delay being due to the propagation time of the signals in the inverters . the form of the pulses of the signals e 1 , e 2 is rounded in relation to the signals cmd + and cmd − due to the presence of the buffers bff 4 , bff 5 . fig2 c show variation curves of the voltages of the signals v 1 , v 2 . each signal v 1 , v 2 comprises a sequence of six voltage steps , these two signals being shifted one in relation to the other of around half a period of the signal cmd + or cmd −. fig2 d shows the form of the signals s + and s − at the output terminals of the adder add 5 . each signal s + and s − comprises a stream of positive pulses of variable amplitude and shifted one in relation to the other of half a period of the signal cmd + or cmd −. fig2 e shows the signals r , on and s ( t ). the signal on is at 0 v except during the period where pulses are present in the signals cmd − and cmd + where it is at the voltage vdd . the signal r is at 0 v during the period where the signal on is at vdd , and switches to vdd during a certain duration when the signal on is at 0 v . the signal s ( t ) comprises a sequence of pulses comprising pulses corresponding in duration and amplitude to the pulses of the signal s +, and pulses corresponding in duration and amplitude to the pulses of the signal s − but reverted . the signal r opens the switches it 2 , and the signal on goes to 1 . the oscillator osc starts and starts supplying signals cmd +, cmd − different from zero . in parallel , the shift registers rsr 1 , rsr 2 supply voltages v 1 , v 2 , v 1 p , v 2 p different from zero while elementary pulses are generated in the signals e 1 , e 2 . after the generation of the twelve elementary pulses , the counter cpt supplies a counting end signal cry which causes the signal on to go to 0 and therefore the oscillator osc to stop . after some times , corresponding to the propagation time of the pulses in the circuits , the signal r goes to 1 to control the switches it 2 and thus unload the h bridge of the adder add 5 . it may be noted in fig2 e that the signal s ( t ) obtained comprises eleven elementary pulses ( the first elementary pulse having a setpoint amplitude equal to 0 ), alternately negative and positive , and having amplitudes substantially equal to those mentioned above . the amplitude difference which may be observed between the setpoint amplitudes and the amplitudes obtained is not strictly linear . it may be observed that these nonlinearities are all the more important that the generator operates at high frequency ( higher than 3 ghz ), but may be reduced using a more efficient technology for manufacturing integrated circuits . in addition , the possibility of acting on the amplitude of each elementary pulse may be taken advantage of to compensate these nonlinearities , without penalizing the operation of the generator . this possibility may also be taken advantage of to compensate variations of operation features of the integrated circuit in which the generator is made , resulting from variations pvt ( manufacturing conditions of the circuit , power supply voltage of the circuit , operating ambient temperature of the circuit ). it is to be noted that the adder may comprise more branches , for example 4 or 6 , or more generally b branches . if the adder comprises b branches , the circuit agn may comprise b sets of shift registers receiving b sets of control words ma 11 . . . ma 1 n to mab 1 . . . mabn , and as many analog to digital converters cna 11 to cna 1 b supplying pairs of complementary voltages v 1 , v 1 p to vb , vbp . the frequency of the oscillator osc is then adjusted to 1 /( b · tp ), where tp is the duration of the elementary pulses . the oscillator supplies b signals e 1 to eb having phases uniformly distributed on a period of the oscillator . so as to generate bipolar waveforms in the signal s ( t ), i . e . successively and alternately starting by a positive and negative elementary pulse , the generator pgn 1 may be modified so that the first elementary pulse may be generated as one chooses in the branch b 1 or the branch b 2 of the adder add 5 . to that end , the generator pgn 1 comprises an elementary pulse generation circuit ffa 1 as shown in fig2 . the circuit ffa 1 differs from the circuit ffa in that it comprises an additional control logic circuit cmlc and counting logic circuit cplc . the circuit cmlc is configured to direct the complementary outputs cmd + and cmd − of the oscillator osc to complementary outputs e 1 and e 1 p or e 2 and e 2 p depending on whether a negative or positive waveform is to be generated . the polarity of the waveform to be generated is defined by a polarity control signal pb . the circuit cmlc implements the following truth table : the circuit cmlc supplies through buffers , for example two buffers of differential type bff 6 , bff 7 , two pairs of complementary signals e 1 , e 1 p and e 2 , e 2 p . the circuit cplc makes it possible to select as a function of the signal pb among the signals cmd + or cmd −, the signal which falling edges trigger a counting of the counter cpt . thus , the circuit cplc supplies at the counting input of the counter cpt the signal cmd − if the signal pb is at 0 and the signal cmd + if the signal pb is at 1 . fig2 shows the adder add 5 and in particular its connection mode for connecting to the circuit ffa 1 . the connection mode of the circuit ffa 1 for connecting to the adder add 5 differs from that shown in fig2 in that the gate of the transistor m 10 of each gate tg 12 , tg 13 receives the signal e 1 , the gate of the transistor p 10 of each gate tg 12 , tg 13 receives the signal e 1 p , the gate of the transistor m 10 of each gate tg 22 , tg 23 receives the signal e 2 , and the gate of the transistor p 10 of each gate tg 22 , tg 23 receives the signal e 2 p . the connection mode of the adder add 5 for connecting to the circuit agn remains unchanged ( like in fig2 ), but the circuit agn is modified to comprise a circuit of the type cmlc allowing the signals v 1 , v 1 p to be replaced by the signals v 2 , v 2 p and vice versa , during the generation of a negative waveform . that way , depending on the polarity of the waveform to be generated , during the generation of the first elementary pulse , the signals e 1 , e 1 p correspond either to the signals cmd +, cmd −, or to the signals cmd −, cmd + and inversely for the signals e 2 , e 2 p . the result is that the first elementary pulse of the waveform is generated either by the first branch producing a positive elementary pulse , or by the second branch of the adder add 5 producing a negative elementary pulse . instead of providing a circuit of the type cmlc which may introduce differences between the positive and negative pulses , it may be provided to duplicate the number of shift registers at the input of the analog to digital converters , with a set of registers being provided for the positive pulses and a set of registers for the negative pulses . switches may also be provided for selecting one of the two sets of registers as a function of the polarity of the waveform to be generated . the generators pgn , pgn 1 are adapted to the compensation of the variations pvt . two compensation techniques may be implemented , separately or combined . a first technique consists in performing a calibration at manufacture output . this calibration consists in listing all the waveforms to be generated for a given application and determining the control words allowing each waveform to be obtained . a second technique consists in performing a dynamic calibration of the generator , during the operation thereof , so as to maintain sufficient performances , for example a maximum error rate on the bits ( teb ) as a part of a data transmission . fig2 shows a calibration system comprising an external memory emem , an internal memory imem , a set cnas of digital to analog converters cna 1 , cna 2 , . . . cnal , a waveform generator pgn 2 , a delay line dlg , a test calculator tstc and a logic gate of or type og 1 . the generator pgn 2 may be the generator pgn or pgn 1 according to one of the embodiments previously described . in the case of the generator pgn 1 , the converters cna 1 . . . cnal are those of the generator . the memory emem comprises an output of read data connected to an input of data to be written in the memory imem . the memory imem comprises an output of read data connected to respective inputs of the converters cna 1 . . . cnal . each converter cna 1 . . . cnal supplies an amplitude setpoint voltage to the generator pgn 2 . the generator pgn 2 supplies a signal s ( t ) to the calculator tstc . the calculator tstc supplies the trigger signal vdec to the generator pgn 2 , and signals tnk , tk indicating if a test is positive or negative . the output tnk is connected to an input of the gate og 1 and an erase signal input er of the memory imem . the output tk is connected to an input of the gate og 1 and a read or write address incrementation input of the memory imem . the output of the gate og 1 is connected to an input of the delay line dlg and a read address incrementation input of the memory emem . the memory emem memorizes all the possible values of sets of control words such as shown in fig5 or 21 , according to the embodiment of the generator pgn 2 . according to a calibration procedure , the values of a first set of these control words at a first read address are transferred to the memory imem at a first address . the different values of the control words transferred to the memory imem are transmitted to the converters cna 1 . . . cnal . the analog values produced by the converters are transmitted to the corresponding inputs of the generator pgn 2 . after the calculator tstc triggering the generator pgn 2 thanks to the signal vdec , the signal s ( t ) coming from the generator pgn 2 is transmitted to the calculator tstc which analyzes the signal s ( t ). the calculator tstc compares the features of the signal s ( t ) to an ideal signal by applying compliance criteria . these criteria may be of temporal or spectral order and correspond to the needs of an application ( for example compliance of the spectrum of the signal s ( t ) in relation to a standard ). if the signal s ( t ) does not comply with the criteria , the signal tnk is active , causing the erasure of the set of control words at the read address of the memory imem . if the signal s ( t ) complies with the criteria , the calculator tstc activates the signal tk , causing the incrementation of the read address of the memory imem . the result is that the last set of control words transferred to the internal memory imem is kept . the activation of the signal tk or tnk triggers the incrementation of the read address of the memory emem to read a following set of control words and transfer it to the memory imem , either at the address of the previous set of control words , erased if the corresponding signal s ( t ) does not comply , or to a following address , and the putting the memory imem in write mode through the delay line dlg . at the end of the calibration procedure , the memory imem memorizes all the control words allowing a signal s ( t ) complying with the compliance criteria to be obtained . the values of a single set of control words may be retained at the end of the calibration procedure , by selecting the set of control words giving the best result , for example the one which makes it possible to obtain the most powerful signal . the memory imem may then be reduced to a single register able to memorize one or two sets of control words . a dynamic calibration may also be performed for example as a part of a data transmission between a transmitter and a receiver , to guarantee a maximum quality of service qos . thus , fig2 shows a data transmission system implementing the generator pgn 2 . the transmission system comprises two devices dev 1 , dev 2 , each comprising a data transmitter tx 1 , tx 2 and a data receiver rx 1 , rx 2 configured to receive data emitted by the transmitter tx 1 , tx 2 of the other device . the transmitter tx 1 and the receiver rx 1 are connected to an antenna at . likewise , the transmitter tx 2 and the receiver rx 2 are connected to an antenna at 1 . at least the transmitter tx 1 comprises the generator pgn 2 according to one of the embodiments previously described , connected to the antenna at , and in the case of the generator pgn , the set of digital to analog converters cnas connected between the memory imem and the generator pgn 2 . the converters cnas receive sets of control words memorized in the memory imem , and supply analog control signals to the generator pgn 2 . at least the transmitter rx 2 comprises reception circuits rec connected to a circuit for analyzing qan the quality of service qos of the signals received , the circuit qan being connected to a memory mem 1 . during a calibration phase , the generator pgn 2 and the memory imem are controlled to generate and transmit a first signal s ( t ) from a first set of control words read in the memory imem , the signal s ( t ) emitted being modulated by a test frame comprising for example the address of the set of control words read in the memory imem . the receiver rx 2 receives a signal s ′( t ) corresponding to the signal s ( t ) emitted . the receiver rx 2 measures the quality of the signal s ′( t ) and memorizes in the memory mem 1 the address of the set of control words transmitted in the signal s ′( t ) in association with the signal quality measured . the transmitter tx 2 of the device dev 2 sends to the device dev 1 an acknowledgement message or waits for a following frame . after the reception of the acknowledgement message by the receiver rx 1 of the device dev 1 , or after the term of a time out of a certain duration corresponding to a processing and response time by the device dev 2 , the transmitter tx 1 accesses a following set of control words in the memory imem and the generator pgn 2 controlled through the new set of control words selected , generates a new signal s ( t ) which is modulated by the test frame including the new read address of the memory imem . the receiver rx 2 of the device dev 2 receives this signal , takes a new measure of the quality of the received signal and memorizes in the memory mem 1 the address transmitted and the quality measure obtained . once all the sets of control words have been read in the memory imem and used to generate a test frame signal , the device dev 1 sends to the device dev 2 a calibration end signal . upon receiving this calibration end signal , the device dev 2 searches in the memory mem 1 , the address corresponding to the best quality measure and sends this address to the device dev 1 in response to the calibration end signal . the device dev 1 may then configure the transmitter tx 1 so that it uses the set of control words located in the memory imem at the address transmitted by the device dev 2 . if the quality of the transmission measured by the device dev 2 becomes insufficient , the device dev 2 may send to the device dev 1 a signal for triggering a new calibration . admittedly , the calibration procedure which has just been described between the transmitter tx 1 and the receiver rx 2 may also be performed between the transmitter tx 2 and the receiver rx 1 . it will be clear to those skilled in the art that the present disclosure is susceptible of various embodiments and applications . in particular , the disclosure is not limited to the use of a controlled oscillator . other known means may be used to generate pulse streams . the disclosure is not limited either to the use of an h bridge to combine the pulse signals and the amplitude setpoint signals of the pulses . the various embodiments described above can be combined to provide further embodiments . these and other changes can be made to the embodiments in light of the above - detailed description . in general , in the following claims , the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims , but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled . accordingly , the claims are not limited by the disclosure . s . bourdel , y . bachelet , j . gaubert , r . vauché , o . fourquin , n . dehaese , and h . barthelemy ; “ a 9 pj / pulse 1 . 42 vpp ook cmos uwb pulse generator for the 3 . 1 - 10 . 6 ghz fcc band ”; microwave theory and techniques , ieee transaction on ; january 2010 wentzloff , d . d . ; chandrakasan , a . p . ; “ a 47 pj / pulse 3 . 1 - to - 5 ghz all - digital uwb transmitter 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