Opinion ID: 613056
Heading Depth: 2
Heading Rank: 2

Heading: Harari v. Mihnea: Written Description

Text: The claims at issue can be divided into two categories: those with an “offset erase verify bias” limitation and those without. In Mihnea, the Board held that if the ’579 application was incorporated by reference, the claims without an “offset erase verify bias” limitation, such as claim 68, were supported by the specification. On appeal, Micron does not dispute that those claims – those not reciting the offset erase verify bias limitation – are supported if the disputed portions of ’579 application were indeed incorporated by reference. With regard to those claims reciting an “offset erase verify bias” limitation, the Board held that they lacked written description support even if all of the ’579 application was incorporated by reference. Harari disputes this determination. Harari’s claim 70 illustrates the offset erase verify bias claims at issue here: 70. The method of claim 68, wherein said erasing step comprises: HARARI v. LEE 14 offsetting an erase verify bias used to deter- mine if the flash memory cells are in first of said at least two data states; applying at least one erase pulse to each flash memory cell; determining whether contents of the cells are erased using the offset erase verify bias; and repeating said applying and determining steps until all of the cells are erased to a state other than one of at least two data states. Mihnea J.A. 757, 909-18 (emphases added). The applying, determining, and repeating steps of claim 70 recite an erase/verify cycle at least similar to that described in the ’579 application. Memory cells are alternately pulsed with an erase voltage and then verified by comparing to a threshold to see if they are in a non-data state, which Harari’s specification calls the “erased” state (which is similar to the “over-erased” condition described in Mihnea). See Lee J.A. 345-46; 695-96; Mihnea patent col.6 l.20 - col.7 l.61. 2 In Mihnea, the Board’s determination turned on whether the second read implementation could be used to verify the cells. The Board’s reasoning echoed its incorporation by reference reasoning: the indirect read – along with its description of adjusting the bias of master reference cells – applied only to the read operation and not the verify operation. Mihnea J.A. 36. Thus, the Board concluded, even assuming the indirect read implementation was incorporated, Harari could not rely on it to support the erase verify bias claims. Mihnea J.A. 36. 2 All citations to a Mihnea patent specification are to U.S. Patent No. 6,426,898. 15 HARARI v. LEE We disagree. As we described above with respect to incorporation by reference, the ’579 application describes using both the indirect and the direct read implementations to perform the verify portion of the erase/verify and write/verify cycles. The application clearly states that local reference cells “are used directly or indirectly to erase verify, program verify or read the sector’s addressed memory cells.” Lee J.A. 342. Furthermore, immediately after describing the indirect read implementation, the ’579 application explains that “the read circuits and operation described are also employed in the programming and erasing of the memory cells, particularly in the verifying part of the operation.” Lee J.A. 345. Micron also argues that Harari’s offset erase verify bias claims are not supported even if the indirect read may be used to verify. Specifically, Micron argues that Harari’s applications never discuss adjusting the threshold of a data state (i.e., offsetting an erase verify bias that is used to determine if a cell is in the data state) to erase a memory cell through the data state into a non-data state as the claims require. Micron asserts that Harari merely adjusts thresholds stored in master reference cells to reflect the values stored in local reference cells. According to Micron, this ensures that cells are erased to the desired state despite memory cell degradation over time. Mihnea Appellee’s Br. 44. Harari, pointing to the ’579 application’s discussion of “erase margining schemes,” argues that the application describes bias offsets that are used to erase the cell deep into the erased state. Mihnea Reply Br. 25. Mihnea’s specification explains that during erase verifying, the memory cell’s value is compared to a threshold called an erase verify bias to determine if the cell is in the lowest data state, which it calls the erased state and corresponds to Harari’s ground state. By changing that HARARI v. LEE 16 threshold by some amount, i.e., by offsetting the erase verify bias, the erase/verify cycle will drive the cell’s value down until the cell is in a non-data state that Mihnea calls the over-erased state and Harari calls the erased state. In other words, Mihnea applies erase pulses until the cell is verified to be past a new threshold value equal to the erase verify bias including the offset. Mihnea patent col.8 ll.25-50. In contrast, Harari’s ’579 application describes an indirect read implementation where the memory cell is compared to a threshold stored in a master reference cell that has been biased by a value reflecting another copy of the same threshold stored in a local reference cell. Lee J.A. 343-45 (“[E]very time a sector is read, the master reference cells [holding the thresholds] are re-biased relative to the local reference cells, and used for reading the memory cells in the sector.”). Thus, “local reference cells (which track threshold deviations of the addressed cells) are used to effectively readjust the breakpoint thresholds of the master reference cells.” Lee J.A. 343-44. Because the local reference cells are subject to the same conditions and number of cycles as their associated memory cells, this automatically compensates for changes in cell performance over time or due to local conditions. Lee J.A. 343-44. The ’579 application also discusses margining, a procedure that can be used to help compensate for charge retention problems in memory cells. Over time, the stored charge in a memory cell’s floating gate may diminish through leakage, which could cause the cell’s voltage to drop below a threshold into the next lower state. To compensate, the ’579 application discusses putting the memory cell further into the desired state by erasing and programming memory cells past the desired state’s threshold by a safety margin. Lee J.A. 335, 351-52. For 17 HARARI v. LEE example, when performing the verification in the erase/verify cycle, a variable voltage is adjusted downward by an amount corresponding to the safety margin, causing the cell to be pulsed further into the desired state. Lee J.A. 352. Thus, the dispute is whether the ’579 application’s description of margining and biasing a master reference cell relative to a local reference cell provides written description support for the offset erase verify bias claims. We decline to resolve this technical, fact-intensive question in the first instance, and instead vacate and remand to the Board for further proceedings consistent with this opinion.