Opinion ID: 6215967
Heading Depth: 4
Heading Rank: 2

Heading: JMOL on Infringement

Text: Broadcom and Apple argue that the evidence before the jury on infringement permitted only one verdict, namely no infringement, and that the district court erred in denying JMOL. Broadcom and Apple put forth two rationales for noninfringement of the “irregular repeat” requirement, Appellant’s Br. 27–31. First, looking at each gate alone and commenting on the “repeat” requirement, they argue that the AND gate does not “repeat” the inputted information bit “because the AND gate’s output depends on not only the information bit but also the parity-check-matrix bit.” Appellant’s Br. 29. Second, focusing on the “irregular” half of “irregular repeat,” they argue that “even if the outputted bits could be deemed ‘repeats’ of the information bits,” “any repetition is not ‘irregular’ because each information bit leads to the same number of outputted bits.” Appellant’s Br. 30. Caltech argues in response that the jury was provided with substantial evidence to support the verdict of infringement and that the district court correctly denied JMOL. Caltech asserts that the fact that an AND gate doesn’t have an information-bit/output match for every information bit hardly means that it isn’t repeating any information bit. Appellee’s Br. 21–22 (citing J. App’x 3036–38). All that matters, according to Caltech, is that sometimes there is such a match that qualifies as a “repeat,” so long as each and every bit is repeated at least once. Caltech argues that Broadcom ignores ample expert testimony, which the jury could credit, that sometimes an AND gate repeats an information bit and that, taking the 972 AND gates together, the carefully designed parity-bit table/matrix meant that “the products output and store information bits between two and twelve times.” Appellee’s Br. 22. Caltech asserts Case: 20-2222 Document: 63 Page: 16 Filed: 02/04/2022 16 THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED that, considering the system as a whole, each information bit is in fact repeated, and they are not all repeated the same number of times. We agree with Caltech. Caltech’s expert, Dr. Matthew Shoemake began his testimony with reference to the exemplary table reproduced above. See J. App’x 3036–38. He explained that in the parity-check-bit-equals-1 situation (second and fourth rows of the table), the output bit is a “repeat” of the informationbit input. Where the parity-check bit is 1, the gate affirmatively enables the information bit to be duplicated as the output bit. That is a “repeat.” That is so, he explained, because the information bit in that situation “flows through” to appear again in the output. He also addressed the one other situation where the output bit is identical to the information bit, namely, in the first row of the above table, where both the information bit and the parity-check bit are 0, and so is the output. Despite the identity of the information bit and the output bit, he explained, that situation does not involve a “repeat.” A 0 parity-check bit turns every information bit (0 or 1) into a 0 output, so the output bit in that situation tells one nothing about the information bit. Since the whole point of this encoding scheme is to use outputs that give information about the information bits, a 0 parity-check bit does not produce a “repeat” even when the information-bit input and the output are the same. Broadcom’s expert, Dr. Wayne Stark, expressly recognized that this was exactly what Dr. Shoemake said in his testimony. J. App’x 3956 (“He said it’s a repeat only if the enable [parity-check] signal is a one and it’s not a repeat if an enable [parity-check] symbol is a zero.”). Dr. Shoemake also explained to the jury that “flow through” means that the information bit is repeated at the output gate. See, e.g., J. App’x 2810, 2812, 3017–19. When the information bit “flows through” to the output gate because the parity-check bit is 1, that’s a repeat, both according to the expert’s usage and a plain understanding of the Case: 20-2222 Document: 63 Page: 17 Filed: 02/04/2022 THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED 17 word “repeat.” See, e.g., J. App’x 3038. When the information bit is not allowed to flow through (because the parity-check bit is 0), that’s not a repeat (even though both the information bit and the output bit are 0). 4 In explaining the operation of the RU encoder itself, Dr. Shoemake testified that it contains “972 mac_reg modules [AND gates], and the information bits are connected to every single one of them.” J. App’x 2831. He further testified that: “[D]epending on which information bit it is, 3 to 12 of these gates are enabled which then allows 3 to 12 … [information bits] to flow through 3 to 12 times and since that number varies, there’s irregular repetition,” J. App’x 3034-35; “[W]hat really happens in the accused products, the tables tell you how many times should information bit number one be repeated. And the tables I've mentioned several times that they allow information bits, and I should force information bits to be repeated between 3 and 12 times,” J. App’x 3080; and “[T]he information bit starts off in one location in the chip, and then it’s connected to 972 distinct locations so it can be irregularly repeated in this architecture.” J. App’x 3018. Dr. Shoemake’s position was consistent throughout his testimony: the physical connection of the first inputs of all 972 AND gates for simultaneous receipt of the information bit stream and the connection of the parity-bit system to the other inputs of the AND gates to selectively enable 3 to 12 of those gates at any time together implement irregular 4 Caltech’s Red Brief incorrectly cited this example as representing a repeat. Red. Br. 21. This was evidently error, given that it directly contracted the directly cited pages of Dr. Shoemake’s testimony. This error does not, however, change the fact that Caltech correctly identified the substantial trial testimony on which the jury could base its decision. Case: 20-2222 Document: 63 Page: 18 Filed: 02/04/2022 18 THE CALIFORNIA INSTITUTE v. BROADCOM LIMITED repetition. Dr. Shoemake explained that this is exactly what one sees when one looks at the “overall architecture” (“whole architecture”), not each gate alone. J. App’x 3031, 3035, 3038. As he specifically testified: Q: Your position, your opinion . . . is that that branch wire creates 972 repeat bits within the meaning of the claims in the Caltech patents; cor- rect? A: So based on my analysis, this wire going to the Mac rag modules and the AND gates under control of the tables that are stored in the RU encoder actually allows the infor- mation bits to flow through [a] different number of times. It’s always 3 to 12 times for a particular information bit. And so [i]n my analysis, this is exactly how the RU en- coder is implementing irregular repetition of information bits. J. App’x 3019 (emphasis added). For the foregoing reasons, substantial evidence supports the jury’s verdict of infringement of the ’710 and ’032 patents. We are not persuaded that the record before the jury permits only a verdict of no infringement. We therefore affirm the district court’s denial of JMOL.