Opinion ID: 806686
Heading Depth: 3
Heading Rank: 2

Heading: Memory Controller

Text: Rambus also disagrees with the examiner’s construction of the term “memory device” as encompassing devices that perform a control function. As an initial matter, the PTO contends that Rambus waived this argument because Rambus did not raise the issue in its appeal to the Board. See In re Watts, 354 F.3d 1362, 1367-68 (Fed. Cir. 2004). We disagree. Rambus did in fact raise this argument in its appeal brief before the Board, maintaining that the memory device in claim 18 of IN RE RAMBUS 13 the ’918 Patent consists of a single memory chip and arguing that the examiner’s construction was even broader than the district court’s construction, which concluded that the memory device “does not include a microprocessor like a CPU or memory controller.” Patent Owner’s Appeal Br. at 15 Ex parte Rambus, Inc., Reexamination No. 90/010,420 (May 4, 2010). On the merits, Rambus argues that the term memory device cannot include a memory controller and cites Lisle to argue that the speed and efficiency goals of the invention described by the specification require that the memory devices be kept as simple as possible, thus excluding a memory controller. 298 F.3d at 1314. Rambus also points to portions of the specification indicating that control functions are carried out by master devices, not slave devices like the memory device. See ’918 Patent col. 7 ll. 32-65 (fault tolerance), col. 16 ll. 54-56 (error checking), col. 14 ll. 38-44 (queuing requests), col. 14 ll. 59-67 (device configuration). According to Rambus, these time consuming control operations are carried out by the master devices and do not slow the transfer of data from the slave memory devices, which simply respond to signals. Rambus also argues that the term “memory device” cannot be construed to include a controller because Rambus’s “argument for allowance [over Jackson] hinged on the BIU— a memory controller—not being part of the claimed memory device.” Appellant’s Br. 45 (emphasis in original). The PTO disagrees with Rambus’s master-slave analogy and instead argues that the specification makes clear that the ’918 Patent’s memory device includes functions like those performed by the iAPX manual’s MCU. The PTO also agrees with the district court’s conclusion that the memory device can, and indeed must, provide at least the control functionality necessary to enable the memory chip or chips to interface with the rest of the system, similar to how the MCU controls the array in the iAPX 14 IN RE RAMBUS Manual. The PTO argues this is true even if the argument to overcome Jackson resulted in a disclaimer of a CPU or global bus controller. We agree with the PTO. Rambus’s construction broadly excluding any memory controller that provides more functionality than simple control logic fails. First, claim 18 itself does not limit any “control” function that the memory device might carry out. In fact, the claim expressly calls for the memory device to provide the control functionality of receiving block size requests and outputting specific amounts of data. Nothing in the claim prevents the memory device from consisting of a storage chip and a device that facilitates the receiving and outputting from that storage chip. And at oral argument Rambus conceded that the memory device must at minimum have such control logic. See Oral Arg. at 12:2012:33, available at http://www.cafc.uscourts.gov/oral-argu ment-recordings/2011-1247/all. Rambus only attempted to exclude more complex controllers from the memory device. Oral Arg. at 15:35-15:50. But excluding more complex controllers does not eliminate all control functionality. Nor does Lisle compel a different result. In Lisle, “an object of the patented invention [was] to provide a single tool that [could] be used on many different tie rod configurations.” 398 F.3d at 1314. That goal informed the construction of a claim limitation because a contrary construction would have rendered the invention mechanically incapable of meeting that goal. Id. Here, the general speed and efficiency goals Rambus relies on do not require a construction of “memory device” that excludes all control functionality. Pursuant to claim 18, the memory device needs only to receive and output specific data, functions it can perform even while exhibiting other minor functionality, without wholly defeating the invention’s speed and efficiency goals. And while Rambus did IN RE RAMBUS 15 exclude the functions of Jackson’s BIU during prosecution, this restriction only prevents the memory device from containing a global bus controller or CPU, not from containing a component that interfaces with the computer system, even when that component provides some additional functionality. Finally, Rambus admits that a key part of the ’918 Patent’s invention was a device with “‘all the functionality’ of prior art memory boards.” Appellant’s Br. 39. Thus, a memory device is not just a functionless storage chip. The memory device must have some functionality— specifically the data receiving and outputting functions described in claim 18. Thus, consistent with the specification, prosecution history, and the Micron district court’s construction, we construe a “memory device” as a component of a memory subsystem, not limited to a single chip, where the device may have a controller that, at least, provides the logic necessary to receive and output specific data, but does not perform the control function of a CPU or bus controller. B. Anticipation The parties entire anticipation dispute turns on whether the memory device in claim 18 of the ’918 Patent reads on the memory module in the iAPX Manual. We conclude that substantial evidence supports the Board’s decision that it does. The Board accepted Rambus’s characterization of the iAPX Manual’s module as “contain[ing] at least 12 TTL packaged chips, a memory controller chip, and several DRAM chips” without further comment on the examiner’s control function analysis. Board Op. at 12. Correctly construed, the “memory device” described in claim 18 of the ’918 Patent can contain more than one chip and may contain a controller that provides the logic necessary for 16 IN RE RAMBUS the memory device to receive and output specific data, but that controller does not function like a CPU. Rambus agreed at oral argument that the MCU in the memory module of the iAPX Manual provided the necessary logic, but tried to distinguish the MCU because it “does more than that.” Oral Arg. at 15:22-15:35. But as the examiner recognized, it is the bus controller (i.e., the “BIU”) of the iAPX that is akin to the BIU that Rambus distin- guished during prosecution, not the local “MCU” that is within iAPX’s “memory module.” There is no suggestion that the BIU of the iAPX is within the memory module, rather it is clearly outside of the memory module, thus satisfying the requirement that the memory module receive a request from a bus controller. By not restricting a memory device to a single chip or otherwise restricting the necessary interface control logic function within the claims, there is simply no principled way to distinguish the iAPX Manual’s memory module, which contains several chips and a controller that provides the logic for those chips to function, from the ’918 Patent’s memory device. Thus, substantial evidence supports the Board’s conclusion that the iAPX memory module reads directly on the ’918 Patent’s memory device.